Multilayer wiring board

Abstract

To provide a multilayer wiring board having high insulation reliability and a method for manufacturing the same.SOLUTION: A multilayer wiring board includes insulating resin layers 001, 001' and at least one layer or more of a conductor wiring layer 006. A barrier metal film 003 is formed on a bottom surface and both side surfaces of the conductor wiring layer 006.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a multilayer wiring board having high insulation reliability, such as a fine wiring board.

Background Art

[0002] In recent years, with the miniaturization and high functionality of electronic devices, there has been a demand for coping with fine pitch of wiring in multilayer wiring boards. As the wiring pitch becomes finer, insulation degradation due to migration between wirings becomes a problem. Therefore, when forming a wiring by a damascene method as in Patent Document 1, a barrier metal may be formed. However, migration may easily occur at the resin interface between the wiring (conductor wiring layer) and the insulating resin layers formed above and below it, even if the insulating resistance of the insulating resin is high. In that case, in the method of Patent Document 1, since a barrier metal is not formed on the upper part of the conductor such as the wiring where the resin interface exists, migration may progress from the contact portion between the resin interface and the conductor such as the wiring, resulting in a short circuit failure.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a multilayer wiring board having high insulation reliability and a method for manufacturing the same.

Means for Solving the Problems

[0005] To solve the problems, an aspect of the present invention is a multilayer wiring board in which at least one insulating resin layer and one conductor wiring layer are formed, wherein a barrier metal film is formed on the lower surface and the side surface of the conductor wiring layer. Here, "bottom surface" refers to the surface facing one direction in the thickness direction. For example, the bottom surface refers to the surface facing the substrate side (the bottom surface in the stacking direction). Furthermore, a method for manufacturing a multilayer wiring substrate according to an aspect of the present invention includes the steps of: forming a resist for wiring formation using plated copper on an insulating resin layer; forming a barrier metal film and a plated seed layer on the resist and insulating resin in that order; forming copper by plating up to above the upper end surface position in the thickness direction of the resist; removing the copper, seed layer and barrier metal film above the resist so that the upper end surface of the resist is exposed to form a conductor wiring layer; and removing the resist. [Effects of the Invention]

[0006] According to an aspect of the present invention, since a barrier metal film is interposed at the resin interface between the lower surface of the wiring and both sides in the width direction, it becomes possible to provide a multilayer wiring board with high insulation reliability. [Brief explanation of the drawing]

[0007] [Figure 1] This is an explanatory diagram showing a multilayer wiring board and a manufacturing method according to the first embodiment of the present invention. [Figure 2] This is an explanatory diagram showing a multilayer wiring board and a manufacturing method according to a second embodiment of the present invention. [Figure 3] This is an enlarged cross-sectional view showing a part of a multilayer wiring board in an embodiment of the present invention. [Figure 4] This is an enlarged cross-sectional view showing a part of a multilayer wiring board in a second embodiment of the present invention. [Figure 5] This is an enlarged cross-sectional view showing a modified example of a multilayer wiring board according to an embodiment of the present invention. [Figure 6] This is a magnified cross-sectional view showing a portion of a multilayer wiring board in a conventional damascene pattern. [Figure 7] This is a magnified cross-sectional view showing a portion of a multilayer wiring board in a conventional semi-additive wiring method. [Modes for carrying out the invention]

[0008] Next, embodiments based on the present invention will be described with reference to the drawings. Here, the dimensional ratios in the drawings may differ from the actual ratios for explanatory purposes, and some components may be omitted from the drawings. (composition) As shown in Figures 1(h), 2(i), 3, and 4, the multilayer wiring board of this embodiment is a multilayer wiring board in which at least one insulating resin layer and one conductive wiring layer are formed. In the example of the multilayer wiring board shown in Figures 1(h), 2(i), 3, and 4, a conductive wiring layer 006 is formed on the insulating resin layer 001, and furthermore, an insulating resin layer 001' is formed on the insulating resin layer 001 so as to cover the conductive wiring layer 006.

[0009] The conductor wiring layer 006 has barrier metal films 003 formed on its bottom surface and both sides. The wiring width of the conductor wiring layer 006 may be configured such that the width of the top surface is wider than the width of the bottom surface, as shown in Figure 4. This is preferable. For example, a configuration in which the wiring width increases as you move upward in the stacking direction is preferred. The barrier metal film 003 is composed of, for example, a metal with a lower inoization tendency than copper, or titanium. The thickness of the barrier metal film 003 is, for example, 20 nm to 200 nm. The material constituting the conductor wiring layer 006 is, for example, copper. As described above, in this embodiment, since a barrier metal film 003 is interposed at the interface between the insulating resin layers 001, 001' on the lower surface and both sides in the width direction of the wiring, it is possible to provide a multilayer wiring board with high insulation reliability.

[0010] (Manufacturing method) The manufacturing method of the multilayer wiring board of this embodiment includes, for example, the following steps a to e. a: A process of forming a resist for wiring formation using plated copper on an insulating resin layer. b: A process of forming a barrier metal film and a plating seed layer on a resist and an insulating resin in this order. Step c: forming copper above the upper end surface position in the thickness direction of the resist by plating Step d: forming a conductor wiring layer by removing the copper, seed layer, and barrier metal film located above the resist so that the upper end surface in the thickness direction of the resist is exposed Step e: removing the resist Here, the removal of the copper, seed layer, and barrier metal film located above the upper end surface in the thickness direction of the resist is performed, for example, by wet etching, dry etching, CMP, or a combination thereof.

[0011] Hereinafter, an example of the method for manufacturing a multilayer wiring board in the present embodiment will be specifically described with reference to the drawings. <First Embodiment> The method for manufacturing a multilayer wiring board according to the first embodiment will be described with reference to FIG. 1. First, a resist 002 is applied onto an insulating resin layer 001 and exposed and developed to form a resist pattern corresponding to a conductor pattern in the resist 002 (see FIG. 1(b)). Here, when forming an opening corresponding to the conductor pattern in the resist 002, exposure and development may be performed so that the opening has a tapered shape (see FIG. 4). In this case, formation of the barrier metal film 003 and plating seed layer 004 described later on the side surface of the opening becomes easy.

[0012] Next, a barrier metal film 003 is formed by sputtering on the resist 002 and the surface of its opening (see FIG. 1(c)). If the barrier metal film is too thin, the barrier effect becomes low, and if it is too thick, the wiring becomes thin and removal becomes difficult. Therefore, the film thickness is preferably 20 nm or more and 200 nm or less. The barrier metal film 003 is preferably a metal with a smaller ionization tendency than copper. Also, a metal such as titanium that is passivated and stabilized by oxidation or the like is also preferable.

[0013] Next, an electrolytic plating seed layer 004 is formed on the barrier metal film 003 by sputtering or electroless plating (see FIG. 1(d)). Next, a conductive layer 005 consisting of an electroplated layer is formed on the seed layer 004 by electroplating (see Figure 1(e)). For electroplated copper plating, for example, filled plating can be used to fill the openings in the resist 002 with a conductor, thereby obtaining a plated conductive layer 005 with a flat surface. The term "conductor pattern" includes not only conductor wiring and terminal lands, but also dummy patterns that do not actually function as an electrical circuit but are placed for purposes such as preventing warping, heat storage, and electromagnetic shielding.

[0014] Next, the conductor layer 005, seed layer 004, and barrier metal film 003 are removed flat by CMP or the like until the resist 002 is exposed (see Figure 1(f)). Next, the resist 002 is removed (see Figure 1(g)). This forms the conductor wiring layer 006. The conductor wiring layer 006 has a barrier metal film 003 formed (coated) on its bottom and sides. Next, an insulating resin layer 001' is formed on the conductor wiring layer 006 and the insulating resin layer 001. A multilayer wiring substrate can be formed by repeating the same procedure as described above, from the formation of the resist 002 to the formation of the insulating resin layer 001'.

[0015] <Second Embodiment> Next, the manufacturing method of the multilayer wiring board according to the second embodiment will be described with reference to Figure 2. The steps up to the formation of the conductive layer 005 (Figures 2(a) to (e)) are the same as in the first embodiment, so their explanation is omitted. In the second embodiment, after the formation of the conductor layer 005, the electroplating layer 005 and the seed layer 004 are removed by wet etching until the barrier metal film 003 above the wiring is exposed (see Figures 2(f) and 2(g)). At this time, the barrier metal film 003 on the side of the wiring becomes slightly lower than the top of the wiring due to etching. The difference is that the electroplating layer 005, the seed layer 004, and the barrier metal film 003 are removed by wet etching or dry etching. The steps after the removal of resist 002 (Figures 2(h) and (i) are the same as in the first embodiment, so their explanation is omitted.) Thus, in the wiring layers 006 formed in the first and second embodiments, as shown in Figures 3 to 5, the distance between the upper and lower resin interfaces and the copper not covered by the barrier metal film 003 is large, which suppresses the occurrence of migration at the resin interface. However, when a barrier metal film is formed using conventional damascene methods (Figure 6) or semi-additive methods (Figure 7), the distance between the resin interface and the copper where the barrier metal film is not formed is short, making migration at the resin interface more likely to occur. [Examples]

[0016] <Example 1> Example 1 describes an example of fabricating a multilayer wiring board according to the first embodiment. First, an insulating resin layer 001 with a thickness of approximately 7 μm was formed on a thermal oxide silicon wafer by spin coating with an insulating resin. A photoresist 002 with a thickness of approximately 3 μm was then spin coated onto the insulating resin layer 001, and a resist pattern for wiring was formed by exposure and development. Next, titanium was formed on the insulating resin layer 001 and the resist 002 to a thickness of approximately 100 nm by sputtering, and then copper was formed on top of that to a thickness of 200 nm by sputtering. Next, copper was formed on the resist by electroplating until it reached a thickness of approximately 3 μm. Next, the upper surface of the resist 002 was exposed by polishing to a thickness of approximately 5 μm using CMP, and then the resist 002 was peeled off to form the conductor wiring layer 006. Next, an insulating resin layer 001' was formed by spin-coating the insulating resin layer 001 and the conductor wiring layer 006 so that the thickness on the wiring was approximately 5 μm. [Explanation of Symbols]

[0017] 001, 001'... Insulating resin layer 002...Resist 003... Barrier metal film 004... Seed layer 005...Conducting layer (electrolytic plating layer) 006...Conductor wiring layer 007...Wiring section 008...Beer Club 009...Pad section 010... Beer opening

Claims

1. A multilayer wiring board having at least one insulating resin layer and one conductive wiring layer formed thereon, The above-mentioned conductor wiring layer has a barrier metal film formed on its bottom surface and both sides. The above-mentioned conductor wiring layer has a seed layer formed inside the barrier metal film, in contact with the barrier metal film. The above seed layer is made of copper. The wiring width of the above-mentioned conductor wiring layer is such that the width of the top surface is wider than the width of the bottom surface. The thickness of the above barrier metal film is 200 nm or less. A multilayer wiring substrate characterized in that the upper end of the barrier metal film formed on the side surface of the wiring consisting of the conductor wiring layer is located below the upper surface of the conductor wiring layer.

2. The multilayer wiring substrate according to claim 1, characterized in that the barrier metal film is made of a metal having a lower ionization tendency than copper.

3. The multilayer wiring substrate according to claim 1, characterized in that the barrier metal film is made of a metal having a lower ionization tendency than copper (excluding platinum, palladium, and gold).

4. The multilayer wiring substrate according to claim 1, characterized in that the barrier metal film is made of titanium.

5. The multilayer wiring substrate according to any one of claims 1 to 4, characterized in that the conductor wiring layer comprises a conductor layer, a seed layer, and a barrier metal film in this order.

6. The multilayer wiring substrate according to any one of claims 1 to 5, characterized in that the conductor wiring layer does not have a barrier metal film formed on its upper surface.

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