Task scheduler device, computing system, task scheduling method and program

Abstract

This task scheduler device (100, 100A) comprises: a dedicated command execution detecting unit (110) that detects the execution of a dedicated command; a dedicated command execution affected core identifying unit (120) that identifies a logical core that originates from the execution of the dedicated command, operates in a physical core that is the same as the dedicated command execution affected core, and has a reduced operating frequency; a low frequency permitted process allocation determining unit (140) that makes a determination for identifying a process that satisfies a predetermined performance requirement even when operating at a low frequency, with respect to the logical core that has the reduced operating frequency identified by the dedicated command execution affected core identifying unit (120); and a process core allocating unit (150) that allocates the process identified by the low frequency permitted process allocation determining unit (140) to the logical core that has the reduced operating frequency.

Description

Technical Field

[0001] The present invention relates to a task scheduler device, a computing system, a task scheduling method, and a program.

Background Art

[0002] In applications that perform signal / media processing on a CPU (for example, vRAN (virtual Radio Access Network) L1 signal processing and Deep-Learning), in order to perform high-throughput arithmetic processing, the SIMD (Single Instruction Multiple Data) extended instruction set of the CPU (for example, Intel SSE / AVX512) is frequently used. In recent years, SIMD extended instruction sets consume a large amount of power and generate a large amount of heat, and the frequency of the core that executes SIMD instructions temporarily decreases (see Non-Patent Document 1).

[0003] The following describes the peripheral technology trends in SIMD operations / (in the following description, " / " represents "or") instructions. At the academic level, there are the following. Since 2019, scheduling technologies that take into account the decrease in frequency during execution have been proposed at the academic level. The technology described in Non-Patent Document 2 identifies processes affected by the frequency decrease due to SIMD operations and ensures fairness by compensation through scheduling over a long period of time ("fairness ensuring"). The technology described in Non-Patent Document 3 eliminates interference by scheduling to specialize the core that executes SIMD instructions ("elimination of interference").

[0004] Also, in actual use cases in the market, there are the following. Normally, the utilization of the SIMD unit is limited and only part of the processing is offloaded, so it has not been a major problem. For example, in the encryption processing of SSL (Secure Sockets Layer), there are reports of a certain degree of performance degradation.

[0005] On the other hand, vRAN (vDU) fully utilizes SIMD computations, which makes it highly likely to present challenges when trying to improve core efficiency. Here, the above vRAN (vDU) refers to the DU in a vRAN where the base station function is separated into RU (Radio Unit) / DU (Distributed Unit) / CU (Centralized Unit) in a general-purpose server that performs radio signal processing at the base station (BBU: Broad Band Unit).

[0006] Additionally, there is the FlexRAN software reference platform developed by Intel®. FlexRAN is the main building block of the Layer 1 (L1) functionality of RAN for building software-based wireless base stations. Currently, FlexRAN operates all cores at low frequencies and comes pre-configured with CPUs that can meet performance requirements even at low frequencies. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] Intel-avx-512-instruction-set, [online], [Retrieved September 6, 2022], Internet <URL: https: / / builders.intel.com / docs / networkbuilders / intel-avx-512-instruction-set-for-packet-processing-technology-guide-1617440657.pdf (p15)> [Non-Patent Document 2] Fair Scheduling for AVX2 and AVX-512 Workloads, Mathias Gottschlag, usenix ATC 2021, [online], [Accessed September 6, 2022], Internet <URL: https: / / www.usenix.org / conference / atc21 / presentation / gottschlag> [Non-Patent Document 3] Automatic Core Specialization for AVX-512 Applications, Mathias Gottschlag SYSTOR '20: Proceedings of the 13th ACM International Systems and Storage Conference,[online],[Retrieved September 6, 2022],Internet <URL :https: / / dl.acm.org / doi / 10.1145 / 3383669.<3398282> Summary of the Invention Problems to be Solved by the Invention

[0008] In a computer system, a CPU on a computer (hereinafter referred to as a server) supports general-purpose instructions and dedicated instructions specialized for specific operations (SIMD operation instructions and dedicated instructions for encryption). Dedicated instructions for encryption are shown, for example, at "https: / / www.isus.jp / hpc / intel-advanced-encryption-standard-instructions-aes-ni / ". In this configuration, an event occurs in which the frequency of the CPU physical core fluctuates when a dedicated instruction is executed.

[0009] [Core Operating Frequency Reduction Event due to SIMD Operation] Referring to FIGS. 14 and 15, a core operating frequency reduction event due to SIMD operation will be described. FIG. 14 is a diagram showing the configuration of a CPU including a SIMD unit that executes SIMD instructions. As shown in FIG. 14, the CPU 10 includes four physical cores (CPU cores) 11 and SIMD units 12 installed in each of the four physical cores 11 to execute SIMD instructions. In this specification, the physical core 11 is a single CPU core that executes two or more processes simultaneously. As shown in the enlarged view of Figure 14, each physical core 11 has logical cores 1 and 2, each executing two threads. The four physical cores 11 shown in Figure 14 have eight logical cores, since each core executes two threads. In other words, the number of logical cores is the number of physical cores 11 multiplied by the number of threads that can be executed on each core using hardware multithreading technology (e.g., Intel Hyper-Threading). This hyperthreading allows a single physical core 11 to operate like two logical cores.

[0010] Figure 15 shows the execution instructions and operating frequency of the logic core shown in Figure 14. The upper part of Figure 15 shows the execution instructions of the logic core shown in Figure 14, and the lower part of Figure 15 shows the core operating frequency when the logic core execution instructions are executed. As shown in the upper diagram of Figure 15, the logic core 1 instruction executes a normal instruction, a SIMD instruction, and another normal instruction. The logic core 2 instruction executes a normal instruction while the logic core 1 instruction is executing the SIMD instruction (indicated by symbol a in the upper diagram of Figure 15).

[0011] When using hyperthreading, which makes one physical core appear as two, the operating frequencies of the SIMD extended instruction execution core (here, logical core 1) and the logical core operating on the same physical core (here, logical core 2) decrease (indicated by b in the lower part of Figure 15). For example, as shown in the lower part of Figure 15, the core operating frequency decreases from high (approximately 3.5 GHz) to low (approximately 1.9 GHz). Furthermore, after SIMD execution, the core operating frequency continues to decrease for a certain period of time (e.g., 2 ms) before it returns to its original level (indicated by c in the upper part of Figure 15) (<Frequency decrease of logical core 2>).

[0012] The operating frequency of the logical core (here, logical core 2) that operates on the same physical core as the SIMD extended instruction execution core mentioned above decreases, and this decrease in the operating frequency of logical core 2 continues for a certain period of time, resulting in a "period of reduced operating frequency" (indicated by d in the lower part of Figure 15). As a result, the number of instructions executed per unit of time decreases, leading to performance fluctuations and a decrease in responsiveness (<overall core performance degradation>).

[0013] Thus, when using hyperthreading, executing SIMD instructions (dedicated instructions) increases the power consumption of the core, which can reduce the operating frequency of logical cores running on the same physical core. In this case, the processing performance of the core executing the dedicated instructions and the processes scheduled on the same physical core will decrease.

[0014] Refer to Figures 16-18 for a more detailed explanation of the challenges of existing technologies. <Existing Technology 1: Ensuring Equality> There is a technology (existing technology 1) that ensures fairness by allocating a fixed amount of CPU time to each process. Existing technology 1 is implemented, for example, in Linux CFS (Completely Fair Scheduler).

[0015] Figures 16 and 17 illustrate existing technology 1. Figure 16 shows the core allocation status when a CPU has multiple physical cores, and each of these physical cores operates like two logical cores. Figure 17 shows the cumulative allocated CPU time of the process group allocated according to the core allocation status of each physical core in Figure 16.

[0016] As shown in Figure 16, the CPU 10 has two physical cores (physical core 1, physical core 2) 11. Hyperthreading allows a single physical core (physical core 1, physical core 2) 11 to function as if it were two logical cores (logical core 1, logical core 2). In Figure 16, the coarsely shaded physical core (physical core 1) 11 has a logical core 1 that executes dedicated instruction-intensive (SIMD) processes, and a logical core 2 that executes a group of normal instructions called process 1. Similarly, in Figure 16, the finely shaded physical core (physical core 2) 11 has a logical core 1 that executes a group of normal instructions called process 2, and a logical core 2 that executes a group of normal instructions called process 3.

[0017] When CPU time is allocated to the physical cores (Physical Core 1, Physical Core 2) 11, the variation in the operating frequency is not considered. In the example of FIG. 16, Physical Core 1 has a low operating frequency and Physical Core 2 has a high operating frequency.

[0018] In the prior art 1, by allocating a certain amount of CPU time to each process, equality is ensured. However, since the variation in the operating frequency is not considered, it does not meet the requirement "Requirement 1: Each process is allocated the CPU processing time required by each process".

[0019] That is, as shown in FIG. 17, since the priority levels of Process Group 1 and Process Group 2 are both "Medium", the same length of CPU time is allocated. However, Process Group 1 and Process Group 2 have different frequencies. Since the same length of CPU time is allocated to Process Group 1 and Process Group 2, depending on the performance characteristics of each process with respect to the frequency, the processing performance may not be satisfied. In the prior art 1, there is a problem that the minimization of the number of execution cores cannot be achieved by process allocation considering the variation in the operating frequency.

[0020] <Prior Art 2: Static Core Allocation> FIG. 18 is a diagram for explaining the prior art 2. FIG. 18 shows the core allocation situation when the CPU has a plurality of physical cores and each of these plurality of physical cores operates as two logical cores.

[0021] As shown in FIG. 18, the CPU 10 has three physical cores (physical core 1, physical core 2, physical core 3) 11. Through hyperthreading, a single physical core (physical core 1, physical core 2, physical core 3) 11 operates like two logical cores (logical core 1, logical core 2). Among these, the physical core (physical core 1) 11 is for dedicated instruction allocation. As described above, dedicated instructions are SIMD operation instructions and dedicated instructions for encryption. The logical core 1 of the physical core 1 for dedicated instruction allocation is a core that executes a dedicated instruction process (SIMD). The logical core 2 of the physical core 1 for dedicated instruction allocation is a core that executes dedicated instructions, but is not allocated here. That is, only processes that execute dedicated instructions are allocated to the logical core 1 and logical core 2 of the physical core 1 for dedicated instruction allocation. Also, the logical core 1 of the physical core 2 is a core that executes a group of process 1 which are normal instructions, and the logical core 2 is a core that executes a group of process 2 which are normal instructions. Similarly, the logical core 1 of the physical core 3 is a core that executes a group of process 3 which are normal instructions, and no process group is allocated to the logical core 2.

[0022] In the prior art 2, the process that executes dedicated instructions and the cores of other processes are separated and specialized. In the example of FIG. 18, in the physical core 1 for dedicated instruction allocation, an unused logical core 2 is generated (reference sign e in FIG. 18), and the efficiency of the number of execution cores deteriorates. The generation of the unused logical core 2 leads to an increase in the number of operating cores, so there is a problem that it does not meet "requirement 2: minimization of the number of execution cores".

[0023] In view of such a background, the present invention has been made, and the present invention aims to improve core utilization rate and reduce the number of CPU operating cores.

Means for Solving the Problem

[0024] To solve the aforementioned problems, a task scheduler device is provided for a computing system that executes dedicated instructions specialized for a particular operation, which uses hardware multithreading to make one physical core appear as multiple logical cores, and assigns the execution process of the dedicated instructions to the logical core. The processor comprises, Dedicated instruction detection that detects the execution of the aforementioned dedicated instruction. function Core identification identifies the logical core whose operating frequency decreases due to the execution of the dedicated instruction, and which operates on the same physical core as the core that executes the dedicated instruction. function And, the core identification function For the logic cores whose operating frequency has been identified as having a reduced operating frequency, an acceptable process determination is made to identify a process that can operate at a lower frequency while still meeting predetermined performance requirements. function And the aforementioned acceptable process determination function Process core assignment: Assigning the identified process to the logic core where the operating frequency is reduced. It has functions and A task scheduler device characterized by the following features was provided. [Effects of the Invention]

[0025] According to the present invention, it is possible to improve core utilization and reduce the number of operating CPU cores. [Brief explanation of the drawing]

[0026] [Figure 1] This is a schematic diagram of a computing system equipped with a task scheduler device according to an embodiment of the present invention. [Figure 2] This is an example configuration in which the task scheduler device of the computing system according to the present invention is placed in the user space. [Figure 3] This is an example of a configuration in which a task scheduler device of a computing system according to an embodiment of the present invention is placed in the OS. [Figure 4] This figure shows an example of applying a computing system according to an embodiment of the present invention to a task scheduler device in a server virtualization environment with a general-purpose Linux kernel (registered trademark) and a VM configuration. [Figure 5]This figure shows the structure of the management database of the dedicated command execution detection unit of the task scheduler device of the computing system according to an embodiment of the present invention. [Figure 6] This figure shows the structure of the database of the operational process frequency performance impact determination unit of the task scheduler device of the computing system according to an embodiment of the present invention. [Figure 7] This figure shows the operation pattern of the task scheduler device when moving the core of a running process in a computing system according to an embodiment of the present invention. [Figure 8] This is a flowchart of the operation pattern of the task scheduler device when moving the core of a running process in a computing system according to an embodiment of the present invention. [Figure 9] This figure shows the operation pattern of the task scheduler when scheduling a new startup process for the task scheduler of a computing system according to an embodiment of the present invention. [Figure 10] This is a flowchart of the operation pattern of the task scheduler when scheduling a new startup process for the task scheduler of a computing system according to an embodiment of the present invention. [Figure 11] This figure shows the operation pattern of the task scheduler device for collecting frequency influence information (executed periodically) for each process of the task scheduler device of the computing system according to the present invention. [Figure 12] This is a flowchart of the operation pattern of the task scheduler device for collecting frequency influence information (executed periodically) for each process of the task scheduler device of the computing system according to the present invention. [Figure 13] This is a hardware configuration diagram showing an example of a computer that implements the functions of a task scheduler device in a computing system according to an embodiment of the present invention. [Figure 14] This diagram shows the configuration of a CPU equipped with a SIMD unit that executes SIMD instructions. [Figure 15]Figure 14 shows the execution instructions and operating frequency of the logic core. [Figure 16] This diagram shows the core allocation situation in existing technology 1, where the CPU has multiple physical cores, and each of these physical cores operates like two logical cores. [Figure 17] This figure shows the cumulative allocated CPU time for a group of processes, based on the core allocation status when, in existing technology 1, the CPU has multiple physical cores, and each of these physical cores operates like two logical cores. [Figure 18] This diagram shows the core allocation situation in existing technology 2, where the CPU has multiple physical cores, and each of these physical cores operates like two logical cores. [Modes for carrying out the invention]

[0027] The following describes a task scheduler device and the like in an embodiment of the present invention (hereinafter referred to as "this embodiment") with reference to the drawings. [overview] Figure 1 is a schematic diagram of a computing system equipped with a task scheduler device according to an embodiment of the present invention. This embodiment is an example of application to a CPU as a computing system. It can be similarly applied to other processors such as GPUs (Graphics Processing Units), FPGAs (Field Programmable Gate Arrays), and ASICs (Application Specific Integrated Circuits).

[0028] As shown in Figure 1, the computing system 1000 comprises hardware (HW) consisting of a CPU 10, physical cores (physical core 1, physical core 2, ..., physical core N) 11 (processors) on the CPU 10, an OS 20, a userland 30, and a server consisting of a task scheduler device 100. The computing system 1000 executes specialized instructions that are dedicated to specific operations, including SIMD instructions or dedicated instructions for encryption. The computing system 1000 includes a task scheduler device 100 that assigns the execution process of the specialized instructions to the logical cores using hardware multithreading, which makes one physical core appear as multiple logical cores.

[0029] The prerequisite configuration for the computing system 1000 is summarized below. ·server The server (task scheduler device 100) is equipped with a CPU (processor). The CPU has one or more physical cores. The CPU supports hardware multithreading technology, which allows a single physical core to appear as multiple logical cores.

[0030] ·process There are three types of processes that run on the server (task scheduler device 100): 1. Execution process of dedicated instructions 2. Processes suitable for low-frequency operation. These processes are characterized by high I / O (input / output) volume, long CPU latency, and less stringent real-time requirements. 3. Processes unsuitable for low-frequency operation. These processes are characterized by a large amount of CPU processing and strict real-time requirements.

[0031] • Scheduler There are multiple types of processes running on the server (task scheduler device 100), each with different characteristics such as the proportion of dedicated instructions executed, the amount of input / output processing, and processing priority.

[0032] <cpu10> The CPU 10 comprises physical cores (physical core 1, physical core 2, ..., physical core N) 11. Specifically, the physical cores (physical core 1, physical core 2, ..., physical core N) 11 are CPU cores (CPUcore #0, CPUcore #1, ...) (not shown). The physical cores 11 have logical cores 1 and 2 that execute two threads each, by using hyperthreading which makes one physical core appear as two.

[0033] <os20> OS20 includes a process execution priority management unit 21 and a process I / O amount recording unit 22. The process execution priority management unit 21 obtains a list of processes running on the server and their respective execution priorities. Specifically, the process execution priority management unit 21 obtains the execution priority (for example, the nice value) of each process using the nice command.

[0034] The process I / O volume recording unit 22 obtains a list of processes running on the server (task scheduler device 100) and their respective Input / Output volumes. Specifically, the process I / O volume recording unit 22 obtains the I / O volume of each process (for example, IOStat) using the IOStat command.

[0035] [Task Scheduler Device 100] The task scheduler device 100 includes a dedicated instruction execution detection unit 110 (dedicated instruction detection unit), a dedicated instruction execution influencing core identification unit 120 (core identification unit), an operating process operating frequency performance influence determination unit 130 (performance influence determination unit), a low frequency permissible process assignment determination unit 140 (permissible process determination unit), a process core assignment unit 150, and a new process startup / low frequency operation feasibility determination unit 160.

[0036] [Placement of Task Scheduler Device] Figures 2 and 3 illustrate the arrangement of the task scheduler device 100 shown in Figure 1. • Placing the Task Scheduler device in user space Figure 2 shows an example configuration in which the task scheduler device 100 from Figure 1 is placed in user space. In the computing system 1000 shown in Figure 2, a task scheduler device 100 is located in User space 40. The computing system 1000 executes application (APL) 1 located in User space 40. The computing system 1000 executes APL 1 on a server equipped with an OS.

[0037] The present invention can be applied when there are threads in user space 40, such as in the Intel DPDK (Intel Data Plane Development Kit) (DPDK) (registered trademark).

[0038] · Arrangement of the task scheduler device in the OS FIG. 3 is a configuration example in which the task scheduler device 100 of FIG. 1 is arranged in the OS 20. In the computing system 1000 shown in FIG. 3, the task scheduler device 100 is arranged in the OS 20. The computing system 1000 executes APL1 on a server including the OS 20.

[0039] The present invention can be applied when there are threads inside the kernel, such as in the New API (NAPI) (registered trademark).

[0040] [Variations in the VM configuration of the task scheduler device] As described above with reference to FIG. 2, it can be applied to the configuration example in which the task scheduler device 100 is arranged in user space 40. In this case, the OS is not limited. Also, it is not limited to being in a server virtualization environment.

[0041] [Example of application to the VM configuration] Based on the progress of virtualization technologies such as NFV (Network Functions Virtualization), systems are being constructed and operated for each service. Also, from the form of constructing a system for each service, the service functions are divided into reusable module units and operated on an independent virtual machine (VM: Virtual Machine or container, etc.) environment, so that it can be used as needed like a component to improve the operability. This form called SFC (Service Function Chaining) is becoming the mainstream.

[0042] Figure 4 shows an example of applying the Computing System 1000A to a task scheduler device in a server virtualization environment with a general-purpose Linux kernel (registered trademark) and VM configuration. The same reference numerals are used for components identical to those in Figure 1. The computing system 1000A comprises a CPU 10, physical cores (physical core 1, physical core 2, ..., physical core N) 11 (processors) on the CPU 10, a VM 50, a virtual machine monitor (VMM: Virtual Machine Monitor) 51 on the VM 50, an OS 20, a userland 30, and a task scheduler device 100A. The Virtual Machine Monitor (VMM) 51 virtualizes the computer and allows multiple different operating systems to run in parallel without interfering with each other. The Virtual Machine Monitor (VMM) 51 creates virtual machines (VMs) that behave like physical computers to software, and can run various types of operating systems on them.

[0043] Each of the multiple VMs (VM1, VM2) has a process execution priority management unit 21 and a process I / O amount recording unit 22 in the OS20, and a dedicated instruction execution detection unit 110 and a dedicated instruction execution influencing core identification unit 120 in the userland 30.

[0044] The task scheduler device 100A includes a running process operating frequency performance impact determination unit 130, a low-frequency permissible process assignment determination unit 140, a process core assignment unit 150, and a new process startup / low-frequency operation feasibility determination unit 160. The task scheduler device 100A is not located in the userland 30 of a single OS 20, but is located separately externally and operates as a so-called controller function unit. The task scheduler device 100A performs core allocation based on information about processes spanning multiple VMs in a VM configuration.

[0045] [Configuration of each functional unit of the task scheduler device] <Dedicated command execution detection unit 110> The dedicated instruction execution detection unit 110 detects (determines) whether or not a dedicated instruction has been executed in a currently running process. Specifically, the dedicated instruction execution detection unit 110 receives the identifier (PID: Process IDentifier, etc.) of the process to which the execution of the dedicated instruction should be determined, and outputs whether or not the relevant process has executed the dedicated instruction.

[0046] There are two methods for determining whether a specific instruction has been executed in a currently running process: 1: Static detection method The dedicated instruction execution detection unit 110 determines whether or not a process uses a dedicated instruction based on information such as the process name.

[0047] Figure 5 is a table showing the structure of the management database of the dedicated instruction execution detection unit 110. Figure 5 is an example of the management database of a process that executes a dedicated instruction. As shown in Figure 5, a process name (signal_p, fec_dec, fec_enc, fft_process) is registered for each ID. Each of these process names (signal_p, fec_dec, fec_enc, fft_process) is a process that executes a dedicated command. The dedicated instruction execution detection unit 110 compares a list of processes that use pre-registered dedicated instructions (Figure 5) with the name of the currently running process to determine whether or not a dedicated instruction has been executed.

[0048] 2: Dynamic detection methods The system uses special registers within the CPU (for example, the XCR0 register in x86 processors, which indicates the modified data area for SIMD) to determine whether a specific instruction has been executed. In this case, the OS kernel scheduler checks for changes in the value of this register when the execution of the target process is switched over.

[0049] Information regarding the special registers used by the CPU can be found in "Chapter 13, Managing State Using The Xsave Feature Set" (PDF). Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture. Intel Corporation (2019). Retrieved 23 March 2019.

[0050] <Dedicated instruction execution impact core identification unit 120> The dedicated instruction execution affected core identification unit 120 identifies logical cores that operate on the same physical core as the dedicated instruction execution core and whose operating frequency is reduced as a result of the execution of a dedicated instruction. In this embodiment, the dedicated instruction execution affected core identification unit 120 identifies the core executing the input process ID and the cores affected by it. Specifically, the dedicated instruction execution affected core identification unit 120 receives the number of the process executing the dedicated instruction and outputs the number of the CPU core affected by the dedicated instruction.

[0051] For example, the pidstat command in Linux can be used to identify the core on which a process is running from its Process ID (PID). A reference for the pidstat command is pidstat(1) Linux manual page, [online], [accessed September 6, 2022], Internet <URL: https: / / man7.org / linux / man-pages / man1 / pidstat.1.html>.

[0052] The dedicated instruction execution influencing core identification unit 120 extracts the operating core information number from the command output, identifies the CPU core number operating on the same physical core as the core in question as CPU core information (for example, cpuinfo in Linux), and outputs it.

[0053] <Operating process frequency performance impact determination unit 130> The in-operation process operating frequency performance impact determination unit 130 determines the performance impact of the operating frequency of the in-operation process. In this embodiment, the running process operating frequency performance impact determination unit 130 determines the performance impact of the operating frequency for all processes operating within the server (task scheduler device 100). Specifically, the running process operating frequency performance impact determination unit 130 is activated at regular intervals (for example, 10 seconds) or when a process is started or terminated, and determines the performance impact of the CPU operating frequency on each process.

[0054] There are two methods for determining the impact of the operating frequency performance of a running process: 1: Static methods Static methods determine the influence of operating frequency based on information such as process names.

[0055] Figure 6 is a table showing the structure of the database of the operational process frequency performance impact determination unit 130. Figure 6 is an example of a process database for determining the frequency impact of a process. As shown in Figure 6, the process name (nic_io, calc_crc, packet_process) and the frequency performance impact are registered for each ID. The process names (nic_io, calc_crc, packet_process) are all processes used to determine the frequency impact of a process. The running process operating frequency performance impact determination unit 130 compares the name of the currently running process with a pre-registered list of processes (list of process IDs) running on the server (task scheduler device 100) (Figure 6), and determines the impact on the running process operating frequency performance.

[0056] 2: Dynamic methods The dynamic method determines the impact of frequency changes on each process based on the execution priority (e.g., nice value) of each process in the process execution priority management unit 21 and the I / O amount (e.g., iostat) results in the process I / O amount recording unit 22.

[0057] The running process operating frequency performance impact determination unit 130 obtains the execution priority (nice value) and I / O amount (iostat) of each process from the process execution priority management unit 21 and the process I / O amount recording unit 22, integrates these two values ​​to obtain an impact score, and determines the impact on the operating frequency performance of the running process based on this impact score.

[0058] The following describes specific examples of how to calculate the impact. The operational process frequency performance impact determination unit 130 obtains the priority N (e.g., -20 to 20) of each process from the process execution priority management unit 21, and the I / O amount (X Mbytes / s) from the process I / O amount recording unit 22. The I / O amount is divided by a predetermined value (e.g., "5") to obtain M (0-20) (if 21 or greater, it is set to 20). These two values ​​are then added together (K=NM) to determine the impact level.

[0059] <Low-frequency permissible process assignment determination unit 140> The low-frequency-tolerant process assignment determination unit 140 determines which processes will satisfy predetermined performance requirements even when operating at a low frequency, based on the logic cores whose operating frequency is reduced, as identified by the dedicated instruction execution-affected core identification unit 120. For example, the low-frequency-tolerant process assignment determination unit 140 selects a pair of processes that are less affected by operating at low frequencies and cores that are affected by the dedicated instructions, based on information about the core numbers affected by the dedicated instructions and performance impact information based on the operating frequency of each process.

[0060] Specifically, the low-frequency-tolerant process assignment determination unit 140 selects processes that are allowed to operate at a low frequency from the input list of process IDs, selects CPU cores that will be affected by dedicated instructions, and outputs them as pairs. The process ID selection logic at this time selects the processes with the highest tolerance for low-frequency operation.

[0061] (Input / output of the low-frequency permissible process assignment determination unit 140) The inputs and outputs of the low-frequency permissible process assignment determination unit 140 are described below. Input 1: The dedicated instruction execution affected core identification unit 120 receives the numbers of the CPU cores affected by the dedicated instructions. Input 2: The Running Process Operating Frequency Performance Impact Determination Unit 130 inputs a list of process IDs running on the server in question, along with the impact of each process's operating frequency. Next, the output of the low-frequency permissible process assignment determination unit 140 is as follows. Output: Outputs pairs of process IDs capable of low-frequency operation and core IDs affected by dedicated instructions.

[0062] (Operation of the low-frequency permissible process assignment determination unit 140) The operation of the low-frequency permissible process assignment determination unit 140 will be described below. As shown in Figure 1, the CPU 10 has 10 physical cores 11 (No. 1-No. 10), and six processes (A, B, C, D, E, F) are running. In this situation, the low-frequency permissible process assignment determination unit 140 makes the following determination.

[0063] The low-frequency permissible process assignment determination unit 140 accepts the following two inputs, input 1 and input 2. Input 1: "Information about the core numbers affected by the dedicated instruction" ⇒ Effects are being observed (frequency decrease): No.1, No.2, No.3, No.4, No.5, No.6 ⇒ No impact observed: No.7, No.8, No.9, No.10

[0064] Input 2: "A list of process IDs running on the server in question, and their respective characteristics (the degree of influence from the operating frequency)." ⇒Affected (performance degradation): A, B, C, D ⇒ Unaffected: E, F

[0065] The low-frequency permissible process assignment determination unit 140 selects processes E and F from the list of process IDs as "processes that may be operated at a low frequency". To run these processes, we select "No.1" and "No.2" from among "No.1, No.2, No.3, No.4, No.5, No.6". Finally, the two pairs (Core No. 1 and Process E) and (Core No. 2 and Process F) are output.

[0066] <Process core allocation section 150> The process core allocation unit 150 assigns the processes identified by the low-frequency-tolerant process allocation determination unit 140 to logical cores where the operating frequency will decrease. For example, the process core allocation unit 150 assigns a process with the input process ID to a CPU core that will run on the input CPU core. The cores affected by the input performance are stored as a list of cores (not shown). The process core allocation unit 150 performs the following inputs and outputs. Input (when changing core allocation for an existing process): Pair of process ID and CPU core ID Input (when starting a new process): Command name Output: None

[0067] The core allocation method for the process core allocation unit 150 to the process will be described below. Pattern 1: OS Scheduler Method As shown in Figures 2 and 3, the OS scheduler method modifies the OS kernel's task scheduler to schedule tasks to specific CPU cores.

[0068] The second method involves changing the scheduling to a specific CPU core by modifying the CPU allocation of running tasks, such as the sched_setaffinity() function [online], [searched September 6, 2022], Internet <URL:https: / / linuxjm.osdn.jp / html / LDP_man-pages / man2 / sched_setaffinity.2.html>.

[0069] Pattern 2: Implementation method for the task scheduler in an application As shown in Figures 2 and 3, the implementation method for task schedulers in applications is such that, if an application has its own task scheduler, this task scheduler allocates CPU cores. Specifically, a mechanism for dynamically specifying the CPU core to which a task should be scheduled is used, such as the pthread_setaffinity function ([online], [searched September 6, 2022], Internet <URL: https: / / linuxjm.osdn.jp / html / LDP_man-pages / man3 / pthread_setaffinity_np.3.html>, and the relevant process and CPU core are specified.

[0070] Pattern 3: Method of application when a new process is started Taskset, [online], [searched September 6, 2022], Internet <URL: https: / / www.man7.org / linux / man-pages / man1 / taskset.1.html> This method uses a technique to specify the CPU core on which a process will run when it is started, allowing it to run on a specific core.

[0071] In the above-described example of the operation of the low-frequency-permissible process assignment determination unit 140, we will now describe the case where the low-frequency-permissible process assignment determination unit 140 outputs two pairs (core No. 1 and process E) and (core No. 2 and process F) to the process core assignment unit 150. The process core assignment unit 150 receives two pairs (core No. 1 and process E) and (core No. 2 and process F) from the low-frequency permissible process assignment determination unit 140, and sets the core No. 1 to run process E and the core No. 2 to run process F.

[0072] <New process startup / low-frequency operation feasibility determination unit 160> The new process startup / low-frequency operation feasibility determination unit 160 uses command names for both input and output. The new process startup / low-frequency operation feasibility determination unit 160 determines whether the input command is capable of low-frequency operation. If it is, it outputs the command name to the process core allocation unit 150 so that it can be operated on a CPU core affected by the dedicated instruction. Specifically, the new process startup / low-frequency operation feasibility determination unit 160 compares the input command name with a command name in an internal database to determine whether it is capable of low-frequency operation. If the new process startup / low-frequency operation feasibility determination unit 160 determines that it is capable of low-frequency operation, it outputs the command name to the process core allocation unit 150.

[0073] The operation of the computing system 1000, configured as described above, will be explained below. [Task Scheduler Device Operation] This section describes how the task scheduler operates when moving the core of a running process. In the following description, "physical core" will be referred to as "CPU core."

[0074] <When moving the core of a running process> Figure 7 shows the operation pattern of the task scheduler device when moving the core of a running process, and Figure 8 is its flowchart. In Figure 7, the functional parts of the corresponding operation are shown as thick blocks. In step S11, the dedicated instruction execution detection unit 110 receives the identifier (PID, etc.) of the process to be determined as the process that will execute the dedicated instruction, and outputs whether or not the process will execute the dedicated instruction.

[0075] In step S12, the dedicated instruction execution detection unit 110 determines whether or not it has detected the execution of a dedicated instruction. If it does not detect the execution of a dedicated instruction (S12: No), the process returns to step S11.

[0076] If the execution of a dedicated instruction is detected (S12: Yes) (symbol aa in Figure 7), in step S13, the dedicated instruction execution affected core identification unit 120 identifies the core executing the input process ID and the cores affected by it. Specifically, the dedicated instruction execution affected core identification unit 120 receives the number of the process executing the dedicated instruction and outputs the number of the CPU core affected by the dedicated instruction (symbol bb in Figure 7).

[0077] In step S14, the low-frequency permissible process assignment determination unit 140 refers to the information collection process shown in Figure 12, which is being executed by the running process operating frequency performance impact determination unit 130, and receives the determination result of the impact on the operating frequency performance of the running process from the running process operating frequency performance impact determination unit 130 (indicated by cc in Figure 7).

[0078] In step S15, the low-frequency-tolerant process assignment determination unit 140 determines, based on the information of the core numbers affected by the dedicated instructions and the performance impact information due to the operating frequency of each process, which processes will have less impact even when operating at a low frequency, to assign to the cores affected by the dedicated instructions.

[0079] In step S16, the low-frequency permissible process assignment determination unit 140 determines whether or not there is a change in the assigned core for the low-frequency process. If there is no change in the assigned core for the low-frequency process (S16: No), the process returns to step S11.

[0080] If there is a change in the assigned core for a low-frequency process (S:Yes) (indicated as dd in Figure 7), in step S17, the process core assignment unit 150 runs the process with the input process ID on the input CPU core. The process core assignment unit 150 changes the core assignment for the input performance-affected core (indicated as ee in Figure 7), retains the information as a list of cores (not shown), and terminates the processing of this flow.

[0081] <When scheduling a new startup process> Figure 9 shows the operation pattern of the task scheduler device when scheduling a new startup process, and Figure 10 is its flowchart. In Figure 9, the functional parts of the corresponding operation are shown as thick blocks. In step S21, the new process startup / low-frequency operation feasibility determination unit 160 determines whether the input command is capable of low-frequency operation. If it is, it outputs the command name to the process core allocation unit 150 (indicated as ff in Figure 9) so that the command can be executed on a CPU core affected by the dedicated instruction.

[0082] In step S22, the process core allocation unit 150 runs the process with the input process ID on the input CPU core. The process core allocation unit 150 modifies the core allocation for the performance-affected core (indicated by the symbol ee in Figure 9), retains the information as a list of cores, and terminates the processing of this flow.

[0083] <Collection of frequency impact information for each process (performed periodically)> Figure 11 shows the operation pattern of the task scheduler device for collecting frequency influence information (executed periodically) for each process, and Figure 12 is its flowchart. In Figure 11, the functional parts of the corresponding operation are shown as thick blocks.

[0084] In step S31, the running process operating frequency performance impact determination unit 130 determines the performance impact of the operating frequency for all processes running within the server (task scheduler device 100). Specifically, the running process operating frequency performance impact determination unit 130 is activated at regular intervals (for example, 10 seconds) or when a process is started or terminated, and determines the performance impact of the CPU operating frequency on each process.

[0085] In step S32, the process execution priority management unit 21, based on instructions from the running process operating frequency performance impact determination unit 130, obtains a list of process IDs and their respective execution priorities within the server (task scheduler device 100) and sends them to the running process operating frequency performance impact determination unit 130 (indicated as gg in Figure 11). Specifically, the process execution priority management unit 21 obtains the execution priority of each process using the nice command.

[0086] In step S33, the running process operating frequency performance impact determination unit 130 is activated at regular intervals (for example, 10 seconds) or when a new process is started or terminated, and determines the performance impact of the CPU operating frequency on each process.

[0087] In step S34, the process IO amount recording unit 22, based on instructions from the running process operating frequency performance impact determination unit 130, obtains a list of processes operating within the server (task scheduler device 100) and their respective Input / Output amounts, and sends them to the running process operating frequency performance impact determination unit 130 (symbol hh in Figure 11). Specifically, the process IO amount recording unit 22 obtains the IO amount of each process using the iostat command and terminates the processing of this flow.

[0088] [Hardware configuration] The task scheduler devices 100 and 100A (Figures 1 to 4) according to the above embodiment are implemented by a computer 900 having a configuration such as that shown in Figure 13. Figure 13 is a hardware configuration diagram showing an example of a computer 900 that implements the functions of task scheduler devices 100 and 100A (Figures 1 to 4). Computer 900 has a CPU 901, ROM 902, RAM 903, HDD 904, communication interface (I / F: Interface) 906, input / output interface (I / F) 905, and media interface (I / F) 907.

[0089] The CPU 901 operates based on programs stored in the ROM 902 or HDD 904, and controls the various parts of the task scheduler devices 100 and 100A (Figures 1 to 4). The ROM 902 stores boot programs executed by the CPU 901 when the computer 900 starts up, as well as programs that depend on the computer 900's hardware.

[0090] The CPU 901 controls input devices 910, such as a mouse or keyboard, and output devices 911, such as a display, via the input / output interface 905. The CPU 901 acquires data from the input devices 910 via the input / output interface 905 and outputs the generated data to the output devices 911. In addition to the CPU 901, a GPU (Graphics Processing Unit) or the like may also be used as a processor.

[0091] HDD904 stores programs executed by CPU901 and data used by those programs. Communication I / F906 receives data from other devices via a communication network (e.g., NW(Network)920) and outputs it to CPU901, and also transmits data generated by CPU901 to other devices via the communication network.

[0092] The media interface 907 reads a program or data stored in the recording medium 912 and outputs it to the CPU 901 via the RAM 903. The CPU 901 loads the program related to the desired processing from the recording medium 912 onto the RAM 903 via the media interface 907 and executes the loaded program. The recording medium 912 can be an optical recording medium such as a DVD (Digital Versatile Disc) or PD (Phase Change Rewritable Disk), a magneto-optical recording medium such as an MO (Magneto Optical Disk), a magnetic recording medium, a conductive memory tape medium, or a semiconductor memory.

[0093] For example, when computer 900 functions as a task scheduler device 100, 100A (Figures 1 to 4) configured as one of the devices according to this embodiment, the CPU 901 of computer 900 realizes the functions of task scheduler devices 100, 100A by executing a program loaded on RAM 903. The HDD 904 stores the data in RAM 903. The CPU 901 reads and executes a program related to the desired processing from the recording medium 912. Alternatively, the CPU 901 may read a program related to the desired processing from another device via a communication network (NW 920).

[0094] [effect] As described above, in a computing system 1000, 1000A (Figures 1 to 4) that executes dedicated instructions specialized for a specific operation, a task scheduler device 100, 100A (Figures 1 to 4) assigns a dedicated instruction execution process to a logical core using hardware multithreading that makes one physical core appear as multiple logical cores, and comprises a dedicated instruction execution detection unit 110 (dedicated instruction detection unit) that detects when a dedicated instruction is executed, a dedicated instruction execution affected core identification unit 120 (core identification unit) that identifies a logical core whose operating frequency decreases due to the execution of a dedicated instruction and which operates on the same physical core as the dedicated instruction execution core, a low-frequency tolerable process assignment determination unit 140 (tolerable process determination unit) that makes a determination to identify a process that satisfies predetermined performance requirements even when operating at a low frequency for the logical core whose operating frequency decreases as identified by the dedicated instruction execution affected core identification unit 120, and a process core assignment unit 150 that assigns the process identified by the low-frequency tolerable process assignment determination unit 140 to the logical core whose operating frequency decreases.

[0095] In this way, the task scheduler devices 100 and 100A can reduce the number of physical cores running on a group of processes, including processes that execute specialized instructions, such as SIMD instructions or dedicated instructions for encryption, while allocating the necessary CPU time to each process. By reducing the number of physical cores running on a group of processes, power consumption can be reduced. In other words, cores with reduced operating frequencies are identified, and processes that meet predetermined performance requirements even when operating at low frequencies (processes that are less affected by low-frequency operation) are scheduled to the same physical cores as SIMD execution, thereby increasing core utilization. This improves core utilization, reduces the number of operating CPU cores, and reduces power consumption. In particular, since vRAN (vDU) makes full use of SIMD operations, improving core efficiency is likely to be a challenge, but this task scheduler device 100A (Figure 4) can achieve both improved core utilization and a reduction in the number of operating CPU cores in vRAN.

[0096] The requirements to be achieved can be summarized as follows: Requirement 1: Each process is allocated the necessary CPU processing time (performance improvement effect). Requirement 2: Reduction of the number of execution cores (minimizing the number of execution cores required for each process to run) (power saving effect) Requirements 1 and 2 above can be achieved.

[0097] In the task scheduler devices 100 and 100A (Figures 1 to 4), the dedicated instruction execution detection unit 110 stores a list of processes that use pre-registered dedicated instructions, and compares this process list with the names of currently running processes to detect whether or not a dedicated instruction has been executed.

[0098] In this way, the task scheduler devices 100 and 100A can improve core utilization, reduce the number of CPU cores in operation, and reduce power consumption.

[0099] In the task scheduler devices 100 and 100A (Figures 1 to 4), the low-frequency permissible process assignment determination unit 140 selects a pair of processes that may be operated at a low frequency and cores that are affected by the dedicated instructions, based on information about the core numbers affected by the dedicated instructions and performance impact information based on the operating frequency of each process.

[0100] In this way, the task scheduler devices 100 and 100A select processes that can operate at low frequencies and CPU cores affected by dedicated instructions, outputting them as pairs. This allows for selection of various combinations, such as selecting from those with the highest tolerance for low-frequency operation. Furthermore, the task scheduler devices 100 and 100A enable selection in order of priority according to tolerance.

[0101] Task scheduler devices 100 and 100A (Figures 1 to 4) are equipped with a running process operating frequency performance impact determination unit 130 (performance impact determination unit) that determines the performance impact of the operating frequency of a running process. The running process operating frequency performance impact determination unit 130 compares a pre-registered process list (process ID list) with the name of the currently running process to determine the impact of the operating frequency performance of the running process.

[0102] Thus, task scheduler devices 100 and 100A can determine the performance impact of operating frequency using a static method that determines the effect of operating frequency based on information such as process names. Since the static method involves comparing a pre-registered list of processes with the name of the currently running process, it requires little computation and can be determined quickly.

[0103] Task scheduler devices 100 and 100A (Figures 1 to 4) are equipped with a running process operating frequency performance impact determination unit 130 (performance impact determination unit) that determines the performance impact of the operating frequency of a running process. The running process operating frequency performance impact determination unit 130 acquires the execution priority and process input / output amount of each process, integrates the execution priority and process input / output amount to obtain an impact score, and determines the impact of the operating frequency performance of the running process based on this impact score.

[0104] Thus, task scheduler devices 100 and 100A can determine the performance impact of operating frequency by a dynamic method for determining the performance impact of operating frequency on a running process. The computational dynamic method can dynamically determine the performance impact of operating frequency. Even in cases where static methods cannot adequately address the issue, the performance impact of operating frequency can be adaptively determined.

[0105] Furthermore, the computing system 1000, 1000A (Figures 1-4) executes dedicated instructions specialized for specific operations, and includes a task scheduler device 100, 100A (Figures 1-4) that assigns the dedicated instruction execution process to a logical core using hardware multithreading, which makes one physical core appear as multiple logical cores. The task scheduler device 100, 100A (Figures 1-4) includes a dedicated instruction execution detection unit 110 that detects the execution of a dedicated instruction, a dedicated instruction execution affected core identification unit 120 that identifies a logical core whose operating frequency decreases due to the execution of a dedicated instruction and which operates on the same physical core as the dedicated instruction execution core, a low-frequency-tolerant process assignment determination unit 140 that determines to identify a process that satisfies predetermined performance requirements even when operating at a low frequency for the logical core whose operating frequency decreases as identified by the dedicated instruction execution affected core identification unit 120, and a process core assignment unit 150 that assigns the process identified by the low-frequency-tolerant process assignment determination unit 140 to the logical core whose operating frequency decreases.

[0106] The computing systems 1000 and 1000A (Figures 1 to 4) are computer systems in which the CPU (processor) on the server supports general-purpose instructions as well as specialized instructions specific to particular operations (such as SIMD arithmetic instructions and specialized instructions for encryption). The above processor can also be applied to other processors besides CPUs, such as GPUs, FPGAs, and ASICs, if they have a function to identify SIMD computation execution cores.

[0107] Note that a dedicated instruction can be any instruction that is specialized for a particular operation. In this embodiment, a SIMD instruction or a dedicated instruction for encryption is used as an example, but SIMD / encryption is just an example, and the same can be applied to dedicated instructions other than SIMD / encryption.

[0108] Furthermore, among the processes described in the above embodiments, all or part of the processes described as being performed automatically may be performed manually, or all or part of the processes described as being performed manually may be performed automatically by known methods. In addition, the processing procedures, control procedures, specific names, and information including various data and parameters shown in the above documents and drawings may be changed at will unless otherwise specified. Furthermore, the components of each illustrated device are functionally conceptual and do not necessarily need to be physically configured as shown. In other words, the specific forms of distribution and integration of each device are not limited to those shown, and all or part of them can be functionally or physically distributed and integrated in any unit according to various loads and usage conditions.

[0109] Furthermore, each of the above configurations, functions, processing units, and processing means may be implemented in hardware, either partially or entirely, by designing them as integrated circuits, for example. Alternatively, each of the above configurations and functions may be implemented in software that allows the processor to interpret and execute programs that implement each function. Information such as programs, tables, and files that implement each function can be stored in memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC (Integrated Circuit) card, an SD (Secure Digital) card, or an optical disc. [Explanation of Symbols]

[0110] 10 CPUs (Processors) 11 physical cores 20 OS 21 Process Execution Priority Management Unit 22 Process I / O Amount Recording Unit 30 userland 100,100A Task Scheduler Device 110 Dedicated Instruction Execution Detection Unit (Dedicated Instruction Detection Unit) 120 Dedicated Instruction Execution Influence Core Identification Unit (Core Identification Unit) 130 Performance impact determination unit for the operating frequency of the running process (Performance impact determination unit) 140 Low-frequency permissible process assignment determination unit (permissible process determination unit) 150 Process Core Allocation Unit 160 New process startup / low-frequency operation feasibility determination unit 1000,1000A Calculation System

Claims

1. A task scheduler device for a computing system that executes specialized instructions for specific operations, which uses hardware multithreading to make one physical core appear as multiple logical cores, and assigns the execution process of the specialized instructions to the logical cores, Equipped with a processor, The aforementioned processor, A dedicated instruction detection function that detects when the aforementioned dedicated instruction is executed, A core identification function that identifies the logical core whose operating frequency is reduced, which operates on the same physical core as the core that executes the dedicated instruction, as a result of the execution of the dedicated instruction, The core identification function determines which process satisfies predetermined performance requirements even when operating at a low frequency for the logic core whose operating frequency has decreased, and The process core assignment function assigns the process identified by the acceptable process determination function to the logic core whose operating frequency is reduced. A task scheduler device characterized by the following:

2. The dedicated instruction detection function of the processor stores a list of processes that use pre-registered dedicated instructions, compares the process list with the name of a currently running process, and detects whether or not the dedicated instruction has been executed. The task scheduler device according to claim 1.

3. The permissible process determination function of the processor selects a pair of processes that may be operated at a lower frequency and cores that are affected by the dedicated instructions, based on information about the number of cores affected by the dedicated instructions and performance impact information based on the operating frequency of each process. The task scheduler device according to claim 1.

4. The processor is It has a performance impact determination function that determines the performance impact of the operating frequency of a running process. The performance impact determination function of the aforementioned processor compares a pre-registered list of processes with the name of a currently running process to determine the impact of the operating frequency performance of the running process. The task scheduler device according to claim 1.

5. The processor is It has a performance impact determination function that determines the performance impact of the operating frequency of a running process. The performance impact determination function of the processor acquires the execution priority and process I / O volume of each process, integrates the execution priority and process I / O volume to obtain an impact score, and determines the impact of the operating frequency performance of the running process based on this impact score. The task scheduler device according to claim 1.

6. A computing system that executes specialized instructions for specific operations, The system includes a task scheduler device that uses hardware multithreading to make one physical core appear as multiple logical cores, and assigns the execution process of the dedicated instructions to the logical core. The task scheduler device, A dedicated instruction detection unit that detects when the aforementioned dedicated instruction is to be executed, A core identification unit identifies the logical core whose operating frequency decreases due to the execution of a dedicated instruction, and which operates on the same physical core as the core that executes the dedicated instruction. The core identification unit determines which process satisfies predetermined performance requirements even when operating at a low frequency for the logic core whose operating frequency is reduced, and The system includes a process core allocation unit that assigns the process identified by the permissible process determination unit to the logic core whose operating frequency is reduced. A computing system characterized by the following features.

7. A task scheduling method for a task scheduler device that assigns execution processes for dedicated instructions specialized for specific operations, A step of detecting that the aforementioned dedicated instruction is to be executed, The steps include identifying a logical core whose operating frequency is reduced, which operates on the same physical core as the core executing the dedicated instruction, as a result of the execution of the dedicated instruction, The steps include determining which processes will meet predetermined performance requirements even when operating at a lower frequency for the identified logic cores with reduced operating frequencies, and The steps include assigning the identified process to the logic core whose operating frequency is reduced, Execute A task scheduling method characterized by the following:

8. A program for causing a computer to function as a task scheduler device according to any one of claims 1 to 5.

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