Semiconductor equipment

Abstract

To provide a semiconductor device with reduced power consumption that can perform a product-sum operation.SOLUTION: A semiconductor device includes first and second circuits, and the second circuit includes first and second switches, a current / voltage conversion circuit, and a first transistor. The first circuit is electrically connected to a first terminal of the second circuit. A first terminal of the first switch is electrically connected to the first terminal of the second circuit. A second terminal of the first switch is electrically connected to an input terminal of the current / voltage conversion circuit. An output terminal of the current / voltage conversion circuit is electrically connected to a first terminal of the first transistor. A second terminal of the first transistor is electrically connected to a first terminal of the second switch. A second terminal of the second switch is electrically connected to a second terminal of the second circuit. The first circuit has a function of retaining a plurality of pieces of first data and a function of making a current in an amount responsive to the sum of products of the plurality of pieces of first data and a plurality of pieces of second data flow to the first terminal of the second circuit when the plurality of pieces of second data are input to the first circuit.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] One aspect of the present invention relates to semiconductor devices and electronic devices.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to objects, methods of operation, or methods of manufacture. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed herein include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, memory devices, signal processing devices, sensors, processors, electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for testing them. [Background technology]

[0003] Currently, there is a great deal of activity in developing integrated circuits that mimic the structure of the human brain. These integrated circuits incorporate the brain's structure as electronic circuits, possessing circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brainmorphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture and are expected to be able to perform parallel processing with extremely low power consumption compared to von Neumann architectures, where power consumption increases with increasing processing speed.

[0004] A model of information processing that mimics a neural network containing "neurons" and "synapses" is called an artificial neural network (ANN). By using an ANN, it is possible to perform inference with accuracy comparable to or exceeding that of humans. In an ANN, the main operation is the sum of products, or weighted sum of neuron outputs.

[0005] An invention utilizing a memory cell with an OS transistor as a circuit for performing multiply-accumulate operations is disclosed, for example, in Patent Document 1. An OS transistor (sometimes called an oxide semiconductor transistor) is a transistor having a metal oxide semiconductor in its channel formation region, and it has been reported that it has an extremely small off-current (for example, Non-Patent Documents 1 and 2). Furthermore, various semiconductor devices using OS transistors have been fabricated (for example, Non-Patent Documents 3 and 4). The manufacturing process for OS transistors can be incorporated into the conventional CMOS process for Si transistors, and OS transistors can be stacked on top of Si transistors (for example, Non-Patent Document 4). [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2017-168099 [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-Patent Document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-Patent Document 3] S. Amano et al., “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). [Non-Patent Document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol.79, pp.149-156 (2017). [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] When performing a sum-of-accumulate operation using digital circuits, the multiplication of the multiplier (multiplier data) and the multiplicand (multiplicand data) is performed by a digital multiplier circuit. Subsequently, the digital data obtained from this multiplication (product data) is added by a digital adder circuit to obtain the digital data (sum-of-accumulate data) as the result of the sum-of-accumulate operation. It is preferable that the digital multiplier circuit and digital adder circuit be capable of handling multi-bit operations. However, in this case, the circuit size of each of the digital multiplier circuit and digital adder circuit may increase, which may lead to an increase in the overall circuit area of ​​the arithmetic circuit and an increase in power consumption.

[0009] In addition to multiply-accumulate operations, artificial neural networks also perform activation function calculations. If the activation function calculations are performed using digital circuits, as mentioned above, this may lead to an increase in the overall circuit area of ​​the calculation circuit and an increase in power consumption. Furthermore, if multiply-accumulate operations are performed using analog circuits instead of digital multipliers and digital adders, the result of the calculation output by the analog circuit will be an analog signal. Therefore, in order to input this result into the digital circuit that performs the activation function calculation, it is necessary to convert the analog signal to a digital signal first. Moreover, since the digital circuit outputs the result of the activation function calculation as a digital signal, in order to perform a multiply-accumulate operation again using this result, it is necessary to convert the digital signal of the calculation result into an analog signal before inputting it into the analog circuit. In particular, in artificial neural networks, multiply-accumulate operations and activation function calculations are performed repeatedly, so in circuits that mix analog and digital circuits, conversion between digital and analog signals occurs frequently. For this reason, the power consumption of the circuit that performs the conversion between digital and analog signals may also increase.

[0010] One aspect of the present invention aims to provide a semiconductor device capable of calculating activation functions. Alternatively, one aspect of the present invention aims to provide a semiconductor device with low power consumption.

[0011] Alternatively, one aspect of the present invention aims to provide a novel semiconductor device or the like. Alternatively, one aspect of the present invention aims to provide an electronic device having the above-mentioned semiconductor device.

[0012] It should be noted that the problems addressed by one aspect of the present invention are not limited to those listed above. The problems listed above do not preclude the existence of other problems. These other problems are those not mentioned in this section, as described below. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention solves at least one of the problems listed above and other problems. It should be noted that one aspect of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0013] (1) One aspect of the present invention is a semiconductor device having a first circuit and a second circuit, wherein the second circuit includes a first switch, a second switch, a current-voltage conversion circuit, and a first transistor. The first circuit is electrically connected to the first terminal of the second circuit, and the first terminal of the second circuit is electrically connected to the first terminal of the first switch, so the first circuit is electrically connected to the first terminal of the first switch. The second terminal of the first switch is electrically connected to the input terminal of the current-voltage conversion circuit. The output terminal of the current-voltage conversion circuit is electrically connected to the first terminal of the first transistor, and the second terminal of the first transistor is electrically connected to the first terminal of the second switch. The first circuit has a plurality of first data, W1 to W m (m is an integer greater than or equal to 1.) The function of holding X1 to X as multiple second data in the first circuit. m The first transistor has the function of supplying a current corresponding to the value of equation (A1) to the first terminal of the second circuit when a current is input. The current-voltage conversion circuit also has the function of outputting a first potential corresponding to the current input to the input terminal of the current-voltage conversion circuit to the output terminal of the current-voltage conversion circuit. The first transistor also has the function of outputting a first potential from its second terminal when the first potential is greater than or equal to the sum of the gate potential of the first transistor and the threshold voltage of the first transistor, and the function of outputting a potential equal to the sum from its second terminal when the first potential is less than the sum.

[0014]

number

[0015] (2) Alternatively, in one aspect of the present invention, in (1) above, the current-voltage conversion circuit may be configured to include an operational amplifier and a load. In particular, it is preferable that the inverting input terminal of the operational amplifier is electrically connected to the first terminal of the current-voltage conversion circuit and the first terminal of the load, and the output terminal of the operational amplifier is electrically connected to the second terminal of the load.

[0016] (3) Alternatively, in one aspect of the present invention, in (2) above, the load may be configured to have one of a resistor, a diode, or a transistor.

[0017] (4) Alternatively, in one aspect of the present invention, any one of the semiconductor devices described in (1) to (3) above has a third circuit including a current mirror circuit, and further, the first circuit has a first cell, a second cell, a first wiring, a second wiring, and a third wiring, the first cell has a first capacitance, and the second cell has a second capacitance. Specifically, the first wiring is electrically connected to the first cell, the first terminal of the second circuit, and the third circuit; the second wiring is electrically connected to the second cell and the third circuit; and the third wiring is electrically connected to the first terminal of the first capacitance and the first terminal of the second capacitance. The first cell also has the function of holding a first potential at the second terminal of the first capacitance and the function of flowing a current amount corresponding to the first potential through the first wiring. The second cell also has the function of holding a second potential at the second terminal of the second capacitance and the function of flowing a current amount corresponding to the second potential through the second wiring. Furthermore, the current mirror circuit has the function of passing the current flowing through the second wiring to the first wiring as well. One of the multiple first data points corresponds to the potential difference between the first potential and the second potential. The third wiring receives a potential corresponding to one of the multiple second data points.

[0018] (5) Alternatively, in any one of (1) to (4) above, the first cell may have a configuration in which the first cell has a second transistor and a third transistor, and the second cell has a fourth transistor and a fifth transistor. Specifically, the first terminal of the second transistor is electrically connected to the second terminal of the first capacitor and the gate of the third transistor, the first terminal of the third transistor is electrically connected to the first wiring, the first terminal of the fourth transistor is electrically connected to the second terminal of the second capacitor and the gate of the fifth transistor, and the first terminal of the fifth transistor is electrically connected to the second wiring.

[0019] (6) Alternatively, one aspect of the present invention is an electronic device having any one of the semiconductor devices described in (1) to (5) above, and a housing. Furthermore, the semiconductor device performs multiply-accumulate operations and ReLU function operations.

[0020] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), and devices having such circuits. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components that house chips in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices and may contain semiconductor devices.

[0021] Furthermore, when it is stated in this specification that X and Y are connected, it is assumed that this specification discloses the cases in which X and Y are electrically connected, functionally connected, and directly connected. Therefore, it is assumed that the disclosed connections are not limited to predetermined connections, such as those shown in the figures or text, but also include connections other than those shown in the figures or text. X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0022] One example of a case where X and Y are electrically connected is that one or more elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitive elements, inductors, resistors, diodes, display devices, light-emitting devices, loads, etc.) can be connected between X and Y. A switch has the function of controlling on / off states. In other words, a switch has the function of controlling whether or not current flows by being in a conductive state (on state) or a non-conductive state (off state).

[0023] One example of a functional connection between X and Y is when one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal conversion circuits (digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase the signal amplitude or current amount, etc., operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y.

[0024] Furthermore, when it is explicitly stated that X and Y are electrically connected, this includes both cases where X and Y are electrically connected (i.e., connected with another element or circuit in between) and cases where X and Y are directly connected (i.e., connected without another element or circuit in between).

[0025] Furthermore, it can be expressed as, for example, "X, Y, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and the connection is in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Alternatively, it can be expressed as, "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Alternatively, it can be expressed as, "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using similar notation to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and their technical scope determined. Note that these notational methods are examples only and are not limited to them. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0026] Even if independent components are shown as electrically connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a wire also functions as an electrode, a single conductive film possesses the functions of both a wire and an electrode. Therefore, in this specification, "electrically connected" includes cases where a single conductive film possesses the functions of multiple components.

[0027] Furthermore, in this specification, "resistive element" can refer to, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, "resistive element" includes wiring having a resistance value, transistors, diodes, coils, etc., through which current flows between the source and drain. Therefore, the term "resistive element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistive element." The resistance value can be, for example, preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Also, for example, 1Ω or more and 1 × 10 9 It may also be less than or equal to Ω.

[0028] Furthermore, in this specification, "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value, parasitic capacitance, the gate capacitance of a transistor, etc. Therefore, in this specification, it includes parasitic capacitance appearing between wirings, the gate capacitance appearing between one of the sources or drains of a transistor and the gate, etc. Also, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Also, the term "pair of electrodes" in "capacitance" can be replaced with terms such as "pair of conductors," "pair of conductive regions," and "pair of regions." The capacitance value can be, for example, 0.05fF or more and 10pF or less. Alternatively, it may be, for example, 1pF or more and 10μF or less.

[0029] Furthermore, in this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as either the source or the drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, the terms source and drain can be used interchangeably. Also, in this specification, when describing the connection relationships of a transistor, the notation "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) is used. Depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case, in this specification, one of the gate or back gate of the transistor may be called the first gate, and the other of the gate or back gate of the transistor may be called the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, if a transistor has three or more gates, in this specification, each gate may be referred to as the first gate, second gate, third gate, and so on.

[0030] Furthermore, in this specification, the term "node" can be replaced with terms such as terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration, device structure, etc. Also, terminals, wiring, etc. can be replaced with "node."

[0031] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative, and as the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, and the potential output from the circuit also change.

[0032] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, if two wires are described as "functioning as wires that supply a high-level potential," the high-level potentials provided by each wire do not have to be equal. Similarly, if two wires are described as "functioning as wires that supply a low-level potential," the low-level potentials provided by each wire do not have to be equal.

[0033] "Electric current" refers to the phenomenon of electric charge movement (electrical conduction). For example, the statement "electrical conduction of positively charged elements is occurring" can be rephrased as "electrical conduction of negatively charged elements is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of electric charge movement associated with the movement of carriers (electrical conduction). Carriers here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., is the direction in which positive carriers move and is expressed as a positive current quantity. In other words, the direction in which negative carriers move is the opposite direction to the direction of the current and is expressed as a negative current quantity. Therefore, in this specification, if there is no specification regarding the positive or negative (or direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, descriptions such as "current is input to element A" can be rephrased as "current is output from element A."

[0034] Furthermore, the ordinal numbers "1st," "2nd," and "3rd" in this specification are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "1st" in one embodiment of this specification may be referred to as "2nd" in another embodiment or in the claims. Also, for example, a constituent element referred to as "1st" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0035] Furthermore, in this specification, terms indicating placement such as "above" and "below" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms explained in the specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0036] Furthermore, the terms "above" or "below" do not limit the positional relationship of the components to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0037] Furthermore, in this specification, terms such as "film" and "layer" can be interchanged as needed. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Alternatively, depending on the circumstances, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the terms "insulating layer" or "insulating film" may be changed to the term "insulator."

[0038] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wiring" are formed as a single unit. Similarly, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where multiple "electrodes," "wiring," or "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and for example, a "terminal" can be part of "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" depending on the circumstances.

[0039] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" can be interchanged with each other depending on the circumstances or situation. For example, the term "wiring" may be changed to the term "signal line." Also, for example, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true; terms such as "signal line" and "power line" may be changed to the term "wiring." Terms such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true; terms such as "signal line" may be changed to the term "power line." In addition, the term "potential" applied to the wiring may be changed to the term "signal," depending on the circumstances or situation. Similarly, the reverse is also true; terms such as "signal" may be changed to the term "potential."

[0040] In this specification, semiconductor impurities refer to elements other than the main components that make up the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. In particular, examples include hydrogen (which is also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that alter the properties of the semiconductor include, for example, Group 1 elements (excluding hydrogen), Group 2 elements, Group 13 elements, Group 15 elements, and oxygen.

[0041] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive (on) state or a non-conductive (off) state. Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows. Examples include electrical switches and mechanical switches. In other words, a switch is not limited to any particular type, as long as it can control current.

[0042] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. When a transistor is used as a switch, the "conducting state" of the transistor refers to a state in which the source and drain electrodes of the transistor can be considered to be electrically short-circuited. Conversely, the "non-conducting state" of the transistor refers to a state in which the source and drain electrodes of the transistor can be considered to be electrically disconnected. When a transistor is used simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0043] One example of a mechanical switch is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and it operates by controlling the conduction and non-conductivity through the movement of these electrodes.

[0044] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Furthermore, "approximately parallel" or "roughly parallel" means a state in which two lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Furthermore, "approximately perpendicular" or "roughly perpendicular" means a state in which two lines are positioned at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0045] According to one aspect of the present invention, a semiconductor device capable of calculating activation functions can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0046] Alternatively, according to one aspect of the present invention, a novel semiconductor device or the like can be provided. Alternatively, according to one aspect of the present invention, an electronic device having the above-mentioned semiconductor device can be provided.

[0047] The effects of one aspect of the present invention are not limited to those listed above. The effects listed above do not preclude the existence of other effects. These other effects are those described below and not mentioned in this section. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. One aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may, in some cases, not have the effects listed above. [Brief explanation of the drawing]

[0048] [Figure 1] Figure 1 is a block diagram showing an example of a semiconductor device configuration. [Figure 2] Figure 2 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 3] Figures 3A and 3B are circuit diagrams showing example configurations of circuits included in a semiconductor device. [Figure 4] Figure 4 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 5] Figure 5 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 6] Figure 6 is a timing chart showing an example of the operation of a semiconductor device. [Figure 7] Figure 7 is a block diagram showing an example configuration of a semiconductor device. [Figure 8] Figure 8 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 9] Figure 9 is a block diagram showing an example configuration of a semiconductor device. [Figure 10]Figure 10 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 11] Figure 11 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 12] Figures 12A and 12B illustrate a hierarchical neural network. [Figure 13] Figure 13 is a block diagram showing an example of a semiconductor device configuration. [Figure 14] Figure 14 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 15] Figure 15 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 16] Figures 16A to 16C are schematic cross-sectional diagrams showing examples of transistor configurations. [Figure 17] Figure 17 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 18] Figure 18 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 19] Figures 19A and 19B are schematic cross-sectional diagrams showing examples of transistor configurations. [Figure 20] Figures 20A and 20B are schematic cross-sectional diagrams showing examples of transistor configurations. [Figure 21] Figure 21A is a top view showing an example configuration of a capacitive element, while Figures 21B and 21C are cross-sectional perspective views showing an example configuration of a capacitive element. [Figure 22] Figure 22A is a top view showing an example of the configuration of a capacitive element, Figure 22B is a cross-sectional view showing an example of the configuration of a capacitor, and Figure 22C is a cross-sectional perspective view showing an example of the configuration of a capacitive element. [Figure 23] Figure 23 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 24] Figure 24 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 25] Figure 25A illustrates the classification of IGZO crystal structures, Figure 25B illustrates the XRD spectrum of crystalline IGZO, and Figure 25C illustrates the micro-electron diffraction pattern of crystalline IGZO. [Figure 26] Figure 26A is a perspective view showing an example of a semiconductor wafer, Figure 26B is a perspective view showing an example of a chip, and Figures 26C and 26D are perspective views showing examples of electronic components. [Figure 27] Figures 27A to 27F are perspective views of the package and module containing the imaging device. [Figure 28] Figure 28 is a perspective view showing an example of an electronic device. [Figure 29] Figures 29A to 29C are perspective views showing an example of an electronic device. [Figure 30] Figure 30 is a circuit diagram showing the circuit configuration input into the circuit simulator. [Figure 31] Figure 31 is a graph showing the relationship between the input current and the output voltage, obtained by the circuit simulator. [Figure 32] Figure 32A is a graph showing the relationship between time and current, and Figure 32B is a graph showing the time variation of the output voltage obtained by the circuit simulator. [Modes for carrying out the invention]

[0049] In artificial neural networks (hereinafter referred to as neural networks), the strength of synaptic connections can be changed by providing the neural network with existing information. This process of providing the neural network with existing information to determine the connection strength is sometimes referred to as "learning."

[0050] Furthermore, by providing some information to a neural network that has undergone "training" (where connection strengths have been defined), it is possible to output new information based on those connection strengths. In this way, the process of outputting new information based on the given information and connection strengths in a neural network is sometimes called "inference" or "cognition."

[0051] Examples of neural network models include the Hopfield type and hierarchical types. In particular, a multi-layered neural network is sometimes called a "deep neural network" (DNN), and machine learning using deep neural networks is sometimes called "deep learning."

[0052] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, if a metal oxide can constitute a channel-forming region of a transistor having at least one of amplification, rectification, and switching functions, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0053] Furthermore, in this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Alternatively, metal oxides containing nitrogen may be called metal oxynitrides.

[0054] Furthermore, in this specification, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Also, if multiple configuration examples are shown within one embodiment, these configuration examples can be appropriately combined with each other.

[0055] Furthermore, any content described in one embodiment (even partial content) may be applied to, combined with, or substituted for at least one of the contents described in another embodiment (even partial content) and one or more other embodiments (even partial content).

[0056] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0057] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in the same embodiment, and at least one diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0058] The embodiments described herein will be explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention is not to be interpreted as being limited to the contents of the embodiments. In the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Also, in perspective views and the like, some components may be omitted in order to ensure clarity of the drawings.

[0059] In this specification, when the same symbol is used for multiple elements, and especially when it is necessary to distinguish them, an identifying symbol such as "_1", "[n]", or "[m,n]" may be added to the symbol.

[0060] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0061] (Embodiment 1) In this embodiment, an example of an arithmetic circuit, which is a semiconductor device according to one aspect of the present invention, will be described.

[0062] <Example of arithmetic circuit configuration 1> Figure 1 shows an example of an arithmetic circuit MAC1 capable of multiply-accumulate operations and function calculations. MAC1 is a circuit that performs multiply-accumulate operations on multiple first data held in multiple memory cells (described later) and multiple input second data, and then uses the results of these multiply-accumulate operations to perform activation function calculations. The multiple first data and multiple second data can, for example, be analog data or multi-level data (discrete data).

[0063] The arithmetic circuit MAC1 includes, as an example, a memory cell array CA, a circuit CMS, a circuit WDD, a circuit XLD, a circuit WLD, and a circuit ACTV.

[0064] The memory cell array CA comprises memory cells AM[1,1] to AM[m,n] and memory cells AMr[1] to AMr[m]. In the memory cell array CA, memory cells AM[1,1] to AM[m,n] are arranged in an m x n matrix (where m is an integer greater than or equal to 1 and n is an integer greater than or equal to 1). Memory cells AMr[1] to AMr[m] are located in the (n+1)th column of the memory cell array CA.

[0065] Memory cells AM[1,1] through AM[m,n] have the function of holding the first data, and memory cells AMr[1] through AMr[m] have the function of holding the reference data necessary for performing multiply-accumulate operations. The reference data, like the first and second data, can be analog data or multi-level data (discrete data).

[0066] Memory cell AM[1,1] is electrically connected to wiring WD[1], wiring BL[1], wiring WL[1], and wiring XL[1]. Memory cell AM[m,1] is electrically connected to wiring WD[1], wiring BL[1], wiring WL[m], and wiring XL[m]. Memory cell AM[1,n] is electrically connected to wiring WD[n], wiring BL[n], wiring WL[1], and wiring XL[1]. Memory cell AM[m,n] is electrically connected to wiring WD[n], wiring BL[n], wiring WL[m], and wiring XL[m]. Memory cell AMr[1] is electrically connected to wiring WDr, wiring BLr, wiring WL[1], and wiring XL[1]. Furthermore, the memory cell AMr[m] is electrically connected to the wiring WDr, wiring BLr, wiring WL[m], and wiring XL[m].

[0067] Detailed circuit configuration examples for memory cells AM[1,1] through AM[m,n] and memory cells AMr[1] through AMr[m] will be described later.

[0068] Circuit CMS is electrically connected, for example, to wiring BL[1] to wiring BL[n] and wiring BLr. Circuit CMS has the function of supplying current from wiring BL[1] to each of memory cells AM[1,1] to memory cells AM[m,1] and setting said current to a constant current. Circuit CMS also has the function of supplying current from wiring BL[n] to each of memory cells AM[1,n] to memory cells AM[m,n] and setting said current to a constant current. Circuit CMS also has the function of supplying current from wiring BLr to each of memory cells AMr[1] to memory cells AMr[m], the function of supplying approximately the same amount of current to wiring BL[1] to wiring BL[n] and setting said current to a constant current.

[0069] Circuit WDD is electrically connected, for example, to wiring WD[1] through WD[n] and wiring WDr. Circuit WDD has the function of transmitting data to be stored in each memory cell of the memory cell array CA. For example, circuit WDD can transmit first data as said data to wiring WD[1] through WD[n] and reference data as said data to wiring WDr.

[0070] Circuit WLD is electrically connected to wiring WL[1] through WL[m], for example. Circuit WLD has the function of selecting the memory cell to which data will be written when writing data to a memory cell of the memory cell array CA. Specifically, when writing data to the i-th row (where i is an integer between 1 and m) of the memory cell array CA, circuit WLD can select the memory cell AM[i,1] through AM[i,n] or memory cell AMr[i] to write the data by applying a high-level potential to wiring WL[i] and a low-level potential to wiring WL[1] through WL[m] other than wiring WL[i].

[0071] Circuit XLD is electrically connected, for example, to wiring XL[1] to wiring XL[m]. Circuit XLD has the function of transmitting second data for multiplication with first data to each memory cell of the memory cell array CA. Specifically, for example, circuit XLD can apply a potential to wiring XL[1] to wiring XL[m] according to the second data.

[0072] Circuit ACTV is electrically connected, for example, to wiring BL[1] to wiring BL[n], wiring BLr, and wiring NIL[1] to wiring NIL[n]. Circuit ACTV has, for example, the function of inputting a predetermined voltage to wiring BL[1] to wiring BL[n] and wiring BLr. Circuit ACTV also has, for example, the function of outputting a voltage corresponding to the amount of current flowing from wiring BL[1] to circuit ACTV, the function of performing calculations according to a predefined set of functions using said voltage, and the function of outputting the result of the calculation of said functions to wiring NIL[1]. Circuit ACTV also has, for example, the function of converting the amount of current flowing from wiring BL[n] to circuit ACTV into a voltage, the function of performing calculations according to a predefined set of functions using said voltage, and the function of outputting the result of the calculation of said functions to wiring NIL[n].

[0073] In particular, predefined function sets for the ACTV circuit include, for example, the sigmoid function, tanh function, softmax function, ReLU function (ramp function), and threshold function. These functions can also be applied, for example, as activation functions in neural networks.

[0074] <<Example of ACTV circuit configuration>> Next, we will describe an example configuration of the ACTV circuit that can be applied to the MAC1 arithmetic circuit.

[0075] Figure 2 is a circuit diagram showing an example configuration of the ACTV circuit. The ACTV circuit, as an example, includes transistors Tr51[1] to Tr51[n], circuits IVC[1] to IVC[n], switches SW4A[1] to SW4A[n], switches SW4B[1] to SW4B[n], switches SW5[1] to SW5[n], and switch SW5r.

[0076] For each of the transistors Tr51[1] through Tr51[n], for example, a p-channel transistor can be used.

[0077] Furthermore, it is preferable that each of the transistors Tr51[1] through Tr51[n] has the same electrical characteristics as the others. To achieve this, for example, it is preferable that each of the transistors Tr51[1] through Tr51[n] has the same size (e.g., channel length, channel width, transistor configuration, etc.). By making the sizes of each of the transistors Tr51[1] through Tr51[n] equal, each of the transistors Tr51[1] through Tr51[n] can perform substantially the same operation under identical conditions. Here, identical conditions refer to, for example, the potentials of the source, drain, gate, etc., of each of the transistors Tr51[1] through Tr51[n].

[0078] Furthermore, unless otherwise specified, transistors Tr51[1] through Tr51[n] include cases where they operate in the saturation region when they are ON. That is, the gate, source, and drain of each of the transistors described above include cases where a voltage within the range of operation in the saturation region is appropriately input.

[0079] Furthermore, it is preferable to use transistors in which silicon is included in the channel formation region (hereinafter referred to as Si transistors) for each of the transistors Tr51[1] to Tr51[n]. In addition, the silicon can be, for example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or monocrystalline silicon.

[0080] Furthermore, instead of p-channel transistors, n-channel transistors may be used for each of the transistors Tr51[1] through Tr51[n]. Also, OS transistors may be used for each of the transistors Tr51[1] through Tr51[n].

[0081] Furthermore, each of the switches SW4A[1] to SW4A[n], SW4B[1] to SW4B[n], SW5[1] to SW5[n], and SW5r can be replaced with an electrical switch, such as an analog switch or a transistor. Alternatively, a mechanical switch may be used for each of the switches SW4A[1] to SW4A[n], SW4B[1] to SW4B[n], SW5[1] to SW5[n], and SW5r. When a transistor is used for each of the switches SW4A[1] to SW4A[n], SW4B[1] to SW4B[n], SW5[1] to SW5[n], and SW5r, the transistor can be an OS transistor or a Si transistor.

[0082] In this embodiment, each of the switches SW4A[1] to SW4A[n], SW4B[1] to SW4B[n], SW5[1] to SW5[n], and SW5r is configured to be ON when a high-level potential is input to the control terminal and OFF when a low-level potential is input.

[0083] The first terminal of switch SW4A[1] is electrically connected to the first terminal of switch SW5[1] and to wiring BL[1], and the second terminal of switch SW4A[1] is electrically connected to the first terminal of circuit IVC[1]. Also, since wiring BL[1] is electrically connected to one of the multiple first terminals of circuit ACTV, for example, the above statement "The first terminal of switch SW4A[1] is electrically connected to the first terminal of switch SW5[1] and to wiring BL[1]" can be rephrased as "The first terminal of switch SW4A[1] is electrically connected to the first terminal of switch SW5[1] and to one of the multiple first terminals of circuit ACTV." The second terminal of circuit IVC[1] is electrically connected to the first terminal of transistor Tr51[1], and the second terminal of transistor Tr51[1] is electrically connected to the first terminal of switch SW4B[1]. The second terminal of switch SW4B[1] is electrically connected to wiring NIL[1]. Furthermore, since wiring NIL[1] is electrically connected to one of the multiple second terminals of circuit ACTV, for example, the above statement "the second terminal of switch SW4B[1] is electrically connected to wiring NIL[1]" can be rephrased as "the second terminal of switch SW4B[1] is electrically connected to one of the multiple second terminals of circuit ACTV."

[0084] Similarly, the first terminal of switch SW4A[n] is electrically connected to the first terminal of switch SW5[n] and wiring BL[n], and the second terminal of switch SW4A[n] is electrically connected to the first terminal of circuit IVC[n]. Also, since wiring BL[n] is electrically connected to one of the plurality of first terminals of circuit ACTV as an example, the above "the first terminal of switch SW4A[n] is electrically connected to the first terminal of switch SW5[n] and wiring BL[n]" can be paraphrased as "the first terminal of switch SW4A[n] is electrically connected to the first terminal of switch SW5[n] and one of the plurality of first terminals of circuit ACTV". The second terminal of circuit IVC[n] is electrically connected to the first terminal of transistor Tr51[n], and the second terminal of transistor Tr51[n] is electrically connected to the first terminal of switch SW4B[n]. The second terminal of switch SW4B[n] is electrically connected to wiring NIL[n]. Also, since wiring NIL[n] is electrically connected to one of the plurality of second terminals of circuit ACTV as an example, the above "the second terminal of switch SW4B[n] is electrically connected to wiring NIL[n]" can be paraphrased as "the second terminal of switch SW4B[n] is electrically connected to one of the plurality of second terminals of circuit ACTV".

[0085] Also, the second terminal of each of switches SW5[1] to SW5[n] is electrically connected to wiring VSL, and the control terminal of each of switches SW5[1] to SW5[n] is electrically connected to wiring WE. Also, the gate of each of transistors Tr51[1] to Tr51[n] is electrically connected to wiring VBA. Also, the control terminal of each of switches SW4A[1] to SW4A[n] and switches SW4B[1] to SW4B[n] is electrically connected to wiring SL4.

[0086] Also, the first terminal of switch SW5r is electrically connected to wiring BLr, the second terminal of switch SW5r is electrically connected to wiring VSL, and the control terminal of switch SW5r is electrically connected to wiring WE.

[0087] Each of circuits IVC[1] to IVC[n] has a function of outputting a voltage corresponding to the amount of current input to the first terminal to the second terminal. That is, circuits IVC[1] to IVC[n] have a function as a current-voltage conversion circuit.

[0088] As an example, wiring VSL functions as wiring that supplies a constant voltage. The constant voltage can be, for example, a low-level potential, a ground potential, or the like.

[0089] As an example, wiring WE functions as wiring that supplies a voltage for switching between the conductive state and the non-conductive state of switches SW5[1] to SW5[n] and switch SW5r.

[0090] As an example, wiring SL4 functions as wiring that supplies a voltage for switching between the conductive state and the non-conductive state of switches SW4[1] to SW4[n].

[0091] As an example, wiring VBA functions as wiring that supplies a constant voltage.

[0092] Each of transistors Tr51[1] to Tr51[n] has a function of controlling, for example, the voltage between the first terminal and the second terminal of each of transistors Tr51[1] to Tr51[n]. Specifically, each of transistors Tr51[1] to Tr51[n] has a function of restricting the potential transferred from the second terminal of each of circuits IVC[1] to IVC[n] to the second terminal of each of transistors Tr51[1] to Tr51[n]. At this time, the voltage between the first terminal and the second terminal of each of transistors Tr51[1] to Tr51[n] is determined by the constant voltage supplied by wiring VBA and the potential of the first terminal of each of transistors Tr51[1] to Tr51[n].

[0093] Next, we will describe examples of circuit configurations that can be applied to circuits IVC[1] through IVC[n]. Circuit ACTV in Figure 3A shows the specific circuit configuration of circuits IVC[1] through IVC[n].

[0094] In the ACTV circuit of Figure 3A, circuit IVC[1] comprises a resistor RE[1] and an operational amplifier OP[1]. Similarly, circuit IVC[n] comprises a resistor RE[n] and an operational amplifier OP[n].

[0095] In circuit IVC[1], the inverting input terminal of operational amplifier OP[1] is electrically connected to the first terminal of circuit IVC[1] and the first terminal of resistor RE[1]. The non-inverting input terminal of operational amplifier OP[1] is electrically connected to wiring VdL. The output terminal of operational amplifier OP[1] is electrically connected to the second terminal of resistor RE[1] and the second terminal of circuit IVC[1].

[0096] Furthermore, in circuit IVC[n], the inverting input terminal of the operational amplifier OP[n] is electrically connected to the first terminal of circuit IVC[n] and the first terminal of resistor RE[n]. The non-inverting input terminal of the operational amplifier OP[n] is electrically connected to wiring VdL. The output terminal of the operational amplifier OP[n] is electrically connected to the second terminal of resistor RE[n] and the second terminal of circuit IVC[n].

[0097] Wiring VdL functions, for example, as wiring that provides a constant voltage. This constant voltage can be, for example, ground potential or low-level potential.

[0098] In other words, the ACTV circuit in Figure 3A consists of n current-voltage conversion circuits, each composed of resistors RE[1] through RE[n], operational amplifiers OP[1] through OP[n], and wiring VdL.

[0099] Furthermore, the circuit configurations applicable to circuits IVC[1] to IVC[n] are not limited to those shown in Figure 3A. For example, as shown in the circuit ACTV in Figure 3B, each of the resistors RE[1] to RE[n] in circuits IVC[1] to IVC[n] in Figure 3A may be replaced with loads LE[1] to LE[n]. For example, diodes, transistors, etc., may be used as loads LE[1] to LE[n], and even when these circuit elements are used, n current-voltage conversion circuits can be configured using loads LE[1] to LE[n] and operational amplifiers OP[1] to OP[n].

[0100] Next, we will explain a specific example of the ACTV circuit's operation. Here, we will describe the operation of the ACTV circuit shown in Figure 3A as an example.

[0101] In circuit ACTV, by inputting a high-level potential to wiring WE and wiring SL4, switches SW5[1] to SW5[n], SW4A[1] to SW4A[n], and SW4B[1] to SW4B[n] are each turned ON. As a result, the potential supplied by wiring VSL is applied to the first terminal of each of circuits IVC[1] to IVC[n].

[0102] The potential supplied by wiring VSL can be, for example, the initialization potential in each of circuits IVC[1] to IVC[n]. Therefore, a potential corresponding to the initialization potential is output from the second terminal of each of circuits IVC[1] to IVC[n]. Also, if current is flowing from wiring BL[j] (where j is an integer between 1 and n) to circuit ACTV, that current flows to the wiring VSL side.

[0103] Furthermore, in circuit ACTV, by inputting a high-level potential to wiring WE and a low-level potential to wiring SL4, switches SW5[1] to SW5[n] and SW5r are turned ON, and switches SW4A[1] to SW4A[n] and SW4B[1] to SW4B[n] are turned OFF. At this time, the potential supplied by wiring VSL is applied to wiring BL[1] to wiring BL[n] and wiring BLr.

[0104] Furthermore, in circuit ACTV, by inputting a low-level potential to wiring WE and a high-level potential to wiring SL4, switches SW5[1] through SW5[n] are turned off, and switches SW4A[1] through SW4A[n] and SW4B[1] through SW4B[n] are turned on. As a result, the first terminals of circuits IVC[1] through IVC[n] are connected to wirings BL[1] through BL[n].

[0105] At this time, a current I flows from the wiring BL[j] (where j is an integer between 1 and n) through the first terminal of the circuit IVC[j] to the resistor RE[j]. S Assume that current [j] flows. The operational amplifier OP[j] included in circuit IVC[j] has a negative feedback configuration via resistor RE[j], so let the resistance value of resistor RE[j] be R, and the potential supplied by the wiring VdL be V ref Let V be the potential of the second terminal of circuit IVC[j]. A When [j] is the potential, V A [j] can be expressed by the following formula:

[0106]

number

[0107] Also, potential V A[j] is input to the first terminal of transistor Tr51[j]. At this time, the potential output from the second terminal of transistor Tr51[j] is determined according to the potential provided by wiring VBA input to the gate of transistor Tr51[j] and the potential V A [j]. Let the potential provided by wiring VBA be V BIAS , let the threshold voltage of transistor Tr51[j] be V th , and let the potential output from the second terminal of transistor Tr51[j] be V OUT [j]. When the potential V OUT [j] is expressed by the following approximate formula.

[0108] [Equation]

[0109] Note that Equation (1.2) holds when V A [j] is greater than or equal to V BIAS +V th , and Equation (1.3) holds when V A [j] is less than V BIAS +V th .

[0110] From Equation (1.2) and Equation (1.3), the relationship between the potential input to the first terminal of transistor Tr51[i] and the potential output from the second terminal of transistor Tr51[i] can be regarded as the operation of the ReLU function (ramp function).

[0111] The ReLU function can be treated as, for example, the activation function of neurons included in the hierarchical neural network described in Embodiment 3. That is, by using circuit ACTV, the operation of the activation function in the hierarchical neural network can be performed.

[0112] [<<Configuration Example of Memory Cell>>] Next, we will explain an example of the configuration of memory cells AM[1,1] to AM[m,n] and memory cells AMr[1] to AMr[m] included in the memory cell array CA.

[0113] Figure 4 is a circuit diagram showing an example configuration of a memory cell array CA and a circuit CMS. The memory cell array CA and the circuit CMS have the function of calculating the sum of products of multiple first data and multiple second data.

[0114] In the memory cell array CA shown in Figure 4, each of the memory cells AM[1,1] to AM[m,n] and memory cells AMr[1] to AMr[m] has a transistor Tr11, a transistor Tr12, and a capacitor C1.

[0115] Furthermore, it is preferable that the sizes of the transistors Tr11 contained in memory cells AM[1,1] to AM[m,n] and memory cells AMr[1] to AMr[m] are equal. Also, it is preferable that the sizes of the transistors Tr12 contained in memory cells AM[1,1] to AM[m,n] and memory cells AMr[1] to AMr[m] are equal.

[0116] By making the sizes of transistors equal, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the size of transistor Tr11 contained in each of the memory cells AM[1,1] to AM[m,n] and AMr[1] to AMr[m] equal, and by making the size of transistor Tr12 contained in each of the memory cells AM[1,1] to AM[m,n] and AMr[1] to AMr[m] equal, each of the memory cells AM[1,1] to AM[m,n] and AMr[1] to AMr[m] can perform approximately the same operation under identical conditions. These identical conditions refer to, for example, the potentials of the source, drain, and gate of transistor Tr11, the potentials of the source, drain, and gate of transistor Tr12, and the voltages input to each of the memory cells AM[1,1] to AM[m,n] and AMr[1] to AMr[m].

[0117] Unless otherwise specified, transistor Tr11 includes cases where it functions as a switching element. That is, the gate, source, and drain of transistor Tr11 are appropriately supplied with voltages within the range in which transistor Tr11 operates as a switching element. Furthermore, transistor Tr11 may operate in the saturation region when it is ON, and may operate in a mixture of the linear region and the saturation region.

[0118] Furthermore, unless otherwise specified, transistor Tr12 is assumed to operate in the saturation region when it is ON. That is, the gate, source, and drain of each of the transistors described above are assumed to be appropriately supplied with voltages within the range that allows them to operate in the saturation region.

[0119] Furthermore, it is preferable that transistor Tr11 is an OS transistor. In addition, it is more preferable that the channel formation region of transistor Tr11 contains an oxide containing at least one of indium, gallium, and zinc. Alternatively, the channel formation region of transistor Tr11 may be an oxide containing at least one of indium, element M (for example, one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium), and zinc. Moreover, it is even more preferable that transistor Tr11 has the transistor structure described in Embodiment 4.

[0120] By using an OS transistor as transistor Tr11, the leakage current of transistor Tr11 can be suppressed, which can enable the realization of a multiply-accumulate operation circuit with high calculation accuracy. Furthermore, by using an OS transistor as transistor Tr11, the leakage current from the holding nodes (e.g., nodes N[1,1], N[m,1], N[1,n], N[m,n], Nr[1], Nr[m], etc., described later) to the write word lines (e.g., wiring WD[1] to wiring WD[n], wiring WDr, etc.) when transistor Tr11 is in a non-conducting state can be made very small. In other words, the refresh operation of the potential of the holding nodes can be reduced, thus reducing the power consumption of the multiply-accumulate operation circuit.

[0121] Furthermore, by using an OS transistor for transistor Tr12, it can be fabricated simultaneously with transistor Tr11, which may shorten the fabrication process for the multiply-accumulate circuit. Alternatively, transistor Tr12 may be a Si transistor instead of an OS transistor. Examples of silicon materials include amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, and monocrystalline silicon.

[0122] In Figure 4, back gates are shown for transistors Tr11 and Tr12. Although the connection configuration of these back gates is not shown, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor with a back gate, the gate and back gate may be electrically connected to increase the on-current of the transistor. That is, for example, the gate and back gate of transistor Tr11 may be electrically connected, or the gate and back gate of transistor Tr12 may be electrically connected. Alternatively, in a transistor with a back gate, for example, wiring may be provided to electrically connect the back gate of the transistor to an external circuit, etc., in order to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, thereby providing a potential to the back gate of the transistor through the external circuit, etc.

[0123] Furthermore, although transistors Tr11 and Tr12 shown in Figure 4 have back gates, the semiconductor device according to one embodiment of the present invention is not limited to this. For example, transistors Tr11 and Tr12 shown in Figure 4 may be configured without back gates, that is, single-gate transistors. Alternatively, some transistors may have back gates, while others may not.

[0124] Furthermore, although transistors Tr11 and Tr12 shown in Figure 4 are n-channel type transistors, the semiconductor device according to one aspect of the present invention is not limited to this. For example, some or all of transistors Tr11 and Tr12 may be replaced with p-channel type transistors.

[0125] The above examples of changes to the structure and polarity of transistors are not limited to transistors Tr11 and Tr12. For example, the same applies to transistors Tr33 and Tr34, which will be described later, as well as transistors described elsewhere in the specification or illustrated in other drawings.

[0126] In each of the memory cells AM[1,1] to [m,n] and memory cells AMr[1] to AMr[m], the first terminal of transistor Tr11 is electrically connected to the gate of transistor Tr12. The first terminal of transistor Tr12 is electrically connected to the wiring VR. The first terminal of capacitor C1 is electrically connected to the gate of transistor Tr12.

[0127] In memory cell AM[1,1], the second terminal of transistor Tr11 is electrically connected to wiring WD[1], and the gate of transistor Tr11 is electrically connected to wiring WL[1]. The second terminal of transistor Tr12 is electrically connected to wiring BL[1], and the second terminal of capacitor C1 is electrically connected to wiring XL[1]. In memory cell AM[1,1], the electrical connection point between the first terminal of transistor Tr11, the gate of transistor Tr12, and the first terminal of capacitor C1 is defined as node N[1,1].

[0128] In memory cell AM[m,1], the second terminal of transistor Tr11 is electrically connected to wiring WD[1], and the gate of transistor Tr11 is electrically connected to wiring WL[m]. The second terminal of transistor Tr12 is electrically connected to wiring BL[1], and the second terminal of capacitor C1 is electrically connected to wiring XL[m]. In memory cell AM[m,1], the electrical connection point between the first terminal of transistor Tr11, the gate of transistor Tr12, and the first terminal of capacitor C1 is defined as node N[m,1].

[0129] In memory cell AM[1,n], the second terminal of transistor Tr11 is electrically connected to wiring WD[n], and the gate of transistor Tr11 is electrically connected to wiring WL[1]. The second terminal of transistor Tr12 is electrically connected to wiring BL[n], and the second terminal of capacitor C1 is electrically connected to wiring XL[1]. In memory cell AM[1,n], the electrical connection point between the first terminal of transistor Tr11, the gate of transistor Tr12, and the first terminal of capacitor C1 is defined as node N[1,n].

[0130] In memory cell AM[m,n], the second terminal of transistor Tr11 is electrically connected to wiring WD[n], and the gate of transistor Tr11 is electrically connected to wiring WL[m]. The second terminal of transistor Tr12 is electrically connected to wiring BL[n], and the second terminal of capacitor C1 is electrically connected to wiring XL[m]. In memory cell AM[m,n], the electrical connection point between the first terminal of transistor Tr11, the gate of transistor Tr12, and the first terminal of capacitor C1 is defined as node N[m,n].

[0131] In the memory cell AMr[1], the second terminal of transistor Tr11 is electrically connected to wiring WDr, and the gate of transistor Tr11 is electrically connected to wiring WL[1]. The second terminal of transistor Tr12 is electrically connected to wiring BLr, and the second terminal of capacitor C1 is electrically connected to wiring XL[1]. In memory cell AMr[1], the electrical connection point between the first terminal of transistor Tr11, the gate of transistor Tr12, and the first terminal of capacitor C1 is defined as node Nr[1]. In addition, the current flowing from wiring BLr to the second terminal of transistor Tr12 is defined as I AMr[1] Let's assume that.

[0132] In memory cell AMr[m], the second terminal of transistor Tr11 is electrically connected to wiring WDr, and the gate of transistor Tr11 is electrically connected to wiring WL[m]. The second terminal of transistor Tr12 is electrically connected to wiring BLr, and the second terminal of capacitor C1 is electrically connected to wiring XL[m]. In memory cell AMr[m], the electrical connection point between the first terminal of transistor Tr11, the gate of transistor Tr12, and the first terminal of capacitor C1 is defined as node Nr[m]. In addition, the current flowing from wiring BLr to the second terminal of transistor Tr12 is defined as I AMr[2] Let's assume that.

[0133] The aforementioned nodes N[1], N[m], Nr[1], and Nr[m] function as memory cell holding nodes.

[0134] The VR wiring is for conducting current between the first and second terminals of the transistor Tr12 of each memory cell AM[1,1] to AM[m,n] and memory cell AMr[1] to AMr[m]. Therefore, the VR wiring functions as wiring for supplying a predetermined potential. In this embodiment, the potential supplied by the VR wiring can be, for example, a low-level potential, a ground potential, or a potential lower than the ground potential.

[0135] <<Example of Circuit CMS Configuration>> Next, we will describe an example of a circuit CMS configuration.

[0136] In Figure 4, circuit CMS includes circuits CS1[1] to CS1[n], circuits CS2[1] to CS2[n], circuit CM, switches SW3[1] to SW3[n], switches SW7[1] to SW7[n], and switch SW7r.

[0137] Furthermore, the control terminals of switches SW3[1] through SW3[n] are electrically connected to wiring SL3. Also, the control terminals of switches SW7[1] through SW7[n] and SW7r are electrically connected to wiring SL7.

[0138] Furthermore, the first terminals of switches SW7[1] through SW7[n] are electrically connected to the wirings BL[1] through BL[n], respectively. Also, the first terminal of switch SW7r is electrically connected to the wiring BLr.

[0139] Wiring SL3 functions as wiring that supplies voltage to switch the conduction state and non-conduction state of switches SW3[1] through SW3[n], respectively. Wiring SL7 also functions as wiring that supplies voltage to switch the conduction state and non-conduction state of switches SW7[1] through SW7[n] and switch SW7r, respectively.

[0140] Each of circuits CS1[1] through CS1[n] functions, for example, as a current source circuit that supplies a constant current. Furthermore, as will be described in more detail later, each of circuits CS1[1] through CS1[n] has a function to set the amount of the constant current.

[0141] Each of circuits CS1[1] through CS1[n] includes a p-channel transistor Tr33, a capacitor C6, and a switch SW1.

[0142] Furthermore, it is preferable that transistor Tr33 is a Si transistor. In addition, the silicon included in the channel formation region of transistor Tr33 can be, for example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or monocrystalline silicon.

[0143] Furthermore, it is preferable that the transistors Tr33 included in each of circuits CS1[1] to CS1[n] have the same electrical characteristics. To achieve this, for example, it is preferable that the transistors Tr33 in each of circuits CS1[1] to CS1[n] have the same size.

[0144] Furthermore, unless otherwise specified, each transistor Tr33 in circuits CS1[1] to CS1[n] includes the case where it operates in the saturation region when it is ON. That is, the gate, source, and drain of each of the transistors described above include the case where a voltage within the range in which it operates in the saturation region is appropriately input.

[0145] In each of circuits CS1[1] to CS1[n], the first terminal of transistor Tr33 is electrically connected to wiring VHE, the gate of transistor Tr33 is electrically connected to the first terminal of capacitor C6 and the first terminal of switch SW1, and the second terminal of transistor Tr33 is electrically connected to the second terminal of switch SW1. The second terminal of capacitor C6 is also electrically connected to wiring VHE. The control terminal of switch SW1 is also electrically connected to wiring SL1.

[0146] In circuit CS1[1], the second terminal of transistor Tr33 and the second terminal of switch SW1 are electrically connected to the first terminal of switch SW3[1] and the second terminal of switch SW7[1].

[0147] In circuit CS1[n], the second terminal of transistor Tr33 and the second terminal of switch SW1 are electrically connected to the first terminal of switch SW3[n] and the second terminal of switch SW7[n].

[0148] Wiring VHE functions as wiring that provides a constant voltage. Preferably, this constant voltage is, for example, a high-level potential.

[0149] Wiring SL1 functions as wiring that supplies voltage to switch the conduction state and non-conduction state of each switch SW1 in circuits CS1[1] to CS1[n].

[0150] Each of circuits CS1[1] through CS1[n] has the function of keeping the amount of current flowing between the source and drain of transistor Tr33 constant, even if the source-drain voltage of transistor Tr33 changes. Specifically, in each of circuits CS1[1] through CS1[n], switch SW1 is turned ON to configure transistor Tr33 in a diode connection. At this time, a current flows between the source and drain of transistor Tr33 corresponding to the source-drain (gate) voltage of transistor Tr33. Also, the gate potential of transistor Tr33 becomes approximately equal to the drain potential. Here, by turning switch SW1 OFF and holding the gate potential of transistor Tr33 by the first terminal of capacitor C6, the gate-source voltage of transistor Tr33 can be kept constant. Therefore, when transistor Tr33 operates in the saturation region, even if the drain potential changes, the amount of current flowing between the source and drain can be kept constant, remaining the same as the current flowing when switch SW1 is ON.

[0151] In this specification, the process of temporarily configuring a transistor in a diode connection, making the gate potential of the transistor approximately equal to the drain potential, and then making the gate and drain of the transistor non-conductive to maintain a constant source-drain current is described as "setting (programming) the amount of current flowing between the source and drain of the transistor to the transistor." Furthermore, when the transistor is included in a circuit, as in circuits CS1[1] to CS1[n], it is described as "setting (programming) the amount of current flowing through the circuit to the circuit," or "setting (programming) the amount of current flowing out of the circuit (current flowing into the circuit) to the circuit."

[0152] Each of circuits CS2[1] through CS2[n] functions, for example, as a current source circuit that supplies a constant current. Furthermore, each of circuits CS2[1] through CS2[n], like each of circuits CS1[1] through CS1[n], has the function of setting the amount of the constant current.

[0153] Each of circuits CS2[1] through CS2[n] includes a transistor Tr34, which is an n-channel transistor, a capacitor C7, and a switch SW2.

[0154] Furthermore, transistor Tr34 can be replaced with, for example, an OS transistor or Si transistor, which can be used for transistor Tr11. In addition, when a Si transistor is used for transistor Tr34, the silicon included in the channel formation region of transistor Tr34 can be, for example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or monocrystalline silicon.

[0155] Furthermore, it is preferable that the transistors Tr34 included in each of circuits CS2[1] to CS2[n] have the same electrical characteristics. To achieve this, for example, it is preferable that the transistors Tr34 in circuits CS2[1] to CS2[n] have the same size.

[0156] Furthermore, unless otherwise specified, each transistor Tr34 in circuits CS2[1] to CS2[n] includes the case where it operates in the saturation region when it is ON. That is, the gate, source, and drain of each of the transistors described above include the case where a voltage within the range in which it operates in the saturation region is appropriately input.

[0157] In each of circuits CS2[1] to CS2[n], the first terminal of transistor Tr34 is electrically connected to the wiring VLE, ​​the gate of transistor Tr34 is electrically connected to the first terminal of capacitor C7 and the first terminal of switch SW2, and the second terminal of transistor Tr34 is electrically connected to the second terminal of switch SW2. The second terminal of capacitor C7 is also electrically connected to the wiring VLE. The control terminal of switch SW2 is also electrically connected to the wiring SL2.

[0158] In circuit CS2[1], the second terminal of transistor Tr34 and the second terminal of switch SW2 are electrically connected to the second terminal of switch SW3[1].

[0159] In circuit CS2[n], the second terminal of transistor Tr34 and the second terminal of switch SW2 are electrically connected to the second terminal of switch SW3[n].

[0160] The VLE wiring functions as wiring that provides a constant voltage. Preferably, this constant voltage is, for example, a low-level potential.

[0161] Wiring SL2 functions as wiring that supplies voltage to switch the conduction state and non-conduction state of each switch SW2 in circuits CS2[1] to CS2[n].

[0162] Each of circuits CS2[1] through CS2[n], for example, has the function of keeping the amount of current flowing between the source and drain of transistor Tr34 constant even when the source-drain voltage of transistor Tr34 changes, similar to each of circuits CS1[1] through CS1[n]. Specifically, in each of circuits CS2[1] through CS2[n], switch SW2 is turned ON to configure transistor Tr34 in a diode connection. At this time, a current flows between the source and drain of transistor Tr34 corresponding to the source-drain (gate) voltage of transistor Tr34. Also, the gate potential of transistor Tr34 becomes approximately equal to the drain potential. Here, by turning switch SW2 OFF and holding the gate potential of transistor Tr34 by the first terminal of capacitor C7, the gate-source voltage of transistor Tr34 can be kept constant. Therefore, when transistor Tr34 operates in the saturation region, even if the drain potential changes, the amount of current flowing between the source and drain can be kept constant, remaining the same as the current flowing when switch SW2 is ON.

[0163] Circuit CM functions, for example, as a current mirror circuit. Circuit CM includes, as an example, transistor Tr31 and transistors Tr32[1] to Tr32[n].

[0164] Furthermore, in order for the circuit CM to function as a current mirror circuit, it is preferable that transistors Tr31 and Tr32[1] through Tr32[n] each have the same electrical characteristics. For this purpose, for example, it is preferable that transistors Tr31 and Tr32[1] through Tr32[n] each have the same size.

[0165] Furthermore, unless otherwise specified, each of transistors Tr31 and Tr32[1] through Tr32[n] is assumed to operate in the saturation region when turned on. That is, the gate, source, and drain of each of the above-mentioned transistors are assumed to be appropriately supplied with voltages within the range that allows them to operate in the saturation region.

[0166] The first terminals of transistors Tr31 and Tr32[1] through Tr32[n] are electrically connected to the wiring VHE. The second terminal of transistor Tr31 is electrically connected to the gate of transistor Tr31, to the gates of transistors Tr31[1] through Tr31[n], and to the second terminal of switch SW7r.

[0167] The second terminal of transistor Tr32[1] is electrically connected to the second terminal of switch SW3[1], the second terminal of transistor Tr34 in circuit CS2[1], and the second terminal of switch SW2 in circuit CS2[1]. Additionally, the second terminal of transistor Tr32[n] is electrically connected to the second terminal of switch SW3[n], the second terminal of transistor Tr34 in circuit CS2[n], and the second terminal of switch SW2 in circuit CS2[n].

[0168] By configuring the circuit CM as shown in Figure 4, it is possible to flow approximately the same amount of current between the first and second terminals of transistors Tr32[1] to Tr32[n] as the current flowing between the first and second terminals of transistor Tr31.

[0169] Switches SW1, SW2, SW3[1] to SW3[n], SW7[1] to SW7[n], and SW7r can be, for example, electrical switches such as analog switches or transistors. Alternatively, switches SW1, SW2, SW3[1] to SW3[n], SW7[1] to SW7[n], and SW7r can be, for example, mechanical switches. When transistors are used for switches SW1, SW2, SW3[1] to SW3[n], SW7[1] to SW7[n], and SW7r, the transistors can be OS transistors or Si transistors.

[0170] Furthermore, the configuration of circuit CM is not limited to the configuration shown in Figure 4. For example, the configuration of circuit CM may be as shown in circuit CM in Figure 5, in which transistors Tr31 and Tr35 are cascode-connected, and each of transistors Tr32[1] to Tr32[n] is cascode-connected to each of transistors Tr36[1] to Tr36[n]. As shown in circuit CM in Figure 5, by cascode-connecting the transistors included in the current mirror circuit, the operation of the current mirror circuit can be made more stable.

[0171] In this embodiment, each of switches SW1, SW2, SW3[1] to SW3[n], SW7[1] to SW7[n], and SW7r is configured to be ON when a high-level potential is input to the control terminal and OFF when a low-level potential is input.

[0172] <Example of operation of the arithmetic circuit> Next, we will explain an example of the operation of the MAC1 arithmetic circuit.

[0173] Figure 6 shows a timing chart of an example of the operation of the arithmetic circuit MAC1. The timing chart in Figure 6 shows the potential fluctuations of wiring WL[1], wiring WL[2], wiring WL[m] (in this example, m is an integer of 4 or more), wiring SL1, wiring SL2, wiring SL3, wiring SL4, wiring SL7, wiring WE, wiring WD[1], wiring WDr, node N[1,1], node N[2,1], node N[m,1], node Nr[1], node Nr[2], node Nr[m], wiring XL[1], wiring XL[2], and wiring XL[m] at times T01 to T14 and in the vicinity thereof. In Figure 6, high-level potentials are denoted as High and low-level potentials are denoted as Low.

[0174] In this example, the voltage supplied by the wiring VR is considered to be the ground potential.

[0175] <<From time T01 to time T02>> Between time T01 and time T02, a high-level potential is input to wiring WE. As a result, switches SW5[1] through SW5[n] and switch SW5r included in circuit ACTV are turned ON.

[0176] When switches SW5[1] through SW5[n] and SW5r are turned ON, conduction occurs between each of the wires BL[1] through BL[n] and BLr and the wire VSL, and an initialization potential is supplied to each of the wires BL[1] through BL[n] and BLr from the wire VSL. In this example of operation, the initialization potential supplied by the wire VSL is set to the ground potential.

[0177] Furthermore, a high-level potential is input to wiring SL4 between time T01 and time T02. As a result, switches SW4A[1] through SW4A[n] and switches SW4B[1] through SW4B[n] included in circuit ACTV are turned ON.

[0178] When switches SW4A[1] through SW4A[n] are turned ON, the ground potential is supplied to the first terminal of each circuit IVC[1] through IVC[n] from the wiring VSL. In addition, in this example of operation, by setting the potential supplied by the wiring VdL as the ground potential, a potential of 0V is output from the second terminal of each circuit IVC[1] through IVC[n].

[0179] Furthermore, a low-level potential is input to wiring WL[1] through wiring WL[m] between time T01 and time T02.

[0180] Furthermore, between time T01 and time T02, a low-level potential is input to wiring SL1 through SL3 and wiring SL7. As a result, in circuit CMS, switch SW1 included in circuits CS1[1] through CS1[n], switch SW2 included in circuits CS2[1] through CS2[n], switch SW3[1] through switch SW3[n], switch SW7[1] through switch SW7[n], and switch SW7r are all in the OFF state.

[0181] Furthermore, between time T01 and time T02, the ground potential (labeled GND in Figure 6) is input to wiring WD[1] and wiring WDr.

[0182] Furthermore, between time T01 and time T02, each of the wires XL[1] through XL[m] is supplied with voltage from circuit XLD. Here, for example, the voltage supplied from circuit XLD to each of the wires XL[1] through XL[m] is set to a reference potential (V in Figure 6). RFP It is written as follows.

[0183] Furthermore, between time T01 and time T02, the potentials of nodes N[1,1] through N[m,n] and the potentials of nodes Nr[1] through Nr[m] are set to the ground potential (indicated as GND in Figure 6).

[0184] <<From time T02 to time T03>> Between time T02 and time T03, a low-level potential is input to wiring SL4. As a result, switches SW4A[1] through SW4A[n] and switches SW4B[1] through SW4B[n] included in circuit ACTV are turned off.

[0185] As a result, no current flows from each of the wirings BL[1] to BL[n] to the respective first terminals of the first terminals of the circuits IVC[1] to IVC[n]. Therefore, changes in the potential of the first terminals of the circuits IVC[1] to IVC[n] due to changes in the potential of each of the wirings BL[1] to BL[n] can be suppressed. This completes the initialization of the circuits IVC[1] to IVC[n].

[0186] Furthermore, between time T02 and time T03, a high-level potential is continuously input to wiring WE, as it was before time T02. Also, between time T02 and time T03, a low-level potential is continuously input to wirings SL1, SL2, SL3, SL4, and SL7, as it was before time T02.

[0187] <<From time T03 to time T04>> Between time T03 and time T04, a high-level potential is input to wiring WL[1]. As a result, a high-level potential is applied to the gates of transistors Tr11 contained in memory cells AM[1,1] to AM[1,n] and memory cell AMr[1] in the memory cell array CA, causing each of the transistors Tr11 to turn ON.

[0188] Furthermore, between time T03 and time T04, the wiring WD[1] has a potential higher than ground potential. PR -V W[1,1]A large potential is input. At this time, the transistor Tr11 of memory cell AM[1,1] is ON, so the connection between wiring WD[1] and node N[1,1] becomes conductive, and the first terminal (node ​​N[1,1]) of the capacitance C1 of memory cell AM[1,1] has a potential higher than ground potential. PR -V W[1,1] A large potential is input.

[0189] Note that in this example of operation, V PR V is the potential corresponding to the reference data. W[1,1] This is the potential corresponding to the first data held in memory cell AM[1,1].

[0190] Furthermore, between time T03 and time T04, the wiring WDr has a potential higher than ground potential. PR A large potential is input. At this time, the transistor Tr11 of memory cell AMr[1] is ON, so the connection between the wiring WDr and node Nr[1] becomes conductive, and the first terminal (node ​​Nr[1]) of the capacitance C1 of memory cell AMr[1] has a potential higher than ground potential. PR A large potential is input.

[0191] Furthermore, since switches SW5[1] to SW5[n] are in the ON state, the ground potential is input to each of the wirings BL[1] to BL[n]. Also, in memory cells AM[1,1] to AM[m,n], the ground potential from wiring VR is input to the first terminal of transistor Tr12, so the voltage between the first and second terminals of transistor Tr12 is approximately 0V. For this reason, no current flows between the first and second terminals of transistor Tr12 in each of the memory cells AM[1,1] to AM[m,n].

[0192] Furthermore, since switch SW5r is also in the ON state, the ground potential is input to the wiring BLr. Also, in memory cells AMr[1] to AMr[m], the ground potential from wiring VR is input to the first terminal of transistor Tr12, so the voltage between the first and second terminals of transistor Tr12 is approximately 0V. For this reason, no current flows between the first and second terminals of transistor Tr12 in each of memory cells AMr[1] to AMr[m].

[0193] Furthermore, between time T03 and time T04, transistor Tr11 of memory cells AM[1,2] to AM[1,n] is also ON. At this timing, by inputting the first data from each of the wirings WD[2] to WD[n] to memory cells AM[1,2] to AM[1,n], a potential corresponding to the first data can be written to nodes N[1,2] to N[1,n]. Note that in this example of operation, we will focus on memory cells AM[1,1] to AM[m,1] electrically connected to wiring WD[1] and memory cells AMr[1] to AMr[m] electrically connected to wiring WDr, and will omit the description of the operation of other memory cells.

[0194] Furthermore, between time T03 and time T04, a low-level potential is continuously applied to wiring WL[2] through wiring WL[m], as it was before time T03. As a result, a low-level potential is applied to the gates of transistors Tr11 in each of the memory cells AM[2,1] through memory cells AM[m,1] and AMr[2] through memory cells AMr[m] located in rows 2 through m of the memory cell array CA, and each of the transistors Tr11 is in the off state. Consequently, the data input to wiring WD[1] and wiring WDr is not written to nodes N[2,1] through nodes N[m,1] and nodes Nr[2] through nodes Nr[m].

[0195] <<From time T04 to time T05>> Between time T04 and time T05, a low-level potential is input to wiring WL[1]. As a result, a low-level potential is applied to the gates of transistors Tr11 in each of the memory cells AM[1,1] through AM[1,n] and AMr[1] in the memory cell array CA, causing each transistor Tr11 to turn off.

[0196] In memory cell AM[1,1], when transistor Tr11 is turned off, the first terminal (node ​​N[1,1]) of the capacitance C1 of memory cell AM[1,1] becomes V11 higher than ground potential. PR -V W[1,1] A large potential is maintained. Also, in memory cell AMr[1], when transistor Tr11 is turned off, the first terminal (node ​​Nr[1]) of the capacitance C1 of memory cell AMr[1] has a potential higher than ground potential. PR A high potential is maintained.

[0197] <<From time T05 to time T06>> Between time T05 and time T06, a high-level potential is input to wiring WL[2]. As a result, a high-level potential is applied to the gates of transistors Tr11 contained in memory cells AM[2,1] through AM[2,n] and memory cell AMr[2] in the memory cell array CA, causing each of the transistors Tr11 to turn ON.

[0198] Furthermore, between time T05 and time T06, the wiring WD[1] has a potential higher than ground potential. PR -V W[2,1] A large potential is input. At this time, the transistor Tr11 of memory cell AM[2,1] is ON, so the connection between wiring WD[1] and node N[2,1] becomes conductive, and the first terminal (node ​​N[2,1]) of capacitance C1 of memory cell AM[2,1] has a potential higher than ground potential. PR -V W[2,1] A large potential is input.

[0199] Note that in this example of operation, V W[2,1] This is the potential corresponding to the first data held in memory cell AM[2,1].

[0200] Furthermore, between time T05 and time T06, the wiring WDr has a potential higher than ground potential. PR A large potential is input. At this time, the transistor Tr11 of memory cell AMr[2] is ON, so the connection between the wiring WDr and node Nr[2] becomes conductive, and the first terminal (node ​​Nr[2]) of the capacitance C1 of memory cell AMr[2] has a potential higher than ground potential. PR A large potential is input.

[0201] Furthermore, between time T05 and time T06, a low-level potential is continuously applied to wiring WL[1] and wiring WL[3] through wiring WL[m], as it was before time T05. As a result, a low-level potential is applied to the gates of transistors Tr11 in each of the memory cells AM[1,1], AM[3,1] through AM[m,1], AMr[1], and AMr[3] through AMr[m] located in the first row and rows 3 through m of the memory cell array CA, and each of the transistors Tr11 is in the off state. Consequently, the data input to wiring WD[1] and wiring WDr is not written to nodes N[1,1], N[3,1] through N[m,1], Nr[1], and Nr[3] through Nr[m].

[0202] <<From time T06 to time T07>> Between time T06 and time T07, a low-level potential is input to wiring WL[2]. As a result, a low-level potential is applied to the gates of transistors Tr11 in each of the memory cells AM[2,1] through AM[2,n] and AMr[2] in the memory cell array CA, causing each transistor Tr11 to turn off.

[0203] In memory cell AM[2,1], when transistor Tr11 is turned off, the first terminal (node ​​N[2,1]) of the capacitance C1 of memory cell AM[2,1] becomes V12 higher than ground potential. PR -V W[2,1] A large potential is maintained. Also, in memory cell AMr[2], when transistor Tr11 is turned off, the first terminal (node ​​Nr[2]) of the capacitance C1 of memory cell AMr[2] has a potential higher than ground potential. PR A high potential is maintained.

[0204] <<From time T07 to time T08>> Between time T07 and time T08, similar to the operations between time T03 and time T04, and between time T05 and time T06 described above, a potential corresponding to the first data is maintained at the first terminal of the capacitance C1 of each memory cell AM[3,1] to AM[m-1,n]. Specifically, for example, at the first terminal of the capacitance C1 of memory cell AM[3,1] (node ​​N[3,1]), a potential V higher than ground potential is maintained. PR -V W[3,1] A high potential is maintained, and the first terminal (node ​​N[m-1,1]) of the capacitance C1 of memory cell AM[m-1,1] has a potential higher than ground potential. PR -V W[m-1,1] A high potential is maintained.

[0205] Note that in this example of operation, V W[3,1] V is the potential corresponding to the first data held in memory cell AM[3,1], W[m-1,1] This is the potential corresponding to the first data stored in memory cell AM[m-1,1].

[0206] <<From time T08 to time T09>> Between time T08 and time T09, a high-level potential is input to wiring WL[m]. As a result, a high-level potential is applied to the gates of transistors Tr11 contained in memory cells AM[m,1] through AM[m,n] and AMr[m] in the memory cell array CA, causing each of the transistors Tr11 to turn ON.

[0207] Furthermore, between time T08 and time T09, the wiring WD[1] has a potential higher than ground potential. PR -V W[m,1] A large potential is input. At this time, the transistor Tr11 of memory cell AM[m,1] is ON, so the connection between wiring WD[1] and node N[m,1] becomes conductive, and the first terminal (node ​​N[m,1]) of capacitance C1 of memory cell AM[m,1] has a potential higher than ground potential. PR -V W[m,1] A large potential is input.

[0208] Note that in this example of operation, V W[m,1] This is the potential corresponding to the first data held in memory cell AM[m,1].

[0209] Furthermore, between time T08 and time T09, the wiring WDr has a potential higher than ground potential. PR A large potential is input. At this time, the transistor Tr11 of the memory cell AMr[m] is ON, so the connection between the wiring WDr and node Nr[m] becomes conductive, and the first terminal (node ​​Nr[m]) of the capacitance C1 of the memory cell AMr[m] has a potential higher than ground potential. PR A large potential is input.

[0210] Furthermore, between time T08 and time T09, a low-level potential is continuously applied to wiring WL[1] through wiring WL[m-1], as it was before time T08. As a result, in the memory cell array CA, a low-level potential is applied to the gates of transistors Tr11 contained in each of the memory cells AM[1,1] through memory cells AM[m-1,1] and AMr[1] through memory cells AMr[m-1] located from row 1 to row m-1, and each of the transistors Tr11 is in the off state. Consequently, the data input to wiring WD[1] and wiring WDr is not written to nodes N[1,1] through nodes N[m-1,1] and Nr[1] through nodes Nr[m-1].

[0211] <<From time T09 to time T10>> Between time T09 and time T10, a low-level potential is input to wiring WL[m]. As a result, a low-level potential is applied to the gates of transistors Tr11 contained in memory cells AM[m,1] through AM[m,n] and AMr[m] in the memory cell array CA, causing each of the transistors Tr11 to turn off.

[0212] In memory cell AM[m,1], when transistor Tr11 is turned off, the first terminal (node ​​N[m,1]) of the capacitance C1 of memory cell AM[m,1] becomes V12 higher than ground potential. PR -V W[m,1] A large potential is maintained. Also, in memory cell AMr[m], when transistor Tr11 is turned off, the first terminal (node ​​Nr[m]) of the capacitance C1 of memory cell AMr[m] becomes V higher than ground potential. PR A high potential is maintained.

[0213] <<From time T10 to time T11>> Between time T10 and time T11, a low-level potential is input to wiring WE. As a result, switches SW5[1] through SW5[n] and SW5r in circuit ACTV are turned off.

[0214] <<From time T11 to time T12>> Between time T11 and time T12, a high-level potential is input to wiring SL1, wiring SL2, and wiring SL7. As a result, in circuit CMS, switches SW1 included in circuits CS1[1] through CS1[n], switches SW2 included in circuits CS2[1] through CS2[n], switches SW7[1] through SW7[n], and switches SW7r are turned ON.

[0215] At this time, each of the memory cells AM[1,1] through AM[m,1] becomes conductive with the circuit CS1[1] included in the circuit CMS via the wiring BL[1]. Also, each of the memory cells AMr[1] through AMr[m] becomes conductive with the circuit CM included in the circuit CMS via BLr.

[0216] Here, we consider the current flowing from the second terminal to the first terminal of each transistor Tr12 in memory cell AM[1,1] to memory cell AM[m,1].

[0217] For example, the current flowing from the wiring BL to the first terminal of the memory cell AM[1,1] via the second terminal of transistor Tr12 is I AM[1,1],1 In that case, I AM[1,1],1 It can be expressed by the following formula.

[0218]

number

[0219] k is a constant determined by the channel length, channel width, mobility, and gate dielectric capacitance of transistor Tr12. thV is the threshold voltage of transistor Tr12. The constant k is applicable not only to memory cell AM[1,1] but also to other memory cells AM and AMr. Furthermore, the threshold voltage of transistor Tr12 in other memory cells AM and AMr, not just AM[1,1], is also V. th Let's assume that.

[0220] Furthermore, for example, the current flowing from the wiring BL to the first terminal of the memory cell AM[2,1] via the second terminal of transistor Tr12 is I AM[2,1],1 In that case, I AM[2,1],1 It can be expressed by the following formula.

[0221]

number

[0222] Furthermore, for example, the current flowing from the wiring BL to the first terminal of the memory cell AM[m,1] via the second terminal of transistor Tr12 is I AM[m,1],1 In that case, I AM[m,1],1 It can be expressed by the following formula.

[0223]

number

[0224] Here, we consider the current flowing between the first and second terminals of transistor Tr33 in circuit CS1[1], which is included in circuit CMS. In this example, the amount of this current will be denoted as I1.

[0225] Between time T11 and time T12, switch SW1 of circuit CS1[1] is ON, switch SW3[1] is OFF, switch SW7[1] is ON, and switch SW4A[1] of circuit AVTC is OFF. Therefore, the amount of current I1 flowing between the first and second terminals of transistor Tr33 of circuit CS1[1] can be described by Kirchhoff's laws as follows:

[0226]

number

[0227] Furthermore, the transistor Tr33 in circuit CS1[1] is configured with diode connections, and the first terminal of transistor Tr33 in circuit CS1[1] is electrically connected to wiring VHE, which provides a constant high-level potential. Therefore, the potential of the gate (second terminal) of transistor Tr33 in circuit CS1[1] is determined by the amount of current I1 flowing between the first and second terminals of transistor Tr33.

[0228] Next, we consider the current flowing from the second terminal to the first terminal of each transistor Tr12 in memory cell AMr[1] to memory cell AMr[m].

[0229] For example, the current flowing from the wiring BLr to the first terminal of the memory cell AMr[1] via the second terminal of transistor Tr12 is I AMr[1],2 In that case, similarly, I AMr[1],2 It can be expressed by the following formula.

[0230]

number

[0231] Furthermore, for example, the current flowing from the wiring BLr to the first terminal of the memory cell AMr[2] via the second terminal of transistor Tr12 is I AMr[2],2 In that case, similarly, I AMr[2],2 It can be expressed by the following formula.

[0232]

number

[0233] Furthermore, for example, the current flowing from the wiring BLr to the first terminal of the memory cell AMr[m] via the second terminal of transistor Tr12 is I AMr[m],2 In that case, similarly, IAMr[m],2 It can be expressed by the following formula.

[0234]

number

[0235] Here, we consider the current flowing between the first and second terminals of transistor Tr34 in circuit CS2[1], which is included in circuit CMS. In this example, the amount of this current will be denoted as I2.

[0236] Between time T11 and time T12, switch SW2 of circuit CS2[1] is ON, switch SW3[1] is OFF, and switch SW7r is ON. Therefore, the amount of current flowing between the first and second terminals of transistor Tr34 in circuit CS2[1] is approximately equal to the amount of current flowing between the first and second terminals of transistor Tr32[1].

[0237] Furthermore, since the circuit CM is configured as a current mirror circuit, the amount of current flowing between the first and second terminals of transistor Tr32[1] is approximately equal to the amount of current flowing between the first and second terminals of transistor Tr31.

[0238] Since the amount of current flowing between the first and second terminals of transistor Tr31 is the sum of the currents flowing from the wiring BLr to the memory cells AMr[1] to AMr[m], the amount of current I2 flowing between the first and second terminals of transistor Tr34 in circuit CS2[1] can be described by the following equation.

[0239]

number

[0240] Furthermore, the transistor Tr34 in circuit CS2[1] is configured with diode connections, and a wiring VLE that provides a high-level potential as a constant voltage is electrically connected to the first terminal of transistor Tr34 in circuit CS2[1]. Therefore, the potential of the gate (second terminal) of transistor Tr34 in circuit CS2[1] is determined by the amount of current I2 flowing between the first and second terminals of transistor Tr34.

[0241] <<From time T12 to time T13>> Between time T12 and time T13, a low-level potential is input to wiring SL1 and wiring SL2. As a result, in circuit CMS, switch SW1 included in each of circuits CS1[1] through CS1[n] is turned off, and switch SW2 included in each of circuits CS2[1] through CS2[n] is turned off.

[0242] Therefore, between time T12 and time T13, the gate potential of transistor Tr33 in circuit CS1[1] is maintained by the first terminal of capacitor C6, and the gate potential of transistor Tr34 in circuit CS2[1] is maintained by the first terminal of capacitor C7. As a result, the gate-source voltage of transistor Tr33 in circuit CS1[1] is maintained, and a current I1 is always set to flow between the first and second terminals of transistor Tr33. Similarly, the gate-source voltage of transistor Tr34 in circuit CS2[1] is maintained, and a current I2 is always set to flow between the first and second terminals of transistor Tr34. In other words, circuit CS[1] is set to have a current I1 flowing out of circuit CS[1], and circuit CS2[1] is set to have a current I2 flowing into circuit CS2[1].

[0243] <<From time T13 to time T14>> Between time T13 and time T14, a high-level potential is input to wiring SL3 and wiring SL4. As a result, switches SW3[1] through SW3[n] in circuit CMS are turned ON. Also, switches SW4A[1] through SW4A[n] and SW4B[1] through SW4B[n] in circuit ACTV are turned ON.

[0244] Furthermore, between time T13 and time T14, a potential corresponding to the second data is input to each of the wires XL[1] through XL[m]. Here, for example, the potential input from circuit RPC[1] to wire XL[1] is set to be V higher than the ground potential. RFP +V X[1] The potential is set to be high, and the potential input from circuit RPC[2] to wiring XL[2] is set to be V higher than the ground potential. RFP +V X[2] Assuming a high potential, the potential input from circuit RPC[m] to wiring XL[m] is set to V higher than the ground potential. RFP +V X[m] Set the potential to high.

[0245] In this example of operation, the potential V X[1] ~V X[m] This is the potential corresponding to the second data point.

[0246] Between time T13 and time T14, the potential of wiring XL[1] is the reference potential V RFP From V RFP +V X[1] As the temperature rises, the second terminal of the respective capacitance C1 of memory cell AM[1] and memory cell AMR[1] has V RFP +V X[1] This voltage is then applied. At this time, since nodes N[1,1] and Nr[1] are electrically floating, the capacitive coupling of capacitor C1 causes the potentials of nodes N[1,1] and Nr[1] to change.

[0247] In each of memory cell AM[1] and memory cell AMr[1], the increase in the potential of the gate of transistor Tr12 is a potential obtained by multiplying the change in the potential of wiring XL[1] by a capacitance coupling coefficient determined by the configuration of the memory cell. The capacitance coupling coefficient is calculated based on the capacitance of capacitor C1, the gate capacitance of transistor Tr12, parasitic capacitance, etc. In this operation example, for the sake of avoiding complexity in explanation, the increase in the potential of wiring XL[1] and the increase in the potential of the gate of transistor Tr12 are both described as having the same value. This corresponds to setting the respective capacitance coupling coefficients in memory cell AM[1,1] and memory cell AMr[1] to 1. Also, in this operation example, for the memory cells other than memory cell AM[1,1] and memory cell AMr[1] included in memory cell array CA, the respective capacitance coupling coefficients are also described as 1.

[0248] Since the capacitance coupling coefficient is 1, when the potential of the second terminal of each capacitor C1 in memory cell AM[1,1] and memory cell AMr[1] varies from V RFP to V RFP +V X[1] the potentials of node N[1,1] and node Nr[1] each rise by V X[1] .

[0249] Here, when the current flowing from wiring BL through the second terminal of transistor Tr12 in memory cell AM[1,1] to the first terminal is I AM[1,1],3 , I AM[1.1],3 can be expressed by the following equation.

[0250]

Equation

[0251] Similarly, when the current flowing from wiring BLr through the second terminal of transistor Tr12 in memory cell AMr[1] to the first terminal is I AMr[1],4 , I AMr[1],4 can be expressed by the following equation.

[0252]

Number

[0253] Also, for memory cell AM[2,1] and memory cell AMr[2], since the capacitance coupling coefficient is set to 1, the potential of the second terminal of the capacitance C1 included in each of them is V RFP to V RFP +V X[2] By varying to, the potentials of node N[2,1] and node Nr[2] rise to V X[2] respectively.

[0254] Here, for example, when the current flowing from wiring BL through the second terminal of transistor Tr12 of memory cell AM[2,1] to the first terminal is I AM[2,1],3 then I AM[2.1],3 can be expressed by the following formula.

[0255]

Number

[0256] Similarly, for example, when the current flowing from wiring BLr through the second terminal of transistor Tr12 of memory cell AMr[2] to the first terminal is I AMr[2],4 then I AMr[2],4 can be expressed by the following formula.

[0257]

Number

[0258] Also, for memory cell AM[m,1] and memory cell AMr[m], since the capacitance coupling coefficient is set to 1, the potential of the second terminal of the capacitance C1 included in each of them is V RFP to V RFP +V X[m] By varying to, the potentials of node N[m,1] and node Nr[m] rise to V X[m] respectively.

[0259] Here, for example, the current flowing from the wiring BL to the first terminal of the memory cell AM[m,1] via the second terminal of transistor Tr12 is I AM[m,1],3 In that case, I AM[m.1],3 It can be expressed by the following formula.

[0260]

number

[0261] Similarly, for example, the current flowing from the wiring BLr to the first terminal of the memory cell AMr[2] via the second terminal of transistor Tr12 is I AMr[m],4 In that case, I AMr[m],4 It can be expressed by the following formula.

[0262]

number

[0263] When I3 is the sum of the amounts of current flowing from wiring BL[1] to memory cells AM[1,1] through AM[m,1] between time T13 and time T14, the amount of current I3 can be described by the following equation.

[0264]

number

[0265] Furthermore, since circuit CM is configured as a current mirror circuit, the amount of current flowing between the first and second terminals of transistor Tr32[1] included in circuit CM is approximately equal to the amount of current flowing between the first and second terminals of transistor Tr31. Also, the amount of current flowing between the first and second terminals of transistor Tr31 is the sum of the currents flowing from wiring BLr to memory cells AMr[1] to AMr[m]. Between time T13 and time T14, if the amount of current flowing between the first and second terminals of transistor Tr32[1] included in circuit CM is I4, then the amount of current I4 can be described by the following equation.

[0266]

number

[0267] Furthermore, between time T13 and time T14, switches SW3[1] to SW3[n], SW4A[1] to SW4A[n], and SW4B[1] to SW4B[n] are turned ON, so current flows through circuit ACTV from circuit CMS and memory cell array CA via wiring BL. Specifically, for example, current I1 flows out from circuit CS1[1], current I2 flows into circuit CS2[1], a total current I3 flows through memory cell AM[1,1] to memory cell AM[m,1], and current I4 flows between the source and drain of transistor Tr32[1] of circuit CM. Here, the amount of current flowing from wiring BL[1] to wiring NIL[1] is I S [1] When this is the case, the amount of current I S [1] can be written by Kirchhoff's laws as follows:

[0268]

number

[0269] From equation (1.20), the amount of current I input from wiring BL[1] to circuit ACTV is given by S [1] is the potential V corresponding to the first data. W[1,1] ~V W[m,1] And the potential V corresponding to the second data. X[1] ~V X[m] It is proportional to the sum of the products of the first and second data. In other words, the sum of the products of the first and second data is proportional to the amount of current I S [1] can be expressed as

[0270] In this embodiment, the case in which the transistor included in the arithmetic circuit MAC1 is an OS transistor or a Si transistor has been described, but the present invention is not limited to these. The transistor included in the arithmetic circuit MAC1 can be, for example, a transistor in which Ge or the like is included in the channel formation region, a transistor in which compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe are included in the channel formation region, a transistor in which carbon nanotubes are included in the channel formation region, or a transistor in which organic semiconductors are included in the channel formation region.

[0271] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0272] (Embodiment 2) In this embodiment, we will describe an arithmetic circuit with a different configuration from the arithmetic circuit MAC1 described in Embodiment 1.

[0273] <Example of arithmetic circuit configuration 2> The arithmetic circuit MAC2 shown in Figure 7 differs from the arithmetic circuit MAC1 in that it has memory cells AMb[1] to AMb[n] in the memory cell array CA.

[0274] Memory cell AMb[1] is electrically connected to wiring BL[1], wiring WD[1], wiring XLb, and wiring WLb. Similarly, memory cell AMb[n] is electrically connected to wiring BL[n], wiring WD[n], wiring XLb, and wiring WLb.

[0275] Figure 8 shows specific configuration examples of memory cells AMb[1] to AMb[n]. In addition, Figure 8 also shows memory cells AM[1,1] to AM[m,n], memory cells AMr[1] to AMr[m], circuit WDD, circuit CMS, and circuit ACTV to show the electrical connections to each of the memory cells AMb[1] to AMb[n].

[0276] As shown in Figure 8, memory cells AMb[1] to AMb[n] can have a configuration almost identical to that of memory cells AM[1,1] to AM[m,n] and memory cells AMr[1] to AMr[m]. Therefore, in the MAC2 arithmetic circuit in Figure 8, each of the memory cells AMb[1] to AMb[n] has a transistor Tr11, a transistor Tr12, and a capacitor C1.

[0277] In each of the memory cells AMb[1] to AMb[n], the first terminal of transistor Tr12 is electrically connected to wiring VRA.

[0278] Furthermore, in memory cell AMb[1], the electrical connection point between the first terminal of transistor Tr11, the gate of transistor Tr12, and the first terminal of capacitor C1 is defined as node Nb[1]. Similarly, in memory cell AMb[n], the electrical connection point between the first terminal of transistor Tr11, the gate of transistor Tr12, and the first terminal of capacitor C1 is defined as node Nb[n].

[0279] Wiring WLb functions as wiring that supplies a selection signal from circuit WLD to memory cells AMb[1] to AMb[n] when writing data to memory cells AMb[1] to AMb[n]. Wiring XLb functions as wiring that applies a constant potential to the second terminal of the capacitance C1 of memory cells AMb[1] to AMb[n], for example. The constant potential is preferably the ground potential, a low-level potential, a high-level potential, etc. Alternatively, wiring XLb may function as wiring for supplying an arbitrary potential from circuit XLD.

[0280] Each wiring VRA of memory cells AMb[1] to AMb[n] can be set to a low-level potential, ground potential, or a potential lower than ground potential, similar to the wiring VRs of memory cells AM[1,1] to AM[m,n] and memory cells AMr[1] to AMr[m]. Alternatively, each wiring VRA of memory cells AMb[1] to AMb[n] may, in some cases, be set to a high-level potential. For example, if it is desired to flow a positive current from memory cell AMb[1] to wiring BL[1], the wiring VRA of memory cell AMb[1] should be set to a high-level potential.

[0281] As an example of the operation of the arithmetic circuit MAC2 in Figure 8, for example, in the timing chart in Figure 6, from before time T02 to time T11, the transistor Tr12 of memory cells AMb[1] to AMb[n] is turned off, and the nodes Nb[1] to Nb[n] are maintained at ground potential, low level potential, or the potential supplied by the wiring VR. Then, in the timing chart in Figure 6, from time T14 to time T15, an arbitrary amount of current I is applied between the first and second terminals of each transistor Tr12 of memory cells AMb[1] to AMb[n]. BIAS [1]~I BIAS To allow [n] to flow, a potential V is applied to each of nodes Nb[1] through Nb[n]. BIAS [1]~V BIAS It holds [n]. For example, in this case, I BIAS [1] can be expressed by the following formula:

[0282]

number

[0283] Therefore, between time T14 and time T15, for example, the amount of current I flowing from wiring BL[1] to wiring NIL[1] via circuit ACTV. S [1] is given by the following equation:

[0284]

number

[0285] Equation (2.2) corresponds to an operation that further applies an arbitrary bias to the result of a sum-of-products operation. As will be explained in detail in Embodiment 3, an operation that further applies an arbitrary bias to the result of a sum-of-products operation is used in the operations of a hierarchical neural network. For this reason, the MAC2 operation circuit is suitable for performing operations of a hierarchical neural network.

[0286] <Example of arithmetic circuit configuration 3> Next, we will describe an example of the configuration of an arithmetic circuit, which is a semiconductor device according to one embodiment of the present invention, and is different from the arithmetic circuit MAC1 in Figure 1 and the arithmetic circuit MAC2 in Figure 7.

[0287] The arithmetic circuit MAC3 shown in Figure 9 differs from arithmetic circuits MAC1 and MAC2 in that the current related to the result of the sum-of-accumulate operation flows from circuit CMS to circuit ACTV.

[0288] In the arithmetic circuit MAC3 shown in Figure 9, circuit CMS is electrically connected to circuit ACTV via wiring BLO[1] to BLO[n]. For other circuit configurations, please refer to the explanation of the arithmetic circuit MAC1 shown in Figure 1.

[0289] Figure 10 shows specific configuration examples of the ACTV circuit and the CMS circuit.

[0290] The circuit CMS shown in Figure 10 is configured as shown in the circuit CMS of Figure 4 described in Embodiment 1, with wiring BLO[1] electrically connected to the second terminal of switch SW3[1], the second terminal of transistor Tr32[1], and the second terminal of transistor Tr34 of circuit CS2[1], and wiring BLO[n] electrically connected to the second terminal of switch SW3[n], the second terminal of transistor Tr32[n], and the second terminal of transistor Tr34 of circuit CS2[n].

[0291] Furthermore, the circuit CMS shown in Figure 10 has switches SW8[1] to SW8[n] and switch SW8r. The first terminals of each of switches SW8[1] to SW8[n] are electrically connected to the wirings BL[1] to BL[n] and to the first terminals of each of switches SW7[1] to SW7[n]. The first terminal of switch SW8r is electrically connected to the wiring BLr. The second terminals of each of switches SW8[1] to SW8[n] and switch SW8r are electrically connected to the wiring VLL, and the control terminals of each of switches SW8[1] to SW8[n] and switch SW8r are electrically connected to the wiring SL8.

[0292] Switches SW8[1] to SW8[n] and SW8r can be, for example, switches applicable to switches SW1, SW2, SW3[1] to SW3[n], etc. In this specification, each of switches SW8[1] to SW8[n] and SW8r is assumed to be ON when a high-level potential is input to the control terminal and OFF when a low-level potential is input, similar to switches SW1, SW2, and SW3[1] to SW3[n].

[0293] Wiring VLL functions, for example, as wiring that provides a constant voltage. This constant voltage can be, for example, a low-level potential or ground potential. In particular, the constant voltage provided by wiring VLL may be equal to the constant voltage provided by wiring VSL. In other words, wiring VLL and wiring VSL may be combined into a single wiring.

[0294] Wiring SL8 functions, for example, as wiring that supplies voltage to switch switches SW8[1] to SW8[n] and switch SW8r between the conductive and non-conductive states.

[0295] Furthermore, the ACTV circuit shown in Figure 10 has almost the same configuration as the ACTV circuit shown in Figure 2.

[0296] Furthermore, in Figure 10, the wiring that electrically connects circuit ACTV and circuit CMS is denoted as wiring BLO[1] to wiring BLO[n]. Each of wiring BLO[1] to wiring BLO[n] is electrically connected to the first terminal of switch SW4[1] to switch SW4, which is included in circuit ACTV in Figure 2.

[0297] By applying the circuit CMS and circuit ACTV, configured as shown in Figure 10, to the arithmetic circuit MAC3 in Figure 9, the same operation as the arithmetic circuit MAC1 described in Embodiment 1 can be achieved.

[0298] In the timing chart of Figure 6, when writing the potential corresponding to the first data to each of the memory cells AM[1,1] to AM[m,n] and AMr[1] to AMr[m], that is, between time T03 and time T09, a high-level potential is applied to the wiring WE to turn on switches SW5[1] to SW5[n] and SW5r, and the potentials of wiring BL[1] to BL[n] and BLr are set to ground potential. However, in the calculation circuit MAC3 to which the circuit CMS and ACTV of Figure 10 are applied, a high-level potential is applied to the wiring SL8 to turn on switches SW8[1] to SW8[n] and SW8r, and the potentials of wiring BL[1] to BL[n] and BLr are set to ground potential. Furthermore, when current is supplied from wiring BL[1] to wiring BL[n] and wiring BLr to the corresponding memory cells AM and AMr, for example, from time T11 onwards in the timing chart of Figure 6, a low-level potential can be applied to wiring SL8 to turn off switches SW8[1] to SW8[n] and SW8r.

[0299] Furthermore, the configurations of circuits CMS and ACTV included in the arithmetic circuit MAC3 in Figure 9 are not limited to the configuration shown in Figure 10. For example, the circuits CMS and ACTV included in the arithmetic circuit MAC3 in Figure 9 may also be the configuration example shown in Figure 11.

[0300] The circuit CMS shown in Figure 11 is configured by adding switches SW6[1] to SW6[n] to the circuit CMS in Figure 10. Specifically, the first terminal of switch SW6[1] is electrically connected to the second terminal of switch SW3[1], the second terminal of transistor Tr32[1], and the second terminal of transistor Tr34. The second terminal of switch SW6[1] is electrically connected to wiring BLO[1]. In addition, the control terminals of switches SW6[1] to SW6[n] are electrically connected to wiring SL6.

[0301] Switches SW6[1] to SW6[n] can be, for example, switches applicable to switches SW1, SW2, SW3[1] to SW3[n], etc. In this specification, each of switches SW6[1] to SW6[n] is assumed to be ON when a high-level potential is input to the control terminal and OFF when a low-level potential is input, similar to switches SW1, SW2, SW3[1] to SW3[n].

[0302] Furthermore, the ACTV circuit shown in Figure 11 is configured in a way that the switches SW4A[1] to SW4A[n] are not present in the ACTV circuit shown in Figure 2. Therefore, the first terminals of circuits IVC[1] to IVC[n] included in the ACTV circuit in Figure 11 are electrically connected to the wiring BLO[1] to BLO[n].

[0303] In other words, the circuit CMS in Figure 11 is configured such that switches SW6[1] to SW6[n] are provided as replacements for switches SW4A[1] to SW4A[n] included in the circuit ACTV in Figure 10.

[0304] Furthermore, when performing the operation of the timing chart in Figure 6 described in Embodiment 1 using the calculation circuit MAC3 to which the circuit CMS and circuit ACTV in Figure 11 are applied, the timing at which switches SW3[1] to SW3[n], switches SW4B[1] to SW4B[n], and switches SW6[1] to SW6[n] each become ON or OFF is the same, so wiring SL3, wiring SL4, and wiring SL6 may be combined into a single wiring.

[0305] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0306] (Embodiment 3) This embodiment describes the configuration of a hierarchical neural network that can perform calculations using a semiconductor device according to one aspect of the present invention.

[0307] A hierarchical neural network, for example, has one input layer, one or more hidden layers, and one output layer, and is composed of a total of three or more layers. The hierarchical neural network 100 shown in Figure 12A is an example of such a network, and the neural network 100 has layers 1 through R (where R can be an integer of 4 or more). In particular, layer 1 corresponds to the input layer, layer R corresponds to the output layer, and the other layers correspond to hidden layers. Note that in Figure 12A, layers (k-1) and k (where k is an integer between 3 and R-1) are shown as hidden layers.

[0308] Each layer of the neural network 100 has one or more neurons. In Figure 12A, the first layer is neuron N1 (1) Neuron N p (1) (Here, p is an integer greater than or equal to 1.) The (k-1)th layer has neuron N1 (k-1) Neuron N m (k-1) (where m is an integer greater than or equal to 1.) The k-th layer has neurons N1 (k)Neuron N n (k) (where n is an integer greater than or equal to 1.) The R layer has neurons N1 (R) Neuron N q (R) (where q is an integer greater than or equal to 1.)

[0309] Note that Figure 12A shows neuron N1 (1) , Neuron N p (1) , neuron N1 (k-1) , Neuron N m (k-1) , neuron N1 (k) , Neuron N n (k) , neuron N1 (R) , Neuron N q (R) In addition, the (k-1) layer neurons N i (k-1) (Here, i is an integer between 1 and m, inclusive.) Neuron N of layer k j (k) (Here, j is an integer between 1 and n, inclusive.) This is an excerpt illustrating that part.

[0310] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals that are input and output in each neuron. Note that in this explanation, we will assume that the neurons in layer k are N j (k) We are focusing on that.

[0311] Figure 12B shows neurons N in layer k. j (k) And, neuron N j (k) The signal input to and neuron N j (k) This shows the signal output from and .

[0312] Specifically, the (k-1) neuron N1 (k-1) Neuron N m (k-1) z1 is the output signal of each of the following: (k-1)~z m (k-1) However, neuron N j (k) It is outputting towards neuron N. j (k) is z1 (k-1) ~z m (k-1) z j (k) Generate z j (k) This is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0313] The degree to which signals are transmitted from neurons in the previous layer to neurons in the next layer is determined by the strength of the synaptic connections (hereinafter referred to as weight coefficients) between those neurons. In neural network 100, the product of the signal output from the neuron in the previous layer and the corresponding weight coefficient is input to the neuron in the next layer. Neuron N in the (k-1)th layer i (k-1) and the k-th layer of neurons N j (k) The weight coefficient of the synapse between w i (k-1) j (k) When this is the case, the neurons N in layer k j (k) The signal input to the device can be expressed by equation (3.1).

[0314]

number

[0315] In other words, the (k-1)th layer neuron N1 (k-1) Neuron N m (k-1) From each of these, the k-th layer neurons N j (k) When a signal is transmitted to z1, the signal in question is z1 (k-1) ~z m (k-1) This includes weight coefficients (w1) corresponding to each signal. (k-1)j (k) Or maybe lol m (k-1) j (k) ) is multiplied. And the neuron N in layer k j (k) w1 (k-1) j (k) ·z1 (k-1) Or maybe lol m (k-1) j (k) ·z m (k-1) This is input. At this time, the neuron N in layer k j (k) The sum of the signals input to u j (k) This is given by equation (3.2).

[0316]

number

[0317] Also, the weight coefficient w1 (k-1) j (k) Or maybe lol m (k-1) j (k) And the neuron's signal z1 (k-1) ~z m (k-1) The result of the sum of products of and may be biased. When the bias is b, equation (3.2) can be rewritten as follows:

[0318]

number

[0319] Neuron N j (k) , u j (k) Depending on the output signal z j (k) It generates neuron N. j (k) Output signal z fromj (k) We define it by the following formula.

[0320]

number

[0321] function f(u j (k) The activation function in a hierarchical neural network can be the step function, ReLU function (ramp function), sigmoid function, etc. The activation function may be the same for all neurons, or it may be different for all neurons. Furthermore, the activation functions of neurons may be the same or different for each layer.

[0322] By the way, the signals output by neurons in each layer, the weight coefficient w, or the bias b, may be analog values, digital values, or multi-level values. As digital values, for example, they may be binary, and as multi-level values, for example, they may be three or more levels. They may also be values ​​with a larger number of bits. As an example, in the case of analog values, activation functions such as the ReLU function or the sigmoid function may be used. In the case of binary digital values, for example, a step function that outputs -1 or 1, or 0 or 1 may be used. Furthermore, the signals output by neurons in each layer may be three or more levels. For example, as an activation function that outputs three levels, a step function that outputs -1, 0, or 1, or a step function that outputs 0, 1, or 2 may be used. Also, for example, as an activation function that outputs five levels, a step function that outputs -2, -1, 0, 1, or 2 may be used. By using digital values ​​for at least one of the signals, weight coefficients w, or bias b output by neurons in each layer, it is possible to reduce circuit size, lower power consumption, or increase computation speed. Furthermore, by using analog values ​​for at least one of the signals, weight coefficients w, or bias b output by neurons in each layer, it is possible to improve computational accuracy.

[0323] When an input signal is input to the first layer (input layer), the neural network 100 sequentially generates an output signal in each layer from the first layer (input layer) to the last layer (output layer) based on the signal input from the previous layer, using equations (3.1), (3.2) (or (3.3)), and (3.4), and outputs that output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result calculated by the neural network 100.

[0324] The calculations performed in the first layer (input layer), hidden layer, and last layer (output layer) of the neural network 100 can be carried out using the calculation circuits MAC1 to MAC3 described in Embodiment 1 and Embodiment 2.

[0325] In particular, if you want to add a bias to the sum-of-products result, as shown in equation (3.3), you can use the MAC2 arithmetic circuit described in Embodiment 2. In this case, the bias b in equation (3.3) is equal to I in equations (2.1) and (2.2). BIAS [1] corresponds to this.

[0326] The circuits XLD of the arithmetic circuits MAC1 to MAC3 described in Embodiment 1 and Embodiment 2 can be applied, for example, as the input layer described in this embodiment. Here, the second layer is a neuron N1 (2) Neuron N r (2) Let's consider the case where a signal is sent from a neuron in the first layer to a neuron in the second layer, assuming that (r is an integer greater than or equal to 1) is included. In this case, the memory cell array CA of the arithmetic circuits MAC1 to MAC3 is configured such that the memory cells AM are arranged in a matrix of p rows and r columns.

[0327] Neurons N in the first layer (input layer) s[1] (1) (s[1] is an integer between 1 and p) is the received signal z s[1](1) This signal is output to all neurons in the second layer (hidden layer). s[1] (1) By using this as the potential output from the circuit XLD (second data), the signal z output from the first layer (input layer) is obtained. s[1] (1) This can be input to memory cells AM[s[1],1] to AM[s[1],r] and memory cells AMr[s[1]] included in the memory cell array CA via wiring XL[s[1]].

[0328] At this time, each memory cell AM in the s[2] column of the memory cell array CA (where s[2] is an integer between 1 and r, inclusive) is assigned a weight coefficient w. s[1] (1) s[2] (2) Because it is stored as the first data, the neurons N in the second layer (hidden layer) s[2] (2) In the signal z s[1] (1) and weight coefficient w s[1] (1) s[2] (2) The sum of products of can be calculated. Specifically, the current I flowing from wiring BL[s[2]] to circuit ACTV S From [s[2]], the signal z s[1] (1) and weight coefficient w s[1] (1) s[2] (2) The sum of products can be calculated. In addition, by using the ACTV circuit to determine the value of the activation function from the result of the sum of products, the value of the activation function can be calculated for the second layer neuron N. s[2] (2) Output signal z s[2] (2) It can be output from wiring NIL[s[2]].

[0329] Furthermore, the arithmetic circuits MAC1 to MAC3 described in Embodiment 1 and Embodiment 2 can be applied as the hidden layers described above. Here, we consider the case where a signal is sent from a neuron in the (k-1)th layer to a neuron in the kth layer. In this case, the memory cell array CA of the arithmetic circuits MAC1 to MAC3 is configured such that the memory cells AM are arranged in an m x n matrix.

[0330] Neurons N in layer (k-1) i (k-1) is the signal z i (k-1) to neuron N1 in layer k (k) Neuron N n (k) Output to the signal z. i (k-1) By using this as the potential output from the circuit XLD (second data), the signal z output from the (k-1)th layer is obtained. i (k-1) This can be input to memory cells AM[i,1] through AM[i,n] and AMr[i] included in the memory cell array CA via wiring XL[i].

[0331] At this time, each memory cell AM in the j-th column of the memory cell array CA is assigned a weighting coefficient w. i (k-1) j (k) Because it is stored as the first data, the neurons N in layer k j (k) In the signal z i (k-1) and weight coefficient w i (k-1) j (k) The sum of products of can be calculated. Specifically, the current I flowing from wiring BL[j] to circuit AVTC S From [j], signal z i (k-1) and weight coefficient w i (k-1) j (k)The sum of products can be calculated. In addition, by determining the value of the activation function from the result of the sum of products using the ACTV circuit, the value of the activation function can be calculated for the layer k neuron N. j (k) Output signal z j (k) It can be output from wiring NIL[j].

[0332] Furthermore, the arithmetic circuits MAC1 to MAC3 described in Embodiment 1 and Embodiment 2 can be applied as the output layer described above. Here, the (R-1) layer is a neuron N1 (R-1) Neuron N v (R-1) Let's consider the case where a signal is sent from a neuron in layer (R-1) to a neuron in layer R, assuming that (v is an integer greater than or equal to 1) is included. In this case, the memory cell array CA of arithmetic circuits MAC1 to MAC3 is configured such that the memory cells AM are arranged in a matrix of v rows and q columns.

[0333] Neurons in layer (R-1) N s[R-1] (R-1) (s[R-1] is an integer between 1 and v, inclusive.) is the signal z s[R-1] (R-1) Neuron N1 in layer R (R) Neuron N q (R) Output to the signal z. s[R-1] (R-1) By using this as the potential output from circuit XLD (second data), the signal z output from the (R-1) layer is obtained. s[R-1] (R-1) This can be input to memory cells AM[s[R-1],1] to AM[s[R-1],n] and memory cells AMR[s[R-1]] included in the memory cell array CA via wiring XL[s[R-1]].

[0334] At this time, each memory cell AM in the s[R] column of the memory cell array CA (where s[R] is an integer between 1 and q, inclusive) is assigned a weight coefficient w s[R-1](R-1) s[R] (R) Because this is stored as the first data, the neurons N in layer R s[R] (R) In the signal z s[R-1] (R-1) and weight coefficient w s[R-1] (R-1) s[R] (R) The sum of products of can be calculated. Specifically, the current I flowing from wiring BL[s[R]] to circuit ACTV S [s[R]] signal z s[R-1] (R-1) and weight coefficient w s[R-1] (R-1) s[R] (R) The sum of products can be calculated. In addition, by using the ACTV circuit to determine the value of the activation function from the result of the sum of products, the value of the activation function can be calculated for the neuron N in layer R. s[R] (R) Output signal z s[R] (R) It can be output from wiring NIL[s[R]].

[0335] In the arithmetic circuit described in this embodiment, the number of rows of the memory cell array (AM) corresponds to the number of neurons in the previous layer. In other words, the number of rows of the memory cell array corresponds to the number of output signals from the previous layer's neurons that are input to one neuron in the next layer. Also, in the arithmetic circuit described in this embodiment, the number of columns of the memory cell array corresponds to the number of neurons in the next layer. In other words, the number of columns of the memory cell array corresponds to the number of output signals output from the neurons in the next layer. In short, the number of rows and columns of the memory cell array in the arithmetic circuit is determined by the number of neurons in the previous and next layers, so the number of rows and columns of the memory cell array should be determined and designed according to the neural network to be constructed.

[0336] For example, when the arithmetic circuit MAC1 described in Embodiment 1 is applied as the hidden layer described above, the weight coefficient w i (k-1) j (k)This is used as the first data, and the potential corresponding to the first data is sequentially stored in the memory cells AM of the same column, and the (k-1) layer neuron N i (k-1) Output signal z from i (k-1) Using this as the second data, a potential corresponding to the second data is supplied from circuit XLD to the wiring XL of each row, thereby determining the amount of current I flowing from wiring BL[k] to circuit ACTV. S signal z i (k-1) and weight coefficient w i (k-1) j (k) The sum of products of the two values ​​can be calculated, and the ACTV circuit can then calculate the value of the activation function corresponding to that value. In other words, the value of the activation function is used as a signal for the neuron N in layer k. j (k) Output signal z j (k) This can be done. Furthermore, the ACTV circuit is configured to output a potential corresponding to the value of the activation function, and the k-layer neuron N j (k) Output signal z j (k) By configuring it to input to another arithmetic circuit MAC1, the neurons N output from the (k+1)th layer neurons in that other arithmetic circuit MAC1 are generated. s[k+1] (k+1) The output signal z (where s[k+1] is an integer greater than or equal to 1 and less than or equal to the total number of neurons in the k+1th layer). s[k+1] (k+1) It is possible to calculate this.

[0337] Specifically, the above calculations can be performed by using the arithmetic circuit MAC4 shown in Figure 13. The arithmetic circuit MAC4 in Figure 13 includes, as an example, arithmetic circuit MAC1-1, which is configured in the same way as the arithmetic circuit MAC1 in Figure 1 but without the circuit WDD, arithmetic circuit MAC1-2, which is configured in the same way as the arithmetic circuit MAC1 in Figure 1 but without the circuits WDD and XLD, and the circuit WDD.

[0338] In the arithmetic circuit MAC1-1, the memory cell array CA1 corresponds to the memory cell array CA of the arithmetic circuit MAC1 in Figure 1, the circuit CMS1 corresponds to the circuit CMS of the arithmetic circuit MAC1 in Figure 1, the circuit XLD1 corresponds to the circuit XLD of the arithmetic circuit MAC1 in Figure 1, the circuit WLD1 corresponds to the circuit WLD of the arithmetic circuit MAC1 in Figure 1, and the circuit ACTV1 corresponds to the circuit ACTV of the arithmetic circuit MAC1 in Figure 1. Furthermore, in the arithmetic circuit MAC1-2, the memory cell array CA2 corresponds to the memory cell array CA of the arithmetic circuit MAC1 in Figure 1, the circuit CMS2 corresponds to the circuit CMS of the arithmetic circuit MAC1 in Figure 1, the circuit WLD2 corresponds to the circuit WLD of the arithmetic circuit MAC1 in Figure 1, and the circuit ACTV2 corresponds to the circuit ACTV of the arithmetic circuit MAC1 in Figure 1.

[0339] Furthermore, the memory cell array CA1 of the arithmetic circuit MAC1-1 has m × n memory cells AM and m memory cells AMr arranged in a matrix, and the memory cell array CA2 of the arithmetic circuit MAC1-2 has n × t memory cells AM (where t is an integer greater than or equal to 1, and is the total number of neurons in the (k+1)th layer) and n memory cells AMr arranged in a matrix.

[0340] Therefore, in the arithmetic circuit MAC1-1, wiring BL1[1] to wiring BL1[n] corresponds to wiring BL[1] to wiring BL[n] of the arithmetic circuit MAC1 in Figure 1, wiring BLr1 corresponds to wiring BLr of the arithmetic circuit MAC1 in Figure 1, wiring XL1[1] to wiring XL1[m] corresponds to wiring XL[1] to wiring XL[m] of the arithmetic circuit MAC1 in Figure 1, wiring WL1[1] to wiring WL1[m] corresponds to wiring WL[1] to wiring WL[n] of the arithmetic circuit MAC1 in Figure 1, wiring WD1[1] to wiring WD1[n] corresponds to wiring WD[1] to wiring WD[n] of the arithmetic circuit MAC1 in Figure 1, wiring WDr1 corresponds to wiring WDr of the arithmetic circuit MAC1 in Figure 1, and wiring NIL1[1] to wiring NIL1[n] corresponds to wiring NIL to wiring NIL[n] of the arithmetic circuit MAC1 in Figure 1. Furthermore, in the arithmetic circuit MAC1-2, wiring BL2[1] to wiring BL2[n] corresponds to wiring BL[1] to wiring BL[n] of the arithmetic circuit MAC1 in Figure 1, wiring BLr2 corresponds to wiring BLr of the arithmetic circuit MAC1 in Figure 1, wiring XL2[1] to wiring XL2[n] corresponds to wiring XL[1] to wiring XL[m] of the arithmetic circuit MAC1 in Figure 1, wiring WL2[1] to wiring WL2[n] corresponds to wiring WL[1] to wiring WL[n] of the arithmetic circuit MAC1 in Figure 1, wiring WD2[1] to wiring WD2[t] corresponds to wiring WD[1] to wiring WD[n] of the arithmetic circuit MAC1 in Figure 1, and wiring WDr2 corresponds to wiring WDr of the arithmetic circuit MAC1 in Figure 1.

[0341] Furthermore, each of the wirings NIL[1] through NIL[n] of the arithmetic circuit MAC1-1 is electrically connected to the wirings XL[1] through XL[n] of the arithmetic circuit MAC1-2.

[0342] For example, in the arithmetic circuit MAC1-1 shown in Figure 13, the weight coefficient between the (k-1)th layer neuron and the k-th layer neuron is stored as the first data in memory cells AM[1,1] to AM[m,n] of the memory cell array CA1, and the (k-1)th layer neuron N s[k-1] (k-1) Output signal z from s[k-1] (k-1)Using this as the second data, a potential corresponding to the second data is passed from circuit XLD1 to the wiring XL1 of each row, so that from each of the wirings BL1[1] to BL1[n], through each of the wirings NIL1[1] to NIL1[n], the neurons N1 of layer k (k) Neuron N n (k) Output signal z1 (k) ~z n (k) It can output the following. Note that the output signal z1 (k) ~z n (k) Each of these values ​​can be expressed as the potential output from circuit ACTV1 to wiring NIL1[1] through wiring NIL1[n], respectively.

[0343] Here, in the arithmetic circuit MAC1-2 shown in Figure 13, the weight coefficient between the neuron of layer k and the neuron of layer (k+1) is stored as the first data in memory cells AM[1,1] to AM[n,t] of the memory cell array CA2, and the potential supplied to the wiring XL2 of each row, i.e., the neuron N1 of layer k, is used. (k) Neuron N n (k) Output signal z1 (k) ~z n (k) By using this as the second data, from each of the wirings BL2[1] to BL2[t], via each of the wirings NIL2[1] to NIL2[t], the neurons N1 of the (k+1) layer (k+1) Neuron N t (k+1) Each output signal z1 (k+1) ~z t (k+1) It can output the following. Note that the output signal z1 (k+1) ~z n (k+1) Each of these values ​​can be expressed as the potential output from circuit ACTV2 to wiring NIL2[1] through wiring NIL2[n], respectively.

[0344] In the MAC4 arithmetic circuit shown in Figure 13, wires WD1[1] through WD1[n] and wires WD2[1] through WD2[t] are illustrated, but wires located in the same column may be combined into a single wire. For example, wires WD1[1] and WD2[1] may be combined into a single wire, or, for example, if n is less than t, wires WD1[n] and WD2[n] may be combined into a single wire, or, for example, if n is greater than t, wires WD1[t] and WD2[t] may be combined into a single wire. Similarly, wires WDr1 and WDr2 may be combined into a single wire. As described above, by combining wires WD1 and WD2 into a single wire, the number of wires that transmit the first data can be reduced, and thus the number of drive circuits required for each wire in the WDD can be reduced. In other words, the circuit area of ​​the WDD can be reduced.

[0345] As described above, the arithmetic circuits MAC1 to MAC3 can determine the number of rows and columns of the memory cell array CA according to the scale of the hierarchical neural network. Furthermore, by connecting at least one of the arithmetic circuits MAC1 to MAC3 as shown in Figure 13, calculations can be performed according to the number of layers of the hierarchical neural network.

[0346] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0347] (Embodiment 4) This embodiment describes an example of the configuration of a semiconductor device as described in the above embodiment, and an example of the configuration of a transistor that can be applied to a semiconductor device.

[0348] <Example of semiconductor device configuration> The semiconductor device shown in Figure 14 includes a transistor 300, a transistor 500, and a capacitive element 600. Figure 16A is a cross-sectional view of transistor 500 in the channel length direction, Figure 16B is a cross-sectional view of transistor 500 in the channel width direction, and Figure 16C is a cross-sectional view of transistor 300 in the channel width direction.

[0349] Transistor 500 is a transistor (OS transistor) having a metal oxide in its channel formation region. Transistor 500 has the characteristics of low off-current and unchanging field-effect mobility even at high temperatures. By applying transistor 500 to a semiconductor device, such as a transistor included in the arithmetic circuit MAC1, MAC2, MAC3, MAC4 described in the above embodiment, a semiconductor device can be realized that does not experience a decrease in operating capability even at high temperatures. In particular, by utilizing the characteristic of low off-current and applying transistor 500 to, for example, transistor Tr11 of arithmetic circuit MAC1, the potential written to the first terminal of the memory cell's capacitance C1 can be maintained for a long time.

[0350] In the semiconductor device shown in Figure 14, transistor 500 is provided, for example, above transistor 300, and capacitive element 600 is provided, for example, above both transistor 300 and transistor 500. Capacitive element 600 can be a capacitor included in the arithmetic circuits MAC1, MAC2, MAC3, MAC4, etc., described in the above embodiment. Depending on the circuit configuration, the capacitive element 600 shown in Figure 14 does not necessarily have to be provided.

[0351] The transistor 300 is provided on the substrate 311 and has a conductor 316, an insulator 315, a semiconductor region 313 consisting of a part of the substrate 311, a low-resistance region 314a that functions as a source region or drain region, and a low-resistance region 314b. The transistor 300 can be applied to, for example, transistors included in the arithmetic circuits MAC1, MAC2, MAC3, MAC4, etc., described in the above embodiment. Specifically, for example, it can be transistor Tr12 in arithmetic circuit MAC1. Alternatively, for example, it can be a transistor included in circuit ACTV. In Figure 14, the gate of transistor 300 is shown to be electrically connected to either the source or drain of transistor 500 via one of the pair of electrodes of the capacitive element 600. However, depending on the configuration of the arithmetic circuits MAC1, MAC2, MAC3, MAC4, etc., either the source or drain of transistor 300 may be electrically connected to either the source or drain of transistor 500 via one of the pair of electrodes of the capacitive element 600. Alternatively, either the source or drain of transistor 300 may be electrically connected to the gate of transistor 500 via one of the pair of electrodes of the capacitive element 600. Furthermore, each terminal of transistor 300 may not be electrically connected to any of the terminals of transistor 500 or any of the terminals of the capacitive element 600.

[0352] Furthermore, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate) as the substrate 311.

[0353] As shown in Figure 16C, the transistor 300 has its semiconductor region 313's top surface and side surface in the channel width direction covered by a conductor 316 via an insulator 315. By making the transistor 300 a Fin type in this way, the effective channel width can be increased, thereby improving the on-characteristics of the transistor 300. In addition, the contribution of the gate electrode's electric field can be increased, thus improving the off-characteristics of the transistor 300.

[0354] Note that transistor 300 can be either a p-channel or n-channel type.

[0355] In the low-resistance region 314a and low-resistance region 314b, which are the channel-forming region of the semiconductor region 313, the region near it, the source region, or the drain region, it is preferable that a semiconductor such as a silicon-based semiconductor is included, and it is preferable that single-crystal silicon is included. Alternatively, it may be formed from a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), etc. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing is also possible. Alternatively, the transistor 300 may be made into a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, etc.

[0356] The low-resistance region 314a and the low-resistance region 314b include, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity, such as arsenic and phosphorus, or elements that impart p-type conductivity, such as boron.

[0357] The conductor 316, which functions as the gate electrode, can be made of a conductive material such as silicon, a semiconductor material, a metallic material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0358] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride or tantalum nitride as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use a laminate of metal materials such as tungsten or aluminum as the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0359] Note that the transistor 300 shown in Figure 14 is just one example, and its structure is not limited to this example. Any appropriate transistor can be used depending on the circuit configuration, driving method, etc. For example, if the semiconductor device is a unipolar circuit using only OS transistors, the configuration of transistor 300 can be the same as that of transistor 500, which uses an oxide semiconductor, as shown in Figure 15. Details of transistor 500 will be described later.

[0360] In Figure 15, the transistor 300 is mounted on a substrate 312. In this case, the substrate 312 may be a semiconductor substrate, similar to the substrate 311 of the semiconductor device in Figure 14. The substrate 312 can be, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, synthetic resins such as acrylic can also be used. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Alternatively, examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or paper.

[0361] The transistor 300 is covered by insulators 320, 322, 324, and 326, which are stacked in that order.

[0362] For insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, etc. may be used.

[0363] In this specification, silicon oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride refers to a material in which the nitrogen content is greater than the oxygen content. Furthermore, in this specification, aluminum oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and aluminum nitride refers to a material in which the nitrogen content is greater than the oxygen content.

[0364] The insulator 322 may also function as a planarizing film that flattens steps caused by transistors 300 or the like located below it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment using chemical mechanical polishing (CMP) or the like to improve its flatness.

[0365] Furthermore, it is preferable to use a film for the insulator 324 that has barrier properties to prevent hydrogen, impurities, etc. from diffusing from the substrate 311 or the transistor 300 to the region where the transistor 500 is provided.

[0366] As an example of a film having barrier properties against hydrogen, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the properties of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0367] The amount of hydrogen desorption can be analyzed, for example, using a thermal desorption gas analysis (TDS) method. For example, in TDS analysis, the amount of hydrogen desorption from insulator 324, when the film surface temperature is in the range of 50°C to 500°C, is calculated as 10 × 10¹⁶ hydrogen atoms per unit area of ​​insulator 324. 15 atoms / cm 2 The following is preferably 5 × 10 15 atoms / cm 2 The following is acceptable.

[0368] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, and more preferably less than 3. Also, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, than that of the relative permittivity of the insulator 324. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0369] Furthermore, insulators 320, 322, 324, and 326 have embedded conductors 328 and 330, which connect to the capacitive element 600 or the transistor 500. Conductors 328 and 330 function as plugs or wires. Conductors that function as plugs or wires may be grouped together and assigned the same reference numeral. In this specification, the wire and the plug connected to the wire may be an integrated unit. That is, a part of the conductor may function as a wire, and a part of the conductor may function as a plug.

[0370] The plugs and wiring (conductor 328, conductor 330, etc.) can be made of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials, which can be used in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form them with low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce the wiring resistance.

[0371] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 14, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. Conductors 356 function as a plug or wiring for connecting to the transistor 300. Conductors 356 can be provided using the same material as conductors 328 and 330.

[0372] For example, it is preferable that the insulator 350, like the insulator 324, be an insulator that has barrier properties against hydrogen. It is also preferable that the conductor 356 includes a conductor that has barrier properties against hydrogen. In particular, a conductor that has barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 350. With this configuration, transistor 300 and transistor 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0373] For example, tantalum nitride may be used as the conductor that has barrier properties against hydrogen. Furthermore, by laminating tantalum nitride with highly conductive tungsten, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining conductivity as wiring. In this case, it is preferable that the tantalum nitride layer, which has barrier properties against hydrogen, is in contact with the insulator 350, which also has barrier properties against hydrogen.

[0374] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in Figure 14, insulators 360, 362, and 364 are stacked in order. Furthermore, a conductor 366 is formed on insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductor 366 can be provided using the same material as conductors 328 and 330.

[0375] For example, it is preferable that the insulator 360, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 366 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 360. With this configuration, transistor 300 and transistor 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0376] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in Figure 14, insulators 370, 372, and 374 are stacked in order. Furthermore, a conductor 376 is formed on insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. The conductor 376 can be provided using the same material as the conductors 328 and 330.

[0377] For example, it is preferable that the insulator 370, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 376 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 370. With this configuration, transistor 300 and transistor 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0378] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in Figure 14, insulators 380, 382, ​​and 384 are stacked in order. Furthermore, a conductor 386 is formed on insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductor 386 can be provided using the same material as the conductors 328 and 330.

[0379] For example, it is preferable that the insulator 380, like the insulator 324, be an insulator having barrier properties against hydrogen. Furthermore, it is preferable that the conductor 386 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 380. With this configuration, transistor 300 and transistor 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0380] In the above, wiring layers including conductor 356, wiring layers including conductor 366, wiring layers including conductor 376, and wiring layers including conductor 386 have been described, but the semiconductor device according to this embodiment is not limited thereto. Three or fewer wiring layers similar to the wiring layer including conductor 356 may be used, or five or more wiring layers similar to the wiring layer including conductor 356 may be used.

[0381] Insulators 510, 512, 514, and 516 are layered sequentially on the insulator 384. It is preferable that one of the insulators 510, 512, 514, and 516 is made of a material that has barrier properties against oxygen, hydrogen, etc.

[0382] For example, it is preferable to use a film for insulators 510 and 514 that has barrier properties to prevent hydrogen, impurities, etc. from diffusing from, for example, the substrate 311 or the region where the transistor 300 is installed to the region where the transistor 500 is installed. Therefore, the same material as for insulator 324 can be used.

[0383] As an example of a film having hydrogen barrier properties, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0384] Furthermore, as films having barrier properties against hydrogen, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for insulators 510 and 514.

[0385] In particular, aluminum oxide exhibits a high barrier effect, preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical properties of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen and moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0386] Furthermore, for example, the same materials as those used for insulator 320 can be used for insulator 512 and insulator 516. Additionally, by applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wiring can be reduced. For example, silicon oxide films, silicon oxynitride films, etc., can be used as insulators 512 and insulator 516.

[0387] Furthermore, insulators 510, 512, 514, and 516 have a conductor 518 and a conductor constituting the transistor 500 (for example, conductor 503) embedded in them. The conductor 518 functions as a plug or wiring for connecting to the capacitive element 600 or the transistor 300. The conductor 518 can be provided using the same material as conductors 328 and 330.

[0388] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, transistor 300 and transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0389] A transistor 500 is provided above the insulator 516.

[0390] As shown in Figures 16A and 16B, the transistor 500 includes a conductor 503 arranged to be embedded in insulators 514 and 516, an insulator 520 arranged on top of insulators 516 and 503, an insulator 522 arranged on top of insulator 520, an insulator 524 arranged on top of insulator 522, an oxide 530a arranged on top of insulator 524, an oxide 530b arranged on top of oxide 530a, conductors 542a and 542b arranged spaced apart from each other on oxide 530b, an insulator 580 arranged on top of conductors 542a and 542b with an opening formed between conductors 542a and 542b, an oxide 530c arranged on the bottom and side surfaces of the opening, an insulator 550 arranged on the forming surface of oxide 530c, and a conductor 560 arranged on the forming surface of insulator 550. In this specification, conductors 542a and 542b are collectively referred to as conductor 542.

[0391] Furthermore, as shown in Figures 16A and 16B, it is preferable that an insulator 544 is placed between the oxide 530a, oxide 530b, conductor 542a, and conductor 542b and the insulator 580. Also, as shown in Figures 16A and 16B, it is preferable that the conductor 560 has a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a. Furthermore, as shown in Figures 16A and 16B, it is preferable that an insulator 574 is placed on top of the insulator 580, conductor 560, and insulator 550.

[0392] In the following, oxides 530a, 530b, and 530c may be collectively referred to as oxide 530.

[0393] While the transistor 500 shows a configuration in which three layers of oxide 530a, oxide 530b, and oxide 530c are stacked in the region where the channel is formed and in its vicinity, the present invention is not limited to this configuration. For example, a single layer of oxide 530b, a two-layer structure of oxide 530b and oxide 530a, a two-layer structure of oxide 530b and oxide 530c, or a stacked structure of four or more layers may be provided. Furthermore, while the conductor 560 is shown as a two-layer stacked structure in the transistor 500, the present invention is not limited to this configuration. For example, the conductor 560 may be a single-layer structure or a stacked structure of three or more layers. Also, the transistor 500 shown in Figures 14, 16A, and 16B is just an example, and the present invention is not limited to its structure; an appropriate transistor may be used depending on the circuit configuration, driving method, etc.

[0394] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode or drain electrode, respectively. As described above, the conductor 560 is formed to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. In other words, in the transistor 500, the gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing a positional margin, the occupied area of ​​the transistor 500 can be reduced. This enables miniaturization and high integration of semiconductor devices.

[0395] Furthermore, since the conductor 560 is formed self-aligned in the region between the conductors 542a and 542b, the conductor 560 does not have any region that overlaps with the conductors 542a or 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. Therefore, the switching speed of the transistor 500 can be improved, and it can be given high frequency characteristics.

[0396] Conductor 560 may function as a first gate (also called a top gate) electrode. Conductor 503 may function as a second gate (also called a bottom gate) electrode. In this case, the threshold voltage of transistor 500 can be controlled by changing the potential applied to conductor 503 independently of the potential applied to conductor 560, without linking them. In particular, by applying a negative potential to conductor 503, it is possible to make the threshold voltage of transistor 500 greater than 0V and reduce the off-current. Therefore, applying a negative potential to conductor 503 reduces the drain current when the potential applied to conductor 560 is 0V compared to not applying a negative potential.

[0397] The conductor 503 is positioned to overlap with the oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 connect, covering the channel-forming region formed in the oxide 530. In this specification, a transistor structure in which the channel-forming region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0398] Furthermore, the conductor 503 has a similar configuration to the conductor 518, with conductor 503a formed in contact with the inner walls of the openings of the insulators 514 and 516, and conductor 503b formed further inside. Although the transistor 500 shows a configuration in which conductors 503a and conductor 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or as a stacked structure of three or more layers.

[0399] Here, it is preferable to use a conductive material for the conductor 503a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (i.e., the above impurities are less permeable). Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen is less permeable). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or oxygen.

[0400] For example, the conductor 503a has a function of suppressing oxygen diffusion, which can prevent the conductor 503b from oxidizing and reducing its conductivity.

[0401] Furthermore, if the conductor 503 also functions as wiring, it is preferable that the conductor 503b be made of a highly conductive material mainly composed of tungsten, copper, or aluminum. Also, if the conductivity of the wiring can be maintained at a high level, the conductor 503a does not necessarily have to be provided. Although the conductor 503b is shown as a single layer, it may also be a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material.

[0402] Insulators 520, 522, and 524 function as second gate insulating films.

[0403] Here, it is preferable to use an insulator 524 that contains more oxygen than satisfactorily satisfactorily satisfactorily to contact the oxide 530. In other words, it is preferable that an excess oxygen region is formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, the oxygen deficiency in the oxide 530 can be reduced, and the reliability of the transistor 500 can be improved.

[0404] Specifically, as an insulator having an excess oxygen region, it is preferable to use an oxide material in which some of the oxygen is desorbed upon heating. An oxide that desorbs oxygen upon heating is one in which the amount of oxygen desorbed, converted to oxygen atoms, is 1.0 × 10⁻⁶ as determined by TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 Preferably 1.0 × 10 19 atoms / cm 3 More preferably 2.0 × 10 19 atoms / cm 3 The above, or 3.0 × 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0405] Furthermore, the insulator having the excess oxygen region described above and the oxide 530 may be brought into contact and subjected to one or more of the following treatments: heat treatment, microwave treatment, or RF treatment. By performing this treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction occurs in which the VoH bond is broken, in other words, "V O H→V O A reaction of "+H" occurs, allowing for dehydrogenation. Some of the hydrogen generated at this time may combine with oxygen to form H2O and be removed from oxide 530 or the insulator near oxide 530. In addition, some of the hydrogen may diffuse into or be captured (also called gettering) the conductors 542a and 542b.

[0406] Furthermore, the above microwave processing is preferably carried out using, for example, a device having a power supply that generates high-density plasma, or a device having a power supply that applies RF to the substrate side. For example, by using an oxygen-containing gas and a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. In addition, the above microwave processing should be carried out at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. In addition, as the gas introduced into the device for microwave processing, for example, oxygen and argon should be used, and the oxygen flow rate ratio (O2 / (O2+Ar)) should be 50% or less, preferably 10% to 30% or less.

[0407] Furthermore, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment while the surface of the oxide 530 is exposed. This heat treatment may be performed, for example, at a temperature of 100°C to 450°C, more preferably 350°C to 400°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby preventing oxygen deficiency (V OThis can reduce the amount of oxygen released. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0408] Furthermore, by performing an oxygenation treatment on oxide 530, oxygen deficiencies in oxide 530 are repaired by the supplied oxygen, or in other words, "V O This can accelerate the reaction "+O→null". Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 530, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 530 recombines with the oxygen vacancy and V O This can suppress the formation of H.

[0409] Furthermore, if the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function to suppress the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less permeable).

[0410] The insulator 522 has a function of suppressing the diffusion of oxygen, impurities, etc., so the oxygen contained in the oxide 530 does not diffuse toward the insulator 520, which is preferable. Furthermore, it is possible to suppress the reaction of the conductor 503 with the oxygen contained in the insulator 524 and the oxide 530.

[0411] The insulator 522 preferably uses a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulating film can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0412] In particular, it is preferable to use an insulator containing an oxide of either aluminum or hafnium, or both, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (the above-mentioned oxygen is less permeable). As an insulator containing an oxide of either aluminum or hafnium, or both, it is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When an insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the mixing of impurities such as hydrogen from the periphery of the transistor 500 into the oxide 530.

[0413] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated onto the above insulators.

[0414] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxide-nitride are suitable because they are thermally stable. Also, by combining a high-k material insulator with silicon oxide or silicon oxide-nitride, an insulator 520 with a thermally stable and high dielectric constant laminated structure can be obtained.

[0415] In Figures 16A and 16B, transistor 500 is shown with insulators 520, 522, and 524 as a second gate insulating film consisting of a three-layer laminated structure. However, the second gate insulating film may have a single-layer, two-layer, or four-layer or more laminated structure. In that case, it is not limited to a laminated structure made of the same material, but may also be a laminated structure made of different materials.

[0416] In transistor 500, it is preferable to use a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region. For example, as the oxide 530, a metal oxide such as In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) is preferable. In particular, the In-M-Zn oxide that can be applied as oxide 530 is preferably CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) or CAC-OS (Cloud-Aligned Composite Oxide Semiconductor). Alternatively, In-Ga oxide, In-Zn oxide, In oxide, etc., may be used as the oxide 530.

[0417] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for transistor 500. When the carrier concentration of the metal oxide is low, the impurity concentration in the metal oxide should be lowered to reduce the defect level density. In this specification, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0418] In particular, hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to form water, which can create oxygen vacancies in the metal oxide. Furthermore, if hydrogen enters an oxygen vacancy in oxide 530, the oxygen vacancy and hydrogen combine to form V O It may form H. O H can function as a donor, and electrons, which are carriers, can be generated. In addition, some hydrogen can combine with oxygen that is bonded to metal atoms, generating electrons, which are carriers. Therefore, transistors using metal oxides that contain a large amount of hydrogen tend to exhibit normally-on characteristics. Furthermore, since hydrogen in metal oxides is easily moved by stress such as heat and electric fields, the reliability of the transistor may deteriorate if the metal oxide contains a large amount of hydrogen. In one embodiment of the present invention, V in oxide 530 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. Thus, V O To obtain a metal oxide with sufficiently reduced H content, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration and dehydrogenation treatment) and to supply oxygen to the metal oxide to compensate for oxygen deficiency (sometimes referred to as oxygenation treatment). O By using metal oxides with sufficiently reduced impurities such as H in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0419] Defects where hydrogen fills an oxygen vacancy can function as donors for metal oxides. However, quantitatively evaluating such defects is difficult. Therefore, in metal oxides, evaluation is sometimes done using carrier concentration rather than donor concentration. Accordingly, in this specification, the carrier concentration, assuming no electric field is applied, may be used as a parameter for metal oxides, rather than the donor concentration. In other words, "carrier concentration" as described in this specification may sometimes be rephrased as "donor concentration."

[0420] Therefore, when using metal oxides in oxide 530, it is preferable that the hydrogen content in the metal oxide is reduced as much as possible. Specifically, in metal oxides, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 It should be less than [amount]. By using metal oxides with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0421] Furthermore, when a metal oxide is used for oxide 530, the metal oxide is a semiconductor with a high band gap, is intrinsic (also called type I), or substantially intrinsic, and the carrier concentration of the metal oxide in the channel-forming region is 1 × 10⁻⁶ 18 cm -3 Preferably less than 1 × 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 It is even more preferable that it be less than 1 × 10 12 cm -3 It is even more preferable that it be less than . There are no particular limitations on the lower limit of the carrier concentration of the metal oxide in the channel-forming region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0422] Furthermore, when a metal oxide is used for oxide 530, contact between conductors 542a and 542b and oxide 530 may cause oxygen in oxide 530 to diffuse into conductors 542a and 542b, leading to oxidation of conductors 542a and 542b. Oxidation of conductors 542a and 542b is highly likely to decrease their conductivity. Note that the diffusion of oxygen in oxide 530 into conductors 542a and 542b can be rephrased as conductors 542a and 542b absorbing oxygen in oxide 530.

[0423] Furthermore, oxygen in the oxide 530 may diffuse into the conductors 542a and 542b, forming a heterogeneous layer between the conductor 542a and the oxide 530b, and between the conductor 542b and the oxide 530b. Since this heterogeneous layer contains more oxygen than the conductors 542a and 542b, it is presumed to have insulating properties. In this case, the three-layer structure of the conductor 542a or 542b, the heterogeneous layer, and the oxide 530b can be considered a three-layer structure consisting of a metal-insulator-semiconductor, and may be referred to as an MIS (Metal-Insulator-Semiconductor) structure, or as a diode junction structure mainly composed of an MIS structure.

[0424] Furthermore, the above-mentioned heterogeneous layer is not limited to being formed between the conductors 542a and 542b and the oxide 530b. For example, the heterogeneous layer may be formed between the conductors 542a and 542b and the oxide 530c, or between the conductors 542a and 542b and the oxide 530b, or between the conductors 542a and 542b and the oxide 530c.

[0425] In oxide 530, it is preferable to use a metal oxide that functions as a channel-forming region and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0426] By having oxide 530a below oxide 530b, the diffusion of impurities from structures formed below oxide 530a to oxide 530b can be suppressed. Furthermore, by having oxide 530c above oxide 530b, the diffusion of impurities from structures formed above oxide 530c to oxide 530b can be suppressed.

[0427] Furthermore, it is preferable that oxide 530 has a layered structure comprising multiple oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for oxide 530a, it is preferable that the atomic ratio of element M in the constituent elements is greater than the atomic ratio of element M in the constituent elements of the metal oxide used for oxide 530b. Also, in the metal oxide used for oxide 530a, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, in the metal oxide used for oxide 530b, it is preferable that the atomic ratio of In to element M is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a. In addition, oxide 530c can be any metal oxide that can be used for oxide 530a or oxide 530b.

[0428] Specifically, for oxide 530a, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn = 1:3:4 or 1:1:0.5 may be used. For oxide 530b, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn = 4:2:3 or 1:1:1 may be used. For oxide 530c, a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn = 1:3:4 and an atomic ratio of Ga to Zn of Ga:Zn = 2:1 or Ga:Zn = 2:5 may be used. Furthermore, specific examples of layered structures using oxide 530c include layered structures with atomic ratios of In, Ga, and Zn of In:Ga:Zn=4:2:3 and In:Ga:Zn=1:3:4, layered structures with atomic ratios of Ga and Zn of Ga:Zn=2:1 and In, Ga, and Zn=4:2:3, layered structures with atomic ratios of Ga and Zn of Ga:Zn=2:5 and In, Ga, and Zn=4:2:3, and layered structures with gallium oxide and atomic ratios of In, Ga, and Zn=4:2:3.

[0429] Furthermore, for example, if the atomic ratio of In to element M in the metal oxide used for oxide 530a is smaller than the atomic ratio of In to element M in the metal oxide used for oxide 530b, then an In-Ga-Zn oxide can be used as oxide 530b, having an atomic ratio of In, Ga, and Zn such as In:Ga:Zn=5:1:6 or nearby, In:Ga:Zn=5:1:3 or nearby, or In:Ga:Zn=10:1:3 or nearby.

[0430] In addition to the compositions mentioned above, the oxide 530b can be a metal oxide having, for example, a composition of In:Zn=2:1, a composition of In:Zn=5:1, a composition of In:Zn=10:1, or a composition close to any one of these.

[0431] It is preferable to combine these oxides 530a, 530b, and 530c in a manner that satisfies the above-mentioned atomic ratio relationship. For example, it is preferable that oxides 530a and 530c be metal oxides having a composition of In:Ga:Zn = 1:3:4 or a composition close to it, and oxide 530b be a metal oxide having a composition of In:Ga:Zn = 4:2:3 to 4.1 or a composition close to it. Note that the above composition refers to the atomic ratio in the oxide formed on the substrate, or the atomic ratio in the sputtering target. Furthermore, increasing the ratio of In in the composition of oxide 530b is preferable because it can increase the on-current or field-effect mobility of the transistor.

[0432] Furthermore, it is preferable that the energy at the lower end of the conduction band of oxide 530a and oxide 530c is higher than the energy at the lower end of the conduction band of oxide 530b. In other words, it is preferable that the electron affinity of oxide 530a and oxide 530c is smaller than the electron affinity of oxide 530b.

[0433] Here, at the junctions of oxide 530a, oxide 530b, and oxide 530c, the energy level at the lower end of the conduction band changes smoothly. In other words, the energy level at the lower end of the conduction band at the junctions of oxide 530a, oxide 530b, and oxide 530c can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 530a and oxide 530b, and at the interface between oxide 530b and oxide 530c.

[0434] Specifically, a mixed layer with a low defect level density can be formed if oxide 530a and oxide 530b, and oxide 530b and oxide 530c, have a common element other than oxygen (as the main component). For example, if oxide 530b is In-Ga-Zn oxide, then In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc., can be used as oxide 530a and oxide 530c.

[0435] In this case, the primary carrier pathway is oxide 530b. By configuring oxides 530a and 530c as described above, the defect level density at the interface between oxide 530a and oxide 530b, and at the interface between oxide 530b and oxide 530c, can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 500 can obtain a high on-current.

[0436] Conductors 542a and 542b, which function as source electrodes and drain electrodes, are provided on the oxide 530b. It is preferable to use metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum as conductors 542a and 542b, or alloys composed of the above metallic elements, or alloys combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. In addition, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0437] Furthermore, although conductors 542a and 542b are shown as single-layer structures in Figures 16A and 16B, they may also be laminated structures of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Alternatively, a titanium film and an aluminum film may be laminated. In addition, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may also be used.

[0438] Furthermore, there are three-layer structures such as a titanium film or titanium nitride film, an aluminum film or copper film laminated on top of the titanium film or titanium nitride film, and a titanium film or titanium nitride film formed on top of that; and a molybdenum film or molybdenum nitride film, an aluminum film or copper film laminated on top of the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film formed on top of that. Transparent conductive materials containing indium oxide, tin oxide, or zinc oxide may also be used.

[0439] Furthermore, as shown in Figure 16A, regions 543a and 543b may be formed as low-resistance regions at and near the interface between the oxide 530 and the conductor 542a (conductor 542b). In this case, region 543a functions as either a source region or a drain region, and region 543b functions as either a source region or a drain region. In addition, a channel-forming region is formed in the region sandwiched between regions 543a and 543b.

[0440] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in region 543a (region 543b) may be reduced. In addition, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in region 543a (region 543b). In such cases, the carrier concentration in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region.

[0441] The insulator 544 is provided so as to cover the conductors 542a and 542b, thereby suppressing oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided so as to cover the respective sides of the oxide 530 and the insulator 524 and be in contact with the insulator 522.

[0442] As the insulator 544, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, or magnesium can be used. Alternatively, silicon nitride or silicon nitride can also be used as the insulator 544.

[0443] In particular, it is preferable to use an insulator 544 that contains an oxide of either aluminum or hafnium, or both, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is especially preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in a later process. Note that if the conductors 542a and 542b are made of oxidation-resistant materials, or if their conductivity does not significantly decrease even when oxygen is absorbed, the insulator 544 is not an essential component. It can be designed appropriately according to the desired transistor characteristics.

[0444] The presence of the insulator 544 suppresses the diffusion of water and other impurities such as hydrogen contained in the insulator 580 to the oxide 530b via the oxide 530c and insulator 550. Furthermore, it suppresses the oxidation of the conductor 560 due to excess oxygen present in the insulator 580.

[0445] The insulator 550 functions as a first gate insulating film. It is preferable that the insulator 550 is placed in contact with the inside (top surface and side surface) of the oxide 530c. It is preferable that the insulator 550 is formed using an insulator that contains an excess of oxygen and releases oxygen upon heating, similar to the insulator 524 described above.

[0446] Specifically, silicon oxide with excess oxygen, silicon oxide-nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide can be used. Silicon oxide and silicon oxide-nitride are particularly preferred because they are stable to heat.

[0447] By providing an insulator 550, which releases oxygen upon heating, in contact with the upper surface of oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel-forming region of oxide 530b through oxide 530c. Furthermore, similar to the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The film thickness of the insulator 550 is preferably between 1 nm and 20 nm.

[0448] Furthermore, in order to efficiently supply excess oxygen from the insulator 550 to the oxide 530, a metal oxide may be provided between the insulator 550 and the conductor 560. It is preferable that the metal oxide suppresses the diffusion of oxygen from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, the reduction in the amount of excess oxygen supplied to the oxide 530 can be suppressed. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, any material that can be used for the insulator 544 may be used.

[0449] Furthermore, the insulator 550 may have a multilayer structure, similar to the second gate insulating film. As transistors become smaller and more integrated, thinning of the gate insulating film can lead to problems such as leakage current. Therefore, by using a multilayer structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a multilayer structure that is thermally stable and has a high dielectric constant can be achieved.

[0450] The conductor 560, which functions as the first gate electrode, is shown as a two-layer structure in Figures 16A and 16B, but it may also be a single-layer structure or a stacked structure of three or more layers.

[0451] It is preferable to use a conductive material for the conductor 560a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules). By having the function of suppressing the diffusion of oxygen in the conductor 560a, it is possible to suppress the oxidation of the conductor 560b by the oxygen contained in the insulator 550, which reduces the conductivity. As a conductive material that has the function of suppressing the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Furthermore, an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, by depositing the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0452] Furthermore, it is preferable that the conductor 560b is made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductor 560b functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 560b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0453] The insulator 580 is provided on the conductors 542a and 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and porous silicon oxide are particularly preferred because they can easily form an excess oxygen region in a later process.

[0454] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580, which releases oxygen upon heating, in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

[0455] The opening in the insulator 580 is formed superimposed on the region between the conductors 542a and 542b. As a result, the conductor 560 is formed to be embedded in the opening in the insulator 580 and in the region sandwiched between the conductors 542a and 542b.

[0456] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to ensure that the conductivity of the conductor 560 does not decrease. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may take on a shape with a high aspect ratio. In this embodiment, since the conductor 560 is embedded in the opening of the insulator 580, even if the conductor 560 has a shape with a high aspect ratio, it can be formed without the conductor 560 collapsing during the manufacturing process.

[0457] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. By forming the insulator 574 by sputtering, an excess oxygen region can be created in the insulator 550 and the insulator 580. This allows oxygen to be supplied to the oxide 530 from the excess oxygen region.

[0458] For example, as the insulator 574, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0459] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in thin films between 0.5 nm and 3.0 nm in thickness. Therefore, aluminum oxide deposited by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0460] Furthermore, it is preferable to provide an insulator 581 that functions as an interlayer film on top of the insulator 574. Similar to the insulator 524, it is preferable that the insulator 581 has a reduced concentration of impurities such as water or hydrogen in the film.

[0461] Furthermore, conductors 540a and 540b are placed in the openings formed in insulators 581, 574, 580, and 544. Conductors 540a and 540b are provided facing each other with conductor 560 in between. Conductors 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.

[0462] An insulator 582 is provided on the insulator 581. It is preferable to use a material that has barrier properties against oxygen, hydrogen, etc. for the insulator 582. Therefore, the same material as the insulator 514 can be used for the insulator 582. For example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide for the insulator 582.

[0463] In particular, aluminum oxide exhibits a high barrier effect, preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical properties of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen and moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0464] Furthermore, an insulator 586 is provided on the insulator 582. The insulator 586 can be made of the same material as the insulator 320. By applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wirings can be reduced. For example, silicon oxide films, silicon oxynitride films, etc., can be used as the insulator 586.

[0465] Furthermore, conductors 546 and 548, etc., are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0466] Conductors 546 and 548 function as plugs or wires for connecting to the capacitive element 600, transistor 500, or transistor 300. Conductors 546 and 548 can be provided using the same materials as conductors 328 and 330.

[0467] Furthermore, after the formation of the transistor 500, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By enclosing the transistor 500 with the above-mentioned high-barrier insulator, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be encased together with an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, forming an opening that reaches the insulator 514 or insulator 522, and forming the above-mentioned high-barrier insulator in contact with the insulator 514 or insulator 522 is preferable because it can also serve as part of the manufacturing process for the transistor 500. For example, the same material as insulator 522 may be used as the insulator with high barrier properties against hydrogen or water.

[0468] Next, a capacitive element 600 is provided above the transistor 500. The capacitive element 600 has a conductor 610, a conductor 620, and an insulator 630.

[0469] Furthermore, a conductor 612 may be provided on the conductors 546 and 548. The conductor 612 functions as a plug or wiring for connecting to the transistor 500. The conductor 610 functions as an electrode for the capacitive element 600. Note that the conductors 612 and 610 can be formed simultaneously.

[0470] The conductors 612 and 610 can be a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) composed of the above elements. Alternatively, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added can also be used.

[0471] In Figure 14, the conductors 612 and 610 are shown as single-layer structures, but the configuration is not limited to this, and a laminated structure of two or more layers is also possible. For example, a conductor with high adhesion to both the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0472] A conductor 620 is provided so as to cover the region that overlaps with the conductor 610 via an insulator 630. The conductor 620 can be made of a conductive material such as a metal, alloy, or metal oxide. It is preferable to use a high-melting-point material such as tungsten or molybdenum that provides both heat resistance and conductivity, and tungsten is particularly preferred. When forming the conductor simultaneously with other structures, low-resistance metallic materials such as Cu (copper) or Al (aluminum) may be used.

[0473] An insulator 650 is provided on the conductor 620 and the insulator 630. The insulator 650 can be provided using the same material as the insulator 320. The insulator 650 may also function as a planarizing film that covers the uneven shape below it.

[0474] By using this structure, fluctuations in electrical characteristics and reliability can be suppressed in semiconductor devices using transistors with oxide semiconductors. Alternatively, miniaturization or high integration can be achieved in semiconductor devices using transistors with oxide semiconductors.

[0475] In addition, one embodiment of the present invention may have a configuration in which another semiconductor substrate on which a circuit is formed is bonded below the substrate 311 on which the transistor 300 is formed. Figure 17 shows a configuration in which layer SA, which is part of the semiconductor device of Figure 14, and layer SB, on which a circuit is formed, are bonded together. Specifically, the semiconductor device shown in Figure 17 has a configuration in which a substrate 211 on which the circuit and the like are formed, which are included in layer SB, are bonded below the substrate 311 included in layer SA. Note that in Figure 17, the conductor, insulator, etc. above the insulator 360 in layer SA are omitted.

[0476] On substrate 211, as an example, insulators 220, 222, 224, 226, and 230 are provided in order to cover the transistor 200, similar to the transistor 300 on substrate 311.

[0477] Furthermore, for insulators 220, 222, 224, 226, 230, and 231, materials applicable to insulators 320, 322, 324, 326, and 230 can be used. Also, for insulators 220, 222, 224, 226, 230, and 231 can be formed by the same process as for insulators 320, 322, 324, 326, and 350.

[0478] Furthermore, insulators 220, 222, 224, and 226 have conductors 228 and 229 embedded within them. Conductors 228 and 229, like conductors 328 and 330, function as plugs or wiring. In addition, materials applicable to conductors 328 and 330 can be used for conductors 228 and 229.

[0479] The insulator 232 functions as a bonding layer to the insulator 341, which is located below the substrate 311, as will be described later. In addition, a conductor 233 is embedded in the insulators 231 and 232 so as to be electrically connected to a portion of the conductor 229, and the conductor 233 also functions as part of the bonding layer.

[0480] As the insulator 232, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, titanium nitride, etc. can be used.

[0481] For example, the conductor 233 can be copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold. It is preferable to use copper, aluminum, tungsten, or gold due to their ease of bonding with the conductor 342, which will be described later.

[0482] The conductor 233 may have a multilayer structure including multiple layers. For example, a first conductor may be formed on the sides of the insulators 231 and 232, and then a second conductor may be formed to fill the openings in the insulators 231 and 232. As the first conductor, for example, a conductor having barrier properties against hydrogen, such as tantalum nitride, can be used, and as the second conductor, for example, highly conductive tungsten can be used.

[0483] Furthermore, an insulator 341 is formed beneath the substrate 311 included in layer SA. The insulator 341 functions as a bonding layer to the insulator 232 on the substrate 211.

[0484] For example, any material applicable to the insulator 232 can be used as the insulator 341. In particular, it is preferable that the insulator 232 and the insulator 341 are composed of the same components in order to join the insulator 232 and the insulator 341.

[0485] In layer SA, the insulator 341, substrate 311, insulator 320, and insulator 322 have a conductor 342 embedded in them so as to be electrically connected to a portion of the conductor 330, and the conductor 342 also functions as part of the bonding layer.

[0486] For example, any material applicable to the conductor 233 can be used as the conductor 342. In particular, it is preferable that the conductor 342 and the conductor 233 be made of the same metallic material in order to join them together.

[0487] The conductor 342 may have a multilayer structure including multiple layers. For example, a first conductor may be formed on the sides of the insulator 341, substrate 311, insulator 320, and insulator 322, and then a second conductor may be formed to fill the openings in the insulator 341, substrate 311, insulator 320, and insulator 322. As the first conductor, for example, a conductor having barrier properties against hydrogen, such as tantalum nitride, can be used, and as the second conductor, for example, highly conductive tungsten can be used.

[0488] Next, we will explain the bonding of layer SA and layer SB.

[0489] In the pre-processing step before bonding layer SA and layer SB, the surfaces of the insulator 226 and conductor 229 in layer SB are planarized so that their heights are the same. Similarly, the surfaces of the insulator 341 and conductor 342 in layer SA are planarized so that their heights are the same.

[0490] In the bonding process, when joining insulator 232 and insulator 341, that is, joining insulating layers, a hydrophilic bonding method can be used. This method involves first providing high flatness through polishing, then bringing the surfaces that have been hydrophilically treated with oxygen plasma or the like into contact for temporary bonding, followed by dehydration through heat treatment to perform the final bonding. Since the hydrophilic bonding method also involves bonding at the atomic level, a mechanically superior bond can be obtained.

[0491] Furthermore, when joining conductor 233 and conductor 342, that is, joining conductors to each other, a surface activation bonding method can be used, in which the oxide film and adsorbed impurity layer on the surface are removed by sputtering or other methods, and the cleaned and activated surfaces are brought into contact for bonding. Alternatively, a diffusion bonding method can be used, which uses both temperature and pressure to bond the surfaces. In both cases, bonding occurs at the atomic level, so a bonding method that is excellent not only electrically but also mechanically can be obtained.

[0492] By performing the bonding process described above, the conductor 342 contained in layer SA can be electrically connected to the conductor 233 contained in layer SB. Furthermore, a mechanically strong connection can be obtained between the insulator 341 contained in layer SA and the insulator 232 contained in layer SB.

[0493] When bonding layers SA and SB, insulating and metal layers are present at each bonding surface; therefore, a combination of surface activation bonding and hydrophilic bonding methods can be used.

[0494] For example, a method can be used in which the surface is cleaned after polishing, an anti-oxidation treatment is applied to the surface of the metal layer, and then a hydrophilic treatment is performed before joining. Alternatively, the surface of the metal layer may be made of a metal that is difficult to oxidize, such as gold, and then a hydrophilic treatment may be performed. In addition, joining methods other than those described above may also be used.

[0495] By using the bonding process described above, additional circuits can be added to a semiconductor device. Therefore, the increase in the circuit area of ​​the semiconductor device can be suppressed. Furthermore, this bonding process allows for the electrical connection of other semiconductor devices (e.g., logic circuits, signal conversion circuits, potential level conversion circuits, current sources, voltage sources, switching circuits, amplification circuits, photoelectric conversion circuits, arithmetic circuits, etc.) to the semiconductor device. Therefore, novel semiconductor devices can be constructed.

[0496] As an example, a transistor 200 is formed on the substrate 211 included in layer SB. In Figure 17, as an example, transistor 200 is shown with the same structure as transistor 300, but transistor 200 may have a different structure from transistor 300. For example, as shown in Figure 18, transistor 200 may have the same structure as transistor 500 shown in Figure 16 as an OS transistor. As for the substrate 212 shown in Figure 18, for example, a substrate applicable to the substrate 312 of the semiconductor device shown in Figure 15 can be used.

[0497] Next, we will describe another example of an OS transistor configuration, as shown in Figures 14 and 15.

[0498] Figures 19A and 19B show modified versions of the transistor 500 shown in Figures 16A and 16B, respectively. Figure 19A is a cross-sectional view of the transistor 500 in the channel length direction, and Figure 19B is a cross-sectional view of the transistor 500 in the channel width direction. The configurations shown in Figures 19A and 19B can also be applied to other transistors in a semiconductor device according to one embodiment of the present invention, such as transistor 300.

[0499] The transistor 500 with the configuration shown in Figures 19A and 19B differs from the transistor 500 with the configuration shown in Figures 16A and 16B in that it has insulators 402 and 404. It also differs from the transistor 500 with the configuration shown in Figures 16A and 16B in that an insulator 552 is provided in contact with the side surface of the conductor 540a, and an insulator 552 is provided in contact with the side surface of the conductor 540b. Furthermore, it differs from the transistor 500 with the configuration shown in Figures 16A and 16B in that it does not have an insulator 520.

[0500] In the transistor 500 with the configuration shown in Figures 19A and 19B, an insulator 402 is provided on an insulator 512. In addition, an insulator 404 is provided on an insulator 574 and on an insulator 402.

[0501] In the transistor 500 with the configuration shown in Figures 19A and 19B, insulators 514, 516, 522, 524, 544, 580, and 574 are provided, and insulator 404 covers them. In other words, insulator 404 is in contact with the top surface of insulator 574, the side surface of insulator 574, the side surface of insulator 580, the side surface of insulator 544, the side surface of insulator 524, the side surface of insulator 522, the side surface of insulator 516, the side surface of insulator 514, and the top surface of insulator 402, respectively. As a result, oxides 530 and the like are isolated from the outside by insulators 404 and 402.

[0502] It is preferable that insulators 402 and 404 have a high ability to suppress the diffusion of hydrogen (for example, at least one such as a hydrogen atom or hydrogen molecule) or water molecules. For example, it is preferable to use silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties, as insulators 402 and 404. This makes it possible to suppress the diffusion of hydrogen, etc., into the oxide 530, and thus suppress the deterioration of the characteristics of the transistor 500. Therefore, the reliability of a semiconductor device according to one embodiment of the present invention can be improved.

[0503] The insulator 552 is provided in contact with the insulators 581, 404, 574, 580, and 544. Preferably, the insulator 552 has the function of suppressing the diffusion of hydrogen or water molecules. For example, it is preferable to use an insulator 552 that has high hydrogen barrier properties, such as silicon nitride, aluminum oxide, or silicon nitride oxide. In particular, silicon nitride is a material with high hydrogen barrier properties, so it is suitable for use as the insulator 552. By using a material with high hydrogen barrier properties as the insulator 552, it is possible to suppress the diffusion of impurities such as water or hydrogen from the insulator 580, etc., through the conductors 540a and 540b to the oxide 530. In addition, it is possible to suppress the absorption of oxygen contained in the insulator 580 by the conductors 540a and 540b. As a result, the reliability of the semiconductor device according to one embodiment of the present invention can be improved.

[0504] Furthermore, the transistor 500 shown in Figures 19A and 19B may have its configuration changed depending on the circumstances. For example, the transistor 500 in Figures 19A and 19B can be modified to the transistor shown in Figures 20A and 20B. Figure 20A is a cross-sectional view of the transistor in the channel length direction, and Figure 20B is a cross-sectional view of the transistor in the channel width direction. The transistors shown in Figures 20A and 20B differ from the transistors shown in Figures 19A and 19B in that the oxide 530c has a two-layer structure of oxide 530c1 and oxide 530c2.

[0505] Oxide 530c1 is in contact with the top surface of insulator 524, the side surface of oxide 530a, the top and side surfaces of oxide 530b, the side surfaces of conductors 542a and 542b, the side surface of insulator 544, and the side surface of insulator 580. Oxide 530c2 is in contact with insulator 550.

[0506] For example, an In-Zn oxide can be used as oxide 530c1. Furthermore, for oxide 530c2, a material similar to the material that can be used for oxide 530c when oxide 530c has a single-layer structure can be used. For example, as oxide 530c2, a metal oxide with an atomic ratio of In:Ga:Zn=1:3:4, Ga:Zn=2:1, or Ga:Zn=2:5 can be used.

[0507] By making oxide 530c a two-layer structure of oxide 530c1 and oxide 530c2, the on-current of the transistor can be increased compared to when oxide 530c is a single-layer structure. Therefore, the transistor can be used, for example, as a power MOS transistor. Note that the oxide 530c in the transistors with the configurations shown in Figures 16A and 16B can also be a two-layer structure of oxide 530c1 and oxide 530c2.

[0508] The transistors with the configurations shown in Figures 20A and 20B can be applied, for example, to the transistor 300 shown in Figures 14 and 15. Furthermore, as mentioned above, the transistor 300 can be applied to transistors included in the semiconductor device described in the above embodiment, such as arithmetic circuits MAC1, MAC2, MAC3, MAC4, etc. Note that the transistors shown in Figures 20A and 20B can also be applied to transistors other than transistor 300 and transistor 500 in the semiconductor device according to one aspect of the present invention.

[0509] Next, we will describe the capacitive elements that can be applied to the semiconductor devices shown in Figures 14 and 15.

[0510] Figure 21 shows a capacitive element 600A as an example of a capacitive element 600 applicable to the semiconductor device shown in Figures 14 and 15. Figure 21A is a top view of the capacitive element 600A, Figure 21B is a perspective view showing a cross-section of the capacitive element 600A along the dashed line L3-L4, and Figure 21C is a perspective view showing a cross-section of the capacitive element 600A along the dashed line W3-L4.

[0511] The conductor 610 functions as one of the pair of electrodes of the capacitive element 600A, and the conductor 620 functions as the other of the pair of electrodes of the capacitive element 600A. The insulator 630 functions as a dielectric sandwiched between the pair of electrodes.

[0512] For example, the insulator 630 can be silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium oxide nitride, hafnium nitride, zirconium oxide, etc., and can be provided in a laminated or single layer.

[0513] In this specification, hafnium oxidoxide refers to a material in which the oxygen content is greater than the nitrogen content, and hafnium oxide nitride refers to a material in which the nitrogen content is greater than the oxygen content.

[0514] Furthermore, for example, the insulator 630 may be a laminated structure of a material with high dielectric strength, such as silicon oxidnitride, and a high dielectric constant (high-k) material. With this configuration, the capacitive element 600A can secure sufficient capacitance by having a high dielectric constant (high-k) insulator, and the dielectric strength is improved by having an insulator with high dielectric strength, thereby suppressing electrostatic discharge breakdown of the capacitive element 600A.

[0515] Examples of high-dielectric constant (high-k) materials (materials with a high relative permittivity) that serve as insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0516] Alternatively, the insulator 630 may be a single-layer or multi-layer insulator containing a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). For example, when the insulator 630 is multi-layered, a three-layer laminate of zirconium oxide, aluminum oxide, and zirconium oxide in that order, or a four-layer laminate of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in that order may be used. In addition, a compound containing hafnium and zirconium may be used as the insulator 630. As semiconductor devices become smaller and more integrated, thinning of the dielectric material used for gate insulators and capacitive elements may cause problems such as leakage current in transistors and capacitive elements. By using high-k materials as insulators that function as dielectrics in gate insulators and capacitive elements, it becomes possible to reduce the gate potential during transistor operation and ensure the capacitance of capacitive elements while maintaining the physical film thickness.

[0517] Capacitive element 600 is electrically connected to conductors 546 and 548 at the lower part of conductor 610. Conductors 546 and 548 function as plugs or wires for connecting to other circuit elements. In Figures 21A to 21C, conductors 546 and 548 are collectively referred to as conductor 540.

[0518] Furthermore, in Figure 21, for the sake of clarity, the insulator 586 in which the conductors 546 and 548 are embedded, and the insulator 650 covering the conductors 620 and insulator 630 are omitted.

[0519] Although the capacitive elements 600 shown in Figures 14, 15, and 21A to 21C are planar type, the shape of the capacitive elements is not limited to this. For example, the capacitive element 600 may be a cylindrical capacitive element 600B as shown in Figures 22A to 22C.

[0520] Figure 22A is a top view of the capacitive element 600B, Figure 22B is a cross-sectional view of the capacitive element 600B along the dashed line L3-L4, and Figure 22C is a perspective view showing a cross-section of the capacitive element 600B along the dashed line W3-L4.

[0521] In Figure 22B, the capacitive element 600B includes an insulator 631 on an insulator 586 in which a conductor 540 is embedded, an insulator 651 having an opening, a conductor 610 that functions as one of a pair of electrodes, and a conductor 620 that functions as the other of a pair of electrodes.

[0522] Furthermore, in Figure 22C, insulators 586, 650, and 651 are omitted for clarity.

[0523] For example, the same material as that used for insulator 586 can be used for insulator 631.

[0524] Furthermore, a conductor 611 is embedded in the insulator 631 so as to be electrically connected to the conductor 540. The conductor 611 can be made of the same material as the conductors 330 and 518, for example.

[0525] For example, the same material as that used for insulator 586 can be used for insulator 651.

[0526] Furthermore, as described above, the insulator 651 has an opening, and this opening is superimposed on the conductor 611.

[0527] The conductor 610 is formed at the bottom and side of the opening. In other words, the conductor 610 is superimposed on the conductor 611 and is electrically connected to the conductor 611.

[0528] The method for forming the conductor 610 involves creating openings in the insulator 651 by etching or the like, and then depositing the conductor 610 by sputtering, ALD, or the like. After that, the conductor 610 deposited on the insulator 651 can be removed by CMP (Chemichal Mechanical Polishing) or the like, leaving the conductor 610 deposited in the openings.

[0529] The insulator 630 is located on the insulator 651 and on the forming surface of the conductor 610. The insulator 630 functions as a dielectric sandwiched between a pair of electrodes in the capacitive element.

[0530] The conductor 620 is formed on the insulator 630 such that it fills the opening in the insulator 651.

[0531] The insulator 650 is formed to cover the insulator 630 and the conductor 620.

[0532] The cylindrical capacitive element 600B shown in Figure 22 can achieve a higher capacitance value than the planar capacitive element 600A.

[0533] Furthermore, in one embodiment of the present invention, a photoelectric conversion element may be provided above the capacitive element 600 of the semiconductor device shown in Figures 14 and 15. In other words, one embodiment of the present invention may be a semiconductor device that includes the arithmetic circuit MAC1 described in the above embodiment and a photoelectric conversion element.

[0534] Photoelectric conversion elements have the function of inducing an electric current in response to incident light. By utilizing this property, an imaging device can be obtained by arranging multiple photoelectric conversion elements, for example, in a matrix.

[0535] By combining the arithmetic circuits MAC1, MAC2, MAC3, MAC4, etc., described in the above embodiment with an imaging device, for example, image information captured by the imaging device can be input to the arithmetic circuits as second data. In other words, a sum-of-products operation can be performed between the image information and the first data. In particular, by using the first data as a filter value, convolution processing of the image information can be performed. Furthermore, by combining the imaging device with the arithmetic circuit MAC4, etc., a configuration can be created that repeatedly performs convolution processing. By utilizing this configuration, calculations of a convolutional neural network (CNN) can be performed.

[0536] Figure 23 shows an example of a semiconductor device configuration in which a photoelectric conversion element 700 is provided above the capacitive element 600 in Figure 14. Note that the photoelectric conversion element 700 may be provided below the transistor 300 instead of above the capacitive element 600.

[0537] The photoelectric conversion element 700, as an example, has layers 767a, 767b, 767c, 767d, and 767e.

[0538] The photoelectric conversion element 700 shown in Figure 23 is an example of an organic photoconductive film, where layer 767a is the lower electrode, layer 767e is the light-transmitting upper electrode, and layers 767b, 767c, and 767d correspond to the photoelectric conversion section. Alternatively, the photoelectric conversion element 700 shown in Figure 23 may be replaced with, for example, a pn junction photodiode or an avalanche photodiode.

[0539] The lower electrode layer 767a can be either the anode or the cathode, and the upper electrode layer 767b can be either the anode or the cathode. In this embodiment, layer 767a is the cathode and layer 767b is the anode.

[0540] For layer 767a, it is preferable to use, for example, a low-resistance metal layer. Specifically, for layer 767a, for example, aluminum, titanium, tungsten, tantalum, silver, or a lamination thereof can be used.

[0541] For layer 767e, it is preferable to use a conductive layer that has high light transmittance to visible light, for example. Specifically, for layer 767e, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, or graphene can be used. Note that a configuration in which layer 767e is omitted is also possible.

[0542] In the photoelectric conversion section, either layer 767b or layer 767d can be a hole transport layer, and the other can be an electron transport layer. Additionally, layer 767c can be a photoelectric conversion layer.

[0543] For the hole transport layer, for example, molybdenum oxide can be used. For the electron transport layer, for example, C 60 , C 70 Fullerenes such as those mentioned above, or their derivatives, can be used.

[0544] As the photoelectric conversion layer, a mixed layer of n-type organic semiconductors and p-type organic semiconductors (bulk heterojunction structure) can be used.

[0545] In the semiconductor device shown in Figure 23, the insulator 751 is provided on the insulator 650, and the layer 767a is provided on the insulator 751. The insulator 752 is provided on both the insulator 751 and the layer 767a. The layer 767b is provided on both the insulator 752 and the layer 767a.

[0546] Furthermore, layers 767c, 767d, 767e, and an insulator 753 are stacked in order on layer 767b.

[0547] The insulator 751 functions, for example, as an interlayer insulating film. It is preferable to use an insulator 751 that has hydrogen barrier properties, similar to insulator 324. By using an insulator 751 that has hydrogen barrier properties, the diffusion of hydrogen into the transistor 500 can be suppressed. Therefore, as an example, a material applicable to insulator 324 can be used for insulator 751.

[0548] The insulator 752 functions, for example, as an element isolation layer. Although not shown in the figure, the insulator 752 is provided to prevent short circuits with other photoelectric conversion elements located nearby. It is preferable to use an organic insulator, for example, as the insulator 752.

[0549] The insulator 753 functions, for example, as a translucent planarization film. As the insulator 753, materials such as silicon oxide, silicon oxide nitride, silicon nitride, and silicon nitride can be used.

[0550] Above the insulator 753, for example, a light-shielding layer 771, an optical conversion layer 772, and a microlens array 773 are provided.

[0551] The light-shielding layer 771 provided on the insulator 753 can suppress the inflow of light to adjacent pixels. The light-shielding layer 771 can be made of a metal layer such as aluminum or tungsten. Alternatively, a dielectric film having the function of an anti-reflective coating may be laminated with the metal layer.

[0552] A color filter can be used in the optical conversion layer 772, which is provided on the insulator 753 and the light-shielding layer 771. By assigning colors such as red (G), green (G), blue (B), yellow (Y), cyan (C), and magenta (M) to each pixel in the color filter, a color image can be obtained.

[0553] Furthermore, by using a wavelength cut filter in the optical conversion layer 772, a semiconductor device can be created that can obtain images in various wavelength ranges.

[0554] For example, the semiconductor device shown in Figure 23 can function as an infrared imaging device by using a filter in the optical conversion layer 772 that blocks light with wavelengths below the visible light spectrum. Furthermore, the semiconductor device shown in Figure 23 can function as a far-infrared imaging device by using a filter in the optical conversion layer 772 that blocks light with wavelengths below the near-infrared spectrum. Additionally, the semiconductor device shown in Figure 23 can function as an ultraviolet imaging device by using a filter in the optical conversion layer 772 that blocks light with wavelengths above the visible light spectrum.

[0555] Furthermore, the semiconductor device shown in Figure 23 can function as an imaging device that obtains images visualizing the intensity of radiation, such as those used in X-ray imaging devices, by using a scintillator in the optical conversion layer 772. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light and ultraviolet light through the photoluminescence phenomenon. Image data is then acquired by detecting this light with the photoelectric conversion element 700. Alternatively, a semiconductor device with this configuration may be used in radiation detectors, etc.

[0556] Scintillators contain substances that, when irradiated with radiation such as X-rays and gamma rays, absorb energy and emit visible light and ultraviolet light. For example, scintillators can be made by dispersing substances such as Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, and ZnO in resins, ceramics, etc.

[0557] A microlens array 773 is provided on the light-shielding layer 771 and on the optical conversion layer 772. Light passing through each lens of the microlens array 773 passes through the optical conversion layer 772 directly below and irradiates the photoelectric conversion element 700. By providing the microlens array 773, the focused light can be incident on the photoelectric conversion element 700, thereby enabling efficient photoelectric conversion. The microlens array 773 is preferably formed of a resin or glass with high light transmittance to visible light.

[0558] Incidentally, Figure 23 shows a configuration of a semiconductor device in which a photoelectric conversion element 700 using an organic photoconductive film is provided above transistors 300 and 500, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, the semiconductor device according to one aspect of the present invention may have a configuration in which a back-illuminated, pn-junction type photoelectric conversion element is provided instead of the photoelectric conversion element 700.

[0559] Figure 24 shows an example of a semiconductor device configuration in which a back-illuminated, pn-junction type photoelectric conversion element 700A is provided above transistors 300 and 500 in Figure 14. The semiconductor device shown in Figure 24 has a structure SC having the photoelectric conversion element 700A bonded to a substrate 311 on which transistors 300, 500 and capacitive element 600 are provided.

[0560] The structure SC includes a light-shielding layer 771, an optical conversion layer 772, and a microlens array 773. For explanations of these components, please refer to the explanations above.

[0561] The photoelectric conversion element 700A is a pn junction type photodiode formed on a silicon substrate, and has a layer 765b corresponding to the p-type region and a layer 765a corresponding to the n-type region. The photoelectric conversion element 700A is an embedded type photodiode, and the dark current can be suppressed and noise reduced by a thin p-type region (part of layer 765b) provided on the surface side (current extraction side) of layer 765a.

[0562] Insulator 701, conductor 741, and conductor 742 function as bonding layers. Insulator 754 functions as an interlayer insulating film and planarization film. Insulator 755 functions as an element isolation layer. Insulator 756 has the function of suppressing carrier outflow.

[0563] The silicon substrate is provided with grooves to separate the pixels, and the insulator 756 is provided on the upper surface of the silicon substrate and in these grooves. The provision of the insulator 756 prevents carriers generated in the photoelectric conversion element 700A from flowing out to adjacent pixels. The insulator 756 also has the function of suppressing the intrusion of stray light. Therefore, the insulator 756 can suppress color mixing. An anti-reflective film may be provided between the upper surface of the silicon substrate and the insulator 756.

[0564] The element isolation layer can be formed using the LOCOS (LOCal Oxidation of Silicon) method, or it may be formed using the STI (Shallow Trench Isolation) method, etc. As the insulator 756, for example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic can be used. The insulator 756 may also have a multilayer structure.

[0565] Layer 765a (n-type region, corresponding to the cathode) of the photoelectric conversion element 700A is electrically connected to the conductor 741. Layer 765b (p-type region, corresponding to the anode) is electrically connected to the conductor 742. Conductors 741 and 742 have regions embedded in the insulator 701. In addition, the surfaces of the insulator 701, conductor 741, and conductor 742 are flattened so that their heights are the same.

[0566] Above the insulator 650, insulators 691 and 692 are stacked in order. Insulators 691 and 692 also have openings, and a conductor 743 is formed to fill these openings.

[0567] For example, the insulator 691 can be made from a material that is applicable to the insulator 751.

[0568] Furthermore, as the insulator 692, for example, a material applicable to the insulator 650 can be used.

[0569] Insulator 693 and insulator 701 each function as part of the bonding layer. Conductors 741, 742, and 743 also each function as part of the bonding layer.

[0570] For example, silicon oxide, silicon oxide-nitride, silicon nitride, silicon nitride, titanium nitride, etc., can be used as insulators 693 and 701. In particular, it is preferable that insulators 693 and 701 are composed of the same components in order to join them together.

[0571] For example, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold can be used as conductors 741, 742, and 743. In particular, it is preferable to use copper, aluminum, tungsten, or gold to facilitate the joining of conductors 741 and 743, and conductors 742 and 743.

[0572] Furthermore, the conductors 741, 742, and 743 may have a multilayer structure including multiple layers. For example, a first conductor may be formed on the side surface of an opening in which conductors 741, 742, or 743 are provided, and then a second conductor may be formed to fill the opening. As the first conductor, for example, a conductor having barrier properties against hydrogen, such as tantalum nitride, can be used, and as the second conductor, for example, highly conductive tungsten can be used.

[0573] In the pre-processing step for bonding the bonding layer on the substrate 311 side to the bonding layer on the structure SC side, the surfaces of the insulator 693 and the conductor 743 on the substrate 311 side are flattened so that their heights are the same. Similarly, on the structure SC side, the surfaces of the insulator 701, the conductor 741, and the conductor 742 are flattened so that their heights are the same.

[0574] In the bonding process, when joining insulator 693 and insulator 701, that is, joining insulating layers, a hydrophilic bonding method can be used. This method involves first providing high flatness through polishing, then bringing the surfaces that have been hydrophilically treated with oxygen plasma or the like into contact for temporary bonding, followed by dehydration through heat treatment to perform the final bonding. Since the hydrophilic bonding method also involves bonding at the atomic level, a mechanically superior bond can be obtained.

[0575] Furthermore, when joining conductor 741 and conductor 743, or conductor 742 and conductor 743, that is, when joining conductors to conductors, a surface activation bonding method can be used, in which the oxide film and adsorbed impurity layer on the surface are removed by sputtering or other methods, and the cleaned and activated surfaces are brought into contact for bonding. Alternatively, a diffusion bonding method can be used, which uses both temperature and pressure to bond the surfaces. In both cases, bonding occurs at the atomic level, so a bonding method that is excellent not only electrically but also mechanically can be obtained.

[0576] By performing the bonding process described above, the conductor 743 on the substrate 311 side can be electrically connected to the conductors 741 and 742 on the structure SC side. Furthermore, a mechanically strong connection can be obtained between the insulator 693 on the substrate 311 side and the insulator 701 on the structure SC side.

[0577] When bonding the substrate 311 and the structure SC, insulating layers and metal layers are present on each bonding surface, so for example, a combination of surface activation bonding and hydrophilic bonding methods may be used.

[0578] For example, a method can be used in which the surface is cleaned after polishing, an anti-oxidation treatment is applied to the surface of the metal layer, and then a hydrophilic treatment is performed before joining. Alternatively, the surface of the metal layer may be made of a metal that is difficult to oxidize, such as gold, and then a hydrophilic treatment may be performed. In addition, joining methods other than those described above may also be used.

[0579] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0580] (Embodiment 5) This embodiment describes metal oxides (hereinafter also referred to as oxide semiconductors) that can be used in the OS transistor described in the above embodiment.

[0581] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0582] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 25A. Figure 25A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0583] As shown in Figure 25A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous semiconductors. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite). Note that single crystal, polycrystal, and completely amorphous semiconductors are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal semiconductors.

[0584] The structure within the thick frame shown in Figure 25A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0585] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 25B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 25B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 25B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 25B is 500 nm.

[0586] As shown in Figure 25B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 25B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0587] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 25C. Figure 25C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 25C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0588] As shown in Figure 25C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0589] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 25A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0590] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0591] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0592] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0593] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0594] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0595] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0596] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0597] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0598] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities and the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0599] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0600] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0601] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0602] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0603] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0604] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0605] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0606] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0607] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0608] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation.

[0609] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0610] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0611] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0612] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm -3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations may also be referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0613] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0614] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0615] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0616] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0617] In oxide semiconductors, the presence of silicon, one of the Group 14 elements, or carbon, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are compared by 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0618] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0619] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0620] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons, which act as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0621] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0622] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0623] (Embodiment 6) This embodiment shows an example of a semiconductor wafer on which the semiconductor device shown in the above embodiment is formed, and an example of an electronic component into which the semiconductor device is incorporated.

[0624] <Semiconductor wafers> First, an example of a semiconductor wafer on which semiconductor devices are formed will be explained using Figure 26A.

[0625] The semiconductor wafer 4800 shown in Figure 26A comprises a wafer 4801 and a plurality of circuit sections 4802 provided on the upper surface of the wafer 4801. The portion of the upper surface of the wafer 4801 without circuit sections 4802 is the spacing 4803, which is the region for dicing.

[0626] The semiconductor wafer 4800 can be manufactured by forming multiple circuit sections 4802 on the surface of wafer 4801 in a previous process. Alternatively, the opposite side of wafer 4801 from where the circuit sections 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801, enabling miniaturization of the component.

[0627] The next step is the dicing process. Dicing is performed along the scribe lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by the dashed lines. In order to facilitate the dicing process, it is preferable that the spacing 4803 be arranged so that multiple scribe lines SCL1 are parallel, multiple scribe lines SCL2 are parallel, and scribe lines SCL1 and SCL2 are perpendicular.

[0628] By performing the dicing process, a chip 4800a, as shown in Figure 26B, can be cut from the semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit section 4802, and spacing 4803a. It is preferable to make the spacing 4803a as small as possible. In this case, the width of the spacing 4803 between adjacent circuit sections 4802 should be approximately the same length as the cutting allowance of the scribe line SCL1 or the cutting allowance of the scribe line SCL2.

[0629] The shape of the element substrate in one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in Figure 26A. For example, it may be a rectangular semiconductor wafer. The shape of the element substrate can be appropriately changed depending on the manufacturing process of the element and the apparatus for manufacturing the element.

[0630] <Electronic Components> Figure 26C shows a perspective view of the electronic component 4700 and the circuit board (mounted board 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in Figure 26C has a chip 4800a within a mold 4711. As shown in Figure 26C, the chip 4800a may also have a configuration in which circuit sections 4802 are stacked. Figure 26C omits some parts to show the inside of the electronic component 4700. The electronic component 4700 has a land 4712 on the outside of the mold 4711. The land 4712 is electrically connected to an electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a by a wire 4714. The electronic component 4700 is mounted, for example, on a printed circuit board 4702. Multiple such electronic components are combined and electrically connected on the printed circuit board 4702 to complete the mounted board 4704.

[0631] Figure 26D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 are provided on the interposer 4731.

[0632] Electronic component 4730 includes a semiconductor device 4710. The semiconductor device 4710 can be, for example, the semiconductor device described in the above embodiment, or a high-bandwidth memory (HBM). Furthermore, the semiconductor device 4735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, FPGA, or memory device.

[0633] The package substrate 4732 can be a ceramic substrate, a plastic substrate, or a glass epoxy substrate, etc. The interposer 4731 can be a silicon interposer, a resin interposer, etc.

[0634] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes referred to as a "redistribution substrate" or "intermediate substrate." In addition, through electrodes may be provided on the interposer 4731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 4732. Furthermore, in silicon interposers, TSVs (Through Silicon Vias) can be used as through electrodes.

[0635] It is preferable to use a silicon interposer as the interposer 4731. Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring, which is difficult with resin interposers.

[0636] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0637] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit placed on the silicon interposer and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0638] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 4730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 4710 and the semiconductor device 4735.

[0639] To mount the electronic component 4730 onto another substrate, electrodes 4733 may be provided at the bottom of the package substrate 4732. Figure 26D shows an example where electrodes 4733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 4733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0640] The electronic component 4730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0641] Next, we will describe an electronic component having an image sensor chip (imaging device) that includes a photoelectric conversion element.

[0642] Figure 27A is a perspective view of the top surface of a package containing an image sensor chip. The package includes a package substrate 4510 for fixing the image sensor chip 4550 (see Figure 27C), a cover glass 4520, and an adhesive 4530 for bonding the two together.

[0643] Figure 27B is a perspective view of the bottom surface of the package. The bottom surface of the package has a BGA (Ball Grid Array) with solder balls as bumps 4540. Note that it may also have LGA (Land Grid Array), PGA (Pin Grid Array), etc., instead of BGA.

[0644] Figure 27C is a perspective view of the package, with some of the cover glass 4520 and adhesive 4530 omitted. Electrode pads 4560 are formed on the package substrate 4510, and the electrode pads 4560 and bumps 4540 are electrically connected via through-holes. The electrode pads 4560 are electrically connected to the image sensor chip 4550 by wires 4570.

[0645] Figure 27D is a perspective view of the top side of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 4511 for fixing the image sensor chip 4551 (Figure 27F), a lens cover 4521, and a lens 4535, etc. An IC chip 4590 (Figure 27F) having functions such as a drive circuit and a signal conversion circuit for the imaging device is also provided between the package substrate 4511 and the image sensor chip 4551, thus having a System in Package (SiP) configuration.

[0646] Figure 27E is a perspective view of the lower side of the camera module. The package substrate 4511 has a QFN (Quad Flat No-lead package) configuration with mounting lands 4541 on the lower and side surfaces. Note that this configuration is just an example, and a QFP (Quad Flat Package), the aforementioned BGA, etc., may also be provided.

[0647] Figure 27F is a perspective view of the module, with the lens cover 4521 and part of the lens 4535 omitted. Land 4541 is electrically connected to electrode pad 4561, and electrode pad 4561 is electrically connected to image sensor chip 4551 or IC chip 4590 by wire 4571.

[0648] By housing the image sensor chip in the package described above, mounting it on printed circuit boards and the like becomes easier, allowing the image sensor chip to be incorporated into various semiconductor devices and electronic equipment. For example, by incorporating the image sensor chip into the arithmetic circuit described in the above embodiment, the information captured by the image sensor chip can be input to the arithmetic circuit as input data.

[0649] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0650] (Embodiment 7) This embodiment describes an example of an electronic device having the semiconductor device described in the above embodiment. Figure 28 illustrates how the electronic component 4700 having the semiconductor device is included in each electronic device. Although Figure 28 shows the electronic component 4700, the imaging device shown in Figure 27 may be used instead.

[0651] [mobile phone] The information terminal 5500 shown in Figure 28 is a type of information terminal, specifically a mobile phone (smartphone). The information terminal 5500 has a housing 5510 and a display unit 5511. For input interfaces, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0652] The information terminal 5500 can execute applications utilizing artificial intelligence by applying the semiconductor device described in the above embodiment. Examples of applications utilizing artificial intelligence include applications that recognize conversations and display the conversation content on the display unit 5511, applications that recognize characters, figures, etc., entered by the user on the touch panel provided on the display unit 5511 and display them on the display unit 5511, and applications that perform biometric authentication such as fingerprints and voiceprints.

[0653] [Wearable devices] Figure 28 also shows a wristwatch-type information terminal 5900 as an example of a wearable device. The information terminal 5900 includes a housing 5901, a display unit 5902, operation buttons 5903, a control element 5904, a band 5905, and the like.

[0654] Similar to the information terminal 5500 mentioned above, wearable devices can run applications utilizing artificial intelligence by applying the semiconductor device described in the above embodiment. Examples of applications utilizing artificial intelligence include applications that manage the health status of a person wearing the wearable device, and navigation systems that select and guide the user along the optimal route based on the destination input.

[0655] [Information terminal] Figure 28 also illustrates a desktop information terminal 5300. The desktop information terminal 5300 comprises a main unit 5301, a display 5302, and a keyboard 5303.

[0656] The desktop information terminal 5300, like the information terminal 5500 mentioned above, can run applications utilizing artificial intelligence by applying the semiconductor device described in the above embodiment. Examples of applications utilizing artificial intelligence include design support software, document editing software, and automatic menu generation software. Furthermore, the desktop information terminal 5300 can be used to develop new artificial intelligence.

[0657] In the above, smartphones, desktop information terminals, and wearable devices were used as examples of electronic devices and illustrated in Figure 28, but other information devices can also be applied. Examples of information devices other than smartphones, desktop information terminals, and wearable devices include PDAs (Personal Digital Assistants), notebook computers, and workstations.

[0658] [electric appliances] Figure 28 also shows an electric refrigerator-freezer 5800 as an example of an electrical appliance. The electric refrigerator-freezer 5800 has a casing 5801, a refrigerator door 5802, a freezer door 5803, etc.

[0659] By applying the semiconductor device described in the above embodiment to the electric refrigerator 5800, an electric refrigerator 5800 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator 5800 can have functions such as automatically generating menus based on the ingredients stored in the electric refrigerator 5800 and their expiration dates, and automatically adjusting the temperature to suit the ingredients stored in the electric refrigerator 5800.

[0660] In this example, an electric refrigerator was described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction heating (IH) cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0661] [Game console] Figure 28 also shows a portable game console 5200, which is an example of a game console. The portable game console 5200 has a casing 5201, a display unit 5202, buttons 5203, etc.

[0662] Furthermore, Figure 28 illustrates a home console 7500, which is an example of a game console. The home console 7500 has a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a wired connection. Although not shown in Figure 28, the controller 7522 may also be equipped with a display unit for displaying game images, a touch panel as an input interface other than buttons, a joystick, a rotary knob, a sliding knob, etc. Moreover, the shape of the controller 7522 is not limited to the shape shown in Figure 28, and its shape may be changed in various ways depending on the genre of game. For example, in shooting games such as FPS (First Person Shooter), a controller with triggers as buttons and a shape that mimics a gun can be used. Also, for example, in music games, a controller with a shape that mimics a musical instrument or musical equipment can be used. Furthermore, home game consoles may not use controllers, but instead be equipped with cameras, depth sensors, microphones, etc., and operated by the game player's gestures and / or voice.

[0663] Furthermore, the video from the aforementioned game console can be output by display devices such as televisions, personal computer displays, game displays, and head-mounted displays.

[0664] By applying the semiconductor device described in the above embodiment to the portable game console 5200, a low-power portable game console 5200 can be realized. Furthermore, because the low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized.

[0665] Furthermore, by applying the semiconductor device described in the above embodiment to the portable game console 5200, a portable game console 5200 with artificial intelligence can be realized.

[0666] Normally, the progression of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are determined by the game's program. However, by applying artificial intelligence to the 5200 handheld game console, it becomes possible to express things that are not limited to the game's program. For example, it becomes possible to express changes in the content of questions asked by the player, the game's progress, the time, and the behavior of characters appearing in the game.

[0667] Furthermore, when playing games that require multiple players on the 5200 handheld game console, artificial intelligence can be used to create anthropomorphic game players. By using AI-generated game players as opponents, it becomes possible to play the game even by a single player.

[0668] Figure 28 illustrates a portable game console as an example of a game console, but the electronic devices of one aspect of the present invention are not limited to this. Examples of electronic devices of one aspect of the present invention include home game consoles, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), and pitching machines for batting practice installed in sports facilities.

[0669] [Mobile] The semiconductor device described in the above embodiment can be applied to a mobile vehicle and the area around the driver's seat of the vehicle.

[0670] Figure 28 shows an example of a mobile vehicle, the automobile 5700.

[0671] The driver's seat area of ​​the 5700 automobile is equipped with an instrument panel that can display information such as the speedometer, tachometer, mileage, fuel gauge, gear status, and air conditioning settings. Additionally, a display device showing this information may be provided around the driver's seat.

[0672] In particular, by displaying images from an imaging device (not shown) installed in the automobile 5700, the display device can compensate for obstructed views from pillars and other obstructions, as well as blind spots in the driver's seat, thereby enhancing safety. In other words, by displaying images from an imaging device installed on the outside of the automobile 5700, blind spots can be compensated for, and safety can be enhanced.

[0673] The semiconductor device described in the above embodiment can be applied as a component of artificial intelligence; for example, the computer can be used in an autonomous driving system for automobile 5700. It can also be used in systems that perform tasks such as road guidance and hazard prediction. The display device may be configured to display information such as road guidance and hazard prediction.

[0674] Although automobiles are described above as an example of a mobile vehicle, mobile vehicles are not limited to automobiles. For example, mobile vehicles can also include trains, monorails, ships, and aerial vehicles (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and a computer according to one aspect of the present invention can be applied to these mobile vehicles to provide them with a system utilizing artificial intelligence.

[0675] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0676] Figure 28 shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation buttons 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. In this example, the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and housing 6241 may be integrated. Furthermore, the digital camera 6240 may be configured to allow for the attachment of a strobe device, viewfinder, etc. separately.

[0677] By applying the semiconductor device described in the above embodiment to the digital camera 6240, a low-power digital camera 6240 can be realized. Furthermore, because the low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized.

[0678] Furthermore, by applying the semiconductor device described in the above embodiment to the digital camera 6240, a digital camera 6240 with artificial intelligence can be realized. By utilizing artificial intelligence, the digital camera 6240 can have functions such as automatically recognizing subjects such as faces and objects, adjusting the focus according to the subject, automatically firing the flash according to the environment, and toning the color of captured images.

[0679] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0680] Figure 28 shows a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, operation keys 6304, a lens 6305, a connection unit 6306, etc. The operation keys 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0681] When recording video captured with the 6300 video camera, encoding is required according to the data recording format. By utilizing artificial intelligence, the 6300 video camera can perform AI-based pattern recognition during encoding. This pattern recognition allows the camera to calculate differential data for people, animals, objects, etc., contained in consecutive captured image data, and compress the data.

[0682] [Extension devices for PCs] The semiconductor device described in the above embodiment can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0683] Figure 29A shows an example of such an expansion device, an external expansion device 6100 for a PC, equipped with a portable, arithmetic-processing chip. The expansion device 6100 can perform arithmetic processing by connecting to a PC, for example, via USB (Universal Serial Bus). Although Figure 29A illustrates a portable form of the expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may be a relatively large form of expansion device equipped with, for example, a cooling fan.

[0684] The expansion device 6100 comprises a housing 6101, a cap 6102, a USB connector 6103, and a circuit board 6104. The circuit board 6104 is housed in the housing 6101. The circuit board 6104 is provided with circuits for driving semiconductor devices and the like described in the above embodiment. For example, the circuit board 6104 is fitted with a chip 6105 (for example, a semiconductor device, electronic component 4700, memory chip, etc., as described in the above embodiment) and a controller chip 6106. The USB connector 6103 functions as an interface for connecting to external devices.

[0685] By using the expansion device 6100 with a PC, the processing power of that PC can be increased. This allows even PCs with insufficient processing power to perform calculations such as artificial intelligence and video processing.

[0686] [Broadcasting System] The semiconductor device described in the above embodiment can be applied to a broadcasting system.

[0687] Figure 29B schematically illustrates data transmission in a broadcasting system. Specifically, Figure 29B shows the path from radio waves (broadcast signals) transmitted from broadcasting station 5680 to television receiving devices (TVs) 5600 in each household. TV 5600 is equipped with a receiving device (not shown), and the broadcast signal received by antenna 5650 is transmitted to TV 5600 via this receiving device.

[0688] In Figure 29B, antenna 5650 is shown as a UHF (Ultra High Frequency) antenna, but antennas such as BS / 110°CS antennas and CS antennas can also be used as antenna 5650.

[0689] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting. Radio tower 5670 amplifies the received radio wave 5675A and transmits radio wave 5675B. Each household can receive radio wave 5675B with antenna 5650 and watch terrestrial broadcasts on TV 5600. Note that the broadcasting system is not limited to terrestrial broadcasting as shown in Figure 29B, but may also include satellite broadcasting using artificial satellites, data broadcasting via fiber optic lines, etc.

[0690] The broadcasting system described above may also be an artificial intelligence-based broadcasting system by applying the semiconductor device described in the above embodiment. When broadcasting data is transmitted from the broadcasting station 5680 to the TVs 5600 in each home, the broadcasting data is compressed by an encoder, and when the antenna 5650 receives the broadcasting data, the decoder of the receiving device included in the TV 5600 restores the broadcasting data. By using artificial intelligence, for example, in motion compensation prediction, which is one of the compression methods of the encoder, it is possible to recognize display patterns included in the display image. It is also possible to perform in-frame prediction using artificial intelligence. Furthermore, for example, when low-resolution broadcasting data is received and the broadcasting data is displayed on a high-resolution TV...

Claims

1. It has a first circuit and a second circuit, The second circuit comprises a first switch, a second switch, a current-voltage conversion circuit, and a first transistor. The first circuit is electrically connected to the first terminal of the first switch, The second terminal of the first switch is electrically connected to the input terminal of the current-voltage conversion circuit. The output terminal of the current-voltage conversion circuit is electrically connected to the first terminal of the first transistor. The second terminal of the first transistor is electrically connected to the first terminal of the second switch. The first circuit takes W as a plurality of first data １ Or W ｍ The function of holding (m is an integer of 1 or more), and the first circuit has a plurality of second data X １ ~X ｍ The second circuit has a function that, when input, supplies a current corresponding to the value of equation (A1) to the first terminal of the second circuit, The current-voltage conversion circuit comprises an operational amplifier and a load. The inverting input terminal of the operational amplifier is electrically connected to the first terminal of the current-voltage conversion circuit and the first terminal of the load. The output terminal of the operational amplifier is electrically connected to the second terminal of the load. The load has one of the following: a resistor, a diode, or a transistor. The channel formation region of the first transistor is a semiconductor device having an oxide semiconductor containing In. [Math 1]

2. In claim 1, The current-voltage conversion circuit has the function of outputting a first potential corresponding to the current input to the input terminal of the current-voltage conversion circuit to the output terminal of the current-voltage conversion circuit.

3. In claim 2, The first transistor is, The function of outputting the first potential from the second terminal of the first transistor when the first potential is greater than or equal to the sum of the gate potential of the first transistor and the threshold voltage of the first transistor, A semiconductor device having a function of outputting the potential of the sum from the second terminal of the first transistor when the first potential is smaller than the sum.

Images