Staircase structure in a 3D memory device and method for forming it

Abstract

To provide a staircase structure in a three-dimensional memory device. and a forming method thereof.SOLUTION: There are provided a 3D memory devices having a staircase structure and a forming method thereof according an embodiment. In the example, the 3D memory device includes a memory array structure, a staircase structure located in the middle of the memory array structure that laterally divides the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone includes a first pair of stairs facing each other in a first lateral direction and at different depths. Each staircase includes multiple steps. At least one step in the first pair of stairs is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.SELECTED DRAWING: Figure 4

Description

Technical Field

[0005]

[0001] Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods of fabricating the same.

Background Art

[0002] Planar memory cells are scaled down to a smaller size by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the feature size of the memory cells approaches the lower limit, the planar process and fabrication technology become difficult and the cost increases. As a result, the memory density of the planer memory cells is approaching the upper limit.

[0003] 3D memory architectures can address this density limit of planer memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

Summary of the Invention

Problems to be Solved by the Invention

[0006] In another example, a 3D memory device comprises a memory array structure and a staircase structure located in the middle of the memory array structure, which laterally divides the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone comprises a first staircase comprising a plurality of divisions in the second lateral direction. Each division comprises a plurality of steps in the first lateral direction perpendicular to the second lateral direction. A step in one of the divisions is perpendicular to two steps in another division of the division. At least one step in the first staircase is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

[0007] In yet another example, a method for forming a staircase structure for a 3D memory device is disclosed. A staircase zone mask is pattern-formed in the middle of a stack structure comprising a first material layer and a second material layer arranged alternately in the vertical direction, with openings for a first staircase zone and a second staircase zone. In each of the first and second staircase zones, at least one pair of stairs facing each other in a first transverse direction of the same depth is formed, thereby forming a bridge structure between the first and second staircase zones in a second transverse direction perpendicular to the first transverse direction. In each of the first and second staircase zones, each of the at least one pair of stairs is chopped to a different depth.

[0008] The accompanying drawings, incorporated herein and forming part thereof, illustrate embodiments of the present disclosure and, together with the description, further assist in explaining the principles of the present disclosure and enabling those skilled in the art to fabricate and use the present disclosure. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic diagram showing a 3D memory device with a stepped structure. [Figure 2] This is a schematic diagram illustrating an exemplary 3D memory device having a stepped structure according to some embodiments of the present disclosure. [Figure 3] This is a plan view showing an exemplary 3D memory device having a stepped structure according to some embodiments of the present disclosure. [Figure 4] This is a top front perspective view showing an exemplary stepped structure of a 3D memory device according to some embodiments of the present disclosure. [Figure 5A] This figure shows various exemplary masks for forming exemplary stepped structures in a 3D memory device according to some embodiments of the present disclosure. [Figure 5B] This figure shows various exemplary masks for forming exemplary stepped structures in a 3D memory device according to some embodiments of the present disclosure. [Figure 5C]This figure shows various exemplary masks for forming exemplary stepped structures in a 3D memory device according to some embodiments of the present disclosure. [Figure 5D] This figure shows various exemplary masks for forming exemplary stepped structures in a 3D memory device according to some embodiments of the present disclosure. [Figure 5E] This figure shows various exemplary masks for forming exemplary stepped structures in a 3D memory device according to some embodiments of the present disclosure. [Figure 5F] This figure shows various exemplary masks for forming exemplary stepped structures in a 3D memory device according to some embodiments of the present disclosure. [Figure 6A] This figure shows a fabrication process for forming an exemplary stepped structure of a 3D memory device according to various embodiments of the present disclosure. [Figure 6B] This figure shows a fabrication process for forming an exemplary stepped structure of a 3D memory device according to various embodiments of the present disclosure. [Figure 7A] This figure shows various exemplary schemes for dividing a staircase into different depths within a staircase structure, according to some embodiments of the present disclosure. [Figure 7B] This figure shows various exemplary schemes for dividing a staircase into different depths within a staircase structure, according to some embodiments of the present disclosure. [Figure 7C] This figure shows various exemplary schemes for dividing a staircase into different depths within a staircase structure, according to some embodiments of the present disclosure. [Figure 7D] This figure shows various exemplary schemes for dividing a staircase into different depths within a staircase structure, according to some embodiments of the present disclosure. [Figure 8] This is a flowchart of a method for forming an exemplary stepped structure of a 3D memory device according to several embodiments. [Figure 9] This is a flowchart of another method for forming an exemplary staircase structure of a 3D memory device according to several embodiments. [Modes for carrying out the invention]

[0010] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0011] While specific configurations and arrangements are described, it will be understood that these are for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure may be adopted in a variety of other applications.

[0012] References in the specification such as "one embodiment," "embodiment," "exemplary embodiment," and "some embodiments" should be noted to indicate that the embodiments described may have certain features, structures, or characteristics, but not all embodiments may necessarily include those features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when certain features, structures, or characteristics are described in relation to an embodiment, it will be within the knowledge of those skilled in the art that such features, structures, or characteristics may be affected in relation to other embodiments, whether or not they are explicitly described.

[0013] In general, terms can be understood, at least in part, from their usage in context. For example, at least in part, depending on the context, the term “one or more” as used herein may be used in a singular sense to describe a feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics. Similarly, here again, terms such as “a,” “an,” or “the” may be understood, at least in part, depending on the context, to convey either singular or plural use. In addition, the term “based on” can be understood not necessarily intended to convey an exclusive set of elements, but instead, at least in part, depending on the context, may allow for the presence of additional elements that are not necessarily explicitly described.

[0014] As used in this disclosure, the meanings of "above", "higher than", and "upper" should be immediately understood to be interpreted in the broadest sense such that "above" means not only directly above something, but also above something with intervening intermediate features or layers therebetween, and "higher than" or "upper" means not only higher than or above something, but may also include the meaning of being directly (i.e., without any intervening intermediate features or layers) higher than or above something.

[0015] Furthermore, spatial relative terms such as "below", "lower than", "bottom", "above", "top", and the like may be used herein to facilitate description of the relationship between one element or feature and another element or feature as illustrated in the figures. The spatial relative terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures, or in operation. The device may be oriented in some other way (rotated 90 degrees or in some other orientation), and the spatial relative descriptors used herein may likewise be interpreted accordingly.

[0016] As used herein, the term "substrate" refers to the material to which subsequent material layers are added. The substrate itself can be patterned. The material added on the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from electrically non-conductive materials such as glass, plastic, or sapphire wafers.

[0017] As used herein, the term “layer” refers to a portion of a material that includes a region having thickness. A layer may extend across an entire structure below or above it, or it may have a smaller extent than the extent of the structure below or above it. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuum having a thickness smaller than the thickness of the continuum. For example, a layer may be located between the top and bottom surfaces of a continuum, or between a pair of horizontal planes at the top and bottom surfaces. A layer may extend along a transverse, vertical, and / or tapered surface. A substrate may be a layer, may contain one or more layers within it, and / or have one or more layers above, above, and / or below it. A layer may include multiple layers. For example, an interconnection layer may include one or more conductor and contact layers (on which interconnection lines and / or via contacts are formed) and one or more dielectric layers.

[0018] As used herein, the term “nominal” refers to a desired or target value of a characteristic or parameter for a component or process operation, set at the design stage of the product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or manufacturing tolerances. As used herein, the term “approximately” indicates a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of the subject. Based on a particular technology node, the term “approximately” may indicate a value of a given quantity that varies, for example, within 10 to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0019] As used herein, the term “3D memory device” refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND memory strings) on a transversely oriented substrate such that the memory strings extend perpendicularly with respect to the substrate. As used herein, the term “perpendicular / vertically” means nominally perpendicular to the transverse surface of the substrate.

[0020] In some 3D memory devices, memory cells for storing data are stacked vertically through a stacked storage structure (e.g., a memory stack). 3D memory devices typically feature a stepped structure formed on one or more sides (edges) of the stacked storage structure for purposes such as word line fan-out. Since the stepped structure is usually formed on the edge of each memory plane, the memory cells are driven in one direction by a row decoder (also called an "x-decoder") located on the edge of each memory plane through the corresponding stepped structure along the word line.

[0021] For example, Figure 1 shows a schematic diagram of a 3D memory device 100 having a stepped structure 104. The 3D memory device 100, such as a 3D NAND memory device, comprises two memory planes 102, each having a memory cell array within a memory array structure 106. Note that Figure 1 includes the x and y axes to illustrate two orthogonal (perpendicular) directions in the wafer plane. The x direction is the word line direction of the 3D memory device 100, and the y direction is the bit line direction of the 3D memory device 100. The 3D memory device 100 also comprises two stepped structures 104 on opposite sides of each memory array structure 106 in the x direction. Each word line of the memory plane 102 extends laterally in the x direction, traversing the entire memory plane 102 and reaching each step (level) of the stepped structure 104. Row decoders (not shown) are formed directly above, directly below, or adjacent to each stepped structure 104 to shorten the interconnection length. In other words, each row decoder drives half of the memory cell through half of the word line in one direction (either positive or negative x-direction, but not both), and each of these traverses the entire memory plane 102.

[0022] Therefore, the load of the unidirectional word line drive system includes the resistance of the entire word line traversing the memory plane 102. Furthermore, as the demand for higher storage capacity continues to increase, the number of vertical levels in the stacked storage structure increases, and the thickness of the stack layer, including each word line film, decreases. Consequently, even higher resistance is introduced into the load, which can cause significant resistance-capacitance (RC) delay. Thus, the performance of the 3D memory device 100, such as read speed and write speed, may be affected by the unidirectional word line drive system by the lateral step structure 104.

[0023] Various embodiments of this disclosure provide intermediate staircase structures for memory planes and methods for fabricating them to enable bidirectional word line driving schemes for reducing RC delay. By replacing conventional lateral staircase structures with, for example, central staircase structures, each row decoder can drive word lines bidirectionally from the middle of the memory plane in opposite directions so that resistance in the load can be reduced when the length of the word line driven by the row decoder is shortened, for example, to half. In some embodiments, a bridge structure is introduced as part of the staircase structure, thereby connecting word lines separated by the central staircase structure. In some embodiments, a multi-part staircase structure, in which each step of the staircase structure includes multiple divisions for fanning out multiple word lines, is used to increase the utilization rate of the staircase structure and reduce the complexity of fabrication. In some embodiments, multiple chopping processes are used to form multiple staircases of different depths, reducing the number of trim etch processes, thereby further reducing the complexity of fabrication and improving yield.

[0024] Figure 2 is a schematic diagram showing an exemplary 3D memory device 200 having a stepped structure 204 according to some embodiments of the present disclosure. In some embodiments, the 3D memory device 200 comprises a plurality of memory planes 202. Each memory plane 102 may comprise a memory array structure 206-1 / 206-2 and a stepped structure 204 located between the memory array structures 206-1 / 206-2, which laterally divides the memory array structures 206-1 / 206-2 into a first memory array structure 206-1 and a second memory array structure 206-2 in the x-direction (word line direction). Unlike the 3D memory device 100 of Figure 1, where the stepped structure 104 is on opposite sides of each memory array structure 106, the stepped structure 204 of the 3D memory device 200 is located between the first and second memory array structures 206-1 and 206-2 according to some embodiments. In some embodiments, for each memory plane 202, the step structure 204 is located in the middle of the memory array structures 206-1 / 206-2. That is, the step structure 204 may be a central step structure that equally divides the memory array structures 206-1 / 206-2 into first and second memory array structures 206-1 and 206-2 having the same number of memory cells. For example, the first and second memory array structures 206-1 and 206-2 may be symmetrical in the x-direction with respect to the central step structure 204. In some examples, the step structure 204 may be intermediate rather than in the middle (center) of the memory array structures 206-1 / 206-2, so it is understood that the first and second memory array structures 206-1 and 206-2 may have different sizes and / or numbers of memory cells. In some embodiments, the 3D memory device 200 is a NAND flash memory device in which memory cells are provided in the form of arrays of NAND memory strings (not shown) in first and second memory array structures 206-1 and 206-2. The first and second memory array structures 206-1 and 206-2 may include, but are not limited to, gate line slits (GLS), through-array contacts (TAC), array common sources (ACS), and any other suitable components.

[0025] Each word line (not shown) of the memory plane 202, which extends laterally in the x-direction, can be separated by a staircase structure 204 into two parts: a first word line portion that crosses the first memory array structure 206-1 and a second word line portion that crosses the second memory array structure 206-2. As described in detail below, the two parts of each word line can be electrically connected at each step of the staircase structure 204 by a bridge structure (not shown) within the staircase structure 204. Row decoders (not shown) can be formed directly above, directly below, or adjacent to each staircase structure 204 to shorten the interconnection length. As a result, unlike the row decoder of the 3D memory device 100 in Figure 1, each row decoder of the 3D memory device 200 can drive memory cells in the first and second memory array structures 206-1 and 206-2 in both directions (both positive and negative x-directions). In other words, by replacing the conventional side staircase structure (e.g., 104 in Figure 1) with, for example, a staircase structure 204 located in the middle of the memory array structure 206-1 / 206-2, each row decoder can drive word lines in both directions from the middle of the memory plane 202 in opposite directions, thereby reducing the resistance in the load as the length of each portion of word line driven by the row decoder is reduced to half, for example, when the staircase structure 204 is in the middle of the memory array structure 206-1 / 206-2. That is, in some embodiments, the row decoder of the 3D memory device 200 only needs to drive either a first word line portion or a second word line portion of each word line.

[0026] In Figure 2, the stepped structures 204 located between each of the memory planes 202 are functional stepped structures used to land interconnects (e.g., word line contacts). However, it is understood that additional stepped structures (e.g., dummy stepped structures, not shown) may also be formed on one or more sides to balance the load during the etching or chemical mechanical polishing (CMP) process during fabrication and to isolate adjacent memory planes 202. Since the stepped structures 204 located between each of the memory planes 202 can increase the total area of ​​the memory planes 202, steeper dummy stepped structures with smaller areas may be formed to reduce the die size.

[0027] Figure 3 is a plan view showing an exemplary 3D memory device 300 having a stepped structure 301 according to some embodiments of the present disclosure. The 3D memory device 300 may be an example of a portion of the memory plane 202 of Figure 2, which includes a stepped structure 204, and the stepped structure 301 of the 3D memory device 300 may be an example of a stepped structure 204 within the memory plane 202. As shown in Figure 3, the 3D memory device 300 may include a plurality of blocks 302 in the y-direction (bit line direction) separated by parallel GLS 308. In some embodiments where the 3D memory device 300 is a NAND flash memory device, each block 302 is the smallest erasable unit of the NAND flash memory device. Each block 302 may further comprise a plurality of fingers 304 in the y-direction separated by some of the GLS 308 having "H" cuts 310.

[0028] In some embodiments, the staircase structure 301 is located in the middle (e.g., in the center) of the 3D memory device 300 in the x-direction (word line direction). In some embodiments, Figure 3 also shows a pair of peripheral regions 303 of the memory array structure adjacent to the staircase structure 301. The peripheral regions 303 separated by the staircase structure 301 can be used to form a top select gate (TSG), which may be driven individually or electrically connected by interconnects on the staircase structure 301. As described in detail below, the staircase structure 301 may include a plurality of staircase zones, each corresponding to a respective finger 304, and a plurality of bridge structures 306, each located between two adjacent staircase zones in the y-direction. Each staircase zone may be located within one or two blocks 302. The 3D memory device 300 may include a plurality of dummy channel structures 314 within the staircase zones and bridge structures 306 to provide mechanical support and / or load balancing. The 3D memory device 300 may further include word line contacts 312 within the stair zone of the stair structure 301, each of which should land on a respective word line (not shown) at each step of the stair structure 301 for word line driving.

[0029] To achieve a bidirectional word line driving scheme, in some embodiments, each bridge structure 306 connects (both physically and electrically) a first memory array structure and a second memory array structure (not shown). That is, in some embodiments, the staircase structure 301 does not completely disconnect the intermediate memory array structure, but instead leaves the first and second memory array structures connected by its bridge structure 306. Thus, each word line can be driven in both directions (both positive and negative x-directions) from the respective word line contacts 312 in the staircase zone of the staircase structure 301 in the middle of the 3D memory device 300 through the bridge structure 306. For example, Figure 3 further illustrates an exemplary current path of a bidirectional word line driving scheme by the bridge structure 306. The first current path, indicated by the solid arrow, and the second current path, indicated by the hollow arrow, represent currents passing through two separate word lines at different levels, respectively.

[0030] Figure 4 is a top front perspective view showing an exemplary stepped structure 400 of a 3D memory device according to several embodiments of the present disclosure. The stepped structure 400 may be an example of the stepped structure 204 of the 3D memory device 200 in Figure 2 or the stepped structure 301 of the 3D memory device 300 in Figure 3. The stepped structure 400 may include a stacked structure 401 on a substrate (not shown), which may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0031] Note that the x, y, and z axes are included in Figure 4 to further illustrate the spatial relationships of the components of the staircase structure 400. The substrate of the 3D memory device includes two transverse surfaces extending laterally in the xy plane: a top surface on the front side of the wafer on which the staircase structure 400 can be formed, and a bottom surface on the back side of the wafer opposite to the front side. The z axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., a layer or device) is "above," "above," or "below" another component (e.g., a layer or device) of the 3D memory device is determined with respect to the substrate of the 3D memory device in the z direction (a vertical direction perpendicular to the xy plane) when the substrate is positioned in the bottom plane of the 3D memory device in the z direction. The same concepts for describing spatial relationships apply throughout this disclosure.

[0032] The stack structure 401 may include a first material layer arranged alternately in the vertical direction and a second material layer different from the first material layer. The first and second material layers may be arranged alternately in the vertical direction. In some embodiments, the stack structure 401 may include a plurality of material layer pairs stacked perpendicularly in the z direction, each of which includes a first material layer and a second material layer. The number of material layer pairs in the stack structure 401 (e.g., 32, 64, 96, 128, 160, 192, 224, or 256) can determine the number of memory cells in the 3D memory device.

[0033] In some embodiments, the 3D memory device is a NAND flash memory device, and the stack structure 401 is a stacked storage structure formed by passing NAND memory strings through it. Each of the first material layers includes a conductive layer, and each of the second material layers includes a dielectric layer. That is, the stack structure 401 may include alternating conductive layers and dielectric layers (not shown). In some embodiments, each conductive layer may function as a gate line of the NAND memory string, and a word line extending laterally from the gate line for word line fan-out, ending in the stepped structure 400. The conductive layers may include conductive materials including, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. The dielectric layers may include dielectric materials including, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductive layers include a metal such as tungsten, and the dielectric layers include silicon oxide.

[0034] Each step (indicated as “level”) of the staircase structure 400 may include one or more pairs of material layers. In some embodiments, the top material layer of each step is a conductive layer for vertical interconnection. In some embodiments, adjacent steps of the staircase structure 400 are offset by nominally the same distance in the z direction and nominally the same distance in the x direction every two steps. Thus, each offset can form a “landing region” for interconnecting with word line contacts of a 3D memory device in the z direction (e.g., 312 in Figure 3, not shown in Figure 4).

[0035] As shown in Figure 4, the staircase structure 400 may include a first staircase zone 402, a second staircase zone 412, and a bridge structure 404 between the first staircase zone 402 and the second staircase zone 412 in the y-direction (bit line direction). In some embodiments, the first staircase zone 402 includes multiple pairs of stairs, including a first pair of stairs 406-1 and 406-2 in the x-direction (word line direction), a second pair of stairs 410-1 and 410-2, and a third pair of stairs 416-1 and 416-2. Each of the stairs 406-1, 406-2, 410-1, 410-2, 416-1, or 416-2 may, in some embodiments, have multiple steps in the x-direction. In some embodiments, each staircase 406-1, 406-2, 410-1, 410-2, 416-1, or 416-2 is a functional staircase used to land interconnects (e.g., word line via contacts), as opposed to a dummy staircase. In other words, in some embodiments, none of the staircases 406-1, 406-2, 410-1, 410-2, 416-1, and 416-2 in the first staircase zone 402 are dummy staircases.

[0036] In some embodiments, each pair of stairs 406-1 / 406-2, 410-1 / 410-2, or 416-1 / 416-2 faces each other in the x-direction and is at different depths. In one example, the first pair of stairs 406-1 / 406-2 may face each other in the x-direction, for example, with stairs 406-1 inclined toward the negative x-direction and stairs 406-2 inclined toward the positive x-direction. Similarly, in another example, the second pair of stairs 410-1 / 410-2 may face each other in the x-direction, for example, with stairs 410-1 inclined toward the negative x-direction and stairs 410-2 inclined toward the positive x-direction. Since a single staircase may contain multiple steps, it will be understood that the depths of stairs disclosed herein may be based on the depth of the same step (at the same relative level) in the z-direction, such as the upper, middle, or lower steps. In one example, the first pair of stairs 406-1 / 406-2 may be at different depths, for example, the upper step of stairs 406-1 is higher than the upper step of stairs 406-2 in the z-direction. Similarly, in another example, the second pair of stairs 410-1 / 410-2 may be at different depths, for example, the upper step of stairs 410-1 is higher than the upper step of stairs 410-2 in the z-direction. In some embodiments, each pair of stairs 406-1 / 406-2, 410-1 / 410-2, or 416-1 / 416-2 does not overlap in the z-direction. That is, in some embodiments, the lower step of a higher staircase is not lower than the upper step of a lower staircase of the same pair.

[0037] The number of pairs of stairs in each stair zone (for example, the first stair zone 402) is not limited to 3, as shown in Figure 4, but it is understood that the same step pattern described above (i.e., each pair of stairs facing each other in the x-direction and at different depths) can be applied to any number of pairs of stairs. As a result, in some embodiments, each of the stairs 406-1, 406-2, 410-1, 410-2, 416-1, and 416-2 in the first stair zone 402 is at a different depth. That is, in some embodiments, none of the stairs 406-1, 406-2, 410-1, 410-2, 416-1, and 416-2 in the first stair zone 402 overlap in the z-direction. Furthermore, since each step of the stairs may be at a different depth, each step in the first stair zone 402 may be at a different depth. In other words, in some embodiments, none of the steps within the first stair zone 402 overlap in the z-direction (i.e., they are not at the same level). As a result, each step within the stair zone (e.g., the first stair zone 402) can be used to land interconnections (e.g., word line contacts) that are in contact with their respective word lines at different levels.

[0038] As shown in Figure 4, the staircase structure 400 can be a multi-section staircase structure including multiple divisions in the y-direction within each staircase zone (for example, the first staircase zone 402 or the second staircase zone 412). In some embodiments, each staircase 406-1, 406-2, 410-1, 410-2, 416-1, or 416-2 within the first staircase zone 402 includes multiple divisions in the y-direction, each of which includes multiple steps in the x-direction. By introducing multiple divisions in the y-direction, the dimensions (e.g., length) of the staircase structure 400 in the x-direction can be reduced without reducing the total number of steps. In some embodiments, in each staircase 406-1, 406-2, 410-1, 410-2, 416-1, or 416-2, the steps in one of the divisions are perpendicular to two steps in another of the divisions. That is, within each staircase, the step depth first changes along the y-direction (for example, increasing in the negative y-direction in Figure 4), and then changes along the x-direction (for example, increasing in the negative x-direction in Figure 4). As a result, for any division within the staircase, the depth of at least one step may be within the depth range of its adjacent division. The step depth patterns between divisions described above can be set based on the order in which the trim-etch and cutting processes are applied. Specifically, the step depth patterns between divisions disclosed herein can be achieved by applying the cutting process before the trim-etch process, as described in detail below with respect to the manufacturing process. For example, as shown in Figure 4, the staircase structure 400 may be a four-part staircase structure in which each staircase in a staircase zone (for example, each staircase 406-1, 406-2, 410-1, 410-2, 416-1, or 416-2 in the first staircase zone 402) may contain four divisions 408-1, 408-2, 408-3, and 408-4 in the y-direction. In one example, in staircase 406-1, there may be an intermediate step of division 408-2 perpendicularly between the upper and lower steps of another division 408-1, 408-3, or 408-4. It is understood that the number of divisions is not limited by the example in Figure 4 and may be any positive integer (i.e., 1, 2, 3, 4, 5, ...).

[0039] Although the first stair zone 402 is described in detail above, it will be understood that the arrangement of stairs within the first stair zone 402 disclosed herein may be similarly applied to a second stair zone 412 or any other stair zone within the stair structure 400. For example, the second stair zone 412 may include a pair of stairs 414-1 and 414-2 (e.g., a multi-part staircase) facing each other in the x-direction and at different depths, similar to the first stair zone 402.

[0040] As shown in Figure 4, the first stair zone 402 and the second stair zone 412 are asymmetrical in the y-direction in some embodiments. For example, the stair patterns in the first stair zone 402 and the second stair zone 412 may not be symmetrical with respect to the bridge structure 404. By asymmetrically arranging the stairs within adjacent stair zones, the mechanical stresses introduced by the stair structure 400 can be distributed more evenly. In other examples, it is understood that the first stair zone 402 and the second stair zone 412 may also be symmetrical in the y-direction.

[0041] As part of the stack structure 401, the bridge structure 404 may include conductive and dielectric layers (not shown) arranged alternately in the vertical direction, and the conductive layers (e.g., metal or polysilicon layers) may function as part of the word lines. Unlike at least some steps in the first and second step zones 402 and 412 where the word lines within are disconnected from the memory array structure in the x-direction (e.g., positive x-direction, negative x-direction, or both), the word lines in the bridge structure 404 can be saved to bridge word line contacts that land on the steps and memory array structure to achieve a bidirectional word line driving scheme. In some embodiments, at least one step of the steps in the first or second step zone 402 or 412 is electrically connected to at least one of the first and second memory array structures through the bridge structure 404. At least one word line can extend laterally in the memory array structure and the bridge structure 404, thereby allowing at least one step to be electrically connected to at least one of the first and second memory array structures through the bridge structure 404 by at least one word line. In one example, a step in step 406-1 may be electrically connected to the first memory array structure (in the negative x direction) by each word line portion extending in the negative x direction through the bridge structure 404. However, since the bridge structure 404 is not separated by each word line portion extending in the positive x direction, it may not be necessary to electrically connect the same step to the second memory array structure (in the positive x direction). In another example, a step in step 416-2 may be electrically connected to the second memory array structure (in the positive x direction) by each word line portion extending in the positive x direction through the bridge structure 404. However, since the bridge structure 404 does not separate each word line portion extending in the negative x direction, it may not be necessary to electrically connect the same stage to the first memory array structure (in the negative x direction).

[0042] In some embodiments, at least one step of a staircase within the first or second staircase zone 402 or 412 is electrically connected to each of the first and second memory array structures through a bridge structure 404. For example, as shown in Figure 4, a step within staircase 416-1 may be electrically connected to both the first and second memory array structures through the bridge structure 404 by respective word line portions extending in the negative and positive x directions, respectively, as indicated by current paths (indicated by arrows).

[0043] Figures 5A to 5F show various exemplary masks for forming exemplary staircase structures of a 3D memory device according to several embodiments of the present disclosure. Figures 6A and 6B show fabrication processes for forming exemplary staircase structures of a 3D memory device according to various embodiments of the present disclosure. Figure 8 is a flowchart of method 800 for forming exemplary staircase structures of a 3D memory device according to several embodiments. Figure 9 is a flowchart of another method 900 for forming exemplary staircase structures of a 3D memory device according to several embodiments. Examples of staircase structures depicted in Figures 6A, 6B, 8, and 9 include staircase structure 400 depicted in Figure 4. Figures 5A to 5F, 6A, 6B, 8, and 9 will be described together. The operations shown in methods 800 and 900 are not exhaustive, and it is understood that other operations may be performed before, after, or between any of the exemplary operations. Furthermore, some of these operations may be performed simultaneously or in a different order than those shown in Figures 8 and 9.

[0044] Referring to Figure 8, Method 800 begins with Operation 802, and a stair zone mask is patterned, which includes openings for a first stair zone and a second stair zone located in the middle of the stack structure. In some embodiments, the stair zone mask includes a hard mask. The stack structure may include first and second material layers arranged alternately in the vertical direction. In some embodiments, the stack structure is a dielectric stack, where each of the first material layers includes a first dielectric layer (also called a “sacrificial layer”), and each of the second material layers includes a second dielectric layer distinct from the first dielectric layer. The alternating first and second dielectric layers may be deposited alternately above the substrate.

[0045] Referring to Figure 6A, a stack structure 602 is formed on a silicon substrate (not shown) that includes multiple pairs of first dielectric layers (also called “sacrificial layers,” not shown) and second dielectric layers (collectively referred to herein as “dielectric layer pairs,” not shown). That is, the stack structure 602 includes alternatingly arranged sacrificial layers and dielectric layers, according to several embodiments. The dielectric layers and sacrificial layers may be deposited alternately on the silicon substrate to form the stack structure 602. In some embodiments, each dielectric layer includes a layer of silicon oxide, and each sacrificial layer includes a layer of silicon nitride. The stack structure 602 may be formed by one or more thin-film deposition processes, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0046] In some embodiments, the stack structure is a memory stack, where each of the first material layers includes a conductive layer and each of the second material layers includes a dielectric layer. Alternating conductive layers (e.g., polysilicon layers) and dielectric layers (e.g., silicon oxide layers) may be deposited alternately on top of the substrate. The alternating conductive layers (e.g., metal layers) and dielectric layers (e.g., silicon oxide layers) may also be formed by a gate substitution process in which sacrificial layers in the dielectric stack are replaced with conductive layers. That is, the stepped structure may be formed on the dielectric stack or either before or after a gate substitution process on the memory stack.

[0047] Referring to Figure 6A, the stack structure 602 may include multiple pairs of conductive and dielectric layers (collectively referred to herein as “conductive layer / dielectric layer pairs”). That is, the stack structure 602 includes alternating conductive and dielectric layers according to several embodiments. In some embodiments, each dielectric layer includes a layer of silicon oxide, and each conductive layer includes a layer of metal, such as tungsten, or a layer of semiconductor, such as polysilicon. In some embodiments, slit openings (not shown) may be formed through the dielectric stack to form the stack structure 602, and the sacrificial layers within the dielectric stack may be etched by etchanting through the slit openings to form multiple lateral depressions, and the conductive layers may be deposited in the lateral depressions using one or more thin-film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0048] Referring to Figure 5A, the stair zone mask 502 is patterned on the stack structure 602 (shown in Figure 6A). The stair zone mask 502 includes openings 508-1 and 508-2 for multiple stair zones, including a first stair zone and a second stair zone, in the middle (for example, in the center) of the stack structure 602 (shown in Figure 6A) in the x-direction (word line direction). The stack structure 602 may include multiple blocks 504 in the y-direction (bit line direction) separated by parallel GLS 506. Each opening 508-1 or 508-2 is located in two blocks 504, traversing the respective GLS 506 between them, as shown in Figure 5A, in some embodiments. In another example, it is understood that each opening 508-1 or 508-2 may be in a single block 504 without traversing the GLS 506. The stair zone mask 502 can be used to define the stair zones of the stair structure through openings 508-1 and 508-2, so that each stair zone may correspond to one or two blocks in the final product of the 3D memory device. As shown in Figure 5A, the stair zone mask 502 covers a bridge structure 510 between adjacent openings 508-1 and 508-2 in the y-direction, in some embodiments. The bridge structure 510 within the stair zone mask 502 can define regions where a bridge structure within the stair structure in the final product of the 3D memory device may be formed, and the openings 508-1 and 508-2 within the stair zone mask 502 can define regions where stairs within the stair structure in the final product of the 3D memory device may be formed. Referring to Figure 6A, the stair zones 604 and 616 are defined by openings 508-1 and 508-2, respectively, within the stair zone mask 502, and the bridge structure 614 between the stair zones 604 and 616 in the y-direction is covered in some embodiments by a bridge structure 510 within the stair zone mask 502.

[0049] In some embodiments, the stepped zone mask 502 is a hard mask, as opposed to a soft mask (e.g., a photoresist mask), and can be made of a material that can withstand various processes until the stepped structure is formed, for example, until the delamination process in operation 808 described below. Thus, the stepped zone mask 502 can protect the covered portion of the stack structure 602 (e.g., the bridge structure 614) during subsequent processes until the stepped zone mask 502 is removed, leaving the covered portion of the stack structure 602 (and the alternating first and second material layers within it) intact. The stepped zone mask 502 can be made of, for example, polysilicon, a high-k dielectric, titanium nitride (TiN), or any other suitable hard mask material. The stepped zone mask 502 can be formed by first depositing a hard mask material layer on the stack structure 602 using one or more thin-film deposition processes, including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The hard mask material layer can then be patterned to form openings 508-1 and 508-2 using lithography and dry and / or wet etching processes such as reactive ion etching (RIE). In some embodiments, prior to the formation of the stair zone mask 502, TSG cutting steps are formed in each pair of peripheral regions (e.g., peripheral region 303 in Figure 3) adjacent to openings 508-1 and 508-2 in the x-direction.

[0050] Optionally, method 800 proceeds to operation 804, as illustrated in Figure 8, in which a second lateral division is formed at different depths in each of the first and second stair zones. Referring to Figure 9, in order to form the divisions, a division mask containing openings in the first and second stair zones is patterned in operation 902, and the multiple divisions of different depths are formed in operation 904 by one or more trim etch cycles according to the division mask. It is understood that operation 804 may be skipped in some examples where a multi-division stair structure is not used.

[0051] As illustrated in Figure 5B, the splitting mask 512 is patterned on the stair zone mask 502. In some embodiments, the splitting mask 512 includes openings 514-1 and 514-2, respectively, within openings to first and second stair zones 508-1 and 508-2 for forming splits in the y-direction. In some embodiments, the splitting mask 512 is a soft mask (e.g., a photoresist mask) and can be trimmed in a trim etch process to form splits in the y-direction. Each opening 514-1 or 514-2 may have a nominally rectangular shape. The solid lines of openings 514-1 and 514-2 in Figure 5B illustrate the boundaries of the photoresist layer covering beneath the stack structure 602 (shown in Figure 6A). The bridge structure 510 remains on the splitting mask 512 to cover beneath the bridge structure 614 (shown in Figure 6A) in some embodiments. In some embodiments, the segmented mask 512 is formed by coating a photoresist layer onto the stepped zone mask 502 using spin coating and then patterning the coated photoresist layer using lithography and development processes. The segmented mask 512 can be used as an etch mask for etching exposed portions of the stacked structure 602.

[0052] As illustrated in Figure 6A, multiple divisions of different depths (e.g., four divisions 612-1, 612-2, 612-3, and 612-4) are formed by one or more trim etch cycles (e.g., two trim etch cycles) in the y direction according to a division mask 512 (shown in Figure 5B). A division mask 512 having openings 514-1 and 514-2 (represented by solid lines) can be used as a first etch mask. The portion of the stack structure 602 exposed by the first etch mask can be etched to the division depth using a wet etch and / or dry etch process. Any suitable etchant (e.g., wet etching and / or dry etching) can be used to remove a certain thickness (e.g., division depth) of the stack structure 602 within the exposed portion. The etched thickness (e.g., division depth) can be controlled by the etch rate and / or etch time. In some embodiments, the splitting depth is nominally the same as the thickness of the material layer pair (e.g., a dielectric layer pair or a conductor / dielectric layer pair). In some embodiments, it is understood that the splitting depth is several times the thickness of the material layer pair.

[0053] As illustrated in Figure 5B, the split mask 512 can be trimmed (e.g., incrementally and inwardly etched). The dashed lines of openings 514-1 and 514-2 illustrate the boundaries of the trimmed photoresist layer covering the stack structure 602. Each of openings 514-1 and 514-2 can be trimmed in both the x and y directions due to its rectangular shape. The split mask 512 having the trimmed openings 514-1 and 514-2 (represented by dashed lines) can be used as a second etch mask.

[0054] As illustrated in Figure 6A, the amount of photoresist layer trimmed from the first etch mask may be controlled by the trim rate and / or trim time, and may be directly related to (e.g., a determinant of) the dimensions of the resulting partitions. Trimming of the first etch mask can be performed using any preferred etching process, e.g., isotropic dry etching or wet etching. Trimming of the first etch mask may result in an expansion of the portion of the stack structure 602 exposed by the first etch mask. The expanded exposed portion of the stack structure 602 can be etched again using the trimmed first etch mask as a second etch mask to form more partitions of different depths within each step zone 604 or 616. Any preferred etchant (e.g., wet etching and / or dry etching) may be used to remove a certain thickness (e.g., partition depth) of the stack structure 602 within the expanded exposed portion. The etched thickness (e.g., partition depth) may be controlled by the etch rate and / or etch time. In some embodiments, the etched thickness is nominally the same as the etched thickness in the previous etching step. As a result, the depth offset between adjacent divisions is nominally the same. In some embodiments, it is understood that the etched thickness differs in different etching steps, and the depth offset differs between adjacent divisions. The trimming process of the photoresist mask and the subsequent etching process of the stack structure are referred to herein as trim etch cycles. The number of trim etch cycles can determine the number of divisions formed according to the division mask 512. In some embodiments, the bridge structure 614 is protected from the bridge structure 510 of the untrimmed division mask 512 (shown in Figure 5B), so it remains intact after the formation of divisions 612-1, 612-2, 612-3, and 612-4 by multiple trim etch cycles (e.g., two trim etch cycles).

[0055] Figure 6A shows an example of forming a four-part staircase structure including four divisions 612-1, 612-2, 612-3, and 612-4 of different depths within each staircase zone 604 or 616. However, it is understood that multi-part staircase structures and their fabrication methods are not limited to four divisions and may be any integer greater than 1 by appropriately changing not only the number of trim etch cycles but also the design of the division mask 512.

[0056] Method 800 proceeds to operation 806, as illustrated in Figure 8, in which at least one pair of stairs facing each other in the first lateral direction is formed to the same depth in each of the first and second stair zones, thereby forming a bridge structure between the first and second stair zones in the second lateral direction perpendicular to the first lateral direction. In some embodiments, each of the at least one pair of stairs comprises multiple steps in the first lateral direction. In some embodiments, operation 806 is performed after operation 804 in which a division in the second lateral direction is formed in operation 804, i.e., the division in the second lateral direction is formed before the stairs in the first lateral direction. Referring to Figure 9, in order to form the stairs, in operation 906 a stair mask including an opening in the first lateral direction is pattern-formed, and in operation 908 at least one pair of stairs is formed to the same depth by multiple trim etch cycles according to the stair mask.

[0057] As illustrated in Figure 5C, the segmented mask 512 (shown in Figure 5B) is removed after the segmented sections 612-1, 612-2, 612-3, and 612-4 are formed, and the stair mask 516 is patterned on the stair zone mask 502. In some embodiments, the stair mask 516 comprises x-direction openings 518-1, 518-2, and 518-3, respectively, for forming pairs of staircases facing each other at the same depth. It is understood that the number of openings 518-1, 518-2, and 518-3 can determine the number of pairs of staircases facing each other to be formed, and therefore may be any preferred number depending on the arrangement of the staircase structure in the final product of the 3D memory device. In some embodiments, the stair mask 516 is a soft mask (e.g., a photoresist mask) and may be trimmed in a trim etch process to form staircases in the x direction. Each opening 518-1, 518-2, or 518-3 has a nominally rectangular shape and may extend across the openings 508-1 and 508-2 of the stair zone. The solid lines of openings 518-1, 518-2, and 518-3 in Figure 5C illustrate the boundaries of the photoresist layer covering the stack structure 602 (shown in Figure 6A). In some embodiments, the stair mask 516 is formed by coating a photoresist layer on the stair zone mask 502 using spin coating and then patterning the coated photoresist layer using lithography and development processes. The stair mask 516 may be used as an etch mask for etching exposed portions of the stack structure 602.

[0058] As illustrated in Figure 6A, multiple pairs of stairs (for example, three pairs of stairs 606-1 / 606-2, 608-1 / 608-2, and 610-1 / 610-2) are formed to the same depth within each stair zone 604 or 616 by multiple trim etch cycles according to a stair mask 516 (shown in Figure 5C). A bridge structure 614 is formed between stair zones 604 and 616 in the y-direction in some embodiments. Each pair of stairs 606-1 / 606-2, 608-1 / 608-2, or 610-1 / 610-2 faces each other in the x-direction and is at the same depth in some embodiments. Taking one pair of stairs 606-1 / 606-2 as an example, stairs 606-1 may be inclined toward the negative x-direction, and stairs 606-2 may be inclined toward the positive x-direction. Each staircase 606-1, 606-2, 608-1, 608-2, 610-1, or 610-2 may have the same number of steps in the x-direction. In some embodiments, the number of pairs of stairs in each stair zone 604 or 616 (e.g., three pairs of stairs 606-1 / 606-2, 608-1 / 608-2, and 610-1 / 610-2) is determined based on the number of openings in the stair mask 516 (e.g., three openings 518-1, 518-2, and 518-3), and the number of steps in each staircase is determined based on the number of trim etch cycles. In some embodiments, as shown in Figure 6A, a plurality of divisions 612-1, 612-2, 612-3, and 612-4 are formed prior to the formation of stairs 606-1, 606-2, 608-1, 608-2, 610-1, or 610-2, and each of the stairs 606-1, 606-2, 608-1, 608-2, 610-1, and 610-2 includes a plurality of divisions 612-1, 612-2, 612-3, and 612-4.

[0059] The trim etch process for forming steps 606-1, 606-2, 608-1, 608-2, 610-1, and 610-2 is described in detail above and will not be repeated here for the sake of clarity. The dimensions of each step in steps 606-1, 606-2, 608-1, 608-2, 610-1, and 610-2 can be determined by the amount of trimmed photoresist layer of the step mask 516 in each cycle (e.g., determining the dimension in the x-direction) and by the etched thickness in each cycle (e.g., determining the depth in the z-direction). In some embodiments, the amount of trimmed photoresist layer in each cycle is nominally the same, and therefore the dimensions of each step in steps 606-1, 606-2, 608-1, 608-2, 610-1, and 610-2 in the x-direction are nominally the same. In some embodiments, the etched thickness in each cycle is nominally the same, and therefore the depth of each step of steps 606-1, 606-2, 608-1, 608-2, 610-1, and 610-2 is nominally the same. Since the same trim etching process (e.g., the same number of trim etching cycles) is performed simultaneously through openings 518-1, 518-2, and 518-3 of the step mask 516, each step 606-1, 606-2, 608-1, 608-2, 610-1, or 610-2 can have the same depth. For example, the first pair of steps 606-1 / 606-2 may be formed through opening 518-1, the second pair of steps 608-1 / 608-2 may be formed through opening 518-2, and the third pair of steps 610-1 / 610-2 may be formed through opening 518-3. In some embodiments, the bridge structure 614 remains intact during the trim etch process.

[0060] Method 800 proceeds to operation 808, as illustrated in Figure 8, in which each of at least one pair of stairs in each of the first and second stair zones is chopped to a different depth. In some embodiments, after chopping each stair, at least one step of each stair is connected to the rest of the stack structure covered by the stair zone mask through a bridge structure by at least one of the sacrificial layers or at least one of the conductive layers. Referring to Figure 9, in order to chop the stairs, a first chop mask containing first openings in the first and second stair zones is patterned in operation 910, and the first set of stairs exposed by the first openings is chopped to a first depth by multiple etch cycles according to the first chop mask in operation 912. In some embodiments, to cut the stairs, a second cutting mask including a second opening within first and second stair zones is patterned in operation 914, and the second set of stairs exposed by the second opening is cut to a second depth by multiple etch cycles according to the second cutting mask in operation 916.

[0061] As illustrated in Figure 5D, the stair mask 516 (shown in Figure 5C) is removed after the stairs 606-1, 606-2, 608-1, 608-2, 610-1, and 610-2 are formed, and a first cutout mask 520 is patterned on the stair zone mask 502. The first cutout mask 520 includes openings 522-1 and 522-2 within the openings of the first and second stair zones 508-1 and 508-2, respectively, to cut a first set of stairs exposed by the openings 522-1 and 522-2 to the same first depth. The openings 522-1 and 522-2 of the first cutting mask 520 correspond to the steps 610-2, 610-1, and 608-2 (shown in Figures 6A and 6B), and according to the first cutting mask 520, only the steps 610-2, 610-1, and 608-2 can be cut to a first depth. Since the first cutting mask 520 does not need to be trimmed, the first cutting mask 520 can be either a hard mask or a soft mask. Each opening 522-1 or 522-2 has a nominally rectangular shape and is located in the respective opening of the step zone 508-1 or 508-2. In some embodiments where the first cutting mask 520 is a soft mask, the first cutting mask 520 is formed by coating a photoresist layer onto the step zone mask 502 using spin coating and then patterning the coated photoresist layer using lithography and development processes. In some embodiments where the first cutting mask 520 is a hard mask, the first cutting mask 520 is formed by first depositing a hard mask material layer on the stepped zone mask 502 using one or more thin film deposition processes, but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The hard mask material layer may then be patterned to form openings 522-1 and 522-2 using dry etch and / or wet etch processes such as lithography and RIE.The first cutting mask 520 can be used as an etching mask for cutting the exposed first set of steps 610-2, 610-1, and 608-2 to the same first depth.

[0062] As used herein, the “separation” process is a process of reducing the depth of one or more steps by multiple etch cycles. Each etch cycle may include one or more dry etch and / or wet etch processes that etch one step, i.e., reduce the depth by the depth of one step. As described in detail above, the purpose of the separation process is, in some embodiments, to make each step (and each step) in the final product of the 3D memory device a different depth. Thus, depending on the number of steps, a certain number of separation processes may be required.

[0063] As illustrated in Figure 5E, the first cutout mask 520 (shown in Figure 5D) is removed after the first set of stairs 610-1, 610-2, and 608-2 have been cut out, and a second cutout mask 524 is patterned on the stair zone mask 502. In some embodiments, the second cutout mask 524 includes openings 526-1 and 526-2 within the openings of the first and second stair zones 508-1 and 508-2, respectively, to cut out a second set of stairs exposed by the openings 526-1 and 526-2 to the same second depth. The openings 526-1 and 526-2 of the second cutting mask 524 correspond to steps 610-1, 608-2, 608-1, and 606-2 (shown in Figures 6A and 6B), and according to the second cutting mask 524, only steps 610-1, 608-2, 608-1, and 606-2 can be cut to a second depth. Similar to the first cutting mask 520, the second cutting mask 524 can be either a hard mask or a soft mask. The second cutting mask 524 can be used as an etch mask to cut a second exposed set of steps 610-1, 608-2, 608-1, and 606-2 to the same second depth. After the second decomposition process by the second decomposition mask 524, some steps (e.g., 610-1 and 608-2) are decomposed twice to a depth equal to the sum of the first and second depths, some steps (e.g., 610-2) are decomposed once at the first depth, some steps (e.g., 608-1 and 606-2) are decomposed once at the second depth, and some steps (e.g., 606-1) remain undecomposed.

[0064] To make each staircase 606-1, 606-2, 608-1, 608-2, 610-1, or 610-2 a different depth, one or more cutout masks and cutout processes may be required. For example, as illustrated in Figure 5F, a second cutout mask 524 (shown in Figure 5E) may be removed after a second set of staircases 610-1, 608-2, 608-1, and 606-2 has been cut out, and a third cutout mask 528 may be patterned on the staircase zone mask 502. In some embodiments, the third cutout mask 528 includes openings 530-1 and 530-2 within the openings of the first and second staircase zones 508-1 and 508-2, respectively, to cut a third set of staircases exposed by openings 530-1 and 530-2 to the same third depth. The openings 530-1 and 530-2 of the third cutting mask 528 correspond to steps 608-2 and 608-1 (shown in Figures 6A and 6B), and according to the third cutting mask 528, only steps 608-2 and 608-1 can be cut to a third depth. Similar to the first and second cutting masks 520 and 524, the third cutting mask 528 can be either a hard mask or a soft mask. The third cutting mask 528 can be used as an etch mask to cut the exposed third set of steps 608-2 and 608-1 to the same third depth. As a result, after the third cutting process by the third cutting mask 528, each step 606-1, 606-2, 608-1, 608-2, 610-1, or 610-2 can have a different depth.

[0065] In some embodiments, the stair zone mask 502 is removed after the third detangling process, i.e., after the completion of the detangling process, for example, using a wet etch and / or dry etch process. That is, in some embodiments, the stair zone mask 502 remains on the stack structure 602 at least until the detangling process in operation 808 to protect the alternating first and second material layers within the bridge structure 614 of the stair structure, as well as the memory array structure, from being etched by various trim etch and detangling processes.

[0066] The first, second, and third partitioning masks 520, 524, and 528 and the first, second, and third partitioning processes described above are examples of partitioning steps 606-1, 606-2, 608-1, 608-2, 610-1, and 610-2, and it is understood that other suitable partitioning schemes (including various partitioning masks and processes) may be used to obtain the same result. It is also understood that various partitioning schemes may achieve the same effect in which each step of the stair structure in the final product of the 3D memory device has a different depth. For example, Figures 7A to 7D show various exemplary schemes for partitioning steps into different depths within a stair structure according to some embodiments of the present disclosure. Each figure in Figures 7A to 7D illustrates one exemplary partitioning scheme that can partition six steps (represented by dashed lines in Figures 7A to 7D) into different depths. As explained above, the number of cut masks, the order of the cut masks, the design of each cut mask (e.g., the number and pattern of openings), and / or the reduced depth by each cut process (e.g., the number of etch cycles) can affect the specific depth of each step after the cut process, even though the steps are at different depths.

[0067] In one aspect of the present disclosure, a 3D memory device comprises a memory array structure and a staircase structure located in the middle of the memory array structure, which laterally divides the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone includes a first pair of stairs facing each other in a first lateral direction and at different depths. Each staircase comprises a plurality of steps. At least one step in the first pair of stairs is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

[0068] In some embodiments, each step in a first pair of stairs includes a number of second lateral divisions perpendicular to the first lateral division. In some embodiments, a step in one of the divisions is perpendicular to two steps in another of the divisions.

[0069] In some embodiments, the memory array structure comprises a second lateral block. In some embodiments, the first stair zone is located within one or two of those blocks.

[0070] In some embodiments, the staircase structure further comprises a second staircase zone. In some embodiments, the bridge structure is located between the first and second staircase zones in a second lateral direction.

[0071] In some embodiments, the second stair zone includes a second pair of stairs facing each other in the first lateral direction and at different depths. In some embodiments, the first and second stair zones are asymmetrical in the second lateral direction.

[0072] In some embodiments, the first stair zone comprises a second pair of stairs facing each other in a first lateral direction and at different depths. In some embodiments, each step of the first and second pairs of stairs is at a different depth. In some embodiments, each step of the first and second pairs of stairs is at a different depth.

[0073] In some embodiments, the 3D memory device further comprises at least one word line extending laterally within the memory array structure and the bridge structure, thereby at least one stage being electrically connected to at least one of the first and second memory array structures through the bridge structure by at least one word line.

[0074] In some embodiments, at least one step in a first pair of stairs is electrically connected to one of the first memory array structures and one of the second memory array structures through a bridge structure.

[0075] In some embodiments, the bridge structure includes alternatingly arranged conductive and dielectric layers.

[0076] In another aspect of the present disclosure, a 3D memory device comprises a memory array structure and a staircase structure located in the middle of the memory array structure, which laterally divides the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone comprises a first staircase comprising a plurality of divisions in the second lateral direction. Each division comprises a plurality of steps in the first lateral direction perpendicular to the second lateral direction. A step in one of the divisions is perpendicular to two steps in another division of the division. At least one step in the first staircase is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

[0077] In some embodiments, the first stair zone further includes a second staircase. In some embodiments, the first and second staircases face each other in the first lateral direction and have different depths.

[0078] In some embodiments, each step in the first and second staircases is at a different depth. In some embodiments, each step in the first and second staircases is electrically connected to at least one of the first and second memory array structures through a bridge structure.

[0079] In some embodiments, the memory array structure comprises a second lateral block. In some embodiments, the first stair zone is located within one or two of those blocks.

[0080] In some embodiments, the staircase structure further comprises a second staircase zone. In some embodiments, the bridge structure is located between the first and second staircase zones in a second lateral direction.

[0081] In some embodiments, the 3D memory device further comprises at least one word line extending laterally within the memory array structure and the bridge structure, thereby at least one stage being electrically connected to at least one of the first and second memory array structures through the bridge structure by at least one word line.

[0082] In some embodiments, at least one step in a first pair of stairs is electrically connected to one of the first memory array structures and one of the second memory array structures through a bridge structure.

[0083] In some embodiments, the bridge structure includes alternatingly arranged conductive and dielectric layers.

[0084] In some embodiments, the staircase structure is located in the middle of the memory array structure.

[0085] In yet another aspect of this disclosure, a method for forming a staircase structure for a 3D memory device is disclosed. A staircase zone mask is pattern-formed in the middle of a stack structure comprising a first material layer and a second material layer arranged alternately in the vertical direction, with openings for a first staircase zone and a second staircase zone. In each of the first and second staircase zones, at least one pair of stairs facing each other in a first transverse direction of the same depth is formed, thereby forming a bridge structure between the first and second staircase zones in a second transverse direction perpendicular to the first transverse direction. In each of the first and second staircase zones, each of the at least one pair of stairs is cut to a different depth.

[0086] In some embodiments, a plurality of divisions are formed at second laterally different depths before forming at least one pair of stairs, so that each step of at least one pair of stairs comprises the plurality of divisions.

[0087] In some embodiments, to form a plurality of divisions, a division mask including openings in first and second stair zones is pattern-formed, and the plurality of divisions are formed to different depths by one or more trim etch cycles according to the division mask.

[0088] In some embodiments, the bridge structure is covered by a stair zone mask or a split mask.

[0089] In some embodiments, a stair mask including a first lateral opening is pattern-formed to form at least one pair of stairs, and at least one pair of stairs is formed to the same depth by multiple trim etch cycles according to the stair mask.

[0090] In some embodiments, a first cutting mask is formed, including a first opening within first and second stair zones, to cut each staircase, and a first set of staircases exposed by the first opening is cut to a first depth by multiple etch cycles according to the first cutting mask.

[0091] In some embodiments, a second cutting mask is formed, including a second opening within first and second stair zones, to cut each staircase, and the second set of staircases exposed by the second opening is cut to a second depth by multiple etch cycles according to the second cutting mask.

[0092] In some embodiments, each of the first material layers includes a sacrificial layer, and each of the second material layers includes a dielectric layer.

[0093] In some embodiments, each of the first material layers includes a conductive layer, and each of the second material layers includes a dielectric layer.

[0094] In some embodiments, each of at least one pair of stairs comprises a first lateral number of steps. In some embodiments, after each stair is separated, at least one step of each stair is connected by at least one of the sacrificial layers or by at least one of the conductive layers to the rest of the stack structure which is covered by the stair zone mask through a bridge structure.

[0095] In some embodiments, the stair zone mask remains until at least each stair is separated. In some embodiments, the stair zone mask includes a hard mask.

[0096] The above descriptions of specific embodiments will reveal the general nature of the disclosure so that others can easily modify and / or adapt such specific embodiments to various uses without departing from the general concepts of the disclosure or conducting unnecessary experiments, by applying knowledge within the scope of the art. Such adaptations and modifications are therefore intended to fall within the meaning and scope of the equivalent embodiments of the disclosed embodiments, based on the teachings and guidance presented herein. It will be understood that the language or terminology herein is for illustrative purposes only and not limiting, and therefore should be interpreted by those skilled in the art in light of the teachings and guidance.

[0097] Embodiments of the present disclosure have been described above with the help of functional configuration blocks illustrating implementations of specified functions and their relationships. The boundaries of these functional configuration blocks are arbitrarily defined herein for the sake of clarity. Alternative boundaries may be defined insofar as the specified functions and their relationships are adequately performed.

[0098] The sections on the summary and abstract of the invention may specify one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventors, and are therefore not intended to limit the scope of the present disclosure and the accompanying claims in any way.

[0099] The breadth and scope of this disclosure should not be limited by the exemplary embodiments described above, but should be defined solely by the following claims and their equivalents. [Explanation of Symbols]

[0100] 100 3D memory devices 102 memory planes 104 Stair structure, side staircase structure 106 Memory Array Structure 200 3D memory devices 202 memory plane 204 Stair structure, central staircase structure 206-1 Memory Array Structure 206-2 Memory Array Structure 300 3D memory devices 301 Staircase structure 302 blocks 303 Peripheral area 304 Finger 306 Bridge structure 308 GLS 310 "H" cut 312 Word Line Contacts 314 Dummy channel structure 400 staircase structure 401 Stack Structure 402 First Staircase Zone 404 Bridge structure 406-1 Stairs 406-2 Stairs 408-1 Split section 408-2 Split section 408-3 Split section 408-4 Split section 410-1 Stairs 410-2 Stairs 412 Second Staircase Zone 414-1 Stairs 414-2 Stairs 416-1 Stairs 416-2 Stairs 502 Staircase Zone Mask 504 blocks 506 GLS 508-1 Opening, first staircase zone 508-2 Opening, second staircase zone 510 Bridge structure 512-part mask 514-1 Opening 514-2 Opening 516 Staircase Mask 518-1 Opening 518-2 Opening 518-3 Opening 520 First Separation Mask 522-1 Opening 522-2 Opening 524 Second cutting mask 526-1 Opening 526-2 Opening 528 Third Separation Mask 530-1 Opening 530-2 Opening 602 Stack Structure 604 Staircase Zone 606-1 Stairs 606-2 Stairs 608-1 Stairs 608-2 Stairs 610-1 Stairs 610-2 Stairs 612-1 Split section 612-2 Split section 612-3 Split section 612-4 Split section 614 Bridge structure 616 Staircase Zone

Claims

1. A memory array structure including a first memory array structure and a second memory array structure, A staircase structure located between the first memory array structure and the second memory array structure in a first lateral direction, comprising a first staircase zone and a second staircase zone, The invention comprises a first and second bridge structure located between the first and second stair zones in a second lateral direction perpendicular to the first lateral direction, wherein the first and second bridge structures are separated by a gate line slit structure, The gate line slit structure extends within the memory array structure, and the width of the gate line slit structure along the second lateral direction is constant in the first lateral direction. Each of the first stair zone and the second stair zone is, The structure includes alternating first and second sub-staircases, the alternating first and second sub-staircases being at different depths, each of the first sub-staircases including ascending steps of different depths, and each of the second sub-staircases including descending steps of different depths, and at least one step in each of the first and second sub-staircases being connected to at least one of the first and second bridge structures, Three-dimensional (3D) memory device.

2. The 3D memory device according to claim 1, wherein the first sub-staircase and the second sub-staircase of the first staircase zone, and the first sub-staircase and the second sub-staircase of the second staircase zone, are asymmetrical in the second lateral direction.

3. The 3D memory device according to claim 1, wherein in each of the first stair zone and the second stair zone, neither the first sub-stair nor the second sub-stair overlaps in a third direction perpendicular to both the first lateral direction and the second lateral direction.

4. The 3D memory device according to claim 1, wherein the memory array structure includes a plurality of blocks in the second lateral direction.

5. The 3D memory device according to claim 4, wherein the first stair zone and the second stair zone are located in different blocks.

6. The 3D memory device according to claim 1, wherein the first and second bridge structures include alternatingly arranged conductive layers and dielectric layers.

7. Each of the first sub-staircase and the second sub-staircase includes a plurality of divisions in the second lateral direction. The 3D memory device according to claim 1, wherein a step in one of the divisions is perpendicular to two steps in another division.

8. The 3D memory device according to claim 1, further comprising a row decoder directly above, directly below, or adjacent to the aforementioned staircase structure.

9. A stack structure including alternating conductive layers and dielectric layers, The structure comprises a gate line slit structure that penetrates the stack structure in a first lateral direction and divides the stack structure into a first block and a second block in a second lateral direction perpendicular to the first lateral direction, The stack structure includes a first stair zone in the first block and a second stair zone in the second block, each of the first and second stair zones including first sub-stairs and second sub-stairs arranged alternately in the first lateral direction, the alternately arranged first and second sub-stairs being at different depths, each of the first sub-stairs including a plurality of ascending steps of different depths, and each of the second sub-stairs including a plurality of descending steps of different depths. The stack structure comprises a first bridge structure adjacent to the first staircase zone in the second lateral direction within the first block, The second block further comprises a second bridge structure adjacent to the second staircase zone in the second lateral direction, A three-dimensional (3D) memory device in which the first bridge structure and the second bridge structure are separated by the gate line slit structure, and the width of the gate line slit structure along the second lateral direction is constant in the first lateral direction.

10. The 3D memory device according to claim 9, wherein the first sub-staircase and the second sub-staircase of the first staircase zone, and the first sub-staircase and the second sub-staircase of the second staircase zone, are asymmetrical in the second lateral direction.

11. The 3D memory device according to claim 9, wherein neither the first sub-staircase nor the second sub-staircase overlaps in a third direction perpendicular to both the first lateral direction and the second lateral direction.

12. The 3D memory device according to claim 9, wherein at least one step in the first stair zone is connected to the first memory array structure and the second memory array structure in the first block through the first bridge structure.

13. The 3D memory device according to claim 9, wherein at least one step in the second stair zone is connected to the first memory array structure and the second memory array structure in the second block through the second bridge structure.

14. The 3D memory device according to claim 9, wherein each of the first bridge structure and the second bridge structure includes alternatingly arranged conductive layers and dielectric layers.

15. The 3D memory device according to claim 10, wherein each of the first sub-staircase and the second sub-staircase includes a plurality of steps in the second lateral direction.

16. A memory array structure including a first memory array structure and a second memory array structure, A staircase structure located between the first memory array structure and the second memory array structure in a first lateral direction, wherein the staircase structure includes a first staircase zone and a second staircase zone, and each of the first staircase zone and the second staircase zone is A first pair of stairs, including a first descending step and a first ascending step of different depths, A second pair of stairs, including a second descending step and a second ascending step of different depths, A third pair of stairs, including a third descending step and a third ascending step of different depths, Includes a staircase structure, A first and second bridge structure located between the first and second stair zones in a second lateral direction perpendicular to the first lateral and vertical directions, and divided by a gate line slit structure, Equipped with, A three-dimensional (3D) memory device in which the gate line slit structure extends within the memory array structure, and the width of the gate line slit structure along the second lateral direction is constant in the first lateral direction.

17. The 3D memory device according to claim 16, wherein none of the first pair of stairs, the second pair of stairs, and the third pair of stairs overlap in a vertical direction perpendicular to the lateral direction of the first pair.

18. The 3D memory device according to claim 16, wherein at least one step in each of the first stair zone and the second stair zone is connected to the first memory array structure and the second memory array structure through at least one of the first and second bridge structures.

19. The 3D memory device according to claim 16, wherein the first and second bridge structures include alternatingly arranged conductive layers and dielectric layers.

20. The 3D memory device according to claim 16, further comprising a row decoder directly above, directly below, or adjacent to the aforementioned staircase structure.

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