Semiconductor equipment

Abstract

To provide a semiconductor memory device which operates at high speed, consumes low power, has increased storage capacity per unit area, and has increased capacitance of a capacitor.SOLUTION: A semiconductor memory device 300 includes a memory cell CL formed by stacking two or more sub-memory cells SCL. The sub-memory cells each include a word line WL, a bit line BL, a first capacitor Cf, a second capacitor Cb, and a transistor Tr. In the transistor, a first gate and a second gate are formed with a semiconductor film provided therebetween; the first gate and the second gate overlap with each other and are connected to the word line; one of a source and a drain is connected to a bit line; the other of the source and the drain is connected to the first capacitor and the second capacitor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Regarding semiconductor memory devices. [Background technology]

[0002] Semiconductor memory devices (also called memory devices or memory cells) include volatile memory such as DR Examples include AM (Dynamic Random Access Memory). AM (Automatic Memory) can store one bit of data using one transistor and one capacitor. It is a semiconductor memory device that has a small area per unit memory cell and can be modularized. It can be easily integrated and manufactured inexpensively.

[0003] Furthermore, by using transistors containing oxide semiconductors in DRAM, the cost of oxide semiconductors can be reduced. Due to its off-current characteristics, the charge held in the capacitor in the DRAM can be retained for a long time. This allows for a longer refresh cycle, thereby reducing power consumption. The force can be reduced (see Patent Document 1).

[0004] Furthermore, in order to increase the operating speed and storage capacity of semiconductor memory devices, microfabrication technology High integration is required. However, as the miniaturization of semiconductor memory devices progresses, semiconductors The channel length of transistors used in memory devices is short, and is represented by the gate insulating layer, etc. Various insulating layers become thinner. As a result, the leakage current of the transistor increases, and consumption Power consumption will increase.

[0005] Furthermore, in order to reduce the footprint of semiconductor memory devices, the circuit layout can be improved. It is possible to reduce the cell area occupied (see Patent Document 2).

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] Due to the miniaturization and high integration of semiconductor memory devices, the high-speed operation and memory capacity of the memory device can be increased. However, for example, DRAM is composed of transistors and capacitors. Due to miniaturization and high integration, the area of the capacitor is also reduced, and its capacitance value becomes small. Therefore, the difference in the amount of charge between the writing state and the erasing state in the memory device becomes small, making it difficult to accurately hold the stored information.

[0008] In addition, transistors using oxide semiconductors can hold the charge stored in the capacitors in DRAM for a long time due to their low off-current characteristics, reducing power consumption. However, on the other hand, the on-current is small compared to transistors using single-crystalline silicon or polycrystalline silicon. Therefore, it becomes a disadvantageous characteristic in terms of the operating speed of the memory device.

[0009] Therefore, one aspect of the present invention is to provide a semiconductor memory device with high-speed operation and low power consumption as one of the problems. [[ID=5②]] [[ID=5③]]

[0010] [[ID=5④]] Furthermore, one aspect of the present invention is to provide a semiconductor memory device with an increased memory capacity per unit area. ​​​​One of the problems is to provide it.

[0011] Another problem is to increase the capacitance of the capacitor in the semiconductor memory device.

Means for Solving the Problem

[0012] One aspect of the present invention has a memory cell having two or more sub-memory cells each having a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the memory cell, the sub-memory cells are stacked. The transistor has a first gate and a second gate formed via a semiconductor film. The first gate and the second gate are connected to the word line. One of the source and drain of the transistor is connected to the bit line, and the other of the source and drain of the transistor is connected to the first capacitor and the second capacitor. The first gate and the second gate of the transistor are superimposed and connected. A semiconductor memory device characterized by this is provided.

[0013]

[0014] In another aspect of the present invention, the first capacitor and the second capacitor in each of the sub-memory cells may be formed so as to be superimposed.

[0014] In one aspect of the present invention, the memory cell may be formed in a matrix shape in a plane.

[0015]

[0015] One aspect of the present invention uses an oxide semiconductor for the transistor.

[0016] One aspect of the present invention can form a memory cell by stacking sub-memory cells. This is because an oxide semiconductor is used for the active layer of the transistor in the sub-memory cell. This is because oxide semiconductors can be formed by deposition methods such as sputtering. By stacking and layering molycells, small-area memory cells can be fabricated, and per unit area The storage capacity of each memory module can be further increased.

[0017] Furthermore, one aspect of the present invention relates to a transistor having silicon that is stacked with submembrane cells. It can have a transistor. A silicon transistor is a stacked semiconductor memory. It is preferable to place it at the bottom layer of the apparatus, and can be formed using, for example, a silicon substrate. Furthermore, it may be formed not only on a single layer, but at multiple locations between submemory cells.

[0018] One aspect of the present invention is a semiconductor memory device characterized in that the submemory cell is DRAM. be. [Effects of the Invention]

[0019] According to one aspect of the present invention, an oxide having the characteristic of possessing both a high on-current and a low off-current. By using transistors containing semiconductors, high-speed operation and low power consumption are achieved. It can provide a storage device.

[0020] According to one aspect of the present invention, by stacking multiple submemory cells by superimposing them, the unit surface This allows us to provide a semiconductor memory device with increased storage capacity per unit area.

[0021] According to one aspect of the present invention, the capacitance of a capacitor in a semiconductor memory device can be increased. Cut. [Brief explanation of the drawing]

[0022] [Figure 1]A perspective view and a circuit diagram showing an example of a semiconductor memory device according to one aspect of the present invention. [Figure 2] A top view and a cross-sectional view showing an example of a memory cell in a semiconductor memory device according to one aspect of the present invention. [Figure 3] A top view and a cross-sectional view showing an example of a submembrane in a semiconductor memory device according to one aspect of the present invention. [Figure 4] A cross-sectional view showing an example of a memory cell manufacturing process according to one aspect of the present invention. [Figure 5] A cross-sectional view showing an example of a memory cell manufacturing process according to one aspect of the present invention. [Figure 6] A top view and a cross-sectional view showing an example of a semiconductor memory device according to one aspect of the present invention. [Figure 7] A block diagram and a circuit diagram of a part thereof showing a specific example of a CPU using a semiconductor memory device according to one aspect of the present invention. [Figure 8] A perspective view showing an example of an electronic device having a semiconductor memory device according to one aspect of the present invention. [Modes for carrying out the invention]

[0023] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is described below. The present invention is not limited to any particular form or detail and may be described in any way without departing from the spirit and scope of the present invention. Those skilled in the art will readily understand that the invention can be modified in various ways. Therefore, the present invention is as shown below. This is not to be interpreted as being limited to the description of the form of application. Furthermore, the present invention described below... In the configuration, the same reference numeral is used for identical parts or parts with similar functions across different drawings. This is used in common, and its repeated explanation will be omitted.

[0024] In each figure described herein, the size, film thickness, or region of each component is clearly indicated. It may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. .

[0025] Furthermore, the terms "first," "second," "third," etc. used in this specification are used to avoid confusion of constituent elements. This is attached to the number and does not limit it numerically. Therefore, for example, "the first" can be written as " This can be explained by replacing it with "the second" or "the third," etc., as appropriate.

[0026] In this specification, the source and drain of a transistor are referred to as the drain. The other is used as the source. That is, they are not distinguished by their potential. Therefore, In this specification, the term "source" may also be interpreted as "drain."

[0027] In this specification, the gate of a transistor is referred to as the gate or gate electrode. They are not distinguished. Furthermore, the source and drain of a transistor are referred to as source and drain, so The source region and drain region, or source electrode and drain electrode, are referred to as such, and they are distinguished from each other. do not have.

[0028] In this specification, even when the term "connect" is used, in actual circuits... In some cases, there are no physical connections, and only wiring extends. For example, insulation In a field-effect transistor (MISFET) circuit, a single wire can connect multiple MISFs. In some cases, it also serves as the gate for the ET (Electronic Timer). In that case, the circuit diagram will show a single wire leading to the gate. Sometimes it is written in a way that results in multiple branches. In this specification, even in such cases, The expression "the wiring connects to the gate" is sometimes used.

[0029] (Embodiment 1) This embodiment describes an example of the configuration and operation of a memory cell, which is a semiconductor memory device. This will be explained using Figures 1 and 2, etc.

[0030] A semiconductor memory device 300, which is one embodiment of the present invention as shown in Figure 1(A), includes a transistor, a first Capacitor (also called front capacitor (Cf)) and second capacitor (back capacitor) Also called cyanocytosis (Cb). Submembrane cells SCLs consisting of ) are stacked to form a memory cell CL A matrix was formed. The memory cell CL was arranged in a plane with a horizontal row and b vertical rows (a and b are natural numbers). It is arranged in a ribbed pattern.

[0031] The submemory cell SCL consists of a transistor, a front capacitor, and a back capacitor. It is a memory device, and in other words, it is composed of DRAM.

[0032] CL consists of SCL_1 to SCL_c, which are stacked in c layers (where c is a natural number), and each SCL_j ( j = natural numbers from 1 to c) is a transistor Tr_j (a natural number from j = 1 to c), Cf_j (j It is composed of (a natural number from 1 to c) and Cb_j (a natural number from 1 to c). Tr_j This refers to the gate of Tr_j (also called the first gate or front gate) and the semiconductor film. The gate of Tr_(j-1) superimposed on the gate via (the second gate or back gate) It is a so-called dual-gate transistor controlled by (also known as ). However, In the case of Tr_1, the back gate is not the gate of Tr_(j-1), but Tr_ The wiring superimposed on the gate via semiconductor film 1 is used as the back gate. The front gate and back gate of the transistor in the memory cell are electrically connected. It is.

[0033] Cf_j is formed from the same material and layer as the front gate in Tr_j. The capacitance of the gate insulating film between the capacitive electrode and either the source or drain of Tr_j It is formed from the capacitive electrode at Cf_(j-1) and the so of Tr_j. It is formed by the capacitance of the insulating film between the drain and one of the other.

[0034] Furthermore, Cb_1 is configured as either the source or drain of Tr_1, and separately below SCL_1. This can be achieved by the capacitance of the insulating film between the digit capacitance wiring and the surrounding wiring.

[0035] As shown in Figure 1(B), in CL consisting of SCL_1 to SCL_c, in the circuit The connection is such that, for example, looking at SCL_1, the front gate and back gate of Tr_1 are Connect to the drain line WL, and connect one of the source and drain of Tr_1 to the bit line BL_1. The source and drain of Tr_1 are connected to one end of Cf_1 and Cb_1, and Cf_1 The other end of Cb_1 is grounded (connected to GND). Furthermore, the other end of Cf_1 is It is connected to the other end of Cb_2 in SCL_2.

[0036] Furthermore, the gate and wattage of the transistors in each submemory cell that is formed by stacking The word lines are connected. Therefore, by inputting a signal into the word lines, each of the stacked layers can be connected. The transistors in the submemory cells can be driven simultaneously.

[0037] As shown in Figure 1(B), the other end of Cb_j is grounded when j is 1, and when j is 1 If it is larger, it is connected to the other end of Cf_(j-1).

[0038] A transistor with a low off-current should be used for the transistor Tr_j. For example, a bandgear By using a wide-bandgap semiconductor with a band of 2.5 eV or more, a low off-current is achieved. This allows for the formation of transistors, and the use of oxide semiconductors is particularly preferable.

[0039] By using transistors with low off-current as sub-memory cells, the front capacitor and The charge held in the buck capacitor leaks through the transistor Tr_j. This can be suppressed. As a result, the potential retention period is extended, and refresh in DRAM Because the frequency of operation can be reduced, power consumption can be lowered.

[0040] Furthermore, the transistor Tr_j shown in this embodiment has a front gate and a back gate. It is a so-called dual-gate type transistor. Therefore, the front of the transistor When a voltage greater than the threshold is applied to the gate, the transistor turns on, and furthermore, the battery Because the same voltage is applied to the gate, the threshold is shifted to the negative. Therefore, the on-current at gate voltages above a certain threshold is the same as the trough without a back gate. It becomes larger compared to a transistor. Also, the front gate of the transistor is smaller than the threshold voltage. When a voltage is applied, the transistor turns off, and the same voltage is also applied to the back gate. The pressure applied causes the threshold to shift positively. As a result, above a certain threshold... The off-current at small gate voltages is smaller compared to transistors without a back gate. Yes.

[0041] In other words, the semiconductor memory device shown in this embodiment uses a transistor having an oxide semiconductor. By adopting a configuration that combines high on-current and low off-current, high-speed operation and It is possible to reduce power consumption.

[0042] Furthermore, by adjusting the capacitance of the capacitor in each submemory cell, the data is retained. It is possible to give it multiple potentials, thereby creating a multi-level memory cell. Cut.

[0043] Next, the methods for writing and reading data to and from memory cells will be explained below.

[0044] First, data can be written to each sub-memory cell individually. In this, the potential of the word line is set to VH (transistor threshold voltage (Vth)) and VDD (power supply voltage). Let the potential be higher than the added potential. Next, let the bit line of an arbitrary selection be VDD, and Set all other bit lines to GND. This will allow the sub-mechanism connected to the selected bit line to be GND. The capacitor in the Morissel is charged with VDD. Next, the potential of the word line is set to GND. This ensures that the data is stored in the corresponding submemory cell. After that, the submemory cell is changed. Then, the data is written in order. This concludes the explanation of how to write data to a memory cell.

[0045] The data written in this manner is generated using an oxide semiconductor film according to one aspect of the present invention. Because the transistor's off-current is small, it can be maintained for a long period of time.

[0046] Next, we will explain how to read the data. Data is read for each sub-memory cell. First, set the bit line of any choice to a predetermined potential (constant potential). Next, the word line By setting this to VH, a potential corresponding to the data written to the capacitor is applied to the bit line. Then, the given potential is read out using a sense amplifier (not specifically shown in the diagram). The data is lost as soon as it is read, but it is amplified by the sense amplifier and read again. Data can be written to the main memory cell. Then, the sub-memory cell is changed, in order. The data is then read out. The above describes how to read data from a memory cell.

[0047] Furthermore, the method for writing to and reading from the memory cell is determined by the method described above for each sub-memory cell. It's not limited to that; it can also be done all at once, simultaneously.

[0048] Next, as shown in Figure 1, a memory cell CL is stacked with submemory cells SCL superimposed on it. The cross-sectional structure will be explained using Figure 2. The memory cell CL shown in Figure 2 is superimposed It consists of c submemory cells SCL_1 to SCL_c, and each submemory cell is transient Starter Tr_j (j=1 to c, a natural number), front capacitor Cf_j (j=1 to c, a natural number) It is composed of a number and a buck capacitor Cb_j (a natural number from 1 to c). Figure 2 ( Figure 2(A) shows a top view of submemory cell SCL_j, and Figure 2(B) shows submemory cells SCL_1~S A cross-sectional view of CL_c is shown.

[0049] Figure 2(A) shows the transistor Tr_j and front key in the submemory cell SCL_j. A top view of capacitor Cf_j is shown. Note that, to avoid complexity, the back capacitor is shown. Cb_j is not shown. Also, one point in the top view of SCL_j shown in Figure 2(A) The dashed line AB, the dotted-dotted line CD, and the dotted-dotted line EF correspond to the sections AB, CD, and EF. The surface is shown in Figure 2(B).

[0050] As shown in Figure 2(B), each submemory cell is stacked in a superposition, and furthermore, each submemory cell The films in the transistors and capacitors that make up the Morissel are also formed in a superimposed manner. Furthermore, the front gate (including the back gate) of the transistor in each submemory cell. (These are all electrically connected.)

[0051] Next, Figure 3 shows the cross-sectional structure of Tr_1, Cf_1, and Cb_1 in SCL_1. I will use this to explain in detail.

[0052] Figure 3(A) shows transistor Tr_1 and front key in submemory cell SCL_1. A top view of capacitor Cf_1 is shown. Note that, to avoid complexity, the back capacitor is shown. Cb_1 is not shown. Also, one point in the top view of SCL_1 shown in Figure 3(A) The dashed line AB, the dotted-dotted line CD, and the dotted-dotted line EF correspond to the sections AB, CD, and EF. The surface is shown in Figure 3(B).

[0053] The transistor Tr_1 shown in Figure 3(B) consists of a substrate 100 and a terminal provided on the substrate 100. Wiring 101 and wiring 340, and provided on wiring 101 and wiring 340 The first interlayer insulating film 102 and the underlayer insulating film provided on the first interlayer insulating film 102 104, a channel forming region 106a provided on the underlying insulating film 104, a source region and An oxide semiconductor film 106 having a drain region 106b, and a gate on the oxide semiconductor film 106. A gate insulating film 108, a gate electrode 110 and a capacitive electrode 130 on the gate insulating film 108, and The second interlayer insulating film 112 on the electrode electrode 110 and the capacitive electrode 130, and the second interlayer insulating film 1 In the contact hole provided in 12, the source region and drain region 106b are in contact It has a second wiring 114 that continues from there.

[0054] Furthermore, the capacitive electrode 130 in capacitor Cf_1 is made of the same material as the gate electrode 110. It can be formed in a single layer.

[0055] Furthermore, the third wiring 140 in capacitor Cb_1 is made of the same material as the first wiring 101 and It can be formed from the same layer.

[0056] Furthermore, the first wiring 101 functions as the back gate of transistor Tr_1.

[0057] Furthermore, it is also possible to omit the underlying insulating film 104 and use it in conjunction with the first interlayer insulating film 102. No.

[0058] Furthermore, the formation of contact holes is not limited to that shown in this embodiment. For example, a contact hole may be formed that penetrates multiple layers in one step, or layer by layer. The contact holes may be formed in multiple stages.

[0059] In this embodiment, the oxide semiconductor film 106 has a channel formation region 106a and the channel It has a source region and a drain region 106b that have lower resistance than the drain formation region 106a. By providing a source region and a drain region 106b as shown, the second wiring 114 This reduces the contact resistance, thereby improving the on-characteristics of the transistor. This can be done. However, the oxidation in which the source region and drain region 106b are formed in this manner This is not limited to the material semiconductor film 106, but does not provide a low-resistance region in the oxide semiconductor film. It can also be used as a composition.

[0060] Furthermore, the source region and drain region 106b are selected from phosphorus, boron, nitrogen, and fluorine. It contains one or more of the elements that have been identified. By adding the above elements to an oxide semiconductor film... This allows us to lower the resistance of the oxide semiconductor film.

[0061] There are no major restrictions on the substrate 100, but it should at least have enough heat resistance to withstand subsequent heat treatment. It is necessary to do so. For example, glass substrates, ceramic substrates, quartz substrates, sapphire substrates These may be used as the substrate 100. Alternatively, single crystal semiconductors such as silicon or silicon carbide may be used. Conductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as GaN, SOI (Silicon It is also possible to apply boards such as On Insulator boards on these boards. It is preferable to use a substrate 100 that is equipped with semiconductor elements.

[0062] Furthermore, a flexible substrate may be used as the substrate 100. One method for creating a transistor is to fabricate a transistor on a non-flexible substrate, and then... Another method involves peeling off the zista and transferring it to a flexible substrate, substrate 100. In that case, It is preferable to provide a delamination layer between the non-flexible substrate and the transistor.

[0063] The substrate 100 may be one that has undergone heat treatment. For example, heat treatment using a high-temperature gas may be performed. The GRTA (Gas Rapid Thermal Annealing) device used It is sufficient to use a product that has been heat-treated at 650°C for 1 to 5 minutes. The high-temperature gas used is a noble gas such as argon, or a gas like nitrogen, which is treated by heat treatment. An inert gas that does not react with the substance is used. Additionally, an electric furnace is used at 500°C for 30 minutes to 1 hour. Heat treatment may be performed in between.

[0064] The first wiring 101 and the third wiring 140 are made of molybdenum, titanium, tantalum, and tungsten. Metal materials such as aluminum, copper, chromium, neodymium, scandium, or materials primarily composed of these. It can be formed using an alloy material as a component. Also, as the first wiring 101, Semiconductor films, such as polycrystalline silicon films doped with impurity elements like nickel, and nickel-silver films. Silicide films such as reside may be used. Also, the first wiring 101 and the third wiring 1 40 may be a single-layer structure or a laminated structure.

[0065] Furthermore, the first wiring 101 and the third wiring 140 are made of indium oxide, tin oxide, and tung oxide. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, and tungsten oxide. Indium oxide containing tan, indium tin oxide containing titanium oxide, indium oxide Conductive materials such as zinc oxide and indium tin oxide with added silicon dioxide can also be used. Cut.

[0066] The first interlayer insulating film 102 and the underlayer insulating film 104 are silicon oxide, silicon oxide nitride, and nitrogen Silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide Zirconium oxide, yttrium oxide, gallium oxide, lanthanum oxide, cesium oxide, Select one or more of tantalum oxide and magnesium oxide and use them in a single layer or multilayer configuration. stomach.

[0067] Furthermore, hydrogen or moisture contained in the first interlayer insulating film 102 or the underlayer insulating film 104, etc. To remove impurities, it is preferable to perform heat treatment after the deposition of the underlying insulating film 104. The heat treatment temperature should be 350°C or higher but below the strain point of the substrate, preferably 450°C or higher and 650°C or lower. The process is carried out in the following manner. The heat treatment atmosphere can be an inert atmosphere, an oxidizing atmosphere, etc.

[0068] Furthermore, it is preferable that the first interlayer insulating film 102 and the underlayer insulating film 104 have sufficient flatness. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and Preferably, a base film is provided so that the thickness is 0.1 nm or less. This makes it easier for crystalline regions to form in the oxide semiconductor film. Note that Ra is JI Arithmetic mean rough as defined in SB 0601:2001 (ISO 4287:1997). This is a three-dimensional extension of the principle so that it can be applied to curved surfaces, and it is described as "from the reference plane to the specified plane." It can be expressed as "the average of the absolute values ​​of the deviations," and is defined by formula (1).

[0069]

number

[0070] Here, the specified surface is the surface to be measured for roughness, and the coordinates are ((x1, y1, f(x1, y1))(x1,y2,f(x1,y2))(x2,y1,f(x2,y1))(x2, Let the region be a quadrilateral represented by the four points y², f(x², y²), and project the specified plane onto the xy-plane. Let S0 be the area of ​​the rectangle and Z0 be the average height of the specified surface. Ra is measured using an atomic force microscope (AF). Measurement is possible using an Atomic Force Microscope (M).

[0071] Silicon oxiditride refers to a material in which the oxygen content is higher than the nitrogen content. For example, oxygen at 50 to 70 atomic percent and nitrogen at 0.5 to 15 atomic percent. The range is 25 atomic percent to 35 atomic percent of silicon and 0 atomic percent to 10 atomic percent of hydrogen. It refers to substances that are included in it. Also, silicon nitride oxide is a substance whose composition contains more nitrogen than oxygen. This indicates the amount of an element present in large quantities. For example, oxygen is present in 5 to 30 atomic percent, and nitrogen in 20 atomic percent. Ato% to 55 atomic%, silicon 25 atomic% to 35 atomic%, hydrogen 10 atoms This refers to substances containing between % and 25 atoms. However, the above range is defined as the Rutherford period. Rutherford Backscattering Spectrometer (RBS) (rometry) and hydrogen forward scattering (HFS) This is the result of measurements using cattering spectrometry. Furthermore, the composition of the constituent elements shall not exceed a total of 100 atomic percent.

[0072] Furthermore, the first interlayer insulating film 102 and the underlayer insulating film 104 release oxygen upon heat treatment. Using an insulating film is preferable.

[0073] "Releasing oxygen through heat treatment" refers to TDS (Thermal Desorptosis). n Spectroscopy (temperature-induced desorption gas spectroscopy) analysis, converted to oxygen atoms The amount of oxygen released is 1.0 × 10⁻⁶ 18 atoms / cm 3 Preferably 3.0 × 10 20 atoms / cm 3 This means that it is as described above.

[0074] Here, we will explain the method for measuring the amount of oxygen released in terms of oxygen atoms using TDS analysis, as follows: I will explain it to them.

[0075] When performing TDS analysis, the gas emission amount is proportional to the integral value of the spectrum. Therefore, the gas emission amount can be calculated by the ratio of the integral value of the measured spectrum to the reference value of the standard sample. The reference value of the standard sample is the ratio of the atomic density to the integral value of the spectrum of the sample containing a predetermined atom.

[0076] For example, from the TDS analysis results of a silicon wafer containing hydrogen with a predetermined density as a standard sample and the TDS analysis results of the insulating film, the oxygen molecule emission amount (N ) of the insulating film can be obtained by Equation 2. O2 Here, it is assumed that all of the spectra detected at mass number 32 obtained by TDS analysis are derived from oxygen molecules. Although there is also CH3OH as the one with mass number 32, it is not considered here as the possibility of its existence is low. Also, regarding oxygen molecules containing oxygen atoms with mass number 17 and oxygen atoms with mass number 18, which are isotopes of oxygen atoms, they are not considered because their abundance ratios in nature are extremely small.

[0077]

Equation

[0078] N H2 is the value obtained by converting the hydrogen molecules desorbed from the standard sample into density. S H2 is the integral value of the spectrum when the standard sample is subjected to TDS analysis. Here, let the reference value of the standard sample be N / S H2 H2 S O2 is the integral value of the spectrum when the insulating film is subjected to TDS analysis. α is a coefficient that affects the spectrum intensity in TDS analysis. Regarding the details of Equation 2 For further information, please refer to Japanese Patent Publication No. 6-275697. The amount of oxygen released from the insulating film is as follows: Using the EMD-WA1000S / W temperature-controlled desorption analyzer manufactured by Denshi Kagaku Co., Ltd., a standard sample and and 1 x 10 16 atoms / cm 2 Measurement is performed using a silicon wafer containing hydrogen atoms. .

[0079] Furthermore, in TDS analysis, some oxygen is detected as oxygen atoms. Oxygen molecules and oxygen atoms The ratio of these can be calculated from the ionization rate of oxygen molecules. Note that α above represents the oxygen component. Because it includes the ionization rate of the oxygen atom, by evaluating the amount of oxygen molecule released, the amount of oxygen atom released can be determined. Even if it's there, it can still be estimated.

[0080] Note N O2 This is the amount of oxygen molecules released. The amount released when converted to oxygen atoms is the amount of oxygen molecules. This will be twice the amount released.

[0081] In the case of a transistor using an oxide semiconductor film, oxygen is supplied from the underlying insulating film to the oxide semiconductor film. By supplying this material, the interface state density between the oxide semiconductor film and the underlying insulating film can be reduced. Due to the operation of transistors, etc., carriers can form at the interface between the oxide semiconductor film and the underlying insulating film. This can suppress the capture of certain particles, resulting in a more reliable transistor. .

[0082] Furthermore, electric charge can be generated due to oxygen vacancies in oxide semiconductor films. Generally, oxide semiconductors Oxygen deficiencies in a conductive film cause some of them to act as donors, releasing electrons which are carriers. As a result, The threshold voltage of the transistor shifts in the negative direction. Therefore, from the underlying insulating film... The oxide semiconductor film is supplied with sufficient oxygen, preferably with an excess of oxygen. This is a factor that causes the threshold voltage to shift in the negative direction, specifically oxide semiconductors. This can reduce the oxygen deficiency density of the body membrane.

[0083] The material used for the oxide semiconductor film 106 is at least indium (In) or sub- It is preferable that it contains lead (Zn). It is particularly preferable that it contains In and Zn. Stabilizer for reducing variations in the electrical characteristics of transistors using a monocrystalline semiconductor film 106 It is preferable that the zer also contains gallium (Ga) in addition to those. As a material, it is tin (Sn), hafnium (Hf), aluminum (Al), titanium (Ti It is preferable that it has ) or zirconium (Zr).

[0084] Also, other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lu It may contain one or more types of tecium (Lu).

[0085] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn-based oxides. Substances, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides Materials, In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides (IGZO and (Also written as), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Z n-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides Oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn acids In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides Materials, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides In-Yb-Zn oxides, In-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn -Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf-Al-Zn acids Monsters can be used.

[0086] The oxide semiconductor film 106 is a single crystal, polycrystalline (also called polycrystal), or amorphous Which state will it take?

[0087] Preferably, the oxide semiconductor film 106 is CAAC-OS (C Axis Aligned The film is made of crystalline oxide semiconductor material.

[0088] CAAC-OS films are neither perfectly single crystals nor perfectly amorphous. This is an oxide semiconductor film with a crystalline-amorphous multiphase structure having a crystalline portion in an amorphous phase. The crystalline portion is often small enough to fit within a cube with sides less than 100 nm long. Transmission Electron Microscope (TEM) Observation images using a scope show the boundary between amorphous and crystalline parts in the CAAC-OS film. It is not clear. Also, TEM reveals grain boundaries in the CAAC-OS film. - Also known as. ) cannot be confirmed. Therefore, the CAAC-OS film does not exhibit electron transfer due to grain boundaries. The decrease in mobility is suppressed.

[0089] The crystalline portion contained in the CAAC-OS film has a c-axis that is the normal vector to the surface on which the CAAC-OS film is formed. Aligned in a direction parallel to the normal vector of the plane or surface, and triangular when viewed from a direction perpendicular to the ab plane. Having a shape or hexagonal atomic arrangement, the metal atoms are layered or when viewed from a direction perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. Furthermore, the a-axis and between different crystalline regions are as follows: The orientation of the b-axis may be different. In this specification, when it is simply described as vertical, 85 The range of ° to 95° is also included. Furthermore, when simply described as parallel, -5° is used. This also includes the range of 5° or less.

[0090] Furthermore, the distribution of crystalline regions in the CAAC-OS film does not need to be uniform. For example, CAA In the formation process of a C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the shape The proportion of crystalline material may be higher near the surface compared to near the surface of the material. Also, CA By adding impurities to the AC-OS film, the crystalline region in the impurity-added area becomes amorphous. It can also become qualitative.

[0091] The c-axis of the crystalline portion contained in the CAAC-OS film is the normal vector to the surface on which the CAAC-OS film is formed. Because it aligns in a direction parallel to the normal vector of the surface or the material, the shape of the CAAC-OS film (formed Depending on the cross-sectional shape of the surface or face, they may face in different directions. Oh, the direction of the c-axis of the crystalline portion is the normal vector to the surface on which the CAAC-OS film was formed. The direction is parallel to the normal vector of the crystalline or surface. The crystalline portion is formed by deposition, and It is formed by performing crystallization treatments such as heat treatment after film formation.

[0092] Transistors using CAAC-OS film exhibit changes in electrical properties due to irradiation with visible light and ultraviolet light. Its value is small. Therefore, this transistor is highly reliable.

[0093] Furthermore, some of the oxygen constituting the oxide semiconductor film may be replaced with nitrogen.

[0094] Furthermore, in oxide semiconductors with crystalline regions, such as CAAC-OS, bulk defects can be reduced even further. It can be reduced. Furthermore, by increasing the flatness of the surface, the amorphous state can be reduced. It is possible to obtain mobility higher than that of oxide semiconductors. To improve surface flatness, a flat surface It is preferable to form an oxide semiconductor on the surface, specifically, the average surface roughness (Ra) is 1 Formed on a surface with a wavelength of 0.3 nm or less, preferably 0.1 nm or less. It would be good to do so.

[0095] Oxide semiconductor films are produced using sputtering and MBE (Molecular Beam Epoxy). Taxy method, CVD method, pulsed laser deposition, ALD (Atomic Layer Deposition) Methods such as eposition can be used as appropriate. In addition, oxide semiconductor films can be spalled. With multiple substrate surfaces set approximately perpendicular to the surface of the taring target, the film is deposited. The film may also be deposited using a sputtering apparatus.

[0096] Furthermore, oxide semiconductor films contain almost no impurities such as copper, aluminum, and chlorine. It is desirable that it be highly purified. In the transistor manufacturing process, By appropriately selecting a process that does not pose a risk of these impurities being introduced or adhering to the oxide semiconductor film surface, Preferably, if it adheres to the surface of an oxide semiconductor film, it is exposed to oxalic acid or dilute hydrofluoric acid. Alternatively, by performing plasma treatment (such as N2O plasma treatment), the surface of the oxide semiconductor film can be modified. It is preferable to remove impurities from the surface. Specifically, the copper concentration of the oxide semiconductor film is 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 1 × 10 17 atoms / cm 3 The following applies: Furthermore, the aluminum concentration in the oxide semiconductor film is 1 × 10⁻⁶ 18 atoms / cm 3 The following applies: Furthermore, the chlorine concentration of the oxide semiconductor film is 2 × 10⁻⁶. 18 atoms / cm 3 The following applies:

[0097] The gate insulating film 108 can be formed by plasma CVD or sputtering. It can produce silicon oxide, silicon oxide nitride, aluminum oxide, aluminum oxide nitride, acid Hafnium oxide, gallium oxide, magnesium oxide, tantalum oxide, yttrium oxide, acid Select one or more materials containing zirconium oxide, lanthanum oxide, and neodymium oxide, and form a single layer Alternatively, they can be used in a stacked configuration.

[0098] Furthermore, the gate insulating film 108 is made of hafnium oxide, yttrium oxide, and hafnium. Silicate (HfSi x O y (x>0, y>0), nitrogen-added hafnium silicate (HfSiO x N y (x>0, y>0), hafnium aluminate (HfAl x O y (x>0, y>0), by using high-k materials such as lanthanum oxide, gate The break current can be reduced. Also, when the gate insulating film 108 is used as a capacitor, the capacitance can be increased. It is preferable because it can be added. Also, the gate insulating film 108 may be a single layer structure. It can also be used as a laminated structure.

[0099] The gate electrode 110 and the capacitive electrode 130 are made of molybdenum, titanium, tantalum, and tungsten. Metal materials such as aluminum, copper, chromium, neodymium, scandium, or materials mainly composed of these It can be formed using an alloy material such as phosphorus as the gate electrode 110. Semiconductor films, such as polycrystalline silicon films doped with impurity elements, and nickel silicon A silicide film such as an id may be used. The gate electrode 110 may have a single-layer structure. A laminated structure may also be used.

[0100] Furthermore, the gate electrode 110 and the capacitive electrode 130 are made of indium tin oxide and tungsten oxide. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium oxide Conductive materials such as indium tin oxide with added zinc and silicon dioxide can also be used. ru.

[0101] Furthermore, a nitrogen-containing metal oxide is used as one layer of the gate electrode 110 that is in contact with the gate insulating film 108. Specifically, materials such as nitrogen-containing In-Ga-Zn-O films and nitrogen-containing In-Sn-O films. , In-Ga-O film containing nitrogen, In-Zn-O film containing nitrogen, Sn-O film containing nitrogen Films, nitrogen-containing In-O films, and metal nitride films (InN, SnN, etc.) can be used. These films are designed to withstand temperatures of 5 eV (electron volts), preferably 5.5 eV (electron volts) or higher. It has a function, and when used as a gate electrode layer, the threshold voltage of the transistor's electrical characteristics This can be turned into a positive.

[0102] The second interlayer insulating film 112 is formed from the same material as the underlying insulating film 104.

[0103] The second interlayer insulating film 112 preferably has a low relative permittivity and sufficient thickness. For example, using a silicon oxide film with a relative permittivity of approximately 3.8, and with a wavelength of 300 nm to 1000 nm The following thickness is acceptable. The surface of the interlayer insulating film 112 is slightly hardened due to the influence of atmospheric components, etc. It has a constant charge, and as a result, the threshold voltage of the transistor may fluctuate. Therefore, the interlayer insulating film 112 is within a range such that the influence of charges generated on the surface is sufficiently small. It is preferable to specify the relative permittivity and thickness.

[0104] The second wiring 114 is made of aluminum (Al), chromium (Cr), copper (Cu), tantalum ( Elements selected from Ta, titanium (Ti), molybdenum (Mo), and tungsten (W) Metal films containing the above-mentioned elements, or metal nitride films (titanium nitride film, molybdenum nitride film) Den film, tungsten nitride film, etc. can be used. In addition, metal films such as Al and Cu can be used. A high-melting-point metal film such as Ti, Mo, or W is applied to either the lower or upper side, or both sides. A structure in which a nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.) is laminated. It may also be formed from a conductive metal oxide. These include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), and oxide Indium tin oxide (In2O3-SnO2, abbreviated as ITO), indium oxide Zinc (In2O3-ZnO) or these metal oxide materials containing silicon oxide You can use this.

[0105] (Transistor fabrication method) Next, one point of the submemory cell SCL_1 shown in Figure 3(B) Transistor Tr_1, front capacitor Cf_1, and back capacitor in the cross-section shown by the dashed line AB. The method for fabricating capacitor Cb_1 will be explained using Figures 4 and 5.

[0106] First, the first wiring 101 and the third wiring 140 are formed on the substrate 100 (Figure 4(A)). (See reference.) The first wiring 101 and the third wiring 140 have a conductive film deposited on the substrate 100. The conductive film is then processed to form the first wiring 101 and the third wiring 140. Depending on the 100, a separate connection may be made between the circuit board 100 and the first wiring 101 and the third wiring 140. An insulating film may be provided in between. For example, to prevent the diffusion of impurities from the substrate, A silicon nitride film with locking ability may be formed.

[0107] Note that "processing" refers to the process of creating something using photolithography unless otherwise specified. This refers to obtaining a film of a desired shape by using a resist mask and performing an etching process.

[0108] The conductive film can be etched using either dry etching or wet etching, or both. You may also use [this].

[0109] Next, the first interlayer insulating film 102 is applied to the substrate 100, the first wiring 101, and the third wiring 140. and a base insulating film 104 is formed (see Figure 4(B)). The first interlayer insulating film 102 and the base The insulating film 104 is grown using chemical vapor deposition (CVD). Methods include sputtering, molecular beam epitaxy (MBE), and the ion method. Beam Epitaxy or pulsed laser deposition (PLD) The film can be deposited using the (ser Deposition) method, and sputtering is preferred. It's nice.

[0110] Furthermore, the first interlayer insulating film 102 is applied to the substrate 100, the first wiring 101, and the third wiring 140. After forming, it is preferable to perform a surface planarization treatment. Planarization treatment can be performed, for example, chemical mechanical polishing. Using the Chemical Mechanical Polishing (CMP) method The surface of the first interlayer insulating film 102 is flattened, and then the underlayer insulating film 104 is formed. This planarization suppresses the formation of the thin film in subsequent processes. This can control and improve exposure accuracy in photolithography. After the formation of the interlayer insulating film 102 and after the formation of the underlayer insulating film 104, a planarization treatment is performed. Alternatively, the planarization treatment may be performed only after the formation of the underlying insulating film 104.

[0111] The planarization treatment is not particularly limited, but may include CMP treatment, dry etching treatment, etc. Plasma treatment and other methods can be used.

[0112] Furthermore, hydrogen or moisture contained in the first interlayer insulating film 102 or the underlayer insulating film 104 may also be present. To remove impurities, heat is applied after the formation of the first interlayer insulating film 102 or the underlayer insulating film 104. It is preferable to perform the treatment. The heat treatment temperature is preferably 350°C or higher and below the strain point of the substrate. The process is carried out at a temperature between 450°C and 650°C. The heat treatment atmosphere can be an inert atmosphere, an oxidizing atmosphere, etc. You can do it this way.

[0113] Next, an oxide semiconductor film is deposited on the underlying insulating film 104. The deposition of the oxide semiconductor film is performed using CV The film can be deposited using the D method, sputtering method, MBE method, or PLD method, and sputtering method It is preferable to use [this].

[0114] In the deposition of oxide semiconductor films, the oxide semiconductor film should contain as little hydrogen or water as possible. To achieve this, as a pretreatment for deposition of oxide semiconductor films, the base is processed in the processing chamber of the sputtering apparatus. The board is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 100 and the underlying insulating film 104 are removed. It is preferable to detach them.

[0115] Furthermore, before depositing the oxide semiconductor film, a planarization treatment may be performed on the surface of the underlying insulating film 104. stomach.

[0116] For plasma processing, reverse sputtering can be performed. Reverse sputtering is, For example, in an argon atmosphere, a voltage is applied to the substrate side using an RF power supply, and near the substrate... This method involves forming a plasma to modify the surface to be treated. Note that nitrogen can be used instead of an argon atmosphere. Helium, oxygen, etc., may also be used.

[0117] Furthermore, oxide semiconductor films are formed under conditions where a large amount of oxygen is present during film formation (for example, 100% oxygen). It is preferable to deposit the film by sputtering in a % atmosphere.

[0118] After forming the oxide semiconductor film, a heat treatment may be performed. When this heat treatment is performed, the oxide semiconductor The degree of crystallinity of the film increases. Also, the concentration of impurities (hydrogen and water, etc.) in the oxide semiconductor film increases. It can reduce the defect level.

[0119] The heat treatment is performed using one of the following atmospheres: an oxidizing atmosphere, an inert atmosphere, a reduced pressure atmosphere, and a dry air atmosphere. This can be done by combining two or more types. Preferably, the heat treatment is carried out in an inert atmosphere, The following heat treatment is performed in an oxidizing atmosphere. The heat treatment temperature is between 150°C and 650°C. Preferably a temperature of 250°C to 500°C, and more preferably 300°C to 450°C. It should be done at a suitable temperature. Heat treatment can be performed using resistance heating, lamp heaters, or heated gases. Use it.

[0120] An oxidizing atmosphere is an atmosphere that contains oxidizing gases. Oxidizing gases include oxygen, ozone, and It is preferably nitrous oxide or the like, and does not contain water, hydrogen, etc. For example, heat treatment The purity of oxygen, ozone, and nitrous oxide introduced into the device must be 8N (99.999999%) or higher. Preferably, the nitrogen content should be 9N (99.9999999%) or higher. In the oxidizing atmosphere, oxidizing gas The oxidizing gas may be mixed with an inert gas. In that case, the oxidizing gas must be at least 10 ppm. The atmosphere shall contain the above. Heat treatment in an oxidizing atmosphere will reduce the acidity of the oxide semiconductor film. This can reduce the density of primary defects.

[0121] An inert atmosphere refers to an atmosphere whose main component is inert gases such as nitrogen and noble gases. The atmosphere should contain less than 10 ppm of reactive gases such as oxidizing gases. By performing a heat treatment, the concentration of impurities contained in the oxide semiconductor film can be reduced. .

[0122] A reduced pressure atmosphere refers to an atmosphere in the processing chamber where the pressure is 10 Pa or less. Heat treatment in a reduced pressure atmosphere This method further reduces the impurity concentration in the oxide semiconductor film compared to an inert atmosphere. It is possible.

[0123] A dry air atmosphere is defined as an oxygen atmosphere with a dew point of -40°C or lower, preferably -50°C or lower, and containing about 20% oxygen. It refers to an atmosphere containing approximately 80% nitrogen. It is a type of oxidizing atmosphere, but relatively low cost. Because it is a type, it is suitable for mass production.

[0124] Next, the oxide semiconductor film is processed to form the oxide semiconductor film 103 (see Figure 4(C)). .

[0125] Note that etching of oxide semiconductor films can be done by either dry etching or wet etching. Both may be used. The etching solution used for wet etching of oxide semiconductor films and For example, a solution of phosphoric acid, acetic acid, and nitric acid can be used. Also, ITO-07 N (manufactured by Kanto Chemical Co., Ltd.) may also be used. In addition, ICP (Inductively Coupling) may be used. Dry etching using an inductively coupled plasma etching device. You may go.

[0126] Furthermore, the oxide semiconductor film contains oxygen (at least oxygen radicals, oxygen atoms, and oxygen ions). Oxygen may be supplied into the membrane by introducing (including either of the following).

[0127] By introducing oxygen into an oxide semiconductor film and supplying oxygen to the film, the oxide semiconductor film This compensates for oxygen deficiencies and brings the material closer to an intrinsic semiconductor. To further improve reliability by shifting the threshold of transistors using conductive films to a positive value. It is possible.

[0128] Methods for introducing oxygen include ion implantation, ion doping, and plasma treatment. It is possible.

[0129] Next, a gate insulating film 108 is formed on the oxide semiconductor film 103. The gate insulating film 108 may be formed by a CVD method, a sputtering method, an MBE method, or a PLD method. In particular, it is preferable to use the sputtering method.

[0130] Next, a resist mask 107 is formed on the gate insulating film 108. The resist mask 107 is formed by performing exposure and development processes after applying a resist.

[0131] Next, using the resist mask 107 as a mask, a dopant is added to the oxide semiconductor film 103. The oxide semiconductor film 103 to which the dopant is added is made to have a lower resistance. In this way, by adding a dopant to the oxide semiconductor film 103, a source region and a drain region 106b that have been doped with the dopant and have a lower resistance, and a channel formation region 106a that has not been doped with the dopant are formed, and an oxide semiconductor film 106 having these is formed (refer to FIG. 5(A)). ).

[0132] The dopant is an impurity that reduces the resistance of the oxide semiconductor film, and one or more elements selected from phosphorus (P), boron ( B), nitrogen (N), and fluorine (F) can be used.

[0133] As a method for adding the dopant, an ion implantation method, an ion doping method, or the like can be used. Also, it may be performed while heating the substrate 100 at that time.

[0134] Note that the process of adding the dopant may be performed multiple times, and multiple types of dopants may also be used.

[0135] ​​​​​Also, heat treatment may be performed after the addition of the dopant. The heating conditions are 300 °C or higher and 700 °C or lower, preferably 300 °C or higher and 450 °C or lower for 1 hour in an oxygen atmosphere. Further, heat treatment may be performed in a nitrogen atmosphere, under reduced pressure, or in air (ultra-dry air).

[0136] Next, after removing the resist mask 107, a conductive film is formed on the gate insulating film, and the conductive film is processed by etching to form the gate electrode 110 and the capacitor electrode 130 (see FIG. 5(B)).

[0137] Next, a second interlayer insulating film 112 is formed on the gate insulating film 108, the gate electrode 110, and the capacitor electrode 130. The second interlayer insulating film 112 may be formed by CVD, sputtering, MBE, PLD, or spin coating, and can be formed of the same material as the underlying insulating film 104. Further, a contact hole is formed in the second interlayer insulating film 112 to expose a part of one of the source region and the drain region 106b, and a second wiring 114 that connects to one of the source region and the drain region 106b is formed (see FIG. 5(C)).

[0138] Also, the transistor structure in this embodiment shows a planar transistor structure, but is not limited thereto. A top gate top contact type, a top gate bottom contact type, a bottom gate top contact type, a bottom gate bottom contact type, etc., in which source and drain electrodes are formed in contact with the oxide semiconductor film may be used. Further, in the upper surface shape of the transistor, in this embodiment, a rectangular shape is shown, but it may be formed in a circular (circle) shape or the like.

[0139] As shown above, the gate electrode 110 (front gate electrode) superimposed on the channel formation region 106a Dual gate having (also called a back gate) and first wiring 101 (also called a back gate). A transistor Tr_1 with a diaphragm structure can be formed. Furthermore, the source region and drain region can be formed. Front capacitor Cf_1 formed by the other side of the in region 106b and the capacitive electrode 130 The other of the source region and drain region 106b and the third wiring 140 form a A buck capacitor Cb_1 can be formed.

[0140] In this embodiment, in a transistor in which a channel region is provided in an oxide semiconductor film, By incorporating a front gate and a back gate, it achieves high on-current and low off-current. A transistor possessing these combined characteristics can be provided. This makes it possible to provide semiconductor memory devices that operate at high speed and consume less power.

[0141] According to one aspect of the present invention, a front capacitor and a back capacitor can be formed. This makes it possible to increase the capacitance of capacitors in semiconductor memory devices.

[0142] By using the transistor and capacitor according to one aspect of the present invention, DRAM A semiconductor memory device can be formed. Furthermore, multiple semiconductor memory devices can be stacked by superimposing them. By doing so, we can provide a semiconductor memory device that increases the storage capacity per unit area. It is possible.

[0143] This embodiment can be used in combination with other embodiments as appropriate.

[0144] (Embodiment 2) In this embodiment, a semiconductor memory device having a structure different from that of Embodiment 1 will be described with reference to FIG. 6 The difference from Embodiment 1 is that, in addition to the memory cells formed using transistors having an oxide semiconductor, a semiconductor memory device further having transistors having silicon is provided.

[0145] Since the transistors having silicon have a larger field-effect mobility than the transistors having an oxide semiconductor, they are preferably used for peripheral circuits of memory cells and the like. Further, the transistors having silicon are preferably provided below the memory cells formed by stacking sub-memory cells, but may be provided in a layer between the stacked sub-memory cells, and further either a single layer or a plurality of layers may be used.

[0146] In this embodiment, a semiconductor memory device in which transistors having silicon are formed in the lowermost layer and the memory cells shown in Embodiment 1 are stacked thereon will be described.

[0147] FIG. 6 shows a top view and a cross-sectional view of the semiconductor memory device in this embodiment. FIG. 6(A) shows a top view of the sub-memory cell SCL_j, and FIG. 6(B) shows a cross-sectional view of the sub-memory cells SCL_1 to SCL_c As shown in FIG. 6(B), a layer having a transistor 800 having silicon is formed below the memory cell CL in which the sub-memory cells are stacked.

[0148] FIG. 6(A) shows a top view of the transistor Tr_j and the front capacitor Cf_j in the sub-memory cell SCL_j. Note that, to avoid complexity, the back capacitor capacitor ​​​​​​Cb_j is not shown. Also, one point in the top view of SCL_j shown in Figure 6(A) The dashed line AB, the dotted-dotted line CD, and the dotted-dotted line EF correspond to the sections AB, CD, and EF. The surface is shown in Figure 6(B).

[0149] Figure 6(C) shows a cross-sectional view of transistor 800, which has silicon.

[0150] The transistor 800 has a channel formation region 201 provided on the silicon substrate 200, and An impurity region 206 is provided so as to sandwich the channel formation region 201, and the channel formation region 2 A gate insulating layer 208 provided on 01, and a gate insulating layer 208 provided on the gate insulating layer 208 A pole 210, a first interlayer insulating film 212 on the gate electrode 210 and the impurity region, and a first layer In the contact hole provided in the inter-insulating film 212, the source electricity connects with the impurity region 206. Electrode and drain electrode 214, first interlayer insulating film 212, source electrode and drain electrode 2 It has a second interlayer insulating film 216 on 14.

[0151] Furthermore, an element isolation insulating layer 203 surrounds the transistor 800 on the silicon substrate 200. A system is in place.

[0152] Furthermore, a sidewall insulating film is formed on the side wall of the gate electrode 210 to form an LDD region. This configuration is also acceptable. However, in order to achieve high integration, as shown in Figure 6(C), It is desirable that the 800 inverter does not have a sidewall insulating layer.

[0153] Next, as shown in Embodiment 1, the second interlayer insulating film 216 in the transistor 800 The first wiring 101 and the third wiring 140 should be formed sequentially from above.

[0154] As shown above, a transistor 800 having silicon and the transistor 800 on By stacking them, a transistor using the dual-gate type oxide semiconductor shown in Embodiment 1 is formed. Tr_j can be formed. Furthermore, the other of the source region and drain region 106b The front capacitor Cf_j is formed by the capacitive electrode 130, and the source region and drain Back capacitor Cb_j formed by the other side of the in region 106b and the third wiring 140. It is possible to form this.

[0155] This embodiment includes a transistor 800 having silicon and a semiconductor having an oxide semiconductor film. It is possible to form transistors, and furthermore, transistors having an oxide semiconductor film By providing a front gate and a back gate, high on-current and low off-current are achieved. A transistor having characteristics that also possess current can be provided. By using this, it is possible to provide a semiconductor memory device that operates at high speed and consumes low power. Cut.

[0156] According to one aspect of the present invention, in a submemory cell, the front capacitor and back capacitor A semiconductor memory device having two capacitors can be formed, and thus has two capacitors This allows for an increase in the total capacitance of capacitors in a semiconductor memory device.

[0157] By using the transistor and capacitor according to one aspect of the present invention, DRAM A semiconductor memory device can be formed. Furthermore, multiple semiconductor memory devices can be stacked by superimposing them. By doing so, we can provide a semiconductor memory device that increases the storage capacity per unit area. It is possible.

[0158] Furthermore, transistors made of silicon are superior to transistors made of oxide semiconductors. Due to its high field-effect mobility, it can be used in peripheral circuits of memory cells, etc. The cell and peripheral circuits can be fabricated on the same substrate.

[0159] This embodiment can be used in combination with other embodiments as appropriate.

[0160] (Embodiment 3) Using at least a portion of the semiconductor memory device shown in Embodiment 1 or Embodiment 2, CP A Central Processing Unit (U) can be configured.

[0161] Figure 7(A) is a block diagram showing the specific configuration of the CPU. On board 1190, there is an arithmetic logic unit (ALU). t)1191, ALU controller 1192, instruction decoder 1193, i Interrupt controller 1194, timing controller 1195, register 1196 , register controller 1197, bus interface (Bus I / F) 1198, Rewritable ROM 1199 and ROM interface (ROM I / F) 118 It has 9. The substrate 1190 can be a semiconductor substrate, an SOI substrate, a glass substrate, etc. ROM1199 and ROM interface 1189 may be provided on separate chips. Of course, the CPU shown in Figure 7(A) is merely one example of a simplified configuration, and the actual C PUs have a wide variety of configurations depending on their intended use.

[0162] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to decoder 1193, decoded, and then processed by ALU controller 1192, interface Raptor controller 1194, register controller 1197, timing controller It is entered into 1195.

[0163] ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal for that purpose. Also, the interrupt controller 1194 is the CPU programmer. During execution, interrupt requests from external input / output devices and peripheral circuits are prioritized and masked. The state is judged and processed. The register controller 1197 adds register 1196 It generates a response and reads or writes to register 1196 depending on the CPU state.

[0164] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates a signal that controls the timing of the operation of the zista controller 1197. For example, The ming controller 1195 uses the reference clock signal CLK1 to generate the internal clock signal C It is equipped with an internal clock generation unit that generates LK2, and the internal clock signal CLK2 is used by the above-mentioned It supplies power to the seed circuit.

[0165] In the CPU shown in Figure 7(A), a memory element is provided in register 1196. The memory element of TA 1196 uses a semiconductor memory device as shown in Embodiment 1 or Embodiment 2. It is possible to be there.

[0166] In the CPU shown in Figure 7(A), the register controller 1197 is ALU1191 or Following their instructions, the hold operation is performed in register 1196. That is, register 1196 In the memory elements, is data retention performed using logic elements that invert logic (values)? Data is held by a capacitor. Data is inverted by a logic element. If the value is held, the power supply voltage is supplied to the memory element in register 1196. If data is held by a capacitor, rewriting the data to the capacitor. This process is performed, and the supply of power voltage to the memory elements in register 1196 can be stopped.

[0167] Regarding power shutdown, as shown in Figure 7(B) or Figure 7(C), the memory element group and the power supply A switching element is provided between nodes where the voltage VDD or power supply potential VSS is given. This can be done by doing the following. The circuits in Figures 7(B) and 7(C) are described below.

[0168] Figures 7(B) and 7(C) show a switching element that controls the supply of power potential to the memory element. The child shows an example of a configuration using the transistors shown in Embodiment 1 or Embodiment 2.

[0169] The memory device shown in Figure 7(B) has a switching element 1141 and multiple memory elements 1142. It has a group of memory elements 1143. Specifically, each memory element 1142 has, The memory elements shown in Embodiment 1 or Embodiment 2 can be used. Memory element group 11 Each of the memory elements 1142 in 43 is connected via a switching element 1141. A power supply potential VDD at level 1 is supplied. Furthermore, the memory element group 1143 possesses Each memory element 1142 has a potential for the signal IN and a potential for the low-level power supply potential VSS. It is given.

[0170] In Figure 7(B), the switching element 1141 is a bandgap semiconductor such as an oxide semiconductor. The transistor uses a semiconductor with a large value in its active layer, and this transistor has a large value The switching is controlled by the signal SigA supplied to the terminal.

[0171] Note that in Figure 7(B), the switching element 1141 has a configuration in which it has only one transistor. This indicates, but is not limited to, and may have multiple transistors. When element 1141 has multiple transistors that function as switching elements The above-mentioned transistors may be connected in parallel or in series. Furthermore, a combination of series and parallel connections is also acceptable.

[0172] Furthermore, Figure 7(C) shows that each memory element 1142 of the memory element group 1143 has a S A low-level power supply potential VSS is supplied via the switching element 1141, memory An example of the device is shown. The switching element 1141 controls the memory element group 1143. The supply of a low-level power supply potential VSS to each memory element 1142 can be controlled. ru.

[0173] Between the memory element group and the node to which the power supply potential VDD or power supply potential VSS is provided, When a switching element is installed to temporarily stop the CPU's operation and cut off the power supply voltage, Even when data is stored, it is possible to reduce power consumption. For example, when a personal computer user inputs information into an input device such as a keyboard Even while stopped, the CPU operation can be halted, thereby reducing power consumption. It is possible.

[0174] Here, we used the CPU as an example, but DSP (Digital Signal Processor) Processor), custom LSI, FPGA (Field Programmable) It can also be applied to LSIs such as e Gate Arrays.

[0175] This embodiment can be implemented in appropriate combination with the above embodiment.

[0176] (Embodiment 4) In this embodiment, the semiconductor memory device and embodiment shown in Embodiment 1 or Embodiment 2 An example of an electronic device containing one or more types of CPUs as shown in State 3 will be described.

[0177] Figure 8(A) shows a portable information terminal. The portable information terminal shown in Figure 8(A) has a housing 9300 And, button 9301, microphone 9302, display unit 9303, speaker 930 It is equipped with 4 and a camera 9305, and functions as a portable telephone.

[0178] Figure 8(B) shows the display. The display shown in Figure 8(B) is connected to the housing 9310 and It comprises a display unit 9311 and

[0179] Figure 8(C) shows a digital still camera. The digital still camera shown in Figure 8(C) is , housing 9320, button 9321, microphone 9322, display unit 9323, It is equipped with.

[0180] Figure 8(D) shows a foldable portable information terminal. The information terminal consists of a housing 9630, a display unit 9631a, a display unit 9631b, a fastener 9633, and an operating unit. It has a switch 9638.

[0181] The display unit 9631a and / or the display unit 9631b is a touch panel in part or in whole. It is possible to input data and perform other actions by touching the displayed operation keys.

[0182] By using one aspect of the present invention, the performance of electronic devices can be improved.

[0183] This embodiment can be used in appropriate combination with other embodiments. [Explanation of Symbols]

[0184] 100 circuit boards 101 First Wiring 102 Interlayer insulating film 103 Oxide semiconductor film 104 Underlying insulating film 106 Oxide semiconductor film 106a Channel formation region 106b Source area and drain area 107 Resist Mask 108 gate insulating film 110 Guard Station 112 Interlayer insulating film 114 Second wiring 130 Capacitive electrode 140 Third Wiring 200 silicon substrates 201 Channel formation region 203 Element isolation insulating layer 206 Impurity region 208 Gate Insulation Layer 210 Guard Station 212 Interlayer insulating film 214 Drain electrode 216 Interlayer insulating film 300 Semiconductor memory devices 800 transistors 1141 Switching element 1142 memory element 1143 Memory element group 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 9300 cabinet 9301 button 9302 Microphone 9303 Display section 9304 Speaker 9305 Camera 9310 enclosure 9311 Display section 9320 enclosure 9321 button 9322 Microphone 9323 Display section 9630 cabinet 9631a Display section 9631b Display section 9633 Fastener 9638 Operation switch

Claims

1. A semiconductor device having a first transistor and a second transistor, A first semiconductor film having a channel formation region of the first transistor, A first conductive film having a region positioned above the first semiconductor film, functioning as the front gate of the first transistor, and functioning as the back gate of the second transistor, A second conductive film having a region positioned above the first semiconductor film, An insulating film having a region positioned above the first conductive film and a region positioned above the second conductive film, A second semiconductor film having a region positioned above the insulating film and having a channel formation region for the second transistor, A third conductive film having a region positioned above the second semiconductor film and functioning as the front gate of the second transistor, A fourth conductive film having a region positioned above the second semiconductor film, The second semiconductor film has an overlap with the second conductive film via the insulating film, The second conductive film forms a first capacitance with the first semiconductor film. The second conductive film has an overlap with the fourth conductive film, The first conductive film and the third conductive film are always electrically connected. The second conductive film and the fourth conductive film are always electrically connected. Semiconductor equipment.

2. A semiconductor device having a first transistor and a second transistor, A first semiconductor film having a channel formation region of the first transistor, A first conductive film having a region positioned above the first semiconductor film, functioning as the front gate of the first transistor, and functioning as the back gate of the second transistor, A second conductive film having a region positioned above the first semiconductor film, An insulating film having a region positioned above the first conductive film and a region positioned above the second conductive film, A second semiconductor film having a region positioned above the insulating film and having a channel formation region for the second transistor, A third conductive film having a region positioned above the second semiconductor film and functioning as the front gate of the second transistor, A fourth conductive film having a region positioned above the second semiconductor film, A fifth conductive film having a region located below the first semiconductor film, The second semiconductor film has an overlap with the second conductive film via the insulating film, The second conductive film forms a first capacitance with the first semiconductor film. The fifth conductive film forms a second capacitance with respect to the first semiconductor film. The second conductive film has an overlap with the fourth conductive film, The first conductive film and the third conductive film are always electrically connected. The second conductive film and the fourth conductive film are always electrically connected. Semiconductor equipment.

3. A semiconductor device having a first transistor and a second transistor, A first semiconductor film having a channel formation region of the first transistor, A first conductive film having a region positioned above the first semiconductor film, functioning as the front gate of the first transistor, and functioning as the back gate of the second transistor, A second conductive film having a region positioned above the first semiconductor film, An insulating film having a region positioned above the first conductive film and a region positioned above the second conductive film, A second semiconductor film having a region positioned above the insulating film and having a channel formation region for the second transistor, A third conductive film having a region positioned above the second semiconductor film and functioning as the front gate of the second transistor, A fourth conductive film having a region positioned above the second semiconductor film, The second semiconductor film has an overlap with the second conductive film via the insulating film, The second conductive film forms a first capacitance with the first semiconductor film. The second conductive film has an overlap with the fourth conductive film, The first conductive film and the third conductive film are always electrically connected. The second conductive film and the fourth conductive film are always electrically connected. The second semiconductor film includes an oxide semiconductor, Semiconductor equipment.

4. A semiconductor device having a first transistor and a second transistor, A first semiconductor film having a channel formation region of the first transistor, A first conductive film having a region positioned above the first semiconductor film, functioning as the front gate of the first transistor, and functioning as the back gate of the second transistor, A second conductive film having a region positioned above the first semiconductor film, An insulating film having a region positioned above the first conductive film and a region positioned above the second conductive film, A second semiconductor film having a region positioned above the insulating film and having a channel formation region for the second transistor, A third conductive film having a region positioned above the second semiconductor film and functioning as the front gate of the second transistor, A fourth conductive film having a region positioned above the second semiconductor film, A fifth conductive film having a region located below the first semiconductor film, The second semiconductor film has an overlap with the second conductive film via the insulating film, The second conductive film forms a first capacitance with the first semiconductor film. The fifth conductive film forms a second capacitance with respect to the first semiconductor film. The second conductive film has an overlap with the fourth conductive film, The first conductive film and the third conductive film are always electrically connected. The second conductive film and the fourth conductive film are always electrically connected. The second semiconductor film includes an oxide semiconductor, Semiconductor equipment.

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