Arithmetic processing unit and arithmetic processing method

Abstract

To suppress degrading of cache access efficiency in an arithmetic processing device having a hierarchically structured cache.SOLUTION: An arithmetic processing device includes: a first cache having a first tag area and a first data area; a second tag area; a control unit which controls the first cache on the basis of information held in the second tag area; and a second cache having a third tag area and a second data area. The second tag area includes a first area which holds first information indicating whether the second data area holds cache line data having an address being the same as an address of cache line data held in the first data area. The control unit determines whether a write back destination of the cache line data held in the first cache should be the second cache or an external memory, according to the first information held in the second tag area in correspondence to cache line data being the object of write back.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an arithmetic processing unit and an arithmetic processing method.

Background Art

[0002] A system equipped with an arithmetic processing unit such as a CPU (Central Processing Unit) has multiple levels of cache for performance improvement. Recently, in order to increase the cache capacity and improve the access efficiency, a system that connects a DRAM (Dynamic Random Access Memory) cache to a die including an internal cache is known (see, for example, Patent Documents 1-3). At this time, in order to suppress the access frequency of the tag directory of the DRAM cache, a tag directory cache obtained by copying the tag directory of the DRAM cache may be mounted on the die.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, when a read request issued from a CPU core or the like results in a cache miss in the internal cache and the DRAM cache, the data read from the main memory is stored in both the internal cache and the DRAM cache. Then, the data held in the internal cache becomes in an inclusion state where it is also held in the DRAM cache.

[0005] In an inclusion-based cache system, when data is written back from the DRAM cache to main memory during a DRAM cache replacement process, data in the internal cache is also evicted. Therefore, inclusion-based systems may experience a decrease in cache access performance. For example, when a direct-mapped DRAM cache is used, the replacement process occurs more frequently than in a set-associative cache, making access performance more susceptible to degradation.

[0006] To mitigate the degradation of access performance, it is conceivable to allow data to remain in the internal cache during DRAM cache replacement (inclusion state detachment). However, in this case, data corresponding to data held in the internal cache may or may not be held in the DRAM cache.

[0007] Therefore, when writing data back from the internal cache, the destination of the write-back is determined by accessing the DRAM cache tag and checking the tag's status, which determines whether the data is written back to the DRAM cache or main memory. If the DRAM cache tag is accessed every time data is written back from the internal cache, the cache access performance will deteriorate. Furthermore, simply storing tag information such as MESI protocol information as a directory cache on the die makes it difficult to determine the destination of the data written back from the internal cache.

[0008] In one aspect, the present invention aims to suppress a decrease in cache access efficiency in a processing unit having a hierarchical cache structure. [Means for solving the problem]

[0009] From one perspective, the arithmetic processing unit includes an arithmetic unit that executes instructions, a first cache connected to the arithmetic unit and having a plurality of first entries, each including a first tag area and a first data area that holds cache line data, a second tag area, a control unit that controls the first cache based on information held in the second tag area, and a second cache connected to the first cache via the control unit and having a plurality of second entries, each including a third tag area and a second data area that holds cache line data, wherein the second tag area has a first area that holds first information indicating whether cache line data with the same address as the cache line data held in the first data area is held in the second data area, and the control unit determines whether to write back the cache line data held in the first cache to the second cache or to external memory, according to the first information held in the second tag area corresponding to the cache line data to be written back. [Effects of the Invention]

[0010] In a processing unit with a hierarchical cache structure, the decrease in cache access efficiency can be suppressed. [Brief explanation of the drawing]

[0011] [Figure 1] Block diagram showing an example of a processing unit in one embodiment. [Figure 2] Figure 1 is a block diagram showing an example of an LLC. [Figure 3] An example of a home agent's block screen in Figure 1. [Figure 4] Figure 1 is an explanatory diagram showing an example of physical address allocation used in LLC-TAG, TAGD, and TAG. [Figure 5] Figure 2 shows an example of the components of LLC-TAG, Figure 3 shows TAGD, and Figure 3 shows an example of the components of each entry in the external cache. [Figure 6]It is a timing diagram showing an example of the operation of the arithmetic processing unit in FIG. 1. [Figure 7] It is a timing diagram showing another example of the operation of the arithmetic processing unit in FIG. 1. [Figure 8] It is a timing diagram showing yet another example of the operation of the arithmetic processing unit in FIG. 1. [Figure 9] It is a flowchart showing an example of the operation of the arithmetic processing unit in FIG. 1. [Figure 10] It is a flowchart showing an example of the processing of step S200 in FIG. 9. [Figure 11] It is a flowchart showing another example of the operation of the arithmetic processing unit in FIG. 1. [Figure 12] It is a block diagram showing an example of an arithmetic processing unit in another embodiment. [Figure 13] It is an explanatory diagram showing an example of the components of the LLC-TAG in FIG. 12. [Figure 14] It is a timing diagram showing an example of the operation of the arithmetic processing unit in FIG. 12. [Figure 15] It is a timing diagram showing another example of the operation of the arithmetic processing unit in FIG. 12. [Figure 16] It is a timing diagram showing yet another example of the operation of the arithmetic processing unit in FIG. 12.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments will be described with reference to the drawings.

[0013] FIG. 1 shows an example of an arithmetic processing unit in one embodiment. The arithmetic processing unit 100 shown in FIG. 1 has a die (semiconductor chip) 110 and an external cache 200, and has, for example, a package form. A main storage device 500 is connected to the arithmetic processing unit 100. Then, the arithmetic processing unit 100 and the main storage device 500 operate as an information processing device 600.

[0014] The die 110 has multiple LLC (Last Level Cache) blocks 120, a communication unit 130, a home agent 140, and memory control units 150 and 160. Each LLC block 120 has multiple cores 10, an L1 cache 20 corresponding to each core 10, an LLC 30, and a communication unit interface unit 40.

[0015] LLC block 120 is an example of a cache block. Core 10 is an example of an arithmetic unit, and LLC 30 is an example of a first cache. Home agent 140 is an example of a control unit. External cache 200 is an example of a second cache, and main memory 500 is an example of external memory.

[0016] In the example shown in Figure 1, the die 110 has four LLC blocks 120, but the number of LLC blocks 120 mounted on the die 110 is not limited to four. Also, for example, each LLC block 120 has eight cores 10, but the number of cores 10 mounted on each LLC block 120 is not limited to eight. In the following, memory access requests (read requests or write requests), replace requests, or snoop requests may be simply referred to as requests. Furthermore, the operation when a read request is issued from a core 10 will be described below.

[0017] Each L1 cache 20, if it holds the target data for the read request (load instruction) generated by the corresponding core 10, responds to the core 10 with the target data. If each L1 cache 20 does not hold the target data for the read request generated by the corresponding core 10, it sends the read request to the LLC 30. Each L1 cache 20 responds to the core 10 with the target data transferred from the LLC 30. Note that the L1 cache 20 may be included in the core 10.

[0018] For example, LLC30 employs a set-associative architecture with multiple ways. LLC30 has multiple entries, each capable of holding multiple data (cache line data). Each of these entries is assigned an index address. Therefore, these multiple entries can hold multiple data with the same index address.

[0019] If LLC30 holds the target data for the read request from L1 cache 20, it responds to L1 cache 20 with the target data. If LLC30 does not hold the target data for the read request from L1 cache 20, it sends the read request to home agent 140 via communication interface unit 40 and communication unit 130. LLC30 responds to L1 cache 20 with the target data transferred from home agent 140. An example configuration of LLC30 is shown in Figure 2.

[0020] The communication interface unit 40 controls communication between the LLC 30 and the communication unit 130. The communication unit 130 controls communication between each LLC block 120 and the home agent 140. The home agent 140 sends a read request from the LLC block 120 to either the memory control unit 150 or 160 and receives a response from either the memory control unit 150 or 160. The home agent 140 also performs coherent control between the LLC 30 of the multiple LLC blocks 120 and the external cache 200.

[0021] For example, when the home agent 140 receives a read request from the LLC block 120 via the communication unit 130, it determines whether the target data is held in the external cache 200. If the target data is held in the external cache 200, the home agent 140 sends a read request to the external cache 200 via the memory control unit 150. The home agent 140 receives the target data to be read from the external cache 200 in response to the read request via the memory control unit 150 and sends the received target data to the LLC block 120 that issued the read request.

[0022] If the target data is not held in the external cache 200, the home agent 140 sends a read request to the main memory 500 via the memory control unit 160. The home agent 140 receives the target data to be read from the main memory 500 in response to the read request via the memory control unit 160 and sends the received target data to the LLC block 120 that issued the read request. The home agent 140 also stores the received target data in the external cache 200 via the memory control unit 150. An example configuration of the home agent 140 is shown in Figure 3.

[0023] In this embodiment, multiple LLCs 30 are connected to an external cache 200 and main memory 500 via a home agent 140. Therefore, the home agent 140 can control data transfer between the multiple LLCs 30 and the external cache 200, and also control data transfer between the multiple LLCs 30 and the main memory 500. Since each of the multiple LLCs 30 does not need to control data transfer between the external cache 200 and the main memory 500, data transfer control by cache operation can be simplified, and a decrease in cache access efficiency can be suppressed.

[0024] The external cache 200 has a TAG201 (tag) that holds tag information and a data area DT202 that holds data. TAG201 is an example of a third tag area, and the data area DT202 is an example of a second data area. For example, the external cache 200 employs a direct map scheme with one way. The external cache 200 has multiple entries, each capable of holding one piece of data (cache line data). Index addresses are assigned to the multiple entries.

[0025] Therefore, if a cache miss occurs in an entry of the external cache 200, the data held in that entry is evicted each time. The external cache 200 is a high-bandwidth memory for main memory, such as HBM (High Bandwidth Memory), HMC (Hybrid Memory Cube), or MCDRAM (Multi-Channel Dynamic Random Access Memory). The external cache 200 may be in the form of a chip or a package.

[0026] The home agent 140 determines whether the external cache 200 is experiencing a cache hit or a cache miss by accessing the TAG201 of the external cache 200. Since the external cache 200 is connected to the outside of the die 110, it has a higher number of access cycles compared to the LLC30 mounted inside the die 110. Therefore, it is preferable to have a low frequency of access to TAG201.

[0027] By placing an external cache 200 between LLC30 and main memory 500, throughput can be improved compared to accessing main memory 500 when LLC30 experiences a cache miss by accessing the external cache 200. Note that the L1 cache 20, LLC30, and external cache 200 may each hold the instruction code executed by each core 10 as data. Main memory 500 may, for example, have multiple DIMMs (Dual Inline Memory Modules).

[0028] For example, the storage capacity of the external cache 200 is greater than the storage capacity of the LLC 30, but less than the storage capacity of the main memory 500. Also, for example, the memory bandwidth of the external cache 200 is lower than the memory bandwidth of the LLC 30, but higher than the memory bandwidth of the main memory 500.

[0029] In this embodiment, the external cache 200 does not apply inclusion rules that guarantee that data held in LLC 30 is always held in the external cache 200. For example, in the replacement process of identical entries in the external cache 200 that occurs when new data is registered in LLC 30 from main memory 500 and the same data is registered in the external cache 200, data that is evicted from the external cache 200 to main memory 500 may also be held in LLC 30.

[0030] If the inclusion rule is not applied, data held in LLC30 corresponding to data written back to main memory 500 will remain in LLC30 without being evicted, thus ceasing to be inclusion. The data in LLC30 that was not evicted will then be written back to main memory 500 instead of external cache 200 by subsequent write-back operations.

[0031] Therefore, as will be described later, the home agent 140 performs a process to determine the write-back destination from LLC30 to either the external cache 200 or the main memory 500. In this case, the home agent 140 can determine the write-back destination without accessing the external cache 200. Since access to the external cache 200 to determine the write-back destination can be omitted, a decrease in memory access efficiency can be suppressed.

[0032] In this embodiment, when data is evicted from the external cache 200, it is not necessary to evict the corresponding data from the LLC 30, thus simplifying the control of the evicting process. As a result, the period during which the LLC 30 and the external cache 200 are inaccessible due to the evicting process can be shortened, and a decrease in access efficiency can be suppressed. For example, in a direct-mapped external cache 200, the frequency of data evicting from the external cache 200 is higher compared to a set-associative method, but a decrease in access efficiency can be suppressed.

[0033] Figure 2 shows an example of the LLC30 in Figure 1. The LLC30 includes a data buffer 301, a data memory 302, an LLC-TAG 303 (tag), an evacuation information holding unit 304, multiple ports 305, a pipe insertion unit 306, a pipeline control unit 307, a snoop lock unit 308, and a cache miss control unit 309. The data memory 302 is an example of a first data area, and the LLC-TAG 303 is an example of a first tag area.

[0034] The data buffer 301 has multiple entries that hold store data transferred from the core 10 or data transferred from the communication interface unit 40. The data buffer 301 reads the data held in the entry indicated by the read instruction RINS1 from the pipeline control unit 307 and outputs the read data to the data memory 302.

[0035] The data memory 302 has multiple entries, each capable of holding multiple cache line data. Each of the multiple entries is assigned an index address, which is indicated by a predetermined number of bits from the address included in the memory access request. Based on the control of the pipeline control unit 307, the data memory 302 stores the cache line data received from the data buffer 301 into one of the multiple data areas (ways) of the entry indicated by the index address.

[0036] For example, if a read request issued by a core 10 in the LLC block 120 to which LLC 30 belongs results in a cache hit in LLC 30, the data read from data memory 302 is transferred as a data response to the core 10 that issued the read request. If the data corresponding to a read request issued by a core 10 in another LLC block 120 is not held in the other LLC block 120 but is held in LLC 30 in the same LLC block 120, a cache miss occurs in the other LLC block 120 to which the core 10 that issued the read request belongs. In this case, the other LLC block 120 issues a read request to the home agent 140. The home agent 140 determines which LLC 30 holds the data by referring to TAGD 402 and then instructs the transfer of the data to be read between LLCs 30. The data to be transferred, read from data memory 302, is transferred to the other LLC block 120 via the communication interface unit 40. Furthermore, data read from the data memory 302 during write-back processing is transferred to the external cache 200 or main memory 500 via the communication interface unit 40.

[0037] The LLC-TAG303 has a tag area for each way, corresponding to multiple entries in the data memory 302. The tag area of ​​the LLC-TAG303 includes an area that holds a copy of the tag information (L1 tag information) from the L1 cache 20. The LLC-TAG303 outputs a control signal that controls writing data to the data memory 302 or reading data from the data memory 302, depending on the result of the tag information lookup by the pipeline control unit 307 (cache hit / cache miss, etc.).

[0038] In response to a read instruction RINS2 from the pipeline control unit 307, the LLC-TAG303 outputs the tag information held in the specified area to the pipeline control unit 307. In response to an update instruction UPD1 from the pipeline control unit 307, the LLC-TAG303 updates the tag information. An example of the LLC-TAG303 is shown in Figure 5.

[0039] The evacuation information storage unit 304 stores information for each entry about the way that holds data to be evacuated from the data memory 302, for example, using the LRU (Least Recently Used) algorithm. The evacuation information stored in the evacuation information storage unit 304 is managed by the pipeline control unit 307.

[0040] The multiple ports 305 include multiple ports that each receive memory access requests from multiple cores 10, and a port that receives write-back requests or snoop requests from the home agent 140. Requests received by each port 305 are output to the pipe input unit 306. The pipe input unit 306 sequentially inputs the inputable requests from the multiple requests received from the multiple ports 305 to the pipeline control unit 307.

[0041] The pipeline control unit 307 performs cache hit / cache miss determination, LLC-TAG 303 management, and evicting information holding unit 304 management based on requests sequentially fed from the pipe input unit 306. The pipeline control unit 307 controls the reading of data from the data memory 302 when there is a cache hit. The pipeline control unit 307 controls the evicting of data from the data memory 302 and controls the storage of response data to the data memory 302 when there is a cache miss.

[0042] The snoop lock unit 308 holds the address to be snooped from the time the pipeline control unit 307 issues a snoop request until a snoop response is received. When the snoop lock unit 308 holds the address received from the pipeline control unit 307, it notifies the pipeline control unit 307 that it is in snoop lock mode by outputting address match information AMCH1. When the pipeline control unit 307 is notified that it is in snoop lock mode, it prevents, for example, issuing duplicate snoop requests for the same address.

[0043] The cache miss control unit 309 holds the address of the cache miss when the pipeline control unit 307 determines that a cache miss has occurred. If the cache miss control unit 309 holds the address received from the pipeline control unit 307, it outputs address match information AMCH2 to the pipeline control unit 307.

[0044] Upon receiving the address match information AMCH2, the pipeline control unit 307 sets the lock flag LCK (Figure 5) until the response data corresponding to the cache miss address is transferred to LLC 30, thereby preventing duplicate detection of cache misses at the same address.

[0045] The cache miss control unit 309 outputs a replacement request MORP corresponding to the cache miss to the pipe inlet unit 306. Furthermore, if the cache miss control unit 309 receives response data corresponding to the cache miss, it outputs a move-in request MVIN to the pipe inlet unit 306. The pipeline control unit 407, upon receiving the replacement request MORP or move-in request MVIN from the pipe inlet unit 306, performs processing for the replacement request MORP or move-in request MVIN.

[0046] Figure 3 shows an example of the home agent 140 in Figure 1. In Figure 3, the communication interface unit 40 and communication unit 130, which are located between each LLC 30 and the home agent 140, are omitted. The home agent 140 has a data buffer 401, a TAGD 402 (tag), a store lock unit 403, a memory response receiving unit 404, multiple ports 405, a pipe insertion unit 406, a pipeline control unit 407, a snoop lock unit 408, and a selector 409. The TAGD 402 is an example of a second tag area.

[0047] The data buffer 401 has multiple entries that hold the data to be evicted from each LLC 30. The data buffer 401 outputs the data held in the entries indicated by the read instruction RINS3 from the pipeline control unit 407 to the selector 409 and the memory control units 150 and 160.

[0048] TAGD402 has a region that holds tag information for each region of cache line data allocated to the data memory 302 of the four LLCs 30. That is, TAGD402 holds tag information for multiple ways for each entry of each LLC 30. In response to a read instruction RINS4 from the pipeline control unit 407, TAGD402 outputs the tag information held in the indicated region to the pipeline control unit 407. In response to an update instruction UPD2 from the pipeline control unit 407, TAGD402 updates the tag information. An example of TAGD402 is shown in Figure 5.

[0049] The store lock unit 403 holds the target address for storage from the time it issues a write-back request (store request) to the external cache 200 or main memory 500 until the write-back is completed. If the store lock unit 403 holds the address received from the pipeline control unit 407 as the target address, it notifies the pipeline control unit 407 that it is in a store lock state by outputting address match information AMCH3. The pipeline control unit 407, notified that it is in a store lock state, for example, will suppress the issuance of duplicate requests for the same address.

[0050] The memory response receiving unit 404 receives response data for requests issued by the pipeline control unit 407 to the external cache 200 or main memory 500. The memory response receiving unit 404 outputs the received response data to the pipe input unit 406 and causes the pipeline control unit 407 to register tag information corresponding to the response data.

[0051] The multiple ports 405 each include multiple ports that receive requests from multiple LLCs 30. Requests received by each port 305 are output to the pipe input unit 406. The pipe input unit 406 sequentially inputs the input requests from the multiple requests received from the multiple ports 405 to the pipeline control unit 407.

[0052] The pipeline control unit 407 determines cache hits / cache misses for LLCs 30 other than the LLC 30 that issued the request, based on requests sequentially fed from the pipe input unit 406. In doing so, the pipeline control unit 407 uses the information stored in the TAGD 402 to determine cache hits / cache misses. The pipeline control unit 407 then uses the information stored in the TAGD 402 to manage the data stored in the data memory 302 of each LLC 30. The pipeline control unit 407 also controls the output of the response data received by the memory response receiving unit 404 to the pipe input unit 406 and updates the TAGD 402.

[0053] The snoop lock unit 408 holds the snoop target address from the time the pipeline control unit 407 issues a snoop request to check whether the data for the target address included in the request from LLC 30 is held by another LLC 30 until a snoop response is received. If the snoop lock unit 408 holds the address received from the pipeline control unit 407 as the target address, it outputs address match information AMCH4 to the pipeline control unit 407 to notify it that it is in snoop lock mode. When the pipeline control unit 407 is notified that it is in snoop lock mode, it will, for example, refrain from issuing duplicate snoop requests for the same address.

[0054] The selector 409 selects data output from the data buffer 401, a snoop request output from the pipeline control unit 407, response data output from the external cache 200, or response data output from the main memory 500, and outputs it to the LLC 30.

[0055] Figure 4 shows an example of the allocation of physical address PA[47:0] used by LLC-TAG303, TAGD402, and TAG201 in Figure 1. The information processing device 600 in Figure 1 can access a maximum memory space of 256 TB (terabytes) using 48-bit physical addresses. Therefore, the maximum capacity of the main memory 500 is 256 TB.

[0056] The 28-bit physical address PA[47:20] of each LLC30's LLC-TAG303 and the home agent 140's TAGD402 is used as the tag address LL-TAG-AD. The 13-bit physical address PA[19:7] of LLC-TAG303 and TAGD402 is used as the index address LL-INDX. Thus, each LLC-TAG303 has 8192 entries. TAGD402 has 32768 entries corresponding to the four LLC30s. The 7-bit physical address PA[6:0] of LLC-TAG303 and TAGD402 is used as the 128-byte cache line size CLSIZE.

[0057] In each LLC30, a cache hit is determined if the physical address PA[47:7] included in the memory access request matches the tag address LL-TAG-AD and index address LL-INDX pair included in the entry. In each LLC30, a cache miss is determined if the physical address PA[47:7] included in the memory access request does not match the tag address LL-TAG-AD and index address LL-INDX pair of all entries in that LLC30.

[0058] The 15-bit physical address PA[47:33] of TAG201 in external cache 200 is used as the tag address EC-TAG-AD. The 26-bit physical address PA[32:7] of TAG201 is used as the index address EC-INDX. Therefore, TAG201 has 67,108,854 entries. The physical address PA[6:0] of TAG201 is used as the cache line size CLSIZE, which is 128 bytes.

[0059] In the external cache 200, a cache hit is determined if the physical address PA[47:7] included in the memory access request matches the tag address EC-TAG-AD and index address EC-INDX pair included in the entry. In the external cache 200, a cache miss is determined if the physical address PA[47:7] included in the memory access request does not match the tag address EC-TAG-AD and index address EC-INDX pair of any entry in the external cache 200.

[0060] Figure 5 shows an example of the components of each entry in the LLC-TAG303 in Figure 2, the TAGD402 in Figure 3, and the external cache 200. The LLC-TAG303 of each LLC30 shows the information held per way in each of the 8192 entries that each LLC30 has. The TAGD402 of the home agent 140 shows the information held per way in each of the 32768 entries that the four LLC30s have. Although not particularly limited, for example, each LLC30 has 16 ways.

[0061] LLC-TAG303 has an area where a 28-bit tag address LL-TAG-AD and a 2-bit cache status LL-ST are stored. LLC-TAG303 also has an area where a 2-bit core status C-ST, an 8-bit core presence C-PRS, and a 1-bit lock flag LCK are stored. The core status C-ST and core presence C-PRS are copied from the tag information of L1 cache 20.

[0062] The area of ​​tag address LL-TAG-AD stores the physical address PA[47:20]. The cache status LL-ST and core status C-ST indicate the following states: "00" for invalid state I, "01" for shared state S, "10" for modified state M, and "11" for exclusive state E. In other words, the arithmetic processing unit 100 employs the MESI protocol.

[0063] The Core Presence C-PRS bit corresponds to each of the eight cores 10 and indicates whether the data held in the data memory 302 of the LLC 30 entry is also held in the L1 cache 20.

[0064] The lock flag LCK is set to exclude requests from other L1 caches 20 while processing requests from L1 cache 20 (i.e., core 10). For example, the lock flag LCK is set when a cache miss occurs in LLC 30 and reset when data transferred from external cache 200 or main memory 500 is stored in LLC 30's data memory 302. While the lock flag LCK is set, requests from other L1 caches 20 are aborted.

[0065] The TAGD402 of the home agent 140 indicates the information held for each way in each of the 8192 entries that each of the four LLC30s connected to the home agent 140 has. In other words, the TAGD402 has 62768 entries corresponding to the four LLC30s.

[0066] TAGD402 has an area for storing a 28-bit tag address LL-TAG-AD, a 2-bit cache status LL-ST, a 4-bit core presence LLC-PRS, and a 1-bit lock flag LCK. TAGD402 also has an area for storing a 1-bit inclusion valid flag EC-VAL and a 1-bit write-back completion flag WRBK-CPLT. The inclusion valid flag EC-VAL is an example of the first type of information, and the write-back completion flag WRBK-CPLT is an example of the second type of information.

[0067] The tag address LL-TAG-AD and cache status LL-ST hold the same information as the tag address LL-TAG-AD and cache status LL-ST of LLC-TAG303. The core presence C-PRS has bits corresponding to each of the four LLC30s, indicating whether the data held in the data memory 302 of that entry in LLC30 is also held in the other LLC30s.

[0068] The lock flag LCK is set to exclude requests from other LLCs 30 while processing a request from LLC 30. For example, the lock flag LCK is set when a memory access request from LLC 30 is submitted to the pipeline control unit 407 and reset when the home agent 140 receives response data transferred from the external cache 200 or main memory 500. While the lock flag LCK is set, requests from other LLCs 30 are aborted.

[0069] The inclusion valid flag EC-VAL is set, for example, when data read from main memory 500 during a cache miss in the external cache 200 is stored in LLC 30 and the external cache 200, resulting in an inclusion state. The inclusion valid flag EC-VAL is reset when the target data is evicted from the external cache 200 while the target data is still held in LLC 30, resulting in a non-inclusion state. For example, the set state of the inclusion valid flag EC-VAL is "1", and the reset state of the inclusion valid flag EC-VAL is "0".

[0070] The write-back completion flag WRBK-CPLT is set when the target data has been written back from LLC30 to main memory 500 and the target data remains in the external cache 200. When the write-back completion flag WRBK-CPLT is set, it is used to prevent the dirty target data held in the external cache 200 from being written back to main memory 500.

[0071] In other words, the pipeline control unit 407 of the home agent 140 considers that the write-back of the target data from the external cache 200 to the main memory 500 is complete when the write-back completion flag WRBK-CPLT is set. This prevents the data written back from the LLC 30 to the main memory 500 from being overwritten by older data from the external cache 200, thereby preventing malfunction of the arithmetic processing unit 100.

[0072] Furthermore, by storing some of the same information in TAGD402 as in LLC-TAG303, the pipeline control unit 407 of the home agent 140 can use the information stored in TAGD402 to perform cache control for each LLC30.

[0073] The home agent 140 can understand the status of the data held in each LLC30 by storing the information held in the LLC-TAG303 of each LLC30 in the TAGD402. This reduces the frequency of access from the home agent 140 to each LLC30, thereby suppressing the decrease in cache access efficiency.

[0074] TAG201 of the external cache 200, which employs a direct-map method, indicates the information held in one way for every 67,108,854 entries in the external cache 200. The data area DT202 of the external cache 200 holds the cache line data corresponding to one way for every 67,108,854 entries.

[0075] The external cache 200's tag TAG has an area where a 15-bit tag address C-TAG-AD, a 1-bit valid flag VAL, and a 1-bit dirty flag DRTY are stored. The valid flag VAL is set when valid information is held in the tag TAG and data area DT.

[0076] The dirty flag DRTY is set when data is written back from any of the LLC30. In other words, the dirty flag DRTY is set when the data held at a predetermined address in main memory 500 differs from the data held in data area DT corresponding to that predetermined address. When the dirty flag DRTY is set, it indicates that during the replacement process of the external cache 200, the data to be evicted from the external cache 200 needs to be written back to main memory 500.

[0077] The data area DT of the external cache 200 has an area that holds 128-byte cache lines. However, the size of a single cache line is not limited to 128 bytes.

[0078] When the pipeline control unit 407 of the home agent 140 references TAGD402 using the address included in the request, it performs the address match check shown in equations (1), (2), and (3).

[0079] TAGD-HIT=("LL-ST"!="00")&(RQ-PA[47:20]=="LL-TAG-AD") ‥(1) EC-INDX-MCH=("LL-ST"!="00")&(RQ-PA[32:20]==LL-TAG-AD(PA[32:20])) ‥(2) EC-VICTIM-HIT=("LL-ST"!="00")&(RQ-PA[32:20]==LL-TAG-AD([32:20]))&(RQ-PA[47:33]!=LL-TAG-AD(PA[47:33])) ‥(3)

[0080] In equations (1) through (3), the symbol "!=" indicates inequality, and the symbol "==" indicates equality. The symbol "&" indicates a logical AND. In equations (2) and (3), LL-TAG-AD(PA[32:20]) represents the lower 13 bits of the tag address LL-TAG-AD corresponding to the physical address PA[32:20]. In equation (3), LL-TAG-AD(PA[47:33]) represents the upper 15 bits of the tag address LL-TAG-AD corresponding to the physical address PA[47:33].

[0081] The flag TAGD-HIT in equation (1) is set to "1" if the cache status LL-ST of the entry in TAGD402 that holds the same tag address LL-TAG-AD as the physical address PA[47:20] included in the request is not invalid. When the flag TAGD-HIT is set, it indicates that the data targeted by the request is held in one of the four LLC30s (cache hit state).

[0082] The flag EC-INDX-MCH in equation (2) is set to "1" when the physical address PA[32:7] included in the request matches the index address EC-INDX of a non-invalidated entry. In other words, a set flag EC-INDX-MCH indicates that the entry for TAGD402 (i.e., one of LLC30) holds the address included in the request.

[0083] Here, the lower bits [19:7] of index address EC-INDX are equal to those of index address LL-INDX. Therefore, home agent 140 can determine the match of index address EC-INDX by comparing the upper bits [32:20] held in TAGD402 without referring to TAG201 in external cache 200. Furthermore, the number of bits used to determine the match of index address EC-INDX can be reduced from 26 bits to 13 bits.

[0084] The flag EC-VICTIM-HIT in equation (3) is set when, in an entry that is not in an invalid state in TAGD201, the physical address PA included in the request matches the tag address LL-TAG-AD ([32:20]) but does not match the tag address LL-TAG-AD ([47:33]). In other words, it is set when, during the search of TAGD402 for the address to be accessed, an entry is detected in which the bit value corresponding to the index address of TAG201 matches, but the bit value corresponding to the tag address of TAG201 does not match. The pipeline control unit 407 then resets the flag EC-VAL of the entry corresponding to the set flag EC-VICTIM-HIT to "0".

[0085] The flag EC-VICTIM-HIT in the set state indicates that the target entry in the external cache 200 holds an address for data different from the target data of the request. In other words, the flag EC-VICTIM-HIT in the set state indicates that data with the same address as data that can be evicted from the external cache 200 by replacement is held in one of the entries in LLC30.

[0086] For example, suppose the data for the entry corresponding to the set state flag EC-VICTIM-HIT is evicted from the external cache 200. In this case, the home agent 140 can determine within the LLC 30 that the data held in the LLC 30 corresponding to the data evicted from the external cache 200 will be in a non-inclusion state.

[0087] Figure 6 shows an example of the operation of the arithmetic processing unit 100 in Figure 1. The operation shown in Figure 6 is realized by the arithmetic processing unit 100 executing the arithmetic processing method. Figure 6 shows the operation flow when a read request RD that has a cache miss in one of the LLCs 30 also has a cache miss in the home agent 140 (another LLC 30) and a cache hit in the external cache 200.

[0088] First, one of the cores 10 in LLC block 120 issues a load request (Figure 6(a)). The load request is held in the move import MIP of LLC 30 (self LLC) in LLC block 120 to which the core 10 that issued the load request belongs. The move import MIP is one of the ports 305 of LLC 30. The move import MIP sends a read request RD1 to the pipeline control unit 307 via the pipe inlet unit 306 (Figure 6(b)). The pipeline control unit 307 determines whether there is a cache miss for the read request RD1 and issues a read request RD1 to the home agent 140 (Figure 6(c)).

[0089] The move-import MIP of home agent 140 holds a read request RD from LLC 30 (Figure 6(d)). The move-import MIP is one of the ports 405. The move-import MIP sends a read request RD3 to the pipeline control unit 407 via the pipe inlet 406 (Figure 6(e)). The pipeline control unit 407 searches TAGD 402 and determines a cache miss because none of the four LLC 30s hold the target data for read request RD3. For example, a cache miss is determined by the flag TAGD-HIT="0" in equation (1).

[0090] Furthermore, in the subsequent operation, the external cache 200 will hit the cache, so the flag EC-VICTIM-HIT in equation (3) will be determined to be "0". On the other hand, although not shown in Figure 6, let's assume that the external cache 200 will then miss the cache, and a process will occur in which the data held in LLC30 in the modified state is written back from the external cache 200 to main memory 500.

[0091] In this case, the pipeline control unit 407 determines that the flag EC-VICTIM-HIT is "1" and sets the inclusion valid flag EC-VAL for the corresponding entry in TAGD402 to "0". That is, if cache line data with the same address as the cache line data held in LLC30 is written back from the external cache 200 to the main memory 500 by the replacement process, the pipeline control unit 407 sets the inclusion valid flag EC-VAL corresponding to the address of the cache line data being written back to "0".

[0092] Here, cache line data is the unit of data transfer between LLC30, external cache 200, and main memory 500. Cache line data is held in each way of entries in the data memory 302 of LLC30 and in entries in the data area DT202 of the external cache 200.

[0093] The pipeline control unit 407 issues a read request RD4 to the external cache 200 based on the determination of a cache miss (Figure 6(f)). The pipeline control unit 407 performs update processing of TAGD402, such as setting the lock flag LCK to "1" (Figure 6(g)). By setting the lock flag LCK, processing of other read requests, etc., for the target entry of read request RD4 is suppressed until the processing of receiving response data from the main memory 500 is completed.

[0094] The pipeline control unit 407 outputs a read request processing confirmation notification MIPTKN to the move-in buffer MIB of LLC 30, the issuer of the read request RD2 (Figure 6(h)). For example, the move-in buffer MIB is located within the cache miss control unit 309.

[0095] The external cache 200 determines whether the read request RD4 is a cache hit. The external cache 200 outputs a response RTN1(HIT) along with cache hit information to the move-in buffer MIB of LLC 30, the issuer of the read request RD2 (Figure 6(i)). The pipeline control unit 307 stores the response data received by the move-in buffer MIB in the data memory 302 (MVIN) and updates LLC-TAG 303 (Figure 6(j)). Then, the pipeline control unit 307 responds with the response data to the core 10, the issuer of the load request (Figure 6(k)).

[0096] Furthermore, the external cache 200 outputs a response RTN2(HIT) containing the target data and cache hit information (HIT) to the port MSP of the home agent 140 (Figure 6(l)). The port MSP is located within the memory response receiving unit 404 of the home agent 140.

[0097] The pipeline control unit 407, having received the response RTN2(HIT), sets the inclusion valid flag EC-VAL of the corresponding entry to "1" in response processing because the target data is now held in both the external cache 200 and LLC30 (Figure 6(m)). In response processing, the flag EC-INDX-MCH is "0" and the flag EC-VICTIM-HIT is "0". The pipeline control unit 407 then releases the lock by resetting the lock flag LCK (Figure 6(n)).

[0098] Meanwhile, the cache miss control unit 309 of LLC30 (its own LLC) issues a replace request MORP to the pipeline control unit 307 using the move-in buffer MIB, based on the cache miss determination by the pipeline control unit 307 (Figure 6(o)). For example, the data evicted from LLC30 by the replace request MORP has been updated within LLC30 (LL-ST=M). Therefore, the write-back process of the data evicted from LLC30 to either the external cache 200 or the main memory 500 is performed as follows.

[0099] The pipeline control unit 307 of LLC30 issues a writeback request WRBK1 to the home agent 140 (Figure 6(p)). The home agent 140 receives the writeback request WRBK1 on port CPP. Port CPP is one of several ports 405. Port CPP sends a read request to the pipeline control unit 407 via the pipe inlet unit 406.

[0100] Upon receiving a read request, the pipeline control unit 407 refers to the inclusion valid flag EC-VAL of the target entry in TAGD402. In the example shown in Figure 6, the inclusion valid flag EC-VAL of the data to be evicted from LLC30 is set to "1". Therefore, the pipeline control unit 407 decides to write back the modified data to be evicted from LLC30 to the external cache 200. In this way, the home agent 140 can determine the write-back destination of the data without reading tag information from TAG201 in the external cache 200 by referring to the inclusion valid flag EC-VAL.

[0101] The pipeline control unit 407 outputs a write-back request WRBK2 to the external cache 200 (Figure 6(q)). At this time, the flag EC-INDX-MCH is "1" and the flag EC-VICTIM-HIT is "0".

[0102] The pipeline control unit 407 locks the store by registering the index address of the target entry in TAGD 402 with the store lock unit 403 (Figure 6(r)). For example, the pipeline control unit 407 locks the store based on the flag EC-INDX-MCH="1".

[0103] Upon receiving the writeback request WRBK2, the external cache 200 stores the data to be written back in the data area DT202 and updates TAG201 (Figure 6(s)). The external cache 200 then outputs a writeback completion response REL1 to the home agent 140 (Figure 6(t)). The pipeline control unit 407, having received the writeback completion response REL1 via the pipe inlet unit 406, releases the store lock (Figure 6(u)).

[0104] Furthermore, if the inclusion valid flag EC-VAL of the target entry for writeback request WRBK1 in TAGD402 is reset to "0", the target address for writeback request WRBK is not registered in the external cache 200. In this case, the pipeline control unit 407 can write back the target data to the main memory 500 without reading the tag information from TAG201 in the external cache 200.

[0105] Figure 7 shows another example of the operation of the arithmetic processing unit 100 in Figure 1. Detailed explanations of operations that are the same as or similar to those in Figure 6 are omitted. The operation shown in Figure 7 is realized by the arithmetic processing unit 100 performing an arithmetic processing method. Figure 7 shows an example in which a read request RD1 that has missed a cache in one of the LLCs 30s also misses a cache in the home agent 140 (another LLC 30) and the external cache 200, and the data is read from the main memory 500.

[0106] Note that in Figure 7, the write-back address for replacing LLC30 and the write-back address for replacing external cache 200 do not match. In this case, the write-back from LLC30 is performed on external cache 200. The write-back address for replacing LLC30 is also called the LLC-Victim address or the evicting address. The write-back address for replacing external cache 200 is also called the EC-Victim address or the evicting address. The operation from issuing a read request RD4 to external cache 200 in response to a load request from core 10, and the write-back operation based on the replacement request MORP, are the same as in Figure 6.

[0107] In Figure 7, a read request RD to the external cache 200 results in a cache miss (Figure 7(a)). A cache miss occurs when the external cache 200 does not hold a tag address that matches the target address in the target entry of TAG201 corresponding to the target address of read request RD4.

[0108] The external cache 200 employs a direct-map method. Therefore, the data held in the target entry of the data memory 302 is evicted to make way for the data targeted by read request RD5 transferred from the main memory 500. The external cache 200 detected a cache miss in Figure 7(a), and the information indicated by TAG201 at that time is in the state EC-VICTIM-HIT="1". The external cache 200 decides to write back the evicted data to the main memory 500 if the contents of TAG201 are VAL="1" and DIRTY="1".

[0109] The external cache 200, having detected a cache miss, outputs a response RTN1 containing cache miss information to the move-in buffer MIB of the LLC 30, the issuer of the read request RD2 (Figure 7(b)). The response RTN1 includes information about a dirty flag DRTY="1", indicating that the data held in the target entry of the read request RD2 is dirty. Furthermore, the response RTN1 may also include invalid data in the event of a cache miss.

[0110] The pipeline control unit 307 performs move-in processing based on the response RTN1 received by the move-in buffer MIB (Figure 7(c)). For example, in the move-in processing, the pipeline control unit 307 releases the data area MIDQ of the data buffer 301 that was allocated when a read request RD1 was issued from the port MIP.

[0111] Furthermore, the external cache 200 outputs cache miss information MISS, a dirty flag DRTY="1", and the target address AD as a response RTN2 to the port MSP of the home agent 140 (Figure 7(d)). The dirty flag DRTY="1" indicates that the data to be evicted from the external cache 200 is dirty and therefore needs to be written back to main memory 500.

[0112] Then, a read request HRD for the main memory 500 and a replace request HMORP to evict data from the external cache 200 are output from the port MSP to the pipeline control unit 407 (Figures 7(e), (f)). The address of the read request HRD is the same as the address of the load request from core 10. The address of the replace request HMORP contains the index address of the entry in TAGD402 indicated by the load request from core 10.

[0113] The pipeline control unit 407 issues the read request HRD from the port MSP to the main memory 500 as a read request RD5 without referring to TAGD 402 (Figure 7(g)). The pipeline control unit 407 also detects that the write-back completion flag WRBK-CPLT of the entry to be written back in TAGD 402 is "0" based on the replace request HMORP from the port MSP, and decides to perform the write-back operation.

[0114] The pipeline control unit 407 then issues a write-back request WRBK3 containing write-back data to the main memory 500 (Figure 7(h)). The pipeline control unit 407 also locks the store by registering the index address of the entry to be replaced in TAGD402 with the store lock unit 403 (Figure 7(i)).

[0115] The main memory 500 reads the target data based on the read request RD5 (Figure 7(j)). The main memory 500 outputs the response RTN3, which contains the read target data, to the move-in buffer MIB of LLC30, the issuer of the read request RD2 (Figure 7(k)). The main memory 500 also forwards the response RTN4, which contains the read target data, to the port MSP of the home agent 140 (Figure 7(l)).

[0116] The pipeline control unit 307 stores the response data received by the move-in buffer MIB in the data memory 302 (MVIN) and updates the LLC-TAG 303 (Figure 7(m)). Then, the pipeline control unit 307 responds with the response data to the core 10 that issued the load request (Figure 7(n)).

[0117] Furthermore, the main memory 500 writes back the data included in the write-back request WRBK3 to the memory unit (Figure 7(o)). The data included in the write-back request WRBK3 is the data that was previously evicted from LLC30. Then, the main memory 500 notifies the home agent 140 of the completion response REL1 (including the target address AD) for the write-back request WRBK3 (Figure 7(p)). Upon receiving the write-back completion response REL, the store lock unit 403 releases the store-locked entry (Figure 7(q)).

[0118] The pipeline control unit 407 receives a move-in request HMVIN containing the target data for the read request HRD from the port MSP (Figure 7(r)). The pipeline control unit 407 transfers the target data received from the port MSP along with the move-in request HMVIN to the external cache 200 (Figure 7(s)).

[0119] The pipeline control unit 407 resets the lock flag LCK of the target way of the target entry in TAGD402 to "0". Also, since data from main memory 500 is stored in both the external cache 200 and LLC30, the pipeline control unit 407 sets the inclusion valid flag EC-VAL of the target way of the target entry in TAGD402 to "1". At this time, the pipeline control unit 407 may also reset the write-back completion flag WRBK-CPLT, which is set to "0", to "0". The pipeline control unit 407 stores the entry by registering the index address of the entry to be replaced in TAGD402 with the store lock unit 403 (Figure 7(t)).

[0120] Upon receiving the data for the move-in request HMVIN, the external cache 200 stores the received data in the data area DT202 and updates TAG201 (Figure 7(u)). The external cache 200 then notifies the home agent 140 of the move-in completion response REL2 (Figure 7(v)). Upon receiving the move-in completion response REL2, the store lock unit 403 of the home agent 140 releases the store lock (Figure 7(w)).

[0121] Figure 8 shows yet another example of the operation of the arithmetic processing unit 100 in Figure 1. Detailed explanations of operations identical or similar to those in Figures 6 and 7 are omitted. The operation shown in Figure 8 is achieved by the arithmetic processing unit 100 performing an arithmetic processing method. Figure 8, similar to Figure 7, shows an example in which a read request RD1 that has missed a cache in one of the LLCs 30s also misses a cache in the home agent 140 (another LLC 30) and the external cache 200, and the data is read from the main memory 500.

[0122] However, in Figure 8, the write-back address for replacing LLC30 and the write-back address for replacing external cache 200 coincide. In this case, the write-back from LLC30 is performed on main memory 500 (Figure 8(a)). For example, in Figure 8, when a write-back process is performed after a read process based on a read request RD3, the pipeline control unit 407 detects entries in TAGD402 indicating the lock flag LCK="1", the inclusion valid flag EC-VAL="0", the flag EC-INDX-MCH="1", and the flag EC-TAG-UNMCH="1".

[0123] The flag EC-TAG-UNMCH indicates that the tag address LL-TAG-AD does not match the physical address PA[47:20] included in the request. Based on the detection of the above entry, the pipeline control unit 407 detects a match between the write-back address for replacing LLC30 and the write-back address for replacing external cache 200. Then, at the timing of the write-back from LLC30 to main memory 500, the pipeline control unit 407 sets the write-back completion flag WRBK-CPLT of the target entry for write-back in TAGD402 to "1".

[0124] The pipeline control unit 407 receives a replacement request HMORP output from the port MSP based on the response RTN2 from the external cache 200 (Figure 8(b), (c)). The pipeline control unit 407 decides to cancel the write-back operation because the write-back completion flag WRBK-CPLT for the target entry in TAGD402 is "1" (Figure 8(d)).

[0125] In Figure 8, the dashed line following the replacement request HMORP indicates that the write-back operation will not be performed. This prevents the same address from being written back twice. In practice, because the write-back operation shown by the dashed line is omitted, the timing of the completion response REL2 being notified from the external cache 200 to the home agent 140 can be accelerated. As a result, a decrease in cache access efficiency can be suppressed.

[0126] Figure 9 shows an example of the operation flow of the arithmetic processing unit 100 in Figure 1. That is, Figure 9 shows an example of the arithmetic processing method of the arithmetic processing unit 100. The operation shown in Figure 9 is initiated based on the LLC 30 determining a cache miss and issuing a read request to the home agent 140. For example, Figure 9 shows the operation after the read request RD2 in Figures 6, 7, and 8 is issued. The operation shown in Figure 9 mainly shows the operation of the home agent 140.

[0127] First, in step S102, the home agent 140 refers to TAGD402 and determines whether or not a cache hit occurred. If the home agent 140 determines that a cache hit occurred, it performs step S104; if it determines that a cache miss occurred, it performs step S106.

[0128] In step S104, the home agent 140 reads the data targeted by the read request from the data memory 302 of the LLC 30 that hit the cache, because it encountered a cache hit in an LLC 30 different from the LLC 30 that issued the read request. Then, the operation shown in Figure 9 is completed. The home agent 140 responds to the core 10 of the LLC block 120 that issued the read request RD with the read data. Note that Figures 6 to 8 do not show the process in step S104 because they show the operation when the read request RD1 has a cache miss in all LLC 30s.

[0129] In step S106, the home agent 140 determines whether the flag EC-VICTIM-HIT is "1". If the flag EC-VICTIM-HIT is "1", the home agent 140 performs step S108, and if the flag EC-VICTIM-HIT is "0", it performs step S110. Here, the flag EC-VICTIM-HIT="0" indicates an inclusion state where the data targeted by the read request is held in the external cache 200. The flag EC-VICTIM-HIT="1" indicates a non-inclusion state where the data targeted by the read request is not held in the external cache 200.

[0130] In step S108, the home agent 140 sets the inclusion valid flag EC-VAL to "0" because the data to be read is in a non-inclusion state. The operation then proceeds to step S110. In step S110, the home agent 140 issues a read request to the external cache 200 (for example, RD4 in Figure 6).

[0131] Next, in step S112, the home agent 140 determines whether the external cache 200 has had a cache hit based on the information received from the external cache 200. If the home agent 140 determines that there has been a cache hit, it performs step S114; if it determines that there has been a cache miss, it performs step S200.

[0132] In step S114, the home agent 140 receives the target data for the read request that the external cache 200 has read from the data area DT202. The home agent 140 responds to the LLC block 120, which includes the core 10 that issued the read request, with the received target data. The LLC block 120 forwards the received target data to the core 10 that issued the read request. Then, the operation shown in Figure 9 is completed.

[0133] In step S200, the home agent 140 issues a read request RD to the main memory 500 based on a cache miss in the external cache 200 and performs cache miss processing to retrieve the data to be read. An example of the process in step S200 is shown in Figure 10.

[0134] Figure 10 shows an example of the processing in step S200 of Figure 9. In step S200, the operations of steps S202 to S208, which read the target data of the read request from the main memory 500, and the operations of steps S210 to S216, which write back the data evicted from the external cache 200 to the main memory 500, are performed in parallel.

[0135] In step S202, the home agent 140 issues a read request to the main memory 500 (for example, RD5 in Figures 7 and 8). Next, in step S204, the home agent 140 stores the response data transferred from the main memory 500 in the external cache 200.

[0136] Next, in step S206, the home agent 140 sets the inclusion valid flag EC-VAL of the target way of the entry in TAGD402 indicated by the target address of the read request to "1". An inclusion valid flag EC-VAL of "1" indicates that the target data of the read request RD is stored in both LLC30 and the external cache 200, resulting in an inclusion state. Next, in step S208, the home agent 140 responds to LLC30, the issuer of the read request, with the target data of the read request transferred from main memory 500, and completes the operation shown in Figure 10.

[0137] On the other hand, in step S210, the home agent 140 determines whether the dirty flag DRTY of the data to be evicted included in the response from the external cache 200 is "1". For example, the dirty flag DRTY is included in the response RTN2 in Figures 7 and 8. If the dirty flag DRTY is "1", the home agent 140 performs step S212 to perform a write-back. If the dirty flag DRTY is "0", the home agent 140 does not perform a write-back and terminates the operation shown in Figure 10.

[0138] In step S212, the home agent 140 determines whether the flag WRBK-CPLT of the target way of the entry in TAGD402 indicated by the target address of the read request is "1". If the flag WRBK-CPLT is "1", the address of the modified data to be evicted from LLC30 is the same as the address of the dirty data to be evicted from the external cache 200.

[0139] Therefore, if the flag WRBK-CPLT is "1", the home agent 140 performs step S214 to preferentially write back the modified data evicted from LLC 30 to main memory 500. The operation when the flag WRBK-CPLT is determined to be "1" in step S212 corresponds to the operation in Figure 8. The write-back operation of the data evicted from LLC 30 to main memory 500 is explained in Figure 11.

[0140] On the other hand, if the flag WRBK-CPLT is "0", the addresses of the modified data evicted from LLC30 and the addresses of the dirty data evicted from external cache 200 are different. Therefore, the home agent 140 performs step S216 to write back the modified data evicted from external cache 200 to main memory 500. The operation when the flag WRBK-CPLT is determined to be "0" in step S212 corresponds to the operation in Figure 7.

[0141] In step S214, the home agent 140 prioritizes writing data back from LLC30 to main memory 500, cancels the write-back of data from external cache 200 to main memory 500, and terminates the operation shown in Figure 10. In step S216, the home agent 140 writes back the modified data evicted from the external cache to main memory 500, and terminates the operation shown in Figure 10.

[0142] Figure 11 shows another example of the operation flow of the arithmetic processing unit 100 in Figure 1. Specifically, Figure 11 shows an example of the arithmetic processing method of the arithmetic processing unit 100. The operation shown in Figure 11 is initiated when LLC 30 issues a write-back request WRBK to the home agent 140 based on a cache miss in LLC 30. For example, Figure 11 shows the operation after the write-back request WRBK1 in Figures 6, 7, and 8 is issued. The operation shown in Figure 11 mainly shows the operation of the home agent 140. Note that the data to be written back from LLC 30 is assumed to be in a modified state.

[0143] First, in step S302, the home agent 140 refers to the tag information of the way where the data to be evicted is held in TAGD 402 and determines whether TAGD is in a hit state or not. A hit state for TAGD indicates that the data to be evicted is held in the data memory 302 of LLC 30. If TAGD is in a hit state, the home agent 140 performs step S304; otherwise, it performs step S316.

[0144] In step S304, the home agent 140 determines whether the inclusion valid flag EC-VAL of the way corresponding to the data to be evicted in TAGD402 is "1". If the inclusion valid flag EC-VAL is "1", the data to be written back is in an inclusion state, so the home agent 140 performs step S306 to write it back to the external cache 200.

[0145] On the other hand, if the inclusion valid flag EC-VAL is "0", the target data is in a non-inclusion state, so the home agent 140 performs step S310 to write it back to the main memory 500.

[0146] In step S306, the home agent 140 outputs information to the external cache 200 that sets the dirty flag DRTY of the entry whose data is to be written back to "1" in TAG201 of the external cache 200. Next, in step S308, the home agent 140 writes back the data to be written back to the external cache 200 and terminates the operation shown in Figure 11.

[0147] In step S310, the home agent 140 determines whether the evicting address of LLC30 matches the evicting address of external cache 200. If the evicting addresses match, the home agent 140 performs step S312 to cancel the write-back from external cache 200 to main memory 500. If the evicting addresses do not match, the home agent 140 performs step S314 to enable the write-back from external cache 200 to main memory 500.

[0148] A match in the evicting address is determined when the tag address of the entry locked by the read request in TAG201 of the external cache 200 does not match the corresponding bit of the address in the read request.

[0149] In step S312, the home agent 140 sets the flag WRBK-CPLT of the target way of the entry in TAGD402 indicated by the address to be written back to "1". This cancels the write back to main memory 500 of the entry for which the flag WRBK-CPLT is set to "1", thereby preventing duplicate write back operations.

[0150] In step S314, the home agent 140 outputs information to the external cache 200 that sets the dirty flag DRTY of the entry whose data is to be written back to "1" in TAG201 of the external cache 200. Next, in step S316, the home agent 140 writes back the data to be written back from LLC30 to the main memory 500, and terminates the operation shown in Figure 11.

[0151] In step S318, the home agent 140 detects a protocol error because there is no data to evict from LLC30, and terminates the operation shown in Figure 11. If a protocol error occurs, the home agent 140 may, for example, notify a higher-level control device that manages the arithmetic processing unit 100 of the protocol error.

[0152] In this embodiment, an inclusion-validated flag EC-VAL, which indicates whether the data held in LLC30 is in an inclusion state or an exclusion state, is provided in TAGD402. As a result, the home agent 140 can determine the write-back destination of the data held in LLC30 without reading tag information from TAG201 of the external cache 200 by referring to the inclusion-validated flag EC-VAL. Since access to the external cache 200 to determine the write-back destination can be omitted, a decrease in memory access efficiency can be suppressed. Therefore, in the arithmetic processing unit 100 having a hierarchical cache structure, a decrease in cache access efficiency can be suppressed.

[0153] The home agent 140 sets the inclusion valid flag EC-VAL to "1" based on the fact that the data to be accessed is stored in the external cache 200 and LLC 30 in the event of a cache miss. The home agent 140 resets the corresponding inclusion valid flag EC-VAL to "0" when the data corresponding to the data held in LLC 30 is written back from the external cache 200 to main memory 500 due to a replacement process. This allows the value of the inclusion valid flag EC-VAL to be changed in accordance with changes in the data retention status of LLC 30 and the external cache 200. As a result, the home agent 140 can correctly perform data write-back from LLC 30 by referring to the inclusion valid flag EC-VAL.

[0154] A write-back completion flag, WRBK-CPLT, is provided in TAGD402, which is set when data corresponding to data written back from LLC30 to main memory 500 remains in the external cache 200. This allows the home agent 140 to cancel the write-back from the external cache 200 to main memory 500 when the write-back completion flag WRBK-CPLT is set. This prevents the same address from being written back twice, thus suppressing a decrease in cache access efficiency.

[0155] Therefore, in the arithmetic processing unit 100 having a hierarchical cache structure, a decrease in cache access efficiency can be suppressed. In addition, it is possible to prevent data written back from LLC 30 to main memory 500 from being overwritten by older data from the external cache 200, thereby preventing malfunctions of the arithmetic processing unit 100.

[0156] Multiple LLCs 30 are connected to the external cache 200 and main memory 500 via a home agent 140. Therefore, the home agent 140 can control data transfer between the multiple LLCs 30 and the external cache 200, and between the multiple LLCs 30 and the main memory 500. Since each of the multiple LLCs 30 does not need to control data transfer between the external cache 200 and the main memory 500, data transfer control by the cache operation can be simplified, and a decrease in cache access efficiency can be suppressed.

[0157] The home agent 140 can understand the status of the data held in each LLC30 by storing the information held in the LLC-TAG303 of each LLC30 in the TAGD402. This reduces the frequency of access from the home agent 140 to each LLC30, thereby suppressing the decrease in cache access efficiency.

[0158] Figure 12 shows an example of an arithmetic processing unit in another embodiment. Detailed explanations of elements identical or similar to those in Figure 1 are omitted. The arithmetic processing unit 100A shown in Figure 12 has a die (semiconductor chip) 110A and an external cache 200, and is, for example, in the form of a package. A main memory 500 is connected to the arithmetic processing unit 100A. The external cache 200 and the main memory 500 are identical or similar to the external cache 200 and main memory 500 shown in Figure 1, respectively. The arithmetic processing unit 100A and the main memory 500 then operate as an information processing unit 600A.

[0159] Die 110A has an LLC block 120A and memory control units 150 and 160. The LLC block 120A has multiple cores 10, an L1 cache 20 and an LLC 30A corresponding to each core 10, and does not have the communication interface unit 40 shown in Figure 1. The cores 10, L1 cache 20 and memory control units 150 and 160 are identical or similar to the cores 10, L1 cache 20 and memory control units 150 and 160 shown in Figure 1, respectively.

[0160] LLC30A employs a set-associative scheme with multiple ways, similar to LLC30 shown in Figure 1, and has multiple entries, each capable of holding multiple data with the same index address. LLC30A has LLC-TAG303A (tags). An example of LLC-TAG303A is shown in Figure 13. LLC-TAG303A is an example of a first tag area and a second tag area.

[0161] LLC30A has the same configuration and functions as LLC30 shown in Figure 2, except that it has LLC-TAG303A instead of LLC-TAG303. For example, LLC30A has the same data buffer 301, data memory 302, evacuation information holding unit 304, multiple ports 305, pipe insertion unit 306, pipeline control unit 307, snoop lock unit 308, and cache miss control unit 309 as in Figure 2. The pipeline control unit 307 in LLC30A is an example of a control unit.

[0162] Figure 13 shows an example of the components of LLC-TAG303A shown in Figure 12. Detailed explanations of elements that are the same as or similar to those in Figure 5 are omitted. Note that the components of each entry in the external cache 200 are the same as or similar to those in Figure 5. LLC-TAG303A adds a 1-bit inclusion valid flag EC-VAL and a 1-bit write-back completion flag WRBK-CPLT to LLC-TAG303 shown in Figure 5.

[0163] The usage of the inclusion valid flag EC-VAL and the write-back completion flag WRBK-CPLT is the same as the usage of the inclusion valid flag EC-VAL and the write-back completion flag WRBK-CPLT in TAGD402 shown in Figure 5. The arithmetic processing unit 100A in this embodiment does not have multiple LLC blocks 120.

[0164] Therefore, the arithmetic processing unit 100A does not have the home agent 140 shown in Figure 1, and the functions of the home agent 140 are realized by each LLC block 120A. For example, the pipeline control unit 307 of LLC 30A has the function of setting the inclusion valid flag EC-VAL and the write-back completion flag WRBK-CPLT. The assignment of index addresses for LLC-TAG303A and TAG201 is the same as the assignment of index addresses for LLC-TAG303 and TAG201 shown in Figure 4.

[0165] Figure 14 shows an example of the operation of the arithmetic processing unit 100A in Figure 12. Detailed explanations of operations that are the same as or similar to those in Figure 6 are omitted. The operation shown in Figure 14 is realized by the arithmetic processing unit 100A executing the arithmetic processing method. Figure 14 shows the operation when a read request RD that has missed a cache in any of the LLCs 30A hits the cache in the external cache 200.

[0166] Since the arithmetic processing unit 100A does not have the home agent 140 shown in Figures 1 and 3, lock control is performed by LLC 30A. Figure 14 is similar to the operation in Figure 6, except that various requests to the external cache 200 are issued from LLC 30A, and the response from the external cache 200 is forwarded to LLC 30A, which issued the request.

[0167] Figure 15 shows another example of the operation of the arithmetic processing unit 100A in Figure 12. Detailed explanations of operations identical or similar to those in Figure 7 are omitted. The operation shown in Figure 15 is realized by the arithmetic processing unit 100A executing the arithmetic processing method. Figure 15 shows an example in which a read request RD that missed in the LLC 30A also misses in the external cache 200, and data is read from the main memory 500. When the write-back operation from LLC 30A is performed, the write-back completion flag WRBK-CPLT of the entry to be written back is set to "0".

[0168] In Figure 15, lock control is performed by LLC30A. Figure 15 is similar to the operation in Figure 7, except that various requests to the external cache 200 are issued from LLC30A, and the response from the external cache 200 is forwarded to LLC30A, which issued the request.

[0169] Figure 16 shows yet another example of the operation of the arithmetic processing unit 100A in Figure 12. Detailed explanations of operations identical or similar to those in Figure 8 are omitted. The operation shown in Figure 16 is realized by the arithmetic processing unit 100A performing an arithmetic processing method. Figure 16 shows an example in which a read request RD that missed in the LLC 30A also misses in the external cache 200, and data is read from the main memory 500. When the write-back operation from LLC 30A is performed, the write-back completion flag WRBK-CPLT of the entry to be written back is set to "1".

[0170] In Figure 16, lock control is performed by LLC30A. Figure 16 is similar to the operation in Figure 8, except that various requests to the external cache 200 are issued from LLC30A, and the response from the external cache 200 is forwarded to LLC30A, the issuer of the request. For example, in Figure 16, since the write-back completion flag WRBK-CPLT of the target entry for write-back in LLC-TAG303A is "1", LLC30A decides to cancel the write-back operation. This prevents the same address from being written back twice.

[0171] The operation flow of the arithmetic processing unit 100A is the same as that of Figures 9 to 11, except that each LLC 30A is primarily responsible for performing the processing. In this embodiment, steps S102 and S104 in Figure 9 are omitted.

[0172] As described above, the same effects as those of the embodiments described can be obtained in this embodiment as well. For example, each LLC30A can determine the write-back destination of the data held in LLC30A without reading tag information from TAG201 of the external cache200 by referring to the inclusion valid flag EC-VAL. Since access to the external cache200 to determine the write-back destination can be omitted, a decrease in memory access efficiency can be suppressed. Therefore, in the arithmetic processing unit 100A having a hierarchical cache structure, a decrease in cache access efficiency can be suppressed.

[0173] Furthermore, each LLC30A can cancel the write-back from the external cache 200 to the main memory 500 if the write-back completion flag WRBK-CPLT of LLC-TAG303A is set. This prevents the same address from being written back twice, thereby suppressing a decrease in cache access efficiency. In addition, it prevents data written back from LLC30A to the main memory 500 from being overwritten by older data from the external cache 200, thereby preventing malfunctions of the arithmetic processing unit 100.

[0174] The following additional information is disclosed regarding the embodiments described above. (Note 1) The arithmetic unit that executes the instructions, A first cache connected to the calculation unit, having a plurality of first entries, each including a first tag area and a first data area that holds cache line data, The second tag area and, A control unit that controls the first cache based on the information held in the second tag area, A second cache is connected to the first cache via the control unit and has a plurality of second entries, each including a third tag area and a second data area that holds cache line data, The second tag area has a first area that holds first information indicating whether cache line data with the same address as the cache line data held in the first data area is held in the second data area, The control unit determines, based on the first information held in the second tag area corresponding to the cache line data to be written back, whether to write the cache line data held in the first cache back to the second cache or to external memory. Processing unit. (Note 2) The control unit, When cache line data is transferred from the second cache to the first cache, the first information corresponding to the transferred cache line data is set to a value indicating that the second cache is a write-back destination. When cache line data with the same address as the cache line data held in the first cache is written back from the second cache to the external memory, the first information corresponding to the cache line data being written back is set to a value indicating that the external memory is the write-back destination. The arithmetic processing unit described in Appendix 1. (Note 3) When searching the second tag area for the address to be accessed, if an entry is found in which the bit value corresponding to the index address of the third tag area matches, and the bit value corresponding to the tag address of the third tag area does not match, the first information of the detected entry is set to a value indicating that the external memory is the write-back destination. The arithmetic processing device according to claim 2. (Note 4) The second tag area has a second area that stores second information which is set when cache line data held in the first cache is written back to the external memory, and cache line data with the same address as the written-back cache line data remains in the second cache. The control unit, when it has set second information corresponding to the cache line data to be written back held in the second cache, suppresses the write-back of the cache line data to be written back from the second cache to the external memory. The arithmetic processing unit described in Appendix 1. (Note 5) The system has a plurality of cache blocks, each including the aforementioned calculation unit and the first cache. The control unit is positioned between the plurality of cache blocks and the second cache. The arithmetic processing unit described in any one of the items in Appendix 1 to Appendix 3. (Note 6) The second tag area has a region that holds a portion of the multiple types of tag information held in the first tag area, and the first area. The arithmetic processing unit described in Appendix 4. (Note 7) The second tag area and the control unit are included in the first cache. The arithmetic processing unit described in any one of the items in Appendix 1 to Appendix 3. (Note 8) Each of the plurality of first entries in the first cache has a plurality of ways, Each of the plurality of second entries in the second cache has a single way The arithmetic processing unit described in any one of the items in Appendix 1 to Appendix 3. (Note 9) A die on which the calculation unit and the first cache are mounted, The package comprises the die and the second cache, The control unit is connected to the external memory located outside the package. The arithmetic processing unit described in any one of the items in Appendix 1 to Appendix 3. (Note 10) An arithmetic processing method for an arithmetic processing device comprising: an arithmetic unit for executing instructions; a first cache connected to the arithmetic unit and having a plurality of first entries, each including a first tag area and a first data area for holding cache line data; a second tag area; a control unit; and a second cache connected to the first cache via the control unit and having a plurality of second entries, each including a third tag area and a second data area for holding cache line data, wherein the second tag area has a first area for holding first information indicating whether cache line data with the same address as the cache line data held in the first data area is held in the second data area; The control unit, The first cache is controlled based on the information held in the second tag area. Based on the first information held in the second tag area corresponding to the cache line data to be written back, it is determined whether to write back the cache line data held in the first cache to the second cache or to external memory. Calculation processing method.

[0175] The features and advantages of the embodiments will become clear from the detailed description above. This is intended to be so as not to deviate from the spirit and scope of the claims, that the features and advantages of the embodiments described above are included. Furthermore, any improvement and modification should be readily conceivable to a person with ordinary skill in the art. Therefore, there is no intention to limit the scope of inventive embodiments to those described above, and it is also possible to rely on appropriate improvements and equivalents that fall within the scope disclosed in the embodiments. [Explanation of symbols]

[0176] 10 cores 20 L1 cache 30, 30A LLC 100, 100A Arithmetic Processing Unit 110, 110A die 120, 120A LLC Block 130 Communications Department 140 Home Agents 150, 160 Memory Control Unit 200 External Cache 201 tags 202 Data Area 301 Data Buffer 302 data memory 303, 303A tags 304 Information retention unit for expulsion Port 305 306 Pipe insertion section 307 Pipeline Control Unit 308 Snoop Rock Section 309 Cache Miss Control Unit 401 Data Buffer 402 Tags 403 Store Lock Section 404 Memory Response Receiving Unit Port 405 406 Pipe insertion section 407 Pipeline Control Unit 408 Snoop Rock Section 409 Selector 500 Main storage 600, 600A Information Processing Device EC-INDX-MCH flag EC-VAL Inclusion Valid Flag EC-VICTIM-HIT flag TAGD-HIT flag WRBK-CPLT Writeback complete flag

Claims

1. The arithmetic unit that executes the instructions, A first cache connected to the calculation unit, having a plurality of first entries, each including a first tag area and a first data area that holds cache line data, The second tag area and, A control unit that controls the first cache based on the information held in the second tag area, A second cache is connected to the first cache via the control unit and has a plurality of second entries, each including a third tag area and a second data area that holds cache line data, The second tag area has a first area that holds first information indicating whether cache line data with the same address as the cache line data held in the first data area is held in the second data area, The control unit determines, based on the first information held in the second tag area corresponding to the cache line data to be written back, whether to write the cache line data held in the first cache back to the second cache or to external memory. Processing unit.

2. The control unit, When cache line data is transferred from the second cache to the first cache, the first information corresponding to the transferred cache line data is set to a value indicating that the second cache is a write-back destination. When cache line data with the same address as the cache line data held in the first cache is written back from the second cache to the external memory, the first information corresponding to the cache line data being written back is set to a value indicating that the external memory is the write-back destination. The arithmetic processing device according to claim 1.

3. When searching the second tag area for the address to be accessed, if an entry is found in which the bit value corresponding to the index address of the third tag area matches, and the bit value corresponding to the tag address of the third tag area does not match, the first information of the detected entry is set to a value indicating that the external memory is the write-back destination. The arithmetic processing device according to claim 2.

4. The second tag area has a second area that stores second information which is set when cache line data held in the first cache is written back to the external memory, and cache line data with the same address as the written-back cache line data remains in the second cache. The control unit, when it has set second information corresponding to the cache line data to be written back held in the second cache, suppresses the writing back of the cache line data to be written back from the second cache to the external memory. The arithmetic processing device according to claim 1.

5. The system has a plurality of cache blocks, each including the aforementioned calculation unit and the first cache. The control unit is positioned between the plurality of cache blocks and the second cache. The arithmetic processing apparatus according to any one of claims 1 to 4.

6. The second tag area has a region that holds a portion of the multiple types of tag information held in the first tag area, and the first area. The arithmetic processing apparatus according to claim 5.

7. The first cache includes a fourth tag region including the first tag region and the second tag region, and the control unit, The control unit determines, based on the first information held in the second tag area included in the fourth tag area, whether to write back the cache line data held in the first data area of ​​the first cache to the second cache or to the external memory. The arithmetic processing apparatus according to any one of claims 1 to 4.

8. An arithmetic processing method for an arithmetic processing device comprising: an arithmetic unit for executing instructions; a first cache connected to the arithmetic unit and having a plurality of first entries, each including a first tag area and a first data area for holding cache line data; a second tag area; a control unit; and a second cache connected to the first cache via the control unit and having a plurality of second entries, each including a third tag area and a second data area for holding cache line data, wherein the second tag area has a first area for holding first information indicating whether cache line data with the same address as the cache line data held in the first data area is held in the second data area; The control unit, The first cache is controlled based on the information stored in the second tag area. Based on the first information held in the second tag area corresponding to the cache line data to be written back, it is determined whether the destination for writing back the cache line data held in the first cache is the second cache or external memory. Calculation processing method.

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