Display panel and its manufacturing method, electronic device

Abstract

A display panel and its manufacturing method, and an electronic device, the display panel comprises a base substrate (10), an array structure layer and a light-emitting structure layer (20) disposed on the base substrate (10), the base substrate (10) comprises a transistor (11), the array structure layer comprises a first conductive pillar (13), a connection electrode (14) and a second conductive pillar (16), the light-emitting structure layer (20) comprises a first electrode (21), an organic light-emitting layer (22) and a second electrode (23), the first electrode (21) is located on a side of the organic light-emitting layer (22) that is closer to the base substrate (10), the second electrode (23) is located on a side of the organic light-emitting layer (22) that is farther from the base substrate (10), the first electrode (21) comprises a first sub-electrode (211), a second electrode (23), a third electrode (23), a fourth electrode (23), a fifth electrode (23), a sixth ... The semiconductor device includes a second sub-electrode (212) and a third sub-electrode (213), the second sub-electrode (212) being located on the side of the first sub-electrode (211) that is away from the base substrate (10), the third sub-electrode (213) being located on the side of the first sub-electrode (211) that is closer to the base substrate (10), the reflectivity of the first sub-electrode (211) being greater than a threshold reflectivity and greater than the reflectivity of the second sub-electrode (212), the reflectivity of the second sub-electrode (212) being less than the reflectivity of the third sub-electrode (213), the first electrode (21) being connected to the connection electrode (14) by the second conductive pillar (16), and the connection electrode (14) being connected to the drain electrode of the transistor (11) by the first conductive pillar (13).

Description

Technical Field

[0001] The present disclosure relates to the display technology field, but is not limited thereto, and particularly relates to a display panel, a manufacturing method thereof, and an electronic device.

Background Art

[0002] A micro organic light-emitting diode (abbreviated as Micro-OLED) is a microdisplay that has been developed in recent years, and silicon-based OLED is one of them. The silicon-based OLED can not only realize active addressing of pixels, but also realize manufacturing a plurality of functional circuits including a timing control (TCON) circuit, an overcurrent protection (OCP) circuit, etc. on a silicon substrate, which helps to reduce the volume of the system and achieve weight reduction. The silicon-based OLED is manufactured using a mature complementary metal oxide semiconductor (abbreviated as CMOS) integrated circuit process, and has advantages such as small volume, high resolution (Pixels Per Inch, abbreviated as PPI), and high refresh rate, and is widely applied in the near-eye display field of virtual reality (VR, Virtual Reality) or augmented reality (AR, Augmented Reality).

Summary of the Invention

Means for Solving the Problems

[0003] The following is an overview of the subject matter described in detail in the present disclosure. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, the present disclosure provides a display panel comprising a base substrate and an array structure layer and an emissive structure layer sequentially installed on the base substrate, wherein the base substrate comprises transistors, the array structure layer comprises a first conductive pillar, a connecting electrode and a second conductive pillar sequentially installed, and the emissive structure layer comprises a first electrode, an organic emissive layer and a second electrode, wherein the first electrode is located on the side of the organic emissive layer adjacent to the base substrate, and the second electrode is located on the side of the organic emissive layer away from the base substrate. The first electrode comprises a first sub-electrode, a second sub-electrode, and a third sub-electrode, wherein the second sub-electrode is located on the side of the first sub-electrode away from the base substrate, and the third sub-electrode is located on the side of the first sub-electrode closer to the base substrate. The reflectance of the first sub-electrode is greater than the threshold reflectance and greater than the reflectance of the second sub-electrode, and the reflectance of the second sub-electrode is less than the reflectance of the third sub-electrode. The first electrode is connected to the connecting electrode by the second conductive pillar, and the connecting electrode is connected to the drain electrode of the transistor by the first conductive pillar.

[0005] In some possible implementations, the second sub-electrode is a transparent electrode, and the orthographic projection on the base substrate covers the orthographic projection of the first sub-electrode on the base substrate. The orthographic projection of the third sub-electrode on the base substrate covers at least the orthographic projection of the first sub-electrode on the base substrate, and the orthographic projection of the second sub-electrode on the base substrate covers the orthographic projection of the third sub-electrode on the base substrate.

[0006] In some possible implementations, the display panel further includes gate lines, wherein the length of the first sub-electrode along the first direction is greater than the length of the second sub-electrode along the first direction, and the length of the first sub-electrode along the second direction is less than the length of the second sub-electrode along the second direction. The length of the second sub-electrode along the second direction is 1.2 times the length of the first sub-electrode along the second direction. The first direction is perpendicular to the base substrate, and the second direction is the direction in which the gate line extends.

[0007] In some possible realizations, the manufacturing material for the first sub-electrode contains silver, The length of the first sub-electrode along the first direction is 400 angstroms to 600 angstroms, and the length of the first sub-electrode along the second direction is 1.5 micrometers to 2.5 micrometers.

[0008] In some possible implementations, the manufacturing material for the second sub-electrode includes indium tin oxide. The length of the second sub-electrode along the first direction is 120 angstroms to 180 angstroms, and the length of the second sub-electrode along the second direction is 1.8 micrometers to 4 micrometers.

[0009] In some possible implementations, the manufacturing material for the third sub-electrode includes titanium. The length of the third sub-electrode along the first direction is 80 angstroms to 120 angstroms, and the length of the third sub-electrode along the second direction is 1.5 micrometers to 2.5 micrometers.

[0010] In some possible realizations, the manufacturing material for the first sub-electrode contains silver, the manufacturing material for the second sub-electrode contains indium tin oxide, and the manufacturing material for the third sub-electrode contains titanium.

[0011] In some possible implementations, the threshold reflectance is 80%. The work function of the second sub-electrode is greater than 5, and the light transmittance of the second sub-electrode is greater than 99%.

[0012] In some possible implementations, the display panel further comprises a pixel definition layer, a package layer, and a color film layer. The pixel definition layer is located on the side of the array structure layer away from the base substrate. The package layer is located on the side of the light-emitting structure layer that is away from the base substrate. The color film layer is located on the side of the package layer away from the base substrate, The manufacturing material for the aforementioned pixel definition layer contains silicon dioxide.

[0013] In some possible implementations, the package layer comprises a first inorganic package layer, a second inorganic package layer, and a third organic package layer. The first inorganic package layer is located on the side of the second inorganic package layer that is close to the base substrate. The third organic package layer is located on the side of the second inorganic package layer that is away from the base substrate.

[0014] In some possible implementations, the display panel further comprises a cover plate, The cover plate is located on the side of the color film layer away from the base substrate and is used to protect the color film layer.

[0015] In a second aspect, the disclosure further provides an electronic device comprising the display panel described above.

[0016] In a third aspect, the present disclosure further provides a method for manufacturing a display panel, the method being used to manufacture the display panel, An array structure layer is formed on the base substrate, and the base substrate is equipped with transistors. A first electrode comprising a first sub-electrode, a second sub-electrode, and a third sub-electrode is formed on the side of the array structure layer away from the base substrate, Forming an organic light-emitting layer on the side of the first electrode away from the base substrate, The method includes forming a second electrode on the side of the organic light-emitting layer away from the base substrate, thereby forming a light-emitting structure layer comprising the first electrode, the organic light-emitting layer, and the second electrode.

[0017] In some possible implementation manners, forming a first electrode including a first sub - electrode, a second sub - electrode, and a third sub - electrode on the side of the array structure layer away from the base substrate means that sequentially applying an antireflection thin film and a photoresist on the side of the array structure layer away from the base substrate; performing exposure and development processes on the antireflection thin film and the photoresist; sequentially depositing a first metal thin film and a second metal thin film on the antireflection thin film and the photoresist after the exposure process; immersing the base substrate on which the first metal thin film and the second metal thin film are deposited in a stripping solution to strip the photoresist; performing a development process on the base substrate after the photoresist is stripped to strip the antireflection thin film and form the third sub - electrode and the first sub - electrode; forming a second sub - electrode on the side of the first sub - electrode away from the base substrate, and includes.

[0018] In some possible implementation manners, the immersion time of the base substrate on which the first metal thin film and the second metal thin film are deposited in the stripping solution is less than 30 minutes.

[0019] In some possible implementation manners, forming a second sub - electrode on the side of the first sub - electrode away from the base substrate means that depositing a transparent conductive thin film by a sputtering process on the side of the first sub - electrode away from the base substrate; applying a photoresist on the transparent conductive thin film; performing exposure and development processes on the photoresist; etching the transparent conductive thin film by a dry etching process; stripping the photoresist to form the second sub - electrode, and the orthographic projection of the second sub - electrode on the base substrate covers the orthographic projection of the first sub - electrode on the base substrate, and includes.

[0020] In some possible implementations, the interval between the start time for depositing a transparent conductive thin film by sputtering on the side of the first sub-electrode away from the base substrate and the end time for immersing the base substrate on which the first and second metal thin films are deposited in a stripping solution to remove the photoresist is shorter than 120 minutes.

[0021] In some possible implementations, before forming the organic light-emitting layer on the side of the first electrode away from the base substrate, the method further A pixel-defining thin film is deposited on the side of the first electrode away from the base substrate, Applying a photoresist to the pixel definition thin film, The process involves exposure and development of a photoresist, Etching the pixel definition thin film by a dry etching process, This includes peeling off the photoresist to form a pixel definition layer.

[0022] In some possible implementations, after forming a second electrode on the side away from the base substrate of the organic light-emitting layer, the method further A package layer is formed on the side of the second electrode that is away from the base substrate, A color film layer is formed on the side of the package layer that is away from the base substrate, This includes forming a cover plate on the side of the color film layer that is away from the base substrate.

[0023] After reviewing and understanding the drawings and detailed descriptions, other embodiments can be understood. [Brief explanation of the drawing]

[0024] The drawings are for the purpose of understanding the proposed technical invention of this disclosure and constitute part of the specification, and are used together with the embodiments of this disclosure to interpret the proposed technical invention of this disclosure, and do not limit the proposed technical invention of this disclosure.

[0025] [Figure 1]Figure 1 is a schematic diagram of the structure of a display panel according to an embodiment of the present disclosure. [Figure 2] Figure 2 is a schematic diagram of the circuit principle of a base substrate according to an exemplary embodiment. [Figure 3] Figure 3 is a schematic diagram of the circuit implementation of a voltage control circuit and a pixel driving circuit according to an exemplary embodiment. [Figure 4] Figure 4 is a schematic diagram of the structure of an organic light-emitting layer according to an exemplary embodiment. [Figure 5] Figure 5 is a schematic diagram of the structure of a display panel according to an exemplary embodiment. [Figure 6] Figure 6 is a schematic diagram of the structure of a display panel according to another exemplary embodiment. [Figure 7] Figure 7 is a flowchart of the method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 8] Figure 8 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 9] Figure 9 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 10] Figure 10 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 11] Figure 11 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 12] Figure 12 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 13] Figure 13 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 14] Figure 14 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 15] Figure 15 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 16] Figure 16 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 17] Figure 17 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 18]Figure 18 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 19] Figure 19 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 20] Figure 20 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 21] Figure 21 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 22] Figure 22 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Figure 23] Figure 23 is a schematic diagram of a method for manufacturing a display panel according to an exemplary embodiment. [Modes for carrying out the invention]

[0026] To further clarify the purpose, technical proposals, and advantages of this disclosure, embodiments of this disclosure will be described in detail below with reference to the drawings. Embodiments may be implemented in multiple different forms. It is a fact that will be readily apparent to those skilled in the art that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited only to the embodiments described below. The embodiments and features of these embodiments can be combined in any way as long as they do not conflict with each other.

[0027] In the drawings, the size, layer thickness, or area of ​​each component may be shown enlarged for clarity. Therefore, embodiments of this disclosure are not limited to these sizes, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, while the drawings schematically illustrate ideal examples, embodiments of this disclosure are not limited to the shapes or numerical values ​​shown in the drawings.

[0028] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by those skilled in the art within the field to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, number, or importance, but are merely used to distinguish different components. Similar terms such as “equipment” or “includes” mean that the element or component described after the term covers the elements or components and equivalents listed before the term, but do not exclude other elements or components. Similar terms such as “connection” or “linking” are not limited to physical or mechanical connections, but also include electrical connections, whether direct or indirect. “Up,” “down,” “left,” “right,” etc., refer only to relative positional relationships, and such relative positional relationships may change if the absolute position of the described object changes.

[0029] In this specification, a transistor refers to an element having at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. The channel region refers to the region through which current primarily flows.

[0030] In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. When using transistors with opposite polarity or when the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" may be swapped. Therefore, in this specification, the "source electrode" and "drain electrode" can be swapped with each other.

[0031] In this specification, “connection” includes situations in which components are connected together by an element having an electrical function. “An element having an electrical function” is not particularly limited as long as it can transmit and receive electrical signals between the connected components. Examples of “an element having an electrical function” include electrodes and wiring, as well as switching elements such as transistors, resistors, inductors, capacitors, and various other functional elements.

[0032] In this specification, "film" and "layer" can be interchanged with each other. For example, a "conductive layer" may be replaced with a "conductive film." Similarly, an "insulating film" may be replaced with an "insulating layer."

[0033] A silicon-based OLED comprises a silicon-based backplane on which the driving circuit is integrated, and an OLED light-emitting array formed on the silicon-based backplane. The OLED light-emitting array comprises an anode, an organic light-emitting layer, and a cathode.

[0034] Due to the high PPI of silicon-based OLEDs, a top-emission structure may be used. The anode is configured to achieve reflective functionality. Generally, a titanium / aluminum / titanium stacked structure is used for the anode, resulting in low reflectivity, which further affects the display brightness of the silicon-based OLED and reduces its display effectiveness.

[0035] Figure 1 is a schematic diagram of the structure of a display panel according to an embodiment of the present disclosure. As shown in Figure 1, the display panel according to an embodiment of the present disclosure comprises a base substrate 10, an array structure layer and a light-emitting structure layer 20 installed on the base substrate 10. The base substrate 10 comprises a transistor 11, the array structure layer comprises a first conductive pillar 13, a connecting electrode 14 and a second conductive pillar 16 which are installed sequentially, and the light-emitting structure layer 20 comprises a first electrode 21, an organic light-emitting layer 22 and a second electrode 23. The first electrode 21 is located on the side of the organic light-emitting layer 22 that is close to the base substrate 10, and the second electrode 23 is located on the side of the organic light-emitting layer 22 that is away from the base substrate 10.

[0036] The first electrode 21 comprises a first sub-electrode 211, a second sub-electrode 212, and a third sub-electrode 213, with the second sub-electrode 212 located on the side of the first sub-electrode 211 away from the base substrate 10, and the third sub-electrode 213 located on the side of the first sub-electrode 211 closer to the base substrate 10.

[0037] The reflectance of the first sub-electrode 211 is greater than the threshold reflectance and greater than the reflectance of the second sub-electrode 212, while the reflectance of the second sub-electrode 212 is less than the reflectance of the third sub-electrode 213.

[0038] The first electrode 21 is connected to the connecting electrode 14 by the second conductive pillar 16, and the connecting electrode 14 is connected to the drain electrode of the transistor 11 by the first conductive pillar 13.

[0039] The first sub-electrode 211 is configured to reflect light emitted from the organic light-emitting layer 22, and the second sub-electrode 212 is configured to transmit the light reflected by the first sub-electrode 211. The third sub-electrode 213 is configured to strengthen the adhesion between the first sub-electrode 211 and the array structure layer, thereby preventing aggregation and detachment of the first sub-electrode 211.

[0040] In this exemplary embodiment, the base substrate 10 may be a silicon substrate or a glass substrate, and the active layer of the transistor 11 is formed inside the base substrate 10.

[0041] In the exemplary embodiment, transistor 11 may be a metal oxide semiconductor field-effect transistor (MOS).

[0042] In an exemplary embodiment, the display panel comprises a display area and a non-display area. The display panel comprises a plurality of subpixels located in the display area. The non-display area comprises a control circuit. Figure 1 shows only the display area and explains the case where the display panel comprises three subpixels, subpixels 100A, 100B, and 100C, as an example.

[0043] In an exemplary embodiment, three subpixels of different colors constitute a single pixel, and the three subpixels may be a red subpixel, a green subpixel, and a blue subpixel, respectively. In some possible implementations, a single pixel may have four, five or more subpixels, which may be designed and determined according to the actual application environment.

[0044] In an exemplary embodiment, as shown in Figure 1, transistors in the array structure layer located on the base substrate 10 can constitute a pixel driving circuit.

[0045] Figure 2 is a schematic diagram of the circuit principle of a base substrate according to an exemplary embodiment. As shown in Figure 2, multiple display rows and multiple display columns are formed by the regular arrangement of multiple subpixels in the display area. Each subpixel comprises a pixel driving circuit 101 and a light-emitting device 102 connected to the pixel driving circuit 101. The pixel driving circuit 101 comprises at least a driving transistor. The control circuit comprises at least multiple voltage control circuits 110, each voltage control circuit 110 connected to one of the multiple pixel driving circuits 101. For example, one voltage control circuit 110 is connected to a pixel driving circuit 101 in one display row, the first poles of the driving transistors in the pixel driving circuit 101 of that display row are jointly connected to the voltage control circuit 110, the second pole of each driving transistor is connected to the anode of the light-emitting device 102 of that subpixel, and the cathode of the light-emitting device 102 is connected to the input terminal of the second power supply signal VSS. The voltage control circuits 110 are connected to the input terminals of the first power supply signal VDD, the initialization signal Vinit, the reset control signal RE, and the light emission control signal EM, respectively. The voltage control circuit 110 is configured to output an initialization signal Vinit to the first pole of the drive transistor in response to a reset control signal RE, thereby controlling the corresponding light-emitting device 102 to be reset. The voltage control circuit 110 is further configured to output a first power supply signal VDD to the first pole of the drive transistor in response to a light-emitting control signal EM, thereby driving the light-emitting device 102 to emit light. By having the pixel drive circuits 101 in one display row jointly connected to the voltage control circuit 110, the structure of the pixel drive circuits 101 in the display area can be simplified, reducing the area occupied by the pixel drive circuits 101 in the display area, and thereby allowing more pixel drive circuits 101 and light-emitting devices 102 to be installed in the display area, achieving high PPI display. The voltage control circuit 110 controls the initialization signal Vinit to the first pole of the drive transistor by controlling the reset control signal RE, thereby controlling the corresponding light-emitting device 102 to be reset, which avoids the influence of the voltage applied to the light-emitting device 102 when the previous frame emitted light on the emission of light in the next frame, and can improve the afterimage phenomenon.

[0046] In an exemplary embodiment, one voltage control circuit 110 may be connected to a pixel drive circuit 101 for two adjacent subpixels in the same display row, or it may be connected to a pixel drive circuit 101 for three or more subpixels in the same display row.

[0047] Figure 3 is a schematic diagram of the circuit implementation of a voltage control circuit and a pixel driving circuit according to an exemplary embodiment. As shown in Figure 3, the light-emitting device may include an OLED. The anode of the OLED is connected to the second electrode D of the driving transistor M0, and the cathode of the OLED is connected to the input terminal of the second power supply signal VSS.

[0048] In an exemplary embodiment, the voltage of the second power supply signal VSS is a negative voltage or the ground voltage V GND (Generally, this may be 0V). The voltage of the initialization signal Vinit is the ground voltage V GND That's fine.

[0049] In the exemplary embodiment, the OLED may be a Micro-OLED or Mini-OLED, which helps to achieve high PPI display.

[0050] In an exemplary embodiment, the voltage control circuit 110 is connected to two pixel driving circuits 101 in one display row. Each pixel driving circuit 101 comprises a driving transistor M0, a third transistor M3, a fourth transistor M4, and a storage capacitor Cst, while the voltage control circuit 110 comprises a first transistor M1 and a second transistor M2. The driving transistors M0, M1, M2, M3, and M4 are all transistors manufactured on a base substrate.

[0051] The control electrode of the first transistor M1 is connected to the input terminal of the reset control signal RE and is used to receive the reset control signal RE. The first pole of the first transistor M1 is connected to the input terminal of the initialization signal Vinit and is used to receive the initialization signal Vinit. The second pole of the first transistor M1 is connected to the first pole S of the corresponding drive transistor M0 and the second pole of the second transistor M2, respectively. The control electrode of the second transistor M2 is connected to the input terminal of the light emission control signal EM and is used to receive the light emission control signal EM. The first pole of the second transistor M2 is connected to the input terminal of the first power supply signal VDD and is used to receive the first power supply signal VDD. The second pole of the second transistor M2 is connected to the first pole S of the corresponding drive transistor M0 and the second pole of the first transistor M1, respectively. In exemplary embodiments, the types of the first transistor M1 and the second transistor M2 may be different. For example, the first transistor M1 may be an N-type transistor and the second transistor M2 may be a P-type transistor, or the first transistor M1 may be a P-type transistor and the second transistor M2 may be an N-type transistor. In some possible implementations, the types of the first transistor M1 and the second transistor M2 may be the same, and may be designed and determined according to the actual application environment.

[0052] The pixel driving circuit 101 includes a driving transistor M0, a third transistor M3, a fourth transistor M4, and a storage capacitor Cst. The control electrode G of the driving transistor M0 and the first electrode S of the driving transistor M0 are connected to the second electrode of the first transistor M1 and the second electrode of the second transistor M2, and the second electrode D of the driving transistor M0 is connected to the anode of the OLED. The control electrode of the third transistor M3 is connected to the input terminal of the first control electrode scanning signal S1 and is used to receive the first control electrode scanning signal S1. The first electrode of the third transistor M3 is connected to the input terminal of the data signal DA and is used to receive the data signal DA. The second electrode of the third transistor M3 is connected to the control electrode G of the driving transistor M0. The control electrode of the fourth transistor M4 is connected to the input terminal of the second control electrode scanning signal S2 and is used to receive the second control electrode scanning signal S2. The first electrode of the fourth transistor M4 is connected to the input terminal of the data signal DA and is used to receive the data signal DA. The second electrode of the fourth transistor M4 is connected to the control electrode G of the driving transistor M0. The first terminal of the energy storage capacitor Cst is connected to the control electrode G of the drive transistor M0, and the second terminal of the energy storage capacitor Cst is connected to the ground terminal GND. In an exemplary embodiment, the drive transistor M0 may be an N-type transistor, and the types of the third transistor M3 and the fourth transistor M4 may be different, for example, the third transistor M3 is an N-type transistor and the fourth transistor M4 is a P-type transistor. When the voltage of the data signal DA is a voltage corresponding to a high grayscale, the data signal DA is transmitted to the control electrode G of the drive transistor M0 by turning on the P-type fourth transistor M4, thereby preventing the voltage of the data signal DA from being affected by, for example, the threshold voltage of the N-type third transistor M3. When the voltage of the data signal DA is a voltage corresponding to a low grayscale, the data signal DA is transmitted to the control electrode G of the drive transistor M0 by turning on the N-type third transistor M3, thereby preventing the voltage of the data signal DA from being affected by the threshold voltage of the P-type fourth transistor M4. This allows for a wider voltage range to be input to the control electrode G of the drive transistor M0.

[0053] In the exemplary embodiment, regarding the types of the third transistor M3 and the fourth transistor M4, the third transistor M3 may be a P-type transistor, and the fourth transistor M4 may be an N-type transistor.

[0054] In exemplary embodiments, the pixel driving circuit may be a 3T1C, 5T1C, or 7T1C circuit structure, or a circuit structure having an internal compensation or external compensation function.

[0055] In an exemplary embodiment, as shown in Figure 1, the array structure layer further comprises a first insulating layer 12 located on the side of the transistor 11 away from the base substrate 10, and a second insulating layer 15 located on the side of the first insulating layer 12 away from the base substrate 10.

[0056] A first via is installed in the first insulating layer 12, and the first conductive pillar 13 is installed inside the first via. A second via is installed in the second insulating layer 15, and the second conductive pillar 16 is installed inside the second via.

[0057] In an exemplary embodiment, the transistor 11 comprises an active layer, a gate electrode, a source electrode, a drain electrode, and a gate connection electrode. The source electrode and the drain electrode are each connected to the active layer, and the gate connection electrode is connected to the gate electrode by a conductive pillar. The transistor may have a bottom gate structure or a top gate structure.

[0058] In exemplary embodiments, the manufacturing materials for the first insulating layer 12 and the second insulating layer 15 may be silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). The structure of the first insulating layer 12 and the second insulating layer 15 may be a single-layer structure or a multilayer composite structure.

[0059] In exemplary embodiments, the manufacturing material for the first conductive pillar 13 and the second conductive pillar 16 may be tungsten.

[0060] In exemplary embodiments, the manufacturing material for the connecting electrode 14 may be silver or aluminum. The structure of the connecting electrode 14 may be a single-layer structure or a multi-layer composite structure.

[0061] Figure 4 is a schematic diagram of the structure of an organic light-emitting layer according to an exemplary embodiment. As shown in Figure 4, the organic light-emitting layer according to the exemplary embodiment comprises a first light-emitting sublayer 331, a first charge generation layer 332, a second light-emitting sublayer 333, a second charge generation layer 334, and a third light-emitting sublayer 335 that are sequentially laminated between the anode and the cathode.

[0062] The first light-emitting sublayer 331 is used to emit first-color light and comprises a first hole transport layer (HTL) 3311, a first light-emitting material layer (EML) 3312, and a first electron transport layer (ETL) 3313, which are stacked sequentially. The second light-emitting sublayer 333 is used to emit second-color light and comprises a second hole transport layer 3331, a second light-emitting material layer 3332, and a second electron transport layer 3333, which are stacked sequentially. The third light-emitting sublayer 335 is used to emit third-color light and comprises a third hole transport layer 3351, a third light-emitting material layer 3352, and a third electron transport layer 3353, which are stacked sequentially. The first charge generation layer 332 is installed between the first light-emitting sublayer 331 and the second light-emitting sublayer 333 and is used to connect the two light-emitting sublayers in series to realize carrier transfer. The second charge generation layer 334 is installed between the second light-emitting sublayer 333 and the third light-emitting sublayer 335, and is used to connect the two light-emitting sublayers in series to realize carrier transfer. The organic light-emitting layer comprises a first light-emitting material layer that emits a first color of light, a second light-emitting material layer that emits a second color of light, and a third light-emitting material layer that emits a third color of light, so the light ultimately emitted by the organic light-emitting layer is mixed light. For example, the first light-emitting material layer can be set to be a red light material layer that emits red light, the second light-emitting material layer can be set to be a green light material layer that emits green light, and the third light-emitting material layer can be set to be a blue light material layer that emits blue light, so the organic light-emitting layer ultimately emits white light.

[0063] When actually implementing the design, the structure of the organic light-emitting layer can be designed according to the actual needs. In each light-emitting sublayer, a hole injection layer and an electron injection layer may be added to improve the efficiency of injecting electrons and holes into the light-emitting material layer. To simplify the structure of the organic light-emitting layer, the first electron transport layer 3313, the first charge generation layer 332, and the second hole transport layer 3331 may be canceled, meaning that the second light-emitting material layer 3332 may be directly installed on the first light-emitting material layer 3312.

[0064] In an exemplary embodiment, the organic light-emitting layer may consist of an organic light-emitting layer that emits a first color of light and an organic light-emitting layer that emits complementary light to the first color of light. These two organic light-emitting layers are sequentially laminated on a base substrate, thereby emitting white light as a whole.

[0065] In the exemplary embodiment, the second electrode 23 may be a planar electrode.

[0066] In an exemplary embodiment, the second electrode 23 is a transmission electrode and is used to transmit light emitted from the organic light-emitting layer 22. The light emitted from the organic light-emitting layer 22 includes light emitted by the organic light-emitting layer 22 to the second electrode 23 and light emitted by the organic light-emitting layer 22 to the first electrode 21 and reflected by the first electrode 21.

[0067] In exemplary embodiments, the material used to manufacture the second electrode 23 may be indium tin oxide or zinc tin oxide, or other transparent conductive material.

[0068] In an exemplary embodiment, the orthographic projection of the first electrode 21 on the base substrate 10 covers the orthographic projection of the organic light-emitting layer 22 on the base substrate 10, i.e., the size of the first electrode 21 is larger than the size of the organic light-emitting layer 22, thereby improving the display brightness of the display panel.

[0069] In an exemplary embodiment, the orthographic projection of the first sub-electrode 211 on the base substrate 10 covers the orthographic projection of the organic light-emitting layer 22 on the base substrate 10, meaning that the size of the first sub-electrode 211 is larger than the size of the organic light-emitting layer 22, thereby allowing the first sub-electrode 211 to reflect a large amount of light emitted from the organic light-emitting layer 22 to the first sub-electrode 211, thereby improving the reflection efficiency of the first sub-electrode.

[0070] In an exemplary embodiment, the threshold reflectance may be 80%.

[0071] The display panel according to the embodiment of the present disclosure comprises a base substrate and an array structure layer and an emissive structure layer sequentially installed on the base substrate, the base substrate comprising a transistor, the array structure layer comprising a first conductive pillar, a connecting electrode and a second conductive pillar sequentially installed, the emissive structure layer comprising a first electrode, an organic emissive layer and a second electrode, the first electrode located on the side of the organic emissive layer adjacent to the base substrate, the second electrode located on the side of the organic emissive layer away from the base substrate, the first electrode comprising a first sub-electrode, a second sub-electrode and a third sub-electrode, the second sub-electrode located on the side of the first sub-electrode away from the base substrate, the third sub-electrode located on the side of the first sub-electrode adjacent to the base substrate, the reflectance of the first sub-electrode being greater than the threshold reflectance and greater than the reflectance of the second sub-electrode, the reflectance of the second sub-electrode being less than the reflectance of the third sub-electrode, the first electrode being connected to the connecting electrode by the second conductive pillar, and the connecting electrode being connected to the drain electrode of the transistor by the first conductive pillar. In the invention relating to the embodiment of this disclosure, the first electrode comprises a first sub-electrode, a second sub-electrode, and a third sub-electrode, the reflectance of which is greater than the threshold reflectance. This improves the reflectance of the first electrode, further improves the display brightness of the silicon-based OLED, and enhances the display effect of the silicon-based OLED.

[0072] In an exemplary embodiment, as shown in Figure 1, the orthographic projection of the second sub-electrode 212 on the base substrate 10 covers the orthographic projection of the first sub-electrode 211 on the base substrate 10, i.e., the size of the second sub-electrode 212 is larger than the size of the first sub-electrode 211. The second sub-electrode 212 surrounds the first sub-electrode 211, thereby preventing the first sub-electrode from being damaged and having its reflectivity reduced by the subsequent film manufacturing process of the second sub-electrode, improving the performance of the first sub-electrode, and further protecting the first sub-electrode 211.

[0073] In an exemplary embodiment, the display panel further comprises a plurality of gate lines and a plurality of data lines mounted on a base substrate. The gate lines and data lines intersect vertically and horizontally.

[0074] In an exemplary embodiment, the orthographic projection of the third sub-electrode 213 on the base substrate 10 covers at least the orthographic projection of the first sub-electrode 211 on the base substrate 10, and the orthographic projection of the second sub-electrode 212 on the base substrate 10 covers the orthographic projection of the third sub-electrode 213 on the base substrate 10.

[0075] In exemplary embodiments, the projection area of ​​the third sub-electrode 213 on the base substrate 10 and the projection area of ​​the first sub-electrode 211 on the base substrate 10 may be equal, or the projection area of ​​the third sub-electrode 213 on the base substrate 10 may be larger than the projection area of ​​the first sub-electrode 211 on the base substrate 10.

[0076] In an exemplary embodiment, the length of the first sub-electrode 211 along the first direction A1 is greater than the length of the second sub-electrode 212 along the first direction A1, and the length of the first sub-electrode 211 along the second direction A2 is less than the length of the second sub-electrode 212 along the second direction A2.

[0077] In an exemplary embodiment, the length of the second sub-electrode 212 along the second direction A2 is 1.2 times the length of the first sub-electrode 211 along the second direction A2, ensuring that the second sub-electrode completely covers the first sub-electrode.

[0078] In an exemplary embodiment, as shown in Figure 1, the first direction A1 is perpendicular to the base substrate 10, and the second direction A2 is the direction in which the gate lines extend.

[0079] In the exemplary embodiment, since a second sub-electrode 212 is present, the manufacturing material of the first sub-electrode 211 may include silver, thereby allowing the reflectivity of the first electrode 21 to be 95%, and significantly improving the reflectivity of the first electrode.

[0080] In exemplary embodiments, the length of the first sub-electrode 211 along the first direction A1 is 400 angstroms to 600 angstroms, or the length of the first sub-electrode 211 along the first direction A1 may vary by ±10%. In exemplary embodiments, the length of the first sub-electrode 211 along the first direction A1 is 500 angstroms.

[0081] In exemplary embodiments, the length of the first sub-electrode 211 along the second direction A2 is 1.5 micrometers to 2.5 micrometers, or the length of the first sub-electrode 211 along the second direction A2 may vary by ±20%. In exemplary embodiments, the length of the first sub-electrode 211 along the second direction A2 is 2 micrometers.

[0082] In the exemplary embodiment, the reflectivity of the first sub-electrode 211 increases with increasing length along the first direction A1 of the first sub-electrode 211.

[0083] In exemplary embodiments, the manufacturing material for the second sub-electrode 212 may include indium tin oxide.

[0084] In the exemplary embodiment, the work function of the second sub-electrode 212 is greater than 5, and the light transmittance of the second sub-electrode 212 is greater than 99%, so that it can be matched to the energy level in the organic light-emitting layer, enabling better injection of holes into the organic light-emitting layer and reducing power loss of the display panel.

[0085] In exemplary embodiments, the length of the second sub-electrode 212 along the first direction A1 is 120 angstroms to 180 angstroms, or the length of the second sub-electrode 212 along the first direction A1 may vary by ±20%. In exemplary embodiments, the length of the second sub-electrode 212 along the first direction A1 is 150 angstroms.

[0086] In exemplary embodiments, the length of the second sub-electrode 212 along the second direction A2 is 1.8 micrometers to 4 micrometers, or the length of the second sub-electrode 212 along the second direction A2 may vary by ±20%. In exemplary embodiments, the length of the second sub-electrode 212 along the second direction A2 is 2.4 micrometers.

[0087] Because steps exist when the second sub-electrode 212 forms a film on the edge of the first sub-electrode 211, in the exemplary embodiment, the length of the second sub-electrode 212 along the first direction is such that the second sub-electrode 212 forms a film on the edge of the first sub-electrode 211. First sub-electrode 211 This allows the first sub-electrode 211 to be enclosed and secured, preventing oxidation corrosion and subsequent failure, and extending the service life of the first electrode.

[0088] In exemplary embodiments, the manufacturing material for the third sub-electrode 213 includes titanium.

[0089] In exemplary embodiments, the length of the third sub-electrode along the first direction A1 is 80 angstroms to 120 angstroms, or the length of the third sub-electrode along the first direction A1 may vary by ±20%. In exemplary embodiments, the length of the third sub-electrode along the first direction A1 is 100 angstroms.

[0090] In exemplary embodiments, the length of the third sub-electrode along the second direction A2 is 1.5 micrometers to 2.5 micrometers, or the length of the third sub-electrode along the second direction A2 may vary by ±20%. In exemplary embodiments, the length of the third sub-electrode along the second direction A2 is 2 micrometers.

[0091] In exemplary embodiments, the manufacturing material for the first sub-electrode 211 contains silver, the manufacturing material for the second sub-electrode 212 contains indium tin oxide, and the manufacturing material for the third sub-electrode 213 contains titanium.

[0092] In an exemplary embodiment, as shown in Figure 1, the display panel according to the exemplary embodiment further comprises a pixel definition layer 24 for defining pixel regions. The pixel definition layer 24 is located on the side away from the base substrate 10 of the array structure layer.

[0093] In exemplary embodiments, the manufacturing material for the pixel definition layer 24 may include silicon dioxide.

[0094] Figure 5 is a schematic diagram of the structure of a display panel according to another exemplary embodiment. As shown in Figure 5, the display panel according to the exemplary embodiment further comprises a package layer 25 and a color film layer 30.

[0095] The package layer 25 is located on the side of the light-emitting structure layer 20 away from the base substrate 10 and is configured to block water vapor and oxygen, while the color film layer 30 is located on the side of the package layer 25 away from the base substrate 10.

[0096] In an exemplary embodiment, as shown in Figure 5, the package layer 25 comprises a first inorganic package layer 251, a second inorganic package layer 252, and a third organic package layer 253.

[0097] The first inorganic package layer 251 is located on the side of the second inorganic package layer 252 that is close to the base substrate 10, and the third organic package layer 253 is located on the side of the second inorganic package layer 252 that is away from the base substrate 10.

[0098] In exemplary embodiments, the manufacturing material for the first inorganic package layer 251 may include silicon nitride. The first inorganic package layer can avoid damaging the light-emitting structure layer when manufacturing the second inorganic package layer. Because the first inorganic package layer 251 has inorganic properties, it not only has excellent packaging properties but also excellent adhesion to the second electrode, ensuring the packaging effect of the package layer.

[0099] In exemplary embodiments, the manufacturing material for the second inorganic packaging layer 252 may include aluminum oxide. The second inorganic packaging layer 252 can prevent water vapor and oxygen from entering the luminescent structure layer, thereby extending the service life of the luminescent structure layer.

[0100] In an exemplary embodiment, the length of the second inorganic package layer 252 along the first direction A1 is greater than the length of the first inorganic package layer 251 along the first direction A1.

[0101] In exemplary embodiments, the manufacturing material for the third organic packaging layer 253 may include poly-P-xylene. Because the third organic packaging layer 253 has organic properties, it not only has relatively excellent organic packaging properties but also relatively excellent particle coating ability, which allows it to effectively coat particles in the film layer and prevent them from penetrating the film layer. Furthermore, materials with organic properties effectively release stress between inorganic layers, preventing defects such as microcracks or peeling from occurring in the film layer due to relatively large stresses. The third organic packaging layer 253 also has relatively high flatness, providing a relatively flat base substrate for the subsequent color film layer manufacturing process and preventing damage to the second inorganic packaging layer during the color film layer manufacturing process.

[0102] In an exemplary embodiment, the color film layer 30 is installed on the package layer 25, and the color film layer 30 achieves full-color display using a method that combines white light and color film. The color film layer 30 includes at least a first-color optical filter, a second-color optical filter, and a third-color optical filter corresponding to subpixels. In an exemplary embodiment, the first-color optical filter may be a green (G) optical filter, the second-color optical filter may be a red (R) optical filter, and the third-color optical filter may be a blue (B) optical filter.

[0103] In exemplary embodiments, the color film layer 30 may further comprise a white optical filter or an optical filter of another color.

[0104] In exemplary embodiments, the color film layer 30 may further comprise a black matrix.

[0105] In an exemplary embodiment, a method combining white light and color film can be used to achieve a resolution greater than 2000, satisfying VR / AR needs.

[0106] Figure 6 is a schematic diagram of the structure of a display panel according to another exemplary embodiment. As shown in Figure 6, the display panel according to the exemplary embodiment further comprises a cover plate 40, the cover plate 40 located on the side of the color film layer 30 away from the base substrate 10.

[0107] In exemplary embodiments, the cover plate may be a glass cover plate. The cover plate 40 and the base substrate 10 are fixed together with a sealant (not shown). The cover plate can serve to protect the color film layer 30.

[0108] In an exemplary embodiment, the sealant is placed between the base substrate and the cover plate, providing assurance to prevent the ingress of water vapor and oxygen, thereby significantly extending the lifespan of the silicon-based OLED display panel. In another exemplary embodiment, the sealant may be placed on the side of the cover plate, sealing the space between the side of the cover plate and the base substrate, with the end face of the sealant away from the base substrate positioned between the surface of the cover plate adjacent to the base substrate and the surface of the cover plate away from the base substrate. This not only ensures a sealing effect but also prevents an increase in the thickness of the display panel due to the sealant being higher than the cover plate.

[0109] Figure 7 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure. As shown in Figure 7, the embodiment of the present disclosure further provides a method for manufacturing a display panel, which can be used to manufacture a display panel according to any one of the above embodiments, and the method for manufacturing a display panel according to an embodiment of the present disclosure includes the following steps.

[0110] Step 100: A transistor is formed inside the base substrate, and An array structure layer is formed on the base substrate.

[0111] The base substrate comprises a transistor. The transistor comprises an active layer, a gate electrode, a source electrode, a drain electrode, and a gate connection electrode. The source electrode and drain electrode are connected to the active layer, respectively, and the gate connection electrode is connected to the gate electrode by a conductive pillar. The transistor may have a bottom gate structure or a top gate structure.

[0112] Step 200: A first electrode is formed on the side of the array structure layer away from the base substrate, comprising a first sub-electrode, a second sub-electrode, and a third sub-electrode.

[0113] Step 300: An organic light-emitting layer is formed on the side of the first electrode that is away from the base substrate.

[0114] Step 400: A second electrode is formed on the side of the organic light-emitting layer away from the base substrate, thereby forming a light-emitting structure layer comprising the first electrode, the organic light-emitting layer, and the second electrode.

[0115] The method for manufacturing the display panel in the embodiments of this disclosure is used to manufacture the display panel according to any one of the embodiments described above, and since the implementation principle and effect are similar, a detailed explanation is omitted here.

[0116] In an exemplary embodiment, step 100 includes forming a transistor on a base substrate, forming a first insulating layer on the base substrate on which the transistor is formed, forming a first conductive pillar within the first via, forming a connecting electrode on the first insulating layer, forming a second insulating layer on the first insulating layer on which the connecting electrode is formed, forming a second conductive pillar within the second via.

[0117] In an exemplary embodiment, step 200 includes sequentially applying an anti-reflective thin film and a photoresist to the side of the array structure layer away from the base substrate; performing exposure and development treatment on the anti-reflective thin film and photoresist; sequentially depositing a first metal thin film and a second metal thin film on the anti-reflective thin film and photoresist after exposure treatment; immersing the base substrate on which the first metal thin film and the second metal thin film are deposited in a stripping solution to strip the photoresist; developing the base substrate after the photoresist has been stripped to strip the anti-reflective thin film and form a third sub-electrode and a first sub-electrode; and forming a second sub-electrode on the side of the first sub-electrode away from the base substrate.

[0118] In an exemplary embodiment, forming a second sub-electrode on the side of the first sub-electrode away from the base substrate includes: depositing a transparent conductive thin film on the side of the first sub-electrode away from the base substrate by a sputtering process; applying a photoresist to the transparent conductive thin film; performing exposure and development treatments on the photoresist; etching the transparent conductive thin film by a dry etching process; peeling off the photoresist to form the second sub-electrode; and ensuring that the orthogonal projection of the second sub-electrode on the base substrate covers the orthogonal projection of the first sub-electrode on the base substrate.

[0119] In this exemplary embodiment, the accuracy of the second sub-electrode can be ensured by forming the second sub-electrode by dry etching.

[0120] In an exemplary embodiment, the interval between the start time for depositing a transparent conductive thin film by sputtering on the side of the first sub-electrode away from the base substrate and the end time for immersing the base substrate on which the first and second metal thin films are deposited in a stripping solution to remove the photoresist is shorter than 120 minutes, thereby avoiding oxidative corrosion of the first sub-electrode.

[0121] In an exemplary embodiment, the method for manufacturing a display panel further includes cleaning the base substrate on which the array structure layer is installed, before sequentially applying the anti-reflective thin film and photoresist to the side of the array structure layer away from the base substrate.

[0122] In an exemplary embodiment, after exposure and development treatment of the anti-reflective thin film and photoresist, the method for manufacturing the display panel further includes removing dust adhering to the base substrate on which the anti-reflective thin film and photoresist are deposited.

[0123] In exemplary embodiments, applying an anti-reflective thin film before applying the photoresist can broaden the window of the photolithography process and improve width control of the photolithography strip.

[0124] In an exemplary embodiment, after exposure of the anti-reflective thin film and photoresist, grooves are formed by the anti-reflective thin film and photoresist. The grooves include a first groove formed in the anti-reflective thin film and a second groove formed in the photoresist, and the orthographic projection of the first groove on the base substrate covers the orthographic projection of the second groove on the base substrate, i.e., the grooves formed by the anti-reflective thin film and photoresist have an undercut structure.

[0125] In the exemplary embodiment, the first metal thin film is not etched during the manufacturing process for forming the first sub-electrode. Therefore, the first sub-electrode is not damaged by the etching process, and the precision of the first sub-electrode can be ensured to satisfy the requirements of silicon-based OLEDs. Accordingly, in the exemplary embodiment, the manufacturing material for the second metal thin film may be silver, and since the reflectivity of silver can reach 95%, the reflectivity of the first sub-electrode can be improved.

[0126] In exemplary embodiments, the material used to manufacture the first metal thin film may be titanium.

[0127] In exemplary embodiments, the immersion time of the base substrate on which the first and second metal thin films are deposited in the stripping solution is shorter than 30 minutes, thereby avoiding damage to the second metal thin film by the stripping solution, and damage to the second metal thin film includes agglomeration damage or shrinkage of the second metal thin film.

[0128] In an exemplary embodiment, prior to step 300, the method for manufacturing the display panel further includes depositing a pixel definition thin film on the side of the first electrode away from the base substrate, applying a photoresist to the pixel definition thin film, performing exposure and development treatment on the photoresist, etching the pixel definition thin film by a dry etching process, and peeling off the photoresist to form a pixel definition layer.

[0129] In an exemplary embodiment, after step 400, the method for manufacturing the display panel further includes forming a package layer on the side of the second electrode away from the base substrate, forming a color film layer on the side of the package layer away from the base substrate, and forming a cover plate on the side of the color film layer away from the base substrate.

[0130] The structure of a display panel will be described below with reference to Figures 8 to 23, using an example of the manufacturing process of a display panel. In this disclosure, the “patterning process” includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping. Deposition may be performed using one or more of sputtering, vapor deposition, and chemical vapor deposition, and coating may be performed using one or more of spray and spin coating. A “thin film” refers to a single thin film produced by a deposition or coating process of a material on a base substrate. If the “thin film” does not require a patterning process throughout the entire manufacturing process, the “thin film” may further be referred to as a “layer.” If the “thin film” requires a patterning process throughout the entire manufacturing process, it is referred to as a “thin film” before the patterning process and as a “layer” after the patterning process. A “layer” after the patterning process includes at least one “pattern.”

[0131] Step S1: A base board 10 is provided, which includes a transistor 11. The transistor constitutes a pixel driving circuit. As shown in Figure 8, the base board 10 includes a plurality of subpixels, and each subpixel includes one pixel driving circuit.

[0132] In an exemplary embodiment, the display panel comprises a display area and a non-display area, with subpixels located in the display area. Figure 8 shows three subpixels in the display area, namely the first subpixel 100A, the second subpixel 100B, and the third subpixel 100C, and a transistor 11 included in the pixel driving circuit. After manufacturing is complete, the source and drain electrodes of the display area are exposed on the surface of the base substrate 10.

[0133] Step S2: A first insulating thin film is deposited on the base substrate 10, and the first insulating thin film is patterned by a patterning process to form a first insulating layer 12 that covers the base substrate 10. Multiple first vias are formed in the first insulating layer 12, and each of the multiple first vias exposes the drain electrode of each subpixel. Subsequently, a first conductive pillar 13 is formed inside the first vias, and the first conductive pillar 13 is connected to the drain electrode of each subpixel. A conductive thin film is deposited on the first insulating layer 12, and the conductive thin film is patterned by a patterning process to form a connecting electrode 14 that is connected to the first conductive pillar 13. As shown in Figure 9, a second insulating thin film is deposited on the connecting electrode 14, and the second insulating thin film is patterned by a patterning process to form a second insulating layer 15 that covers the base substrate. Multiple second vias are formed in the second insulating layer 15, each of which exposes the connecting electrode 14. A second conductive pillar 16 connected to the connecting electrode 14 is formed inside the second via, thereby forming an array structure layer.

[0134] Step S3: As shown in Figure 10, the anti-reflective thin film 200A and the photoresist 200B are sequentially applied to the array structure layer.

[0135] In exemplary embodiments, the anti-reflective thin film manufacturing material may be an organic or inorganic material. By applying a single layer of anti-reflective thin film before applying the photoresist, the window of the photolithography process can be expanded, and the objective of improving width control of the photolithography strip can be achieved.

[0136] Step S4: As shown in Figure 11, the anti-reflective thin film 200A and the photoresist 200B are exposed by transmitting ultraviolet light through the first mask M1.

[0137] Step S5: As shown in Figure 12, the anti-reflective thin film 200A and photoresist 200B after exposure are developed, and then the base substrate is dust-removed.

[0138] Undercut grooves are formed in the anti-reflective thin film 200A and the photoresist 200B after development. The grooves include a first groove formed in the anti-reflective thin film 200A after exposure and a second groove formed in the photoresist 200B after exposure, and the orthographic projection of the first groove on the base substrate 10 covers the orthographic projection of the second groove on the base substrate 10.

[0139] Step S6: As shown in Figure 13, the first metal thin film 210A and the second metal thin film 210B are sequentially deposited on the anti-reflective thin film 200A and photoresist 200B after exposure treatment.

[0140] Step S7: As shown in Figure 14, the base substrate 10 on which the first metal thin film 210A and the second metal thin film 210B are deposited is immersed in a stripping solution to remove the photoresist 200B, and the immersion time is less than 30 minutes.

[0141] If the immersion time in the stripping solution is relatively long, the second metal thin film 210B may be damaged and aggregated, causing the second metal thin film 210B to detach from the surface of the first metal thin film 210A, or the second metal thin film 210B to shrink.

[0142] Step S8: As shown in Figure 15, the anti-reflective thin film 200A is developed and peeled off to form the third sub-electrode 213 and the first sub-electrode 211.

[0143] Step S9: As shown in Figure 16, a transparent conductive thin film 210C is deposited on the base substrate on which the first sub-electrode 211 is formed by a sputtering process.

[0144] The time interval between the end of step S7 and the start of step S9 is shorter than 120 minutes, thereby preventing the first sub-electrode 211 from oxidizing and corroding, causing it to turn black.

[0145] Step S10: As shown in Figure 17, a photoresist 200B is applied to the transparent conductive thin film 210C, and the photoresist 200B is exposed by transmitting ultraviolet light through the second mask M2.

[0146] Step S11: As shown in Figure 18, the photoresist 200B after exposure treatment is developed, the transparent conductive thin film 210C is etched by a dry etching process, and the photoresist is peeled off to form a second sub-electrode 212, thereby forming the first electrode 21.

[0147] Step S12: As shown in Figure 19, a pixel-defining thin film 240 is deposited on the base substrate on which the first electrode is formed by a plasma-accelerated chemical vapor deposition (PECVD) process.

[0148] Step S13: As shown in Figure 20, the photoresist 200B is applied to the pixel definition thin film 240, and the photoresist 200B is exposed by transmitting ultraviolet light through the second mask M3.

[0149] Step S14: As shown in Figure 21, the photoresist 200B after exposure treatment is developed, the pixel definition thin film 240 is etched by a dry etching process, and the photoresist is peeled off to form the pixel definition layer 24.

[0150] In each subpixel, a pixel aperture is created in the pixel definition layer 24, and the surface of the first electrode 21 is exposed in the pixel aperture.

[0151] Step S15: As shown in Figure 22, the organic light-emitting layer 22 and the second electrode 23 are sequentially formed on the base substrate on which the pixel definition layer is formed.

[0152] In each subpixel, the organic light-emitting layer 22 is electrically connected to the first electrode 21, and the second electrode 23 is electrically connected to the organic light-emitting layer 22.

[0153] In step S16, as shown in Figure 23, the first package film is deposited on the second electrode 23, and the first package film is patterned by a patterning process. First inorganic package layer 251 Forming, First inorganic package layer 251 The second package film is deposited on top, and the second package film is patterned by a patterning process. Second inorganic package layer 252 Forming, Second inorganic package layer 252 The third package film is applied to the material, and the third package film is patterned by the masking, exposure, and development processes. Third organic packaging layer 253 This forms a layer, thereby creating the package layer 25.

[0154] Step S17: As shown in Figure 5, a color film layer 30 is formed on the side of the package layer 25 that is away from the base substrate.

[0155] In an exemplary embodiment, the color film layer 30 includes a first-color optical filter, a second-color optical filter, and a third-color optical filter corresponding to subpixels.

[0156] In exemplary embodiments, the first optical filter may be a green (G) optical filter, the second optical filter may be a red (R) optical filter, and the third optical filter may be a blue (B) optical filter. In some possible implementations, the manufacturing process of the color film layer 30 includes first forming a blue (B) optical filter, then a red (R) optical filter, and then a green (G) optical filter. The blue optical filter has relatively high tackiness, and forming the blue optical filter first can reduce the likelihood of the color film layer 30 peeling off from the film in contact with the color film layer. The red optical filter has relatively low tackiness but high fluidity, so in the process of forming the red optical filter R, the number of bubbles on the surface away from the second electrode of the blue and red optical filters can be reduced, thereby improving the uniformity of the film thickness at the overlapping position of both the blue and red optical filters. Since the substrate material of the green optical filter and the substrate material of the red optical filter are almost the same, the adhesive force between the green optical filter and the red optical filter is relatively large, which reduces the possibility of the color film layer 30 peeling off from the second electrode. In some possible implementations, the color film layer 30 may include optical filters of other colors, such as white or yellow.

[0157] Step S18: As shown in Figure 6, the cover plate 40 is formed by a sealing process, and the cover plate 40 and the base substrate 10 are fixed together with sealant (not shown).

[0158] The embodiments of this disclosure further provide an electronic device comprising a display panel according to any one of the embodiments described above.

[0159] In exemplary embodiments, the electronic device includes a VR device or an AR device.

[0160] The drawings in this disclosure relate only to structures relating to embodiments of this disclosure; for other structures, reference may be made to conventional designs.

[0161] For clarity, the thickness and size of layers or microstructures are magnified in the drawings illustrating embodiments of the present disclosure. As can be understood, when an element such as a layer, film, region, or substrate is said to be located "above" or "below" another element, the element may be located "directly" above or below the other element, or an intermediate element may be present.

[0162] The above are embodiments disclosed herein, and are merely used to facilitate understanding of the disclosure, and are not intended to limit the disclosure. Those skilled in the art may make any modifications or changes to the embodiments and details without departing from the spirit or scope of the disclosure, but the scope of patent protection of the disclosure shall still be limited to the scope of the appended claims. [Explanation of symbols]

[0163] 10 Base substrate 20 Light-emitting structural layer 11 transistors 13 First conductive pillar 14 connecting electrodes 16. Second conductive pillar 20. Luminescent structural layer 21 1st electrode 22 Organic light-emitting layer 23 2nd electrode 211 First sub-electrode 212 Second Sub-electrode 213 Third Sub-electrode

Claims

1. It is a display panel, The device comprises a base substrate, an array structure layer and a light-emitting structure layer sequentially installed on the base substrate, the base substrate comprising a transistor installed therein, the array structure layer comprising a first conductive pillar, a connecting electrode and a second conductive pillar sequentially installed, the light-emitting structure layer comprising a first electrode, an organic light-emitting layer and a second electrode, the first electrode located on the side of the organic light-emitting layer adjacent to the base substrate and the second electrode located on the side of the organic light-emitting layer away from the base substrate. The first electrode comprises a first sub-electrode, a second sub-electrode, and a third sub-electrode, wherein the second sub-electrode is located on the side of the first sub-electrode away from the base substrate, and the third sub-electrode is located on the side of the first sub-electrode closer to the base substrate. The reflectance of the first sub-electrode is greater than the threshold reflectance and greater than the reflectance of the second sub-electrode, the reflectance of the second sub-electrode is less than the reflectance of the third sub-electrode, and the threshold reflectance is 80%. The first electrode is connected to the connecting electrode by the second conductive pillar, and the connecting electrode is connected to the drain electrode of the transistor by the first conductive pillar. A display panel in which the size of the second sub-electrode is larger than the sizes of the first sub-electrode and the third sub-electrode, and the second sub-electrode simultaneously surrounds the first sub-electrode and the third sub-electrode.

2. The second sub-electrode is a transparent electrode, and the orthographic projection on the base substrate covers the orthographic projection of the first sub-electrode on the base substrate. The display panel according to claim 1, wherein the orthographic projection of the third sub-electrode on the base substrate covers at least the orthographic projection of the first sub-electrode on the base substrate, and the orthographic projection of the second sub-electrode on the base substrate covers the orthographic projection of the third sub-electrode on the base substrate.

3. The display panel further includes gate lines, wherein the length of the first sub-electrode along the first direction is greater than the length of the second sub-electrode along the first direction, and the length of the first sub-electrode along the second direction is less than the length of the second sub-electrode along the second direction. The length of the second sub-electrode along the second direction is 1.2 times the length of the first sub-electrode along the second direction. The display panel according to claim 1, wherein the first direction is perpendicular to the base substrate and the second direction is the direction in which the gate line extends.

4. The manufacturing material for the first sub-electrode contains silver, The display panel according to claim 3, wherein the length of the first sub-electrode along the first direction is 400 angstroms to 600 angstroms, and the length of the first sub-electrode along the second direction is 1.5 micrometers to 2.5 micrometers.

5. The manufacturing material for the second sub-electrode contains indium tin oxide. The display panel according to claim 3, wherein the length of the second sub-electrode along the first direction is 120 angstroms to 180 angstroms, and the length of the second sub-electrode along the second direction is 1.8 micrometers to 4 micrometers.

6. The manufacturing material for the third sub-electrode contains titanium. The display panel according to claim 3, wherein the length of the third sub-electrode along the first direction is 80 angstroms to 120 angstroms, and the length of the third sub-electrode along the second direction is 1.5 micrometers to 2.5 micrometers.

7. The display panel according to claim 1, wherein the manufacturing material for the first sub-electrode contains silver, the manufacturing material for the second sub-electrode contains indium tin oxide, and the manufacturing material for the third sub-electrode contains titanium.

8. The display panel according to claim 1, wherein the work function of the second sub-electrode is greater than 5 electron volts (eV), and the light transmittance of the second sub-electrode is greater than 99%.

9. The display panel further comprises a pixel definition layer, a package layer, and a color film layer. The pixel definition layer is located on the side of the array structure layer away from the base substrate. The package layer is located on the side of the light-emitting structure layer that is away from the base substrate. The color film layer is located on the side of the package layer away from the base substrate, The display panel according to claim 1, wherein the manufacturing material for the pixel definition layer includes silicon dioxide.

10. The aforementioned package layer comprises a first inorganic package layer, a second inorganic package layer, and a third organic package layer. The first inorganic package layer is located on the side of the second inorganic package layer that is close to the base substrate. The display panel according to claim 9, wherein the third organic package layer is located on the side of the second inorganic package layer away from the base substrate.

11. The aforementioned display panel further includes a cover plate, The display panel according to claim 9 or 10, wherein the cover plate is located on the side of the color film layer away from the base substrate.

12. An electronic device comprising a display panel according to any one of claims 1 to 11.

13. A method for manufacturing a display panel used to manufacture a display panel according to any one of claims 1 to 11, An array structure layer is formed on the base substrate, and the base substrate is equipped with transistors installed therein. A first electrode comprising a first sub-electrode, a second sub-electrode, and a third sub-electrode is formed on the side of the array structure layer away from the base substrate, The first electrode is formed on the side away from the base substrate, This includes forming a second electrode on the side of the organic light-emitting layer away from the base substrate, thereby forming a light-emitting structure layer comprising the first electrode, the organic light-emitting layer, and the second electrode, The size of the second sub-electrode is larger than the size of the first sub-electrode, and the second sub-electrode surrounds the first sub-electrode. The size of the second sub-electrode is larger than the sizes of the first sub-electrode and the third sub-electrode, and the second sub-electrode surrounds the first sub-electrode and the third sub-electrode simultaneously; a method for manufacturing a display panel.

14. Forming a first electrode comprising a first sub-electrode, a second sub-electrode, and a third sub-electrode on the side of the array structure layer away from the base substrate is, The anti-reflective thin film and photoresist are sequentially applied to the side of the array structure layer that is away from the base substrate. Exposure and development treatments are performed on anti-reflective thin films and photoresists. The process involves sequentially depositing a first metal thin film and a second metal thin film onto the anti-reflective thin film and photoresist after exposure treatment, The process involves immersing a base substrate on which the first and second metal thin films are deposited in a stripping solution to remove the photoresist, By developing the base substrate after the photoresist has been removed, the anti-reflective thin film is removed to form the third sub-electrode and the first sub-electrode. The method according to claim 13, further comprising forming a second sub-electrode on the side of the first sub-electrode away from the base substrate.

15. The method according to claim 14, wherein the immersion time of the base substrate on which the first metal thin film and the second metal thin film are deposited in the stripping solution is less than 30 minutes.

16. Forming the second sub-electrode on the side of the first sub-electrode away from the base substrate means that A transparent conductive thin film is deposited on the side of the first sub-electrode away from the base substrate by a sputtering process, The process involves coating a transparent conductive thin film with a photoresist, The process involves exposure and development of a photoresist, Etching a transparent conductive thin film by a dry etching process, The method according to claim 14, comprising: peeling off a photoresist to form a second sub-electrode; and the orthogonal projection of the second sub-electrode on the base substrate covering the orthogonal projection of the first sub-electrode on the base substrate.

17. The method according to claim 14, wherein the interval between the start time for depositing a transparent conductive thin film by sputtering on the side of the first sub-electrode away from the base substrate and the end time for immersing the base substrate on which the first and second metal thin films are deposited in a stripping solution to remove the photoresist is less than 120 minutes.

18. Before forming the organic light-emitting layer on the side of the first electrode away from the base substrate, the method further: A pixel-defining thin film is deposited on the side of the first electrode that is away from the base substrate, Applying a photoresist to the pixel definition thin film, The process involves exposure and development of a photoresist, Etching the pixel definition thin film by a dry etching process, The method according to claim 13, which includes peeling off a photoresist to form a pixel definition layer. method.

19. After forming a second electrode on the side of the organic light-emitting layer away from the base substrate, the method further: A package layer is formed on the side of the second electrode that is away from the base substrate, A color film layer is formed on the side of the package layer that is away from the base substrate, The method according to claim 13, further comprising forming a cover plate on the side of the color film layer that is away from the base substrate.

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