Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor that can reduce a reduction in capacitance while reducing the occurrence of cracks.SOLUTION: A multilayer ceramic capacitor 1 includes a laminate 21 formed by alternately laminating a plurality of dielectric layers 4 and a plurality of internal electrode layers 5. The plurality of internal electrode layers 5 include partially thin-wall internal electrode layers 51. The partially thin-wall internal electrode layers 51 each have a thick wall part 51a and at least one thin wall part 51b. The thin wall part 51b is thinner than the thick wall part 51a in a lamination direction of the plurality of dielectric layers 4 and the plurality of internal electrode layers 5, and has a cavity 10 between the thin wall part and at least one of the adjacent two dielectric layers 4.SELECTED DRAWING: Figure 3

Description

Technical Field

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[0001] The present disclosure relates to a multilayer ceramic capacitor.

Background Art

[0002] A multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrode layers are alternately laminated. The laminate is produced by firing a laminate precursor in which a plurality of ceramic green sheets serving as dielectric layers and conductive paste layers serving as internal electrode layers are alternately laminated. In a multilayer ceramic capacitor, cracks may occur in the laminate due to differences in the shrinkage behavior between the dielectric layer and the internal electrode layer during the temperature drop process in the firing step.

[0003] Patent Document 1 discloses a multilayer ceramic capacitor that suppresses crack generation by forming a large number of through holes in the internal electrode layer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a conventional multilayer ceramic capacitor, since the internal electrode layer has a large number of through holes, the effective area of the internal electrode layer contributing to the acquisition of capacitance decreases, and the capacitance may decrease.

Means for Solving the Problems

[0006] The multilayer ceramic capacitor of this disclosure includes a laminate in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked. The plurality of internal electrode layers include a partially thin internal electrode layer. The partially thin internal electrode layer has a thick portion and at least one thin portion. The thin portion is thinner than the thick portion in the stacking direction of the plurality of dielectric layers and the plurality of internal electrode layers, and has a gap between it and at least one of two adjacent dielectric layers. [Effects of the Invention]

[0007] The multilayer ceramic capacitor of this disclosure can reduce the decrease in capacitance while reducing the occurrence of cracks. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view showing the multilayer ceramic capacitor of this embodiment. [Figure 2] Figure 1 is a perspective view showing the basic structure of a multilayer ceramic capacitor. [Figure 3] This is a cross-sectional view taken along line III-III in Figure 1. [Figure 4] This is an enlarged cross-sectional view showing section IV of Figure 3. [Figure 5] This graph shows the relationship between the number ratio of thin-walled sections and the volume value. [Modes for carrying out the invention]

[0009] Embodiments of the multilayer ceramic capacitors of this disclosure will be described below with reference to the drawings. The figures used in the following description are schematic, and the dimensional ratios, etc., shown in the drawings do not necessarily correspond to those of reality. The number of components shown in each figure (e.g., the number of dielectric layers and internal electrode layers) may not be consistent with each other. In this specification, in some drawings, a Cartesian coordinate system XYZ is defined for convenience. The X-axis direction is also referred to as the first direction or length direction. The Y-axis direction is also referred to as the second direction or width direction. The Z-axis direction is also referred to as the third direction, height direction, or stacking direction.

[0010] Figure 1 is a perspective view showing the multilayer ceramic capacitor of this embodiment, Figure 2 is a perspective view showing the basic structure of the multilayer ceramic capacitor of Figure 1, Figure 3 is a cross-sectional view taken along the line III-III in Figure 1, Figure 4 is an enlarged cross-sectional view showing part IV in Figure 3, and Figure 5 is a graph showing the relationship between the number ratio of thin-walled parts and the capacitance value.

[0011] The multilayer ceramic capacitor 1 of this embodiment includes a laminate 21, as shown in Figures 1 to 3, for example. The laminate 21 has a substantially rectangular parallelepiped shape. The laminate 21 has a first face 7a and a second face 7b facing each other in a third direction, a first end face 8a and a second end face 8b facing each other in a first direction, and a first side face 9a and a second side face 9b facing each other in a second direction. The first face 7a and the second face 7b may be perpendicular to the third direction. The first end face 8a and the second end face 8b may be perpendicular to the first direction. The first side face 9a and the second side face 9b may be perpendicular to the second direction. Hereinafter, the first face 7a and the second face 7b may be collectively referred to as the main face 7a and 7b, the first end face 8a and the second end face 8b may be collectively referred to as the end face 8a and 8b, and the first side face 9a and the second side face 9b may be collectively referred to as the side face 9a and 9b.

[0012] The laminate 21 is constructed by alternately stacking multiple dielectric layers 4 and multiple internal electrode layers 5 in a third direction (stacking direction).

[0013] The dielectric layer 4 is composed of an insulating material. The dielectric layer 4 may be composed of a ceramic material mainly composed of, for example, BaTiO3 (barium titanate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), or BaZrO3 (barium zirconate). In this specification, "main component" refers to the component with the highest proportion in the material or component of interest. The proportion may be expressed as concentration (mol%). The dielectric layer 4 may have a thickness of, for example, 0.1 μm to 1.0 μm in the third direction, or a thickness of 0.4 μm to 0.5 μm.

[0014] The internal electrode layer 5 is made of a conductive material. The internal electrode layer 5 may be made of a metallic material mainly composed of, for example, Ni (nickel), Pd (palladium), Ag (silver), or Cu (copper). The internal electrode layer 5 may have a thickness of, for example, 0.1 μm to 1.0 μm in the third direction, or a thickness of 0.4 μm to 0.5 μm.

[0015] The internal electrode layer 5 is exposed on the first side surface 9a and the second side surface 9b. Additionally, the internal electrode layer 5 is exposed on either the first end surface 8a or the second end surface 8b, depending on its polarity.

[0016] The multilayer ceramic capacitor 1 includes a protective layer 6, as shown in Figure 2, for example. The protective layer 6 is located on the first side surface 9a and the second side surface 9b of the laminate 21. The protective layer 6 electrically insulates the internal electrode layers 5 with different polarities that are exposed on the sides 9a and 9b. The protective layer 6 also mechanically protects the edges of the internal electrode layers 5 that are exposed on the sides 9a and 9b. The laminate 21 with the protective layer 6 disposed on the sides 9a and 9b is also called the base body 2.

[0017] The protective layer 6 is made of an insulating material. The protective layer 6 may be made of a ceramic material mainly composed of, for example, BaTiO3 (barium titanate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), or BaZrO3 (barium zirconate). The protective layer 6 may be made of the same ceramic material as the ceramic material that constitutes the dielectric layer 4. The protective layer 6 may have a thickness of, for example, 5 μm to 30 μm in the second direction.

[0018] The multilayer ceramic capacitor 1 includes external electrodes 3, as shown in Figures 1 and 2, for example. The external electrodes 3 are used for electrical connection to an external substrate or external device.

[0019] The external electrodes 3 are composed of a first external electrode 31 and a second external electrode 32. The first external electrode 31 is located on the first end face 8a of the laminate 21. The first external electrode 31 is electrically connected to the internal electrode layer 5 exposed on the first end face 8a. The second external electrode 32 is located on the second end face 8b of the laminate 21. The second external electrode 32 is electrically connected to the internal electrode layer 5 exposed on the second end face 8b. The first external electrode 31 and the second external electrode 32 may be located on the main surfaces 7a, 7b, as shown in FIGS. 1 and 2, for example. Also, the first external electrode 31 and the second external electrode 32 may be located on the side surfaces 9a, 9b and cover the protective layer 6, as shown in FIG. 1, for example.

[0020] The first external electrode 31 and the second external electrode 32 may be composed of a single conductive layer or a plurality of conductive layers. In this embodiment, as shown in FIG. 3, for example, the first external electrode 31 and the second external electrode 32 are composed of an underlayer 3a and an outer layer 3b.

[0021] The underlayer 3a is in contact with the laminate 21 and is connected to the internal electrode layer 5 exposed on the end faces 8a, 8b. The underlayer 3a may be formed using a thin film formation technique such as plating, sputtering, evaporation, or a thick film formation technique such as screen printing or gravure printing. The underlayer 3a is composed of a metal material. The metal material used for the underlayer 3a may be a metal such as Ni, Cu, Ag, Pd, Au or an alloy composed of these metals.

[0022] The outer layer 3b covers the underlayer 3a. The outer layer 3b may be formed using a thin film formation technique such as electroless plating or electrolytic plating. The outer layer 3b is composed of a metal material. The metal material used for the outer layer 3b may be a metal such as Ni, Sn, Cu, Au or an alloy composed of these metals. The outer layer 3b may be composed of a single plating layer or a plurality of plating layers.

[0023] The multiple internal electrode layers 5 include, for example, a partially thin-walled internal electrode layer (hereinafter also referred to as a partially thin-walled layer) 51, as shown in Figure 2. The partially thin-walled layer 51 has a thick portion 51a and at least one thin portion 51b. The thin portion 51b is thinner in the stacking direction than the thick portion 51a. The thin portion 51b has a gap 10 between it and at least one of two adjacent dielectric layers 4 in the stacking direction.

[0024] The thin-walled portion 51b may be electrically connected to the thick-walled portion 51a. In other words, the thin-walled portion 51b may be electrically connected to the external electrode 3 via the thick-walled portion 51a. In this case, the thin-walled portion 51b can contribute to the acquisition of capacitance.

[0025] In the multilayer ceramic capacitor 1, since there is a gap 10 between the dielectric layer 4 and the internal electrode layer 5, internal stress caused by the difference in thermal expansion coefficient and Young's modulus (i.e., difference in shrinkage behavior) between the dielectric layer 4 and the internal electrode layer 5 can be relieved during the cooling process in the firing process, and as a result, the occurrence of cracks can be reduced. In addition, since the thin-walled portion 51b of the multilayer ceramic capacitor 1 can contribute to the acquisition of capacitance, the decrease in capacitance can be reduced compared to a multilayer ceramic capacitor in which the internal electrode layer 5 does not have a partially thin-walled layer 51.

[0026] The multilayer ceramic capacitor 1 may have a configuration in which each of the multiple internal electrode layers 5 has a thick portion 51a and at least one thin portion 51b. In this case, the decrease in capacitance can be reduced while effectively reducing the occurrence of cracks.

[0027] The internal electrode layer 5 may have through holes 11, for example, as shown in Figures 3 and 4. The through holes 11 penetrate the internal electrode layer 5 in the thickness direction (i.e., the stacking direction). The through holes 11 are not in communication with the void 10, and the thin-walled portion 51b is not located inside the through holes 11. The multilayer ceramic capacitor 1 can effectively reduce the occurrence of cracks by having through holes 11 in the internal electrode layer 5.

[0028] The thin-walled portion 51b may be connected to the thick-walled portion 51a. In this case, the thin-walled portion 51b contributes to the acquisition of capacitance, thus effectively reducing the decrease in capacitance. In the cross-sectional views shown in Figures 3 and 4, a thin-walled portion 51b that is not connected to the thick-walled portion 51a is shown in the first direction, but such a thin-walled portion 51b is connected to the thick-walled portion 51a in the second direction.

[0029] The thin-walled portion 51b may have a shape in which, when viewed in cross-section along the stacking direction, the length in the direction perpendicular to the stacking direction is longer than the thickness in the stacking direction, as shown in Figure 4, for example. In this case, the thin-walled portion 51b has a relatively large planar area compared to the case in which the length in the stacking direction is longer than the length perpendicular to the stacking direction. As a result, the contribution of the thin-walled portion 51b to the capacitance is increased, and the decrease in capacitance can be effectively reduced. Here, "planar area" refers to the area when viewed along the stacking direction. When viewed in cross-section along the stacking direction, the thin-walled portion 51b may have a shape such as an ellipse, rectangle, or oblong shape, or it may have other shapes.

[0030] The thin-walled portion 51b may have an aspect ratio (B / A, also referred to as the aspect ratio) of 1.5 to 5.0 when viewed in cross-section along the lamination direction, where B is the length in the direction perpendicular to the lamination direction and A is the thickness in the lamination direction. If the aspect ratio is less than 1.5, the stress relaxation effect of the air gap 10 decreases, resulting in a higher crack defect rate. If the aspect ratio exceeds 5.0, the contribution of the thin-walled portion 51b to the capacitance decreases, reducing the effect of reducing the decrease in capacitance. By having an aspect ratio of 1.5 to 5.0, the decrease in capacitance can be reduced while effectively reducing the occurrence of cracks.

[0031] The thin-walled portion 51b may have a thickness ratio (hereinafter also referred to as the thickness ratio) of the thickness of the thin-walled portion 51b in the lamination direction to the thickness of the thick-walled portion 51a in the lamination direction, which is 20% or more and 70% or less. If the thickness ratio of the thin-walled portion 51b exceeds 70%, the stress relaxation effect of the air gap 10 decreases, resulting in a higher crack defect rate. Also, if the thickness ratio of the thin-walled portion 51b is less than 20%, the contribution of the thin-walled portion 51b to the capacitance decreases, resulting in a reduced effect in reducing the decrease in capacitance. By having a thickness ratio of the thin-walled portion 51b between 20% and 70%, the decrease in capacitance can be reduced while effectively reducing the occurrence of cracks.

[0032] Each of the multiple internal electrode layers 5 has at least one partially thin-walled layer 51, and each of the at least one partially thin-walled layer 51 may have a total of M (M is a natural number) thin-walled portions 51b. Furthermore, each of the multiple internal electrode layers 5 may have a total of N (N is a natural number) through-holes 11. The multilayer ceramic capacitor 1 may have a number ratio expressed as M / (M+N) of 0.3 or more. The number ratio can also be described as the ratio of the number of air gaps 10 (i.e., the number of thin-walled portions 51b) to the total number of air gaps 10 and through-holes 11 in the multiple internal electrode layers 5. If the number ratio M / (M+N) is less than 0.3, the proportion of thin-walled portions 51b is small, which reduces the occurrence of cracks, but also makes it easier for the capacitance to decrease. A number ratio M / (M+N) of 0.3 or more effectively reduces the occurrence of cracks while also reducing the decrease in capacitance.

[0033] Next, an example of a manufacturing method for the multilayer ceramic capacitor 1 will be described.

[0034] First, a dielectric powder mainly composed of BaTiO3 is mixed with an organic vehicle (prepared by dissolving an organic binder in a solvent) to prepare a paste for the dielectric layer 4. Then, a metal powder mainly composed of Ni is mixed with an organic vehicle to prepare a paste for the internal electrode layer 5.

[0035] Next, a laminate precursor to become the laminate 21 is prepared using the paste for the dielectric layer 4 and the paste for the internal electrode layer 5. The laminate precursor can be prepared, for example, using the sheet method or the printing method. In the sheet method, first, a ceramic green sheet is formed using the paste for the dielectric layer 4. Next, a pattern sheet is formed on the surface of the ceramic green sheet using the paste for the internal electrode layer 5, with an electrode pattern printed on it. After that, a laminate precursor can be prepared by stacking multiple pattern sheets and cutting them into a predetermined shape. In the printing method, the paste for the dielectric layer 4 and the paste for the internal electrode layer 5 are alternately printed on a substrate, cut into a predetermined shape, and then peeled off from the substrate to prepare the laminate precursor.

[0036] After fabricating a laminated precursor, a dielectric layer that will serve as a protective layer 6 is formed on the side surface of the laminated precursor to create a base material precursor. The protective layer 6 may be formed by attaching a ceramic green sheet to the side surface of the laminated precursor, or by applying a paste for the dielectric layer 4 to the side surface of the laminated precursor.

[0037] Next, the base material precursor is degreased. In the manufacturing method of the multilayer ceramic capacitor 1, primary degreasing and secondary degreasing are performed as degreasing treatments. Primary degreasing is performed in air at a temperature of about 240°C to remove solvents and plasticizers contained in the base material precursor. Secondary degreasing is performed after primary degreasing. Secondary degreasing is performed in a nitrogen atmosphere at a temperature of about 700°C to 1050°C to remove binders contained in the base material precursor by thermal decomposition and combustion. By performing secondary degreasing, the binder contained in the internal electrode layer 5 can be appropriately removed, and a partially thin layer 51 having a thin portion 51b can be formed after firing of the base material precursor.

[0038] After degreasing, the base material precursor is fired in a predetermined atmosphere and temperature to produce the base material. Subsequently, to remove the corners and burrs of the base material, it is placed in a pot containing polishing powder, polishing media, etc., and rotated to polish it. By forming external electrodes 3 on the polished base material, a multilayer ceramic capacitor 1 can be manufactured. [Examples]

[0039] Next, an example of multilayer ceramic capacitor 1 will be described. As an example, multilayer ceramic capacitors No. 2 to No. 8 in Table 1 and No. 9 to No. 12 in Table 2 were manufactured using the manufacturing method described above. In addition, a multilayer ceramic capacitor No. 1 in Table 1 was manufactured as a comparative example. The multilayer ceramic capacitors No. 2 to No. 8 have different secondary degreasing temperatures. The multilayer ceramic capacitors No. 9 to No. 12 have different average particle sizes of Ni powder used in the paste for the internal electrode layer 5. Sample No. 1 is a sample in which secondary degreasing was not performed on the base material precursor.

[0040] For multilayer ceramic capacitors No. 1 to No. 8, the capacitance value (hereinafter also simply referred to as capacitance value) was measured, and the cross-section of the samples was observed to measure the presence or absence of thin-walled areas, the aspect ratio of the thin-walled areas, the thickness ratio of the thin-walled areas, and the crack defect rate. For the cross-sectional observation, a polishing machine was used to polish the laminate 21 up to the center, and the central region of the polished surface was observed. Specifically, an electron microscope was used to photograph a 10 μm square area of ​​the backscattered electron image of the polished surface at a magnification of 10,000x, and based on the captured image, the presence or absence of thin-walled areas, the aspect ratio of the thin-walled areas, the thickness ratio of the thin-walled areas, and the crack defect rate were measured. The crack defect rate refers to the ratio of multilayer ceramic capacitors that developed cracks out of a predetermined number (e.g., 100) of multilayer ceramic capacitors.

[0041] [Table 1]

[0042] Sample No. 1 is a sample in which only primary degreasing was performed on the base material precursor, and no secondary degreasing was performed. In Sample No. 1, a relatively large amount of binder remains in the internal electrode layer. Therefore, the internal electrode layer is prone to melting during the firing of the base material precursor, and even if thick and thin sections are temporarily formed in the internal electrode layer during firing, the thin sections integrate with the thick sections, resulting in through holes. As a result, only through holes are formed in the internal electrode layer after firing, and no thin sections are formed. Sample No. 1 can effectively reduce the crack defect rate, but the volume value tends to decrease.

[0043] Samples No. 2 to No. 5 are samples in which at least one of the multiple internal electrode layers 5 has been made into a partially thin-walled layer 51 by performing secondary degreasing. Samples No. 2 and No. 3 have higher volume values ​​compared to sample No. 1 because they have the partially thin-walled layer 51. Samples No. 2 and No. 3 have a relatively small aspect ratio and a relatively large thickness ratio in the thin-walled portion 51b. Therefore, the stress relaxation effect of the void 10 is smaller than the stress relaxation effect of the through hole 11. As a result, samples No. 2 and No. 3 have a slightly higher crack defect rate compared to sample No. 1.

[0044] For samples No. 2 to No. 5, the volume value increases as the secondary degreasing temperature increases. This increase in volume value is because, as the secondary degreasing temperature increases, the amount of binder removed from the substrate precursor increases, making it more difficult for the internal electrode layer 5 to melt during firing, and thus easier to form the thin-walled portion 51b. Furthermore, as the secondary degreasing temperature increases, the aspect ratio of the thin-walled portion 51b increases and the thickness ratio decreases, resulting in a decrease in the crack defect rate.

[0045] As in samples No. 4 to No. 6, when the aspect ratio of the thin-walled portion 51b is between 1.5 and 5.0, and the thickness of the thin-walled portion 51b is between 20% and 70% of the thickness of the thick-walled portion 51a, the decrease in capacitance can be reduced while effectively reducing the occurrence of cracks.

[0046] As seen in samples No. 6 to No. 8, further increasing the secondary degreasing temperature increases the aspect ratio of the thin-walled section 51b and further decreases the thickness ratio. As a result, the crack defect rate can be effectively reduced, but the volume value begins to decrease. Samples No. 6 to No. 8 show a decrease in volume value compared to sample No. 5, but an increase in volume value compared to sample No. 1.

[0047] [Table 2]

[0048] For multilayer ceramic capacitors No. 9 to No. 12, the capacitance values ​​were measured, and the number ratio M / (M+N) was determined by observing the cross-section of the samples. The number ratio was determined by observing the cross-section of samples No. 9 to No. 12 with an electron microscope, similar to the previously mentioned measurement methods for crack defect rate, etc. Samples No. 9 to No. 12 were prepared by setting the secondary degreasing temperature to 900°C. Samples No. 9 to No. 12 differ in the average particle size of the Ni powder used to prepare the paste for the internal electrode layer 5. Figure 5 is a graph of the results in Table 2. Figure 5 shows the relationship between the number ratio M / (M+N) of the thin-walled portion and the capacitance value of the multilayer ceramic capacitor.

[0049] As shown in Table 2, reducing the average particle size of the Ni powder used in the paste for the internal electrode layer 5 increases the number ratio M / (M+N), and as a result, increases the capacitance value of the multilayer ceramic capacitor. The number ratio M / (M+N) increases as the average particle size of the Ni powder decreases. The increase in the number ratio M / (M+N) is because, when the average particle size of the Ni powder is small, when a thick-walled portion 51a and a thin-walled portion 51b are formed in the internal electrode layer 5 during firing, the Ni particles constituting the thin-walled portion 51b do not move easily, and the thin-walled portion 51b does not easily integrate with the thick-walled portion 51a. By reducing the average particle size of the Ni powder, the crack defect rate can be effectively reduced while effectively reducing the decrease in capacitance value.

[0050] Although embodiments of this disclosure have been described in detail above, this disclosure is not limited to the embodiments described above, and various modifications and improvements are possible without departing from the gist of this disclosure.

[0051] The multilayer ceramic capacitor of this disclosure can be implemented in the following embodiments (1) to (7).

[0052] (1) A laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers stacked alternately, The plurality of internal electrode layers include a partially thin-walled internal electrode layer. The aforementioned partially thin-walled internal electrode layer has a thick-walled portion and at least one thin-walled portion. The thin-walled portion has a thinner thickness in the stacking direction of the plurality of dielectric layers and the plurality of internal electrode layers than the thick-walled portion, and has an air gap between at least one of two adjacent dielectric layers, in a multilayer ceramic capacitor.

[0053] (2) The thin portion is electrically connected to the thick portion, and the multilayer ceramic capacitor is as described in (1) above.

[0054] (3) The multilayer ceramic capacitor according to (1) or (2) above, wherein, when viewed in cross-section along the stacking direction, the length in the direction perpendicular to the stacking direction is longer than the thickness in the stacking direction.

[0055] (4) The thin portion is a multilayer ceramic capacitor according to any one of (1) to (3) above, wherein, when viewed in cross-section along the stacking direction, the ratio of the thickness in the stacking direction to the length in the direction perpendicular to the stacking direction is 1.5 or more and 5.0 or less.

[0056] (5) A multilayer ceramic capacitor according to any one of (1) to (3) above, wherein the thickness of the thin portion in the stacking direction is 20% or more and 70% or less of the thickness of the thick portion in the stacking direction.

[0057] (6) The multilayer ceramic capacitor according to (4) above, wherein the thickness of the thin portion in the stacking direction is 20% or more and 70% or less of the thickness of the thick portion in the stacking direction.

[0058] (7) The partially thin internal electrode layer has M (where M is a natural number) of the thin portions, Each of the aforementioned internal electrode layers has N (N is a natural number) through holes that penetrate through the stacking direction, and the N through holes do not communicate with the void. A multilayer ceramic capacitor as described in configuration (6) above, wherein the number ratio expressed as M / (M+N) is 0.3 or greater. [Explanation of symbols]

[0059] 1. Multilayer ceramic capacitor 2. Base body 21 Laminate 3 External electrode 3a Base layer 3b outer layer 31 1st external electrode 32 2nd external electrode 4. Dielectric layer 5 Internal electrode layer 51 Partially thin internal electrode layer (partially thin layer) 51a Thick wall part 51b Thin wall part 6 Protective layer 7a 1st page 7b 2nd side 8a 1st end face 8b 2nd end face 9a 1st side 9b Second side 10 void 11 Through hole

Claims

1. The laminate includes a plurality of dielectric layers and a plurality of internal electrode layers stacked alternately, The plurality of internal electrode layers include a partially thin-walled internal electrode layer. The aforementioned partially thin-walled internal electrode layer has a thick-walled portion and at least one thin-walled portion. The thin-walled portion has a thinner thickness in the stacking direction of the plurality of dielectric layers and the plurality of internal electrode layers than the thick-walled portion, and has a gap between at least one of two adjacent dielectric layers. The thin-walled portion is a multilayer ceramic capacitor in which, when viewed in cross-section along the stacking direction, the ratio of the length in the direction perpendicular to the stacking direction to the thickness in the stacking direction is 1.5 or more and 5.0 or less.

2. The multilayer ceramic capacitor according to claim 1, wherein the thin portion is electrically connected to the thick portion.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the thickness of the thin portion in the stacking direction is 20% or more and 70% or less of the thickness of the thick portion in the stacking direction.

4. The aforementioned thin-walled internal electrode layer has M (where M is a natural number) of the thin-walled portions, Each of the aforementioned internal electrode layers has N (N is a natural number) through holes that penetrate through the stacking direction, and the N through holes do not communicate with the void. The multilayer ceramic capacitor according to claim 3, wherein the number ratio expressed as M / (M+N) is 0.3 or more.

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