Single-crystal AlN substrate, semiconductor wafer using a single-crystal AlN substrate, and methods for manufacturing these.

Abstract

To provide: a single crystal AlN substrate capable of manufacturing a highly reliable semiconductor device at a high yield; a semiconductor wafer using the same; and methods for manufacturing them.SOLUTION: A single crystal AlN substrate includes: a first surface having a flat surface being an Al polar plane and an inclined surface formed to a side surface from an outer edge of the flat surface; and a second surface being a surface on a side opposite to the first surface and a N polar plane. The inclined surface is formed to a position at which a distance from an end part of the single crystal AlN substrate in a direction along the flat surface is 0.45 mm or more and 0.75 mm or less and is formed to a position at which a distance from the flat face in a direction perpendicular to the flat surface is 0.2 mm or more and 0.3 mm or less.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a single-crystal AlN substrate applicable to the fabrication of semiconductor devices including light-emitting elements such as light-emitting diodes (LEDs) and semiconductor lasers (LDs), a semiconductor wafer using a single-crystal AlN substrate, and a method for manufacturing these. [Background technology]

[0002] When manufacturing semiconductor devices such as deep ultraviolet light-emitting devices using AlGaN semiconductors, AlN substrates are suitable as substrates for stacking AlGaN semiconductor layers, from the viewpoint of ease of lattice matching and other factors.

[0003] For example, Patent Document 1 describes an n-type AlN single crystal substrate with lattice matching. X Ga 1-X A group III nitride laminate having an N(0.5≦X<1) layer on an AlN single crystal substrate is disclosed. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] International Publication No. 2018-051772 [Overview of the project] [Problems that the invention aims to solve]

[0005] As described above, when growing an AlGaN-based semiconductor layer on an AlN substrate, a problem arose when removing the native oxide film with an etching solution as a pretreatment for crystal growth. Even if only the surface of the AlN substrate was brought into contact with the etching solution, the etching solution would seep up the sides and into the back surface. This seepage of the etching solution to the back surface resulted in etching of the back side of the AlN substrate, which reduced the in-plane temperature uniformity of the substrate when stacking the AlGaN-based semiconductor layer on the AlN substrate surface to form a semiconductor device. This affected the reliability and yield of the semiconductor device.

[0006] The present invention has been made in view of the above points, and aims to provide a single-crystal AlN substrate, a semiconductor wafer using a single-crystal AlN substrate, and a method for manufacturing the same, which can manufacture highly reliable semiconductor devices with a high yield. [Means for solving the problem]

[0007] The single-crystal AlN substrate according to the present invention is a single-crystal AlN substrate having a first surface having a flat surface which is an Al polar surface and an inclined surface formed from the outer edge to the side surface of the flat surface, and a second surface which is the surface opposite to the first surface and is an N polar surface, wherein the inclined surface is formed in a direction along the flat surface to a position where the distance from the edge of the single-crystal AlN substrate is 0.45 mm or more and 0.75 mm or less, and in a direction perpendicular to the flat surface to a position where the distance from the flat surface is 0.2 mm or more and 0.3 mm or less.

[0008] Furthermore, the single-crystal AlN substrate according to the present invention is a single-crystal AlN substrate having a first surface having a flat surface which is an Al polar surface and an inclined surface formed from the outer edge to the side surface of the flat surface, and a second surface which is the surface opposite to the first surface and is an N polar surface, and includes a PVT-AlN layer formed by the PVT method with the second surface as the lower surface, and an HVPE-AlN layer formed on the upper surface of the PVT-AlN layer by the HVPE method with the first surface as the upper surface, wherein at the end face of the single-crystal AlN substrate, the thickness of the HVPE-AlN layer is 1 / 5 or less of the thickness of the PVT-AlN layer.

[0009] The present invention relates to a method for manufacturing a single-crystal AlN substrate, comprising: (A) growing an HVPE-AlN layer on a PVT-AlN layer formed by a PVT method using an HVPE method to form a template substrate whose upper surface is an Al polar surface; and (B) chamfering the peripheral edge of the upper surface of the HVPE-AlN layer to form an inclined surface that slopes from the outer edge of the flat surface which is the Al polar surface to the side surface of the single-crystal AlN substrate, wherein, after the chamfering step (B), the thickness of the HVPE-AlN layer on the side surface of the single-crystal AlN substrate is 1 / 5 or less of the thickness of the PVT-AlN layer.

[0010] Furthermore, the semiconductor wafer manufacturing method according to the present invention is a method for manufacturing a semiconductor wafer in which a semiconductor layer is formed on a single crystal AlN substrate, comprising: (A) a step of growing an HVPE-AlN layer on a PVT-AlN layer formed by the PVT method by the HVPE method to form a template substrate whose upper surface is an Al polar surface; (B) a chamfering step of chamfering the peripheral edge of the upper surface of the HVPE-AlN layer to form an inclined surface that slopes from the outer edge of the flat surface which is the Al polar surface to the side surface of the single crystal AlN substrate; (C) an immersion treatment step of immersing the upper surface of the HVPE-AlN layer in an acid solution after the chamfering step (B); and (C) an AlN layer and Al on the HVPE-AlN layer by the MOCVD method after the immersion treatment step (C). x Ga 1-xThe method includes a step (D) of forming a laminated film in which N(0.5≦X≦1) layers are stacked in this order, characterized in that, after the chamfering step (B), the thickness of the HVPE-AlN layer on the side surface of the single crystal AlN substrate is 1 / 5 or less of the thickness of the PVT-AlN layer. [Brief explanation of the drawing]

[0011] [Figure 1] This is a top view of a semiconductor wafer according to Example 1. [Figure 2] This is a cross-sectional view showing the structure of the semiconductor wafer edge according to Example 1. [Figure 3] This is a schematic cross-sectional view showing the stacked structure of the semiconductor wafer of Example 1. [Figure 4] This flowchart outlines the manufacturing process of a semiconductor wafer using a single-crystal AlN substrate as described in Example 1. [Figure 5] This figure shows the pretreatment step using an acid solution in the semiconductor wafer manufacturing process of Example 1. [Figure 6] Figure 5 is a magnified view of a portion of the diagram showing the pretreatment process. [Figure 7] This is a cross-sectional view showing the structure of the semiconductor wafer edge according to Example 2. [Figure 8] This is a cross-sectional view showing the structure of the edge of a single-crystal AlN substrate according to a modified example of Example 2. [Figure 9] This is a cross-sectional view showing the structure of the semiconductor wafer edge according to Example 3. [Modes for carrying out the invention]

[0012] Preferred embodiments of the present invention will be described below, but these may be modified and combined as appropriate. In the following description and accompanying drawings, substantially identical or equivalent parts will be denoted by the same reference numerals. [Examples]

[0013] [Semiconductor wafer configuration using single-crystal AlN substrate] The configuration of the semiconductor wafer 100 in this embodiment will be described with reference to Figures 1 to 3. In this embodiment, the semiconductor wafer 100 has a semiconductor layer that will become an ultraviolet light-emitting diode (ultraviolet LED), which is an ultraviolet semiconductor light-emitting element, formed on a single-crystal AlN substrate 11.

[0014] Figure 1 is a top view of the semiconductor wafer 100 of this embodiment. The semiconductor wafer 100 is constructed by stacking semiconductor layers 13 on a single-crystal AlN substrate 11. In Figure 1, the semiconductor layers 13 are shown as dashed lines (double-dotted lines) to clarify the structure of the single-crystal AlN substrate 11. For illustrative purposes, the outer edge of the semiconductor layer 13 is drawn inside the outer edge of the substrate 11, but it should be understood that the semiconductor layer 13 is stacked over the entire top surface of the substrate 11. Hereafter, the direction in which the semiconductor layer 13 exists, as viewed from the substrate 11, will be described as the top of the semiconductor wafer 100.

[0015] As shown in Figure 1, the single-crystal AlN substrate 11 is a disc-shaped substrate having a substantially circular planar shape centered at point C when viewed from above. An orientation flat OF indicating the crystal orientation of the single-crystal AlN substrate 11 is formed at one location on the outer circumference of the single-crystal AlN substrate 11.

[0016] The single-crystal AlN substrate 11 has a flat surface FS and an inclined surface RP formed on a first surface S1 on which the semiconductor layer 13 is formed, extending from the outer edge of the flat surface FS to the edge of the single-crystal AlN substrate 11, that is, towards the outer edge when viewed from above.

[0017] As shown in Figure 1, the inclined surface RP is formed to have a constant width d1. In other words, the inclined surface RP is formed in the region between the edge of the single-crystal AlN substrate 11 and a position radially inward at a distance d1 from that edge. To put it another way, in a top view, the inclined surface RP extends inward from the edge of the single-crystal AlN substrate 11 by a distance d1.

[0018] Figure 2 is a partially enlarged cross-sectional view showing the shape near the edge of the semiconductor wafer 100, obtained by cutting the semiconductor wafer 100 along the line 2-2 passing through the center C shown in Figure 1.

[0019] As shown in Figure 2, the single-crystal AlN substrate 11 has a two-layer structure consisting of a PVT-AlN layer 11A, which is an AlN species substrate fabricated by the physical vapor transport (PVT) method, and an HVPE-AlN layer 11B, which is an AlN thick film grown on the PVT-AlN layer 11A by the hydride vapor phase epitaxy (HVPE) method.

[0020] As shown in Figure 2, the single-crystal AlN substrate 11 has a first surface S1 which is the top surface, a second surface S2 which is the opposite side of the first surface, i.e., the bottom surface, and a side surface S3.

[0021] As described above, the first surface S1 has a flat surface FS and an inclined surface RP.

[0022] The flat surface FS is a surface that has been flattened by polishing using known polishing methods such as chemical mechanical polishing (CMP). The flat surface FS is a C-plane and an Al polar surface. Therefore, it is resistant to etching solutions that etch the native oxide film on the surface, such as a mixed solution of phosphoric acid and sulfuric acid or hydrofluoric acid. The flat surface FS may also be a crystal plane with a so-called OFF angle, which is slightly inclined from the C-plane. The OFF angle is not particularly limited, but setting it in the range of 0.1 to 0.5° makes it easier to obtain good smoothness when an AlGaN layer is stacked on the S1 plane. The direction of the slight inclination can also be determined as appropriate, but it is preferable to have it in the M-axis direction, which yields a linear step-terrace structure.

[0023] The inclined surface RP is formed to slope downward from the outer edge of the flat surface FS toward the edge of the single-crystal AlN substrate 11, i.e., toward the side surface S3, in other words toward the second surface S2. That is, the inclined surface RP is an inclined surface that slopes downward toward the outside of the substrate 11.

[0024] The inclined surface RP can also be described as a chamfered portion formed by chamfering the corner between the surface and the edge of the single-crystal AlN substrate 11.

[0025] Furthermore, the inclined surface RP can also be described as a tapered portion having a tapered shape formed between the flat surface FS and the side surface S3 of the single-crystal AlN substrate 11.

[0026] As described above, the inclined surface RP extends a distance d1 from the outer edge or end of the flat surface FS in a direction along the flat surface FS. That is, the width of the inclined surface RP is d1. The width d1 is the distance measured from the outer edge or end of the flat surface FS.

[0027] Furthermore, the inclined surface RP extends from the flat surface FS in a direction perpendicular to the flat surface FS by a distance d2 in a side view. That is, the depth or height of the inclined surface RP is d2. The height d2 is the distance measured from the upper end of the plane perpendicular to the flat surface FS on the side of the single crystal AlN substrate 11, i.e., the upper end of the side surface S3, in a side view.

[0028] The inclined surface RP may include a curved surface and may have a rounded (R-shaped) cross-section. When the inclined surface RP has a rounded cross-section, the width d1 is measured from the outer edge or end of the flat surface FS, as in the case of a non-rounded surface. The height d2 of the inclined surface RP when it has a rounded cross-section is also measured from the upper end of the surface perpendicular to the flat surface FS, i.e., the upper end of the side surface S3.

[0029] In this embodiment, the inclined surface RP is formed up to a position where the distance d1 from the edge of the single-crystal AlN substrate 11 is 0.45 mm or more and 0.75 mm or less (0.45 ≤ d1 ≤ 0.75). In other words, the width d1 of the inclined surface RP in a top view is 0.45 mm or more and 0.75 mm or less.

[0030] Furthermore, the inclined surface RP is formed to a position where the distance d2 from the flat surface FS in a direction perpendicular to the flat surface FS is 0.2 mm or more and 0.3 mm or less. In other words, the height d2 of the inclined surface RP is 0.2 mm or more and 0.3 mm or less (0.2 ≤ d2 ≤ 0.3).

[0031] The inclined surface RP having the dimensions d1 and d2 described above will be inclined with respect to the flat surface FS at an angle of 23° to 29°. In other words, the angle between the inclined surface RP and the flat surface FS is 23° or more and 29° or less (in Figure 2, 23° ≤ θa ≤ 29°).

[0032] In this embodiment, the single-crystal AlN substrate 11 is first produced by growing a disc-shaped single-crystal AlN substrate using a seed substrate as a seed. Then, the first surface S1 of the single-crystal AlN substrate 11, i.e., the outer edge of the device growth surface, which is one of the main surfaces of the produced disc-shaped substrate, is ground to form an inclined surface RP. The disc-shaped substrate produced using the seed substrate is prone to slip dislocations due to residual stress at the peripheral edge of the growth surface when subjected to temperature changes during semiconductor layer growth. The inclined surface RP described above is the part that is created by removing the part that is prone to these slip dislocations.

[0033] In other words, the single-crystal AlN substrate 11 having an inclined surface RP in this embodiment is a substrate from which the portion where slip dislocations are likely to occur has been removed.

[0034] The second surface S2 may be a flat surface that has been flattened by known polishing methods such as chemical mechanical polishing, or it may be a mechanically polished surface, a so-called lapped surface. The second surface S2 is a -C surface and is an N polar surface. Therefore, it has no resistance to etching solutions that etch the native oxide film on the surface, such as a mixed solution of phosphoric acid and sulfuric acid or hydrofluoric acid, and is etched by such etching solutions. For this reason, from the viewpoint of slowing down the progress of etching, it is preferable that it be a flattened surface.

[0035] The side surface S3 is the side end surface of the single crystal AlN substrate 11, and is a surface perpendicular to the substrate surface and a surface perpendicular to the flat surface FS. The side surface S3 may be a rough surface as compared with the first surface S1 and the second surface S2.

[0036] The semiconductor layer 13 is formed by laminating a plurality of AlGaN-based semiconductor layers including an active layer on the first surface S1 of the single crystal AlN substrate 11 by epitaxial growth.

[0037] Here, while referring to FIG. 3, the layer structure of the semiconductor layer 13 will be described. FIG. 3 is an enlarged view of the portion A surrounded by the broken line in FIG. 2.

[0038] As shown in FIG. 3, on the single crystal AlN substrate 11, the semiconductor layer 13 is sequentially formed by epitaxial growth of an n-type AlGaN layer 14 (hereinafter, also referred to as an n-type Al x Ga 1-x N(0≦x≦1) layer 14), an active layer 15, an AlGaN layer 16, a p-type AlGaN layer 17, and a p-type GaN layer 18.

[0039] The n-type AlGaN layer 14 is an n-type conductive layer doped with Si (silicon). The Al composition of the n-type AlGaN layer 14 can be appropriately determined so as to obtain sufficient transmittance for the desired emission wavelength of ultraviolet light. For example, in an ultraviolet semiconductor light-emitting device using the semiconductor wafer 100, the ultraviolet light emitted from the light-emitting layer is transmitted through the n-type AlGaN layer 14 and the single crystal AlN substrate 11 and emitted to the outside. Also, as the Al composition of the n-type AlGaN layer 14 increases, the bandgap of the n-type AlGaN layer becomes larger, and accordingly, ultraviolet light with a shorter wavelength can be transmitted.

[0040] Also, the n-type Al x Ga 1-x N(0≦x≦1) layer 14 may be formed of a plurality of layers having different Al compositions. For example, the n-type Al x Ga 1-x N(0≦x≦1) layer 14 is an AlN layer and Al x Ga 1-xThe film may also include a laminated film in which N (0.5 ≤ x ≤ 1) layers are stacked in this order.

[0041] Alternatively, an AlN buffer layer may be provided between the single-crystal AlN substrate 11 and the n-type AlGaN layer 14.

[0042] Furthermore, n-type Al x Ga 1-x The N(0≦x≦1) layer 14 can also be a composition gradient layer in which the Al composition is gradient in the stacking direction, that is, in the direction away from the single crystal AlN substrate 11. For example, as shown in Figure 3, the n-type AlGaN layer 14 is a first n-type Al X1 Ga 1-X1 N-layer 14A and second n-type Al X2 Ga 1-X2 It consists of N layers 14B. X1 Ga 1-X1 The N layer 14A is a composition gradient layer in which the Al composition X1 decreases from 1.0 to 0.75 in the stacking direction, and the second n-type Al X2 Ga 1-X2 The N layer 14B can be a composition gradient layer in which the Al composition X2 decreases from 0.75 to 0.70.

[0043] Furthermore, the thickness of the n-type AlGaN layer 14 is not particularly limited and can be determined as appropriate. For example, the thickness of the n-type AlGaN layer 14 is preferably 0.5 μm or more and 2 μm or less. From the viewpoint of lowering the resistance of the n-type AlGaN layer, a thicker n-type AlGaN layer is preferable, but when using a single crystal AlN substrate 11, if the thickness of the n-type AlGaN layer becomes too thick, the n-type AlGaN layer will undergo lattice relaxation and dislocations will be more likely to occur.

[0044] For example, the n-type AlGaN layer 14 is made of the first n-type Al X1 Ga 1-X1 N-layer 14A and second n-type Al X2 Ga 1-X2 When formed as a laminated structure consisting of N layer 14B, the first n-type Al X1 Ga 1-X1 N layer 14A has a layer thickness of 200 nm, and the second n-type AlX2 Ga 1-X2 The AlGaN layer 14B can have a layer thickness of 1000 nm. Also, these first n-type Al X1 Ga 1-X1 GaN layers 14A and the second n-type Al X2 Ga 1-X2 The film thickness of the GaN layer 14B is not limited to the exemplified numbers and can be appropriately determined so that the total film thickness is 2.0 μm or less.

[0045] Also, the Si concentration for doping the n-type AlGaN layer 14 can be appropriately determined so as to obtain a desired n-type conductivity. From the viewpoint of reducing the resistance value of the n-type AlGaN layer 14, it is preferably 1×10 18 ~1×10 20 cm -3 and more preferably 5×10 18 ~5×10 19 cm -3 . Also, the Si doping concentration may be constant in the film thickness direction within the n-type AlGaN layer 14, or modulation doping with different Si concentrations in the film thickness direction can also be performed.

[0046] The active layer (ACT) 15 has a quantum well structure composed of a barrier layer made of an Al A1 Ga 1-A1 N layer and a well layer made of an Al A2 Ga 1-A2 N layer. The emission peak wavelength of the active layer 15 is within the range of 210 to 300 nm. Since the wavelength of the light emitted from the active layer 15 is determined by the Al composition and the film thickness of the well layer, the Al composition and the film thickness can be appropriately determined so as to obtain a desired emission wavelength within the above wavelength range.

[0047] For example, the film thickness of the well layer can be set within the range of 2 to 10 nm, and the Al composition can be determined so as to obtain a desired emission wavelength. Also, regarding the Al composition and the film thickness of the barrier layer, although not particularly limited, for example, the Al composition can be set within the range of A2 < A1 ≤ 1.0 and the film thickness can be set within the range of 2 to 15 nm.

[0048] Also, the well layer and the barrier layer can be n-type layers doped with Si. Both the well layer and the barrier layer may be Si-doped layers, or only the well layer or only the barrier layer may be doped with Si. The Si concentration to be doped is not particularly limited, but is preferably in the range of 1×10 17 ~5×10 18 cm -3 .

[0049] Also, the number of quantum well layers is not particularly limited, and a multiple quantum well (MQW) structure in which a plurality of well layers are formed or a single quantum well (SQW) may be used. The number of well layers is preferably appropriately determined within the range of 1 to 5.

[0050] Al Y1 Ga 1-Y1 N layer 16 is a layer provided adjacent to the active layer 15. Al Y1 Ga 1-Y1 N layer 16 functions as an electron blocking layer (EBL) to suppress the overflow of electrons injected into the active layer 15 to the p-type Al Y2 Ga 1-Y2 N layer 17. Therefore, Al Y1 Ga 1-Y1 N layer 16 has a larger bandgap than the active layer 15 and the p-type Al Y2 Ga 1-Y2 N layer 17 to be described later. The Al composition Y1 of the Al Y1 Ga 1-Y1 N layer 16 is determined within the range of 0.8 < Y1 ≤ 1.0.

[0051] As the emission wavelength shortens, the Al composition of the AlGaN layer epitaxially grown on the substrate 11 increases. When the emission wavelength is shorter than 270 nm, the Al composition Y1 is preferably 0.9 ≤ Y1 ≤ 1.0 in order to sufficiently exhibit the function as an electron blocking layer. In this embodiment, Al Y1 Ga 1-Y1AlN (Y1=1) is used as the N-layer 16.

[0052] Also, Y1 Ga 1-Y1 The N layer 16 may be an undoped layer or may be doped with a p-type dopant, as long as it can function as an electron blocking layer. Y1 Ga 1-Y1 For the p-type dopant material in the N layer 16, Mg (magnesium), Zn (zinc), Be (beryllium), C (carbon), etc., can be used. In particular, it is preferable to use Mg, which is commonly used as a p-type dopant material in the AlGaN layer.

[0053] p-type dopant materials are Al Y1 Ga 1-Y1 The N layer 16 may be uniformly doped in the stacking direction, or the concentration of the dopant material can be varied in the stacking direction. For example, a stacked structure can be formed consisting of an undoped AlN layer 16A (Y1=1) and a Mg (magnesium) doped p-type AlN layer 16B from the side in contact with the active layer.

[0054] Al Y1 Ga 1-Y1 The p-type dopant concentration in layer N16 is particularly limited. Although it does not exist, in order to obtain the function as an electronic block layer, 5 × 10 18 ~1 × 10 20 cm -3 It is preferable that this is the case, and from the viewpoint of being able to improve the carrier injection efficiency into the light-emitting layer, 1 × 10 19 ~8×10 19 cm -3 It is particularly preferable that this be the case.

[0055] Al of the present invention Y1 Ga 1-Y1 Layer N16 either does not contain an n-type dopant, or it contains a p-type Al, as described later. Y2 Ga 1-Y2 It can contain n-type dopants at concentrations lower than those of the n-type dopants contained in layer N17. Specifically, AlY1 Ga 1-Y1 The n-type impurity concentration in the GaN layer 16 is preferably 1×10 18 cm -3 or less. According to the findings of the present inventors, during the growth of the p-type Al Y2 Ga 1-Y2 N layer 17, it has been found that dopant diffusion occurs between the adjacent Al Y1 Ga 1-Y1 N layer 16. Therefore, when the n-type dopant concentration in the Al Y1 Ga 1-Y1 N layer 16 is higher than that in the p-type Al Y2 Ga 1-Y2 N layer 17, it may be difficult to precisely control the n-type dopant concentration in the p-type Al Y1 Ga 1-Y1 N layer 17. In order to prevent the change in the n-type dopant concentration in the p-type Al Y2 Ga 1-Y2 N layer 17 due to this diffusion, at least the n-type dopant in the Al Y2 Ga 1-Y2 N layer 16 needs to be less than the concentration of the n-type dopant contained in the p-type Al Y2 Ga 1-Y2 N layer 17. Y1 Ga 1-Y1 N layer 16 should be less than the concentration of the n-type dopant contained in the p-type Al Y2 Ga 1-Y2 N layer 17.

[0056] Also, the film thickness of the Al Y1 Ga 1-Y1 N layer 16 can be appropriately determined so that it can function as an electron blocking layer and holes can be efficiently injected from the p-type Al Y2 Ga 1-Y2 N layer 17 into the active layer, but a range of 1 to 30 nm is preferable. If the film thickness is less than 1 nm, electrons will tunnel, resulting in a decrease in the function as an electron blocking layer. On the other hand, if the film thickness exceeds 30 nm, it will be difficult for holes to be injected from the p-type Al Y2 Ga 1-Y2 N layer 17 into the active layer. Considering these factors, the Al Y1 Ga 1-Y1The thickness of the N layer 16 is preferably 2 to 20 nm, and more preferably 5 to 15 nm.

[0057] Also, as mentioned above, Al Y1 Ga 1-Y1 The Mg doping in the N layer 16 can also have a concentration difference depending on the stacking direction. For example, an undoped AlN layer 16A can be stacked with a thickness of 1 to 5 nm on the side in contact with the active layer 15, and then a Mg-doped p-type AlN layer 16B can be stacked with a thickness of 5 to 15 nm. In this case, the Mg doping concentration can be 5 × 10⁻⁶, as described above. 18 ~1 × 10 20 cm -3 Preferably, 1 × 10 19 ~8×10 19 cm -3 It is particularly preferable that this be the case.

[0058] The present invention of p-type Al Y2 Ga 1-Y2 The N layer 17 is made of the Al Y1 Ga 1-Y1 It is formed on the N layer 16 and functions as a p-type cladding layer. Y2 Ga 1-Y2 N-layer 17 is co-doped with p-type impurities that act as acceptors and n-type impurities that act as donors.

[0059] p-type Al Y2 Ga 1-Y2 For the p-type impurities doped into the N layer 17, Mg (magnesium), Zn (zinc), Be (beryllium), C (carbon), etc., can be used. Among these, it is preferable to use Mg, which is commonly used as a p-type dopant material for AlGaN semiconductors. For the n-type impurities, Si, Ge (germanium), Se (selenium), S (sulfur), O (oxygen), etc., can be used. Among these, it is preferable to use Si, which is commonly used as an n-type dopant material.

[0060] Also, p-type Al Y2 Ga 1-Y2 The amount of p-type impurities doped into layer N17 is 1 × 10⁻⁶ 17~1.2 × 10 20 cm -3 It is preferable that this is the case. Also, as theoretically shown in J. Applmaru Physmaru, Volmaru 95, No. 8, 15 April (2004), p-type Al Y2 Ga 1-Y2 It is thought that the amount of nitrogen vacancies, which are considered to be a factor in degradation, increases with the amount of p-type impurities in the N layer 17. 20 cm -3 If this value is exceeded, the amount of nitrogen vacancies formed initially becomes too large, making it difficult to achieve a high power maintenance rate.

[0061] Furthermore, when the p-type impurity concentration decreases, especially when the Al composition Y2 is constant, the output decreases due to a decrease in hole concentration and an increase in minority carrier (electron) mobility. When the Al composition Y2 is sloped, the output decreases due to an increase in minority carrier (electron) mobility, making it difficult to obtain high luminescence efficiency. Therefore, the p-type impurity concentration can be appropriately determined within the above range, taking these trade-offs into consideration. However, to obtain a higher power maintenance rate and higher output, 1 × 10⁻⁶ 19 ~5×10 19 cm -3 Preferably, and more preferably, 1 × 10 19 ~4×10 19 cm -3 That is the case.

[0062] p-type Al Y2 Ga 1-Y2 The amount of n-type impurities doped into layer N17 is 1.1 × 10⁻⁶. 18 The above 9.0 x 10 18 cm -3 Preferably, the following, and more preferably, 1.8 × 10 18 The above 8.0 x 10 18 cm -3 The following applies. With these n-type impurity amounts, a light-emitting element with high luminescence efficiency can be obtained.

[0063] Also, p-type Al Y2 Ga 1-Y2The p-type and n-type impurities doped into the N layer 17 may have a constant concentration within the layer, or a concentration difference may be introduced in the stacking direction. For example, Al Y1 Ga 1-Y1 The side adjacent to the N layer 16 is used as the co-doping layer, and the remaining p-type Al Y2 Ga 1-Y2 The 17 N-layers can also be made into layers that are not doped with n-type impurities.

[0064] p-type Al Y2 Ga 1-Y2 The Al composition Y2 of the N layer 17 is between 0.5 and 1.0, and Al Y1 Ga 1-Y1 The Al composition of the N layer 16 is less than or equal to Y1.

[0065] p-type Al Y2 Ga 1-Y2 The Al composition Y2 of the N layer 17, in the case of a structure where Y2 is a constant value in the stacking direction, exceeds the Al composition of the barrier layer of the active layer, and Al Y1 Ga 1-Y1 It is preferable that the Al composition of the N layer 16 is less than or equal to Y1. Y2 Ga 1-Y2 By setting the Al composition Y2 of the N layer 17 within the above range, a high carrier overflow suppression effect can be obtained even when the injection current of the ultraviolet light-emitting element is high. To obtain an even higher effect, the Al composition of the barrier layer of the active layer and the p-type Al Y2 Ga 1-Y2 It is preferable that the difference in Al composition Y2 of the N layer 17 is 0.5 or more. Also, p-type Al Y2 Ga 1-Y2 The Al composition Y2 of the N layer 17 is preferably greater than the Al composition of the n-type AlGaN layer 14. This enhances the effect of suppressing carrier overflow to the p-type layer, thereby increasing the luminescence efficiency of the ultraviolet light-emitting device. Y2 Ga 1-Y2 In the case of a structure where Y2 is a constant value in the stacking direction, the Al composition Y2 of the N layer 17 is preferably 0.6 or more and 0.9 or less.

[0066] Also, p-type Al Y2 Ga 1-Y2The N layer 17 may be a composition gradient layer in which the Al composition Y2 changes in the stacking direction. In particular, Al Y1 Ga 1-Y1 It is preferable that the structure is such that the Al composition Y2 decreases in the stacking direction from the side in contact with the N layer 16. Y2 Ga 1-Y2 Because a polarization doping effect is obtained within the N layer 17, it becomes easier to obtain a higher hole concentration, and as a result, the efficiency of hole injection into the active layer increases. For example, when the emission wavelength is 270 nm or less, Al Y1 Ga 1-Y1 The Al composition on the side in contact with the N layer 16 is preferably 0.95 to 1.0, and the p-type Al on the opposite side Y2 Ga 1-Y2 The Al composition on the surface of the N layer 17 is preferably 0.60 to 0.85. By adopting such a structure, the polarization doping effect described above can be enhanced, and transparency with respect to the emission wavelength can be maintained, making it easier to obtain high luminescence efficiency.

[0067] Also, p-type Al Y2 Ga 1-Y2 The thickness of the N layer 17 is not particularly limited, but can be appropriately determined within the range of 10 to 150 nm. Y2 Ga 1-Y2 When the thickness of the N layer 17 becomes less than 10 nm, the carrier overflow suppression effect described above becomes difficult to obtain, while when the thickness increases and exceeds 150 nm, p-type Al Y2 Ga 1-Y2 The resistance of the N layer 17 increases, which in turn leads to an increase in the operating voltage of the ultraviolet light-emitting element. From this perspective, p-type Al Y2 Ga 1-Y2 The thickness of the N layer 17 is preferably 40 to 120 nm, and particularly preferably 50 to 100 nm.

[0068] p-type Al Y2 Ga 1-Y2A p-type GaN layer 18 doped with a p-type dopant may be formed on the N layer 17 to reduce contact resistance with the electrode. While the known p-type dopant materials described above can be used, Mg is preferred for similar reasons. The Mg doping concentration in the p-type GaN layer 18 is not particularly limited, but to reduce the resistance in the p-type GaN layer and the contact resistance with the electrode, a concentration of 1 × 10⁻¹⁰ is preferable. 18 ~2×10 20 cm -3 This is preferable. Furthermore, the thickness of the p-type GaN layer 18 is not particularly limited and can be appropriately determined within the range of 5 to 500 nm.

[0069] Furthermore, with the exception of the p-type GaN layer 18, all AlGaN layers 14, 15, 16, and 17 are crystallized in a lattice-matched state with the single-crystal AlN substrate 11, and therefore have a low dislocation density equivalent to that of the single-crystal AlN substrate 11.

[0070] In the present invention, the single-crystal AlN substrate 11 is not particularly limited, but in view of the quality of the semiconductor layer 13 grown on the single-crystal AlN substrate 11, it is preferable that it has a low dislocation density. Specifically, the dislocation density of the single-crystal AlN substrate 11 is 10 6 cm -2 It is preferable that the following conditions are met, and more preferably 10 4 cm -2 The following is true: By making the single-crystal AlN substrate 11 have a low dislocation density, the dislocation density in the AlGaN layer formed on the single-crystal AlN substrate 11 can also be reduced. This makes it possible to improve the characteristics of, for example, an ultraviolet light-emitting device using the single-crystal AlN substrate 11.

[0071] Furthermore, if the surface roughness of the flat surface FS is large, it can lead to abnormal growth of the AlGaN layer growing on the flat surface FS. Therefore, the surface roughness (RMS) of the flat surface FS of the single crystal AlN substrate 11 is preferably 5.0 nm or less, more preferably 1.0 nm or less, and even more preferably 0.5 nm or less.

[0072] Furthermore, in an ultraviolet light-emitting device using a single-crystal AlN substrate 11, if the absorption coefficient of the substrate for ultraviolet light emitted from the active layer is large, there is a concern that the total amount of ultraviolet light that can be extracted to the outside will decrease, leading to a decrease in luminescence efficiency. For this reason, the absorption coefficient of the single-crystal AlN substrate 11 is preferably 20 cm⁻¹. -1 The following, and more preferably 10 cm -1 The absorption coefficient of the single-crystal AlN substrate 11 is given by 10 cm². -1 By doing the following, for example, even if the thickness of the single-crystal AlN substrate 11 is 100 μm, a linear transmittance of 90% or more can be secured.

[0073] For example, by keeping the content of impurities such as carbon in the single-crystal AlN substrate 11 low, the absorption coefficient can be lowered and light transmittance can be ensured. For example, in order to sufficiently lower the absorption coefficient, the carbon concentration in the single-crystal AlN substrate 11 should be 5 × 10⁻⁶. 17 cm -3 The following is preferable:

[0074] [Manufacturing method] The manufacturing process for the single-crystal AlN substrate 11 and the semiconductor wafer 100 using it will be explained with reference to Figures 4 to 6.

[0075] Figure 4 is a flowchart showing an overview of the manufacturing process for semiconductor wafer 100.

[0076] First, a template substrate is prepared for fabricating a single-crystal AlN substrate 11 (step S101). In step S101, a PVT-AlN layer 11A is fabricated by the PVT method, and using this as a seed substrate, an HVPE-AlN layer 11B is grown on the PVT-AlN layer 11A by the HVPE method to create a two-layer single-crystal AlN substrate which is used as the template substrate.

[0077] The upper surface of the PVT-AlN layer 11A is an Al polarity surface, and the HVPE-AlN layer 11B is laminated on this upper surface. Therefore, the upper surface of the HVPE-AlN layer 11B, which is the upper surface of the template substrate, is an Al polarity surface, and the lower surface of the PVT-AlN layer 11A, which is the lower surface of the template substrate, is an N polarity surface.

[0078] For example, when single-crystal AlN is grown by the PVT method, discoloration due to impurities is likely to occur, and the desired light transmittance may not be obtained. On the other hand, when single-crystal AlN is grown by the HVPE method, impurities are less likely to be incorporated, and light transmittance is easily ensured. Therefore, in this embodiment, a substrate for fabricating a single-crystal AlN substrate 11 is made by forming a single-crystal AlN by the HVPE method on a single-crystal AlN formed by the PVT method. For example, after the light-emitting element is formed, the portion of the single-crystal AlN substrate 11 formed by the PVT method may be removed. In this way, the light transmittance of the substrate after the formation of the light-emitting element can be ensured.

[0079] In step S101, the upper surface of the HVPE-AlN layer 11B is the Al polarity surface, and the lower surface of the PVT-AlN layer 11A is the N polarity surface.

[0080] Next, the single-crystal AlN substrate prepared in step S101 is chamfered on the outer periphery of the surface to produce a single-crystal AlN substrate 11 (step S102). In step S102, the chamfering is performed to form the inclined surface RP shown in Figure 2.

[0081] Specifically, as described above, the inclined surface RP is formed in a direction along the flat surface FS to a position where the distance from the edge of the single crystal AlN substrate 11 is 0.45 mm or more and 0.75 mm or less, and in a direction perpendicular to the flat surface FS to a position where the distance from the flat surface FS is 0.2 mm or more and 0.3 mm or less.

[0082] In other words, the inclined surface RP is formed such that the distance d1 from the edge of the single-crystal AlN substrate 11 shown in Figure 2 is between 0.45 mm and 0.75 mm (0.45 ≤ d1 ≤ 0.75), and the distance d2 from the flat surface FS in a direction perpendicular to the flat surface FS is between 0.2 mm and 0.3 mm (0.2 ≤ d2 ≤ 0.3).

[0083] In step S102, the chamfering is performed, for example, by grinding using a known chamfering machine. For example, portions in which an orientation flat or notch is formed are also ground to have an inclined surface RP.

[0084] Subsequently, chemical mechanical polishing is performed to form a flat surface FS and a second surface S2 (step S103). For example, the inclined surface RP may become a rounded surface due to the chemical mechanical polishing in step S103 after chamfering.

[0085] A single-crystal AlN substrate 11 is fabricated by steps S101 to S103.

[0086] Subsequently, as a pretreatment for crystal growth to form an ultraviolet light-emitting element on the single-crystal AlN substrate 11, the flat surface FS of the single-crystal AlN substrate 11 is immersed in an acid solution (step S104) to remove the native oxide film formed on the surface of the single-crystal AlN substrate 11. In step S104, for example, a mixed solution of phosphoric acid and sulfuric acid in a ratio of 1:3 is used as the acid solution, and the treatment is carried out at a treatment temperature of 70°C for 10 minutes.

[0087] In step S104, only the flat surface FS of the single crystal AlN substrate 11 is brought into contact with the acid solution, while the back surface of the single crystal AlN substrate 11, i.e., the second surface S2 in Figure 2, is exposed from the acid solution and held in this state for a predetermined processing time.

[0088] As described above, the flat surface FS is an Al polar surface, so only the native oxide film is etched by the acid solution, and the AlN surface is difficult to etch. In contrast, the second surface S2 is an N polar surface, so it is easily etched by the acid solution. Therefore, in step S104, in order to prevent the second surface S2 from being etched by the acid solution, which is an etching solution that removes the native oxide film, only the flat surface FS is treated while the second surface S2 of the single crystal AlN substrate 11 is exposed from the acid solution.

[0089] Figure 5 is a cross-sectional view showing that in step S104 of the above manufacturing process, only the flat surface FS of the single crystal AlN substrate 11 is immersed in the acid solution AC using a Teflon® jig TL. In Figure 5, LL indicates the liquid level of the acid solution AC.

[0090] As shown in Figure 5, the jig TL has a container portion CT for containing liquid and a support portion SP fixed to the container portion to support the wafer. The support portion SP has a receiving portion TR with a substrate receiving surface TRS having a downwardly convex bottom shape. The receiving portion TR supports the single crystal AlN substrate 11 via the substrate receiving surface TRS, which is in contact with the boundary between the flat surface FS and the inclined surface RP of the single crystal AlN substrate 11. The receiving portion is made of, for example, a mesh-like material, and the acid solution AC in the container portion CT passes through the mesh-like material to reach the flat surface FS of the single crystal AlN substrate 11.

[0091] The acid solution AC is poured into the jig TL such that the liquid level LL of the acid solution AC is at the height of the flat surface FS.

[0092] Figure 6 is a magnified view of the area B enclosed by the dashed line in Figure 5. In Figure 6, the jig TL is omitted.

[0093] As described above, when acid solution AC is injected so that its liquid level LL is in contact with the flat surface FS, the acid solution AC spreads and wets the entire flat surface FS. At that time, as shown in Figure 6, due to the effect of surface tension, the acid solution AC tends to crawl upward towards the side surface S3.

[0094] If we consider the case where the acid solution AC creeps up the side surface S3, the angle θ (contact angle θ, not shown) between the tangent line drawn from the point where the acid solution AC and side surface S3 touch the liquid surface and side surface S3 is greater than the angle θb (contact angle θb between inclined surface RP and acid solution AC) between the tangent line drawn from the point where the acid solution AC and inclined surface RP touch the liquid surface and inclined surface RP.

[0095] Considering that the force with which a liquid tries to crawl up a solid surface is proportional to cosθ, we have cosθ > cosθb, and the force with which the acid solution AC tries to crawl up the inclined surface RP is smaller than the force with which it tries to crawl up a vertical surface such as the side surface S3. In other words, the acid solution AC is less likely to crawl up on the inclined surface RP than on the side surface S3. In light of this, it can be said that the formation of RP makes it difficult for the acid solution AC to flow around to the second surface S2 via the side surface of the substrate 11.

[0096] In this embodiment, the dimensions of the inclined surface RP are set to be significantly larger than in the case of simple chamfering, with respect to the distance d1 (width) from the edge of the single-crystal AlN substrate 11 and the vertical distance d2 (height) from the flat surface FS. As a result, the spread of the acid solution AC stops within the range of the inclined surface RP and does not reach the side surface S3. Thus, the inclined surface RP plays a role in preventing the acid solution AC, which has spread across the flat surface FS, from reaching the side surface S3.

[0097] For example, if the width or height of the inclined surface RP is insufficient, the acid solution AC will reach the side surface S3, and then crawl up the side surface S3 to reach the second surface S2. In that case, only the portion of the second surface S2 that the acid solution AC reaches will be etched, resulting in uneven thickness and surface roughness of the 11 single-crystal AlN substrates. Specifically, the region along the outer periphery of the second surface S2 will be partially etched, creating areas with large irregularities and surface roughness.

[0098] The second surface S2 is the surface that contacts the susceptor used to heat the substrate 11 when growing the semiconductor layer 13 on the substrate 11. If areas with large irregularities or surface roughness are formed on this surface as described above, the crystal growth temperature when forming the AlGaN layer on the single-crystal AlN substrate 11 becomes uneven. When a semiconductor device is formed from such a semiconductor wafer, the reliability of the formed semiconductor device decreases, and the yield of the semiconductor device decreases.

[0099] In this embodiment, an inclined surface RP is provided to prevent the acid solution AC from seeping to the back surface. Specifically, as shown in Figure 2, an inclined surface RP is provided such that the distance d1 from the edge of the single crystal AlN substrate 11 is 0.45 mm or more and 0.75 mm or less (0.45 ≤ d1 ≤ 0.75), and the distance d2 from the flat surface FS in a direction perpendicular to the flat surface FS is 0.2 mm or more and 0.3 mm or less (0.2 ≤ d2 ≤ 0.3).

[0100] The dimensions of this inclined surface RP are such that they prevent the acid solution AC from seeping into the second surface S2 of the single-crystal AlN substrate 11, while minimizing the reduction in the area of ​​the flat surface FS of the single-crystal AlN substrate 11 that would render it unusable as a semiconductor device when the inclined surface RP is provided. Therefore, highly reliable semiconductor devices can be obtained without reducing the yield.

[0101] Returning to the explanation of Figure 4, after step S104, the single-crystal AlN substrate 11, after being rinsed with pure water and dried, is introduced into the MOCVD apparatus to perform crystal growth of the semiconductor layer 13 (step S105). In step S105, the n-type AlGaN layer 14, active layer 15, AlGaN layer 16, p-type AlGaN layer 17, and p-type GaN layer 18 shown in Figure 3 are grown to obtain a semiconductor wafer 100.

[0102] In step S105, during the crystal growth of the semiconductor layer 13, Group III (Al, Ga) raw material gases and Group V (N) raw material gases are supplied onto the single-crystal AlN substrate 11 together with a carrier gas such as hydrogen and / or nitrogen. Any known raw material gases can be used for the Group III (Al, Ga) and Group V (N) raw material gases used here, without any particular limitations.

[0103] For example, trimethylaluminum, triethylaluminum, trimethylgallium, and triethylgallium can be used as Group III raw material gases. Ammonia is typically used as a Group V raw material gas.

[0104] Furthermore, the Mg and Si dopant feedstock gases can be any known material without restriction; for example, biscyclopentadienylmagnesium, monosilane, tetraethylsilane, etc., can be used.

[0105] The supply ratio of Group III raw material gas to Group V raw material gas (V / III ratio) can be appropriately determined to obtain the desired characteristics, but it is preferable to set it within the range of 500 to 10000.

[0106] Furthermore, the growth temperature of each layer constituting the semiconductor layer 13 is not particularly restricted. The temperature can be appropriately determined to obtain the desired characteristics of each layer and the characteristics of the ultraviolet LED, but it is preferable to grow it at 1000 to 1200°C, and more preferably at 1000 to 1150°C.

[0107] The semiconductor layer 13 can be manufactured by known crystal growth methods such as molecular beam epitaxy (MBE) in addition to the MOCVD method. Among these, the MOCVD method is preferred because it has high productivity and is widely used industrially.

[0108] Through the above manufacturing process, a semiconductor layer 13 was formed on a single-crystal AlN substrate 11, and a semiconductor wafer 100 was obtained.

[0109] The effectiveness of preventing the leakage of acid solution AC during the manufacturing of wafer 100 and the effectiveness of preventing the occurrence of slip defects in the semiconductor layer 13 of wafer 100 were verified.

[0110] Specifically, a first example sample and a second example sample were fabricated, with the inclined surface RP of the semiconductor wafer 100 having the following dimensions. Sample of the first example: d1=0.47mm, d2=0.20mm Sample of the second example: d1=0.69mm, d2=0.31mm Furthermore, as comparative examples, a first comparative example sample and a second comparative example sample were prepared, both having a conventional chamfering structure with a chamfered portion located at a position corresponding to the inclined surface RP and having a smaller height and width than the inclined surface RP, and otherwise being the same as semiconductor wafer 100.

[0111] The dimensions of a conventional chamfer are expressed by a distance d1 measured from the outer edge or end of the flat surface FS in a direction along the flat surface FS, and a distance d2 measured from the upper end of a plane perpendicular to the flat surface FS on the side of the single-crystal AlN substrate in a side view.

[0112] The first comparative example sample and the second comparative example sample have the following dimensions. First comparative example sample: d1=0.34mm, d2=0.17mm Second comparative example sample: d1=0.28mm, d2=0.17mm Therefore, the first and second comparative example samples do not satisfy the requirements for an inclined surface RP, which are 0.45 ≤ d1 ≤ 0.75 and 0.2 ≤ d2 ≤ 0.3, and instead have d1 < 0.45 and d2 < 0.2. Consequently, the comparative examples have chamfered portions with smaller dimensions than the inclined surface RP of the examples.

[0113] No traces of the acid solution AC seeping onto the second surface S2, i.e., the back surface, were observed in the sample of the first and second examples.

[0114] On the other hand, traces of liquid movement from the outer edge to the inner surface were sometimes observed on the back surface of the semiconductor wafers of the first and second comparative examples. In the case of the first and second comparative examples, it is thought that the acid solution AC could not be prevented from reaching the sides during the pretreatment with the acid solution AC before the growth of the semiconductor layer, and that the acid solution AC reached the sides of the substrate with a conventional chamfered structure, and further reached the back surface.

[0115] Furthermore, in the first and second comparative example samples, which lacked an inclined surface RP and had a conventional chamfered portion, linear defects (slip defects) originating near the outer periphery of the semiconductor layer 13 were prone to occurring.

[0116] The comparative example single-crystal AlN substrate has strain that occurred during crystal growth during its manufacturing process. Therefore, when a semiconductor layer is grown on it, the stress is released due to factors such as the temperature rise during growth, causing some crystal movement, mainly at the outer edge of the substrate, which is thought to have resulted in linear defects due to the creation of steps on the substrate surface.

[0117] Furthermore, as in this embodiment, when a two-layer structure is formed by creating a single-crystal AlN layer by the HVPE method on a single-crystal AlN layer formed by the PVT method, strain tends to remain in the HVPE-AlN layer, which makes slip along the M plane more likely to occur.

[0118] If a linear defect is present within an element, its reliability decreases, and therefore elements containing linear defects are treated as defective. Consequently, the occurrence of linear defects leads to a decrease in yield.

[0119] No linear defects originating from the outer periphery were observed in the semiconductor wafer 100 having the inclined surface RP of this embodiment. Specifically, no linear defects occurred in either the sample of the first embodiment or the sample of the second embodiment described above.

[0120] In this embodiment, it is presumed that the presence of an inclined surface RP either removes the strained portion or, if strain remains, makes it easier to alleviate, thus reducing the likelihood of linear defects.

[0121] From the above, it can be said that the dimensions of the inclined surface RP in this embodiment are sufficient to adequately mitigate the strain that causes the linear defects described above.

[0122] As described in detail above, the single-crystal AlN substrate 11 in the semiconductor wafer 100 of this embodiment has a first surface S1, a second surface S2 which is the surface opposite to the first surface, and a side surface S3. The first surface S1 has a flat surface FS and an inclined surface RP which is formed so as to slope from the outer edge of the flat surface FS toward the second surface S2 toward the side surface S3. The flat surface FS is an Al polar surface, and the second surface S2 is an N polar surface.

[0123] The inclined surface RP is formed in a direction along the flat surface FS, extending to a position of 0.45 mm or more and 0.75 mm or less from the edge of the single-crystal AlN substrate 11. In addition, the inclined surface RP is formed in a direction perpendicular to the flat surface FS, extending to a position of 0.2 mm or more and 0.3 mm or less from the flat surface FS.

[0124] In this embodiment, the semiconductor wafer 100 has a semiconductor layer 13 formed on a first surface S1 of a single-crystal AlN substrate 11.

[0125] With this configuration, according to this embodiment, when only the flat surface FS is immersed in the acid solution as a pretreatment for forming the semiconductor layer 13, it is possible to prevent the acid solution from spreading to the side surface S3 and the second surface S2. This prevents a decrease in device reliability caused by temperature unevenness during the growth of the semiconductor layer 13.

[0126] Furthermore, according to this embodiment, it is possible to prevent linear defects from occurring in the semiconductor wafer 100 on which the semiconductor layer 13 is formed on the single-crystal AlN substrate 11. In this respect as well, it is possible to prevent a decrease in the reliability of the device.

[0127] The dimensions of the inclined surface RP in this embodiment are sufficiently large to prevent leakage. Furthermore, the dimensions of the inclined surface RP in this embodiment are sufficiently large to alleviate the strain on the single-crystal AlN substrate 11 and prevent linear defects.

[0128] Therefore, according to this embodiment, it is possible to provide an AlN single crystal substrate capable of forming highly reliable semiconductor devices with a high yield, a semiconductor wafer using the AlN single crystal substrate, and a method for manufacturing the same. [Examples]

[0129] Referring to Figure 7, the configuration of the semiconductor wafer 200 according to Example 2 will be described. The semiconductor wafer 200 differs from the semiconductor wafer 100 of Example 1 in that it has an inclined surface RP2 instead of an inclined surface RP, but is otherwise configured similarly to the semiconductor wafer 100.

[0130] The inclined surface RP2 is formed on the first surface S1 of the single-crystal AlN substrate 11 so as to be inclined from the outer edge of the flat surface FS to the edge of the single-crystal AlN substrate 11.

[0131] The inclined surface RP2 is formed such that the thickness d3 of the HVPE-AlN layer 11B is 1 / 5 (one-fifth) or less of the thickness d4 of the PVT-AlN layer 11A at the side surface S3, i.e., the edge of the single-crystal AlN substrate 11.

[0132] In this embodiment, the thickness of the PVT-AlN layer 11A is, for example, 0.25 mm, may be 0.1 to 0.37 mm, or average 0.23 mm. The thickness of the HVPE-AlN layer 11B is, for example, 0.25 mm, may be 0.15 to 0.43 mm, or average 0.27 mm.

[0133] In this embodiment, as in the case of Embodiment 1, no traces of the acid solution AC seeping into the second surface S2, i.e., the back surface, were observed on the semiconductor wafer 200.

[0134] Furthermore, no linear defects like those described in Example 1 were observed in the semiconductor wafer 200.

[0135] As described above, when a single-crystal AlN layer (hereinafter also referred to as HVPE-AlN) is formed on a single-crystal AlN layer (hereinafter also referred to as PVT-AlN layer) formed by the PVT method using the HVPE method to create a two-layer structure, strain tends to remain in the HVPE-AlN layer. More specifically, when a thick AlN film is grown on the PVT-AlN layer using the HVPE method, warping of the crystal lattice plane occurs with the C-plane convex downwards, and tensile strain is applied to the HVPE-AlN layer. When a semiconductor layer 13 is grown on the HVPE-AlN layer with such residual strain using the MOCVD method, it is thought that slip defects occur in order to relieve the strain in the HVPE-AlN layer during the heating and cooling process during growth. Furthermore, it is thought that the greater the thickness of the HVPE-AlN layer near the outer edge of the substrate in the comparative example, the more difficult it is for the strain to be relieved, and the more likely slip defects are to occur.

[0136] In this embodiment, by reducing the thickness of the HVPE-AlN layer 11B on the side surface S3 to 1 / 5 or less of the thickness of the PVT-AlN layer 11A, it is possible to remove areas where strain is particularly likely to remain, thereby suppressing the occurrence of linear defects.

[0137] Notwithstanding the above condition that the thickness of the HVPE-AlN layer 11B on the side surface S3 is 1 / 5 or less of the thickness of the PVT-AlN layer 11A, the thickness of the HVPE-AlN layer 11B on the side surface S3 is preferably 100 μm or less, and more preferably 50 μm or less, from the viewpoint of sufficiently reducing residual strain in order to suppress slip defects.

[0138] Furthermore, it is preferable that the inclined surface RP2 is inclined at an angle of 23° to 29° relative to the flat surface FS. In other words, the angle between the inclined surface RP2 and the flat surface FS is 23° or more and 29° or less (23°≦θa≦29° in Figure 7). For example, if the width of the inclined surface RP2 is 0.5mm to 0.6mm and the height is 0.25mm, then 23°≦θa≦29°.

[0139] Furthermore, it is preferable that the inclined surface RP2 is formed such that the distance d1 from the edge of the single crystal AlN substrate 11 is 0.45 mm or more and 0.75 mm (0.45 ≤ d1 ≤ 0.75), and the distance d2 from the flat surface FS in a direction perpendicular to the flat surface FS is 0.2 mm or more and 0.3 mm or less (0.2 ≤ d2 ≤ 0.3).

[0140] In this way, by forming the inclined surface RP2 to be inclined at an angle of 23° to 29° relative to the flat surface FS, or by satisfying the conditions 0.45≦d1≦0.75 and 0.2≦d2≦0.3, the width and height of the inclined surface RP2 can be secured. This is thought to prevent the acid solution from creeping up the side surface S3 and reaching the second surface S2 when only the flat surface FS of the single crystal AlN substrate 11 is immersed in the acid solution as a pretreatment for growing the semiconductor layer 13 of the semiconductor wafer 200. This prevents a decrease in device reliability caused by temperature unevenness during the growth of the semiconductor layer 13.

[0141] Specifically, a third example sample was prepared with a PVT-AlN layer 11A thickness d4=0.33mm, an HVPE-AlN layer 11B thickness of 0.22mm, d1=0.47mm, d2=0.20mm, and d3=0.02mm (6% of the PVT-AlN layer 11A thickness). It was confirmed that no irregularities were formed on the second surface S2, and that the leakage of the acid solution onto the second surface S2 was suppressed. Furthermore, no linear defects were observed in the semiconductor layer 13.

[0142] On the other hand, when a third comparative example sample was prepared with a PVT-AlN layer 11A thickness d4=0.25mm and an HVPE-AlN layer 11B thickness of 0.23mm, d1=0.28mm, d2=0.17mm, and d3=0.06mm (24% of the PVT-AlN layer 11A thickness), pyramidal irregularities were formed at the edge of the second surface, confirming that the acid solution had seeped into the second surface S2. In addition, linear defects occurred in the semiconductor layer 13.

[0143] As explained above, according to this embodiment, it is possible to prevent linear defects from occurring in the semiconductor wafer 200 having an inclined surface RP2. Therefore, it is possible to prevent a decrease in the reliability of the device.

[0144] Therefore, according to Example 2, it is possible to provide a single-crystal AlN substrate capable of manufacturing highly reliable semiconductor devices with a high yield, a semiconductor wafer using the single-crystal AlN substrate, and a method for manufacturing these.

[0145] [Differentiation] Referring to Figure 8, the configuration of the semiconductor wafer 200A according to a modified example of Embodiment 2 will be described. Figure 8 is a cross-sectional view showing the structure of the edge of the semiconductor wafer 200A according to this modified example.

[0146] The semiconductor wafer 200A is formed such that the inclined surface RP2 has zero thickness d3 of the HVPE-AlN layer 11B on the side surface S3 of the single-crystal AlN substrate 11. In other words, the semiconductor wafer 200A has the HVPE-AlN layer 11B completely removed on the side surface S3 of the single-crystal AlN substrate 11, and the ground surface reaches the PVT-AlN layer 11A. In other respects, the semiconductor wafer 200A is configured the same as the semiconductor wafer 200.

[0147] As described above, strain is likely to occur in the outer periphery during the growth of the HVPE-AlN layer 11B. According to this embodiment, it is possible to more reliably remove areas where strain is particularly likely to remain in the HVPE-AlN layer 11B, and it is believed that the occurrence of linear defects in the semiconductor wafer 200A can be suppressed.

[0148] Furthermore, in this modified example, it is preferable that the inclined surface RP2 is inclined at an angle of 23° to 29° with respect to the flat surface FS. In other words, the angle between the inclined surface RP2 and the flat surface FS is 23° or more and 29° or less (in Figure 7, 23° ≤ θa ≤ 29°).

[0149] Furthermore, in this modified example, it is preferable that the inclined surface RP2 is formed such that the distance d1 from the edge of the single crystal AlN substrate 11 is 0.45 mm or more and 0.75 mm or less (0.45 ≤ d1 ≤ 0.75), and the distance d2 from the flat surface FS in a direction perpendicular to the flat surface FS is 0.2 mm or more and 0.3 mm or less (0.2 ≤ d2 ≤ 0.3).

[0150] As a result, with respect to the semiconductor wafer 200A, the inclined surface RP2 prevents the acid solution from spreading to the second surface S2 during the pretreatment process when growing the semiconductor layer 13, thereby preventing a decrease in device reliability caused by temperature unevenness during the growth of the semiconductor layer 13.

[0151] Specifically, when a fourth example sample was prepared with a PVT-AlN layer 11A having a central layer thickness of 0.26 mm and an edge layer thickness d4=0.20 mm, and an HVPE-AlN layer 11B having a layer thickness of 0.25 mm, d1=0.69 mm, d2=0.31 mm, and d3=0 mm, it was possible to suppress the leakage of the acid solution to the second surface S2, and also to suppress the occurrence of linear defects in the semiconductor layer 13. [Examples]

[0152] The configuration of the semiconductor wafer 300 according to Example 3 will be described with reference to Figure 9. Figure 9 is a cross-sectional view showing the structure of the edge of the semiconductor wafer 300 according to Example 3.

[0153] The semiconductor wafer 300 is configured similarly to the semiconductor wafer 100 of Example 1 in that it has a single-layer single-crystal AlN substrate 21 instead of a single-layer single-crystal AlN substrate 11 having a multi-layer structure.

[0154] The single-crystal AlN substrate 21 is a single-layer single-crystal AlN substrate formed, for example, by the PVT method. The single-crystal AlN substrate 21 is constructed similarly to the single-crystal AlN substrate 21 of Example 1, except that it has a single-layer structure.

[0155] Therefore, the single-crystal AlN substrate 21 has a first surface S1 which is the top surface, a second surface S2 which is the bottom surface, and a side surface S3. The first surface S1 has a flat surface FS and an inclined surface RP. The flat surface FS is the Al polar surface, and the second surface S2 is the N polar surface.

[0156] The inclined surface RP is formed to slope downward from the outer edge of the flat surface FS toward the edge of the single-crystal AlN substrate 11, i.e., toward the side surface S3, in other words toward the second surface S2.

[0157] In this embodiment, the inclined surface RP is formed with the same dimensions as in Embodiment 1. Specifically, it is formed at a position of 0.45 mm or more and 0.75 mm or less from the edge of the single-crystal AlN substrate 11. In other words, the width d1 of the inclined surface RP in a top view, i.e., the distance d1 from the edge of the single-crystal AlN substrate 11 shown in Figure 9, is between 0.45 mm and 0.75 mm (0.45 ≤ d1 ≤ 0.75).

[0158] Furthermore, the inclined surface RP is formed at a position that is 0.2 mm or more and 0.3 mm or less from the flat surface FS in a direction perpendicular to the flat surface FS. In other words, the height d2 of the inclined surface RP, i.e., the distance d2 from the flat surface FS in the direction perpendicular to the flat surface FS shown in Figure 9, is between 0.2 mm and 0.3 mm (0.2 ≤ d2 ≤ 0.3).

[0159] The inclined surface RP having the dimensions d1 and d2 described above will be inclined with respect to the flat surface FS at an angle of 23° to 29°. In other words, the angle between the inclined surface RP and the flat surface FS is 23° or more and 29° or less (in Figure 9, 23° ≤ θa ≤ 29°).

[0160] With this configuration, in the semiconductor wafer 300 of this embodiment, when only the flat surface FS is immersed in the acid solution as a pretreatment for forming the semiconductor layer 13, the inclined surface RP prevents the acid solution from spreading to the side surface S3 and the second surface S2. Therefore, etching of a portion of the second surface S2 can be prevented, thus preventing a decrease in device reliability caused by temperature unevenness during the growth of the semiconductor layer 13.

[0161] Furthermore, according to this embodiment, it is possible to prevent linear defects from occurring in the semiconductor wafer 300 on which the semiconductor layer 13 is formed on the single-crystal AlN substrate 21. The single-crystal AlN substrate 21 has a single-layer structure, and although this is more pronounced in a two-layer structure consisting of, for example, a PVT-AlN layer and an HVPE-AlN layer, strain generated during the manufacturing of the single-crystal AlN substrate 21 may remain in the outer periphery. Therefore, by providing an inclined surface RP, it is possible to remove the parts where strain may have occurred. In this respect as well, it is possible to prevent a decrease in the reliability of the device.

[0162] Therefore, according to this embodiment, it is possible to provide an AlN single crystal substrate capable of forming highly reliable semiconductor devices with a high yield, a semiconductor wafer using the AlN single crystal substrate, and a method for manufacturing the same.

[0163] The configurations in the above-described examples and manufacturing methods are merely illustrative and can be modified as appropriate depending on the application.

[0164] For example, the semiconductor wafer using the single-crystal AlN substrate according to the above embodiment has been described as being applicable to the manufacture of ultraviolet light-emitting diodes (UV LEDs) as an ultraviolet semiconductor light-emitting element, but it is not limited to this. The semiconductor wafer according to the above embodiment may also be configured as a semiconductor wafer for ultraviolet semiconductor laser elements (UV LDs). Furthermore, the single-crystal AlN substrate and semiconductor wafer according to the above embodiment can be applied to electronic devices other than light-emitting elements, such as Schottky barrier diodes and HEMTs.

[0165] Furthermore, in the above embodiment, the diameter of the single-crystal AlN substrate can be approximately 45 to 100 mm, but is not limited to this. For example, it may be larger than 100 mm, and the appropriate thickness can be determined according to the diameter.

[0166] In the above examples, metal-organic chemical vapor phase deposition (MOCVD) may be used to fabricate the single-crystal AlN substrate; however, from the viewpoint of growth rate, it is more practical to use the PVT or HVPE method. [Explanation of Symbols]

[0167] 11, 21 Single-crystal AlN substrate 13 Semiconductor layer S1 First side S2 Second side S3 Side FS flat surface RP, RP2 Slope 100, 200, 300 semiconductor wafers

Claims

1. A single crystal AlN substrate having a first surface having a flat surface which is an Al polar surface and an inclined surface formed from the outer edge to the side surface of the flat surface, and a second surface which is the surface opposite to the first surface and is an N polar surface, A PVT-AlN layer formed by the PVT method, having a lower surface which is the second surface and a side surface, The material includes an HVPE-AlN layer formed on the upper surface of the PVT-AlN layer by the HVPE method, having an upper surface which is the flat surface and the inclined surface of the first surface, and a side surface which together with the side surface of the PVT-AlN layer forms the side surface of the single crystal AlN substrate, A single-crystal AlN substrate characterized in that, on the side surface of the single-crystal AlN substrate, the thickness of the HVPE-AlN layer is 1 / 5 or less of the thickness of the PVT-AlN layer.

2. The single crystal AlN substrate according to claim 1, characterized in that the angle between the inclined surface and the flat surface is 23° or more and 29° or less.

3. The single crystal AlN substrate according to claim 1 or 2, characterized in that the inclined surface is formed in a direction along the flat surface to a position where the distance from the edge of the single crystal AlN substrate is 0.45 mm or more and 0.75 mm or less, and in a direction perpendicular to the flat surface to a position where the distance from the flat surface is 0.2 mm or more and 0.3 mm or less.

4. The single crystal AlN substrate according to any one of claims 1 to 3, characterized in that the thickness of the HVPE-AlN layer at the edge of the single crystal AlN substrate is 100 μm or less.

5. The single crystal AlN substrate according to any one of claims 1 to 4, characterized in that the thickness of the HVPE-AlN layer at the edge of the single crystal AlN substrate is 50 μm or less.

6. On the single crystal AlN substrate according to any one of claims 1 to 5, an AlN layer and Al ｘ Ga １－ｘ A semiconductor wafer characterized by containing a multilayer film in which N (0.5 ≤ X ≤ 1) layers are stacked in this order.

7. The aforementioned Al ｘ Ga １－ｘ The semiconductor wafer according to claim 6, characterized in that the N (0.5 ≤ X ≤ 1) layer is a composition gradient layer in which the value of Al composition X decreases in the direction away from the single crystal AlN substrate.

8. A method for manufacturing a single crystal AlN substrate, Step (A) involves growing an HVPE-AlN layer on a PVT-AlN layer formed by the PVT method using the HVPE method to form a template substrate with an Al polar surface on the upper surface, The process includes chamfering (B) to chamfer the peripheral edge of the upper surface of the HVPE-AlN layer to form an inclined surface that slopes from the outer edge of the flat surface which is the Al polar surface to the side surface of the single crystal AlN substrate, A method for manufacturing a single-crystal AlN substrate, characterized in that, after the chamfering step (B), the thickness of the HVPE-AlN layer on the side surface of the single-crystal AlN substrate is 1 / 5 or less of the thickness of the PVT-AlN layer.

9. A method for manufacturing a semiconductor wafer in which a semiconductor layer is formed on a single-crystal AlN substrate, Step (A) involves growing an HVPE-AlN layer on a PVT-AlN layer formed by the PVT method using the HVPE method to form a template substrate with an Al polar surface on the upper surface, Chamfering step (B) involves chamfering the peripheral edge of the upper surface of the HVPE-AlN layer to form an inclined surface that slopes from the outer edge of the flat surface which is the Al polar surface to the side surface of the single crystal AlN substrate, After the chamfering step (B), an immersion treatment step (C) is performed in which the upper surface of the HVPE-AlN layer is immersed in an acid solution. After the immersion treatment step (C), an AlN layer is placed on the HVPE-AlN layer by the MOCVD method, and Al ｘ Ga １－ｘ The process includes (D) a step of forming a laminated film in which N (0.5 ≤ X ≤ 1) layers are stacked in this order, A method for manufacturing a semiconductor wafer, characterized in that, after the chamfering step (B), the thickness of the HVPE-AlN layer on the side surface of the single crystal AlN substrate is 1 / 5 or less of the thickness of the PVT-AlN layer.

10. The method for manufacturing a semiconductor wafer according to claim 9, characterized in that, in the immersion treatment step (C), the lower surface of the PVT-AlN layer is exposed from the acid solution.

11. A single crystal AlN substrate having a first surface having a flat surface which is an Al polar surface and an inclined surface formed from the outer edge of the flat surface to the side surface, and a second surface which is the surface opposite to the first surface and is an N polar surface, A PVT-AlN layer formed by the PVT method, having a lower surface which is the second surface and a side surface, The HVPE-AlN layer is formed on the upper surface of the PVT-AlN layer by the HVPE method and has an upper surface consisting of a part of the inclined surface of the first surface and the flat surface, A single-crystal AlN substrate characterized in that the inclined surface is formed from the outer edge of the flat surface to the side surface of the PVT-AlN layer.

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