Method for manufacturing a display device

Abstract

To provide a display device capable of improving the reliability thereof.SOLUTION: A method of manufacturing a display device according to one embodiment includes: forming a first lower electrode above a substrate; forming an insulating layer covering the first lower electrode; forming a partition including a lower portion on the insulating layer and an upper portion projecting from a side surface of the lower portion; forming, after the forming of the partition, a first pixel aperture overlapping the first lower electrode in the insulating layer; forming a first organic layer in contact with the first lower electrode via the first pixel aperture; forming a first upper electrode covering the first organic layer; and patterning the first organic layer and the first upper electrode to form a first display element including the first lower electrode, the first organic layer and the first upper electrode.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. This display element includes a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0003] When manufacturing a display device, various elements are formed by etching. If other elements are damaged during the etching of a certain element, the reliability of the display device may decrease.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a display device capable of improving reliability.

Means for Solving the Problems

[0006] In a method for manufacturing a display device according to one embodiment, a first lower electrode is formed on a substrate, an insulating layer is formed to cover the first lower electrode, a partition wall is formed having a lower part located on the insulating layer and an upper part protruding from the side surface of the lower part, after the partition wall is formed, a first pixel aperture overlapping the first lower electrode is formed in the insulating layer, a first organic layer is formed that contacts the first lower electrode through the first pixel aperture, a first upper electrode is formed to cover the first organic layer, and the first organic layer and the first upper electrode are patterned to form a first display element including the first lower electrode, the first organic layer and the first upper electrode. The formation of the partition wall includes forming a metal layer above the insulating layer and forming the lower part by wet etching the metal layer.

[0007] In a method for manufacturing a display device according to another aspect of the embodiment, a lower electrode located in a display area and a power supply line located in a peripheral area outside the display area are formed on a substrate, an insulating layer is formed to cover the lower electrode and the power supply line, a contact opening overlapping with the power supply line is formed in the insulating layer, after the contact opening is formed, a partition wall located on the insulating layer in the display area and a conductive layer in the peripheral area that contacts the power supply line through the contact opening are formed, after the partition wall and the conductive layer are formed, a pixel opening overlapping with the lower electrode is formed in the insulating layer, an organic layer that contacts the lower electrode through the pixel opening is formed, and an upper electrode covering the organic layer is formed. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of the configuration of a display device according to one embodiment. [Figure 2] Figure 2 shows an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of the partition wall and its vicinity, magnified. [Figure 5] Figure 5 is a schematic plan view of the area near the boundary between the display area and the surrounding area. [Figure 6]FIG. 6 is a schematic cross-sectional view of a display area and a peripheral area. [Figure 7] FIG. 7 is a flowchart showing an example of a method for manufacturing a display device. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a part of the manufacturing process of a display device. [Figure 9] FIG. 9 is a schematic cross-sectional view showing the manufacturing process following FIG. 8. [Figure 10] FIG. 10 is a schematic cross-sectional view showing the manufacturing process following FIG. 9. [Figure 11] FIG. 11 is a schematic cross-sectional view showing the manufacturing process following FIG. 10. [Figure 12] FIG. 12 is a schematic cross-sectional view showing the manufacturing process following FIG. 11. [Figure 13] FIG. 13 is a schematic cross-sectional view showing the manufacturing process following FIG. 12. [Figure 14] FIG. 14 is a schematic cross-sectional view showing the manufacturing process following FIG. 13. [Figure 15] FIG. 15 is a schematic cross-sectional view showing the manufacturing process following FIG. 14. [Figure 16] FIG. 16 is a schematic cross-sectional view showing the manufacturing process of forming a contact opening in a peripheral area. [Figure 17] FIG. 17 is a schematic cross-sectional view showing the manufacturing process of removing an insulating layer covering a dam portion and a terminal portion in a peripheral area. [Figure 18] FIG. 18 is a schematic cross-sectional view showing the manufacturing process of forming a first display element. [Figure 19] FIG. 19 is a schematic cross-sectional view showing the manufacturing process following FIG. 18. [Figure 20] FIG. 20 is a schematic cross-sectional view showing the manufacturing process following FIG. 19. [Figure 21] FIG. 21 is a schematic cross-sectional view showing the manufacturing process following FIG. 20. [Figure 22] FIG. 22 is a schematic cross-sectional view showing the manufacturing process of forming a second display element. [Figure 23]Figure 23 is a schematic cross-sectional view showing the manufacturing process for forming the third display element. [Modes for carrying out the invention]

[0009] One embodiment will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0010] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction, the direction along the Y axis as the second direction, and the direction along the Z axis as the third direction. Viewing the various elements parallel to the third direction Z is called a plan view.

[0011] The display device according to this embodiment is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted in televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and the like.

[0012] Figure 1 shows an example configuration of a display device DSP according to this embodiment. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0013] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle; it may be a square, a circle, an ellipse, or other shape.

[0014] The display area DA comprises multiple pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes multiple sub-pixels SP. In one example, pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. Pixel PX may also include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of SP1, SP2, or SP3.

[0015] The sub-pixel SP comprises a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0016] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element 20.

[0017] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0018] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element. For example, sub-pixel SP1 is equipped with a display element 20 that emits light in the red wavelength range, sub-pixel SP2 is equipped with a display element 20 that emits light in the green wavelength range, and sub-pixel SP3 is equipped with a display element 20 that emits light in the blue wavelength range.

[0019] A terminal section T is provided in the peripheral region SA. The terminal section T is connected to the circuit board of an electronic device on which a display device DSP is mounted, for example, via a flexible circuit board. Video signals and driving power for displaying images are input to the display device DSP via the terminal section T.

[0020] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP1 and SP2 are aligned in the second direction Y. Furthermore, sub-pixels SP1 and SP2 are aligned with sub-pixel SP3 in the first direction X.

[0021] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0022] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. Another example is that the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.

[0023] The display area DA has ribs 5 and partition walls 6. Ribs 5 have pixel apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel aperture AP2 is larger than pixel aperture AP1, and pixel aperture AP3 is larger than pixel aperture AP2.

[0024] The partition wall 6 is positioned at the boundary between adjacent subpixels SP and overlaps with the rib 5 in a plan view. The partition wall 6 has a plurality of first partition walls 6x extending in the first direction X and a plurality of second partition walls 6y extending in the second direction Y. The plurality of first partition walls 6x are positioned between adjacent pixel apertures AP1 and AP2 in the second direction Y, and between two adjacent pixel apertures AP3 in the second direction Y. The second partition walls 6y are positioned between adjacent pixel apertures AP1 and AP3 in the first direction X, and between adjacent pixel apertures AP2 and AP3 in the first direction X.

[0025] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole forms a grid surrounding the pixel apertures AP1, AP2, and AP3. It can also be said that the partition wall 6, like the rib 5, has apertures in the sub-pixels SP1, SP2, and SP3.

[0026] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3. In the example in Figure 2, the outer shapes of the upper electrode UE1 and organic layer OR1 match, the outer shapes of the upper electrode UE2 and organic layer OR2 match, and the outer shapes of the upper electrode UE3 and organic layer OR3 match.

[0027] The lower electrode LE1, upper electrode UE1, and organic layer OR1 constitute the display element 20 of the sub-pixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 constitute the display element 20 of the sub-pixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 constitute the display element 20 of the sub-pixel SP3.

[0028] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0029] In the example in Figure 2, contact holes CH1 and CH2 completely overlap with the first partition wall 6x between adjacent pixel apertures AP1 and AP2 in the second direction Y. Contact hole CH3 completely overlaps with the first partition wall 6x between two adjacent pixel apertures AP3 in the second direction Y. In another example, at least a portion of contact holes CH1, CH2, and CH3 may not overlap with the first partition wall 6x.

[0030] In the example shown in Figure 2, the lower electrodes LE1 and LE2 each have protrusions PR1 and PR2. Protrusion PR1 protrudes from the main body of the lower electrode LE1 (the part that overlaps with the pixel aperture AP1) toward the contact hole CH1. Protrusion PR2 protrudes from the main body of the lower electrode LE2 (the part that overlaps with the pixel aperture AP2) toward the contact hole CH2. The contact holes CH1 and CH2 overlap with the protrusions PR1 and PR2, respectively.

[0031] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11. Although not shown in the cross-section of Figure 3, the contact holes CH1, CH2, and CH3 described above are provided in the organic insulating layer 12.

[0032] The lower electrodes LE1, LE2, and LE3 are positioned on top of the organic insulating layer 12. The ribs 5 are positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5.

[0033] The bulkhead 6 includes a lower section 61 positioned on the rib 5 and an upper section 62 positioned on top of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, in Figure 3, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of the bulkhead 6 can also be described as overhanging.

[0034] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3.

[0035] In the example shown in Figure 3, cap layer CP1 is placed on organic layer OR1, cap layer CP2 is placed on organic layer OR2, and cap layer CP3 is placed on organic layer OR3. Cap layers CP1, CP2, and CP3 adjust the optical properties of the light emitted by organic layers OR1, OR2, and OR3, respectively.

[0036] A portion of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is located above the upper section 62. This portion is separated from the other portions of the organic layer OR1, the upper electrode UE1, and the cap layer CP1. Similarly, a portion of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 is located above the upper section 62, and this portion is separated from the other portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2. Furthermore, a portion of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 is located above the upper section 62, and this portion is separated from the other portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3.

[0037] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE1, SE2, and SE3, respectively. Sealing layer SE1 continuously covers the cap layer CP1 and the partition wall 6. Sealing layer SE2 continuously covers the cap layer CP2 and the partition wall 6. Sealing layer SE3 continuously covers the cap layer CP3 and the partition wall 6.

[0038] In the example shown in Figure 3, the organic layer OR1, upper electrode UE1, cap layer CP1, and sealing layer SE1 on the partition wall 6 between sub-pixels SP1 and SP3 are separated from the organic layer OR3, upper electrode UE3, cap layer CP3, and sealing layer SE3 on the same partition wall 6. Similarly, the organic layer OR2, upper electrode UE2, cap layer CP2, and sealing layer SE2 on the partition wall 6 between sub-pixels SP2 and SP3 are separated from the organic layer OR3, upper electrode UE3, cap layer CP3, and sealing layer SE3 on the same partition wall 6.

[0039] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 13. The resin layer 13 is covered by a sealing layer 14. Furthermore, the sealing layer 14 is covered by a resin layer 15.

[0040] The organic insulating layer 12 and the resin layers 13 and 15 are formed from organic materials.

[0041] The ribs 5 and sealing layers 14, SE1, SE2, and SE3 are formed from inorganic materials such as silicon nitride (SiNx). Ribs 5 may be formed as a single layer of silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Alternatively, ribs 5 may be formed as a laminate of at least two combinations of silicon nitride layers, silicon oxide layers, silicon oxynitride layers, and aluminum oxide layers.

[0042] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material, such as a magnesium-silver alloy (MgAg). When the potential of the lower electrodes LE1, LE2, and LE3 is relatively higher than the potential of the upper electrodes UE1, UE2, and UE3, the lower electrodes LE1, LE2, and LE3 act as the anode, and the upper electrodes UE1, UE2, and UE3 act as the cathode. Also, when the potential of the upper electrodes UE1, UE2, and UE3 is relatively higher than the potential of the lower electrodes LE1, LE2, and LE3, the upper electrodes UE1, UE2, and UE3 act as the anode, and the lower electrodes LE1, LE2, and LE3 act as the cathode.

[0043] The organic layers OR1, OR2, and OR3 include a pair of functional layers and an emissive layer disposed between these functional layers. As an example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in that order.

[0044] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of multiple transparent thin films. The multilayer structure may include thin films formed from inorganic materials and thin films formed from organic materials. These multiple thin films have different refractive indices. The materials of the thin films constituting the multilayer structure are different from the materials of the upper electrodes UE1, UE2, and UE3, and also different from the materials of the sealing layers SE1, SE2, and SE3. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0045] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the side surface of the lower part 61. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0046] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the blue wavelength range.

[0047] Figure 4 is a schematic, enlarged cross-sectional view of the partition wall 6 located at the boundary between sub-pixels SP1 and SP2 and its vicinity. In this figure, the substrate 10, circuit layer 11, resin layer 13, sealing layer 14, and resin layer 15 are omitted.

[0048] The lower part 61 of the partition wall 6 has a side surface F1 and a side surface F2. The upper part 62 of the partition wall 6 has an end surface E1 protruding from side surface F1 and an end surface E2 protruding from side surface F2. The upper electrodes UE1 and UE3 are in contact with side surfaces F1 and F2, respectively.

[0049] In the example shown in Figure 4, the lower part 61 has a first metal layer 611 placed on the rib 5 and a second metal layer 612 placed on the first metal layer 611. The upper part 62 has a first thin film 621 placed on the second metal layer 612 and a second thin film 622 placed on the first thin film 621.

[0050] The first metal layer 611 is formed of, for example, molybdenum (Mo). The second metal layer 612 is formed of, for example, aluminum (Al) and is thicker than the first metal layer 611. The second metal layer 612 may be formed of an aluminum alloy, or it may have a laminated structure of aluminum and an aluminum alloy.

[0051] The first thin film 621 is formed of, for example, titanium (Ti). The first thin film 621 may also be formed of an inorganic material such as silicon oxide. The second thin film 622 is formed of a transparent conductive oxide such as ITO (IndiumTin Oxide), IZO (IndiumZinc Oxide), and IGZO (IndiumGalliumZinc Oxide). The upper part 62 may have a single-layer structure of titanium or silicon oxide.

[0052] In the example shown in Figure 4, the lower electrode LE1 has a silver layer L1 formed of silver (Ag), a first conductive oxide layer L2 covering the upper surface of the silver layer L1, and a second conductive oxide layer L3 covering the lower surface of the silver layer L1. The conductive oxide layers L2 and L3 can be formed from, for example, ITO, IZO, or IGZO. The lower electrodes LE2 and LE3 have a similar configuration to the lower electrode LE1. For example, the first conductive oxide layer L2 is thinner than the silver layer L1 and the second conductive oxide layer L3. Specifically, the thickness of the silver layer L1 and the second conductive oxide layer L3 is about 100 nm, and the thickness of the first conductive oxide layer L2 is about 10 nm.

[0053] Figure 5 is a schematic plan view of the area near the boundary between the display area DA and the surrounding area SA. The display area DA contains partition walls 6 (first partition wall 6x and second partition wall 6y). The surrounding area SA contains a conductive layer CL connected to partition walls 6. The conductive layer CL and partition walls 6 are integrally formed from the same material using the same manufacturing process.

[0054] The power supply line PW is located in the surrounding area SA. The conductive layer CL is connected to the power supply line PW through multiple contact sections CN. For example, the multiple contact sections CN are arranged to surround the display area DA.

[0055] In the example in Figure 5, the display area DA and the surrounding area SA are aligned in the second direction Y. In such areas, the contact portion CN has an elongated shape in the second direction Y and is aligned in the first direction X. For example, in areas where the display area DA and the surrounding area SA are aligned in the first direction X, the contact portion CN has an elongated shape in the first direction X and is aligned in the second direction Y.

[0056] Figure 6 is a schematic cross-sectional view of the display area DA and the surrounding area SA. In this figure, the organic layers OR1, OR2, OR3, upper electrodes UE1, UE2, UE3, cap layers CP1, CP2, CP3, sealing layers SE1, SE2, SE3, resin layer 13, sealing layer 14, and resin layer 15 are omitted.

[0057] The circuit layer 11 comprises insulating layers 31, 32, 33 and metal layers 41, 42, 43. The insulating layer 31 covers the substrate 10. The metal layer 41 is placed on top of the insulating layer 31 and covered by the insulating layer 32. The metal layer 42 is placed on top of the insulating layer 32 and covered by the insulating layer 33. The metal layer 43 is placed on top of the insulating layer 33 and covered by the organic insulating layer 12.

[0058] The metal layers 41, 42, and 43, together with semiconductor layers (not shown), constitute a gate drive circuit that supplies a scanning signal to the scan line GL, a selector circuit that supplies a video signal to the signal line SL, and so on. In the example in Figure 6, the terminal portion T is formed by the metal layer 41. For example, the metal layer 41 has a laminated structure of titanium, aluminum, and titanium. The terminal portion T may be formed by the metal layer 42 or the metal layer 43, or by conductive layers other than the metal layers 41, 42, and 43.

[0059] Rib 5 is also located in the surrounding region SA. The conductive layer CL is located on top of rib 5. The conductive layer CL includes a lower section 61 and an upper section 62, similar to the partition wall 6 shown in Figures 3 and 4.

[0060] The feed line PW is positioned between the organic insulating layer 12 and the rib 5. The feed line PW is connected to, for example, a portion of the metal layer 43. A common voltage is applied to the feed line PW. The feed line PW is formed by, for example, the same manufacturing process as the lower electrodes LE1, LE2, LE3, and has a silver layer L1 and conductive oxide layers L2, L3 as shown in Figure 4. The rib 5 has a contact opening APc in the contact portion CN. The conductive layer CL is connected to the feed line PW through the contact opening APc.

[0061] In the peripheral region SA, a dam portion DP is positioned between the terminal portion T and the conductive layer CL. The dam portion DP has multiple protrusions R1, R2, R3, and R4. The protrusions R1, R2, R3, and R4 are formed using the same material and process as, for example, the organic insulating layer 12. In the example shown in Figure 6, no ribs 5 are positioned on the dam portion DP or the terminal portion T, and the protrusions R1, R2, R3, and R4 are all positioned on the insulating layer 33.

[0062] For example, the protrusions R1, R2, R3, and R4 form a frame that surrounds the display area DA and the conductive layer CL in a plan view. The resin layer 13 shown in Figure 3 is formed, for example, by an inkjet method. The dam portion DP suppresses the spreading of the resin layer 13 before hardening. Note that the number of protrusions on the dam portion DP is not limited to four.

[0063] Next, we will explain the manufacturing method of the DSP display device. Figure 7 is a flowchart showing an example of a manufacturing method for a display device DSP. Figures 8 to 23 are schematic cross-sectional views showing part of the manufacturing process for a display device DSP. Of these figures, Figures 8 to 15 and Figures 18 to 23 show part of the display area DA, while Figures 16 to 19 mainly show part of the peripheral area SA.

[0064] In this embodiment, the sub-pixels SP1, SP2, and SP3 display elements 20 are formed by separate processes. The formation order of the sub-pixels SP1, SP2, and SP3 display elements 20 is not particularly limited, but for the sake of explanation, the sub-pixel in which the first display element 20 is formed is called the first sub-pixel SPα, the sub-pixel in which the second display element 20 is formed is called the second sub-pixel SPβ, and the sub-pixel in which the third display element 20 is formed is called the third sub-pixel SPγ.

[0065] Furthermore, the lower electrode, organic layer, upper electrode, cap layer, sealing layer, pixel aperture, and display element of the first sub-pixel SPα are referred to as the first lower electrode LEα, the first organic layer ORα, the first upper electrode UEα, the first cap layer CPα, the first sealing layer SEα, the first pixel aperture APα, and the first display element 20α. The lower electrode, organic layer, upper electrode, cap layer, sealing layer, pixel aperture, and display element of the second sub-pixel SPβ are referred to as the second lower electrode LEβ, the second organic layer ORβ, the second upper electrode UEβ, the second cap layer CPβ, the second sealing layer SEβ, the second pixel aperture APβ, and the second display element 20β. The lower electrode, organic layer, upper electrode, cap layer, sealing layer, pixel aperture, and display element of the third sub-pixel SPγ are referred to as the third lower electrode LEγ, the third organic layer ORγ, the third upper electrode UEγ, the third cap layer CPγ, the third sealing layer SEγ, the third pixel aperture APγ, and the third display element 20γ.

[0066] In the manufacturing of a display device DSP, a circuit layer 11 and an organic insulating layer 12 are first formed on the substrate 10 (step P1 in Figure 7). At this time, terminal portions T and protrusions R1, R2, R3, and R4 are also formed.

[0067] After step P1, as shown in Figure 8, the first lower electrode LEα and the second lower electrode LEβ are formed on the organic insulating layer 12 (above the substrate 10) (step P2 in Figure 7). At this time, the third lower electrode LEγ and the power supply line PW are also formed.

[0068] After step P2, an insulating layer 5a, which will form the base of the rib 5, is formed as shown in Figure 9 (step P3 in Figure 7). The insulating layer 5a is made of an inorganic material such as silicon nitride and covers the first lower electrode LEα, the second lower electrode LEβ, the third lower electrode LEγ, and the power supply line PW.

[0069] After step P3, as shown in Figure 16, a contact opening APc is formed in the peripheral region SA (step P4 in Figure 7). During the formation of the contact opening APc, resist RG1 is placed on the insulating layer 5a. Furthermore, the portion of resist RG1 facing the contact opening APc is removed. By performing dry etching using this resist RG1 as a mask, the contact opening APc is formed in the insulating layer 5a. After dry etching, resist RG1 is removed.

[0070] In step P4, the entire display area DA, the dam portion DP, and the terminal portion T are covered by the insulating layer 5a and the resist RG1. Therefore, even after step P4, the lower electrodes LEα, LEβ, LEγ, the protrusions R1, R2, R3, R4, and the terminal portion T are not exposed from the insulating layer 5a.

[0071] After step P4, the partition wall 6 and the conductive layer CL are formed (step P5 in Figure 7). Specifically, as shown in Figure 10, first a first metal layer 611a is formed on the insulating layer 5a, a second metal layer 612a is formed on the first metal layer 611a, a first thin film 621a is formed on the second metal layer 612a, and a second thin film 622a is formed on the first thin film 621a.

[0072] Next, as shown in Figure 11, a resist RG2 corresponding to the shape of the partition wall 6 and the conductive layer CL is formed on the second thin film 622a. Furthermore, by etching using the resist RG2 as a mask, the portions of the second thin film 622a, the first thin film 621a, and the second metal layer 612a exposed from the resist RG2 are removed. As a result, the upper part 62 including the first thin film 621 and the second thin film 622 is formed, as shown in Figure 12. In the example in Figure 12, a portion of the second metal layer 612a exposed from the resist RG2 remains. For example, the etching of the second thin film 622a is wet etching, and the etching of the first thin film 621a and the second metal layer 612a is anisotropic dry etching.

[0073] Next, isotropic wet etching is performed. For example, an etching solution containing phosphoric acid, nitric acid, and acetic acid is used for this wet etching. As shown in Figure 13, this wet etching removes the portions of the second metal layer 612a and the first metal layer 611a that are exposed from the resist RG2, forming a lower section 61 that includes the second metal layer 612 and the first metal layer 611. In this wet etching, the sides of the second metal layer 612 and the first metal layer 611 are also eroded. As a result, the width of the lower section 61 becomes smaller than the width of the upper section 62, and an overhanging partition wall 6 and a conductive layer CL are obtained. The conductive layer CL contacts the power supply line PW through the contact opening APc formed in step P4. After wet etching, the resist RG2 is removed.

[0074] After the formation of the partition wall 6 and the conductive layer CL, pixel apertures APα, APβ, and APγ are formed (step P6 in Figure 7). Specifically, as shown in Figure 14, a resist RG3 is formed that covers the partition wall 6 and the insulating layer 5a in its vicinity. Dry etching using this resist RG3 as a mask removes the portion of the insulating layer 5a exposed from the resist RG3. That is, as shown in Figure 15, the first pixel aperture APα overlapping the first lower electrode LEα and the second pixel aperture APβ overlapping the second lower electrode LEβ are formed. Although not shown in the cross-section of Figure 15, the third pixel aperture APγ overlapping the third lower electrode LEγ is formed in the same way. As a result, ribs 5 with the shapes shown in Figures 2 to 4 are formed.

[0075] In step P6, the portions of the insulating layer 5a located at the dam portion DP and the terminal portion T are also removed. That is, as shown in Figure 17, the resist RG3 covers the conductive layer CL and the insulating layer 5a in its vicinity, but does not cover the dam portion DP and the terminal portion T. As a result, the insulating layer 5a covering the dam portion DP (protrusions R1, R2, R3, R4) and the terminal portion T is removed by dry etching when forming the pixel apertures APα, APβ, APγ.

[0076] After step P6, as shown in Figure 18, a first organic layer ORα that contacts the first lower electrode LEα through the first pixel aperture APα, a first upper electrode UEα covering the first organic layer ORα, a first cap layer CPα covering the first upper electrode UEα, and a first sealing layer SEα covering the first cap layer CPα are sequentially formed by vapor deposition (step P7 in Figure 7). These first organic layer ORα, first upper electrode UEα, first cap layer CPα, and first sealing layer SEα are formed over at least the entire display area DA and are located not only on the first sub-pixel SPα but also on the second sub-pixel SPβ and the third sub-pixel SPγ.

[0077] After step P7, the first organic layer ORα, the first upper electrode UEα, the first cap layer CPα, and the first sealing layer SEα are patterned (step P8 in Figure 7). Specifically, as shown in Figure 19, the resist RG4 is first placed on top of the first sealing layer SEα. The resist RG4 is located directly above the first lower electrode LEα. The resist RG4 is also located directly above the portion of the partition wall 6 between subpixels SPα and SPβ that is closer to the first subpixel SPα, and directly above the portion of the partition wall 6 between subpixels SPα and SPγ that is closer to the first subpixel SPα.

[0078] Next, as shown in Figure 20, the portions of the first organic layer ORα, the first upper electrode UEα, the first cap layer CPα, and the first sealing layer SEα that are exposed from the resist RG4 are removed by etching using the resist RG4 as a mask. Subsequently, as shown in Figure 21, the first display element 20α, including the first organic layer ORα, the first upper electrode UEα, the first cap layer CPα, and the first sealing layer SEα, is completed by removing the resist RG4.

[0079] Following step P8, a second organic layer ORβ that contacts the second lower electrode LEβ through the second pixel aperture APβ, a second upper electrode UEβ covering the second organic layer ORβ, a second cap layer CPβ covering the second upper electrode UEβ, and a second sealing layer SEβ covering the second cap layer CPβ are sequentially formed by vapor deposition (step P9 in Figure 7). Furthermore, by patterning similar to that in step P8, a second display element 20β including the second organic layer ORβ, the second upper electrode UEβ, the second cap layer CPβ, and the second sealing layer SEβ is formed on the second sub-pixel SPβ as shown in Figure 22 (step P10 in Figure 7).

[0080] After step P10, a third organic layer ORγ that contacts the third lower electrode LEγ through the third pixel aperture APγ, a third upper electrode UEγ covering the third organic layer ORγ, a third cap layer CPγ covering the third upper electrode UEγ, and a third sealing layer SEγ covering the third cap layer CPγ are sequentially formed by vapor deposition (step P11 in Figure 7). Furthermore, by patterning similar to step P8, a third display element 20γ including the third organic layer ORγ, the third upper electrode UEγ, the third cap layer CPγ, and the third sealing layer SEγ is formed on the third sub-pixel SPγ as shown in Figure 23 (step P12 in Figure 7).

[0081] After the display elements 20α, 20β, and 20γ are formed in this manner, the resin layer 13, sealing layer 14, and resin layer 15 shown in Figure 3 are formed in sequence, completing the display device DSP (step P13 in Figure 7).

[0082] In the manufacturing method of the DSP display device according to the present embodiment described above, after the partition wall 6 is formed on the insulating layer 5a (rib 5), pixel apertures APα, APβ, and APγ are formed on the insulating layer 5a. If the pixel apertures APα, APβ, and APγ are formed before the formation of the partition wall 6, the lower electrodes LEα, LEβ, and LEγ are exposed to the etching solution during wet etching of the first metal layer 611 and the second metal layer 612 (see Figure 13). At this time, if defects such as fine pinholes occur in the first conductive oxide layer L2 of the lower electrodes LEα, LEβ, and LEγ, the etching solution may erode the silver layer L1 through these defects.

[0083] In contrast, when the pixel apertures APα, APβ, and APγ are formed after the partition wall 6, as in this embodiment, the lower electrodes LEα, LEβ, and LEγ are covered by the insulating layer 5a during the wet etching process. Therefore, erosion of the silver layer L1 by the etching solution can be suppressed. As a result, display defects in the display elements 20α, 20β, and 20γ can be suppressed, and the reliability of the display device DSP can be improved.

[0084] In this embodiment, the portion of the insulating layer 5a that covers the dam portion DP and the terminal portion T is also removed after the formation of the partition wall 6. This makes it possible to suppress the erosion of the terminal portion T during the wet etching process.

[0085] Furthermore, in this embodiment, a contact opening APc is formed in the insulating layer 5a before the partition wall 6 and the conductive layer CL are formed. This makes it possible to obtain a power supply structure in which the conductive layer CL and the power supply line PW are in contact. In addition, various other desirable effects can be obtained from this embodiment.

[0086] All display devices and manufacturing methods that a person skilled in the art can implement by appropriately modifying the design based on the display device and manufacturing method described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0087] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of any of the above-described embodiments, or to add, omit, or change the conditions of any process, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0088] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0089] DSP...Display device, DA...Display area, SA...Peripheral area, PX...Pixel, SP...Sub-pixel, LE...Lower electrode, OR...Organic layer, UE...Upper electrode, SE...Sealing layer, PW...Power supply line, T...Terminal section, DP...Dam section, 5...Rib, 5a...Insulating layer, 6...Partition wall, 10...Substrate, 61...Lower part of partition wall, 62...Upper part of partition wall.

Claims

1. A first lower electrode is formed above the substrate. An insulating layer is formed to cover the first lower electrode. A partition wall is formed having a lower part located on the insulating layer and an upper part protruding from the side surface of the lower part. After forming the partition wall, a first pixel aperture overlapping the first lower electrode is formed in the insulating layer. A first organic layer is formed that contacts the first lower electrode through the first pixel aperture. A first upper electrode is formed to cover the first organic layer. The first organic layer and the first upper electrode are patterned to form a first display element including the first lower electrode, the first organic layer, and the first upper electrode. This includes, The formation of the aforementioned partition wall is A metal layer is formed above the insulating layer. The lower part is formed by wet etching the metal layer. A method for manufacturing a display device, including the following.

2. The aforementioned first lower electrode has a silver layer and a conductive oxide layer covering the silver layer. A method for manufacturing a display device according to claim 1.

3. The aforementioned metal layer contains aluminum, A method for manufacturing a display device according to claim 1.

4. The insulating layer is formed of an inorganic material. A method for manufacturing a display device according to any one of claims 1 to 3.

5. The insulating layer is formed of silicon nitride. A method for manufacturing a display device according to claim 4.

6. Together with the first lower electrode, a second lower electrode is formed above the substrate. A second pixel aperture, which overlaps with the second lower electrode, is formed in the insulating layer along with the first pixel aperture. After forming the first display element, a second layer is formed that contacts the second lower electrode through the second pixel aperture. A second upper electrode is formed to cover the second organic layer. The second organic layer and the second upper electrode are patterned to form a second display element including the second lower electrode, the second organic layer, and the second upper electrode. A method for manufacturing a display device according to any one of claims 1 to 5.

7. A third lower electrode is formed above the substrate, together with the first lower electrode and the second lower electrode. A third pixel aperture overlapping with the third lower electrode is formed in the insulating layer, along with the first and second pixel apertures. After forming the first display element and the second display element, a third layer is formed that contacts the third lower electrode through the third pixel aperture. A third upper electrode is formed to cover the aforementioned third organic layer. The third organic layer and the third upper electrode are patterned to form a third display element including the third lower electrode, the third organic layer, and the third upper electrode. A method for manufacturing a display device according to claim 6.

8. A power supply line covered by the insulating layer is formed in the peripheral region outside the display area including the first lower electrode. Before forming the partition wall, a contact opening overlapping the power supply line is formed in the insulating layer. Together with the partition wall, a conductive layer is formed that contacts the power supply line through the contact opening. A method for manufacturing a display device according to any one of claims 1 to 7.

9. A dam portion is formed in the peripheral region outside the display area including the first lower electrode, surrounding the display area and covered by the insulating layer. After forming the partition wall, remove the insulating layer covering the dam section. A method for manufacturing a display device according to any one of claims 1 to 7.

10. A terminal portion covered by the insulating layer is formed in the peripheral region outside the display area including the first lower electrode. After forming the partition wall, remove the insulating layer covering the terminal portion. A method for manufacturing a display device according to any one of claims 1 to 7.

11. A lower electrode located in the display area and a power supply line located in the peripheral area outside the display area are formed on the upper part of the substrate. An insulating layer is formed to cover the lower electrode and the power supply line. A contact opening overlapping with the power supply line is formed in the insulating layer. After forming the contact opening, a partition wall located on the insulating layer in the display area and a conductive layer in the peripheral area that contacts the power supply line through the contact opening are formed. After forming the partition wall and the conductive layer, a pixel aperture overlapping the lower electrode is formed in the insulating layer. An organic layer is formed that contacts the lower electrode through the pixel aperture. A top electrode is formed covering the organic layer. A method for manufacturing a display device.

12. The power supply line has a silver layer and a conductive oxide layer covering the silver layer. A method for manufacturing a display device according to claim 11.

13. The formation of the aforementioned partition wall is A metal layer is formed above the insulating layer. The aforementioned metal layer is wet-etched. Including, A method for manufacturing a display device according to claim 11 or 12.

14. The aforementioned metal layer contains aluminum, A method for manufacturing a display device according to claim 13.

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