Methods for manufacturing integrated circuits (ICs), integrated circuit packages (ICs), and integrated circuit assemblies.

Abstract

To provide an IC assembly, an IC package, and a method of manufacturing the IC assembly that allows a larger number of memory or logic devices to be incorporated on a chip and has increased capacity.SOLUTION: In an IC assembly 600 based on the use of a transistor with a backside contact, the transistor with the backside contact allows backside powering to an IC component such as a transistor in the IC structures. This is an advantage over front side power supply in some implementations. Furthermore, using a glass support structure 450 on the front side of the IC structure with backside powering advantageously reduces parasitic effects in the IC structure compared to using the silicon-based support structure of the front side.SELECTED DRAWING: Figure 6

Description

[Background technology]

[0001] For decades, feature scaling in integrated circuits has been a driving force behind the continued growth of the semiconductor industry. Scaling to smaller features allows for increased density of functional units on a limited area of ​​a semiconductor chip. For example, reducing the size of transistors makes it possible to incorporate more memory or logic devices on a chip, resulting in the manufacture of products with increased capacity. However, the efforts to continue increasing capacity are not without their challenges. The requirements for optimizing the performance of each device and each interconnect are becoming increasingly stringent. [Brief explanation of the drawing]

[0002] The embodiments will be easily understood by reading the following detailed description in conjunction with the attached drawings. To facilitate this explanation, similar reference numerals refer to similar structural elements. The embodiments in the attached drawings are illustrative and not limiting.

[0003] [Figure 1] This disclosure provides schematic diagrams of cross-sectional views of exemplary transistors having back contacts according to several embodiments of this disclosure.

[0004] [Figure 2] A perspective view (A) and a cross-sectional view (B) of an exemplary transistor having back contacts, which is implemented as a FinFET, according to some embodiments of the present disclosure.

[0005] [Figure 3] This disclosure provides schematic diagrams of cross-sectional views of exemplary memory cells, including transistors having back contacts, according to some embodiments of this disclosure.

[0006] [Figure 4]This disclosure provides block diagrams of integrated circuit (IC) assemblies having rear-side power supply and front-side glass support according to several embodiments of this disclosure.

[0007] [Figure 5] This disclosure provides schematic diagrams of IC assemblies having rear-side power supply and front-side glass support according to various embodiments of this disclosure. [Figure 6] This disclosure provides schematic diagrams of IC assemblies having rear-side power supply and front-side glass support according to various embodiments of this disclosure. [Figure 7] This disclosure provides schematic diagrams of IC assemblies having rear-side power supply and front-side glass support according to various embodiments of this disclosure. [Figure 8] This disclosure provides schematic diagrams of IC assemblies having rear-side power supply and front-side glass support according to various embodiments of this disclosure.

[0008] [Figure 9] Figures (A) to (D) illustrate a first exemplary method for forming an IC assembly having a rear power supply and a front glass support, according to some embodiments of the present disclosure.

[0009] [Figure 10] (A) to (D) show a second exemplary method for forming an IC assembly having a rear power supply and a front glass support, according to some embodiments of the present disclosure.

[0010] [Figure 11] This is a side cross-sectional view of an IC package that may include an IC assembly having a rear power supply and a front glass support, according to any embodiment disclosed herein.

[0011] [Figure 12] This is a side cross-sectional view of an IC device assembly that may include an IC assembly having a rear power supply and a front glass support, according to any embodiment disclosed herein.

[0012] [Figure 13] A block diagram of an exemplary computing device that may include an IC assembly having a backside power supply and a front glass support, according to any of the embodiments disclosed herein. [DETAILED DESCRIPTION OF THE INVENTION]

[0013] [Summary] Each of the systems, methods, and devices of the present disclosure has a plurality of innovative aspects, none of which alone bears all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described herein are set forth in the following description and the accompanying drawings.

[0014] For purposes of explaining the IC assembly having a backside power supply and a front glass support described herein, it may be helpful to first understand the phenomena that can occur in a particular IC arrangement. The following basic information may be regarded as a foundation on which the present disclosure can be properly explained. Such information is provided for illustrative purposes only. Therefore, it should not be construed as limiting the present disclosure and its broad range of potential applications in any way.

[0015] Monolithic ICs generally include multiple transistors such as metal-oxide semiconductor (MOS) field-effect transistors (FETs) (MOSFETs) fabricated on a planar substrate such as a silicon wafer. Although Moore's Law has been valid in the IC industry for decades, at current MOSFET gate dimensions of 20 nanometers and below, lateral scaling of IC dimensions is becoming increasingly difficult. As device sizes continue to shrink, there will come a time when continuing with standard planar scaling will become impractical. This inflection point may be due to economic or physical factors such as extraordinary large capacity or quantum-based variability. Therefore, stacking transistors in three dimensions, typically referred to as vertical scaling or three-dimensional (3D) integration, is a promising means for increasing transistor density.

[0016] 3D integration can be achieved at the package level, for example, by stacking separately manufactured chips. However, the monolithic 3D approach provides the highest interlayer interconnect density, enabling 3D circuits such as 3D logic circuits to be built with the lowest level and the densest circuit density. Realizing a monolithic 3D IC architecture with favorable metrics in terms of power, performance, and footprint area is not an easy task, and further improvements are always desired.

[0017] Embodiments of this disclosure are based on the use of transistors having back-side contacts. Conventional substrate-process (FEOL) transistors have both source and drain contacts on one side of the transistor (typically the side facing away from the substrate). In contrast to methods for constructing logic and memory devices having such conventional FEOL transistors, various embodiments of this disclosure provide transistors, various IC devices incorporating such transistors (e.g., logic devices, memory cells, and arrays), as well as related methods and larger devices in which the transistor has at least one source or drain (S / D) contact on one side and another S / D contact on the other side. One side of the transistor may be referred to as the “front side” and the other side as the “back side,” and generally, in the context of this disclosure, the “side” of the transistor refers to either region or layer above or below the layer of channel material of the transistor. Thus, the transistors described herein may have one front-side S / D contact (the contact referred to as the “front-side contact”) and another back-side S / D contact (the contact referred to as the “back-side contact”). In a further embodiment, both of at least some of the S / D contacts of a transistor used in an IC assembly described herein may be located on the back side of the transistor. Hereinafter, a transistor having one front-side S / D contact and one back-side S / D contact, as well as a transistor having two back-side S / D contacts, may simply be referred to as a "transistor with back-side contacts".

[0018] Using transistors with back-side contacts offers several advantages and enables unique architectures not possible with conventional FEOL logic transistors where both S / D contacts are on one side. One advantage is that such transistors enable back-side power supply to IC components (e.g., transistors) of the IC structure, i.e., power supply from the back of the IC structure. In some implementations, e.g., monolithic 3D IC architectures, back-side power supply can be more advantageous than front-side power supply. Another advantage is that such transistors can be moved to the wiring process (BEOL) layers of advanced complementary metal oxide semiconductor (CMOS) processes. Yet another advantage is that by implementing at least some transistors with S / D contacts on different sides, great flexibility is provided for making electrical connections to these transistors. As a result, at least some of the logic devices and memory cells incorporating such transistors can be supplied on different layers above the support structure, thereby enabling three-dimensional integration of memory and logic devices, and in particular, enabling stacked architectures with many layers of memory and / or logic devices. By providing 3D memory and / or logic devices, it becomes possible to significantly increase the density of these devices having a given footprint area (footprint area defined as the area in the x-y plane of the substrate or a plane parallel to the substrate, i.e., the area in the x-y plane of the exemplary coordinate system shown in the drawings of this disclosure), or conversely, to significantly reduce the footprint area of ​​a structure having a given density of memory and logic devices.

[0019] When back-side power supply is implemented, in addition to the interconnects for supplying power, the back-side power supply structure may include various IC devices (e.g., capacitors, inductors, resistors, etc.) to reduce parasitic effects in the assembly, such as those associated with the interconnects used for power supply. However, as more IC components are mounted on the front side of the IC structure, the density of power interconnects on the back side increases to a point where it becomes difficult to also implement additional IC devices to reduce parasitic effects in the assembly.

[0020] Embodiments of this disclosure are based on the understanding that using a glass support structure on the front side of an IC structure with back-side power supply can advantageously reduce parasitic effects in the IC structure compared to, for example, using a silicon-based (Si) support structure on the front side. As used herein, the term “glass support structure” refers to any support structure having a dielectric constant lower than Si, for example, less than about 11. Such a glass support structure may include any type of glass material in some embodiments, such glass having a dielectric constant in the range of about 5 to 10.5. However, in some embodiments, what is described herein as a glass support structure may include a material other than glass, such as mica, provided that the material has a sufficiently low dielectric constant. By placing a support structure with a dielectric constant lower than Si on the front side of the IC structure, various parasitic effects associated with the IC structure can be advantageously reduced because they are typically proportional to the dielectric constant of the surrounding medium. Furthermore, by arranging such support structures, it becomes possible to implement at least some additional IC devices on the front side of the IC structure to reduce assembly parasitic effects, and thus advantageously, expand back-side power supply without cluttering the valuable real-estate area of ​​the back-side power interconnect.

[0021] An exemplary IC assembly includes a FEOL layer having multiple FEOL devices, a back-side power supply structure having multiple power interconnects electrically coupled to various of the multiple FEOL devices (e.g., making conductive contact with at least some of them), a BEOL layer having multiple BEOL interconnects electrically coupled to one or more of the multiple FEOL devices (e.g., making conductive contact with at least some of them), and a glass support structure (e.g., at least part of a glass wafer), wherein the FEOL layer lies between the back-side power supply structure and the BEOL layer, and the BEOL layer lies between the FEOL layer and the glass support structure.

[0022] In the context of this disclosure, the term “above” may mean further away from the support structure or FEOL of the IC device, and the term “below” may mean approaching the support structure or FEOL of the IC device.

[0023] In the following descriptions, some may refer to a specific side of a transistor, referred to as the front side, and the other side, referred to as the back side, in order to illustrate the general concept of a transistor having S / D contacts on different sides. However, unless otherwise specified, it is not important which side of the transistor is considered the front side and which side is considered the back side. Therefore, the descriptions of some exemplary embodiments of the front and back sides provided herein, on the condition that one S / D contact for the transistor is provided on one side of the channel layer and the other on the other side, are applicable to embodiments in which the designations of front and back sides may be reversed. Furthermore, some descriptions may refer to a specific S / D region or contact that is either a source region / contact or a drain region / contact. However, unless otherwise specified, it is not important which region / contact of the transistor is considered the source region / contact and which region / contact is considered the drain region / contact, because, as is common in the field of FETs, the designations of source and drain are often interchangeable. Therefore, the descriptions of some exemplary embodiments of source and drain regions / contacts provided herein are applicable to embodiments in which the designation of source and drain regions / contacts may be reversed.

[0024] Some descriptions provided herein may refer to transistors that are top-gate transistors, but embodiments of this disclosure are not limited to this design and include transistors in various other architectures or mixtures of different architectures. For example, in various embodiments, transistors having back-side S / D contacts as described herein may include bottom-gate transistors, top-gate transistors, FinFETs, nanowire transistors, planar transistors, and the like, all of which are within the scope of this disclosure. Furthermore, while descriptions of this disclosure may refer to logic devices or memory cells provided in a given layer, each layer of an IC device described herein may also include other types of devices other than the logic or memory devices described herein. For example, in some embodiments, an IC device having a logic device incorporating a transistor having back-side S / D contacts may also include a memory cell in one of its layers.

[0025] Furthermore, in the following detailed description, various exemplary implementations will be described using terminology commonly employed by those skilled in the art to communicate the contents of the research to others skilled in the art.

[0026] For example, the term “interconnect” may be used to describe any element formed from a conductive material to provide electrical connections to and / or between various such components associated with an IC. Generally, “interconnect” can refer to both conductive wires / wires (sometimes referred to as “wires” or “metal wires” or “trenches”) and conductive vias (sometimes referred to as “vias” or “metal vias”). Generally, the term “conductive wire” may be used to describe a conductive element insulated by dielectric material, including interlayer low-k dielectrics, typically provided within the plane of an IC chip. Such conductive wires are typically located on multiple levels or layers of a metallization stack. On the other hand, the term “conductive via” may be used to describe a conductive element that interconnects two or more conductive wires at different levels of a metallization stack. For this purpose, vias may be provided substantially perpendicular to the plane of the IC chip or support structure in which the IC structure is provided, and may interconnect two conductive wires at adjacent levels, or two conductive wires at non-adjacent levels. The term "metallization stack" may be used to refer to a stack of one or more interconnects that provide connectivity to different circuit components of an IC chip.

[0027] In another example, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die.” Unless otherwise specified, “insulation” means “electrical insulation,” and “conductivity” means “electrical conduction.” While an element may be referred to singly in this specification, such an element may include multiple sub-elements. For example, “conductive material” may include one or more conductive materials. When terms such as “oxide,” “carbide,” and “nitride” are used, they refer to compounds containing oxygen, carbon, nitrogen, etc., respectively; the term “high-k dielectric” refers to a material with a dielectric constant higher than silicon oxide; and the term “low-k dielectric” refers to a material with a dielectric constant lower than silicon oxide. Furthermore, the term “connection” may be used to describe a direct electrical or magnetic connection between things that are connected without any intermediate devices, while the term “bonding” may be used to describe either a direct electrical or magnetic connection between things that are connected, or an indirect connection through one or more passive or active intermediate devices. The term “circuit” may be used to describe one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The terms “substantially,” “near,” “approximately,” “near,” and “about” generally refer to being within + / - 20% of a target value, based on the context of specific values ​​described herein or known in the art. Similarly, terms indicating the orientation of various elements, such as “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between elements, generally refer to being within + / - 5-20% of a target value, based on the context of specific values ​​described herein or known in the art.

[0028] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B) or (A and B). For the purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). When the term "between" is used in reference to a measurement range, it includes the values ​​at both ends of the measurement range. As used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0029] Descriptions may use the phrases "in one embodiment" or "in an embodiment." Each of these phrases may refer to one or more of the same or different embodiments. Furthermore, terms such as "comprising," "including," and "having" used in reference to embodiments of this disclosure are synonymous. This disclosure may use descriptions based on perspectives such as "above," "below," "top," "bottom," and "side," but such descriptions are used to facilitate explanation and are not intended to limit the applicability of the disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of ordinal numbers such as "first," "second," and "third" to describe common subjects is merely to indicate different instances of similar subjects and is not intended to suggest that the subjects described in this way must be in a given order in time, space, rank, or any other manner.

[0030] The following detailed description will include references to the accompanying drawings that form part of this specification. These drawings illustrate possible embodiments. It will be understood that other embodiments may be used and structural or logical modifications may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be construed as restrictive. Where there exists a set of drawings designated by different letters (e.g., Figure 9(A) to Figure 9(D)), such a set may be referred to herein without letters, for example, "Figure 9".

[0031] In the drawings, some schematic diagrams of exemplary structures of the various devices and assemblies described herein may be shown with strict right angles and straight lines, but it should be understood that when any of the structures described herein are examined using, for example, scanning electron microscopy (SEM) images or transmission electron microscopy (TEM) images, such schematic diagrams may not reflect the limitations of the actual process which may cause features to appear so "ideally". In such images of actual structures, possible manufacturing defects may be visible, and these defects include, for example, not-so-straight edges of material, tapered vias or other openings, unintended rounding of corners or variations in the thickness of different material layers, occasionally occurring helical dislocations, edge dislocations, or combination dislocations within crystalline regions, and / or occasionally occurring single-atom or cluster of atomic dislocation defects. Other defects that are not listed herein but are common in the field of device manufacturing may exist.

[0032] Various actions may be described in sequence as a plurality of individual actions or operations in a manner that best contributes to understanding the claimed invention. However, the order of description should not be construed as suggesting that these actions are necessarily order-dependent. In particular, these actions do not have to be performed in the order presented. The described actions may be performed in a different order than in the described embodiments. Various additional actions may be performed, and / or the described actions may be omitted in additional embodiments.

[0033] Various IC assemblies having rear-side power supply and front-side glass support, as described herein, may be implemented in or in relation to one or more components associated with the IC, or / or between various such components. In various embodiments, components associated with the IC include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with the IC may include those mounted on the IC or those connected to the IC. The IC may be either analog or digital and, depending on the components associated with the IC, may be used in multiple applications such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc. The IC may be employed as part of a chipset to perform one or more associated functions in a computer. Exemplary transistor architecture

[0034] Figure 1 provides a schematic cross-sectional view of an exemplary transistor 100, which is mounted as an FET and has back contacts, according to some embodiments of the present disclosure.

[0035] In Figure 1 and at least some of the subsequent figures, multiple elements labeled with reference numbers are shown in these figures in different patterns, using a legend provided at the bottom of each drawing page containing these figures that shows the correspondence between reference numbers and patterns. For example, the legend indicates that Figure 1 uses different patterns to show the channel material 102, the S / D area 104, the contacts to the S / D area 104, etc. Furthermore, a certain number of given elements may be shown in Figure 1 and at least some of the subsequent figures, but this is also merely for the sake of clarity, and more or fewer numbers may be included in the IC devices according to various embodiments of this disclosure. Moreover, the representations of various IC devices shown in Figure 1 and at least some of the subsequent figures are intended to show the relative arrangement of various elements therein, and the various IC devices or parts thereof may include other elements or components not shown (e.g., spacer material that may surround the gate stack of transistor 100, etching stop material, etc., or any further materials).

[0036] Generally, an FET, such as a MOSFET, is a three-terminal device that includes source, drain, and gate terminals and uses an electric field to control the current flowing through the device. An FET typically includes a gate stack that includes a channel material, source and drain regions provided in the channel material, and a gate electrode material, alternatively referred to as a “work function” (WF) material, provided on the portion of the channel material between the source and drain regions, and optionally also includes a gate dielectric material between the gate electrode material and the channel material. Figure 1 shows the overall structure comprising a channel material 102, S / D regions 104 (represented as, for example, a first S / D region 104-1 which is the source region, and a second S / D region 104-2 which is, for example, the drain region), contacts 106 to the S / D regions (represented as a first S / D contact 106-1 which provides electrical contact to the first S / D region 104-1, and a second S / D contact 106-2 which provides electrical contact to the second S / D region 104-2), and a gate stack 108 which includes at least a gate electrode 110 and optionally also includes a gate dielectric 112.

[0037] Implementations of the present disclosure may be formed on or performed on a support structure which may be, for example, a substrate, die, wafer, or chip. The substrate may be, for example, wafer 2000 in Figure 11 described below, or may be, for example, a unified die 2002 in Figure 11 described below, or may be contained within a die. The substrate may be a semiconductor substrate constructed from a semiconductor material system which includes, for example, an N-type or P-type material system. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or silicon-on-insulator (SOI) base structure. In other implementations, the semiconductor substrate may be formed using, but is not limited to, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, or gallium antimonide, or other combinations of Group III–V materials (i.e., Group III and V materials of the periodic system of elements), Group II–VI materials (i.e., Group II and IV materials of the periodic system of elements), or Group IV materials (i.e., Group IV materials of the periodic system of elements), which may or may not be bonded to silicon. In some embodiments, the substrate may be amorphous. In some embodiments, the substrate may be a printed circuit board (PCB) substrate. While some examples of materials on which a substrate may be formed are described here, any material that can serve as a base on which an IC assembly having back-side power supply and front-side glass support as described herein can be constructed is within the spirit and scope of this disclosure. In various embodiments, the channel material 102 may include, or be formed on, any substrate material that provides a suitable surface for forming the transistor 100.

[0038] In some embodiments, the channel material 102 may consist of a semiconductor material system, for example, an N-type or P-type material system. In some embodiments, the channel material 102 may include high-mobility oxide semiconductor materials such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material 102 may include a combination of semiconductor materials, one of which may be used for a channel portion (for example, portion 114 shown in Figure 1, which is assumed to refer to the top of the channel material 102), and another material, optionally referred to as a “blocking material,” may be used between the channel portion 114 and the support structure on which the transistor 100 is provided. In some embodiments, the channel material 102 may include a single-crystal semiconductor such as silicon (Si) or germanium (Ge). In some embodiments, the channel material 102 may include a compound semiconductor having a first sublattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from Group V of the periodic table (e.g., P, As, Sb).

[0039] In some exemplary embodiments of N-type transistors (i.e., embodiments in which transistor 100 is an N-type metal oxide semiconductor (NMOS)), the channel portion 114 of the channel material 102 may, advantageously, include, but not limited to, III-V materials with high electron mobility, such as InGaAs, InP, InSb, and InAs. In some such embodiments, the channel portion 114 of the channel material 102 may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. x Ga 1‐x In embodiments of As fin, the In content (x) can be between 0.6 and 0.9, and advantageously, at least 0.7 (e.g., In 0.7 Ga 0.3It can be (As). In some embodiments having the highest mobility, the channel portion 114 of the channel material 102 can be an essential III-V material, that is, a III-V semiconductor material that is not intentionally doped with any electrically active impurities. In alternative embodiments, a nominal impurity dopant level can be present within the channel portion 114 of the channel material 102, for example, to further fine-tune the threshold voltage Vt or to provide a HALO pocket implant. However, even in impurity-doped embodiments, the impurity dopant level within the channel portion 114 of the channel material 102 can be relatively low, for example, below 10 -3 per cubic centimeter (cm 15 ) of dopant atoms, and advantageously below 10 13 cm -3 .

[0040] For some exemplary embodiments of P-type transistors (i.e., embodiments where the transistor 100 is a P-type metal oxide semiconductor (PMOS)), the channel portion 114 of the channel material 102 can advantageously be a Group-IV material having high hole mobility, such as, but not limited to, Ge or a Ge-rich SiGe alloy. In some exemplary embodiments, the channel portion 114 of the channel material 102 can have a Ge content between 0.6 and 0.9, and advantageously can be at least 0.7. In some embodiments having the highest mobility, the channel portion 114 can be an essential III-V (or Group-IV for P-type devices) material that may not be intentionally doped with any electrically active impurities. In alternative embodiments, one or more nominal impurity dopant levels can be present within the channel portion 114, for example, to further set the threshold voltage (Vt) or to provide a HALO pocket implant or the like. However, even in impurity-doped embodiments, the impurity dopant level within the channel portion is relatively low, for example, below 10 15 cm -3 , and advantageously below 10 13 cm-3 It is lower.

[0041] In some embodiments, transistor 100 may be a thin-film transistor (TFT). A TFT is a special type of field-effect transistor made by depositing a thin film of active semiconductor material, as well as a dielectric layer and metal contacts, on a support layer which may be a non-conductive layer. At least a portion of the active semiconductor material forms the channel of the TFT. If transistor 100 is a TFT, the channel material 102 may include high-mobility oxide semiconductor materials such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Generally, if transistor 100 is a TFT, the channel material 102 may include one or more of the following: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, zinc indium oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdic acid, molybdenum diselenide, tungsten disulfide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus (each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium). In some embodiments, the channel material 102 may have a thickness between approximately 5 and 75 nanometers (including all values ​​and ranges within that range). In some embodiments, the thin-film channel material 102 may be deposited at relatively low temperatures, thereby allowing the channel material 102 to be deposited within the thermal history imposed on back-end manufacturing, thus avoiding damage to other components, such as front-end components like logic devices.

[0042] As shown in Figure 1, the first S / D region 104-1 and the second S / D region 104-2 (collectively referred to as “S / D region 104”) may be located on either side of the gate stack 108, thereby realizing a transistor. As is known in the art, source and drain regions (sometimes interchangeably also referred to as “diffusion regions”) are formed for the gate stack of the FET. In some embodiments, the S / D region 104 of transistor 100 may be a region of doped semiconductor to supply charge carriers to the transistor channel, for example, a region of channel material 102 (e.g., of channel portion 114) doped with a suitable dopant up to a suitable dopant concentration. In some embodiments, to favorably form ohmic contact with the respective S / D contacts 106, the S / D region 104 may be, for example, about 1 to 10 21 cm -3While these regions can be highly doped with dopant concentrations, in other embodiments, these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Regardless of the exact doping level, the S / D region 104 of transistor 100 may have a higher dopant concentration than other regions, for example, a higher dopant concentration than in the region of channel material 102 between the first S / D region 104-1 and the second S / D region 104-2, and may therefore be referred to as a “highly doped” (HD) region. In some embodiments, the S / D region 104 may generally be formed using either an implant / diffusion process or an etching / deposition process. In the forming process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into one or more semiconductor materials on top of the channel material 102 to form the S / D region 104. An annealing process may follow the ion implantation process to activate the dopants and further diffuse them into the channel material 102. In the latter process, one or more semiconductor materials of the channel material 102 may be first etched to form recesses in place for the subsequent S / D regions. Next, an epitaxial deposition process may be performed to fill the recesses with the material (which may include a combination of different materials) used to manufacture the S / D regions 104. In some implementations, the S / D regions 104 may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with a dopant such as boron, arsenic, or phosphorus. In further embodiments, the S / D regions 104 may be formed using one or more alternative semiconductor materials such as germanium or III-V materials or alloys. Figure 1 shows first and second S / D regions 104 having a single pattern, suggesting that the material composition of the first and second S / D regions 104 is identical, although this may not be the case in some other embodiments of the transistor 100. Therefore, in some embodiments, the material composition of the first S / D region 104-1 may differ from the material composition of the second S / D region 104-2.

[0043] As further shown in Figure 1, S / D contacts 106-1 and 106-2 (collectively referred to as "S / D contacts 106") formed from one or more conductive materials may be used to provide electrical connections to S / D regions 104-1 and 104-2, respectively. In various embodiments, one or more layers of metal and / or metallic alloys may be used to form the S / D contacts 106. For example, the conductive material of the S / D contacts 106 may include one or more metals or metallic alloys having materials such as copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, aluminum, tantalum nitride, tungsten, doped silicon, doped germanium, or alloys and mixtures of any of these. In some embodiments, the S / D contacts 106 may include one or more conductive alloys, oxides, or carbides of one or more metals. In some embodiments, the S / D contact 106 may include a doped semiconductor such as silicon, or another semiconductor doped with an N-type or P-type dopant. While metals may offer higher conductivity, doped semiconductors can be more easily patterned during manufacturing. Figure 1 shows first and second S / D contacts 106 having a single pattern, suggesting that the material compositions of the first and second S / D contacts 106 are identical, but this may not be the case in some other embodiments of the transistor 100. Thus, in some embodiments, the material composition of the first S / D contact 106-1 may differ from the material composition of the second S / D contact 106-2.

[0044] For the gate stack 108, the gate electrode 110 may include at least one P-type WF metal or N-type WF metal, depending on whether the transistor 100 is a PMOS transistor or an NMOS transistor. In the case of a PMOS transistor, the metals that may be used for the gate electrode 110 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). In the case of an NMOS transistor, the metals that may be used for the gate electrode 110 may include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode 110 may include a stack of two or more metal layers, one or more of which are WF metal layers, and at least one of which is a filler metal layer. Further metal layers may be included for other purposes, such as acting as a diffusion barrier layer as described below.

[0045] When used, the gate dielectric 112 may surround the channel portion 114 at least laterally, and the gate electrode 110 may surround the gate dielectric 112 laterally such that the gate dielectric 112 is positioned between the gate electrode 110 and the channel material 104. In various embodiments, the gate dielectric 112 may comprise one or more high-k dielectric materials and may comprise elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric 112 include, but are not limited to, hafnium oxide, silicon hafnium oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, silicon zirconium oxide, tantalum oxide, titanium oxide, titanium barium strontium oxide, titanium barium oxide, titanium strontium oxide, yttrium oxide, aluminum oxide, tantalum oxide, silicon tantalum oxide, scandium tantalum lead oxide, and lead zinc niobate. In some embodiments, annealing may be performed on the gate dielectric 112 during the manufacture of the transistor 100 to improve the quality of the gate dielectric 112. In some embodiments, the gate dielectric 112 may have a thickness of about 0.5 nanometers to 3 nanometers, for example, about 1 nanometer to 3 nanometers, or about 1 nanometer to 2 nanometers (including all values ​​and ranges thereof).

[0046] In some embodiments, the gate dielectric 112 may be a multilayer gate dielectric, which may include, for example, one layer of high-k dielectric material and a layer of IGZO. In some embodiments, the gate stack 108 may be arranged such that the IGZO is positioned between the high-k dielectric and the channel material 104. In such embodiments, the IGZO may be in contact with the channel material 104 and may provide an interface between the channel material 104 and the rest of the multilayer gate dielectric 112. The IGZO may have a gallium:indium ratio of 1:1, a gallium:indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and / or a gallium:indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10).

[0047] In some embodiments, the gate stack 108 may be surrounded by a dielectric spacer, although not specifically shown in Figure 1. The dielectric spacer may be configured to provide separation between the gate stacks 108 of different transistors 100 that may be provided adjacent to each other (e.g., different transistors 100 provided along a single fin when transistor 100 is a FinFET), and between the gate stack 108 and one of the S / D contacts 106 located on the same side as the gate stack 108. Such a dielectric spacer may comprise one or more low-k dielectric materials. Examples of low-k dielectric materials that can be used as dielectric spacers include, but are not limited to, silicon dioxide, carbon-doped oxides, silicon nitride, fused silica glass (FSG), and organic silicates such as silsesquioxane, siloxane, and organosilicate glasses. Other examples of low-k dielectric materials that can be used as dielectric spacers include organic polymers such as polyimide, polynorbornene, benzocyclobutene, perfluorocyclobutane, or polytetrafluoroethylene (PTFE). Further examples of low-k dielectric materials that can be used as dielectric spacers include silicon-based polymer dielectrics such as hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ). Other examples of low-k materials that can be used in dielectric spacers include various porous dielectric materials, such as porous silicon dioxide or porous carbon-doped silicon dioxide, where large voids or holes are formed in the dielectric to reduce the overall dielectric constant of the layer, as voids can have a dielectric constant close to 1.

[0048] In stark contrast to conventional implementations where both S / D contacts are typically located on a single side of the transistor, typically the front side (where the gate stack 108 is located), the two S / D contacts 106 are located on different sides. That is, as shown in Figure 1, the second S / D contact 106-2 is located on the same side as the gate stack 108, which can be considered the front side of transistor 100, while the first S / D contact 106-1 is located on the opposite side, which can be considered the back side of transistor 100. Thus, the first S / D contact 106-1 is the back side contact, and the second S / D contact 106-2 is the front side contact of transistor 100. When considering the layers above the support structure (not shown in Figure 1) on which transistor 100 is built, the first S / D contact 106-1 can be considered to be on the first layer 120-1 above the support structure, the second S / D contact 106-2 can be considered to be on the second layer 120-2 above the support structure, and the portion of the channel material 102 between the first S / D region 104-1 and the second S / D region 104-2 (e.g., the channel portion 114) is on the third layer 120-3 above the support structure. As can be seen from Figure 1, the third layer 120-3 is between the first layer 120-1 and the second layer 120-2. At least a portion of the gate stack 108, or contacts with the gate stack 108 (gate contacts not specifically shown in Figure 1), may be located on the same layer as one of the S / D contacts 106, for example, the second layer 120-2 shown in Figure 1. In a further embodiment of the transistor 100, the first S / D contact 106-1 may also be implemented in the second layer 120-2.

[0049] Transistors having backside S / D contacts as described herein, such as transistor 100, can be implemented using any suitable transistor architecture, such as a planar or non-planar architecture. One exemplary structure is shown in Figures 2(A) and 2(B), which show perspective and cross-sectional views, respectively, of an exemplary IC device 200 having a transistor having at least one backside contact implemented as a FinFET, according to some embodiments of the present disclosure. Thus, IC device 200 represents one exemplary implementation of transistor 100. Accordingly, some of the reference numbers shown in Figures 2(A) to 2(B) are the same as those used in Figure 1 and refer to the same or similar elements as described with reference to Figure 1, and the description in Figures 2(A) to 2(B) is not repeated.

[0050] A FinFET refers to a transistor having a non-planar architecture on which fins formed from one or more semiconductor materials extend away from the base (the term "base" refers to any suitable support structure on which the transistor can be built, e.g., a substrate). The portion of the fin closest to the base may be enclosed by an insulating material. Such an insulating material, typically an oxide, is generally referred to as a "shallow trench isolation" (STI), and the portion of the fin enclosed by the STI is typically referred to as a "subfin portion" or simply a "subfin." A gate stack, which includes at least a layer of gate electrode material and optionally a layer of gate dielectric, may be provided on the top and sides of the remaining upper part of the fin (i.e., the portion on top of the STI and not enclosed by it), thereby covering the uppermost part of the fin. The portion of the fin covered by the gate stack is typically referred to as the "channel portion" of the fin, because during the operation of the transistor, a conductive channel is formed here and is part of the active region of the fin. The source and drain regions are provided on the opposite side of the gate stack and form the source and drain terminals of the transistor, respectively. FinFETs can be implemented as "tri-gate transistors," and the name "tri-gate" comes from the fact that such transistors can form conduction channels on the three "sides" of the fin during use. FinFETs potentially offer improved performance compared to single-gate and double-gate transistors.

[0051] Figure 2(A) is a perspective view of an IC device / FinFET 200 having one front-side and one back-side S / D contact according to some embodiments of the present disclosure, and Figure 2(B) is a side cross-sectional view thereof. Figures 2(A) to 2(B) show the channel material 102 representing the gate electrode 110 and gate dielectric 112 described above, the S / D region 104, and the gate stack 108. When the transistor 100 is implemented as a FinFET as shown in Figures 2(A) to 2(B), the FinFET 200 may further include a base 202, a fin 204, and an STI material 206 encompassing the sub-fin portion of the fin 204. To avoid complicating the drawings, the S / D contact 106 is not specifically shown in Figures 2(A) to 2(B). The side section view in Figure 2(B) is a representation in the yz plane of the exemplary coordinate system x-y-z shown in Figure 2(A), and the section in Figure 2(B) passes through fin 204 (for example, along the plane shown as plane A-A in Figure 2(A)). On the other hand, the side section view in Figure 1 is a representation in the xz plane of the exemplary coordinate system shown in Figure 2(A), and the section passes through fin 204 for one exemplary portion of gate stack 108 (for example, along the plane shown as plane B-B in Figures 2(A) and 2(B)).

[0052] As shown in Figures 2(A) to 2(B), the fin 204 may extend away from the base 202 and may be substantially perpendicular to the base 202. The fin 204 may include one or more semiconductor materials, for example, a stack of semiconductor materials, and as a result, the uppermost part of the fin (i.e., the portion of the fin 204 encompassed by the gate stack 108) may function as the channel region of the FinFET 200. Thus, the uppermost part of the fin 204 may be formed from the channel material 102 as described above and may include the channel portion 114.

[0053] The subfins of fin 204 may be binary, ternary, or quaternary III-V compound semiconductors, which are alloys of two, three, or even four elements from Group III and Group V of the periodic table, including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth. In some exemplary embodiments of N-type transistors, the subfin portion of fin 204 may be a Group III-V material having a band offset from the channel portion (e.g., a conduction band offset for N-type devices). Exemplary materials include, but are not limited to, GaAs, GaSb, GaAsSb, GaP, InAlAs, GaAsSb, AlAs, AlP, AlSb, and AlGaAs. In some embodiments of N-type transistors of FinFET 200 where the channel portion of fin 204 (e.g., channel portion 114) is InGaAs, the subfins may be GaAs, and at least a portion of the subfins may also be doped with impurities (e.g., P-type) to a higher impurity level than the channel portion. In embodiments of the alternating heterojunction, the subfins and channel portions of fin 204 are, or contain, a Group IV semiconductor (e.g., Si, Ge, SiGe). The subfins of fin 204 may be a first-element semiconductor (e.g., Si or Ge) or a first-element SiGe alloy (e.g., having a wide band gap). In some exemplary embodiments of the P-type transistor, the subfins of fin 204 may be a Group IV material having a band offset from the channel portion (e.g., a valence band offset for a P-type device). Exemplary materials include, but are not limited to, Si or Si-rich SiGe. In some embodiments of the P-type transistor, the subfins of fin 204 are Si, and at least a portion of the subfins may also be doped with impurities (e.g., N-type) to a higher impurity level than the channel portion.

[0054] As further shown in Figures 2(A) to 2(B), the STI material 206 may encompass a portion of the side of the fin 204. The portion of the fin 204 encompassed by the STI 106 forms a subfin. In various embodiments, the STI material 206 may be a low-k or high-k dielectric containing elements such as hafnium, silicon, oxygen, nitrogen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Further examples of dielectric materials that may be used in STI material 206 include, but are not limited to, silicon nitride, silicon oxide, silicon dioxide, silicon carbide, carbon-doped silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, silicon tantalum oxide, scandium tantalum lead oxide, and lead zinc niobate.

[0055] The gate stack 108 may cover the upper part of the fin 204 (the upper portion of the STI 206), as shown in Figures 2(A) to 2(B), and the channel portion of the fin 204 (e.g., the channel portion 114 described above) corresponds to the portion of the fin 204 that is covered by the gate stack 108, as shown in Figures 2(A) to 2(B). In particular, the gate dielectric 112 (if used) may cover the uppermost part of the fin 204, and the gate electrode 110 may cover the gate dielectric 112. The interface between the channel portion and the sub-fin portion of the fin 204 is located near where the gate electrode 110 ends.

[0056] In some embodiments, the FinFET 200 may have a gate length GL (i.e., the distance between the first S / D region 104-1 and the second S / D region 104-2) which is a dimension measured along the fin 204 in the x-axis direction of the exemplary reference coordinate system x-y-z shown in Figures 1 and 2(A) to 2(B), and which may be about 5 to 40 nanometers (including all values ​​and ranges therein, for example, about 22 to 35 nanometers, or about 20 to 30 nanometers). The fin 204 may have a thickness which is a dimension measured in the y-axis direction of the reference coordinate system x-y-z shown in Figures 2(A) to 2(B), and which may be about 5 to 30 nanometers (including all values ​​and ranges therein, for example, about 7 to 20 nanometers, or about 10 to 15 nanometers). In some embodiments, the fin 204 may have a height that is a dimension measured in the z-axis direction of the reference coordinate system x-y-z shown in Figure 1, which may be about 30 to 350 nanometers (including all values ​​and ranges within that, for example, about 30 to 200 nanometers, about 75 to 250 nanometers, or about 150 to 300 nanometers).

[0057] The fin 204 shown in Figures 2(A) and 2(B) is shown as having a rectangular cross-section in the yz plane of the given reference coordinate system. However, the fin 204 may also have a rounded or angled cross-section at its "top," and the gate stack 108 may accommodate a rounded or angled fin 204. During use, the FinFET 200 can form conduction channels on the three "sides" of the channel portion of the fin 204, potentially improving performance compared to single-gate transistors (which can form conduction channels on one "side" of the channel material or substrate) and double-gate transistors (which can form conduction channels on two "sides" of the channel material or substrate).

[0058] Although not specifically shown in Figure 2(A), the S / D contact 106 may be electrically connected to the S / D region 104 but extend in a different perpendicular direction relative to the fin 204. For example, the first S / D contact 106-1 may be electrically connected to the first S / D region 104-1 and extend from the first S / D region 104-1 toward the base 202, thereby forming the back-side S / D contact for the FinFET 200, as described in Figure 1. In such an implementation, the second S / D contact 106-2 may be electrically connected to the second S / D region 104-2 and extend from the second S / D region 104-2 toward the base 202, thereby forming the front-side S / D contact for the FinFET 200, again as described in Figure 1.

[0059] Figures 2(A) and 2(B) show a single FinFET 200, but in some embodiments, multiple FinFETs may be arranged next to each other (with some space between them) along the fin 204. Furthermore, in various further embodiments, a transistor 100 having one front-side S / D contact and one back-side S / D contact can be implemented in many other transistor architectures besides FinFET 200, such as planar FETs, nanowire FETs, or nanoribbon FETs. Exemplary memory implementation

[0060] Embedded memory is crucial to the performance of modern system-on-a-chip (SoC) technology, particularly for enabling 3D monolithic integration. IC assemblies with back-side power supply and front-side glass support may contain embedded memory. Therefore, several considerations regarding memory are discussed here.

[0061] Some memory devices can be considered “standalone” devices in that they are contained within a chip that does not include computational logic (wherein used herein, “computational logic device” or simply “computational logic” or “logic device” refers to a device, e.g., a transistor for performing computational operations). Other memory devices can be contained within a chip in conjunction with computational logic and may be referred to as “embedded” memory devices. Supporting computational logic with embedded memory can improve performance by bringing the memory and computational logic closer together and eliminating interfaces that increase latency. Various embodiments of this disclosure relate to embedded memory arrays and corresponding methods and devices.

[0062] Some embodiments of this disclosure may refer to dynamic random access memory (DRAM), in particular embedded DRAM (eDRAM), because this type of memory was introduced in the past to address the density and standby power limitations of large static random access memory (SRAM)-based caches. However, embodiments of this disclosure are equally applicable to other technologies in which memory cells are implemented. Thus, generally speaking, the memory cells described herein may be implemented as eDRAM cells, spin-transfer torque random access memory (STTRAM) cells, resistive random access memory (RRAM®) cells, or any other non-volatile memory cells.

[0063] A memory cell, such as an eDRAM cell, may include a capacitor for storing bit values, or the memory state of the cell (e.g., a logical "1" or "0"), as well as an access transistor that controls access to the cell (e.g., access to write information to the cell, or access to read information from the cell). Such a memory cell may be referred to as a "1T-1C memory cell" to emphasize the fact that it uses one transistor (i.e., "1T" in the term "1T-1C memory cell") and one capacitor (i.e., "1C" in the term "1T-1C memory cell"). The capacitor of a 1T-1C memory cell may be coupled to one source / drain (S / D) terminal of the access transistor (e.g., the source terminal of the access transistor), while the other S / D terminal of the access transistor may be coupled to the bit line (BL), and the gate terminal of the transistor may be coupled to the word line (WL). Since such a memory cell can be manufactured with only a single access transistor, it may offer higher density and lower standby power than SRAM in the same process technology.

[0064] Various 1T-1C memory cells have conventionally been implemented with access transistors, which are logic process-based transistors mounted on the top layer of a semiconductor substrate (FEOL). The inventors of this disclosure have noticed that using conventional logic transistors presents several challenges when such transistors are used to form three-dimensional memory and logic devices.

[0065] One challenge concerns the location of capacitors in such memory cells. Specifically, it may be desirable to provide capacitors in a metal layer close to the corresponding access transistors. Since logic transistors are implemented as FEOL transistors directly mounted on the semiconductor substrate, the corresponding capacitors in a 1T-1C memory cell then need to be incorporated into a lower metal layer to be sufficiently close to the logic access transistors. Because the pitch of lower metal layers scales significantly at advanced technology nodes, incorporating capacitors into lower metal layers presents significant challenges to scaling 1T-1C-based memory and creating 3D memory devices.

[0066] Another challenge is that, given the usable surface area of ​​the substrate, the number of FEOL transistors that can be formed in that area is limited, which imposes a significant limitation on the density of memory cells or logic devices containing such transistors.

[0067] By implementing the transistors of memory cells (e.g., memory cell access transistors) as transistors with back contacts, at least some of the challenges and problems described above can be mitigated. For example, moving the memory cell access transistors to the BEOL layer (which is made possible by the back contact architecture) means that their corresponding capacitors can be implemented in the upper metal layer, which has correspondingly thicker interlayer dielectrics (ILDs) and larger metal pitches to achieve higher capacitance, thus easing the integration challenges posed by incorporating the capacitors.

[0068] Figure 3 provides schematic cross-sectional views of exemplary memory cells 300, including a transistor having back contacts, according to several embodiments of the present disclosure. Figure 3 shows how the transistor 100 may be used to form a 1T-1C memory cell. In particular, the memory cell 300 shows all the components of the transistor 100 in Figure 1 (and therefore their description is not repeated here), and further schematicly shows that in some embodiments, a capacitor 302 may be coupled to the back S / D contact 106-1 of the transistor 100. The capacitor 302 may be any suitable capacitor, e.g., a metal-insulator-metal (MIM) capacitor for storing bit values ​​or the memory state of the memory cell 300 (e.g., logical "1" or "0"), and the transistor 100 may then function as an access transistor controlling access to the memory cell 300 (e.g., access to write information to the cell or access to read information from the cell). By coupling the capacitor 302 to the S / D area 104-1, the capacitor 302 is configured to store the memory state of the memory cell 300. In some embodiments, capacitor 302 may be coupled to S / D region 104-1 via a storage node (not specifically shown in Figure 3) which is coupled to S / D region 104-1. In some embodiments, S / D contact 106-1 may be considered a storage node.

[0069] Although not specifically shown in Figure 3, the memory cell 300 may further include a bit line for transferring memory state, coupled to one of the S / D regions 104 that is not coupled to capacitor 302 (for example, S / D region 104-2 in the description of Figure 3). Such a bit line may be connected to, for example, a sense amplifier and a bit line driver, which may be provided in a memory peripheral circuit associated with a memory array that may contain the memory cell 300. Furthermore, also not specifically shown in Figure 3, the memory cell 300 may further include a word line coupled to the gate terminal of transistor 100, for example, coupled to gate stack 108, for supplying a gate signal. Transistor 100 may be configured to control the transfer of the memory state of the memory cell 300 between the bit line and a storage node or capacitor 302 in response to the gate signal. Exemplary IC assembly with glass support on the front

[0070] Transistors with back-side contacts can enable three-dimensional integration of IC assemblies with back-side power supply and front-side glass support. An exemplary IC assembly is shown in Figure 4, which provides a block diagram of an IC assembly 400 with back-side power supply and front-side glass support according to some embodiments of the present disclosure.

[0071] As shown in Figure 4, the IC assembly 400 may include a FEOL layer 420 and a BEOL layer 430 on top of the FEOL layer 420. The FEOL layer 420 may include a plurality of FEOL devices, for example, FEOL transistors that are implemented as back-side contact transistors. The BEOL layer 430 may include at least a plurality of interconnects that are electrically coupled to one or more of the plurality of FEOL devices of the FEOL layer 420 (e.g., making conductive contact with at least some of them). In some embodiments, the BEOL layer 430 may further include BEOL devices, for example, back-end transistors, at least some of which may be implemented as transistors having back-side contacts.

[0072] In various embodiments, FEOL transistors with back contacts, implemented in the FEOL layer 420, may be part of the computation logic and / or part of the memory array.

[0073] For example, in some embodiments, some of the FEOL transistors in the FEOL layer 420 may be access transistors for memory cells of a memory array, such as the 1T-1C memory cells described above. In such embodiments, capacitors for such memory cells may then be implemented in the BEOL layer 430. In other embodiments, some of the FEOL transistors in the FEOL layer 420 may be access transistors for memory cells of a type other than 1T-1C. In such embodiments, other parts of the memory cell (e.g., storage transistors) may be implemented in the BEOL layer 430.

[0074] In another example, some of the FEOL transistors in the FEOL layer 420 may be part of the computational logic of the IC assembly 400. For example, such transistors may be responsible for computational logic functions related to read / write operations on data stored in memory cells that may be implemented in the BEOL layer 430. For this purpose, some of the FEOL transistors in the FEOL layer 420 may be part of one or more input / output (I / O) ICs (e.g., memory peripheral circuits) configured to control (e.g., access (read / write), storage, and update) memory cells implemented in the IC assembly 400 (e.g., memory cells implemented in the BEOL layer 430). In some embodiments, some of the FEOL transistors in the FEOL layer 420 may be part of high-performance computational logic configured to perform various operations on data stored in memory cells implemented in the IC assembly 400 (e.g., arithmetic and logical operations, data from one or more memory arrays implemented in the IC assembly 400, and possibly also a data pipeline from an external device chip).

[0075] Transistors having back contacts as described herein, either as standalone transistors (e.g., transistor 100) or included as part of a memory cell (e.g., memory cell 300), may be included in various regions / locations in the IC assembly 400. For example, transistor 100 may be used as a logic transistor in computational logic (e.g., included in the FEOL layer 420). In another example, transistor 100 may be used as an access transistor in one or more memory layers of the BEOL 430. Providing back contacts to transistors can ease the integration challenges posed by incorporating storage nodes (e.g., storage capacitors) of memory cells, enabling the construction of three-dimensional memory and logic devices with stack architectures having many layers of memory and / or computational logic.

[0076] The description of Figure 4 is intended to provide an overall orientation and arrangement of the various layers relative to each other, and unless otherwise specified in this disclosure, embodiments of the IC device 400 include instances in which some of the elements described for one of the layers shown in Figure 4 may extend into or reside within one or more other layers. For example, although not specifically shown in Figure 4, power and signal interconnects for various IC components of the IC assembly 400 may reside in any of the layers shown in Figure 4. Furthermore, although a single BEOL layer 430 is shown in Figure 4, in various embodiments, the BEOL layer 430 of the IC assembly 400 may comprise multiple BEOL layers.

[0077] In some embodiments, the BEOL layer 430 may include one or more memory layers that can form one or more memory arrays. Such memory arrays may include access transistors (e.g., transistor 100), storage nodes (e.g., storage capacitors or storage transistors), and word lines (e.g., row selectors) and bit lines (e.g., column selectors) that constitute memory cells. In some embodiments, the memory layers of the BEOL layer 430 may include TFT type memory cells. The FEOL layer 420, on the other hand, may include various logic layers, circuits, and devices (e.g., logic transistors) to drive and control the logic IC. For example, the logic devices of the FEOL layer 420 may form memory peripheral circuits for controlling (e.g., accessing (reading / writing), storing, updating) the memory cells of the BEOL layer 430. In some embodiments of the IC assembly 400, computation logic may be provided in the FEOL 420 and in one or more of the lowest metal layers of the BEOL layer 430, while one or more memory arrays may be provided in the upper layers of the BEOL layer 430. In other embodiments of the IC assembly 400, the computational logic described with reference to the FEOL layer 420 may be provided on top of the FEOL layer 420 (for example, on the BEOL layer 430), between the memory layers of the BEOL layer 430, or coupled to the memory layers of the BEOL layer 430.

[0078] Various BEOL layers of BEOL layer 430 may include metal layers of the metallization stack of IC assembly 400. Various BEOL metal layers may be used to interconnect various inputs and outputs of logic devices in the computational logic of FEOL layer 420, and / or memory cells in the memory layer of BEOL layer 430. Generally, each metal layer of BEOL layer 430 may include via portions and trench / interconnect portions. Trench portions of metal layers are configured to transfer signals and power along conductive (e.g., metal) wires (sometimes referred to as "trenches") extending in the x-y plane (e.g., in the x or y direction), while via portions of metal layers are configured to transfer signals and power through conductive vias extending in the z direction to, for example, an adjacent metal layer above or below. Thus, vias connect metal structures (e.g., metal wires or vias) from one metal layer to an adjacent metal layer. Although referred to as a "metallic" layer, the various layers of the BEOL layer 430 may include only specific patterns of conductive metals, such as copper (Cu), aluminum (Al), tungsten (W), or cobalt (Co), or metal alloys, or more generally, patterns of conductive materials formed in an insulating medium such as ILD. The insulating medium may include any suitable ILD material such as silicon oxide, carbon-doped silicon oxide, silicon carbide, silicon nitride, aluminum oxide, and / or silicon oxynitride.

[0079] The FEOL layer 420 may originally be provided on a semiconductor support structure such as a substrate, die, wafer, or chip, and may include any of the materials or combinations of materials described with reference to the support structures of the embodiments in Figures 1 to 3. However, such a semiconductor support structure may later be removed to expose the back side of the FEOL device of the FEOL layer 420, and as a result, the back-side power supply structure 410 may be provided on the back side of the FEOL layer 420 (thus the BEOL layer 430 is provided on the front side of the FEOL layer 420, and the back-side power supply structure 410 is provided on the back side of the FEOL layer 420).

[0080] Furthermore, as shown in Figure 4, the IC assembly 400 may further include a bonding interface 440 and a glass support structure 450, the bonding interface 440 being an interface in which the upper surface of the BEOL layer 430 is bonded to the surface of the glass support structure 450. Thus, in the IC assembly 400, the FEOL layer 420 is located between the back-side power supply structure 410 and the BEOL layer 430, and the BEOL layer 430 is located between the FEOL layer 420 and the glass support structure 450.

[0081] Figures 5 to 8 provide schematic diagrams of exemplary implementations of the IC assembly 400 according to various embodiments of the present disclosure.

[0082] Figure 5 provides a schematic diagram of an IC assembly 500 having a rear power supply and a front glass support according to several embodiments of the present disclosure. Parts of the IC assembly 400 shown in Figure 4, such as the rear power supply structure 410 and FEOL 420, are labeled in the IC assembly 500 of Figure 5. The IC assembly 500 further shows exemplary implementations of each of these parts.

[0083] As shown in Figure 5, the rear power supply structure 410 may include a plurality of power interconnects 512 arranged in one or more layers (three such layers separated by horizontal lines are shown in Figure 5, but such separation may not be present in other embodiments, or other embodiments may include a different number of layers and / or different configurations of power interconnects 512 than those shown in Figure 5). The power interconnects 512 may include any preferred combination of vias 512-1 and lines 512-2, some of which are labeled in Figure 5, and some which are left unlabeled to avoid complicating the drawing. The power interconnects 512 may include any preferred conductive material, such as any conductive metal or metallic alloy as described above. Some of the various power interconnects 512 may be enclosed by an insulating material 514, which may include any of the ILD materials described above.

[0084] As further shown in Figure 5, the FEOL layer 420 may include a plurality of FEOL devices 526. One or more of the FEOL devices 526 may be transistors having back contacts as described above, for example, transistor 100. In various embodiments, the FEOL devices 526 may include one or more fin transistors, nanoribbon transistors, and nanowire transistors having one or more back contacts, as are known in the Art but described herein. One or more power interconnects 512 may then be coupled to one or more S / D regions of such transistors having back contacts (i.e., one or more power interconnects 512 may form back contacts to one or more S / D regions of the transistors of the FEOL device 526).

[0085] Furthermore, as shown in Figure 5, the BEOL layer 430 may include a plurality of BEOL interconnects 532 which may contain any preferred conductive material, such as any conductive metal or metallic alloy as described above. The BEOL interconnects 532 may include any preferred combination of vias 532-1 and wires 532-2, some of which are labeled in Figure 5, and some which are left unlabeled to avoid complicating the drawing. One or more of the BEOL interconnects 532 may be electrically coupled to one or more of a plurality of FEOL devices 526 (e.g., making conductive contact with at least some of them). At least some of the BEOL interconnects 532 may be enclosed by an insulating material 534 which may contain any of the ILD materials described above. In some embodiments, the insulating material, such as the insulating material 534, may also at least partially enclose some of the FEOL devices 526. Figure 5 also schematically illustrates that the BEOL layer 430 may include a layer of memory cells 536. The memory cell 536 may be any of the memory cells described above, for example, a TFT type memory cell, for example, memory cell 300. In a further embodiment, the IC assembly 500 may include multiple layers of memory cells 536.

[0086] In some embodiments, the side cross-sectional views of the BEOL interconnect 532 and the power interconnect 512 may have differences in characteristics due to the fact that the BEOL interconnect 532 and the power interconnect 512 are formed on different sides of the FEOL layer 420. In particular, in such embodiments, the cross-section of at least some of the BEOL interconnect 532 and at least some of the power interconnect 512 in a plane perpendicular to the FEOL layer 420 may be trapezoidal. Such a trapezoid may include two parallel sides, one of which is the short side and the other is the long side (i.e., the length of the long side is greater than the length of the short side). Characteristic of the fact that the BEOL interconnect 532 and the power interconnect 512 are formed on different sides of the FEOL layer 420, in the trapezoidal shape of the BEOL interconnect 532, the longer side is closer to the glass support structure 450 than the shorter side, and the shorter side is closer to the FEOL layer 420 than the longer side, while in the trapezoidal shape of the power interconnect 512, the shorter side is closer to both the glass support structure 450 and the FEOL layer 420 than the longer side.

[0087] Figure 5 further illustrates a bonding interface material 540 that may be used to implement the bonding interface 440. This bonding the upper surface of the BEOL layer 430 to a non-semiconductor support structure 550 that may be used to implement the glass support structure 450 as described above. In some embodiments, the bonding interface material 540 may contain an oxide, such as silicon oxide. As shown in Figure 5, in some embodiments, a portion of the bonding interface material 540 (e.g., one face) may be in contact with one or more portions of the glass support structure 450, while another portion of the bonding interface material 540 (e.g., the opposite face) may be in contact with one or more portions of the BEOL layer 430. In some embodiments, the bonding interface material 540 may have a thickness between about 1 nanometer and 100 nanometers, for example, about 1 to 50 nanometers, or about 1 to 20 nanometers.

[0088] In some embodiments, the non-semiconductor support structure 550 may include a glass material. Examples of glass materials may include silicon oxide materials doped with elements and compounds such as boron, carbon, aluminum, and hafnium oxide, for example, with a doping concentration of about 0.01% to 10%. In other embodiments, the non-semiconductor support structure 550 may include other solid materials having a dielectric constant lower than that of Si, for example, lower than about 10.5. In some embodiments, the non-semiconductor support structure 550 may include mica. The thickness of the glass support structure 450 can be any value for the glass support structure 450 that provides mechanical stability for the IC assembly 400 and, in some cases, supports the inclusion of various devices (some such devices are shown in Figure 6 and described above) to further reduce parasitic effects in the IC assembly. In some embodiments, the glass support structure 450 may have a thickness of about 0.2 micrometers (microns) to 100 microns, for example, about 0.5 to 5 microns, or about 1 to 3 microns.

[0089] Figure 6 provides schematic diagrams of IC assembly 600 having a back-side power supply and a glass support with front-side thin-film devices, according to several embodiments of the present disclosure. Parts of IC assembly 400 shown in Figure 4, such as the back-side power supply structure 410, FEOL 420, are labeled in IC assembly 600 in Figure 6. IC assembly 600 further shows exemplary implementations of each of these parts. In particular, IC assembly 600 may be implemented as IC assembly 500 as described above (shown in Figure 6 as IC assembly 600 containing some of the same elements as those included in IC assembly 500 shown in Figure 5, and shown using the same pattern). However, IC assembly 600 further includes one or more thin-film devices 556 arranged on the glass support structure 450. For brevity, a detailed description of IC assembly 500 is not repeated with respect to IC assembly 600, and only the differences are described. Furthermore, in order to avoid complicating the diagram in Figure 6, the power interconnects 512-1 and 512-2 and the BEOL interconnects 532-1 and 532-2 are not specifically labeled in Figure 6, as they were labeled in Figure 5.

[0090] In various embodiments, the thin-film device 556 may be a two-terminal device such as a thin-film resistor, thin-film capacitor, and thin-film inductor, configured to reduce parasitic effects within the IC assembly 600. The first terminal of such a two-terminal thin-film device 556 may be electrically coupled (e.g., to a first BEOL interconnect of a plurality of BEOL interconnects 532) (e.g., to a conductive contact), while the second terminal may be electrically coupled (e.g., to a second BEOL interconnect of a plurality of BEOL interconnects 532) (e.g., to a conductive contact). An example of such two-terminal coupling is labeled in Figure 6 for one of the thin-film devices 556 (although three different thin-film devices 556 are shown in the example in Figure 6). The first terminal of the thin-film device 556 shown on the right side of the IC assembly 600 is coupled to the first BEOL interconnect 612-1 of a plurality of BEOL interconnects 532 (shown as the dotted contour 652-1 in Figure 6), and the second terminal of the thin-film device 556 shown on the right side of the IC assembly 600 is coupled to the second BEOL interconnect 612-2 of a plurality of BEOL interconnects 532 (shown as the dotted contour 652-2 in Figure 6). As shown in Figure 6, in some embodiments, a portion of the thin-film device 556 extends through the bonding interface 450 and may be in electrical contact with each portion of the BEOL interconnects 532.

[0091] Figure 7 provides a schematic diagram of an IC assembly 700 having a back-side power supply and a glass support with a front-side active layer, according to several embodiments of the present disclosure. Parts of the IC assembly 400 shown in Figure 4, such as the back-side power supply structure 410 and FEOL 420, are labeled in the IC assembly 700 of Figure 7. The IC assembly 700 further shows exemplary implementations of each of these parts. In particular, the IC assembly 700 may be implemented as the IC assembly 500 described above (shown in Figure 7 as the IC assembly 700, which includes some of the same elements as those included in the IC assembly 500 shown in Figure 5, and is shown using the same pattern). However, the IC assembly 700 further includes an active layer 650 between the glass support structure 450 and the BEOL layer 430. For brevity, a detailed description of the IC assembly 500 is not repeated for the IC assembly 700, and only the differences are described. Furthermore, in order to avoid complicating the diagram in Figure 7, the power interconnects 512-1 and 512-2, and the BEOL interconnects 532-1 and 532-2 are not specifically labeled in Figure 7, as they were labeled in Figure 5.

[0092] As shown in Figure 7, the active layer 750 may be provided between the glass support structure 450 and the bonding interface 440, which in turn may be provided between the active layer 750 and the BEOL layer 430. In some embodiments, some parts of the bonding interface 440 may be in contact with one or more parts of the active layer 750, and other parts of the bonding interface 440 may be in contact with one or more parts of the BEOL layer 430. The bonding interface 440 may be a hybrid bonding interface in such embodiments, as described below with reference to Figure 10, for example.

[0093] As shown in Figure 7, the active layer 750 may include a plurality of interconnects 752 arranged in one or more layers (two such layers are shown in Figure 7, separated by a horizontal line, but such separation may not be present in other embodiments, or other embodiments may include a different number of layers and / or a different configuration of interconnects 752 than those shown in Figure 7). The interconnects 752 may include any preferred combination of vias 752-1 and lines 752-2, some of which are labeled in Figure 7, and some which are left unlabeled to avoid complicating the drawing. The interconnects 752 may include any preferred conductive material, such as any conductive metal or metallic alloy as described above. Some of the various interconnects 752 may be encompassed by an insulating material 754 which may include any of the ILD materials described above. One or more interconnects 752 of the active layer 750 may be electrically coupled to one or more of the BEOL interconnects 532 (for example, by making conductive contact with at least some of them).

[0094] As further shown in Figure 7, the IC assembly 700 may further include a plurality of devices 756, such as transistors or memory cells. Figure 7 shows the devices 756 as part of a glass support structure 450, but in other embodiments of the IC assembly 700, the devices 756 may be part of the active layer 750. In some embodiments, one or more of the devices 756 may be transistors as described above, such as transistor 100. In some embodiments, one or more of the devices 756 may be memory cells as described above, such as memory cell 300, or any other embedded memory cell. One or more of the interconnects 752 may then be coupled to a portion of one or more of the devices 756, and to one or more of the plurality of BEOL interconnects 532.

[0095] In some embodiments, the side section view of the interconnect 752 may have differences in characteristics due to the fact that the interconnect 752 and the BEOL interconnect 532 are formed on different sides of the bonding interface 440. In particular, in such embodiments, the section of at least some of the interconnect 752 in a plane perpendicular to the FEOL layer 420 may be a trapezoid having one short side and one long side. Such a trapezoid may include two parallel sides, one of which is the short side and the other is the long side (i.e., the length of the long side is greater than the length of the short side). Characteristic of the fact that interconnect 732 and BEOL interconnect 532 are formed on different sides of the bonding interface 440, in the trapezoidal shape of interconnect 732, the shorter side is closer to the glass support structure 450 than the longer side, and the longer side is closer to the bonding interface 440 and the FEOL layer 420 than the shorter side, while in the trapezoidal shape of BEOL interconnect 512, the longer side is closer to both the glass support structure 450 and the bonding interface 440 than the shorter side.

[0096] Figure 8 provides schematic diagrams of IC assembly 800 having a back-side power supply and a glass support having a front-side thin-film device and an active layer, according to several embodiments of the present disclosure. Parts of IC assembly 400 shown in Figure 4, such as the back-side power supply structure 410, FEOL 420, are labeled in IC assembly 800 of Figure 8. IC assembly 800 further shows exemplary implementations of each of these parts. In particular, IC assembly 800 may be implemented as IC assembly 600 having one or more thin-film devices 556 arranged in a glass support structure 450 as described above, and further including the active layer 750 of IC assembly 700 as described above. This is shown in Figure 8 using IC assembly 800 including some of the same elements, and using the same patterns as those included in IC assembly 600 shown in Figure 6 and IC assembly 700 shown in Figure 7. The description of the IC assembly having one or more thin-film devices 556 arranged on a glass support structure 450 and an active layer 750, provided with reference to Figures 6 and 7, is applicable to the IC assembly 800 in Figure 8 and, therefore, will not be repeated for brevity. Exemplary manufacturing method

[0097] IC assemblies having back-side power supply and front-side glass support as described herein may be manufactured using any suitable technique, e.g., subtractive, additive, damascene, dual damascene, etc. Some of such techniques may include suitable deposition and patterning techniques. As used herein, “patterning” may mean forming a pattern of one or more materials using any suitable technique (e.g., applying a resist, patterning the resist using lithography, and then etching one or more materials using dry etching, wet etching, or any suitable technique).

[0098] Figures 9(A) to 9(D) show a first exemplary method for forming an IC assembly having a rear power supply and a front glass support, according to some embodiments of the present disclosure. Figures 10(A) to 10(D) show a second exemplary method for forming an IC assembly having a rear power supply and a front glass support, according to some embodiments of the present disclosure. The IC assemblies shown in Figures 9 and 10 include some of the same elements as those included in the IC assemblies shown in Figures 5 to 8, and are shown using the same patterns. For brevity, a detailed description of those elements is applicable to the IC assemblies shown in Figures 9 and 10 and is not repeated.

[0099] Figure 9(A) shows an IC structure 900A, illustrating that a first manufacturing method may begin by forming a plurality of FEOL devices 526 on a semiconductor support structure 902 which may include any of the support structures described with reference to Figures 1 to 3, then forming a BEOL 430 on a FEOL layer 420 having the FEOL devices 526, and then providing a layer of bonding interface material 540 on the top surface of the BEOL layer 430. Figure 9(B) shows an IC structure 900B, illustrating that the first manufacturing method may then proceed to invert the IC structure 900A of Figure 9(A) and bring the bonding interface material 540 of the IC structure 900A into contact with the bonding interface material provided on the top surface of a glass support structure 450, thereby performing bonding between the IC structure 900A and the glass support structure 450. Generally, the bonding described herein may be an insulator-insulator bonding, such as an oxide-oxide bonding, and the bonding interface material may be applied to one or both sides of the structures to be bonded, and the structures are then assembled together while heating the assembly to a suitable temperature (e.g., moderately high, e.g., about 50-200°C) by applying a suitable pressure, possibly over a period of time. In some embodiments, the bonding interface material 540 may be an adhesive material that ensures the IC structure 900A and the glass support structure 450 are bonded to each other, as shown in Figures 9(B) and 9(C). In some embodiments, the bonding interface material 540 may be an etching stop material. In some embodiments, both bonding interface materials 540 are etching stop materials and may have suitable adhesive properties to ensure the IC structures are bonded to each other as described herein. In some embodiments, no intentionally added adhesive bonding material may be used, in which case the layer labels "540" or "440" in these drawings represent the bonding interface resulting from bonding the respective IC structures to each other.Even when the specific materials of the insulators of the jointly bonded IC structures may be identical (in which case the bonding interface may still be recognizable as a seam or thin layer in what would otherwise appear as a bulk insulator (e.g., bulk oxide) layer), the bonding interface may be recognizable as a seam or thin layer in the IC assembly described herein, for example, using limited-field electron diffraction (SED). Where used herein, references to “bonding interface material 540” or “bonding interface 440” apply to “bonding interface” in embodiments where no intentionally added adhesive material is used to bond the IC structures described herein, unless otherwise specified. Figure 9(C) shows IC structure 900C, and illustrates that after bonding of IC structure 900A and glass support structure 450 has been performed, the first manufacturing method may proceed to remove the semiconductor support structure 902 (e.g., using a suitable polishing or grinding process) to expose the back side of the FEOL device 526 of FEOL 420. Figure 9(D) shows the IC structure 900D, and after the back side of the FEOL device 526 of FEOL420 is exposed, the first manufacturing method can proceed to provide the back side power supply structure 410 as described above.

[0100] Figure 10(A) shows IC structure 1000A, illustrating that a second manufacturing method may begin by forming a plurality of FEOL devices 526 on a semiconductor support structure 902 which may include any of the support structures described with reference to Figures 1 to 3, and then form a BEOL 430 on a FEOL layer 420 having the FEOL devices 526. Figure 10(B) shows IC structure 1000B, illustrating that the second manufacturing method may then proceed to invert IC structure 1000A of Figure 10(A) to bring the BEOL layer 430 of IC structure 1000A into contact with the upper surface of an active layer 750 provided on a glass support structure 450, thereby performing a hybrid junction of IC structure 1000A and glass support structure 450. The junction descriptions provided for Figures 9(A) to 9(D) are applicable to the junction of IC structure 1000A and glass support structure 450, and therefore, for brevity, will not be repeated. Figure 10(C) shows IC structure 1000C and illustrates that after bonding of the BEOL layer 430 and the active layer 750 of IC structure 900A is performed, a bonding interface 440 may be formed between the active layer 750 and the BEOL layer 430. Figure 10(D) later illustrates that a second manufacturing method may proceed to the removal of the semiconductor support structure 902 (e.g., using a suitable polishing or grinding process) to expose the back side of the FEOL device 526 of FEOL 420, and subsequently provide the back side power supply structure 410 as described above. Exemplary electronic device

[0101] IC assemblies having rear-side power supply and front-side glass support disclosed herein may be included in any suitable electronic device. Figures 11–13 show various examples of devices and components that may include one or more IC assemblies having rear-side power supply and front-side glass support, as disclosed herein.

[0102] Figure 11 is a side cross-sectional view of an exemplary IC package 2200, which may include one or more IC assemblies having a rear power supply and a front glass support, according to any embodiment disclosed herein. In some embodiments, the IC package 2200 may be a system-in-package (SiP).

[0103] The package substrate 2252 may be formed from a dielectric material (e.g., ceramic, build-up film, epoxy film with filler particles, etc.) and may have conductive paths extending through the dielectric material between surface 2272 and surface 2274, or between different positions on surface 2272, and / or between different positions on surface 2274.

[0104] The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive paths 2262 through the package substrate 2252, allowing circuits in the die 2256 and / or interposer 2257 to be electrically coupled to various conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).

[0105] The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, a first-level interconnect 2265, and conductive contacts 2263 of the package substrate 2252. The first-level interconnect 2265 shown in Figure 13 is a solder bump, but any preferred first-level interconnect 2265 may be used. In some embodiments, the interposer 2257 may not be included in the IC package 2200, and rather, the die 2256 may be directly coupled to the conductive contacts 2263 on surface 2272 by the first-level interconnect 2265.

[0106] The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the die 2256, a first-level interconnect 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to a conductive path (not shown) through the interposer 2257, allowing circuits within the die 2256 to be electrically coupled to various conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnect 2258 shown in Figure 11 is a solder bump, but any preferred first-level interconnect 2258 may be used. As used herein, “conductive contact” may refer to a portion of a conductive material (e.g., metal) that functions as an interface between different components. The conductive contact may be recessed into the surface of a component, coplanar with the surface, extend away from the surface, or take any suitable form (e.g., a conductive pad or socket).

[0107] In some embodiments, the underfill material 2266 may be positioned between the package substrate 2252 and the interposer 2257 around the first level interconnect 2265, and the mold compound 2268 may be positioned around the die 2256 and the interposer 2257 in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be identical to the mold compound 2268. Exemplary materials that may be used for the underfill material 2266 and the mold compound 2268 are suitable epoxy molding materials. The second level interconnect 2270 may be coupled to the conductive contact 2264. The second level interconnect 2270 shown in Figure 11 is a solder ball (e.g., for a ball grid array configuration), but any suitable second level interconnect 2270 (e.g., a pin in a pin grid array configuration or a land in a land grid array configuration) may be used. The second level interconnect 2270 may be used to connect the IC package 2200 to a circuit board (e.g., a motherboard), an interposer, or another component such as another IC package known in the art and described below with reference to Figure 12.

[0108] The die 2256 may take the form of any embodiment of an IC assembly having a rear power supply and a front glass support, as described herein. In embodiments in which the IC package 2200 includes a plurality of dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The die 2256 may include circuitry for performing any desired function. For example, one or more of the die 2256 may be logic dies (e.g., silicon-based dies), and one or more of the die 2256 may be memory dies (e.g., high-bandwidth memory) including embedded logic and memory devices as described herein. In some embodiments, any of the die 2256 may include one or more IC assemblies having a rear power supply and a front glass support, as described above, for example. In some embodiments, at least some of the die 2256 may not include any of the IC assemblies having a rear power supply and a front glass support.

[0109] The IC package 2200 shown in Figure 11 may be a flip-chip package, but other package architectures may be used. For example, the IC package 2200 may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Two dies 2256 are shown in the IC package 2200 of Figure 11, but the IC package 2200 may contain any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors, which are located on the first or second surface 2272 of the package substrate 2252, or on either surface of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0110] Figure 12 is a side cross-sectional view of an IC device assembly 2300 which may include components having one or more IC assemblies with rear power supply and front glass support, according to any embodiment disclosed herein. The IC device assembly 2300 may include a plurality of components arranged on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components arranged on a first surface 2340 and an opposite second surface 2342 of the circuit board 2302. Generally, components may be arranged on one or both surfaces 2340 and 2342. In particular, any preferred component of the IC device assembly 2300 may include any one or more IC assemblies having rear power supply and front glass support, according to any embodiment disclosed herein. For example, any of the IC packages described below with reference to IC device assembly 2300 may take the form of any of the embodiments of IC package 2200 described above with reference to Figure 11 (which may include, for example, one or more IC assemblies having back-side power supply and front-side glass support provided on die 2256).

[0111] In some embodiments, the circuit board 2302 may be a PCB comprising a plurality of metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. One or more of these metal layers may be formed with a desired circuit pattern to transfer electrical signals (optionally in conjunction with other metal layers) between components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB substrate.

[0112] The IC device assembly 2300 shown in Figure 12 includes a package-on-interposer structure 2336 coupled to the first surface 2340 of a circuit board 2302 by a coupling component 2316. The coupling component 2316 may electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and may include solder balls (e.g., shown in Figure 12), male and female sockets, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0113] The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by a coupling component 2318. The coupling component 2318 may take any suitable form for the application, such as the form described above with reference to the coupling component 2316. The IC package 2320 includes one or more IC assemblies having a back-side power supply and a front-side glass support as described herein. Figure 12 shows a single IC package 2320, but multiple IC packages may be coupled to the interposer 2304. In fact, additional interposers may be coupled to the interposer 2304. The interposer 2304 may provide an intervening substrate used to bridge the circuit board 2302 and the IC package 2320. Generally, the interposer 2304 may spread connections to a wider pitch or reroute connections to different connections. For example, the interposer 2304 may couple the IC package 2320 (e.g., die) to the BGA of the coupling component 2316 for coupling with the circuit board 2302. In the embodiment shown in Figure 12, the IC package 2320 and the circuit board 2302 are attached to opposite sides of the interposer 2304. In other embodiments, the IC package 2320 and the circuit board 2302 may be attached to the same side of the interposer 2304. In some embodiments, three or more components may be interconnected by the interposer 2304.

[0114] The interposer 2304 may be formed from an epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymer material such as polyimide. In some implementations, the interposer 2304 may be formed from alternatingly overlapping rigid or flexible materials, which may include the same materials as those described above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 2304 may include, but are not limited to, metal interconnects 2308 and vias 2310, including through-silicon vias (TSVs) 2306. The interposer 2304 may further include embedded devices 2314, which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices can also be formed on the interposer 2304. The package-on-interposer structure 2336 can take any form of package-on-interposer structure known in the art.

[0115] The IC device assembly 2300 may include an IC package 2324 coupled to the first surface 2340 of a circuit board 2302 by a coupling component 2322. The coupling component 2322 may take any form of the embodiments described above with reference to coupling component 2316, and the IC package 2324 may take any form of the embodiments described above with reference to IC package 2320.

[0116] The IC device assembly 2300 shown in Figure 12 includes a package-on-package structure 2334 coupled to the second surface 2342 of a circuit board 2302 by a coupling component 2328. The package-on-package structure 2334 may include IC packages 2326 and 2332 coupled together by a coupling component 2330 such that IC package 2326 is positioned between the circuit board 2302 and IC package 2332. The coupling components 2328 and 2330 may take any form of the embodiment of coupling component 2316 described above, and the IC packages 2326 and 2332 may take any form of the embodiment of IC package 2320 described above. The package-on-package structure 2334 may be configured according to any package-on-package structure known in the art.

[0117] Figure 13 is a block diagram of an exemplary computing device 2400, which may comprise one or more components having one or more IC assemblies with a rear power supply and a front glass support, according to any embodiment disclosed herein. Any of the components of the computing device 2400 may include an IC package 2200 as described with reference to Figure 11. Any of the components of the computing device 2400 may include an IC device assembly 2300 as described with reference to Figure 12.

[0118] Although multiple components are shown in Figure 13 as being included in the computing device 2400, one or more of these components may be omitted or duplicated if appropriate for the application. In some embodiments, some or all of the components included in the computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single SoC die.

[0119] Additionally, in various embodiments, the computing device 2400 does not have to include one or more of the components shown in Figure 13, but it may include interface circuits for connecting one or more components. For example, the computing device 2400 does not have to include the display device 2406, but it may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 2406 can be connected. In another set of examples, the computing device 2400 does not have to include the audio input device 2418 or the audio output device 2408, but it may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 2418 or the audio output device 2408 can be connected.

[0120] The computing device 2400 may include processing devices 2402 (e.g., one or more processing devices). As used herein, the terms “processing device” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts such electronic data into other electronic data that can be stored in registers and / or memory. Processing devices 2402 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 2400 may include memory 2404, which itself may include one or more memory devices such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard drives. In some embodiments, memory 2404 may include memory that shares a die with processing devices 2402. The memory may be used as cache memory and may include one or more IC assemblies having a back-side power supply and a front-side glass support as described herein.

[0121] In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured to manage wireless communication for data transfer to and from the computing device 2400. The terms “wireless” and their derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data using modulated electromagnetic radiation through a non-solid medium. The terms do not imply that the devices in question are completely wiring-free, although in some embodiments they may be wiring-free.

[0122] The 2412 communication chip may implement any of several wireless standards or protocols, including, but are not limited to, Wi-Fi (IEEE 602.11 family), IEEE standards including the IEEE 602.16 standard (e.g., IEEE 602.16-2005 amendment), and the Long-Term Evolution (LTE) project, including any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP2")). Broadband radio access (BWA) networks compatible with IEEE 602.16 are generally referred to as WiMAX (an acronym for Worldwide Interoperability for Microwave Access) networks, which is a certification mark for products that have passed tests for conformity and interoperability with the IEEE 602.16 standard. The communication chip 2412 may operate in accordance with the Global System for Mobile Communications (GSM®), General-Purpose Packet Radio Service (GPRS), Universal Mobile Communications System (UMTS), High-Speed ​​Packet Access (HSPA), Next Generation HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM® EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Next Generation UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and their derivatives, as well as any other radio protocols designated as 3G, 4G, 5G, and later. In other embodiments, the communication chip 2412 may operate in accordance with other radio protocols. The computing device 2400 may include an antenna 2422 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM radio transmissions).

[0123] In some embodiments, the communication chip 2412 may manage wired communications such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet®). As described above, the communication chip 2412 may include multiple communication chips. For example, the first communication chip 2412 may be dedicated to short-range wireless communications such as Wi-Fi® or Bluetooth®, and the second communication chip 2412 may be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX®, LTE, EV-DO, etc. In some embodiments, the first communication chip 2412 may be dedicated to wireless communications, and the second communication chip 2412 may be dedicated to wired communications.

[0124] The computing device 2400 may include a battery / power supply circuit 2414. The battery / power supply circuit 2414 may include circuits for coupling components of the computing device 2400 to one or more energy storage devices (e.g., batteries or capacitors) and / or an energy source separate from the computing device 2400 (e.g., AC line power).

[0125] The computing device 2400 may include a display device 2406 (or a corresponding interface circuit as described above). The display device 2406 may include any visual indicator, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0126] The computing device 2400 may include an audio output device 2408 (or a corresponding interface circuit as described above). The audio output device 2408 may include any device that generates an audible indicator, such as a speaker, headset, or earphones.

[0127] The computing device 2400 may include an audio input device 2418 (or a corresponding interface circuit as described above). The audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a MIDI (musical instrument digital interface) output).

[0128] The computing device 2400 may include a GPS device 2416 (or a corresponding interface circuit as described above). The GPS device 2416 may communicate with a satellite-based system and receive the position of the computing device 2400 in a manner known in the art.

[0129] The computing device 2400 may include other output devices 2410 (or corresponding interface circuits as described above). Examples of other output devices 2410 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0130] The computing device 2400 may include other input devices 2420 (or corresponding interface circuits as described above). Examples of other input devices 2420 may include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices such as mice, styluses, touchpads, barcode readers, quick response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0131] The computing device 2400 may have any desired form factor, such as a handheld electrical device or mobile computing device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultramobile personal computer, etc.), a desktop computing device, a server device or other network-connected computing component, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data. Example Selection

[0132] The following paragraphs provide various examples of embodiments disclosed herein.

[0133] Example 1 provides an IC assembly comprising a FEOL layer having multiple FEOL devices, a back-side power supply structure having multiple power interconnects electrically coupled to various parts of the multiple FEOL devices (e.g., making conductive contact with at least some of them), a BEOL layer having multiple BEOL interconnects electrically coupled to one or more of the multiple FEOL devices (e.g., making conductive contact with at least some of them), and a glass support structure (e.g., at least part of a glass wafer), wherein the FEOL layer is located between the back-side power supply structure and the BEOL layer, and the BEOL layer is located between the FEOL layer and the glass support structure.

[0134] Example 2 provides an IC assembly according to Example 1, wherein the plurality of BEOL interconnects include a first BEOL interconnect and a second BEOL interconnect (e.g., first and second metal wires), and the glass support structure includes a two-terminal thin-film device having a first terminal electrically coupled (e.g., making conductive contact) to the first BEOL interconnect and a second terminal electrically coupled (e.g., making conductive contact) to the second BEOL interconnect.

[0135] Example 3 provides an IC assembly according to Example 2, wherein the thin-film device is a thin-film resistor.

[0136] Example 4 provides an IC assembly according to Example 2, wherein the thin-film device is a thin-film capacitor.

[0137] Example 5 provides an IC assembly according to Example 2, wherein the thin-film device is a thin-film inductor.

[0138] Example 6 provides an IC assembly according to any one of the above examples, further including a bonding interface between the BEOL layer and the glass support structure.

[0139] Example 7 provides an IC assembly according to Example 6, wherein the bonding interface includes an oxide.

[0140] Example 8 provides an IC assembly according to Example 7, wherein the oxide includes portions that contact one or more portions of the glass support structure and portions that contact one or more portions of the BEOL layer.

[0141] Example 9 provides an IC assembly according to any one of Examples 1-7, wherein the active layer includes multiple IC devices and interconnects, the active layer is located between a glass support structure and a bonding interface, the bonding interface is located between the active layer and a BEOL layer, and at least one of the multiple IC devices and interconnects in the active layer is electrically coupled to one or more of the multiple BEOL interconnects (e.g., making conductive contact with at least some of them).

[0142] Example 10 provides an IC assembly according to Example 9, where the bonding interface is a hybrid bonding interface.

[0143] Example 11 provides an IC assembly according to Example 9 or 10, wherein the bonding interface includes a portion that contacts one or more portions of the active layer and a portion that contacts one or more portions of the BEOL layer.

[0144] Example 12 provides an IC assembly according to any one of Examples 9 to 11, wherein the cross-section of at least one interconnect of the active layer and at least one interconnect of the BEOL interconnect is a trapezoid with two parallel sides, one of which is the short side and the other is the long side, and for the trapezoid of at least one interconnect of the active layer, the short side is closer to the glass support structure than the long side, and for the trapezoid of at least one interconnect of the BEOL interconnect, the long side is closer to the glass support structure than the short side.

[0145] Example 13 provides an IC assembly according to Example 12, wherein the cross-section of at least one interconnect of the power interconnect is a trapezoid with two parallel sides, one of which is the short side and the other is the long side, and for the trapezoid of at least one interconnect of the power interconnect, the short side is closer to the glass support structure than the long side.

[0146] Example 14 provides an IC assembly according to any one of the above examples, wherein the plurality of FEOL devices include FEOL transistors having a source region and a drain region, and at least one power interconnect of the plurality of power interconnects is electrically coupled (e.g., makes conductive contact) to the source region or the drain region.

[0147] Example 15 provides an IC assembly according to any one of the above examples, wherein the rear power supply structure includes an insulating material that encompasses at least a portion of the multiple power interconnects.

[0148] Example 16 provides an IC assembly according to any one of the above examples, wherein the BEOL layer includes one or more memory layers, and the one or more memory layers include memory cells including thin-film transistors.

[0149] Example 17 provides an IC assembly according to any one of the above examples, wherein the glass support structure is replaced with a support structure of a material having a dielectric constant less than 10, which may be glass, but is not limited to glass. For example, the material of the support structure may be mica.

[0150] Example 18 provides an IC assembly according to any one of the above examples, and an IC package including further IC components coupled to the IC assembly.

[0151] Example 19 provides an IC package according to Example 18, wherein the further IC components include one of the package substrate, an interposer, or further IC dies.

[0152] Example 20 provides an IC package according to Example 18 or 20, in which the IC assembly includes, or is part of, at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communication device.

[0153] Example 21 provides an electronic device comprising a carrier substrate, an IC assembly according to any one of the above examples, and one or more IC packages according to any one of the above examples, coupled to the carrier substrate.

[0154] Example 22 provides an electronic device according to Example 21, wherein the carrier board is a motherboard.

[0155] Example 23 provides an electronic device according to Example 21, wherein the carrier substrate is a PCB.

[0156] Example 24 provides an electronic device according to one of Examples 21-23, wherein the electronic device is either a wearable electronic device (e.g., a smartwatch) or a handheld electronic device (e.g., a mobile phone).

[0157] Example 25 provides an electronic device according to any one of Examples 21-24, wherein the electronic device further includes one or more communication chips and antennas.

[0158] Example 26 provides an electronic device according to any one of Examples 21-25, wherein the electronic device is an RF transceiver.

[0159] Example 27 provides an electronic device according to any one of Examples 21-25, wherein the electronic device is one of the RF communication devices, such as an RF transceiver switch, power amplifier, low-noise amplifier, filter, filter bank, duplexer, upconverter, or downconverter.

[0160] Example 28 provides an electronic device according to any one of Examples 21-25, where the electronic device is a computing device.

[0161] Example 29 provides an electronic device according to any one of Examples 21-28, wherein the electronic device is included in a base station of a wireless communication system.

[0162] Example 30 provides an electronic device according to any one of Examples 21-28, in which the electronic device is included in a user device (i.e., a mobile device) of a wireless communication system.

[0163] Example 31 provides a method for manufacturing an IC assembly, the method comprising the steps of: providing a FEOL device on a semiconductor support structure; providing a BEOL layer on the FEOL device, wherein the BEOL layer includes a plurality of BEOL interconnects electrically coupled to (e.g., making conductive contact with at least a portion of) one or more of a plurality of FEOL devices; bonding the BEOL layer and the configuration of the FEOL devices to a non-semiconductor support structure; performing backside exposure by removing at least a portion of the semiconductor support structure to expose a portion of the FEOL device; and providing a backside power supply structure including a plurality of power interconnects electrically coupled to (e.g., making conductive contact with at least a portion of) the exposed portion of the FEOL device.

[0164] Example 32 provides a method according to Example 31, wherein the steps of bonding the BEOL layer and the FEOL device configuration to a non-semiconductor support structure include providing one or more bonding materials to at least one of the surfaces of the BEOL layer to be bonded to the non-semiconductor support structure and the surfaces of the non-semiconductor support structure to be bonded to the BEOL layer, and attaching the surfaces of the BEOL layer to be bonded to the non-semiconductor support structure to the surfaces of the non-semiconductor support structure to be bonded to the BEOL layer.

[0165] Example 33 provides the method according to Example 32, wherein one or more bonding materials include an oxide.

[0166] Example 34 provides a method according to any one of Examples 31 to 33, wherein the step of removing at least a portion of the semiconductor support structure to expose a portion of the FEOL device includes the step of polishing or grinding the semiconductor support structure until a portion of the FEOL device is exposed.

[0167] Example 35 provides a method according to any one of Examples 31-34, in which at least a portion of the semiconductor support structure is removed after the BEOL layer and FEOL device configuration are bonded to the non-semiconductor support structure.

[0168] Example 36 provides a method according to any one of Examples 31 to 35, wherein the rear power supply structure includes an insulating material that encompasses at least a portion of the multiple power interconnects.

[0169] Example 37 provides a method according to any one of Examples 31-36, wherein the non-semiconductor support structure includes glass.

[0170] Example 38 provides a method according to any one of Examples 31-37, wherein the non-semiconductor support structure includes mica.

[0171] Example 39 provides a method according to any one of Examples 31 to 37, wherein the non-semiconductor support structure includes an active layer comprising a plurality of IC devices and interconnects, and the step of bonding the BEOL layer and FEOL device configuration to the non-semiconductor support structure includes bonding the BEOL layer and FEOL device configuration to the active layer, thereby electrically coupling at least one of the plurality of IC devices and interconnects in the active layer to one or more of the plurality of BEOL interconnects.

[0172] Example 40 provides a method according to any one of Examples 31 to 39, further comprising a process for forming an IC assembly according to any one of the above examples (for example, for forming an IC assembly according to any one of Examples 1 to 17).

[0173] The above description of the implementation of the disclosed information, including matters described in the abstract, is not intended to be exhaustive or to limit the disclosure to the exact form provided. Specific implementations and examples of the disclosed information are described herein for illustrative purposes only, and various equivalent variations are possible within the scope of the disclosed information, as will be understood by those skilled in the art. These modifications may be made to the disclosed information in consideration of the above detailed description. [Next to other items] (Item 1) An integrated circuit (IC) assembly, A substrate process (FEOL) layer containing multiple FEOL devices, A back-side power supply structure including multiple power interconnects coupled to various multiple FEOL devices, A wiring process (BEOL) layer including a plurality of BEOL interconnects coupled to one or more of the plurality of FEOL devices, Glass support structure and The FEOL layer is located between the back-side power supply structure and the BEOL layer, The BEOL layer is located between the FEOL layer and the glass support structure. IC assembly. (Item 2) The plurality of BEOL interconnects include a first BEOL interconnect and a second BEOL interconnect, The glass support structure includes a thin-film device having a first terminal coupled to the first BEOL interconnect and a second terminal coupled to the second BEOL interconnect. The IC assembly described in item 1. (Item 3) The thin-film device is a thin-film resistor, as described in item 2 of the IC assembly. (Item 4) The thin-film device is a thin-film capacitor, as described in item 2 of the IC assembly. (Item 5) The thin-film device is a thin-film inductor, as described in item 2 of the IC assembly. (Item 6) The IC assembly according to item 1, further comprising a bonding interface between the BEOL layer and the glass support structure. (Item 7) The bonding interface comprises an oxide, as described in item 6 of the IC assembly. (Item 8) The aforementioned oxide is A portion that contacts one or more parts of the glass support structure, A portion that contacts one or more parts of the BEOL layer and The IC assembly described in item 7, including the one listed in item 7. (Item 9) The system further comprises an active layer containing multiple IC devices and interconnects, The active layer is located between the glass support structure and the bonding interface. The bonding interface is located between the active layer and the BEOL layer. At least one of the plurality of IC devices and interconnects in the active layer is coupled to one or more of the plurality of BEOL interconnects. The IC assembly described in item 1. (Item 10) The bonding interface is a hybrid bonding interface, as described in item 9 of the IC assembly. (Item 11) The bonding interface is A portion that contacts one or more parts of the active layer, A portion that contacts one or more parts of the BEOL layer and The IC assemblies described in item 9, including the IC assemblies described in item 9. (Item 12) The cross-section of at least one interconnect of the active layer and at least one interconnect of the BEOL interconnect is a trapezoid with two parallel sides, one of which is the shorter side and the other is the longer side. Regarding the trapezoid of the at least one interconnect of the active layer, the shorter side is closer to the glass support structure than the longer side. With respect to the trapezoid of the at least one interconnect of the BEOL interconnect, the longer side is closer to the glass support structure than the shorter side. The IC assembly described in item 9. (Item 13) The cross-section of at least one interconnect of the power interconnect is a trapezoid with two parallel sides, one of which is the shorter side and the other is the longer side. With respect to the trapezoid of at least one interconnect of the power interconnect, the shorter side is closer to the glass support structure than the longer side. The IC assembly described in item 12. (Item 14) The plurality of FEOL devices include FEOL transistors having a source region and a drain region, At least one of the plurality of power interconnects is coupled to the source region or the drain region. The IC assembly described in item 1. (Item 15) The IC assembly according to item 1, wherein the rear power supply structure includes an insulating material encompassing at least a portion of the plurality of power interconnects. (Item 16) The IC assembly according to item 1, wherein the BEOL layer includes one or more memory layers, and the one or more memory layers include memory cells including thin-film transistors. (Item 17) Integrated circuit (IC) package, IC assembly and Further IC components coupled to the aforementioned IC assembly The IC assembly is equipped with, A layer comprising multiple transistors, including one or more fin-type transistors, nanoribbon transistors, and nanowire transistors, A backend layer comprising a plurality of backend interconnects coupled to one or more of the plurality of transistors, A back-side power supply structure including a plurality of power interconnects coupled to one or more of the plurality of transistors, Glass support structure and Includes, The layer containing the plurality of transistors is located between the back-side power supply structure and the back-end layer. The back-end layer is located between the layer containing the plurality of transistors and the glass support structure. IC package. (Item 18) The aforementioned further IC component is an IC package as described in item 17, which includes one of the package substrate, an interposer, or a further IC die. (Item 19) A method for manufacturing an integrated circuit (IC) assembly, The process of setting up substrate process (FEOL) devices on a semiconductor support structure, A step of providing a wiring process (BEOL) layer on the FEOL device, wherein the BEOL layer includes a plurality of BEOL interconnects coupled to one or more of the plurality of FEOL devices, The steps include bonding the BEOL layer and the FEOL device to a non-semiconductor support structure, A step of removing at least a portion of the semiconductor support structure in order to expose a portion of the FEOL device, The step of providing a back-side power supply structure including a plurality of power interconnects coupled to the exposed portion of the FEOL device. A method for providing this. (Item 20) The step of bonding the BEOL layer and the configuration of the FEOL device to the non-semiconductor support structure is, The steps include providing one or more bonding materials on at least one surface of the BEOL layer bonded to the non-semiconductor support structure, and on at least one surface of the non-semiconductor support structure bonded to the BEOL layer, The steps include attaching the surface of the BEOL layer, which is bonded to the non-semiconductor support structure, to the surface of the non-semiconductor support structure, which is bonded to the BEOL layer. The method described in item 19, including the method described in item 19.

Claims

1. An integrated circuit (IC) assembly, A substrate process (FEOL) layer containing multiple FEOL devices, A back-side power supply structure including multiple power interconnects coupled to various multiple FEOL devices, A wiring process (BEOL) layer including a plurality of BEOL interconnects coupled to one or more of the plurality of FEOL devices, A glass support structure or non-semiconductor support structure having a dielectric constant lower than that of silicon (Si) and in the range of 5 to 10.

5. The FEOL layer is located between the back-side power supply structure and the BEOL layer, The BEOL layer is located between the FEOL layer and the glass support structure or the non-semiconductor support structure. IC assembly.

2. The plurality of BEOL interconnects include a first BEOL interconnect and a second BEOL interconnect. The glass support structure or the non-semiconductor support structure includes a thin-film device having a first terminal coupled to the first BEOL interconnect and a second terminal coupled to the second BEOL interconnect. The IC assembly according to claim 1.

3. The IC assembly according to claim 2, wherein the thin-film device is a thin-film resistor.

4. The IC assembly according to claim 2, wherein the thin-film device is a thin-film capacitor.

5. The IC assembly according to claim 2, wherein the thin-film device is a thin-film inductor.

6. The IC assembly according to any one of claims 1 to 5, further comprising a bonding interface between the BEOL layer and the glass support structure or the non-semiconductor support structure.

7. The IC assembly according to claim 6, wherein the bonding interface comprises an oxide.

8. The aforementioned oxide is A portion that contacts one or more parts of the glass support structure or the non-semiconductor support structure, A portion that contacts one or more parts of the BEOL layer The IC assembly according to claim 7, including the following:

9. The system further comprises an active layer containing multiple IC devices and interconnects, The active layer is located between the glass support structure or the non-semiconductor support structure and the bonding interface. The bonding interface is located between the active layer and the BEOL layer. At least one of the plurality of IC devices and interconnects in the active layer is coupled to one or more of the plurality of BEOL interconnects. The IC assembly according to claim 6 or 7.

10. The IC assembly according to claim 9, wherein the bonding interface is a hybrid bonding interface.

11. The bonding interface is A portion that contacts one or more parts of the active layer, A portion that contacts one or more parts of the BEOL layer The IC assembly according to claim 9 or 10, including the following:

12. The cross-section of at least one interconnect of the active layer and at least one interconnect of the BEOL interconnect is a trapezoid with two parallel sides, one of which is the shorter side and the other is the longer side. With respect to the trapezoid of the at least one interconnect of the active layer, the shorter side is closer to the glass support structure or the non-semiconductor support structure than the longer side. With respect to the trapezoid of at least one interconnect of the BEOL interconnect, the longer side is closer to the glass support structure or the non-semiconductor support structure than the shorter side. The IC assembly according to any one of claims 9 to 11.

13. The cross-section of at least one interconnect of the power interconnect is a trapezoid with two parallel sides, one of which is the shorter side and the other is the longer side. With respect to the trapezoid of at least one interconnect of the power interconnect, the shorter side is closer to the glass support structure or the non-semiconductor support structure than the longer side. The IC assembly according to claim 12.

14. The plurality of FEOL devices include FEOL transistors having a source region and a drain region. At least one of the plurality of power interconnects is coupled to the source region or the drain region. The IC assembly according to any one of claims 1 to 13.

15. The IC assembly according to any one of claims 1 to 14, wherein the rear power supply structure includes an insulating material encompassing at least a portion of the plurality of power interconnects.

16. The IC assembly according to any one of claims 1 to 15, wherein the BEOL layer includes one or more memory layers, and the one or more memory layers include memory cells including thin-film transistors.

17. An integrated circuit (IC) package, IC assembly and Further IC components coupled to the aforementioned IC assembly The IC assembly is equipped with, A layer comprising multiple transistors, including one or more fin-type transistors, nanoribbon transistors, and nanowire transistors, A backend layer including a plurality of backend interconnects coupled to one or more of the plurality of transistors, A back-side power supply structure including a plurality of power interconnects coupled to one or more of the plurality of transistors, A glass support structure or non-semiconductor support structure having a dielectric constant lower than that of silicon (Si) and in the range of 5 to 10.

5. Includes, The layer containing the plurality of transistors is located between the back-side power supply structure and the back-end layer. The back-end layer is located between the layer containing the plurality of transistors and the glass support structure or the non-semiconductor support structure. IC package.

18. The IC package according to claim 17, wherein the further IC component includes one of a package substrate, an interposer, or a further IC die.

19. A method for manufacturing an integrated circuit (IC) assembly, The process of setting the substrate device (FEOL) on top of the semiconductor support structure, A step of providing a wiring process (BEOL) layer on the FEOL device, wherein the BEOL layer includes a plurality of BEOL interconnects coupled to one or more of the plurality of FEOL devices, The steps include bonding the BEOL layer and the FEOL device to a glass support structure or a non-semiconductor support structure having a dielectric constant lower than that of silicon (Si) and in the range of 5 to 10.5, A step of removing at least a portion of the semiconductor support structure in order to expose a portion of the FEOL device, The step of providing a back-side power supply structure including a plurality of power interconnects coupled to the exposed portion of the FEOL device. A method for providing this.

20. The step of bonding the BEOL layer and the FEOL device configuration to the glass support structure or the non-semiconductor support structure is: The steps include providing one or more bonding materials to at least one surface of the BEOL layer bonded to the glass support structure or the non-semiconductor support structure, and to at least one surface of the glass support structure or the non-semiconductor support structure bonded to the BEOL layer, The steps include: attaching the surface of the BEOL layer, which is bonded to the glass support structure or the non-semiconductor support structure, to the surface of the glass support structure or the non-semiconductor support structure, which is bonded to the BEOL layer; The method according to claim 19, including the method described in claim 19.

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