Lead frame and method for manufacturing the same

Abstract

To provide a lead frame and a manufacturing method thereof that enhance the adhesive strength between a die pad portion, a lead portion and a sealing portion.SOLUTION: A lead frame (100) includes a plurality of lead portions (110), and at least a portion of the top surface of the lead portions (110) and the side wall surfaces of the lead portions (110) are roughened surfaces, and the rough surfaces have an a* value in the CIELab color space in the range of 12 to 19 and a b* value in the range of 12 to 17.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This disclosure relates to a lead frame and a method for manufacturing the same. [Background technology]

[0002] In recent years, there has been a growing demand for miniaturization and thinning of semiconductor devices mounted on substrates. To meet these demands, various types of so-called QFN (Quad Flat Non-leaded package) type semiconductor devices have been proposed. QFN type semiconductor devices are constructed by encapsulating semiconductor elements mounted on the mounting surface of a lead frame with a sealing resin, while leaving a portion of the leads exposed on the back side.

[0003] Conventionally, flip-chip type semiconductor devices are known (see Patent Document 1). In flip-chip type semiconductor devices, when semiconductor elements are mounted on a mounting substrate, the semiconductor elements and the mounting substrate are connected to each other by bumps. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2002-110849 [Patent Document 2] Japanese Patent Publication No. 2019-40994

[0005] In general, flip-chip type semiconductor devices have a short path for moisture from the outside air to penetrate, specifically the distance from the outer periphery of the semiconductor device to the electrodes of the semiconductor element. Therefore, there is a risk of moisture from the air penetrating from the outer periphery of the semiconductor device to the electrodes of the semiconductor element.

[0006] Conventionally, when manufacturing semiconductor packages for automotive applications or those requiring high reliability, die attach films are used to mount semiconductor elements onto die pads. In recent years, however, less expensive die attach pastes have also been used when mounting semiconductor elements onto die pads in such semiconductor packages.

[0007] However, conventionally, when die attach paste is applied to a die pad and then heat-cured after mounting a semiconductor element, a phenomenon called bleed-out occurs where the epoxy resin component in the die attach paste seeps out due to capillary action (see Patent Document 2).

[0008] This embodiment provides a lead frame and a method for manufacturing the same that can produce a semiconductor device capable of suppressing the intrusion of moisture from the air to the electrodes of the semiconductor element.

[0009] This embodiment provides a lead frame and a method for manufacturing the same that can ensure good connection between the bump and the lead frame, and suppress the intrusion of moisture from the outer periphery of the semiconductor device toward the electrodes of the semiconductor element.

[0010] This embodiment provides a lead frame and a method for manufacturing the same, which enables the low-cost production of a lead frame with a roughened surface.

[0011] This embodiment provides a lead frame and a method for manufacturing the same that can suppress the intrusion of moisture from the outer periphery of a semiconductor device toward the electrodes of a semiconductor element.

[0012] This embodiment provides a lead frame and a method for manufacturing the same that can suppress bleed-out and prevent moisture from entering from the outer periphery of a semiconductor device toward the electrodes of a semiconductor element. [Disclosure of the Invention]

[0013] Embodiments of this disclosure relate to the following [1] to

[51] .

[0014] [1] comprising multiple lead portions, at least a portion of the upper surface of the lead portion and the side wall surface of the lead portion are roughened surfaces, and of the CIELab color space of the roughened surface a * The value is in the range of 12 to 19, b * A read frame whose value is in the range of 12 to 17.

[0015] [2] A lead frame comprising multiple lead sections, wherein at least a portion of the upper surface of each lead section and the side wall surface of each lead section are roughened surfaces, and the arithmetic mean curvature Spc of the peaks of the roughened surfaces is 700 mm⁻¹ or greater.

[0016] [3] The lead frame according to [2], wherein the arithmetic mean height Sa of the rough surface is 0.12 μm or more.

[0017] [4] A lead frame according to any one of [1] to [3], wherein a part of the upper surface of the lead portion and the side wall surface of the lead portion are rough surfaces, and a metal plating layer is provided on the non-rough surface of the upper surface of the lead portion.

[0018] [5] The lead frame according to [4], wherein the metal plating layer comprises at least one of an Ag plating layer, a Ni plating layer, a Pd plating layer, and an Au plating layer.

[0019] [6] The lead frame according to any one of [1] to [5], wherein the lead portion includes an inner lead portion that is thinned from the lower surface side of the lead portion, and the lower surface of the inner lead portion is the rough surface.

[0020] [7] A lead frame according to any one of [1] to [5], further comprising a die pad portion on which a semiconductor element is mounted, wherein the plurality of lead portions are arranged around the die pad portion, and the upper surface and the side wall surface of the die pad portion are the rough surface.

[0021] [8] The lead frame according to any one of [1] to [7], wherein the lead frame is used to manufacture a semiconductor device having a sealing portion that seals at least the plurality of lead portions, and the upper surface of the lead portion and the side wall surface of the lead portion that are in contact with the sealing portion are roughened rough surfaces.

[0022] [9] A metal substrate preparation step of preparing a metal substrate having a first surface and a second surface opposite to the first surface; a metal substrate processing step of forming a plurality of lead portions by processing the metal substrate; and a rough surface forming step of roughening at least a part of the upper surface of the lead portions and the side wall surface of the lead portions to form a rough surface, wherein in the rough surface forming step, the a in the CIELab color space of the rough surface * The value is in the range of 12 to 19, b * A method for manufacturing lead frames, in which the lead frame is roughened so that the value is in the range of 12 to 17.

[0023]

[10] A metal substrate preparation step of preparing a metal substrate having a first surface and a second surface opposite to the first surface; a metal substrate processing step of forming a plurality of lead portions by processing the metal substrate; and a rough surface forming step of roughening at least a part of the upper surface of the lead portions and the side wall surface of the lead portions to form a rough surface, wherein in the rough surface forming step, the arithmetic mean curvature Spc of the peaks of the rough surface is 700 mm -1 A method for manufacturing a lead frame, which involves roughening it to the above extent.

[0024]

[11] The method for manufacturing a lead frame according to

[10] , wherein in the surface roughening step, the rough surface is roughened so that the arithmetic mean height Sa of the rough surface is 0.12 μm or more.

[0025]

[12] A method for manufacturing a lead frame according to any one of [9] to

[11] , wherein the lead portion is subjected to alkali treatment after the rough surface forming step.

[0026]

[13] A method for manufacturing a lead frame according to any one of [9] to

[12] , wherein a metal plating layer is provided on a part of the upper surface of the lead portion, and in the roughening step, the upper surface and the side wall surface of the lead portion that are not provided with the metal plating layer are roughened.

[0027]

[14] The method for manufacturing a lead frame according to

[13] , wherein the metal plating layer comprises at least one of an Ag plating layer, a Ni plating layer, a Pd plating layer, and an Au plating layer.

[0028]

[15] A method for manufacturing a lead frame according to any one of [9] to

[14] , wherein in the metal substrate processing step, the lead portion including a thinned inner lead portion is formed from the lower surface side of the lead portion, and in the rough surface forming step, the rough surface is formed on the lower surface of the inner lead portion.

[0029]

[16] A method for manufacturing a lead frame according to any one of [9] to

[15] , comprising the steps of forming a die pad portion on which a semiconductor element is mounted in the metal substrate processing step such that the plurality of lead portions are arranged around the die pad portion, and forming the rough surface in the rough surface forming step by roughening the upper surface of the die pad portion and the side wall surface of the die pad portion, and at least a part of the upper surface of the lead portion and the side wall surface of the lead portion.

[0030]

[17] A lead frame comprising a die pad on which a semiconductor element is mounted, and lead portions located around the die pad, wherein a smooth surface region is formed on the surface of the die pad or the surface of the lead portion, and a rough surface region exists so as to surround the entire circumference of the smooth surface region.

[0031]

[18] The lead frame according to

[17] , wherein the roughened area is formed along the entire periphery of the die pad or the entire periphery of the lead portion in a plan view.

[0032]

[19] The lead frame according to

[17] or

[18] , wherein the lead portion has an inner lead that is thinned from the back side, an inner lead surface is formed on the front side of the inner lead, an inner lead back surface is formed on the back side of the inner lead, an inner lead tip surface is formed on the side of the inner lead that faces the die pad, an external terminal is formed on the portion of the back of the lead portion that is not thinned, the inner lead back surface and the inner lead tip surface are rough surfaces, and the external terminal is a smooth surface.

[0033]

[20] The lead frame according to any one of

[17] to

[19] , wherein the back surface of the die pad is a smooth surface and the side surface of the die pad is a rough surface.

[0034]

[21] The lead frame according to any one of

[17] to

[20] , wherein the smooth surface region is circular, elliptical, or oblong in plan view.

[0035]

[22] The lead frame according to any one of

[17] to

[20] , wherein the smooth surface region is square or rectangular in plan view.

[0036]

[23] The lead frame according to any one of

[17] to

[20] , wherein the region of the smooth surface is a closed figure that includes curves and line segments in a plan view.

[0037]

[24] The lead frame according to any one of

[17] to

[23] , wherein the shortest distance between the smooth surface region and the periphery of the die pad or the lead portion is 0.025 mm or more and 1.0 mm or less.

[0038]

[25] The lead frame according to any one of

[17] to

[24] , wherein the S-ratio of the rough surface is 1.30 or greater, and the S-ratio of the smooth surface is less than 1.30.

[0039]

[26] A method for manufacturing a lead frame, comprising the steps of: preparing a metal substrate; etching the metal substrate to form a die pad and lead portions located around the die pad; forming a plating layer on a part of the metal substrate; forming a rough surface on a portion of the metal substrate not covered by the plating layer; and removing the plating layer, wherein a smooth surface region is formed on the surface of the die pad or the surface of the lead portion, and the rough surface region exists so as to surround the entire circumference of the smooth surface region.

[0040]

[27] A method for manufacturing a lead frame, comprising the steps of: preparing a metal substrate having a die pad and lead portions located around the die pad; forming a plating layer on the outer circumference of the metal substrate, excluding at least a portion of the surface; removing the plating layers while leaving the plating layer present on at least the back surface of the metal substrate; forming a rough surface on the portion of the metal substrate not covered by the plating layer; and removing the plating layer.

[0041]

[28] The method for manufacturing a lead frame according to

[27] , wherein in the step of forming the plating layer, the plating layer is not formed over the entire surface of the metal substrate.

[0042]

[29] The method for manufacturing a lead frame according to

[27] , wherein in the step of forming the plating layer, the plating layer is formed on a part of the surface of the lead portion, and in the step of removing the other plating layers, the plating layer present on a part of the surface of the lead portion is left intact.

[0043]

[30] The method for manufacturing a lead frame according to

[29] , further comprising the step of forming a metal layer on a part of the surface of the metal substrate after the step of removing the plating layer.

[0044]

[31] The method for manufacturing a lead frame according to any one of

[27] to

[30] , wherein the S-ratio of the rough surface is 1.30 or greater.

[0045]

[32] A lead frame comprising a die pad on which a semiconductor element is mounted, and a lead portion located around the die pad, wherein the lead portion has an inner lead that is thinned from the back side, an inner lead surface is formed on the front side of the inner lead, an inner lead back surface is formed on the back side of the inner lead, an inner lead tip surface is formed on the side of the inner lead that faces the die pad, an external terminal is formed on the portion of the back surface of the lead portion that is not thinned, at least a part of the inner lead surface, the inner lead back surface and the inner lead tip surface are rough surfaces, and the external terminal is a smooth surface.

[0046]

[33] The reed frame according to

[32] , wherein the entire surface of the inner reed is rough.

[0047]

[34] The lead frame according to

[32] , wherein a metal layer is formed on the surface of the inner lead, and the portion of the inner lead surface on which the metal layer is formed is a smooth surface.

[0048]

[35] A lead frame comprising a die pad on which a semiconductor element is mounted, and a lead portion located around the die pad, wherein a portion of the lead portion is thinned from the back side, and the thinned portion of the back side of the lead portion is a rough surface, and the non-thinned portion is a smooth surface.

[0049]

[36] The lead frame according to

[35] , wherein a metal layer is located on the surface of the lead portion, and of the surface of the lead portion, a first surface portion adjacent to the outside of the metal layer is a smooth surface, and a second surface portion adjacent to the outside of the first surface portion is a rough surface.

[0050]

[37] The lead frame according to

[35] , wherein a metal layer is located on the surface of the lead portion, a recess is formed on the surface of the lead portion outside the metal layer, a third surface portion adjacent to the outside of the recess is rough, and the inner surface of the recess is smooth.

[0051]

[38] The lead frame according to

[35] , wherein a metal layer is located on the surface of the lead portion, a recess is formed on the surface of the lead portion outside the metal layer, a third surface portion adjacent to the outside of the recess is rough, and the inner surface of the recess is rough.

[0052]

[39] The lead frame according to any one of

[35] to

[38] , wherein the front and back surfaces of the die pad are smooth, and the side surface of the die pad is rough.

[0053]

[40] The lead frame according to any one of

[35] to

[39] , wherein the lead portion has an inner lead that is thinned from the back side, and an inner lead tip surface is formed on the side of the inner lead that faces the die pad, and the inner lead tip surface is a rough surface.

[0054]

[41] The lead frame according to any one of

[35] to

[40] , wherein the S-ratio of the rough surface is 1.30 or greater, and the S-ratio of the smooth surface is less than 1.30.

[0055]

[42] A method for manufacturing a lead frame, comprising the steps of: preparing a metal substrate; etching the metal substrate to form a die pad and a lead portion located around the die pad and partially thinned from the back side; forming a plating layer around the metal substrate; removing a portion of the plating layer present in a region where a rough surface is to be formed; forming a rough surface on the portion of the metal substrate not covered by the plating layer; and removing the plating layer, wherein the thinned portion of the back side of the lead portion becomes a rough surface and the unthinned portion becomes a smooth surface.

[0056]

[43] A lead frame comprising a die pad on which a semiconductor element is mounted, and a lead portion located around the die pad, wherein a first rough surface is formed on at least a portion of the surface of the die pad, and a second rough surface is formed on at least a portion of the surface of the lead portion, and the roughness of the second rough surface of the lead portion is rougher than the roughness of the first rough surface of the die pad.

[0057]

[44] The lead frame according to

[43] , wherein a third rough surface is formed on the side surface of the die pad, and the roughness of the third rough surface of the die pad is rougher than the roughness of the first rough surface of the die pad.

[0058]

[45] The lead frame according to

[43] or

[44] , wherein the lead portion has an inner lead that is thinned from the back side, an inner lead back surface is formed on the back side of the inner lead, a fourth rough surface is formed on the inner lead back surface, and the roughness of the fourth rough surface of the lead portion is rougher than the roughness of the first rough surface of the die pad.

[0059]

[46] The lead frame according to any one of

[43] to

[45] , wherein the lead portion has an inner lead that is thinned from the back side, an inner lead tip surface is formed on the inner lead tip surface facing the die pad, a fifth rough surface is formed on the inner lead tip surface, and the roughness of the fifth rough surface of the lead portion is rougher than the roughness of the first rough surface of the die pad.

[0060]

[47] A lead frame according to any one of

[43] to

[46] , wherein a smooth surface area is formed on the surface of the lead portion.

[0061]

[48] ​​The lead frame according to

[47] , wherein a metal layer is formed in the region of the smooth surface.

[0062]

[49] The lead frame according to

[47] , wherein the region of the smooth surface is exposed outward.

[0063]

[50] A lead frame according to any one of

[43] to

[49] , wherein the S-ratio of the first rough surface is 1.10 or more and less than 1.30, and the S-ratio of the second rough surface is 1.30 or more and 2.30 or less.

[0064]

[51] A method for manufacturing a lead frame, comprising the steps of: preparing a metal substrate; etching the metal substrate to form a die pad and lead portions located around the die pad; forming a coating layer on the die pad and the lead portions; removing the coating layer present on at least a portion of the surface of the die pad; forming a first rough surface on the portion of the die pad not covered by the coating layer; removing the coating layer present on at least a portion of the surface of the lead portions; and forming a second rough surface on the portion of the lead portions not covered by the coating layer, wherein the roughness of the second rough surface on the lead portions is rougher than the roughness of the first rough surface on the die pad.

[0065] According to this embodiment, it is possible to manufacture a semiconductor device that can suppress the intrusion of moisture from the air to the electrodes of the semiconductor element.

[0066] According to this embodiment, the bump and the lead frame are connected well, and the intrusion of moisture from the outer periphery of the semiconductor device toward the electrodes of the semiconductor element can be suppressed.

[0067] According to this embodiment, lead frames with a roughened surface can be manufactured at low cost.

[0068] According to this embodiment, it is possible to suppress the intrusion of moisture from the outer periphery of the semiconductor device toward the electrodes of the semiconductor element.

[0069] According to this embodiment, bleed-out can be suppressed, and moisture can be prevented from entering from the outer periphery of the semiconductor device toward the electrodes of the semiconductor element. [Brief explanation of the drawing]

[0070] [Figure 1] Figure 1 is a plan view showing a lead frame according to the first embodiment. [Figure 2] Figure 2 is a partially cut-off end view of a lead frame according to the first embodiment. [Figure 3] Figure 3 is a plan view showing a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a partial cross-sectional view of a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a partial cross-sectional view of a semiconductor device according to a modified example of the first embodiment. [Figure 6A] Figure 6A is a process diagram illustrating the manufacturing method of a lead frame according to the first embodiment. [Figure 6B] Figure 6B is a process diagram following Figure 6A, illustrating the manufacturing method of the lead frame according to the first embodiment. [Figure 6C] Figure 6C is a process diagram following Figure 6B, illustrating the manufacturing method of the lead frame according to the first embodiment. [Figure 6D] Figure 6D is a process diagram following Figure 6C, illustrating the manufacturing method of the lead frame according to the first embodiment. [Figure 6E] Figure 6E is a process diagram following Figure 6D, illustrating the manufacturing method of the lead frame according to the first embodiment. [Figure 6F] Figure 6F is a process diagram following Figure 6E, illustrating the manufacturing method of the lead frame according to the first embodiment. [Figure 6G] Figure 6G is a process diagram following Figure 6F, illustrating the manufacturing method of the lead frame according to the first embodiment. [Figure 6H] Figure 6H is a process diagram following Figure 6G, illustrating the manufacturing method of the lead frame according to the first embodiment. [Figure 7A] Figure 7A is a process diagram illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 7B]Figure 7B is a process diagram following Figure 7A, illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 7C] Figure 7C is a process diagram following Figure 7B, illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 7D] Figure 7D is a process diagram following Figure 7C, illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 8] Figure 8 is a plan view showing a lead frame according to the second embodiment. [Figure 9] Figure 9 is a cross-sectional view (cross-sectional view along line IX-IX in Figure 8) showing the lead frame according to the second embodiment. [Figure 10] Figures 10(a) and (b) are enlarged plan views showing the surface of the die pad and the surface of the lead portion, respectively. [Figure 11] Figure 11 is a plan view showing a semiconductor device according to the second embodiment. [Figure 12] Figure 12 is a cross-sectional view (cross-sectional view along line XII-XII in Figure 11) showing a semiconductor device according to the second embodiment. [Figure 13] Figures 13(a) and (b) are enlarged cross-sectional views showing the bumps as connection points, respectively. [Figure 14] Figures 14(a)-(i) are cross-sectional views showing a method for manufacturing a lead frame according to the second embodiment. [Figure 15] Figures 15(a)-(d) are cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 16] Figure 16 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 17] Figures 17(a)-(d) are enlarged plan views showing the surface of the die pad and the surface of the lead portion according to a modified example of the second embodiment, respectively. [Figure 18] Figure 18 is a plan view showing a lead frame according to the third embodiment. [Figure 19] Figure 19 is a cross-sectional view (cross-sectional view along line XIX-XIX in Figure 18) showing a lead frame according to the third embodiment. [Figure 20] Figure 20 is a plan view showing a semiconductor device according to the third embodiment. [Figure 21] Figure 21 is a cross-sectional view (cross-sectional view along line XXI-XXI in Figure 20) showing a semiconductor device according to the third embodiment. [Figure 22] Figure 22 is an enlarged cross-sectional view showing the bump as a connecting section. [Figure 23] Figures 23(a)-(i) are cross-sectional views showing a method for manufacturing a lead frame according to the third embodiment. [Figure 24] Figures 24(a)-(d) are cross-sectional views showing a method for manufacturing a semiconductor device according to the third embodiment. [Figure 25] Figure 25 is a partially enlarged cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 26] Figure 26 is a cross-sectional view showing a lead frame according to the fourth embodiment. [Figure 27] Figure 27 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. [Figure 28] Figures 28(a)-(j) are cross-sectional views showing a method for manufacturing a lead frame according to the fourth embodiment. [Figure 29] Figure 29 is a partially enlarged cross-sectional view showing a semiconductor device according to the fourth embodiment. [Figure 30] Figure 30 is a plan view showing a lead frame according to the fifth embodiment. [Figure 31] Figure 31 is a cross-sectional view showing a lead frame according to the fifth embodiment (cross-sectional view along line XXXI-XXXI in Figure 30). [Figure 32] Figure 32 is a plan view showing a semiconductor device according to the fifth embodiment. [Figure 33] Figure 33 is a cross-sectional view (cross-sectional view along line XXXIII-XXXIII in Figure 32) showing a semiconductor device according to the fifth embodiment. [Figure 34] Figure 34 is an enlarged cross-sectional view showing the bump as a connection point. [Figure 35] Figures 35(a)-(j) are cross-sectional views showing a method for manufacturing a lead frame according to the fifth embodiment. [Figure 36] Figures 36(a)-(d) are cross-sectional views showing a method for manufacturing a semiconductor device according to the fifth embodiment. [Figure 37] Figure 37 is a partially enlarged cross-sectional view showing a semiconductor device according to the fifth embodiment. [Figure 38] Figure 38 is a cross-sectional view showing a lead frame according to the sixth embodiment. [Figure 39] Figure 39 is a cross-sectional view showing a semiconductor device according to the sixth embodiment. [Figure 40] Figures 40(a)-(j) are cross-sectional views showing a method for manufacturing a lead frame according to the sixth embodiment. [Figure 41] Figure 41 is a partially enlarged cross-sectional view showing a semiconductor device according to the sixth embodiment. [Figure 42] Figure 42 is a cross-sectional view showing a lead frame according to the seventh embodiment. [Figure 43] Figure 43 is a cross-sectional view showing a semiconductor device according to the seventh embodiment. [Figure 44] Figures 44(a)-(j) are cross-sectional views showing a method for manufacturing a lead frame according to the seventh embodiment. [Figure 45] Figure 45 is a partially enlarged cross-sectional view showing a semiconductor device according to the seventh embodiment. [Figure 46] Figure 46 is a cross-sectional view showing a lead frame according to the eighth embodiment. [Figure 47] Figure 47 is a cross-sectional view showing a semiconductor device according to the eighth embodiment. [Figure 48] Figures 48(a)-(j) are cross-sectional views showing a method for manufacturing a lead frame according to the eighth embodiment. [Figure 49] Figure 49 is a partially enlarged cross-sectional view showing a semiconductor device according to the eighth embodiment. [Figure 50] Figure 50 is a plan view showing a lead frame according to the ninth embodiment. [Figure 51] Figure 51 is a cross-sectional view showing a lead frame according to the ninth embodiment (LI-LI line cross-section in Figure 50). [Figure 52] Figure 52 is a plan view showing a semiconductor device according to the ninth embodiment. [Figure 53] Figure 53 is a cross-sectional view (cross-sectional view along line LIII-LIII in Figure 52) showing a semiconductor device according to the ninth embodiment. [Figure 54] Figures 54(a)-(e) are cross-sectional views showing a method for manufacturing a lead frame according to the ninth embodiment. [Figure 55] Figures 55(a)-(h) are cross-sectional views showing a method for manufacturing a lead frame according to the ninth embodiment. [Figure 56] Figures 56(a)-(e) are cross-sectional views showing a method for manufacturing a semiconductor device according to the ninth embodiment. [Figure 57] Figure 57 is a partially enlarged cross-sectional view showing a semiconductor device according to the ninth embodiment. [Figure 58] Figure 58 is a cross-sectional view showing a lead frame according to a modified example of the ninth embodiment. [Modes for carrying out the invention]

[0071] (First Embodiment) The first embodiment will be described below with reference to Figures 1 to 7D. The embodiments of this disclosure will be described below with reference to the drawings. Note that the drawings are schematic or conceptual, and the dimensions of each component, the ratio of sizes between components, etc., are not necessarily the same as those of actual objects. Furthermore, even when representing the same components, the dimensions and ratios may be represented differently in the drawings. In addition, in the drawings attached to this specification, the shape, scale, and aspect ratio of each part may be changed or exaggerated from the actual object in order to facilitate understanding.

[0072] In this specification, a numerical range indicated by "~" means a range that includes the numerical values ​​before and after "~" as the lower and upper limits, respectively. Also, in this specification, terms such as "film," "sheet," and "plate" are not distinguished from each other based on differences in naming. For example, "plate" is a concept that includes components that may generally be called "sheet" or "film."

[0073] [Lead frame] Embodiments of the lead frame of this disclosure will now be described. The lead frame 100 according to this embodiment is used to manufacture a semiconductor device 200 (see Figures 3 and 4). The lead frame 100 comprises a plurality of package regions 100A. The plurality of package regions 100A are arranged in multiple rows and multiple layers (matrix). Note that in Figure 1, only a portion of the lead frame 100 centered on one package region 100A is shown.

[0074] The package region 100A is the region corresponding to the semiconductor device 200, which will be described later, and is the region surrounded by a rectangular imaginary line (dashed line shown in Figure 1) (see Figure 1). In this embodiment, the lead frame 100 is shown as an example that includes multiple package regions 100A, but the embodiment is not limited to this, and the lead frame 100 may consist of only one package region 100A.

[0075] In this specification, "inside" and "inside" refer to the side of each package region 100A facing toward the center, and "outside" and "outside" refer to the side away from the center of each package region 100A (the connecting bar 130 side). Furthermore, "top surface" refers to the surface on which the semiconductor element 210 is mounted, "bottom surface" refers to the surface opposite the "top surface" that is connected to an external mounting substrate (not shown), and "sidewall surface" refers to the surface located between the "top surface" and the "bottom surface" that constitutes the thickness of the lead frame 100 (metal substrate 310).

[0076] Furthermore, in this specification, half-etching refers to etching the material to be etched partway in its thickness direction. The thickness of the material to be etched after half-etching is 30% to 70%, preferably 40% to 60%, of the thickness of the material to be etched before half-etching.

[0077] As shown in Figures 1 and 2, each package region 100A of the lead frame 100 includes a plurality of lead portions 110, a die pad portion 120, and a connecting bar 130 that connects the lead portions 110. The lead portion 110 may include an inner lead portion 111 and a terminal portion 113. The inner lead portion 111 is a thinned portion from the bottom side and is located on the inside (towards the die pad portion 120) in each package region 100A. The terminal portion 113 is located on the outside (towards the connecting bar 130) in each package region 100A. The inner lead portion 111 extends from the terminal portion 113 towards the die pad portion 120. An internal terminal is formed on the upper side of the inner lead portion 111. This internal terminal is a region that is electrically connected to the semiconductor element 210 via a connecting member 220, as will be described later. A metal plating layer 112 is provided on the internal terminal to improve adhesion with the connecting member 220.

[0078] Each lead portion 110 is connected to the semiconductor element 210 via a connecting member 220, as will be described later, and is positioned with a space between it and the die pad portion 120 (see Figures 4 and 5). The multiple lead portions 110 are arranged at intervals from each other along the longitudinal direction of the connecting bar 130. Each lead portion 110 extends from the connecting bar 130.

[0079] The lead portion 110 is arranged along the periphery of the die pad portion 120. A portion of the lead portion 110 is thinned from the bottom side. This thinned portion from the bottom side is the inner lead portion 111. The portion of the lead portion 110 that is not thinned from the bottom side is the terminal portion 113, and an external terminal 150 is formed on the bottom surface of the terminal portion 113. The external terminal 150 is the part that is electrically connected to an external mounting substrate (not shown). The external terminal 150 is the part that is exposed to the outside of the semiconductor device 200, which will be described later.

[0080] The inner lead portion 111 is thinned from the lower side, for example, by half-etching. The inner lead portion 111 has an inner lead portion upper surface 111A, an inner lead portion lower surface 111B facing the inner lead portion upper surface 111A, and an inner lead portion side wall surface. The inner lead portion upper surface 111A is part of the upper surface of the lead portion 110. The inner lead side wall surface includes a die pad portion facing surface 111C that faces the die pad portion 120, and surfaces that face each other in adjacent lead portions 110. The inner lead portion lower surface 111B is located on the lower side of the lead portion 110.

[0081] The terminal portion 113 is located on the connecting bar 130 side. The terminal portion 113 is connected to the connecting bar 130. The lower surface of the terminal portion 113 constitutes the external terminal 150 described above. The terminal portion 113 has the same thickness as the die pad portion 120 without being half-etched. A portion of the lower surface of the terminal portion 113 located on the connecting bar 130 side may be thinned to form a connection portion with the connecting bar 130.

[0082] At least a portion of the upper surface and the side wall surface of the lead portion 110 are roughened surfaces, while the lower surface of the lead portion 110 (terminal portion 113) is an unroughened surface. The lower surface 111B of the inner lead portion is a roughened surface. In Figure 1, etc., the roughened surfaces are indicated by thick dashed lines.

[0083] In this embodiment, when the term "rough surface" is used, it means a roughened surface, preferably a roughened surface achieved by micro-etching or the like.

[0084] The thinned portion of the lower surface of the lead portion 110 has a roughened surface. Specifically, the entire lower surface 111B of the inner lead portion has a roughened surface. On the other hand, the portion of the lower surface of the lead portion 110 that has not been thinned has a non-roughened surface. Specifically, the terminal portion 113 is not thinned from the lower side, and the entire external terminal 150 located on the lower side of the terminal portion 113 has a non-roughened surface. The entire side wall surface of the inner lead portion, including the die pad opposing surface 111C, has a roughened surface.

[0085] A portion of the upper surface of the lead portion 110 (inner lead portion 111) located on the die pad portion 120 side may be a non-roughened surface, and a metal plating layer 112 may be provided on this non-roughened surface. The metal plating layer 112 may be formed, for example, by an electroplating method. The thickness of the metal plating layer 112 may be in the range of 1 μm to 10 μm. The metal plating layer 112 may be, for example, an Ag plating layer, an Ag alloy plating layer, an Au plating layer, an Au alloy plating layer, a Pt plating layer, a Cu plating layer, a Cu alloy plating layer, a Pd plating layer, a Ni plating layer, etc., and may contain one or more of these. It is preferable that the metal plating layer 112 contains at least one of the Ag plating layer, Ni plating layer, Pd plating layer, and Au plating layer. Furthermore, if an undercoat is required depending on the composition of the metal plating layer 112, a known undercoat may be applied. For example, a Ni plating layer or a Cu plating layer can be used as an undercoat.

[0086] A semiconductor element 210 is mounted on the upper surface of the die pad portion 120, as will be described later. In addition, multiple lead portions 110 may be arranged around the die pad portion 120. The upper surface and side walls of the die pad portion 120 may be roughened surfaces, while the lower surface of the die pad portion 120 may be an unroughened surface (see Figure 2).

[0087] The upper surface of the die pad portion 120 is an area (internal terminal) that is joined to the semiconductor element 210 via an adhesive 240 such as die attach paste, as will be described later. The lower surface of the die pad portion 120 is an unroughened surface that is not thinned by, for example, half etching, and is similar to the metal substrate 310 before processing, as will be described later. The lower surface of the die pad portion 120 is exposed to the outside in the semiconductor device 200, which will be described later.

[0088] Each package region 100A is connected to the others via a connecting bar 130, which extends along the X and Y directions, respectively. The X and Y directions are two directions parallel to each side of the package region 100A within the plane of the lead frame 100, and the X and Y directions are orthogonal to each other.

[0089] Each connecting bar 130 is positioned around the package area 100A, but outside of the package area 100A. Each connecting bar 130 has an elongated rod shape in plan view. The width W of each connecting bar 130 (the distance in the direction perpendicular to the longitudinal direction of the connecting bar 130) is not particularly limited, but can be appropriately set in the range of, for example, 95 μm to 250 μm. Multiple lead portions 110 are connected to each connecting bar 130 at predetermined intervals along the longitudinal direction of the connecting bar 130, and the die pad portion 120 is supported on the connecting bar 130 via suspension leads 140. In this embodiment, the connecting bar 130 is not thinned, but the embodiment is not limited to this. For example, the connecting bar 130 may be thinned by half-etching from its lower surface. In this case, the thickness of the connecting bar 130 can be set considering the configuration of the semiconductor device 200, etc. The thickness of the connecting bar 130 can be appropriately set in the range of, for example, 80 μm to 200 μm.

[0090] The lead frame 100 according to this embodiment is used for manufacturing a semiconductor device 200 including a sealing portion 230 to be described later. The upper surface and the side wall surface of the lead portion 110 that come into contact with the sealing portion 230 may be roughened surfaces. Also, the upper surface and the side wall surface of the lead portion 110 located outside the package region 100A, and the connecting bar 130 may be roughened surfaces or non-roughened surfaces that are not roughened. When manufacturing the semiconductor device 200 using the lead frame 100, dicing is performed along the connecting bar 130. At this time, if each package region 100A is individually molded and diced, foreign matter may be generated when dicing the lead frame 100 if the upper surface of the connecting bar 130 is a roughened surface. Therefore, by making the upper surface of the connecting bar 130 a non-roughened surface that is not roughened, generation of foreign matter can be suppressed when manufacturing the semiconductor device 200.

[0091] In the roughened surface of the lead frame 100 according to this embodiment, in the CIELab color space, a * value is in the range of 12 to 19, and b * value is in the range of 12 to 17. Preferably, a * value is in the range of 13 to 18, and b * value is in the range of 12 to 16. As will be clear from the examples to be described later, when the a * value and b * value in the CIELab color space of the roughened surface of the lead frame 100 according to this embodiment are within a predetermined range, the surface area ratio will be high. Therefore, in a semiconductor device that can be manufactured using the lead frame 100, the adhesion strength with the mold resin increases. Thereby, it is possible to suppress moisture in the air from entering up to the electrodes of the semiconductor element. That is, when the a * value and b * value in the CIELab color space of the roughened surface of the lead frame 100 according to this embodiment are within the above range, it is possible to manufacture a semiconductor device capable of suppressing moisture in the air from entering up to the electrodes of the semiconductor element. In this embodiment, a *Value and b * The values ​​are measured using the eXact spectrophotometer (manufactured by X-rite).

[0092] Here, in the CIELab color space (L * a * b * Let's explain color space. * a * b * The color space is the CIELab chromaticity diagram recommended by the CIE. * This represents brightness, a * represents the degree of red / magenta or green, and b * This indicates the degree of yellow or blue. * The closer the value of is to the negative side, the closer it gets to green, and the closer it gets to the positive side, the closer it gets to red. Also, b * The closer the value is to the negative side, the closer it gets to blue; the closer it is to the positive side, the closer it gets to yellow. * When the value of is 100, it shows white (total internal reflection), L * When the value of is 0, it represents black (total absorption). The middle of these three values ​​represents an intermediate color (gray). That is, L * Movement in the axial direction indicates a change in brightness, a * b * Movement on a plane indicates a change in hue. * a * b * Distance in space corresponds to the closeness of colors, and the closer the distance, the closer the colors are. In the rough surface of the lead frame 100 according to this embodiment, a * The value is between red / magenta and green, b * The values ​​can be said to fall within the predetermined range between yellow and blue.

[0093] Furthermore, in the lead frame 100 according to this embodiment, the arithmetic mean curvature Spc of the peaks of the rough surface is 700 mm -1 The above, preferably 1000 mm -1 ~5000mm -1 And more preferably 2000mm -1 ~4000mm -1As will be clear from the embodiments described later, if the arithmetic mean curvature Spc of the peaks of the rough surface in the lead frame 100 according to this embodiment is within a predetermined range, it indicates that the contact points with the object to be contacted are sharp. In this case, the adhesion strength with the molding resin will be increased in the semiconductor device manufactured using the lead frame 100, and it will be possible to suppress the penetration of moisture from the air to the electrodes of the semiconductor element. That is, by having the arithmetic mean curvature Spc of the peaks of the rough surface in the lead frame 100 according to this embodiment be within the above range, it is possible to manufacture a semiconductor device that can suppress the penetration of moisture from the air to the electrodes of the semiconductor element. Furthermore, it is preferable that the arithmetic mean height Sa of the rough surface be 0.12 μm or more, and more preferably in the range of 0.12 μm to 0.34 μm. -1 As described above, by ensuring that the arithmetic mean height Sa of the rough surface is within a predetermined range, it is possible to manufacture a semiconductor device that can effectively suppress the penetration of moisture from the air to the electrodes of the semiconductor element. The arithmetic mean curvature Spc of the peaks represents the average of the principal curvatures of the peaks present in an object, and the sharper the peak, the larger the value of the arithmetic mean curvature Spc of the peaks. The arithmetic mean height Sa is a parameter that extends the arithmetic mean height Ra of a line to three dimensions, i.e., a surface, and is a numerical value that represents the average of the absolute values ​​of the height differences of each point relative to the average plane of the surface. In this embodiment, the arithmetic mean curvature Spc and the arithmetic mean height Sa of the peaks are measured using a laser microscope VK-X260 (manufactured by Keyence Corporation, measurement unit) and a laser microscope VK-X250 (manufactured by Keyence Corporation, controller unit).

[0094] Generally, lead frames used in QFN (Quad Flat Non-leaded package) type semiconductor devices have been increasingly required in recent years to be smaller and thinner. In such semiconductor devices, the distance from the outer periphery to the electrodes of the semiconductor element, which is the path through which moisture contained in the outside air can penetrate, tends to be shorter, and there is a risk that moisture from the air may penetrate to the electrodes of the semiconductor element, causing the semiconductor device to malfunction.

[0095] Therefore, the inventors realized that the roughened surface condition of the lead frame is important in lead frames used in semiconductor devices. Furthermore, from the viewpoint of reliability required for semiconductor devices, they realized that the CIELab color space or the arithmetic mean curvature Spc and arithmetic mean height Sa of the peak should be considered as indicators of the surface condition. And among the CIELab color space a * The value is in the range of 12 to 19, b * If the value is in the range of 12 to 17, or if the arithmetic mean curvature Spc of the peak of the rough surface is 700 mm -1 The present invention was completed by realizing that a highly reliable lead frame, as required for semiconductor devices, can be obtained when the arithmetic mean height Sa of the rough surface is 0.12 μm or greater.

[0096] The roughened surface according to this embodiment may be formed, for example, by roughening the metal substrate 310, which will be described later, with a micro-etching solution. Examples of micro-etching solutions that can be used in this embodiment include those containing sulfuric acid or hydrochloric acid as the main component, and those containing hydrogen peroxide and sulfuric acid as the main components.

[0097] In this embodiment, the rough surface is a color in the CIELab color space. * The value is in the range of 12 to 19, b * The value is in the range of 12 to 17. Also, the arithmetic mean curvature Spc of the peak of the rough surface is 700 mm. -1 The above conditions are met, and the arithmetic mean height Sa of the rough surface is 0.12 μm or more. By having a rough surface within this predetermined range, it is possible to manufacture a semiconductor device that can suppress the penetration of moisture from the air to the electrodes of the semiconductor element.

[0098] The lead frame 100 described above is made of a metal such as copper, a copper alloy, or a Ni alloy. The thickness of the lead frame 100 can be set considering the configuration of the semiconductor device 200, but the thickness of the lead frame 100 can be appropriately set in the range of, for example, 80 μm to 300 μm.

[0099] In this embodiment, the lead portion 110 is arranged along all four sides of the package area 100A, but is not limited to this, and may be arranged along only two opposing sides of the package area 100A, for example.

[0100] Although the lead frame 100 shown in Figures 1 and 2 has been described in an embodiment that includes a die pad portion 120, it is not limited to this embodiment, and it does not have to include a die pad portion 120. For example, each lead portion 110 may be connected to the semiconductor element 210 via bumps as a connecting member 220, as will be described later (see Figure 5).

[0101] [Semiconductor device] Embodiments of the semiconductor device of the present disclosure will now be described. As shown in Figures 3 and 4, the semiconductor device 200 includes a plurality of lead portions 110, a die pad portion 120, a semiconductor element 210, a connecting member 220, and a sealing portion 230.

[0102] The semiconductor device 200 in this embodiment is manufactured using the lead frame 100 described above. Therefore, the lead portion 110 and the die pad portion 120 of the semiconductor device 200 are provided on the lead frame 100 described above. For this reason, the upper surface of the lead portion 110 that is outside the metal plating layer 112 (the side farther from the die pad portion 120) and the side wall surface of the lead portion 110 are roughened surfaces. The upper surface and the side wall surface of the die pad portion 120 are also roughened surfaces. As shown in Figure 4, the lead portion 110 includes an inner lead portion 111 that is thinned from the lower side of the lead portion 110, and the lower surface 111B of the inner lead portion is a rough surface. The sealing portion 230 is in close contact with the lower surface 111B of the inner lead portion. The terminal portion 113 of the lead portion 110 is not thinned from the lower side. The external terminal 150 located on the lower surface of the terminal portion 113 is a non-roughened surface. The external terminal 150 is exposed from the sealing portion 230.

[0103] Among the CIELab color space in the above rough surface, a * The value is in the range of 12 to 19, b *The value is in the range of 12 to 17. (a) in the CIELab color space for rough surfaces. * Value and b * By keeping the value within the above range, it is possible to suppress the intrusion of moisture from the air into the electrodes of the semiconductor element 210.

[0104] Furthermore, the arithmetic mean curvature Spc of the peaks on the above rough surface is 700 mm. -1 That's all. The arithmetic mean curvature Spc of the mountain peak is 700 mm. -1 The above conditions prevent moisture from the air from penetrating to the electrodes of the semiconductor element 210. Furthermore, it is preferable that the arithmetic mean height Sa of the rough surface is 0.12 μm or more, and more preferably in the range of 0.12 μm to 0.34 μm. The arithmetic mean curvature Spc of the peaks of the rough surface is 700 mm. -1 As described above, by keeping the arithmetic mean height Sa of the rough surface within a predetermined range, it is possible to more effectively suppress the penetration of moisture from the air up to the electrodes of the semiconductor element 210.

[0105] The semiconductor element 210 can be any type of semiconductor element commonly used in the past, and is not particularly limited; for example, integrated circuits, large-scale integrated circuits, transistors, thyristors, diodes, etc., can be used. This semiconductor element 210 has a plurality of electrodes 210A to which connecting members 220 are attached.

[0106] Each connecting member 220 is made of a highly conductive metal material such as copper or gold, and one end of each connecting member 220 is electrically connected to the electrode 210A of the semiconductor element 210, and the other end is electrically connected to the metal plating layer 112 located on each lead portion 110. Examples of materials that can be used as connecting members 220 include conductive materials such as bonding wires and bumps.

[0107] The sealing portion 230 seals at least the lead portion 110, the die pad portion 120, the semiconductor element 210, and the connecting member 220. The sealing portion 230 may be made of a resin such as a thermosetting resin such as silicone resin or epoxy resin, or a thermoplastic resin such as PPS resin. The overall thickness of the sealing portion 230 is not particularly limited, but can be appropriately set in a range of approximately 300 μm to 1500 μm. In a plan view of the semiconductor device 200, the length of one side of the sealing portion 230 (one side of the semiconductor device 200) is not particularly limited, but can be appropriately set in a range of approximately 0.2 mm to 20 mm.

[0108] Although the semiconductor device 200 shown in Figures 3 and 4 has been described in an embodiment that includes a die pad portion 120, it is not limited to this embodiment, and it does not have to include a die pad portion 120. For example, each lead portion 110 may be connected to the electrode 210A of the semiconductor element 210 via a bump as a connecting member 220 (see Figure 5).

[0109] [How to manufacture a lead frame] The manufacturing method of the lead frame 100 shown in Figures 1 and 2 will be explained as an example. Figures 6A to 6H are process diagrams illustrating the manufacturing method of the lead frame according to this embodiment.

[0110] <Metal substrate preparation process> As shown in Figures 6A and 6B, a metal substrate 310 having a first surface 310A and a second surface 310B facing the first surface 310A is prepared (see Figure 6A). Examples of metal substrates 310 that can be used in this embodiment include pure copper substrates, copper alloy substrates, and 42 alloy (Fe alloy with 42% Ni) substrates, but pure copper substrates or copper alloy substrates are preferred. Furthermore, the metal substrate 310 may be used after degreasing and cleaning the first surface 310A and the second surface 310B.

[0111] <Metal substrate processing process> Next, a photosensitive resist 320 is applied to the first surface 310A and the second surface 310B of the metal substrate 310, respectively, and then dried (see Figure 6B). In this embodiment, a conventionally known photosensitive resist 320 can be used.

[0112] Next, the metal substrate 310 is exposed to light through a photomask and developed to form a resist layer 340 having the desired aperture 330 (see Figure 6C).

[0113] Next, the metal substrate 310 is etched with an etching solution using the resist layer 340 as a corrosion-resistant film (see Figure 6D). The etching solution can be appropriately selected depending on the material of the metal substrate 310 used. For example, when a pure copper substrate is used as the metal substrate 310, a ferric chloride aqueous solution is usually used as the etching solution, and spray etching may be performed on both the first surface 310A and the second surface 310B of the metal substrate 310. This forms the outer shape of the lead portion 110, the die pad portion 120, and the connecting bar 130. At this time, the lower surface of a part of the lead portion 110 may be thinned by half-etching, and the inner lead portion 111 and the terminal portion 113 may be formed.

[0114] Next, the resist layer 340 is peeled off and a coating layer 350 is formed on the surface of the etched metal substrate 310 (see Figure 6E). This forms a coating layer 350 around the entire circumference of the lead portion 110, the die pad portion 120, and the connecting bar 130. The thickness of the coating layer 350 is not particularly limited, but for example, it may be greater than 0 μm and less than or equal to 2 μm. The metal used to form the coating layer 350 is also not particularly limited, but for example, silver may be used. If the coating layer 350 consists of a silver plating layer, a silver plating solution mainly composed of silver cyanide and potassium cyanide can be used as the electroplating solution. It is preferable not to form the coating layer 350 on the external terminal 150 on the lower surface of the lead portion 110 (terminal portion 113) and on the lower surface of the die pad portion 120. To avoid forming a coating layer 350 on the lower surface of the external terminal 150 on the lower surface of the lead portion 110 (terminal portion 113) and on the lower surface of the die pad portion 120, for example, a resist layer 400 may be formed on the lower surface of the external terminal 150 on the lower surface of the lead portion 110 (terminal portion 113) and on the lower surface of the die pad portion 120 to avoid the formation of the coating layer 350 (see Figure 6E).

[0115] Next, the coating layer 350 present in the area where the rough surface is formed is removed. Specifically, the coating layer 350 formed on the upper surface of the lead portion 110 other than the area where the metal plating layer 112 is provided, the side wall surface of the lead portion 110, the lower surface of the inner lead portion 111, the upper surface of the die pad portion 120, and the side wall surface of the die pad portion 120 is removed (see Figure 6F). During this time, as shown in Figure 6F, elastic members 410 such as rubber gaskets are placed on the first surface 310A and the second surface 310B of the metal substrate 310, respectively, and the metal substrate 310 is sandwiched by a jig 420 via the elastic members 410. Next, the coating layer 350 in the parts not covered by the elastic members 410 is peeled off. As a result, the upper surface of the lead portion 110 other than the area where the metal plating layer 112 is provided, the side wall surface of the lead portion 110, the lower surface of the inner lead portion 111, the upper surface of the die pad portion 120, and the side wall surface of the die pad portion 120 are exposed. On the other hand, the upper surface of the lead portion 110 covered by the elastic member 410, specifically the area where the metal plating layer 112 is formed, and the coating layer 350 on the connecting bar 130 remain.

[0116] <Surface roughening process> Next, a support layer 360 is provided on the lower side of the metal substrate 310 to support the metal substrate (see Figure 6G). The support layer 360 may be, for example, a resist layer. After providing the support layer 360, a rough surface is formed by roughening the portion of the metal substrate 310 that is not covered by the coating layer 350 (see Figure 6G). Specifically, a rough surface is formed on the upper surface of the lead portion 110 outside the area where the metal plating layer 112 is formed (the side farther from the die pad portion 120), the side wall surface of the lead portion 110, the lower surface of the inner lead portion 111, the upper surface of the die pad portion 120, and the side wall surface of the die pad portion 120. To form a rough surface, for example, a micro-etching solution is supplied to the metal substrate 310. This makes it possible to form a rough surface on the entire metal substrate 310, except for the portion covered by the coating layer 350. A micro-etching solution is a surface treatment agent that slightly dissolves the metal surface and can form a rough surface with fine irregularities. Examples of micro-etching solutions that can be used in this embodiment include those containing sulfuric acid or hydrochloric acid as the main component, and those containing hydrogen peroxide and sulfuric acid as the main components.

[0117] Furthermore, in the process of forming a rough surface, among the CIELab color space in the rough surface, * The value is in the range of 12 to 19, b * The surface is roughened so that the value is in the range of 12 to 17. In addition, during the process of forming the rough surface, the arithmetic mean curvature Spc of the peaks of the rough surface is 700 mm. -1 The surface is roughened to the extent described above. Furthermore, it is preferable that the arithmetic mean height Sa of the roughened surface be 0.12 μm or more, and more preferably that it be roughened to a range of 0.12 μm to 0.34 μm. By forming the roughened surface to such a predetermined range, a lead frame 100 can be obtained that can be used to manufacture a semiconductor device capable of suppressing the penetration of moisture from the air to the electrodes of the semiconductor element.

[0118] Subsequently, the support layer 360 and the coating layer 350 are sequentially peeled off, and a metal plating layer 112 is provided on the inner end (die pad 120 side) of the upper surface 111A of the inner lead portion, thereby obtaining the lead frame 100 shown in Figures 1 and 2 (see Figure 6H). The metal plating layer 112 can be formed, for example, by forming a plating resist layer having a predetermined pattern by photolithography, and then forming the metal plating layer 112 in the areas not covered by the plating resist layer by electroplating. The lead frame 100 manufactured by the above manufacturing method may also be subjected to alkali treatment. Specifically, the lead frame 100 is immersed in an alkaline aqueous solution. By performing alkali treatment, the acid contained in the surface treatment agent used in the rough surface formation process is neutralized, and corrosion of the lead frame 100 can be suppressed. The alkali used for alkali treatment is not particularly limited, and examples include sodium hydroxide and potassium hydroxide, and one of these may be used alone, or two or more may be used in mixture.

[0119] [Manufacturing method for semiconductor devices] The manufacturing method of the semiconductor device 200 shown in Figures 3 and 4 will be explained as an example. Figures 7A to 7D are process diagrams illustrating the manufacturing method of the semiconductor device according to this embodiment.

[0120] First, a lead frame 100 manufactured by the manufacturing method shown in Figures 6A to 6H is prepared (see Figure 7A). Next, a semiconductor element 210 is mounted on the die pad portion 120 of the lead frame 100. In this case, the semiconductor element 210 is placed and fixed on the die pad portion 120 using an adhesive 240, such as die attach paste (see Figure 7B). The adhesive 240 may be an epoxy resin-based adhesive containing components such as silver paste and epoxy resin. At this time, the semiconductor element 210 is positioned on the rough surface of the upper surface of the die pad portion 120 via the adhesive 240.

[0121] Next, each electrode 210A of the semiconductor element 210 and the metal plating layer 112 formed on each lead portion 110 are electrically connected to each other by the connecting member 220 (see Figure 7C).

[0122] Next, a sealing portion 230 is formed on the lead frame 100 by injection molding or transfer molding of a thermosetting resin or thermoplastic resin (see Figure 7D). This allows the lead portion 110, die pad portion 120, semiconductor element 210, and connecting member 220 to be resin-sealed.

[0123] Subsequently, the lead frame 100 is diced for each package region 100A. At this time, since the upper surface of the connecting bar 130 to be diced is an unroughened surface, the generation of foreign matter during dicing can be suppressed. In this way, each semiconductor device 200 is separated into individual pieces, and the semiconductor devices 200 shown in Figures 3 and 4 are obtained.

[0124] Furthermore, if the semiconductor device 200 is used for a long period of time, moisture from the air may penetrate the semiconductor device 200 from the side or bottom. For example, moisture from the air may penetrate through the interface between the sealing portion 230 and the lead portion 110 or die pad portion 120.

[0125] In this embodiment, to address this problem, a rough surface is formed on the upper surface of the lead portion 110 where the metal plating layer 112 is not provided, the side wall surface of the lead portion 110, the upper surface of the die pad portion 120, and the side wall surface of the die pad portion 120. * The value is in the range of 12 to 19, b * The value should be in the range of 12-17, or the arithmetic mean curvature Spc of the peak of the rough surface should be 700 mm. -1As described above, the roughened surface is roughened to have an arithmetic mean height Sa of 0.12 μm or more. This makes the distance of the intrusion path from the interface between the sealing portion 230 and the lead portion 110 or die pad portion 120 to the semiconductor element 210 side relatively longer. Therefore, it is possible to suppress the intrusion of moisture up to the electrode 210A of the semiconductor element 210. Furthermore, by having a roughened surface within the above predetermined range, the adhesion strength between the die pad portion 120 or lead portion 110 and the sealing portion 230 can be increased, and the separation of the die pad portion 120 or lead portion 110 and the sealing portion 230 from each other can be suppressed.

[0126] Furthermore, the lead portion 110 in this embodiment includes an inner lead portion 111 that is thinned from the lower surface side of the lead portion 110. The lower surface of the inner lead portion 111 is rough, which increases the distance of the moisture intrusion path at the interface between the sealing portion 230 and the lead portion 110 on the lower side of the semiconductor device 200. This prevents moisture from penetrating from the interface between the sealing portion 230 and the lead portion 110 to the electrode 210A of the semiconductor element 210. Moreover, having a rough surface within the predetermined range on the lower surface of the inner lead portion 111 increases the adhesion strength between the lead portion 110 and the sealing portion 230, and prevents the lead portion 110 and the sealing portion 230 from peeling off from each other.

[0127] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit it. Accordingly, each element disclosed in the above embodiments is intended to include all design modifications and equivalents that fall within the technical scope of the present invention.

[0128] [Examples] The present disclosure will be described in more detail below with reference to examples and comparative examples, but the present disclosure is not limited in any way to the examples and comparative examples described below.

[0129] [Example 1] The configuration is as shown in Figures 1 and 2. A lead frame 100 was prepared. In the lead frame 100, the upper surface and side wall surface of the lead portion 110, and the upper surface and side wall surface of the die pad portion 120 are a in the CIELab color space. * The value is 17.53, b * The value is 14.80 and the arithmetic mean curvature Spc of the peak is 2431.46 mm -1 Furthermore, it was composed of a rough surface with an arithmetic mean height Sa of 0.14 μm. * Value and b * The values ​​were measured using a spectrophotometer eXact (manufactured by X-rite), while the arithmetic mean curvature Spc and arithmetic mean height Sa of the mountain peak were measured using a laser microscope VK-X260 (manufactured by Keyence, measurement unit) and a laser microscope VK-X250 (manufactured by Keyence, controller unit).

[0130] [Example 2] The upper surface and side wall surface of the lead portion 110, and the upper surface and side wall surface of the die pad portion 120, are a color in the CIELab color space. * The value is 16.03, b * The value is 13.84 and the arithmetic mean curvature Spc of the peak is 2952.08 mm -1 A lead frame 100 was prepared having the same configuration as in Example 1, except that it was composed of a rough surface with an arithmetic mean height Sa of 0.17 μm.

[0131] [Example 3] The upper surface and side wall surface of the lead portion 110, and the upper surface and side wall surface of the die pad portion 120, are a color in the CIELab color space. * The value is 15.39, b * The value is 13.16 and the arithmetic mean curvature Spc of the peak is 3523.76 mm -1 A lead frame 100 was prepared having the same configuration as in Example 1, except that it was composed of a rough surface with an arithmetic mean height Sa of 0.22 μm.

[0132] [Example 4] The upper surface and side wall surface of the lead portion 110, and the upper surface and side wall surface of the die pad portion 120, are a color in the CIELab color space.* The value is 14.65, b * The value is 12.86 and the arithmetic mean curvature Spc of the mountain peak is 3378.00 mm -1 A lead frame 100 was prepared having the same configuration as in Example 1, except that it was composed of a rough surface with an arithmetic mean height Sa of 0.21 μm.

[0133] [Comparative Example 1] The upper surface and side wall surface of the lead portion 110, and the upper surface and side wall surface of the die pad portion 120, are a color in the CIELab color space. * The value is 18.59, b * The value is 17.29 and the arithmetic mean curvature Spc of the peak is 629.05 mm -1 A lead frame was prepared having the same configuration as in Example 1, except that it was composed of a rough surface with an arithmetic mean height Sa of 0.11 μm.

[0134] [Comparative Example 2] The upper surface and side wall surface of the lead portion 110, and the upper surface and side wall surface of the die pad portion 120, are a color in the CIELab color space. * The value is 10.06, b * The value is 7.18 and the arithmetic mean curvature Spc of the peak is 986.96 mm -1 A lead frame was prepared having the same configuration as in Example 1, except that it was composed of an unroughened surface with an arithmetic mean height Sa of 0.09 μm.

[0135] [Example Test] The surface roughness of each lead frame in Examples 1-4 and Comparative Examples 1-2 was observed using SEM and a laser microscope, and the shear strength of each lead frame in Examples 1-4 and Comparative Examples 1-2 was measured. The results are shown in Table 1. The shear strength was measured using a mold resin adhesion strength test (pudding cup test), in which mold resin was molded onto the lead frame and a shear direction was applied. EME-631 (manufactured by Sumitomo Bakelite Co., Ltd.) was used as the mold resin, and the mold resin was molded for a molding time of 120 seconds, a molding temperature of 175±5℃, and a molding pressure of 10MPa, after which it was cured at 175℃ for 6 hours. The size of the molded mold resin was 4 mm in height, 4 mm in base diameter, and 3 mm in top diameter, and the base side was molded onto the lead frame. Subsequently, the lead frame was fixed to a DAGE4000 joint strength testing machine (manufactured by Nordson), and the shear strength was measured by applying a shear load of 1 kg at a speed of 0.1 mm / second from the lateral direction of the molded resin on the lead frame.

[0136] [Table 1]

[0137] As shown in Table 1, among the CIELab color space of the rough surface of the lead frame 100, a * The value is in the range of 12 to 19, b * If the value is in the range of 12 to 17, then a * Value and b * It was confirmed that the shear strength increased compared to when the value was outside the above range. Therefore, a * Value and b * If the value is within the above range, it is presumed that the adhesion strength between the lead frame 100 and the mold resin will increase in semiconductor devices manufactured using the lead frame 100, thereby suppressing the penetration of moisture from the air to the electrodes 210A of the semiconductor element 210.

[0138] Furthermore, the arithmetic mean curvature Spc of the peaks of the rough surface of lead frame 100 is 700 mm -1 If the above is true, the arithmetic mean curvature Spc of the mountain peak is 700 mm. -1It was confirmed that the shear strength increased when it was less than. Furthermore, the arithmetic mean height Sa of the rough surface of each lead frame 100 in Examples 1 to 4 was 0.12 μm or more. From this result, the arithmetic mean curvature Spc of the peak points of the rough surface was 700 mm -1 or more, and when the arithmetic mean height Sa of the rough surface is 0.12 μm or more, in the semiconductor device manufactured using the lead frame 100, it is presumed that the adhesion strength with the mold resin increases, and moisture in the air can be suppressed from entering up to the electrode 210A of the semiconductor element 210. Note that the arithmetic mean curvature Spc of the peak points of the non-roughened surface of Comparative Example 2 that was not roughened is 700 mm -1 or more. This is because when the metal substrate was rolled to manufacture the lead frame of Comparative Example 2, there were sharp peaks of rolling marks, so the value of the arithmetic mean curvature Spc of the peak points became 700 mm -1 or more. Also, the arithmetic mean curvature Spc of the peak points of the rough surface of the lead frame of Comparative Example 1 is smaller than the arithmetic mean curvature Spc of the peak points of the non-roughened surface of Comparative Example 2. This is presumably because when forming the rough surface, the rough surface was formed by roughening to such an extent that the peak points of the sharp peaks of the rolling marks were shaved off, so the value of the arithmetic mean curvature Spc became smaller. The rough surfaces of the lead frames 100 in Examples 1 to 4 are rougher than the rough surface of the lead frame of Comparative Example 1. For this reason, it is presumed that the etching went deeper and the value of the arithmetic mean curvature Spc of the peak points became larger.

[0139] (Second Embodiment) Next, the second embodiment will be described with reference to FIGS. 8 to 17. In the following figures, the same parts are denoted by the same reference numerals, and some detailed descriptions may be omitted.

[0140] (Configuration of Lead Frame) First, the outline of the lead frame according to this embodiment will be described with reference to FIGS. 8 to 10. FIGS. 8 to 10 are diagrams showing the lead frame according to this embodiment.

[0141] The lead frame 10 shown in Figures 8 and 9 is used when manufacturing a semiconductor device 20 (Figures 11 and 12). Such a lead frame 10 has multiple package regions 10a. The multiple package regions 10a are arranged in multiple rows and multiple layers (matrix-like). Note that in Figure 8, only a portion of the lead frame 10 centered on one package region 10a is shown.

[0142] In this specification, "inside" and "inside" refer to the side of each package region 10a facing towards the center. "Outside" and "outside" refer to the side of each package region 10a away from the center (the connecting bar 13 side). Furthermore, "front surface" refers to the side on which the semiconductor element 21 is mounted. "Back surface" refers to the side opposite the "front surface" that is connected to an external mounting substrate (not shown). "Side surface" refers to the surface located between the "front surface" and the "back surface" that constitutes the thickness of the lead frame 10 (metal substrate).

[0143] Furthermore, in this specification, half-etching refers to etching the material to be etched in its thickness direction up to a certain point. The thickness of the material to be etched after half-etching is, for example, 30% to 70%, preferably 40% to 60%, of the thickness of the material to be etched before half-etching.

[0144] As shown in Figures 8 and 9, each package region 10a of the lead frame 10 comprises a die pad 11 and lead portions 12 located around the die pad 11. Of these, a portion of the lead portion 12 is thinned from the back side. The thinned portion of the back surface of the lead portion 12 is rough. The portion of the back surface of the lead portion 12 that is not thinned is smooth.

[0145] The package region 10a is the region corresponding to the semiconductor device 20 (described later). The package region 10a is the region surrounded by rectangular dashed lines in Figure 8. In this embodiment, the lead frame 10 includes multiple package regions 10a. However, it is not limited to this, and a single lead frame 10 may have only one package region 10a.

[0146] Each package region 10a is connected to the others via a connecting bar (support member) 13. This connecting bar 13 supports the die pad 11 and the lead portion 12. The connecting bar 13 extends along either the X direction or the Y direction. Here, the X direction and the Y direction are two directions parallel to each side of the package region 10a within the plane of the lead frame 10. The X direction and the Y direction are orthogonal to each other. The Z direction is perpendicular to both the X direction and the Y direction.

[0147] Each connecting bar 13 is positioned around the package area 10a but outside of it. Each connecting bar 13 has an elongated rod shape in plan view. The width of each connecting bar 13 (the distance in the direction perpendicular to the longitudinal direction of the connecting bar 13) may be between 95 μm and 250 μm. Each connecting bar 13 has multiple lead portions 12 connected to it at intervals along its longitudinal direction. The die pad 11 is supported by the connecting bar 13 via suspension leads 14. The connecting bar 13 is not thinned, but may be thinned from the back side, for example by half-etching. The thickness of the connecting bar 13 may be between 80 μm and 200 μm, depending on the configuration of the semiconductor device 20.

[0148] As shown in Figure 9, the die pad 11 has a die pad surface 11a located on the front side and a die pad back surface 11b located on the back side. A semiconductor element 21 is mounted on the die pad surface 11a, as will be described later. The die pad back surface 11b is exposed outward from the semiconductor device 20 (described later). In addition, a first die pad side surface 11c and a second die pad side surface 11d are formed on the side of the die pad 11 facing the lead portion 12. The first die pad side surface 11c is located on the die pad surface 11a side. The second die pad side surface 11d is located on the die pad back surface 11b side. In this case, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are rough surfaces. On the other hand, the die pad surface 11a has a smooth surface (die pad smooth surface region 11e) and a rough surface (die pad rough surface region 11f), as will be described later. The die pad back surface 11b is a smooth surface.

[0149] In this embodiment, "rough surface" refers to a surface with an S-ratio of 1.30 or higher. "Smooth surface" refers to a surface with an S-ratio of less than 1.30. A rough surface is rougher than a smooth surface. Furthermore, it is preferable that the S-ratio of a "rough surface" be between 1.30 and 2.30. It is preferable that the S-ratio of a "smooth surface" be between 1.00 and 1.20. Here, "S-ratio" is calculated by dividing the surface area obtained by dividing the surface to be measured into multiple pixels using an optical interferometer by the observation area. Specifically, the surface to be measured is divided into multiple pixels using a VertScan manufactured by Hitachi High-Tech Science Corporation, and the obtained surface area is divided by the observation area to calculate the S-ratio.

[0150] The roughened surface may be formed by roughening the outer surface of the metal substrate 31, as described later, with a micro-etching solution mainly composed of hydrogen peroxide and sulfuric acid. The smooth surface may be the unprocessed surface of the metal substrate 31, which has not undergone such roughening treatment. In Figure 9, the roughened portion is shown by a thick dashed line (the same applies to the other cross-sectional views).

[0151] The die pad surface 11a of the die pad 11 is an area (internal terminal) that is electrically connected to the semiconductor element 21 via bumps 26, as will be described later. The die pad surface 11a may be an area that has not been thinned by half etching or the like. The die pad surface 11a has a smooth die pad surface area 11e, which is a smooth surface area, and a rough die pad surface area 11f, which is a rough surface area.

[0152] Multiple die pad smooth surface regions 11e may be formed on the die pad surface 11a. Each die pad smooth surface region 11e is connected to a corresponding bump 26 (see Figure 12). The number of die pad smooth surface regions 11e on the die pad 11 may be the same as the number of bumps 26 connected to the die pad 11. Alternatively, multiple bumps 26 may be arranged on a single die pad smooth surface region 11e. In this case, the number of die pad smooth surface regions 11e on the die pad 11 may be less than the number of bumps 26 connected to the die pad 11.

[0153] The die pad roughening region 11f is rougher (has a larger S-ratio) than the die pad smoothing region 11e. As shown in Figure 10(a), the die pad roughening region 11f is formed to surround the entire circumference of each die pad smoothing region 11e in a plan view. That is, the die pad smoothing region 11e does not directly contact the periphery 11g of the die pad 11. Also, the die pad roughening region 11f is formed along the entire periphery 11g of the die pad 11 in a plan view. Here, the periphery 11g of the die pad 11 refers to the region surrounded by multiple (four) sides of the die pad 11, as shown in Figure 8. Furthermore, all areas of the die pad surface 11a other than the die pad smoothing region 11e may be die pad roughening regions 11f. That is, the die pad surface 11a may consist only of multiple die pad smoothing regions 11e and the remaining die pad roughening regions 11f.

[0154] As shown in Figure 10(a), the die pad smooth surface region 11e may be circular in plan view. Preferably, the die pad smooth surface region 11e is larger than the bump 26 (dummy line) in plan view. The width (diameter) D1 of the die pad smooth surface region 11e may be 0.030 mm or more, or 0.035 mm or more. The width (diameter) D1 may be 0.070 mm or less, or 0.065 mm or less. When the bump 26 is placed at the center of the die pad smooth surface region 11e, the shortest distance d1 between the periphery of the bump 26 and the periphery of the die pad smooth surface region 11e may be 0.005 mm or more, or 0.010 mm or more. The shortest distance d1 may be 0.020 mm or less, or 0.015 mm or less. The shortest distance L1 between the smooth surface region 11e of the die pad and the periphery 11g of the die pad 11 may be 0.025 mm or more, or 0.030 mm or more. The shortest distance L1 may be 1.0 mm or less, or 0.50 mm or less. Because the smooth surface region 11e of the die pad is circular in plan view, it is easy to position the circular bump 26 relative to the smooth surface region 11e of the die pad. In Figures 10(a) and 10(b), the smooth surface is shown in white, and the rough surface is shown in shaded areas (the same applies to Figures 17(a)-17(d)).

[0155] Furthermore, in Figure 10(a), if there are multiple die pad smooth surface regions 11e on the die pad surface 11a, the shortest distance M1 between adjacent die pad smooth surface regions 11e may be 0.030 mm or more, or 0.040 mm or more. The shortest distance M1 may be 1.0 mm or less, or 0.50 mm or less. The pitch P1 between the centers of adjacent die pad smooth surface regions 11e may be 0.045 mm or more, or 0.057 mm or more. The pitch P1 may be 1.2 mm or less, or 0.60 mm or less. Note that the above pitch P1 corresponds to the pitch between the centers of adjacent bumps 26.

[0156] Referring to Figure 9, external terminals may be formed on the back surface 11b of the die pad 11. These external terminals may be electrically connected to a mounting substrate (not shown). The back surface 11b of the die pad is a smooth surface similar to the metal substrate (metal substrate 31 described later) before processing, without being thinned by, for example, half etching. The back surface 11b of the die pad is exposed to the outside from the semiconductor device 20 (described later) after the semiconductor device 20 is manufactured.

[0157] Each lead portion 12 is connected to the semiconductor element 21 via a bump 26, as will be described later, and is positioned with a space between it and the die pad 11. The multiple lead portions 12 are spaced apart from each other along the longitudinal direction of the connecting bar 13. Each lead portion 12 extends from the connecting bar 13.

[0158] The lead portion 12 is arranged along the perimeter of the die pad 11. A portion of the lead portion 12 is thinned on its back side. In this case, the back side of the inner lead 51, which will be described later, is thinned. External terminals 17 are formed on the portion of the back side of the lead portion 12 that is not thinned. The external terminals 17 are electrically connected to an external mounting board (not shown). The external terminals 17 are exposed to the outside of the semiconductor device 20 (described later) after the semiconductor device 20 is manufactured.

[0159] As shown in Figure 9, the lead portion 12 has an inner lead 51 and a terminal portion 53. The inner lead 51 is located on the inside (die pad 11 side). The terminal portion 53 is located on the outside (connecting bar 13 side). The inner lead 51 extends from the terminal portion 53 towards the die pad 11. An internal terminal is formed on the surface side of the inner lead 51. This internal terminal is a region (lead smooth surface region 12e) that is electrically connected to the semiconductor element 21 via the bump 26, as will be described later.

[0160] The inner lead 51 is thinned from the back side, for example by half-etching. The inner lead 51 has an inner lead surface 51a and an inner lead back surface 51b. The inner lead surface 51a is located on the front side. In addition, the inner lead tip surface 51c is formed on the side of the inner lead 51 that faces the die pad 11. The inner lead back surface 51b is located on the back side.

[0161] The terminal portion 53 is located on the connecting bar 13 side. The base end of the terminal portion 53 is connected to the connecting bar 13. The terminal portion 53 has a terminal portion surface 53a. The external terminal 17 described above is formed on the back surface of the terminal portion 53. The terminal portion 53 has the same thickness as the die pad 11 without being half-etched. In addition, the back surface of the portion of the lead portion 12 that is located on the connecting bar 13 side of the terminal portion 53 may be thinned to form a connection portion with the connecting bar 13.

[0162] In this embodiment, the thinned portion of the back surface of the lead portion 12 is rough. Specifically, the inner lead 51 of the lead portion 12 is thinned from the back side. The entire surface of the inner lead back surface 51b, located on the back side of the inner lead 51, is rough. On the other hand, the portion of the back surface of the lead portion 12 that is not thinned is smooth. Specifically, the terminal portion 53 of the lead portion 12 is not thinned from the back side. The entire surface of the external terminal 17, located on the back side of the terminal portion 53, is smooth.

[0163] Furthermore, the entire tip surface 51c of the inner lead of the lead portion 12 is roughened. Although not shown in the figure, both sides along the longitudinal direction of the lead portion 12 may also be roughened. On the other hand, the inner lead 51 of the lead portion 12 is not thinned from the surface side. Also, the terminal portion 53 of the lead portion 12 is not thinned from the surface side.

[0164] The lead surface 12a is formed by the inner lead surface 51a of the inner lead 51 and the terminal surface 53a of the terminal portion 53. The lead surface 12a is a region that has not been thinned from the surface side by half etching or the like. The lead surface 12a has a smooth lead surface region 12e, which is a smooth surface region, and a rough lead surface region 12f, which is a rough surface region.

[0165] Each lead portion 12 has one lead smooth surface region 12e formed on its lead surface 12a. Each lead portion 12 may have multiple lead smooth surface regions 12e formed on its lead surface 12a. Each lead smooth surface region 12e is connected to a corresponding bump 26 (see Figure 12). Multiple bumps 26 may be arranged on a single lead smooth surface region 12e. In this case, the number of lead smooth surface regions 12e on each lead portion 12 may be less than the number of bumps 26 connected to that lead portion 12.

[0166] A lead roughening region 12f exists around the lead smooth surface region 12e. The lead roughening region 12f is rougher (has a larger S-ratio) than the lead smooth surface region 12e. As shown in Figure 10(b), the lead roughening region 12f is formed to surround the entire circumference of each lead smooth surface region 12e in a plan view. That is, the lead smooth surface region 12e does not directly contact the periphery 12g of the lead portion 12. The lead roughening region 12f is also formed along the entire periphery 12g of the lead portion 12 in a plan view. Here, the periphery 12g of the lead portion 12 refers to the region surrounded by multiple (three) sides of the lead portion 12 and the connecting bar 13, as shown in Figure 8. Furthermore, all areas of the lead surface 12a other than the lead smooth surface region 12e may be the lead roughening region 12f. In other words, the lead surface 12a may consist only of a lead smooth surface region 12e and the other lead rough surface region 12f.

[0167] As shown in Figure 10(b), the lead smooth surface region 12e may be circular in plan view. The shape of the lead smooth surface region 12e may be the same as or different from the die pad smooth surface region 11e described above. Furthermore, it is preferable that the lead smooth surface region 12e is larger than the bump 26 (imaginary line) in plan view. The width (diameter) D2 of the lead smooth surface region 12e may be 0.030 mm or more, or 0.035 mm or more. The width (diameter) D2 may be 0.070 mm or less, or 0.065 mm or less. When the bump 26 is placed at the center of the lead smooth surface region 12e, the shortest distance d2 between the periphery of the bump 26 and the periphery of the lead smooth surface region 12e may be 0.005 mm or more, or 0.010 mm or more. The shortest distance d2 may be 0.020 mm or less, or 0.015 mm or less. The shortest distance L2 between the lead smooth surface region 12e and the periphery 12g of the lead portion 12 may be 0.025 mm or more, or 0.030 mm or more. The shortest distance L2 may be 1.0 mm or less, or 0.50 mm or less. Because the lead smooth surface region 12e is circular in plan view, it is easier to position the circular bump 26 relative to the die pad smooth surface region 11e.

[0168] The lead frame 10 described above is composed of metals such as copper, copper alloys, and 42 alloy (Fe alloy with 42% Ni). The thickness of the non-thinned portion of the lead frame 10 may be between 80 μm and 300 μm, depending on the configuration of the semiconductor device 20 being manufactured.

[0169] In this embodiment, the lead portion 12 is arranged along all four sides of the package area 10a, but this is not limited to this configuration. For example, it may be arranged along only two opposing sides of the package area 10a.

[0170] (Configuration of a semiconductor device) Next, the semiconductor device according to this embodiment will be described with reference to Figures 11 to 13. Figures 11 to 13 show the semiconductor device (flip-chip type) according to this embodiment.

[0171] As shown in Figures 11 and 12, the semiconductor device (semiconductor package) 20 comprises a die pad 11, a semiconductor element 21, a plurality of lead portions 12, a plurality of bumps 26, and a sealing resin 23.

[0172] The semiconductor element 21 is mounted on the die pad 11 and the lead portion 12. Multiple bumps 26 electrically connect the semiconductor element 21 to either the die pad 11 or the lead portion 12. In this case, the bumps 26 constitute the connection portion. The bumps 26 may also be pillars. The sealing resin 23 encapsulates the die pad 11, the lead portion 12, the semiconductor element 21, and the bumps 26.

[0173] The die pad 11 and lead portion 12 are manufactured from the lead frame 10 described above. In this case, the inner lead 51 of the lead portion 12 is thinned from the back side. The back surface 51b of the inner lead 51 is rough. The sealing resin 23 is in close contact with the back surface 51b of the inner lead. The terminal portion 53 of the lead portion 12 is not thinned from the back side. The external terminal 17 located on the back surface of the terminal portion 53 is smooth. The external terminal 17 is exposed outward from the sealing resin 23.

[0174] Bumps 26 are provided on the die pad 11 and the lead portion 12, respectively. The bumps 26 on the die pad 11 are located in the smooth surface region 11e of the die pad. The bumps 26 are spaced at the shortest distance d1 from the rough surface region 11f of the die pad. The bumps 26 on the lead portion 12 are located in the smooth surface region 12e of the lead. The bumps 26 are spaced at the shortest distance d2 from the rough surface region 12f of the lead. The semiconductor element 21 and the die pad 11 and lead portion 12 are electrically connected to each other via the bumps 26.

[0175] The semiconductor element 21 can be any of the semiconductor elements that are commonly used in the past, and is not particularly limited, but for example, integrated circuits, large-scale integrated circuits, transistors, thyristors, diodes, etc. can be used. This semiconductor element 21 has a plurality of electrodes 21a to which each bump 26 is attached.

[0176] As the encapsulating resin 23, a thermosetting resin such as silicone resin or epoxy resin, or a thermoplastic resin such as PPS resin can be used. The overall thickness of the encapsulating resin 23 may be approximately 300 μm to 1500 μm. In addition, one side of the encapsulating resin 23 (one side of the semiconductor device 20) may be, for example, 0.2 mm to 20 mm, or 0.2 mm to 16 mm. Note that in Figure 11, the portion of the encapsulating resin 23 located on the surface side of the lead portion 12 and the semiconductor element 21 is omitted from the display.

[0177] The bumps (connecting parts) 26 are made of a highly conductive metal material such as copper, and may have a solid, approximately cylindrical or approximately spherical shape. The upper end of each bump 26 is connected to the electrode 21a of the semiconductor element 21, and the lower end is connected to the die pad smooth surface region 11e or the lead smooth surface region 12e, respectively. The width (diameter) of the bumps 26 may be 0.01 mm or more and 0.070 mm or less. The die pad 11 does not necessarily have to be provided with bumps 26. In this case, the die pad 11 and the semiconductor element 21 may be fixed to each other with an adhesive such as die bonding paste.

[0178] Figures 13(a) and (b) are enlarged cross-sectional views showing the periphery of the bump 26. As shown in Figure 13(a), the bump 26 may consist of a single layer. In this case, the bump 26 may include a metal layer, such as copper. The bump 26 may be made of the same metal as the main metal (e.g., copper) contained in the die pad 11 and lead portion 12. The height of the bump 26 may be 30 μm or more and 110 μm or less.

[0179] Alternatively, as shown in Figure 13(b), the bump 26 may include multiple layers. For example, the bump 26 includes a first layer 26a located on the die pad 11 side or the lead portion 12 side, and a second layer 26b located on the semiconductor element 21 side. The first layer 26a may contain a metal such as tin. The height of the first layer 26a may be 1 μm or more and 10 μm or less. The second layer 26b may contain a metal such as copper. The height of the second layer 26b may be 30 μm or more and 100 μm or less.

[0180] Furthermore, the configuration of the die pad 11 and lead portion 12 is the same as that shown in Figures 8 to 10 above, except for areas not included in the semiconductor device 20, so a detailed explanation is omitted here.

[0181] (Manufacturing method for lead frames) Next, the manufacturing method of the lead frame 10 shown in Figures 8 and 9 will be explained using Figures 14(a)-(i). Figure 14(a)-(i) is a cross-sectional view (corresponding to Figure 9) showing the manufacturing method of the lead frame 10.

[0182] First, a flat metal substrate 31 is prepared as shown in Figure 14(a). This metal substrate 31 can be made of a metal such as copper, a copper alloy, or a 42 alloy (a 42% Ni Fe alloy). It is preferable to use a metal substrate 31 that has been degreased and cleaned on both sides.

[0183] Next, photosensitive resists 32a and 33a are applied to the entire front and back surfaces of the metal substrate 31, respectively, and then dried (Figure 14(b)). Conventional known photosensitive resists 32a and 33a can be used.

[0184] Next, the metal substrate 31 is exposed to light through a photomask and developed to form etching resist layers 32 and 33 having desired openings 32b and 33b (Figure 14(c)).

[0185] Next, the etching resist layers 32 and 33 are used as corrosion-resistant films, and the metal substrate 31 is etched with an etching solution (Figure 14(d)). The etching solution can be appropriately selected depending on the material of the metal substrate 31 used. For example, when copper is used as the metal substrate 31, a ferric chloride aqueous solution is usually used as the etching solution, and spray etching can be performed from both sides of the metal substrate 31. This forms the outer shapes of the die pad 11, lead portion 12, and connecting bar 13. At this time, the lead portion 12 is partially thinned from the back side by half-etching. Specifically, the back side of the inner lead 51 of the lead portion 12 is thinned.

[0186] Next, the etching resist layers 32 and 33 are peeled off and removed (Figure 14(e)). In this way, a metal substrate 31 having a die pad 11 and lead portions 12 located around the die pad 11 is obtained.

[0187] Next, a plating layer 36 is formed on a portion of the metal substrate 31 (Figure 14(f)). First, an elastic member 46, such as a rubber packing, having openings in a predetermined pattern is placed on the surface of the metal substrate 31. The openings of the elastic member 46 have shapes corresponding to the die pad smooth surface region 11e and the lead smooth surface region 12e. Next, the surface of the metal substrate 31 is pressed down by a jig 47 via the elastic member 46. The jig 47 has openings in the same pattern as the elastic member 46. Then, a plating layer 36 is formed on the portion of the surface of the metal substrate 31 that is not covered by the elastic member 46 and the jig 47. As a result, a plating layer 36 is formed on the portion of the die pad 11 corresponding to the die pad smooth surface region 11e and the portion of the lead portion 12 corresponding to the lead smooth surface region 12e. The thickness of the plating layer 36 may be greater than 0 μm and less than or equal to 2 μm. Silver may be used as the metal constituting the plating layer 36. When the plating layer 36 consists of silver plating, a silver plating solution mainly composed of silver cyanide and potassium cyanide can be used as the electrolytic plating solution.

[0188] Next, the elastic member 46 and the jig 47 are removed. A support layer 37 is also provided on the back side of the metal substrate 31 to support the metal substrate 31 (Figure 14(g)). The support layer 37 may be, for example, a resist layer.

[0189] Next, as shown in Figure 14(h), a rough surface is formed on the portion of the metal substrate 31 that is not covered by the plating layer 36 and the support layer 37 by roughening that portion. Specifically, a die pad rough surface region 11f and a lead rough surface region 12f are formed on the metal substrate 31. Furthermore, the first die pad side surface 11c, the second die pad side surface 11d, the inner lead tip surface 51c, and the inner lead back surface 51b are made rough. During this time, a micro-etching solution is supplied to the metal substrate 31 to form a rough surface on the entire metal substrate 31, except for the portion covered by the plating layer 36 and the support layer 37. Here, a micro-etching solution is a surface treatment agent that slightly dissolves the metal surface and forms a rough surface with fine irregularities. For example, when roughening a metal substrate 31 made of copper or a copper alloy, a micro-etching solution mainly composed of hydrogen peroxide and sulfuric acid may be used.

[0190] Next, as shown in Figure 14(i), the support layer 37 and the plating layer 36 are sequentially peeled off to obtain the lead frame 10 shown in Figures 8 and 9.

[0191] (Method of manufacturing semiconductor devices) Next, the manufacturing method of the semiconductor device 20 shown in Figures 11 and 12 will be explained using Figures 15(a)-(d). Figures 15(a)-(d) are cross-sectional views (corresponding to Figure 12) showing the manufacturing method of the semiconductor device 20.

[0192] First, the lead frame 10 is fabricated using the method shown in Figure 14(a)-(i), for example (Figure 15(a)).

[0193] Next, the semiconductor element 21 is mounted on the die pad 11 and lead portion 12 of the lead frame 10. In this case, bumps 26 are formed in advance on the electrodes 21a of the semiconductor element 21. Then, these bumps 26 are connected and fixed to the die pad 11 and lead portion 12, respectively (Figure 15(b)). At this time, each electrode 21a of the semiconductor element 21 and the die pad 11 and lead portion 12 are electrically connected to each other via the bumps 26. The bumps 26 on the die pad 11 are connected to the smooth surface region 11e of the die pad. At this time, the bumps 26 are spaced apart from the rough surface region 11f of the die pad. Similarly, the bumps 26 on the lead portion 12 are connected to the smooth surface region 12e of the lead. At this time, the bumps 26 are spaced apart from the rough surface region 12f of the lead.

[0194] Next, a encapsulating resin 23 is formed on the lead frame 10 by injection molding or transfer molding of a thermosetting resin or thermoplastic resin (Figure 15(c)). This encapsulates the die pad 11, lead portion 12, semiconductor element 21, and bump 26 with resin.

[0195] Subsequently, the lead frame 10 and sealing resin 23 are cut for each package region 10a. This separates the lead frame 10 for each semiconductor device 20, resulting in the semiconductor devices 20 shown in Figures 11 and 12 (Figure 15(d)).

[0196] Incidentally, during long-term use of the semiconductor device 20 manufactured in this manner, it is conceivable that moisture from the air may penetrate the semiconductor device 20 from the side or back side through the interface between the sealing resin 23 and the die pad 11 or lead portion 12.

[0197] In contrast, according to this embodiment, a die pad rough surface region 11f exists so as to surround the entire circumference of the die pad smooth surface region 11e. Similarly, a lead rough surface region 12f exists so as to surround the entire circumference of the lead smooth surface region 12e. As a result, outside the bump 26, the distance of the moisture intrusion path at the interface between the die pad surface 11a or lead surface 12a and the sealing resin 23 is increased. This prevents moisture from entering the semiconductor element 21 side from the interface between the die pad surface 11a or lead surface 12a and the sealing resin 23 (arrow F in Figure 16). A (See reference). As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

[0198] Furthermore, according to this embodiment, the die pad smooth surface region 11e adjacent to the outside of the bump 26 on the die pad surface 11a is a smooth surface. Also, the lead smooth surface region 12e adjacent to the outside of the bump 26 on the lead surface 12a is a smooth surface.

[0199] As a result, when the bump 26 is made of a single metal layer such as copper (see Figure 13(a)), the following effects can be obtained. That is, when mounting the semiconductor element 21 on the die pad 11 and lead portion 12, the adhesion between the bump 26 and the die pad 11 and lead portion 12 can be improved. On the other hand, if the surfaces of the die pad 11 and lead portion 12 to which the bump 26 is connected are rough, the contact area between the bump 26 and the rough surface will be reduced due to the influence of the oxide film (e.g., copper oxide) formed on the rough surface. In this case, the bonding strength between the bump 26 and the die pad 11 and lead portion 12 may be weakened.

[0200] Furthermore, if the bump 26 contains a metal such as tin (see Figure 13(b)), the following effects can be obtained. That is, when mounting the semiconductor element 21 on the die pad 11 and lead portion 12, it is possible to suppress the tin or other metal contained in the bump 26 from flowing out along the rough surface. On the other hand, if the part adjacent to the outside of the bump 26 is rough, there is a risk that the tin or other metal contained in the bump 26 may flow out along the rough surface due to surface tension.

[0201] Further, according to the present embodiment, the die pad rough surface region 11f is formed along the entire periphery 11g of the die pad 11 in a plan view. Also, the lead rough surface region 12f is formed along the entire periphery 12g of the lead portion 12 in a plan view. Thereby, it is possible to more effectively suppress moisture from entering the semiconductor element 21 side from the interface between the die pad surface 11a or the lead surface 12a and the sealing resin 23.

[0202] Also according to the present embodiment, the inner lead back surface 51b and the inner lead tip surface 51c of the lead portion 12 are rough surfaces. Also, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are rough surfaces respectively. For this reason, the distance of the moisture intrusion path at the interface between the sealing resin 23 and the die pad 11 or the lead portion 12 is long. Thereby, it is possible to suppress moisture from entering the semiconductor element 21 side from the interface between the sealing resin 23 and the die pad 11 or the lead portion 12 (arrow F in FIG. 16 B reference). As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

[0203] In particular, in the flip chip type semiconductor device 20, the electrode 21a of the semiconductor element 21 faces the back surface side. For this reason, in the flip chip type semiconductor device 20, the distance from the back surface of the semiconductor device 20 to the electrode 21a of the semiconductor element 21 tends to be short. On the other hand, according to the present embodiment, the thinned portion of the back surface of the lead portion 12 is a rough surface. Thereby, it is possible to more effectively suppress moisture from entering the semiconductor element 21 side from the interface between the sealing resin 23 and the lead portion 12.

[0204] Further, according to the present embodiment, the inner lead back surface 51b and the inner lead tip surface 51c of the lead portion 12 are rough surfaces. Also, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are rough surfaces respectively. Thereby, the adhesion strength between the die pad 11 and the lead portion 12 and the sealing resin 23 is increased, and it is possible to suppress the die pad 11 and the lead portion 12 from peeling off from the sealing resin 23.

[0205] (Modification example) Next, a modification example of the die pad smooth surface region 11e and the lead smooth surface region 12e will be described with reference to FIGS. 17(a)-(d). FIGS. 17(a)-(d) are enlarged plan views showing the die pad smooth surface regions 11e and the lead smooth surface regions 12e (hereinafter also simply referred to as smooth surface regions 11e, 12e), and the die pad rough surface regions 11f and the lead rough surface regions 12f (hereinafter also simply referred to as rough surface regions 11f, 12f).

[0206] As shown in FIG. 17(a), the smooth surface regions 11e, 12e may be square or rectangular in plan view. The width (length of each side) D3 of the smooth surface regions 11e, 12e may be 0.030 mm or more, and may be 0.035 mm or more. The width D3 may be 0.070 mm or less, and may be 0.065 mm or less. Also, when the bump 26 is arranged at the center of the smooth surface regions 11e, 12e, the shortest distance d3 between the periphery of the bump 26 and the periphery of the smooth surface regions 11e, 12e may be 0.005 mm or more, and may be 0.010 mm or more. The shortest distance d3 may be 0.020 mm or less, and may be 0.015 mm or less. Also, the shortest distance L3 between the smooth surface regions 11e, 12e and the periphery 11g of the die pad 11 or the periphery 12g of the lead portion 12 may be 0.025 mm or more, and may be 0.030 mm or more. The shortest distance L3 may be 1.0 mm or less, and may be 0.50 mm or less. Since the smooth surface regions 11e, 12e are square or rectangular in plan view, the shortest distance (interval) d3 between the periphery of the bump 26 and the periphery of the smooth surface regions 11e, 12e can be ensured sufficiently.

[0207] As shown in Figure 17(b), the smooth surface regions 11e and 12e are square or rectangular in plan view, and multiple bumps 26 may be arranged in one smooth surface region 11e or 12e. The length D4a of the long side of the smooth surface regions 11e and 12e may be 0.045 mm or more, or 0.065 mm or more. The length D4a may be 0.12 mm or less, or 0.10 mm or less. The length D4b of the short side of the smooth surface regions 11e and 12e may be 0.030 mm or more, or 0.035 mm or more. The length D4b may be 0.070 mm or less, or 0.065 mm or less. Furthermore, when each bump 26 is positioned at the center of the short-side direction of the smooth surface regions 11e and 12e, the shortest distance d4 in the short-side direction between the periphery of the bump 26 and the periphery of the smooth surface regions 11e and 12e may be 0.005 mm or more, or 0.010 mm or more. The shortest distance d4 may be 0.020 mm or less, or 0.015 mm or less. Also, the shortest distance L4 between the smooth surface regions 11e and 12e and the periphery 11g of the die pad 11 or the periphery 12g of the lead portion 12 may be 0.025 mm or more, or 0.030 mm or more. The shortest distance L4 may be 1.0 mm or less, or 0.50 mm or less. Because the smooth surface regions 11e and 12e are square or rectangular in plan view, a sufficient shortest distance (spacing) d4 between the periphery of the bump 26 and the periphery of the smooth surface regions 11e and 12e can be secured. Furthermore, two or more adjacent bumps 26 can be placed in each smooth surface region 11e, 12e.

[0208] As shown in Figure 17(c), the smooth surface regions 11e and 12e are ellipses or ovals in plan view, and multiple bumps 26 may be arranged in one smooth surface region 11e or 12e. The longitudinal length D5a of the smooth surface regions 11e and 12e may be 0.045 mm or more, or 0.065 mm or more. The length D5a may be 0.12 mm or less, or 0.10 mm or less. The short-side length D5b of the smooth surface regions 11e and 12e may be 0.030 mm or more, or 0.035 mm or more. The length D5b may be 0.070 mm or less, or 0.065 mm or less. Furthermore, when each bump 26 is positioned at the center in the short direction of the smooth surface regions 11e and 12e, the shortest distance d5 between the periphery of the bump 26 and the periphery of the smooth surface regions 11e and 12e may be 0.005 mm or more, or 0.010 mm or more. The shortest distance d5 may be 0.020 mm or less, or 0.015 mm or less. Also, the shortest distance L5 between the smooth surface regions 11e and 12e and the periphery 11g of the die pad 11 or the periphery 12g of the lead portion 12 may be 0.025 mm or more, or 0.030 mm or more. The shortest distance L5 may be 1.0 mm or less, or 0.50 mm or less. Because the smooth surface regions 11e and 12e are elliptical or oblong in plan view, two or more bumps 26 adjacent to each other can be placed in each smooth surface region 11e and 12e.

[0209] As shown in Figure 17(d), the periphery of the smooth surface regions 11e and 12e may be a closed figure containing the curve Cv and the line segment Ls in a plan view. The smooth surface regions 11e and 12e may be a figure obtained by removing a part of a circle or ellipse, for example, a semicircle or a semiellipse. The line segment Ls constituting the periphery of the smooth surface regions 11e and 12e may be parallel to the periphery 11g of the die pad 11 or the periphery 12g of the lead portion 12. The length D6a of the smooth surface regions 11e and 12e in the direction perpendicular to the line segment Ls may be 0.030 mm or more, or 0.050 mm or more. The length D6a may be 0.12 mm or less, or 0.10 mm or less. The length D6b of the smooth surface regions 11e and 12e in the direction parallel to the line segment Ls may be 0.030 mm or more, or 0.035 mm or more. The length D6b may be 0.070 mm or less, or 0.065 mm or less. When each bump 26 is positioned at the center in a direction parallel to and perpendicular to the line segment Ls of the smooth surface regions 11e and 12e, the shortest distance d6 between the periphery of the bump 26 and the periphery of the smooth surface regions 11e and 12e may be 0.005 mm or more, or 0.010 mm or more. The shortest distance d6 may be 0.020 mm or less, or 0.015 mm or less. The shortest distance L6 between the smooth surface regions 11e and 12e and the periphery 11g of the die pad 11 or the periphery 12g of the lead portion 12 may be 0.025 mm or more, or 0.030 mm or more. The shortest distance L6 may be 1.0 mm or less, or 0.50 mm or less. Because the smooth surface regions 11e and 12e are closed figures that include the curve Cv and the line segment Ls in a plan view, a minimum distance L6 between the smooth surface regions 11e and 12e and the periphery 11g of the die pad 11 or the periphery 12g of the lead portion 12 can be ensured to a certain extent.

[0210] (Third embodiment) Next, a third embodiment will be described with reference to Figures 18 to 25. Figures 18 to 25 show the third embodiment. In Figures 18 to 25, the same reference numerals are used for parts that are the same as those shown in Figures 8 to 17, and detailed descriptions are omitted.

[0211] (Lead frame configuration) First, the outline of the lead frame according to this embodiment will be explained with reference to Figures 18 and 19. Figures 18 and 19 are diagrams showing the lead frame according to this embodiment.

[0212] In this specification, "outer periphery" refers to the portion of the lead frame 10 (metal substrate) that is exposed to the outside, and includes the "front surface," "side surface," and "back surface."

[0213] As shown in Figures 18 and 19, each package region 10a of the lead frame 10 comprises a die pad 11 and lead portions 12 located around the die pad 11. Of these, a portion of the lead portion 12 is thinned from the back side. The thinned portion of the back surface of the lead portion 12 is rough. The portion of the back surface of the lead portion 12 that is not thinned is smooth.

[0214] As shown in Figure 19, the die pad 11 has a die pad surface 11a located on the front side and a die pad back surface 11b located on the back side. In this case, the die pad surface 11a, the first die pad side surface 11c, and the second die pad side surface 11d of the die pad 11 are rough surfaces. On the other hand, the die pad back surface 11b of the die pad 11 is a smooth surface.

[0215] As shown in Figure 19, the lead portion 12 has an inner lead 51 and a terminal portion 53. The inner lead 51 is located on the inside (die pad 11 side). The terminal portion 53 is located on the outside (connecting bar 13 side). The inner lead 51 extends from the terminal portion 53 towards the die pad 11. An internal terminal is formed at the tip of the inner lead 51 on the surface side. This internal terminal is a region that is electrically connected to the semiconductor element 21 via a bump 26, as will be described later.

[0216] The inner lead 51 is thinned from the back side, for example by half-etching. The inner lead 51 has an inner lead surface 51a and an inner lead back surface 51b. The inner lead surface 51a is located on the front side. An internal terminal is formed on a part of the inner lead surface 51a. In addition, the inner lead tip surface 51c is formed on the side of the inner lead 51 that faces the die pad 11. The inner lead back surface 51b is located on the back side.

[0217] The tip surface 51c of the inner lead of the lead portion 12 is rough over its entire surface. Although not shown in the figure, both sides along the longitudinal direction of the lead portion 12 may also be rough. On the other hand, the inner lead 51 of the lead portion 12 is not thinned from the surface side. The inner lead surface 51a located on the surface side of the inner lead 51 is rough over its entire surface. Also, the terminal portion 53 of the lead portion 12 is not thinned from the surface side. The terminal portion surface 53a located on the surface side of the terminal portion 53 is rough over its entire surface.

[0218] In addition, the configuration of the lead frame 10 according to this embodiment may be the same as the configuration of the lead frame 10 according to the second embodiment.

[0219] In this embodiment, the definitions and measurement methods of "rough surface" and "smooth surface" are the same as in the second embodiment.

[0220] (Configuration of the semiconductor device) Next, the semiconductor device according to this embodiment will be described with reference to Figures 20 to 22. Figures 20 to 22 show the semiconductor device (flip-chip type) according to this embodiment.

[0221] As shown in Figures 20 and 21, the semiconductor device (semiconductor package) 20 comprises a die pad 11, a semiconductor element 21, a plurality of lead portions 12, a plurality of bumps 26, and a sealing resin 23.

[0222] Among these, the semiconductor element 21 is mounted on the die pad 11. Also, the plurality of lead portions 12 are arranged around the die pad 11. The plurality of bumps 26 electrically connect the semiconductor element 21 to the die pad 11 or the lead portions 12, respectively. In this case, the bumps 26 constitute a connection portion. Also, the bumps 26 may be pillars. The encapsulating resin 23 encapsulates the die pad 11, the lead portions 12, the semiconductor element 21, and the bumps 26 with resin.

[0223] Bumps 26 are provided on the die pad 11 and the lead portions 12. Through these bumps 26, the semiconductor element 21 is electrically connected to the die pad 11 and the lead portions 12 to each other.

[0224] The bump (connection portion) 26 is made of a highly conductive metal material such as copper, for example, and may have a solid substantially cylindrical shape or a substantially spherical shape. The upper end of each bump 26 is connected to the electrode 21a of the semiconductor element 21, and the lower end thereof is connected to the die pad 11 and the lead portions 12, respectively. Note that the die pad 11 does not necessarily have to be provided with the bumps 26. In this case, the die pad 11 and the semiconductor element 21 may be fixed to each other with an adhesive such as a die bonding paste.

[0225] FIG. 22 is an enlarged cross-sectional view showing the periphery of the bump 26. As shown in FIG. 22, the bump 26 may include a plurality of layers. For example, the bump 26 includes a first layer 26a located on the die pad 11 or the lead portion 12 side and a second layer 26b located on the semiconductor element 21 side. The first layer 26a may contain a metal such as tin, for example. The height of the first layer 26a may be 1 μm or more and 10 μm or less. The second layer 26b may contain a metal such as copper, for example. The height of the second layer 26b may be 30 μm or more and 100 μm or less.

[0226] Furthermore, the semiconductor device 20 is not limited to a flip-chip type. Instead of the bump 26, for example, a bonding wire may constitute the connection. In this case, the bonding wire may electrically connect the semiconductor element 21 and the lead portion 12 to each other.

[0227] In addition, the configuration of the semiconductor device 20 according to this embodiment may be the same as the configuration of the semiconductor device 20 according to the second embodiment.

[0228] (Manufacturing method for lead frames) Next, the manufacturing method of the lead frame 10 shown in Figures 18 and 19 will be explained using Figures 23(a)-(i). Figure 23(a)-(i) is a cross-sectional view (corresponding to Figure 19) showing the manufacturing method of the lead frame 10.

[0229] First, a metal substrate 31 having a die pad 11 and lead portions 12 located around the die pad 11 is fabricated in the same manner as in the second embodiment (Figures 14(a)-(e)) (Figure 23(a)-(e)).

[0230] Next, a plating layer 36 is formed on a part of the outer periphery of the metal substrate 31 (Figure 23(f)). At this time, the plating layer 36 is formed on the outer periphery of the metal substrate 31, excluding the entire surface. That is, the plating layer 36 is not formed on the entire surface of the metal substrate 31, but on the entire back surface and the entire side surface of the metal substrate 31. More specifically, the plating layer 36 is not formed on the die pad surface 11a of the die pad 11, or on the inner lead surface 51a and terminal surface 53a of the lead portion 12. On the other hand, the plating layer 36 is formed on the die pad back surface 11b, the first die pad side surface 11c, and the second die pad side surface 11d of the die pad 11. The plating layer 36 is also formed on the external terminal 17, the inner lead back surface 51b, and the inner lead tip surface 51c of the lead portion 12. Note that the plating layer 36 does not have to be formed on the surface of the connecting bar 13. The plating layer 36 may be formed on the back surface of the connecting bar 13.

[0231] In this case, as shown in Figure 23(f), the entire surface of the metal substrate 31 is covered with the first jig 45 via an elastic member 44 such as a rubber gasket. By performing electroplating on the metal substrate 31 in this state, a plating layer 36 is formed on the area of ​​the metal substrate 31 excluding the entire surface. The thickness of the plating layer 36 may be greater than 0 μm and less than or equal to 2 μm. As the metal constituting the plating layer 36, for example, silver may be used. When the plating layer 36 consists of silver plating, a silver plating solution mainly composed of silver cyanide and potassium cyanide can be used as the electroplating solution. In this way, by not forming the plating layer 36 over the entire surface of the metal substrate 31, the amount of metal such as silver that constitutes the plating layer 36 can be reduced. This reduces the manufacturing cost of the lead frame 10.

[0232] Next, some of the plating layer 36 present in the region where the rough surface is formed is removed. Specifically, the plating layer 36 present on at least the back surface of the metal substrate 31 is left, and the other plating layers 36 are removed (Figure 23(g)). Specifically, the portion of the plating layer 36 present on the side surface of the metal substrate 31 is removed. As a result, the plating layer 36 on the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 is removed. In addition, the plating layer 36 on the inner lead tip surface 51c and the inner lead back surface 51b of the lead portion 12 is removed.

[0233] During this time, as shown in Figure 23(g), first an elastic member 46 such as a rubber gasket is placed on the back surface of the metal substrate 31, and the second jig 47A is placed on the back side of the metal substrate 31 via the elastic member 46. Next, the plating layer 36 in the portion not covered by the elastic member 46 is peeled off. As a result, the side surface 11c of the first die pad, the side surface 11d of the second die pad, the tip surface 51c of the inner lead, and the back surface 51b of the inner lead are exposed. On the other hand, the plating layer 36 on the back surface 11b of the die pad and on the external terminal 17, which are covered by the elastic member 46, remain.

[0234] Next, as shown in Figure 23(h), a support layer 37 is provided on the back side of the metal substrate 31 to support the metal substrate 31. The support layer 37 may be, for example, a resist layer. Subsequently, as shown in Figure 23(h), a rough surface is formed on the parts of the metal substrate 31 that are not covered by the plating layer 36 by roughening the parts not covered by the plating layer 36. Specifically, the die pad surface 11a, the first die pad side surface 11c, the second die pad side surface 11d, the inner lead surface 51a, the terminal surface 53a, the inner lead tip surface 51c, and the inner lead back surface 51b are each made into rough surfaces. During this time, a micro-etching solution is supplied to the metal substrate 31 to form a rough surface on the entire metal substrate 31, except for the parts covered by the plating layer 36. Here, a micro-etching solution is a surface treatment agent that slightly dissolves the metal surface and forms a rough surface with fine irregularities. For example, when roughening a metal substrate 31 made of copper or a copper alloy, a micro-etching solution mainly composed of hydrogen peroxide and sulfuric acid may be used.

[0235] Next, as shown in Figure 23(i), the support layer 37 and the plating layer 36 are sequentially peeled off to obtain the lead frame 10 shown in Figures 18 and 19.

[0236] (Manufacturing method for semiconductor device) As shown in Figures 24(a)-(d), the manufacturing method for the semiconductor device 20 according to this embodiment can be carried out in substantially the same manner as the manufacturing method for the semiconductor device 20 according to the second embodiment. In this case, each electrode 21a of the semiconductor element 21 is electrically connected to the die pad 11 and the lead portion 12 via the bump 26.

[0237] As described above, according to this embodiment, a plating layer 36 is formed on the metal substrate 31, excluding the surface (Figure 24(f)). Next, the plating layer 36 on the back surface of the metal substrate 31 is left intact, and the other plating layers 36 are removed (Figure 24(g)). After that, a rough surface is formed on the parts of the metal substrate 31 that are not covered by the plating layer 36 (Figure 24(h)). In this way, the plating layer 36 for forming the rough surface is not provided on the entire surface of the metal substrate 31, but only on the parts of the metal substrate 31 excluding the surface. This reduces the amount of metal such as silver that makes up the plating layer 36. As a result, the manufacturing cost of the lead frame 10 can be reduced.

[0238] Incidentally, during long-term use of the semiconductor device 20 manufactured in this manner, it is conceivable that moisture from the air may penetrate from the back side of the semiconductor device 20 through the interface between the sealing resin 23 and the die pad 11 or lead portion 12. In contrast, according to this embodiment, the back surface 51b of the inner lead and the tip surface 51c of the inner lead of the lead portion 12 are rough surfaces. Also, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are rough surfaces. As a result, the distance of the moisture penetration path at the interface between the sealing resin 23 and the die pad 11 or lead portion 12 is increased. This makes it possible to suppress the penetration of moisture from the interface between the sealing resin 23 and the die pad 11 or lead portion 12 to the semiconductor element 21 side (arrow F in Figure 25). A (See reference). As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

[0239] (Fourth embodiment) Next, a fourth embodiment will be described with reference to Figures 26 to 29. Figures 26 to 29 show the fourth embodiment. The fourth embodiment shown in Figures 26 to 29 differs mainly in that a metal layer 25 is provided on the surface of the die pad 11 and the lead portion 12, while other configurations are substantially the same as the third embodiment described above. In Figures 26 to 29, the same reference numerals are used for parts that are the same as those in the second embodiment shown in Figures 8 to 17 and the third embodiment shown in Figures 18 to 25, and detailed descriptions are omitted.

[0240] (Lead frame and semiconductor device configuration) Figure 26 is a cross-sectional view showing the lead frame 10A according to this embodiment, and Figure 27 is a cross-sectional view showing the semiconductor device 20A according to this embodiment.

[0241] In the lead frame 10A shown in Figure 26 and the semiconductor device 20A shown in Figure 27, a metal layer 25 is located on a portion of the die pad 11 and a portion of the lead portion 12. Specifically, multiple metal layers 25 are provided on the die pad surface 11a of the die pad 11 to improve adhesion with the bumps 26. In addition, a metal layer 25 is provided on the internal terminals formed on the inner leads 51 of the lead portion 12 to improve adhesion with the bumps 26.

[0242] The metal layer 25 is intended to improve the connection between the bump 26 and the die pad 11 and lead portion 12. The metal layer 25 may be a plated layer formed by, for example, electroplating. The thickness of the metal layer 25 may be 1 μm or more and 10 μm or less. The metal that constitutes such a plated layer may be silver, silver alloy, gold, gold alloy, platinum group metals, copper, copper alloy, palladium, etc. Depending on the metal that constitutes the metal layer 25, if an undercoat plating is required, known materials such as nickel or copper may be used.

[0243] As shown in Figures 26 and 27, the surface of the lead portion 12 has a smooth first surface portion 56a and a rough second surface portion 56b. The first surface portion 56a is located at the inner (die pad 11 side) end of the lead portion 12. A metal layer 25 is formed on the first surface portion 56a. The entire first surface portion 56a is smooth. The first surface portion 56a is located in part of the inner lead surface 51a.

[0244] The second surface portion 56b is adjacent to the outside of the first surface portion 56a and the metal layer 25 (opposite side of the die pad 11). The second surface portion 56b is in direct contact with the first surface portion 56a and the metal layer 25. The entire surface of this second surface portion 56b is rough. In the lead frame 10A, it is preferable that the second surface portion 56b extends continuously to the connection between the lead portion 12 and the connecting bar 13. The surface of the connecting bar 13 may also be rough. The second surface portion 56b is located on a part of the inner lead surface 51a and a part of the terminal portion surface 53a.

[0245] As shown in Figure 27, in the semiconductor device 20A, the bumps 26 are provided on the metal layer 25. The upper end of each bump 26 is connected to the electrode 21a of the semiconductor element 21, and the lower end is connected to the die pad 11 and the lead portion 12, respectively, via the metal layer 25. Note that the die pad 11 does not necessarily have to be provided with the metal layer 25 and the bumps 26.

[0246] In this embodiment, the definitions and measurement methods of "rough surface" and "smooth surface" are the same as in the second embodiment.

[0247] (Manufacturing method for lead frames) Next, the manufacturing method of the lead frame 10A shown in Figure 26 will be explained using Figures 28(a)-(j). In Figures 28(a)-(j), the same reference numerals are used for parts that are the same as those shown in Figure 23(a)-(i), and detailed explanations are omitted.

[0248] First, a metal substrate 31 having a die pad 11 and lead portions 12 located around the die pad 11 is fabricated in the same manner as in the second embodiment (Figures 14(a)-(e)) (Figures 28(a)-(e)).

[0249] Next, a plating layer 36 is formed on the metal substrate 31, excluding a portion of the surface (Figure 28(f)). At this time, the plating layer 36 is formed on a portion of the surface, the entire back surface, and the entire side surface of the metal substrate 31. The plating layer 36 is also formed on a portion of the surface of the die pad 11 and a portion of the surface of the lead portion 12. More specifically, the plating layer 36 is formed on the die pad surface 11a of the die pad 11 in the region where the metal layer 25 is formed, and not on any other region. The plating layer 36 is also formed on the die pad back surface 11b, the first die pad side surface 11c, and the second die pad side surface 11d of the die pad 11. The plating layer 36 is also formed on the first surface portion 56a, the external terminal 17, the inner lead back surface 51b, and the inner lead tip surface 51c of the lead portion 12. On the other hand, the plating layer 36 is not formed on the second surface portion 56b of the lead portion 12. Furthermore, the plating layer 36 does not necessarily have to be formed on the surface of the connecting bar 13; it may also be formed on the back surface of the connecting bar 13.

[0250] In this case, as shown in Figure 28(f), a portion of the surface of the metal substrate 31 is covered with the first jig 45A via an elastic member 44A such as a rubber gasket. By performing electroplating on the metal substrate 31 in this state, a plating layer 36 is formed on the area of ​​the metal substrate 31 excluding a portion of the surface. In this way, by not forming the plating layer 36 on a portion of the surface of the metal substrate 31, the amount of metal such as silver that constitutes the plating layer 36 can be reduced. This reduces the manufacturing cost of the lead frame 10A. The material and thickness of the plating layer 36 can be the same as in the third embodiment.

[0251] Next, a portion of the plating layer 36 present in the area where the rough surface is formed is removed (Figure 28(g)). At this time, the plating layer 36 present on a portion of the surface and the back surface of the metal substrate 31 is left, and the rest of the plating layer 36 is removed. Specifically, the portions of the plating layer 36 corresponding to the first die pad side surface 11c, the second die pad side surface 11d, the inner lead tip surface 51c, and the inner lead back surface 51b of the metal substrate 31 are removed.

[0252] During this time, as shown in Figure 28(g), elastic members 46 are first placed on the front and back surfaces of the metal substrate 31, and the metal substrate 31 is sandwiched by the second jig 47B via the elastic members 46, such as rubber gaskets. The elastic member 46 on the front surface of the metal substrate 31 covers the entire surface area of ​​the metal substrate 31. Next, the plating layer 36 in the parts not covered by the elastic members 46 is peeled off. This exposes the first die pad side surface 11c, the second die pad side surface 11d, the inner lead tip surface 51c, and the inner lead back surface 51b. On the other hand, the plating layer 36 on the die pad surface 11a, the die pad back surface 11b, the first surface portion 56a, and the external terminal 17, which are covered by the elastic members 46, remain.

[0253] Next, a support layer 37 is provided on the back side of the metal substrate 31 in substantially the same manner as the process shown in Figure 23(h) above. Then, the portion of the metal substrate 31 not covered by the plating layer 36 is roughened to form a rough surface on the portion not covered by the plating layer 36 (Figure 28(h)). As a result, the first die pad side surface 11c, the second die pad side surface 11d, the second surface portion 56b, the inner lead tip surface 51c, and the inner lead back surface 51b become rough surfaces.

[0254] Next, the support layer 37 and the plating layer 36 are sequentially peeled off in substantially the same manner as shown in Figure 23(i) (Figure 28(i)).

[0255] Subsequently, as shown in Figure 28(j), a metal layer 25 is formed on a portion of the surface of the metal substrate 31. Specifically, the metal layer 25 is formed on a portion of the die pad 11 and a portion of the lead portion 12. In this case, first, a plating resist layer with a predetermined pattern (not shown) is formed on the die pad 11 and the lead portion 12, for example by photolithography. Next, a metal layer 25 consisting of a plating layer is formed on the areas not covered by this plating resist layer, for example by electroplating. After that, the lead frame 10A shown in Figure 26 is obtained by removing the plating resist layer.

[0256] (Manufacturing method for semiconductor device) The manufacturing method for the semiconductor device 20A according to this embodiment can be carried out in substantially the same manner as the manufacturing method for the semiconductor device 20 shown in Figures 24(a)-(d). In this case, each electrode 21a of the semiconductor element 21 is electrically connected to the die pad 11 and the lead portion 12 via the bump 26 and the metal layer 25, respectively.

[0257] As described above, according to this embodiment, a plating layer 36 is formed on the metal substrate 31, excluding a portion of the surface (Figure 28(f)). Next, the plating layer 36 present on a portion of the surface and the back surface of the metal substrate 31 is left, and the other plating layers 36 are removed (Figure 28(g)). After that, a rough surface is formed on the portion of the metal substrate 31 that is not covered by the plating layer 36 (Figure 28(h)). In this way, the plating layer 36 for forming the rough surface is not provided on the entire surface of the metal substrate 31, but only on a portion of the metal substrate 31, excluding a portion of the surface. This reduces the amount of metal such as silver that constitutes the plating layer 36. As a result, the manufacturing cost of the lead frame 10 can be reduced.

[0258] Furthermore, according to this embodiment, the second surface portion 56b adjacent to the outside of the metal layer 25 is roughened. As a result, the distance of the moisture intrusion path at the interface between the surface of the lead portion 12 and the sealing resin 23 is increased. This makes it possible to suppress the intrusion of moisture from the interface between the surface of the lead portion 12 and the sealing resin 23 to the semiconductor element 21 side (arrow F in Figure 29). B (See reference). As a result, the reliability of the semiconductor device 20A after long-term use can be improved.

[0259] Furthermore, according to this embodiment, the second surface portion 56b of the lead portion 12 is roughened. This increases the adhesion strength between the second surface portion 56b and the sealing resin 23, and suppresses the separation of the surface of the lead portion 12 and the sealing resin 23 from each other.

[0260] Also, according to the present embodiment, on the back surface side of the semiconductor device 20A, the distance of the moisture intrusion path at the interface between the encapsulation resin 23 and the die pad 11 or the lead portion 12 is increased. As a result, it is possible to suppress moisture from intruding from the interface between the encapsulation resin 23 and the die pad 11 or the lead portion 12 toward the semiconductor element 21 side (arrow F in FIG. 29 A reference). As a result, the reliability of the semiconductor device 20A after long-term use can be improved.

[0261] (Fifth Embodiment) The fifth embodiment will be described with reference to FIGS. 30 to 37. FIGS. 30 to 37 are diagrams showing the fifth embodiment. In FIGS. 30 to 37, the same parts as those in the embodiments shown in FIGS. 8 to 29 are denoted by the same reference numerals, and detailed description thereof is omitted.

[0262] (Configuration of Lead Frame) First, the outline of the lead frame according to the present embodiment will be described with reference to FIGS. 30 and 31. FIGS. 30 and 31 are diagrams showing the lead frame according to the present embodiment.

[0263] In this specification, the "outer periphery" refers to a portion of the lead frame 10 (metal substrate) that is exposed on the outside, and refers to a region including the "front surface", "side surface", and "back surface".

[0264] As shown in FIGS. 30 and 31, each package region 10a of the lead frame 10 includes a die pad 11 and a lead portion 12 located around the die pad 11. Among these, a part of the lead portion 12 is thinned from the back surface side. Among the back surfaces of the lead portion 12, the thinned portion is a rough surface. Among the back surfaces of the lead portion 12, the non-thinned portion is a smooth surface.

[0265] As shown in Figure 31, the die pad 11 has a die pad surface 11a located on the front side and a die pad back surface 11b located on the back side. A semiconductor element 21 is mounted on the die pad surface 11a, as will be described later. The die pad back surface 11b is exposed outward from the semiconductor device 20 (described later). In addition, a first die pad side surface 11c and a second die pad side surface 11d are formed on the side of the die pad 11 facing the lead portion 12. The first die pad side surface 11c is located on the die pad surface 11a side. The second die pad side surface 11d is located on the die pad back surface 11b side. In this case, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are rough surfaces. On the other hand, the die pad surface 11a and the die pad back surface 11b of the die pad 11 are smooth surfaces.

[0266] In this embodiment, the definitions and measurement methods of "rough surface" and "smooth surface" are the same as in the second embodiment.

[0267] The roughened surface may be formed by roughening the outer surface of the metal substrate 31, as described later, with a micro-etching solution mainly composed of hydrogen peroxide and sulfuric acid. The smooth surface may be the unprocessed surface of the metal substrate 31, which has not undergone such roughening treatment. In Figure 31, the roughened portion is shown by a thick dashed line (the same applies to the other cross-sectional views).

[0268] As shown in Figure 31, the lead portion 12 has an inner lead 51 and a terminal portion 53. The inner lead 51 is located on the inside (die pad 11 side). The terminal portion 53 is located on the outside (connecting bar 13 side). The inner lead 51 extends from the terminal portion 53 towards the die pad 11. An internal terminal is formed at the tip of the inner lead 51 on the surface side. This internal terminal is a region that is electrically connected to the semiconductor element 21 via a bump 26, as will be described later. A metal layer 25 is provided on the internal terminal to improve adhesion with the bump 26.

[0269] The inner lead 51 is thinned from the back side, for example by half-etching. The inner lead 51 has an inner lead surface 51a and an inner lead back surface 51b. The inner lead surface 51a is located on the front side. An internal terminal is formed on a part of the inner lead surface 51a. In addition, the inner lead tip surface 51c is formed on the side of the inner lead 51 that faces the die pad 11. The inner lead back surface 51b is located on the back side.

[0270] Furthermore, the tip surface 51c of the inner lead of the lead portion 12 is rough over its entire surface. Although not shown in the figures, both sides along the longitudinal direction of the lead portion 12 may also be rough. On the other hand, the inner lead 51 of the lead portion 12 is not thinned from the surface side. The inner lead surface 51a located on the surface side of the inner lead 51 is smooth over its entire surface. Also, the terminal portion 53 of the lead portion 12 is not thinned from the surface side. The terminal portion surface 53a located on the surface side of the terminal portion 53 is smooth over its entire surface.

[0271] As shown in Figure 31, a metal layer 25 is located on the die pad 11 and the lead portion 12. This metal layer 25 is formed on a portion of the die pad 11 and a portion of the lead portion 12. The metal layer 25 is intended to improve the connection between the bump 26 and the die pad 11 and the lead portion 12. The metal layer 25 may be a plating layer formed by, for example, electroplating. The thickness of the metal layer 25 may be 1 μm or more and 10 μm or less. As the metal constituting such a plating layer, silver, silver alloys, gold, gold alloys, platinum group metals, copper, copper alloys, palladium, etc. may be used. Depending on the metal constituting the metal layer 25, if an undercoat plating is required, known materials such as nickel or copper may be used.

[0272] In addition, the configuration of the lead frame 10 according to this embodiment may be the same as the configuration of the lead frame 10 according to the second embodiment.

[0273] (Configuration of a semiconductor device) Next, the semiconductor device according to this embodiment will be described with reference to Figures 32 to 34. Figures 32 to 34 show the semiconductor device (flip-chip type) according to this embodiment.

[0274] As shown in Figures 32 and 33, the semiconductor device (semiconductor package) 20 comprises a die pad 11, a semiconductor element 21, a plurality of lead portions 12, a plurality of bumps 26, and a sealing resin 23.

[0275] The semiconductor element 21 is mounted on the die pad 11. Multiple lead portions 12 are arranged around the die pad 11. A metal layer 25 is formed on both the die pad 11 and the lead portions 12. Bumps 26 are provided on the metal layer 25. The semiconductor element 21, the die pad 11, and the lead portions 12 are electrically connected to each other via these bumps 26.

[0276] One side of the sealing resin 23 (one side of the semiconductor device 20) may be, for example, 0.2 mm or more and 16 mm or less.

[0277] The bumps (connecting parts) 26 are made of a highly conductive metal material such as copper, and may have a solid, approximately cylindrical or approximately spherical shape. The upper end of each bump 26 is connected to the electrode 21a of the semiconductor element 21, and the lower end is connected to the die pad 11 and the lead portion 12, respectively, via the metal layer 25. The die pad 11 does not necessarily have to be provided with the metal layer 25 and the bumps 26. In this case, the die pad 11 and the semiconductor element 21 may be fixed to each other with an adhesive such as die bonding paste.

[0278] Figure 34 is an enlarged cross-sectional view showing the periphery of the bump 26. As shown in Figure 34, the bump 26 may include multiple layers. For example, the bump 26 includes a first layer 26a located on the metal layer 25 side and a second layer 26b located on the semiconductor element 21 side. The first layer 26a may contain a metal such as tin. The height of the first layer 26a may be between 1 μm and 10 μm. The second layer 26b may contain a metal such as copper. The height of the second layer 26b may be between 30 μm and 100 μm.

[0279] Furthermore, the configuration of the die pad 11 and lead portion 12 is the same as that shown in Figures 30 and 31 above, except for the areas not included in the semiconductor device 20, so a detailed explanation is omitted here.

[0280] Furthermore, the semiconductor device 20 is not limited to a flip-chip type. Instead of the bump 26, for example, a bonding wire may constitute the connection. In this case, the bonding wire may electrically connect the semiconductor element 21 and the lead portion 12 to each other.

[0281] In addition, the configuration of the semiconductor device 20 according to this embodiment may be the same as the configuration of the semiconductor device 20 according to the second embodiment.

[0282] (Manufacturing method for lead frames) Next, the manufacturing method of the lead frame 10 shown in Figures 30 and 31 will be explained using Figures 35(a)-(j). Figures 35(a)-(j) are cross-sectional views (corresponding to Figure 31) showing the manufacturing method of the lead frame 10.

[0283] First, a metal substrate 31 having a die pad 11 and lead portions 12 located around the die pad 11 is fabricated in the same manner as in the second embodiment (Figures 14(a)-(e)) (Figure 35(a)-(e)).

[0284] Next, a plating layer 36 is formed around the metal substrate 31 (Figure 35(f)). At this time, the plating layer 36 is formed around the entire circumference of the die pad 11, lead portion 12, and connecting bar 13. The thickness of the plating layer 36 may be greater than 0 μm and less than or equal to 2 μm. As the metal constituting the plating layer 36, for example, silver may be used. When the plating layer 36 consists of silver plating, a silver plating solution mainly composed of silver cyanide and potassium cyanide can be used as the electrolytic plating solution.

[0285] Next, a portion of the plating layer 36 present in the region where the rough surface is formed is removed. Specifically, the portion of the plating layer 36 located other than the front and back surfaces of the metal substrate 31 is removed (Figure 35(g)). This removes the plating layer 36 from the first die pad side surface 11c of the die pad 11, the second die pad side surface 11d of the die pad 11, the inner lead tip surface 51c of the lead portion 12, and the inner lead back surface 51b of the lead portion 12.

[0286] During this time, as shown in Figure 35(g), elastic members 46 such as rubber gaskets are first placed on the front and back surfaces of the metal substrate 31, and the metal substrate 31 is sandwiched by a jig 47C via the elastic members 46. Next, the plating layer 36 in the parts not covered by the elastic members 46 is peeled off. As a result, the side surface 11c of the first die pad, the side surface 11d of the second die pad, the tip surface 51c of the inner lead, and the back surface 51b of the inner lead are exposed. On the other hand, the plating layer 36 on the die pad surface 11a, the terminal surface 53a, the back surface 11b of the die pad, the inner lead surface 51a, and the external terminal 17, which are covered by the elastic members 46, remain.

[0287] Next, as shown in Figure 35(h), a support layer 37 is provided on the back side of the metal substrate 31 to support the metal substrate 31. The support layer 37 may be, for example, a resist layer. Subsequently, as shown in Figure 35(h), a rough surface is formed on the parts of the metal substrate 31 that are not covered by the plating layer 36 by roughening the parts not covered by the plating layer 36. Specifically, the first die pad side surface 11c, the second die pad side surface 11d, the inner lead tip surface 51c, and the inner lead back surface 51b are made rough. During this time, a micro-etching solution is supplied to the metal substrate 31 to form a rough surface on the entire metal substrate 31, except for the parts covered by the plating layer 36. Here, a micro-etching solution is a surface treatment agent that slightly dissolves the metal surface and forms a rough surface with fine irregularities. For example, when roughening a metal substrate 31 made of copper or a copper alloy, a micro-etching solution mainly composed of hydrogen peroxide and sulfuric acid may be used.

[0288] Next, as shown in Figure 35(i), the support layer 37 and the plating layer 36 are sequentially peeled off and removed.

[0289] Subsequently, as shown in Figure 35(j), a metal layer 25 is formed on the die pad 11 and lead portion 12. In this case, first, a plating resist layer with a predetermined pattern (not shown) is formed on the die pad 11 and lead portion 12, for example by photolithography. Next, a metal layer 25 consisting of a plating layer is formed in the areas not covered by this plating resist layer, for example by electroplating. After that, the lead frame 10 shown in Figures 30 and 31 is obtained by removing the plating resist layer.

[0290] (Manufacturing method for semiconductor device) As shown in Figures 36(a)-(d), the manufacturing method for the semiconductor device 20 according to this embodiment can be carried out in substantially the same manner as the manufacturing method for the semiconductor device 20 according to the second embodiment. In this case, each electrode 21a of the semiconductor element 21 and the die pad 11 and lead portion 12 are electrically connected to each other via the bump 26 and metal layer 25, respectively.

[0291] Incidentally, during long-term use of the semiconductor device 20 manufactured in this manner, it is conceivable that moisture from the air may penetrate from the back side of the semiconductor device 20 through the interface between the sealing resin 23 and the die pad 11 or lead portion 12. In contrast, according to this embodiment, the back surface 51b of the inner lead and the tip surface 51c of the inner lead of the lead portion 12 are rough surfaces. Also, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are rough surfaces. As a result, the distance of the moisture penetration path at the interface between the sealing resin 23 and the die pad 11 or lead portion 12 is increased. This makes it possible to suppress the penetration of moisture from the interface between the sealing resin 23 and the die pad 11 or lead portion 12 to the semiconductor element 21 side (arrow F in Figure 37). A (See reference). As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

[0292] In particular, in the flip-chip type semiconductor device 20, the electrodes 21a of the semiconductor element 21 face the back side. Therefore, in the flip-chip type semiconductor device 20, the distance from the back side of the semiconductor device 20 to the electrodes 21a of the semiconductor element 21 tends to be short. In contrast, according to this embodiment, the thinned portion of the back side of the lead portion 12 has a rough surface. This makes it possible to more effectively suppress the intrusion of moisture into the semiconductor element 21 side from the interface between the sealing resin 23 and the lead portion 12.

[0293] Furthermore, according to this embodiment, the inner lead back surface 51b and the inner lead tip surface 51c of the lead portion 12 are rough surfaces. Also, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are rough surfaces. This increases the adhesion strength between the die pad 11 and the lead portion 12 and the sealing resin 23, and suppresses the separation of the die pad 11 and the lead portion 12 from the sealing resin 23.

[0294] (Sixth embodiment) Next, a sixth embodiment will be described with reference to Figures 38 to 41. Figures 38 to 41 show the sixth embodiment. The sixth embodiment shown in Figures 38 to 41 differs mainly in that a rough surface is formed on the surface of the lead portion 12, and the other configurations are substantially the same as the fifth embodiment described above. In Figures 38 to 41, the same reference numerals are used for parts that are the same as those in the embodiments shown in Figures 8 to 37, and detailed descriptions are omitted.

[0295] (Lead frame and semiconductor device configuration) Figure 38 is a cross-sectional view showing the lead frame 10A according to this embodiment, and Figure 39 is a cross-sectional view showing the semiconductor device 20A according to this embodiment.

[0296] In the lead frame 10A shown in Figure 38 and the semiconductor device 20A shown in Figure 39, the surface of the lead portion 12 has a first surface portion 54a which is a smooth surface and a second surface portion 54b which is a rough surface.

[0297] The first surface portion 54a is adjacent to the outside of the metal layer 25 (opposite side of the die pad 11). The first surface portion 54a is in direct contact with the metal layer 25. The entire surface of this first surface portion 54a is smooth. The length of the first surface portion 54a along the longitudinal direction of the lead portion 12 (length in the X direction) L A The thickness may be 25 μm or more and 200 μm or less, and preferably 50 μm or more and 100 μm or less. The first surface portion 54a is located in part of the inner lead surface 51a, but is not limited to that. The first surface portion 54a may be located in part of the inner lead surface 51a and part of the terminal surface 53a, for example.

[0298] The second surface portion 54b is adjacent to the outside of the first surface portion 54a. That is, the second surface portion 54b is in direct contact with the first surface portion 54a. The entire surface of this second surface portion 54b is rough. In the lead frame 10A, it is preferable that the second surface portion 54b extends continuously to the connection portion between the lead portion 12 and the connecting bar 13. The surface of the connecting bar 13 may also be rough. The second surface portion 54b is located on a part of the inner lead surface 51a and a part of the terminal portion surface 53a, but is not limited to this. The second surface portion 54b may also be located on a part of the terminal portion surface 53a.

[0299] In this embodiment, the definitions and measurement methods of "rough surface" and "smooth surface" are the same as in the second embodiment.

[0300] (Manufacturing method for lead frames) Next, the manufacturing method of the lead frame 10A shown in Figure 38 will be explained using Figures 40(a)-(j). In Figures 40(a)-(j), the same reference numerals are used for parts that are the same as those shown in Figures 35(a)-(j), and detailed explanations are omitted.

[0301] First, a metal substrate 31 having a die pad 11 and lead portions 12 located around the die pad 11 is fabricated in the same manner as in the second embodiment (Figures 14(a)-(e)) (Figures 40(a)-(e)).

[0302] Next, a plating layer 36 is formed around the entire circumference of the metal substrate 31 in substantially the same manner as the process shown in Figure 35(f) above (Figure 40(f)).

[0303] Next, the portion of the plating layer 36 corresponding to the first die pad side surface 11c, the second die pad side surface 11d, the second surface portion 54b, the inner lead tip surface 51c, and the inner lead back surface 51b of the metal substrate 31 is removed (Figure 40(g)).

[0304] During this time, as shown in Figure 40(g), elastic members 46 such as rubber gaskets are first placed on the front and back surfaces of the metal substrate 31, and the metal substrate 31 is sandwiched by the jig 47D via the elastic members 46. The elastic member 46 on the front surface side of the metal substrate 31 covers the die pad surface 11a, the area corresponding to the first surface portion 54a, and the area where the metal layer 25 of the lead portion 12 is provided. Next, the plating layer 36 in the parts not covered by the elastic member 46 is peeled off. As a result, the first die pad side surface 11c, the second die pad side surface 11d, the second surface portion 54b, the inner lead tip surface 51c, and the inner lead back surface 51b are exposed. On the other hand, the plating layer 36 on the die pad surface 11a, the die pad back surface 11b, the first surface portion 54a, and the external terminal 17, which are covered by the elastic member 46, remain.

[0305] Next, a support layer 37 is provided on the back side of the metal substrate 31 in substantially the same manner as the process shown in Figure 35(h) above. Then, the portion of the metal substrate 31 not covered by the plating layer 36 is roughened to form a rough surface on the portion not covered by the plating layer 36 (Figure 40(h)). As a result, the first die pad side surface 11c, the second die pad side surface 11d, the second surface portion 54b, the inner lead tip surface 51c, and the inner lead back surface 51b become rough surfaces.

[0306] Next, the support layer 37 and the plating layer 36 are sequentially peeled off in substantially the same manner as shown in Figure 35(i) (Figure 40(i)).

[0307] Subsequently, a metal layer 25 is formed on the die pad 11 and lead portion 12 in substantially the same manner as the process shown in Figure 35(j) above. In this way, the lead frame 10A shown in Figure 38 is obtained (Figure 40(j)).

[0308] (Method of manufacturing semiconductor devices) The method for manufacturing the semiconductor device 20A according to this embodiment can be carried out in substantially the same manner as the method for manufacturing the semiconductor device 20 shown in Figures 36(a)-(d).

[0309] According to this embodiment, the first surface portion 54a of the lead portion 12 adjacent to the outside of the metal layer 25 is a smooth surface. This makes it possible to suppress the flow of tin and other materials contained in the bump 26 along the first surface portion 54a when mounting the semiconductor element 21 on the die pad 11 (arrow F in Figure 41). C (See reference). On the other hand, if the first surface portion 54a is rough, there is a risk that tin and other materials contained in the bump 26 may flow out along the first surface portion 54a due to surface tension.

[0310] Furthermore, according to this embodiment, the second surface portion 54b adjacent to the outside of the first surface portion 54a is roughened. As a result, the distance of the moisture intrusion path at the interface between the surface of the lead portion 12 and the sealing resin 23 is increased. This makes it possible to suppress the intrusion of moisture from the interface between the surface of the lead portion 12 and the sealing resin 23 to the semiconductor element 21 side (arrow F in Figure 41). B (See reference). As a result, the reliability of the semiconductor device 20A after long-term use can be improved.

[0311] Furthermore, according to this embodiment, the second surface portion 54b of the lead portion 12 is roughened. This increases the adhesion strength between the second surface portion 54b and the sealing resin 23, and suppresses the separation of the surface of the lead portion 12 and the sealing resin 23 from each other.

[0312] Furthermore, according to this embodiment, on the back side of the semiconductor device 20A, the distance of the moisture intrusion path at the interface between the sealing resin 23 and the die pad 11 or lead portion 12 is increased. This makes it possible to suppress moisture from entering the semiconductor element 21 side from the interface between the sealing resin 23 and the die pad 11 or lead portion 12 (arrow F in Figure 41). A (See reference). As a result, the reliability of the semiconductor device 20A after long-term use can be improved.

[0313] (Seventh Embodiment) Next, a seventh embodiment will be described with reference to Figures 42 to 45. Figures 42 to 45 show the seventh embodiment. The seventh embodiment shown in Figures 42 to 45 differs mainly in that a recess 18 is formed on the surface of the lead portion 12, and the other configurations are substantially the same as the fifth embodiment described above. In Figures 42 to 45, the same reference numerals are used for parts that are the same as those in the embodiments shown in Figures 8 to 41, and detailed descriptions are omitted.

[0314] (Lead frame and semiconductor device configuration) Figure 42 is a cross-sectional view showing the lead frame 10B according to this embodiment, and Figure 43 is a cross-sectional view showing the semiconductor device 20B according to this embodiment.

[0315] In the lead frame 10B shown in Figure 42 and the semiconductor device 20B shown in Figure 43, a recess 18 is formed on the surface of the lead portion 12, on the outside of the metal layer 25 (opposite side of the die pad 11). The portion adjacent to the outside of the recess 18 (third surface portion 54c) is rough. The inner surface of the recess 18 is smooth. The portion located between the recess 18 and the metal layer 25 (fourth surface portion 54d) is smooth.

[0316] The fourth surface portion 54d is adjacent to the outside of the metal layer 25 (opposite side of the die pad 11). The fourth surface portion 54d is in direct contact with the metal layer 25. The entire surface of this fourth surface portion 54d is smooth. The length of the fourth surface portion 54d along the longitudinal direction of the lead portion 12 (length in the X direction) L B The particle size may be 25 μm or more and 200 μm or less, and preferably 50 μm or more and 100 μm or less.

[0317] The recess 18 is adjacent to the outside of the fourth surface portion 54d (opposite side of the die pad 11). The recess 18 is in direct contact with the fourth surface portion 54d. The inner surface of the recess 18 is entirely smooth. The length of the recess 18 along the longitudinal direction of the lead portion 12 (length in the X direction) L cThe thickness of the lead portion may be 50 μm or more and 150 μm or less, preferably 75 μm or more and 100 μm or less. The depth of the recess 18 may be 25 μm or more and 125 μm or less, preferably 50 μm or more and 100 μm or less. The planar shape of the recess 18 may be, for example, a circle, a square, or other polygon. The recess 18 is provided in a part of the width direction of the lead portion 12. However, it is not limited to this, and the recess 18 may be provided over the entire width direction of the lead portion 12.

[0318] The third surface portion 54c is adjacent to the outside of the recess 18 (opposite side of the die pad 11). The third surface portion 54c is in direct contact with the recess 18. The entire surface of this third surface portion 54c is rough. In the lead frame 10B, it is preferable that the third surface portion 54c extends continuously to the connection between the lead portion 12 and the connecting bar 13. The surface of the connecting bar 13 may also be rough.

[0319] In this embodiment, the definitions and measurement methods of "rough surface" and "smooth surface" are the same as in the second embodiment.

[0320] (Manufacturing method for lead frames) Next, the manufacturing method of the lead frame 10B shown in Figure 42 will be explained using Figures 44(a)-(j). In Figures 44(a)-(j), the same reference numerals are used for parts that are the same as those shown in Figures 35(a)-(j), and detailed explanations are omitted.

[0321] First, a metal substrate 31 is prepared in substantially the same manner as the process shown in Figures 35(a) and (b) above (Figure 44(a)), and photosensitive resists 32a and 33a are formed on the front and back surfaces of the metal substrate 31, respectively (Figure 44(b)).

[0322] Next, etching resist layers 32 and 33 having openings 32b and 33b are formed in substantially the same manner as the process shown in Figure 35(c) above (Figure 44(c)). At this time, an opening 32b is also formed in the region corresponding to the recess 18.

[0323] Next, the metal substrate 31 is etched in substantially the same manner as the process shown in Figure 35(d) above to form the outer shapes of the die pad 11, lead portion 12, and connecting bar 13 (Figure 44(d)). At this time, a recess 18 is formed on the surface of the lead portion 12. Then, the etching resist layers 32 and 33 are peeled off in substantially the same manner as the process shown in Figure 35(e) above (Figure 44(e)).

[0324] Next, a plating layer 36 is formed around the entire circumference of the metal substrate 31 in substantially the same manner as the process shown in Figure 35(f) above (Figure 44(f)). At this time, a plating layer 36 is also formed inside the recess 18.

[0325] Next, the portion of the plating layer 36 corresponding to the first die pad side surface 11c, the second die pad side surface 11d, the third surface portion 54c, the inner lead tip surface 51c, and the inner lead back surface 51b of the metal substrate 31 is removed (Figure 44(g)).

[0326] During this time, as shown in Figure 44(g), elastic members 46 such as rubber gaskets are first placed on the front and back surfaces of the metal substrate 31, and the metal substrate 31 is sandwiched by a jig 47E via the elastic members 46. The elastic member 46 on the front surface side of the metal substrate 31 covers the die pad surface 11a, the recess 18, the area corresponding to the fourth surface portion 54d, and the area where the metal layer 25 of the lead portion 12 is provided. Next, the plating layer 36 in the parts not covered by the elastic member 46 is peeled off. As a result, the first die pad side surface 11c, the second die pad side surface 11d, the third surface portion 54c, the inner lead tip surface 51c, and the inner lead back surface 51b are exposed. On the other hand, the plating layer 36 on the die pad surface 11a, the die pad back surface 11b, the inner surface of the recess 18, the fourth surface portion 54d, and the external terminal 17, which were covered by the elastic member 46, remain.

[0327] Next, a support layer 37 is provided on the back side of the metal substrate 31 in substantially the same manner as the process shown in Figure 35(h) above. Then, the portion of the metal substrate 31 not covered by the plating layer 36 is roughened to form a rough surface on the portion not covered by the plating layer 36 (Figure 44(h)). As a result, the first die pad side surface 11c, the second die pad side surface 11d, the third surface portion 54c, the inner lead tip surface 51c, and the inner lead back surface 51b become rough surfaces.

[0328] Next, the support layer 37 and the plating layer 36 are sequentially peeled off in substantially the same manner as shown in Figure 35(i) (Figure 44(i)).

[0329] Subsequently, a metal layer 25 is formed on the die pad 11 and lead portion 12 in substantially the same manner as the process shown in Figure 35(j) above. In this way, the lead frame 10B shown in Figure 42 is obtained (Figure 44(j)).

[0330] (Method of manufacturing semiconductor devices) The method for manufacturing the semiconductor device 20B according to this embodiment can be carried out in substantially the same manner as the method for manufacturing the semiconductor device 20 shown in Figures 36(a)-(d).

[0331] According to this embodiment, the fourth surface portion 54d of the lead portion 12 adjacent to the outside of the metal layer 25 is a smooth surface. This makes it possible to suppress the flow of tin and other materials contained in the bump 26 along the fourth surface portion 54d when mounting the semiconductor element 21 on the die pad 11 (arrow F in Figure 45). C (See reference). On the other hand, if the fourth surface portion 54d is rough, there is a risk that tin and other materials contained in the bump 26 may flow out along the fourth surface portion 54d due to surface tension.

[0332] Furthermore, according to this embodiment, a recess 18 is formed on the surface of the lead portion 12, outside the metal layer 25. As a result, even if tin or the like contained in the bump 26 flows out along the fourth surface portion 54d, the flowing tin or the like can be caught by the recess 18. This prevents the flowing tin or the like from reaching the third surface portion 54c.

[0333] Furthermore, according to this embodiment, the third surface portion 54c adjacent to the outside of the recess 18 is roughened. As a result, the distance of the moisture intrusion path at the interface between the surface of the lead portion 12 and the sealing resin 23 is increased. This makes it possible to suppress the intrusion of moisture from the interface between the surface of the lead portion 12 and the sealing resin 23 to the semiconductor element 21 side (arrow F in Figure 45). B (See reference). As a result, the reliability of the semiconductor device 20B after long-term use can be improved.

[0334] Furthermore, according to this embodiment, the third surface portion 54c of the lead portion 12 is roughened. This increases the adhesion strength between the third surface portion 54c and the sealing resin 23, and suppresses the separation of the surface of the lead portion 12 and the sealing resin 23 from each other.

[0335] Furthermore, according to this embodiment, on the back side of the semiconductor device 20B, the distance of the moisture intrusion path at the interface between the sealing resin 23 and the die pad 11 or lead portion 12 is increased. This makes it possible to suppress moisture from entering the semiconductor element 21 side from the interface between the sealing resin 23 and the die pad 11 or lead portion 12 (arrow F in Figure 45). A (See reference). As a result, the reliability of the semiconductor device 20B after long-term use can be improved.

[0336] (Eighth embodiment) Next, an eighth embodiment will be described with reference to Figures 46 to 49. Figures 46 to 49 show the eighth embodiment. The eighth embodiment shown in Figures 46 to 49 differs mainly in that the inner surface of the recess 18 is roughened, and the other configurations are substantially the same as the seventh embodiment described above. In Figures 46 to 49, the same reference numerals are used for parts that are the same as those in the embodiments shown in Figures 8 to 45, and detailed descriptions are omitted.

[0337] (Lead frame and semiconductor device configuration) Figure 46 is a cross-sectional view showing the lead frame 10C according to this embodiment, and Figure 47 is a cross-sectional view showing the semiconductor device 20C according to this embodiment.

[0338] In the lead frame 10C shown in Figure 46 and the semiconductor device 20C shown in Figure 47, a recess 18 is formed on the surface of the lead portion 12, on the outside of the metal layer 25 (opposite side of the die pad 11). The portion adjacent to the outside of the recess 18 (third surface portion 54c) is rough. The entire inner surface of the recess 18 is rough. The portion located between the recess 18 and the metal layer 25 (fourth surface portion 54d) is smooth.

[0339] In this embodiment, the definitions and measurement methods of "rough surface" and "smooth surface" are the same as in the second embodiment.

[0340] (Manufacturing method for lead frames) Next, the manufacturing method of the lead frame 10C shown in Figure 46 will be explained using Figures 48(a)-(j). In Figures 48(a)-(j), the same reference numerals are used for parts that are the same as those shown in Figure 35(a)-(j), and detailed explanations are omitted.

[0341] First, a metal substrate 31 is prepared in substantially the same manner as the process shown in Figures 35(a) and (b) above (Figure 48(a)), and photosensitive resists 32a and 33a are formed on the front and back surfaces of the metal substrate 31, respectively (Figure 48(b)).

[0342] Next, etching resist layers 32 and 33 having openings 32b and 33b are formed in substantially the same manner as the process shown in Figure 35(c) above (Figure 48(c)). At this time, an opening 32b is also formed in the region corresponding to the recess 18.

[0343] Next, the metal substrate 31 is etched in substantially the same manner as the process shown in Figure 35(d) above to form the outer shapes of the die pad 11, lead portion 12, and connecting bar 13 (Figure 48(d)). At this time, a recess 18 is formed on the surface of the lead portion 12. Then, the etching resist layers 32 and 33 are peeled off in substantially the same manner as the process shown in Figure 35(e) above (Figure 48(e)).

[0344] Next, a plating layer 36 is formed around the entire circumference of the metal substrate 31 in substantially the same manner as the process shown in Figure 35(f) above (Figure 48(f)). At this time, a plating layer 36 is also formed inside the recess 18.

[0345] Next, the portion of the plating layer 36 corresponding to the first die pad side surface 11c, the second die pad side surface 11d, the third surface portion 54c, the recess 18, the inner lead tip surface 51c, and the inner lead back surface 51b of the metal substrate 31 is removed (Figure 48(g)).

[0346] During this time, as shown in Figure 48(g), elastic members 46 such as rubber gaskets are first placed on the front and back surfaces of the metal substrate 31, and the metal substrate 31 is sandwiched by the jig 47F via the elastic members 46. The elastic member 46 on the front surface side of the metal substrate 31 covers the die pad surface 11a, the area corresponding to the fourth surface portion 54d, and the area where the metal layer 25 of the lead portion 12 is provided. Next, the plating layer 36 in the parts not covered by the elastic member 46 is peeled off. As a result, the first die pad side surface 11c, the second die pad side surface 11d, the third surface portion 54c, the recess 18, the inner lead tip surface 51c, and the inner lead back surface 51b are exposed. On the other hand, the plating layer 36 on the die pad surface 11a, the die pad back surface 11b, the fourth surface portion 54d, and the external terminal 17, which are covered by the elastic member 46, remain.

[0347] Next, a support layer 37 is provided on the back side of the metal substrate 31 in substantially the same manner as the process shown in Figure 35(h) above. Then, the portion of the metal substrate 31 not covered by the plating layer 36 is roughened to form a rough surface on the portion not covered by the plating layer 36 (Figure 48(h)). As a result, the first die pad side surface 11c, the second die pad side surface 11d, the third surface portion 54c, the inner surface of the recess 18, the inner lead tip surface 51c, and the back surface 51b of the inner lead become rough surfaces.

[0348] Next, the support layer 37 and the plating layer 36 are sequentially peeled off in substantially the same manner as shown in Figure 35(i) (Figure 48(i)).

[0349] Subsequently, a metal layer 25 is formed on the die pad 11 and lead portion 12 in substantially the same manner as the process shown in Figure 35(j) above. In this way, the lead frame 10C shown in Figure 46 is obtained (Figure 48(j)).

[0350] (Method of manufacturing semiconductor devices) The method for manufacturing the semiconductor device 20C according to this embodiment can be carried out in substantially the same manner as the method for manufacturing the semiconductor device 20 shown in Figures 36(a)-(d).

[0351] According to this embodiment, the fourth surface portion 54d of the lead portion 12 adjacent to the outside of the metal layer 25 is a smooth surface. This makes it possible to suppress the flow of tin and other materials contained in the bump 26 along the fourth surface portion 54d when mounting the semiconductor element 21 on the die pad 11 (arrow F in Figure 49). C (See reference). On the other hand, if the fourth surface portion 54d is rough, there is a risk that tin and other materials contained in the bump 26 may flow out along the fourth surface portion 54d due to surface tension.

[0352] Furthermore, according to this embodiment, a recess 18 is formed on the surface of the lead portion 12, outside the metal layer 25. As a result, even if tin or the like contained in the bump 26 flows out along the fourth surface portion 54d, the flowing tin or the like can be caught by the recess 18. This prevents the flowing tin or the like from reaching the third surface portion 54c.

[0353] Furthermore, according to this embodiment, the inner surface of the recess 18 and the third surface portion 54c are rough surfaces. As a result, the distance of the moisture intrusion path at the interface between the surface of the lead portion 12 and the sealing resin 23 is increased. This makes it possible to suppress the intrusion of moisture from the interface between the surface of the lead portion 12 and the sealing resin 23 to the semiconductor element 21 side (arrow F in Figure 49). B (See reference). As a result, the reliability of the semiconductor device 20C after long-term use can be improved.

[0354] Furthermore, according to this embodiment, the inner surface of the recess 18 and the third surface portion 54c are rough surfaces. This increases the adhesion strength between the recess 18 and the third surface portion 54c and the sealing resin 23, and suppresses the peeling of the surface of the lead portion 12 and the sealing resin 23 from each other.

[0355] Furthermore, according to this embodiment, on the back side of the semiconductor device 20C, the distance of the moisture intrusion path at the interface between the sealing resin 23 and the die pad 11 or lead portion 12 is increased. This makes it possible to suppress moisture from entering the semiconductor element 21 side from the interface between the sealing resin 23 and the die pad 11 or lead portion 12 (arrow F in Figure 49). A (See reference). As a result, the reliability of the semiconductor device 20C after long-term use can be improved.

[0356] (Ninth embodiment) The ninth embodiment will be described with reference to Figures 50 to 57. Figures 50 to 57 show the ninth embodiment. In Figures 50 to 57, the same reference numerals are used for parts that are the same as those in the embodiments shown in Figures 8 to 49, and detailed descriptions are omitted.

[0357] (Lead frame configuration) First, the outline of the lead frame according to this embodiment will be described with reference to Figures 50 and 51. Figures 50 and 51 are diagrams showing the lead frame according to this embodiment.

[0358] As shown in Figures 50 and 51, each package region 10a of the lead frame 10 comprises a die pad 11 and lead portions 12 located around the die pad 11. Of these, a portion of the lead portion 12 is thinned from the back side. The thinned portion of the back surface of the lead portion 12 is rough. The portion of the back surface of the lead portion 12 that is not thinned is smooth.

[0359] As shown in Figure 51, the die pad 11 has a die pad surface 11a located on the front side and a die pad back surface 11b located on the back side. A semiconductor element 21 is mounted on the die pad surface 11a, as will be described later. The die pad back surface 11b is exposed outward from the semiconductor device 20 (described later). In addition, a die pad side surface 11h is formed on the side of the die pad 11 facing the lead portion 12. The die pad side surface 11h extends in the thickness direction (Z direction) from the die pad surface 11a side to the die pad back surface 11b side. In this case, the die pad side surface 11h is rough. That is, a third rough surface R3 is formed on the die pad side surface 11h. On the other hand, the die pad back surface 11b is a smooth surface.

[0360] In this embodiment, "rough surface" refers to a surface with an S-ratio of 1.10 or higher. "Smooth surface" refers to a surface with an S-ratio of less than 1.10. A rough surface is rougher than a smooth surface. Furthermore, it is preferable that the S-ratio of a "rough surface" be between 1.10 and 2.30. It is preferable that the S-ratio of a "smooth surface" be between 1.00 and less than 1.10. Here, "S-ratio" represents the surface area ratio obtained by dividing the surface to be measured into multiple pixels using an optical interferometer and measuring it. Specifically, the surface to be measured is divided into multiple pixels using a VertScan manufactured by Hitachi High-Tech Science Corporation and measured, and the obtained surface area is divided by the observation area to calculate the S-ratio.

[0361] A rough surface may be formed by roughening the outer surface of the metal substrate 31, as described later, for example, with a micro-etching solution. Examples of such micro-etching solutions include those mainly composed of sulfuric acid or hydrochloric acid (for example, the first micro-etching solution described later). Alternatively, a micro-etching solution mainly composed of hydrogen peroxide and sulfuric acid (for example, the second micro-etching solution described later) may be used. A smooth surface may be an unprocessed surface of the metal substrate 31, which has not undergone such roughening treatment. In Figure 51, a rough surface with relatively smooth roughness (for example, the first rough surface R1 described later) is shown with a thin dashed line. Also in Figure 51, a rough surface with relatively coarse roughness (for example, the second rough surface R2, the third rough surface R3, the fourth rough surface R4, and the fifth rough surface R5 described later) is shown with a thick dashed line (the same applies to other cross-sectional views).

[0362] The die pad surface 11a of the die pad 11 is an area (internal terminal) that is joined to the semiconductor element 21 via an adhesive 24 such as die attach paste, as will be described later. The die pad surface 11a may be an area that has not been thinned by half etching or the like. In addition, a first rough surface R1 is formed on the die pad surface 11a. Here, the roughness of the first rough surface R1 is smoother (not rougher) than the roughness of the second rough surface R2 of the lead portion 12, which will be described later. Specifically, the S-ratio of the first rough surface R1 may be 1.10 or more and less than 1.30.

[0363] In this embodiment, the first rough surface R1 is formed over the entire surface of the die pad 11a. However, it is not limited to this, and the first rough surface R1 may be formed on only a part of the die pad surface 11a. In particular, it is preferable that the first rough surface R1 is formed on the outer periphery of the mounting area of ​​the semiconductor element 21 on the die pad surface 11a. This suppresses the phenomenon of components such as epoxy resin in the adhesive 24 seeping out due to capillary action on the die pad surface 11a (bleed-out), as will be described later. Alternatively, the first rough surface R1 may be formed along the entire periphery of the die pad 11. If the first rough surface R1 is formed on only a part of the die pad surface 11a, the parts other than the first rough surface R1 may be smooth. Or, the parts of the die pad surface 11a other than the first rough surface R1 may be rougher than the roughness of the first rough surface R1. For example, the S-ratio of the die pad surface 11a other than the first rough surface R1 may be between 1.30 and 2.30.

[0364] Referring to Figure 51, the back surface 11b of the die pad is a smooth surface similar to the metal substrate (metal substrate 31 described later) before processing, without being thinned by, for example, half-etching. The back surface 11b of the die pad is exposed to the outside from the semiconductor device 20 (described later) after the semiconductor device 20 is manufactured.

[0365] Each lead portion 12 is connected to the semiconductor element 21 via a bonding wire 22, as will be described later, and is positioned with a space between it and the die pad 11. The multiple lead portions 12 are spaced apart from each other along the longitudinal direction of the connecting bar 13. Each lead portion 12 extends from the connecting bar 13.

[0366] As shown in Figure 51, the lead portion 12 has an inner lead 51 and a terminal portion 53. The inner lead 51 is located on the inside (die pad 11 side). The terminal portion 53 is located on the outside (connecting bar 13 side). The inner lead 51 extends from the terminal portion 53 towards the die pad 11. An internal terminal is formed on the surface side of the inner lead 51. This internal terminal is a region that is electrically connected to the semiconductor element 21 via a bonding wire 22, as will be described later. A metal layer 25 is provided on the internal terminal to improve adhesion with the bonding wire 22.

[0367] In this embodiment, the thinned portion of the back surface of the lead portion 12 is roughened. Specifically, the inner lead 51 of the lead portion 12 is thinned from the back side. The entire surface of the inner lead back surface 51b, located on the back side of the inner lead 51, is roughened. That is, a fourth rough surface R4 is formed on the inner lead back surface 51b. On the other hand, the portion of the back surface of the lead portion 12 that is not thinned is smoothened. Specifically, the terminal portion 53 of the lead portion 12 is not thinned from the back side. The entire surface of the external terminal 17, located on the back side of the terminal portion 53, is smoothened.

[0368] Furthermore, the entire tip surface 51c of the inner lead of the lead portion 12 is roughened. That is, a fifth rough surface R5 is formed on the tip surface 51c of the inner lead. Although not shown in the figures, both sides along the longitudinal direction of the lead portion 12 may also be roughened. On the other hand, the inner lead 51 of the lead portion 12 is not thinned from the surface side. Also, the terminal portion 53 of the lead portion 12 is not thinned from the surface side.

[0369] The lead surface 12a is formed by the inner lead surface 51a of the inner lead 51 and the terminal surface 53a of the terminal portion 53. The lead surface 12a is a region that has not been thinned from the surface side by half etching or the like. The lead surface 12a has a smooth surface region S, which is a smooth surface region, and a second rough surface R2, which is a rough surface region.

[0370] The smooth surface region S is located at the inner (die pad 11 side) end of the lead portion 12. A metal layer 25 is formed on the smooth surface region S. In this case, the metal layer 25 covers the entire smooth surface region S in a plan view. The metal layer 25 may be a plating layer formed by, for example, electroplating. The thickness of the metal layer 25 may be 1 μm or more and 10 μm or less. As the metal constituting such a plating layer, silver, silver alloy, gold, gold alloy, platinum group metals, copper, copper alloy, palladium, etc. may be used. Depending on the metal constituting the metal layer 25, if an undercoat plating is required, known materials such as nickel or copper may be applied.

[0371] In this case, one smooth surface region S is formed on the lead surface 12a of each lead portion 12. However, this is not limited to this, and multiple smooth surface regions S may be formed on the lead surface 12a of each lead portion 12. Furthermore, no smooth surface regions S are formed on the lead surface 12a of each lead portion 12. That is, the entire lead surface 12a of each lead portion 12 may be a second rough surface R2.

[0372] A second rough surface R2 is located outside the smooth surface region S and the metal layer 25 (on the connecting bar 13 side). In this case, the second rough surface R2 is provided only outside the smooth surface region S (on the connecting bar 13 side). However, it is not limited to this, and the second rough surface R2 may be provided so as to surround the smooth surface region S in a plan view. The lead surface 12a may consist only of the smooth surface region S and the second rough surface R2.

[0373] In this embodiment, the roughness of the second rough surface R2 is rougher than the roughness of the first rough surface R1 of the die pad 11 described above. Specifically, the S-ratio of the second rough surface R2 may be 1.30 or more and 2.30 or less. On the other hand, as described above, the S-ratio of the first rough surface R1 may be 1.10 or more and less than 1.30.

[0374] The roughness of the third rough surface R3 of the die pad 11 described above may be rougher than the roughness of the first rough surface R1. The S-ratio of the third rough surface R3 may be between 1.30 and 2.30. Also, the roughness of the fourth rough surface R4 of the lead portion 12 may be rougher than the roughness of the first rough surface R1 described above. The S-ratio of the fourth rough surface R4 may be between 1.30 and 2.30. Also, the roughness of the fifth rough surface R5 of the lead portion 12 may be rougher than the roughness of the first rough surface R1 described above. The S-ratio of the fifth rough surface R5 may be between 1.30 and 2.30.

[0375] The relative sizes of the second, third, fourth, and fifth rough surfaces R2, R3, R4, and R5 are not considered. The roughness of the second, third, fourth, and fifth rough surfaces R2, R3, R4, and R5 may be different from or the same as those of the second and fifth rough surfaces R5.

[0376] In addition, the configuration of the lead frame 10 according to this embodiment may be the same as the configuration of the lead frame 10 according to the second embodiment.

[0377] (Configuration of a semiconductor device) Next, the semiconductor device according to this embodiment will be described with reference to Figures 52 and 53. Figures 52 and 53 show the semiconductor device (QFN type) according to this embodiment.

[0378] As shown in Figures 52 and 53, the semiconductor device (semiconductor package) 20 comprises a die pad 11, a semiconductor element 21, a plurality of lead portions 12, a plurality of bonding wires 22, and a sealing resin 23.

[0379] The semiconductor element 21 is mounted on the die pad 11. Multiple bonding wires 22 electrically connect the semiconductor element 21 to the metal layer 25 of the lead portion 12. In this case, the bonding wires 22 constitute connecting members. The sealing resin 23 encapsulates the die pad 11, the lead portion 12, the semiconductor element 21, and the bonding wires 22.

[0380] The die pad 11 and lead portion 12 are manufactured from the lead frame 10 described above. In this case, a first rough surface R1 is formed on the die pad surface 11a of the die pad 11. A second rough surface R2 is formed on the lead surface 12a of the lead portion 12, at a position outside the metal layer 25 (further from the die pad 11). The roughness of the second rough surface R2 of the lead portion 12 is rougher than the roughness of the first rough surface R1 of the die pad 11.

[0381] Furthermore, a third rough surface R3 is formed on the die pad side surface 11h of the die pad 11. The roughness of the third rough surface R3 is coarser than that of the first rough surface R1. The sealing resin 23 is in close contact with the die pad side surface 11h. The inner lead 51 of the lead portion 12 is thinned from the back side. The back surface 51b of the inner lead 51 is a fourth rough surface R4. The roughness of the fourth rough surface R4 is coarser than that of the first rough surface R1. The sealing resin 23 is in close contact with the back surface 51b of the inner lead. Furthermore, a fifth rough surface R5 is formed on the inner lead tip surface 51c of the inner lead 51. The roughness of the fifth rough surface R5 is coarser than that of the first rough surface R1. The sealing resin 23 is in close contact with the inner lead tip surface 51c. The terminal portion 53 of the lead portion 12 is not thinned from the back side. The external terminal 17, located on the back surface of the terminal portion 53, has a smooth surface. The external terminal 17 is exposed to the outside from the sealing resin 23.

[0382] The semiconductor element 21 can be any type of semiconductor element that is commonly used in the past, and is not particularly limited; for example, integrated circuits, large-scale integrated circuits, transistors, thyristors, diodes, etc., can be used. Each semiconductor element 21 has multiple electrodes 21a to which bonding wires 22 are attached. The semiconductor element 21 is fixed to the surface of the die pad 11 by an adhesive 24, such as die attach paste. The adhesive 24 may be an epoxy resin-based adhesive containing components such as silver paste and epoxy resin.

[0383] Each bonding wire 22 is made of a highly conductive material such as gold or copper. One end of each bonding wire 22 is connected to the electrode 21a of the semiconductor element 21, and the other end is connected to the metal layer 25 located on each lead portion 12. Instead of bonding wires 22, conductive materials such as bumps may be used as connecting members. In this case, the semiconductor element 21 can be connected to the lead portion 12 by flip-chip bonding.

[0384] As the encapsulating resin 23, a thermosetting resin such as silicone resin or epoxy resin, or a thermoplastic resin such as PPS resin can be used. The overall thickness of the encapsulating resin 23 may be approximately 300 μm to 1500 μm. Also, the length of one side of the encapsulating resin 23 (one side of the semiconductor device 20) may be, for example, 0.2 mm to 20 mm. Note that in Figure 52, the portion of the encapsulating resin 23 located on the surface side of the lead portion 12 and the semiconductor element 21 is omitted from the display.

[0385] Furthermore, the configuration of the die pad 11 and lead portion 12 is the same as that shown in Figures 50 and 51 above, except for the areas not included in the semiconductor device 20, so a detailed explanation is omitted here.

[0386] (Manufacturing method for lead frames) Next, the manufacturing method of the lead frame 10 shown in Figures 50 and 51 will be explained using Figures 54(a)-(e) and 55(a)-(h). Figures 54(a)-(e) and 55(a)-(h) are cross-sectional views (corresponding to Figure 51) showing the manufacturing method of the lead frame 10.

[0387] First, a metal substrate 31 having a die pad 11 and lead portions 12 located around the die pad 11 is fabricated in the same manner as in the second embodiment (Figures 14(a)-(e)) (Figure 54(a)-(e)).

[0388] Next, a plating layer (coating layer) 36 is formed around the metal substrate 31 (Figure 55(a)). At this time, the plating layer 36 may be formed on the entire portion of the die pad 11, lead portion 12, and connecting bar 13 that is exposed to the outside. The thickness of the plating layer 36 may be greater than 0 μm and less than or equal to 2 μm. As the metal constituting the plating layer 36, for example, silver may be used. When the plating layer 36 consists of silver plating, a silver plating solution mainly composed of silver cyanide and potassium cyanide can be used as the electrolytic plating solution.

[0389] Next, the plating layer 36 present in the region of the metal substrate 31 that forms the first rough surface R1 is removed. Specifically, the plating layer 36 located over the entire surface 11a of the die pad 11 is removed (Figure 55(b)). In this case, for example, the surface and back surface of the metal substrate 31 other than the die pad surface 11a are sandwiched by a jig via an elastic member. Then, the plating layer 36 in the parts not covered by the elastic member and the jig may be peeled off. This removes the plating layer 36 on the die pad surface 11a.

[0390] Next, the portion of the metal substrate 31 not covered by the plating layer 36 is roughened to form a first rough surface R1 on that portion (Figure 55(c)). Specifically, the first micro-etching solution is supplied to the metal substrate 31 to form a first rough surface R1 on the entire die pad surface 11a not covered by the plating layer 36. Here, the first micro-etching solution is a surface treatment agent that slightly dissolves the metal surface to form a first rough surface R1 with fine irregularities. For example, when roughening a metal substrate 31 made of copper or a copper alloy, a micro-etching solution mainly composed of sulfuric acid or hydrochloric acid may be used as the first micro-etching solution.

[0391] Next, the plating layer 36 present on the metal substrate 31 outside the smooth surface region S (the region where the metal layer 25 is formed) of the lead surface 12a is removed. In this case, for example, the surface and back surface of the metal substrate 31 other than the smooth surface region S are sandwiched by a jig via an elastic member. Then, the plating layer 36 in the parts not covered by the elastic member and the jig may be peeled off. This removes the plating layer 36 located on the back surface 11b and the side surface 11h of the die pad 11. In addition, the plating layer 36 located on the parts of the lead surface 12a other than the smooth surface region S, the back surface 51b of the inner lead, the tip surface 51c of the inner lead, and the external terminal 17 of the lead portion 12 is removed.

[0392] Next, protective layers 37A are provided on the front and back surfaces of the metal substrate 31, respectively (Figure 55(e)). The protective layer 37A may be, for example, a resist layer. The protective layer 37A on the front surface covers the die pad surface 11a of the die pad 11 and the plating layer 36 on the smooth surface region S of the lead portion 12. In this case, the protective layer 37A on the front surface covers the entire area of ​​the first rough surface R1 of the die pad 11. The protective layer 37A on the front surface may also cover part or all of the plating layer 36 on the smooth surface region S. The protective layer 37A on the back surface covers the die pad back surface 11b of the die pad 11 and the external terminals 17 of the lead portion 12.

[0393] Next, the portion of the metal substrate 31 not covered by the plating layer 36 and the protective layer 37A is roughened to form a rough surface on that portion (Figure 55(f)). Specifically, a second rough surface R2 is formed on a part of the lead surface 12a of the lead portion 12. A third rough surface R3 is formed on the die pad side surface 11h of the die pad 11. A fourth rough surface R4 is formed on the back surface 51b of the inner lead of the lead portion 12. Furthermore, a fifth rough surface R5 is formed on the tip surface 51c of the inner lead of the lead portion 12.

[0394] During this time, a second micro-etching solution is supplied to the metal substrate 31. This forms a rough surface on the entire metal substrate 31, except for the parts covered by the plating layer 36 and the protective layer 37A. The second micro-etching solution is a surface treatment agent that slightly dissolves the metal surface and forms a rough surface with fine irregularities. For example, when roughening a metal substrate 31 made of copper or a copper alloy, a micro-etching solution mainly composed of hydrogen peroxide and sulfuric acid may be used as the second micro-etching solution. The second micro-etching solution may contain different components from the first micro-etching solution described above. The second micro-etching solution makes the metal rougher than the first micro-etching solution. Therefore, the second rough surface R2, the third rough surface R3, the fourth rough surface R4, and the fifth rough surface R5 are each rougher than the first rough surface R1.

[0395] Next, the protective layer 37A and the plating layer 36 on the surface side of the metal substrate 31 are peeled off (Figure 55(g)). At this time, the plating layer 36 covering the lead surface 12a is removed, and the smooth surface region S is exposed. The protective layer 37A on the back side remains on the metal substrate 31.

[0396] Subsequently, a metal layer 25 is formed on the smooth surface region S of the lead portion 12 (Figure 55(h)). In this case, first, a plating resist layer of a predetermined pattern (not shown) is formed on the die pad 11 and the lead portion 12, excluding the smooth surface region S, for example by photolithography. Next, a metal layer 25 consisting of a plating layer is formed on the smooth surface region S not covered by the plating resist layer, for example by electroplating. After that, the lead frame 10 shown in Figures 50 and 51 is obtained by removing the plating resist layer.

[0397] (Method of manufacturing semiconductor devices) Next, the manufacturing method of the semiconductor device 20 shown in Figures 52 and 53 will be explained using Figures 56(a)-(e). Figures 56(a)-(e) are cross-sectional views (corresponding to Figure 53) showing the manufacturing method of the semiconductor device 20.

[0398] First, the lead frame 10 is manufactured using the method shown in Figures 54(a)-(e) and 55(a)-(h) (Figure 56(a)).

[0399] Next, the semiconductor element 21 is mounted on the die pad 11 of the lead frame 10. In this case, the semiconductor element 21 is placed and fixed on the die pad 11 using an adhesive 24, such as die attach paste (Figure 56(b)). The adhesive 24 may be an epoxy resin-based adhesive containing components such as silver paste and epoxy resin. At this time, the semiconductor element 21 is positioned on the first rough surface R1 of the die pad surface 11a via the adhesive 24. The first rough surface R1 is located along the outer circumference of the semiconductor element 21 and the adhesive 24.

[0400] Next, each electrode 21a of the semiconductor element 21 and the metal layer 25 formed on each lead portion 12 are electrically connected to each other by bonding wires (connecting members) 22 (Figure 56(c)).

[0401] Next, a encapsulating resin 23 is formed on the lead frame 10 by injection molding or transfer molding of a thermosetting resin or thermoplastic resin (Figure 56(d)). This encapsulates the die pad 11, lead portion 12, semiconductor element 21, and bonding wire 22 with resin.

[0402] Subsequently, the lead frame 10 and sealing resin 23 are cut for each package region 10a. This separates the lead frame 10 for each semiconductor device 20, resulting in the semiconductor devices 20 shown in Figures 52 and 53 (Figure 56(e)).

[0403] Incidentally, while the semiconductor device 20 is being manufactured in this manner, a process of heat-curing the adhesive 24 is carried out (Figure 56(b)). Specifically, an adhesive 24 such as die attach paste is applied to the die pad 11, the semiconductor element 21 is mounted on the die pad 11, and then the adhesive 24 is heat-cured. At this time, there is a risk that components such as epoxy resin in the applied adhesive 24 may seep out due to capillary action on the die pad surface 11a. This phenomenon is also called bleed-out or epoxy bleed-out.

[0404] In contrast, according to this embodiment, a first rough surface R1 is formed on the die pad surface 11a of the die pad 11. The roughness of the first rough surface R1 is lower than that of the second rough surface R2. This suppresses the phenomenon of epoxy resin seeping out of the adhesive 24 due to capillary action caused by the irregularities of the die pad surface 11a (bleed-out) (see arrow E in Figure 57). On the other hand, it is also conceivable to make the die pad surface 11a around the adhesive 24 a smooth surface. However, if the viscosity of the epoxy resin in the adhesive 24 is low, the epoxy resin will actually flow more easily along the smooth surface of the die pad surface 11a. For this reason, in this embodiment, the roughness of the die pad surface 11a is made moderately rough to the extent that capillary action does not occur (referred to as the first rough surface R1). This suppresses the flow of epoxy resin along the die pad surface 11a regardless of the viscosity of the epoxy resin in the adhesive 24.

[0405] Furthermore, if such a semiconductor device 20 is used for a long period of time, moisture from the air may enter the semiconductor device 20 from the side or back side. For example, moisture may enter through the interface between the sealing resin 23 and the die pad 11 or lead portion 12.

[0406] In contrast, according to this embodiment, a second rough surface R2 is formed on the lead surface 12a of the lead portion 12. Therefore, the distance of the moisture intrusion path at the interface between the lead surface 12a and the sealing resin 23 is increased. This prevents moisture from entering the semiconductor element 21 side from the interface between the lead surface 12a and the sealing resin 23 (arrow F in Figure 57).A (See reference). As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

[0407] Furthermore, according to this embodiment, the die pad side surface 11h of the die pad 11 is a third rough surface R3. The roughness of the third rough surface R3 is rougher than the roughness of the first rough surface R1. As a result, the distance of the moisture intrusion path at the interface between the sealing resin 23 and the die pad 11 on the back side of the semiconductor device 20 is increased. This makes it possible to suppress the intrusion of moisture from the interface between the sealing resin 23 and the die pad 11 to the semiconductor element 21 side (arrow F in Figure 57). B (See reference). As a result, the reliability of the semiconductor device 20 after long-term use can be improved. Furthermore, the adhesion strength between the die pad 11 and the sealing resin 23 can be increased, and delamination between the die pad 11 and the sealing resin 23 can be suppressed.

[0408] Furthermore, according to this embodiment, the back surface 51b of the inner lead of the lead portion 12 is a fourth rough surface R4. In addition, the tip surface 51c of the inner lead of the lead portion 12 is a fifth rough surface R5. The roughness of the fourth rough surface R4 and the fifth rough surface R5 are both rougher than the roughness of the first rough surface R1. As a result, the distance of the moisture intrusion path at the interface between the sealing resin 23 and the lead portion 12 on the back side of the semiconductor device 20 is increased. This makes it possible to suppress the intrusion of moisture from the interface between the sealing resin 23 and the lead portion 12 to the semiconductor element 21 side (arrow F in Figure 57). c (See reference). As a result, the reliability of the semiconductor device 20 after long-term use can be improved. Furthermore, the adhesion strength between the lead portion 12 and the sealing resin 23 can be increased, and the separation of the lead portion 12 and the sealing resin 23 from each other can be suppressed.

[0409] (modified version) Next, a modified example of the lead frame 10 according to this embodiment will be described with reference to Figure 58. Figure 58 is a cross-sectional view showing the modified lead frame 10. In Figure 58, the same reference numerals are used for parts that are the same as those shown in Figures 50 to 57, and detailed descriptions are omitted.

[0410] In Figure 58, the lead surface 12a of the lead portion 12 has a smooth surface region S and a second rough surface R2. In this case, the smooth surface region S does not have a metal layer 25. Therefore, the smooth surface region S is exposed to the outside of the lead frame 10.

[0411] When manufacturing the lead frame 10 shown in Figure 58, after performing the steps shown in Figures 54(a)-(e) and 55(a)-(g) described above, the step of forming the metal layer 25 (Figure 55(h)) is omitted. This results in the lead frame 10 shown in Figure 58.

[0412] In this way, by not providing a metal layer 25 in the smooth surface region S, the manufacturing process of the lead frame 10 can be reduced. Furthermore, by not providing a metal layer 25 consisting of a plating layer of silver, silver alloy, gold, gold alloy, platinum group metals, copper, copper alloy, palladium, etc., the manufacturing cost of the lead frame 10 can be reduced. Moreover, this is more effective when the semiconductor element 21 is connected to the lead portion 12 by flip-chip bonding rather than by wire bonding.

[0413] The multiple components disclosed in each of the above embodiments and modifications can be combined as needed. Alternatively, some components may be removed from all the components shown in each of the above embodiments and modifications.

Claims

1. A die pad on which a semiconductor element is mounted, The die pad comprises a lead portion located around the die pad, A first rough surface is formed on at least a portion of the surface of the die pad. A third rough surface is formed on the side surface of the die pad. A lead frame wherein the roughness value of the third rough surface of the die pad, based on the S-ratio, is rougher than the roughness value of the first rough surface of the die pad, based on the S-ratio.

2. A die pad on which a semiconductor element is mounted, The die pad comprises a lead portion located around the die pad, A first rough surface is formed on at least a portion of the surface of the die pad. The lead portion has an inner lead that is thinned from the back side, The inner lead back surface is formed on the back side of the inner lead. A fourth rough surface is formed on the back surface of the inner lead. A lead frame in which the roughness value of the fourth rough surface of the lead portion, based on the S-ratio, is rougher than the roughness value of the first rough surface of the die pad, based on the S-ratio.

3. A die pad on which a semiconductor element is mounted, The die pad comprises a lead portion located around the die pad, A first rough surface is formed on at least a portion of the surface of the die pad. The lead portion has an inner lead that is thinned from the back side, The inner lead tip surface is formed on the side of the inner lead facing the die pad. A fifth rough surface is formed on the tip surface of the inner lead. A lead frame in which the roughness value of the fifth rough surface of the lead portion, based on the S-ratio, is rougher than the roughness value of the first rough surface of the die pad, based on the S-ratio.

4. The lead frame according to any one of claims 1 to 3, wherein the S-ratio of the first rough surface is 1.10 or more and less than 1.

30.

5. The lead frame according to claim 1, wherein the S-ratio of the third rough surface is 1.30 or more and 2.30 or less.

6. The lead frame according to claim 2, wherein the S-ratio of the fourth rough surface is 1.30 or more and 2.30 or less.

7. The lead frame according to claim 3, wherein the S-ratio of the fifth rough surface is 1.30 or more and 2.30 or less.

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