Stable low-power analog-to-digital converter reference voltage

Abstract

A conversion circuit for performing analog-to-digital conversion is described. In operation, the conversion circuit receives an input signal. The conversion circuit then performs the analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power supply voltage and a second power supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal with the first power supply voltage and the second power supply voltage. Also, the first power supply voltage and the second power supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with a reference voltage other than the first power supply voltage and the second power supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range is equal to the second full-scale range.

Description

Technical Field

[0001] The present disclosure relates to a conversion circuit such as an analog-to-digital converter (ADC). In particular, the present disclosure uses the power supply voltage as a reference voltage and uses the ratio of the full-scale range corresponding to the power supply voltage to a second full-scale range related to a reference voltage other than or different from the power supply voltage to increase the number of quantization bits and / or scale the quantization output of the conversion circuit, thereby maintaining the resolution of the conversion circuit.

Background Art

[0002] An ADC is a circuit component widely used to convert an analog signal into a quantized or digital representation. Usually, an ADC performs this conversion based at least on a reference voltage.

[0003] For example, as shown in FIG. 1 presenting an existing conversion circuit, a full-scale reference generation circuit can provide reference voltages VREF_P and VREF_M to an N-bit ADC. The reference voltages can define the full-scale range of the N-bit ADC. Also, the N-bit ADC can provide a quantized output, N-bit Dout, corresponding to the analog input signal based at least in part on the reference voltage. In particular, the N-bit ADC can compare the input signal with the reference voltage when determining the quantized output.

[0004] Due to switching noise in the N-bit ADC, the reference voltages provided by the full-scale reference generation circuit are typically buffered. In some conversion circuits, large bypass capacitors are used to help stabilize the buffered reference voltages and reduce noise.

[0005] However, using multiple large capacitors in conversion circuits, such as in a multi-unit interleaved array of an ADC, is often problematic. In particular, large capacitors typically occupy a large area on a semiconductor die or integrated circuit. Furthermore, the conversion speed of the conversion circuit can be negatively affected if extra redundant bits are added in the conversion process, for example, due to imperfect settling of the reference voltage or errors introduced due to noise.

[0006] Furthermore, reference voltage generation and buffer circuits typically consume significant power in switched-capacitor data conversion circuits (such as successive approximation registers or SAR ADCs), and are a potential source of noise and settling errors. Generally, the settling time and noise of a conversion circuit are inversely proportional to the bias current or power. In particular, a higher bias current results in lower impedance, less noise, and faster settling time.

[0007] In addition, a lower reference voltage is generally desirable for detecting small amplitude input signals, but a lower reference voltage often increases the resistance of the feedback switch typically used in capacitive feedback ADCs. This is because a lower reference voltage usually requires a switch voltage near the middle of the power supply range, which reduces the amount of switch overdrive voltage. [Overview of the project] [Means for solving the problem]

[0008] An embodiment of an integrated circuit is described. This integrated circuit includes a conversion circuit. During operation, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to an input signal, at least partially based on a first supply voltage and a second supply voltage of the integrated circuit.

[0009] It should be noted that the quantized output may be at least partially based on a comparison between the input signal and the first and second power supply voltages.

[0010] Furthermore, the first and second power supply voltages can specify the full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range related to a reference voltage other than the first and second power supply voltages, the quantized output may accommodate a larger number of bits than when the full-scale range is equal to the second full-scale range. Alternatively, or in addition, there may be extra bits for redundancy used to correct errors in the analog-to-digital conversion (e.g., for settling errors). Furthermore, when the full-scale range exceeds the second full-scale range, the conversion circuit can scale the quantized output at least partially based on the ratio of the full-scale range to the second full-scale range. In some embodiments, the conversion circuit includes a set of interleaved unit ADCs. It should be noted that the conversion circuit can compensate for differences in the quantized outputs of the set of unit ADCs, and this compensation may include adjusting the ratio of at least one of the unit ADCs.

[0011] Furthermore, the first power supply voltage may include a positive power supply voltage, and the second power supply voltage may include a negative power supply voltage or ground.

[0012] In addition, the conversion circuit may include a SAR ADC or a pipelined ADC.

[0013] Another embodiment provides an electronic device including a conversion circuit.

[0014] Another embodiment provides a system including a conversion circuit.

[0015] Another embodiment provides a method for performing analog-to-digital conversion. This method includes at least some of the operations performed by a conversion circuit.

[0016] This summary is provided for the purpose of illustrating some exemplary embodiments in order to provide a basic understanding of some aspects of the subject matter described herein. It will be understood that the features described above are illustrative and should not be construed in any way as narrowing the scope or spirit of the subject matter described herein. Other features, aspects, and advantages of the subject matter described herein will become apparent from the following detailed description, drawings, and claims. [Brief explanation of the drawing]

[0017] [Figure 1] This is a block diagram showing an example of an existing conversion circuit. [Figure 2] This block diagram shows an example of a conversion circuit according to some embodiments of the present disclosure. [Figure 3] This figure shows an example of scaling the quantized output from the conversion circuit in an embodiment of the present disclosure. [Figure 4] This block diagram shows an example of a conversion circuit according to some embodiments of the present disclosure. [Figure 5] This flowchart illustrates an example of a method for performing analog-to-digital conversion according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0018] Note that similar reference numbers refer to the corresponding parts throughout the drawing. Furthermore, multiple examples of the same part are designated by a common prefix separated by a dash from the example number.

[0019] This describes an integrated circuit. This integrated circuit includes a conversion circuit that performs analog-to-digital conversion of an input signal. For example, the conversion circuit may include a SAR ADC. In particular, the conversion circuit provides a quantized output corresponding to an input signal, at least in part on a first supply voltage and a second supply voltage of the integrated circuit, where the first and second supply voltages specify the full-scale range of the conversion circuit. The first supply voltage includes a positive supply voltage, and the second supply voltage includes a negative supply voltage or ground. Furthermore, when the full-scale range exceeds a second full-scale range related to a reference voltage other than the first and second supply voltages, the quantized output may accommodate a larger number of bits than when the full-scale range is equal to the second full-scale range. Alternatively, or in addition, when the full-scale range exceeds the second full-scale range, the conversion circuit scales the quantized output based at least in part on the ratio of the full-scale range to the second full-scale range.

[0020] By performing analog-to-digital conversion based at least partially on the power supply voltage, these circuit techniques can reduce or eliminate the need for buffer circuits, bias current, and / or large bypass capacitors. Furthermore, the conversion techniques can reduce noise, decrease the area on the semiconductor die, reduce power consumption, and / or increase the speed of the conversion circuit or decrease the settling time. Consequently, the circuit techniques can improve the performance of the ADC. One or more of these capabilities can enable the use of conversion circuit and / or ADC embodiments in a wide variety of systems, electronic devices, and applications.

[0021] Note that in this disclosure, "full scale" is sometimes referred to as "gain." Full scale can provide or specify a quantized output level based on the analog input level.

[0022] Next, embodiments of circuit technology and conversion circuits will be described. As shown in FIG. 2 presenting an example of the conversion circuit 200 in an embodiment of the present disclosure, a quantizer 210 can provide at least an N-bit quantization output 212 corresponding to an input signal based at least in part on a first power supply voltage 214 and a second power supply voltage 216 of an integrated circuit including the conversion circuit 200. The first power supply voltage 214 and the second power supply voltage 216 can define the full scale or dynamic range of the conversion circuit 200. Also, the first power supply voltage 214 can include a single-polarity power supply voltage (e.g., a positive power supply voltage VDD, etc.), and the second power supply voltage 216 can include a ground (VSS). Note that the first power supply voltage 214 and the second power supply voltage 216 can be very stable. FIG. 2 shows a single-ended embodiment of the conversion technology, but in other embodiments, the conversion circuit 200 can be differential. In these embodiments, the second power supply voltage 216 can also be single-polarity and can have a polarity opposite to that of the first power supply voltage 214 (e.g., a negative power supply voltage, etc.).

[0023] Furthermore, when the full scale range exceeds a second full scale range of the conversion circuit 200 related to a reference voltage other than the first power supply voltage 214 and the second power supply voltage 216, the quantization output 212 can correspond to a larger number of bits than when the full scale range is equal to the second full scale range. For example, if the first full scale range is 1V and the second full scale range is 0.5V, one additional bit may be required to resolve a larger related dynamic range.

[0024] As a result, as shown in FIG. 2, the quantizer 210 can provide m additional bits to the quantization output 212 such that the quantization output 212 corresponds to a total of N + m bits. For example, in a 12-bit ADC, m can be 1, so the total number of bits is 13. By using the additional m bits, the conversion circuit 200 can maintain the resolution of the conversion circuit 200 even when the full-scale range of the conversion circuit 200 is increased, in part, by using the first power supply voltage 214 and the second power supply voltage 216.

[0025] Alternatively, or in addition, when the full-scale range exceeds a second full-scale range, the conversion circuit 200 can scale the quantization output 212 based at least in part on the ratio of the full-scale range to the second full-scale range. This is shown in FIG. 3, which presents an example of scaling the quantization (or digitization) output of the conversion circuit 200 in an embodiment of the present disclosure. In particular, as previously discussed, the reference voltages VREF_P310 and VREF_M312 can define the second full-scale range of the N-bit ADC. In an embodiment of the conversion circuit 200 in which the first power supply voltage 214 and the second power supply voltage 216 are used as reference voltages for the conversion circuit 200, the quantization output 212 can be scaled (e.g., multiplied) by the ratio of the full-scale range (or power range) to the second full-scale range. Thereby, the quantization output 212 can be increased such that the quantization output 212 spans the full-scale range of the conversion circuit 200.

[0026] In some embodiments, the quantized output 212 of the conversion circuit 200 may correspond to an additional r redundant bits that can be used, for example, for error correction. For example, a 13-bit ADC may include an additional 2 redundant bits. This is shown in Figure 4, which presents an example of a conversion circuit 400 in embodiments of the present disclosure. In Figure 4, a redundant bit decoder 414 can use an additional r redundant bits after the quantizer 410 to correct errors in the quantized output 412, such as noise-related errors. In addition, a multiplier 418 can multiply the quantized output 416 from the decoder 414 by 2m (or bit-shift and truncate), so that the quantized output 420 provided by the conversion circuit 400 corresponds to N bits. This allows the 13-bit quantized output to be converted back to a 12-bit quantized output.

[0027] For example, in some embodiments, 2 bits of redundancy (r) in the digital conversion can be used to help suppress the effects of power supply noise. Thus, in some embodiments, the quantizer 410 can perform N+m+r bit quantization. After conversion, the redundancy can be decoded to recover the original data word size. In particular, the quantized output 416 from the redundancy bit decoder 414 can contain N+m bits. In addition, the multiplier 418 can multiply the quantized output 416 (i.e., the digital word) by 2m to recover a second full-scale range related to reference voltages other than the power supply voltages 214 and 216 (for example, when m is equal to 1, bit shifts and truncations can be performed corresponding to a coefficient of 2). Thus, the quantized output 420 can contain N bits. When m is equal to 1 in this example, more generally, the m used by the conversion circuit 400 can be programmable or dynamic. Thus, the conversion circuit 200 (Figure 2) or 400 can be dynamically adapted by the control logic 218 (Figure 2) or 422.

[0028] In some embodiments, the conversion technique can be used with an interleaved ADC. However, there may be variations in the full-scale range of different unit ADCs in an interleaved ADC. For example, the full-scale range of a given unit ADC may vary from that of other unit ADCs due to process variations, temperature, and / or transistor mismatches. In these embodiments, the mismatch can be compensated for by adjusting the ratio used to scale the quantized output of a given unit ADC or conversion circuit (relative to the ratio used in at least some of the other unit ADCs). Note that the adjustment can be determined by taking the average of the quantized outputs of the unit ADCs in an interleaved ADC with a large input signal. In principle, the quantized outputs in this case should be the same. Consequently, the variation in the average of the quantized outputs can be used to calculate the adjustment for the ratio used to scale the quantized output of a given unit ADC.

[0029] Referring back to Figure 2, in some embodiments, the conversion circuit 200 can add bits to the resolution of the quantizer 210. This may allow the use of a larger full-scale range (such as when the reference voltages of the conversion circuit 200 are power supply voltages 214 and 216) without sacrificing resolution. Note that a larger full-scale range allows for a reduction in switch resistance because the gate overdrive voltage of the switch increases. However, the use of additional bits may increase the conversion time of the conversion circuit 200.

[0030] If the allowable full-scale range is sufficiently large, the first reference voltage 214 can be the positive supply voltage (VDD), and the second reference voltage 216 can be ground (VSS) instead of the usual reference voltages VREF_P310 (Figure 3) and VREF_M312 (Figure 3). This eliminates the standby bias current. Also, since the supply voltage and ground voltage typically have very low impedance, the reference voltage settling time of the conversion circuit 200 can be reduced or minimized. As a result, this modification eliminates the need for an analog calibration feedback circuit in the conversion circuit 200.

[0031] Furthermore, in interleaved ADCs where gain matching across an array may be required, the quantized output from each interleaved unit ADC can be passed to a digital block or control logic for post-processing correction. In this control logic, the gain error of the unit ADC can be detected by averaging the quantized output or quantized output power. The gain can then be corrected by adjusting the ratio or multiplication coefficient used by the unit ADC. Note that least-squares mean or another coefficient adjustment technique may be used.

[0032] In some embodiments, additional power supply bypass capacitors can be used to help reduce power supply noise. Alternatively, or in addition, Kelvin taps on the power supply connections can be used to provide some resistance isolation between interleaved unit ADCs using the same power supply reference.

[0033] While previous discussions have used SAR ADCs as an example, the disclosed conversion technology can be used with other types of ADCs, such as other types of interleaved ADCs or pipelined ADCs.

[0034] In this discussion, the analog-to-digital conversion performed by the conversion circuit can be applied to a wide variety of input signals. For example, the input signal may include a frame. This frame may include an image, and one or more ADCs in the conversion circuit may receive analog inputs corresponding to different spatial locations or regions. Alternatively, in some embodiments, for example in a scanning system, frames may be gradually captured over time intervals (e.g., several milliseconds). Thus, in these embodiments, one or more ADCs may receive analog inputs corresponding to different spatial locations or regions captured at different times.

[0035] Next, embodiments of the method will be described. Figure 5 shows a flowchart illustrating an example of method 500 for performing analog-to-digital conversion using a conversion circuit such as conversion circuit 200 (Figure 2) or 400 (Figure 4). During operation, the conversion circuit can receive an input signal (operation 510). The conversion circuit can then perform analog-to-digital conversion and provide a quantized output corresponding to the input signal, at least partially based on the first and second power supply voltages of the conversion circuit (operation 512).

[0036] In some embodiments of Method 500, there may be additional or fewer operations. For example, after analog-to-digital conversion (operation 512), the quantized output may be scaled (operation 514). Also, the order of operations can be changed, and / or two or more operations can be combined into a single operation.

[0037] The disclosed conversion circuits and circuit technologies may be (or be included in) any electronic device. For example, an electronic device may include a mobile phone or smartphone, a tablet computer, a laptop computer, a notebook computer, a personal or desktop computer, a netbook computer, a media player device, an ebook device, a MiFi® device, a smartwatch, a wearable computing device, a portable computing device, a home electronic device, an access point, a router, a switch, communication equipment, testing equipment, a vehicle, a ship, an airplane, an automobile, a truck, a bus, a motorcycle, manufacturing equipment, agricultural equipment, construction equipment, or another type of electronic device.

[0038] While specific components are used to describe embodiments of a conversion circuit and / or an integrated circuit including a conversion circuit, in alternative embodiments, different components and / or subsystems may exist in the conversion circuit, the integrated circuit including the conversion circuit, and / or one or more ADCs. Thus, embodiments of a conversion circuit, an integrated circuit including a conversion circuit, and / or one or more ADCs may include fewer components, additional components, different components, two or more components may be combined into a single component, a single component may be separated into two or more components, one or more components may be repositioned, and / or different types of components may be present.

[0039] Furthermore, the circuits and components in the conversion circuit, the integrated circuit including the conversion circuit, and / or one or more embodiments of the ADC can be implemented using any combination of analog and / or digital circuits, including bipolar, PMOS and / or NMOS gates or transistors. In addition, the signals in these embodiments can include digital signals with approximately discrete values ​​and / or analog signals with continuous values. Moreover, the components and circuits may be single-ended or differential, and the power supply may be unipolar or bipolar. It should be noted that the electrical coupling or connection in the prior embodiments may be direct or indirect. In the prior embodiments, a single line corresponding to one route may represent one or more single lines or routes.

[0040] As mentioned earlier, integrated circuits can implement some or all of the functionality of circuit technology. This integrated circuit may include hardware and / or software mechanisms used to implement the functionality related to circuit technology.

[0041] In some embodiments, the output of a process for designing an integrated circuit, or a part of an integrated circuit, that includes one or more of the circuits described herein, may be on a computer-readable medium such as magnetic tape or optical or magnetic disk. The computer-readable medium may be encoded with data structures or other information describing circuits that can be physically instantiated as part of an integrated circuit or as part of an integrated circuit. Various formats may be used for such encoding, but these data structures are generally described in Caltech Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), Electronic Design Interchange Format (EDIF), OpenAccess (OA), or Open Artwork System Interchange Standard (OASIS). Persons skilled in the art of integrated circuit design may develop such data structures from the types of schematic diagrams and corresponding descriptions detailed above and encode the data structures on a computer-readable medium. Persons skilled in the art of integrated circuit manufacturing may use such encoded data to manufacture an integrated circuit that includes one or more of the circuits described herein.

[0042] While some of the operations in the prior embodiments were implemented in hardware or software, the operations in the prior embodiments can generally be implemented in a wide variety of configurations and architectures. Therefore, some or all of the operations in the prior embodiments can be performed in hardware, software, or both. For example, at least some of the operations in circuit technology can be implemented using program instructions executed by a processor in an integrated circuit or in firmware.

[0043] Furthermore, while numerical examples are provided in the preceding discussion, different numerical values ​​will be used in other embodiments. Consequently, the numerical values ​​provided are not intended to be limiting.

[0044] In the preceding description, the phrase "several embodiments" is used. Note that "several embodiments" describes all subsets of possible embodiments, but does not always specify the same subset of embodiments.

[0045] The foregoing description is intended to enable any person skilled in the art to construct and use the disclosure, and is provided in the context of a particular use and its requirements. Furthermore, the foregoing description of embodiments of the disclosure is presented for illustrative and explanatory purposes only. They are not intended to be exhaustive or to limit the disclosure to the disclosed forms. Therefore, many modifications and variations will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and uses without departing from the spirit and scope of the disclosure. In addition, the discussion of prior embodiments is not intended to limit the disclosure. Therefore, the disclosure is not intended to be limited to the embodiments shown, but rather should be given the broadest scope consistent with the principles and features disclosed herein. [Explanation of Symbols]

[0046] 200 Conversion Circuit 210 Quantizer 212 Quantized Output 214 First power supply voltage 216 Second power supply voltage 218 Control Logic 400 Conversion Circuit 410 Quantizer 414 Decoder 416 Quantized Output 418 Multiplier 420 quantized output 422 Control Logic

Claims

1. A conversion circuit configured to perform analog-to-digital conversion and provide a quantized output corresponding to an input signal, at least in part based on a first power supply voltage and a second power supply voltage of an integrated circuit, wherein the first and second power supply voltages specify the full-scale range of the conversion circuit, and when the full-scale range exceeds a second full-scale range related to a reference voltage other than the first and second power supply voltages, the quantized output corresponds to a larger number of bits than when the full-scale range is equal to the second full-scale range. An integrated circuit equipped with the following features.

2. The integrated circuit according to claim 1, wherein the quantized output is at least partially based on a comparison between the input signal and the first power supply voltage and the second power supply voltage.

3. The integrated circuit according to claim 1, wherein the number of bits includes redundant bits, and the conversion circuit is configured to use the redundant bits to correct errors in the analog-to-digital conversion.

4. The integrated circuit according to claim 1, wherein when the full-scale range exceeds the second full-scale range, the conversion circuit is configured to scale the quantized output at least in part on the ratio of the full-scale range to the second full-scale range.

5. The integrated circuit according to claim 4, wherein the conversion circuit includes a set of interleaved unit analog-to-digital converters (ADCs).

6. The conversion circuit is configured to correct the difference in the quantized outputs of the set of unit ADCs. The integrated circuit according to claim 5, wherein the correction includes adjusting the ratio of at least one of the unit ADCs.

7. The integrated circuit according to claim 1, wherein the first power supply voltage includes a positive power supply voltage, and the second power supply voltage includes a negative power supply voltage or ground.

8. The integrated circuit according to claim 1, wherein the conversion circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC).

9. The integrated circuit according to claim 1, wherein the conversion circuit includes a pipelined analog-to-digital converter (ADC).

10. A conversion circuit, which performs analog-to-digital conversion and is configured to provide a quantized output corresponding to an input signal, at least partially based on a first power supply voltage and a second power supply voltage of the conversion circuit. Equipped with, The first power supply voltage and the second power supply voltage specify the full-scale range of the conversion circuit. A system in which, when the full-scale range exceeds a second full-scale range related to a reference voltage other than the first and second power supply voltages, the quantized output corresponds to a larger number of bits than when the full-scale range is equal to the second full-scale range.

11. The system according to claim 10, wherein the quantized output is at least partially based on a comparison between the input signal and the first power supply voltage and the second power supply voltage.

12. The system according to claim 10, wherein the number of bits includes redundant bits, and the conversion circuit is configured to use the redundant bits to correct errors in the analog-to-digital conversion.

13. The system according to claim 10, wherein when the full-scale range exceeds the second full-scale range, the conversion circuit is configured to scale the quantized output at least in part on the ratio of the full-scale range to the second full-scale range.

14. The conversion circuit includes a set of interleaved unit analog-to-digital converters (ADCs), The conversion circuit is configured to correct the difference in the quantized outputs of the set of unit ADCs. The correction includes adjusting the ratio of at least one of the unit ADCs. The system according to claim 13.

15. The system according to claim 10, wherein the conversion circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC) or a pipelined analog-to-digital converter (ADC).

16. By the conversion circuit, The step of receiving the input signal, The steps include performing analog-to-digital conversion and providing a quantized output corresponding to the input signal, at least partially based on the first and second power supply voltages of the conversion circuit, Includes, The first power supply voltage and the second power supply voltage specify the full-scale range of the conversion circuit. A method for performing analog-to-digital conversion, wherein when the full-scale range exceeds a second full-scale range related to a reference voltage other than the first and second power supply voltages, the quantized output corresponds to a larger number of bits than when the full-scale range is equal to the second full-scale range.

17. The method according to claim 16, wherein the quantized output is at least partially based on a comparison of the input signal with the first power supply voltage and the second power supply voltage.

18. The method according to claim 16, wherein the number of bits includes redundant bits, and the conversion circuit further includes the step of using the redundant bits to correct errors in the analog-to-digital conversion.

19. The method according to claim 16, further comprising the step of scaling the quantized output by the conversion circuit at least in part on the ratio of the full-scale range to the second full-scale range when the full-scale range exceeds the second full-scale range.

20. The method according to claim 16, wherein the conversion circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC) or a pipelined analog-to-digital converter (ADC).

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