Semiconductor memory

Abstract

To provide a semiconductor storage device which can be suitably manufactured.SOLUTION: A semiconductor storage device comprises: a substrate; a plurality of first conductive layers which are arrayed in a first direction intersecting the surface of the substrate; a memory structure which includes a first semiconductor layer opposed to the first conductive layer; first wiring; a second conductive layer; a first insulation layer which divides the plurality of first conductive layers in a second direction; a second insulation layer which divides one or the plurality of first conductive layers arranged on the side closest to the substrate in the plurality of first conductive layers in the second direction; and a third insulation layer which divides one or the plurality of first conductive layers arranged on the side farthest from the substrate in the plurality of first conductive layers in the second direction. The memory structure has a tapered shape whose width in the second direction becomes smaller as being apart from the substrate. The third insulation layer has a tapered shape whose width in the second direction becomes smaller as being closer to the substrate.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device.

Background Art

[0002] A semiconductor memory device including a substrate, a plurality of conductive layers stacked in a direction intersecting the surface of the substrate, a semiconductor layer facing the plurality of conductive layers, and a gate insulating layer provided between the conductive layers and the semiconductor layer is known. The gate insulating layer includes a memory portion capable of storing data, such as an insulating charge storage layer or a conductive charge storage layer such as a floating gate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device that can be preferably manufactured.

Means for Solving the Problems

[0005] A semiconductor memory device according to an embodiment includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting the surface of the substrate, a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers, and a gate insulating layer provided between the first semiconductor layer and the plurality of first conductive layers. A memory structure, a first wiring connected to an end of the first semiconductor layer closer to the substrate and extending in a second direction intersecting the first direction, a second conductive layer connected to an end of the first semiconductor layer farther from the substrate, a third direction intersecting the first and second directions for dividing the plurality of first conductive layers in the second direction, a first insulating layer extending in the first direction, a second insulating layer extending in the first and third directions for dividing one or more first conductive layers arranged closest to the substrate among the plurality of first conductive layers in the second direction, and a third insulating layer extending in the first and third directions for dividing one or more first conductive layers arranged farthest from the substrate among the plurality of first conductive layers in the second direction. The memory structure has a tapered shape in which the width in the second direction decreases as it moves away from the substrate. The third insulating layer has a tapered shape in which the width in the second direction decreases as it approaches the substrate.

Brief Description of the Drawings

[0006] [Figure 1] It is a schematic circuit diagram showing the configuration of a memory die MD according to the first embodiment. [Figure 2] It is a schematic perspective view showing the configuration of the memory die MD. [Figure 3] It is a schematic bottom view showing the configuration of the chip CM. [Figure 4] It is a schematic bottom view showing a part of the configuration of the chip CM. [Figure 5] It is a schematic cross-sectional view showing a part of the configuration of the chip CM. [Figure 6] It is a schematic cross-sectional view showing a part of the configuration of the chip CM. [Figure 7] It is a schematic cross-sectional view showing a part of the configuration of the chip CM. [Figure 8] It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 9]This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 10] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 11] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 12] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 13] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 14] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 15] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 16] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 17] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 18] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 19] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 20] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 21] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 22] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 23] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 24] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 25] This is a schematic cross-sectional view showing the configuration of a semiconductor memory device according to the second embodiment. [Figure 26] This is a schematic cross-sectional view showing the configuration of a semiconductor memory device according to the third embodiment. [Figure 27] This is a schematic cross-sectional view illustrating the manufacturing method of the same embodiment. [Figure 28]This is a schematic cross-sectional view showing the configuration of a semiconductor memory device according to the fourth embodiment. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0011] Furthermore, in this specification, the direction intersecting a predetermined surface may be referred to as the first direction, the direction along this predetermined surface as the second direction, and the direction along this predetermined surface that intersects the second direction as the third direction. These first, second, and third directions may or may not correspond to any of the Z, Y, and X directions.

[0012] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0013] Furthermore, in this specification, when we refer to the "width," "length," or "thickness" of a component, member, etc., in a predetermined direction, it may mean the width, length, or thickness of a cross-section observed by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy), etc.

[0014] [First Embodiment] [Circuit Configuration] Figure 1 is an equivalent circuit diagram schematically showing the configuration of a semiconductor memory device according to the first embodiment.

[0015] The semiconductor memory device according to this embodiment comprises a memory cell array MCA and a peripheral circuit PC that controls the memory cell array MCA.

[0016] The memory cell array MCA comprises multiple memory blocks MB. Each of these memory blocks MB comprises multiple string units SU. Each of these string units SU comprises multiple memory units MU. One end of each of these memory units MU is connected to a peripheral circuit PC via a bit line BL. The other end of each of these memory units MU is connected to the peripheral circuit PC via a common source line SL.

[0017] The memory unit MU comprises one or more drain selection transistors STD, multiple memory cells MC, and one or more source selection transistors STS, all connected in series between the bit line BL and the source line SL. Hereinafter, the drain selection transistors STD and STS may simply be referred to as selection transistors (STD, STS), etc.

[0018] A memory cell MC is a field-effect transistor (memory transistor) comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a memory portion capable of storing data. This memory portion is a charge storage film, such as a silicon nitride (SiN) film or a floating gate. The threshold voltage of the memory cell MC changes according to the amount of charge in the charge storage film. A word line WL is connected to the gate electrode of each of the multiple memory cell MCs contained in a single memory unit MU. These word lines WL are commonly connected to memory cells MS at the same location in the series direction of all memory units MU within a single memory block MB.

[0019] A selection transistor (STD, STS) is a field-effect transistor comprising a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. In this example, a memory unit MU is shown to have two drain selection transistors STD and two source selection transistors STS, but a memory unit MU may have one STD or one or more STS selection transistors each. A selection gate line (SGD, SGS) is connected to the gate electrode of each selection transistor (STD, STS).

[0020] The drain-selection gate wire SGD is provided separately for each string unit SU and is connected in common to all drain-selection transistors STD within a single string unit SU. In Figure 1, the drain-selection gate wires SGD connected to each string unit SU are denoted as drain-selection gate wires SGD1, SGD2, ..., SGDn-1, and SGDn.

[0021] The source selection gate line SGS is provided separately for one or more string units SU in a single memory block MB and is connected in common to all source selection transistors STS in one or more string units SU. In Figure 1, the multiple string units SU contained in a single memory block MB are divided into two, and the source selection gate line SGS connected to one set of string units SU is denoted as source selection gate line SGS1, and the source selection gate line SGS connected to the other set of string units SU is denoted as source selection gate line SGS2.

[0022] [Memory die MD structure] Figure 2 is a schematic exploded perspective view showing an example configuration of a semiconductor memory device according to this embodiment. The semiconductor memory device according to this embodiment includes a memory die MD. The memory die MD is a chip C including a memory cell array MCA. M And, including the peripheral circuit PC, chip C P It is equipped with the following.

[0023] Chip CM On its upper surface, a plurality of bonding pad electrodes P X are provided. Also, on the lower surface of chip C M a plurality of first bonding electrodes P I1 are provided. Also, on the upper surface of chip C P a plurality of second bonding electrodes P I2 are provided. Hereinafter, for chip C M the surface on which the plurality of first bonding electrodes P I1 are provided is referred to as the front surface, and the surface on which the plurality of bonding pad electrodes P X are provided is referred to as the back surface. Also, for chip C P the surface on which the plurality of second bonding electrodes P I2 are provided is referred to as the front surface, and the surface on the opposite side of the front surface is referred to as the back surface. In the illustrated example, the front surface of chip C P is provided above the back surface of chip C P , and the back surface of chip C M is provided above the front surface of chip C M .

[0024] Chip C M and chip C P are arranged such that the front surface of chip C M faces the front surface of chip C P . The plurality of first bonding electrodes P I1 are provided corresponding to the plurality of second bonding electrodes P I2 respectively, and are arranged at positions where they can be bonded to the plurality of second bonding electrodes P I2 . The first bonding electrode P I1 and the second bonding electrode P I2 function as bonding electrodes for bonding chip C M and chip C P and electrically connecting them. The bonding pad electrode P X functions as an electrode for electrically connecting the memory die MD to a controller die (not shown) etc.

[0025] In addition, in the example of FIG. 2, the corner portions a1, a2, a3, a4 of chip C M are respectively the chip C PThese correspond to corners b1, b2, b3, and b4.

[0026] Figure 3 shows chip C M This is a schematic bottom view showing the configuration. Figure 4 is a schematic bottom view showing an enlarged view of the configuration of the part indicated by A in Figure 3. Figure 4 also shows plan views of the structure in Figure 5, cut along lines CC', DD', and EE', respectively, and arranged in the direction of the arrows, in the direction of X. Figure 5 is a schematic cross-sectional view of the memory die MD, cut along line BB' shown in Figure 4, and viewed from the direction of the arrow. Figure 6 is a schematic cross-sectional view showing an enlarged view of the configuration of the part indicated by F in Figure 5. Figure 7 is a schematic cross-sectional view showing an enlarged view of the structure of the part indicated by G in Figure 5.

[0027] [Chip C M [Structure] Chip C M For example, as shown in Figure 3, there are four memory cell array regions R aligned in the X and Y directions. MCA and memory cell array region R MCA The outer periphery region R of the memory cell array is provided along the outer edge. MCAE and multiple bonding pad electrodes P X Multiple bonding pad electrode regions R corresponding to each other PX And, Chip C M Edge seal region R provided along the outer edge E It is equipped with the following.

[0028] Memory cell array region R MCA It has multiple memory blocks MB aligned in the Y direction. Between adjacent memory blocks MB in the Y direction, interblock structures ST extending in the X and Z directions are arranged, respectively, as shown in Figures 4 and 5.

[0029] As shown in Figure 5, the memory block MB comprises a plurality of conductive layers 110 arranged in the Z direction and a plurality of memory structures 100 extending in the Z direction.

[0030] The multiple conductive layers 110 are each substantially plate-shaped conductive layers stretched in the X direction. The conductive layers 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layers 110 may also include polycrystalline silicon containing, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction.

[0031] Of the multiple conductive layers 110, one or more conductive layers 110 located at the top function as gate electrodes for the source selection gate line SGS and the multiple source selection transistors STS (Figure 1) connected thereto. Hereinafter, such conductive layers 110 may be referred to as conductive layer 110 (SGS).

[0032] Of the multiple conductive layers 110, one or more conductive layers 110 located at the bottom layer function as gate electrodes for the drain selection gate wire SGD and the multiple drain selection transistors STD (Figure 1) connected thereto. Hereinafter, such conductive layers 110 may be referred to as conductive layer 110 (SGD).

[0033] Among the multiple conductive layers 110, the multiple conductive layers 110 arranged between conductive layer 110(SGS) and conductive layer 110(SGD) function as gate electrodes for the word line WL and the multiple memory cells MC (Figure 1) connected thereto. Hereinafter, such conductive layers 110 may be referred to as conductive layer 110(WL).

[0034] The memory structure 100 comprises a semiconductor layer 120 extending in the Z direction, and a gate insulating film 130 provided between a plurality of conductive layers 110 and the semiconductor layer 120. One or more source selection transistors STS (Figure 1) are configured at a position facing the conductive layer 110 (SGS) of the memory structure 100. One or more drain selection transistors STD (Figure 1) are configured at a position facing the conductive layer 110 (SGD) of the memory structure 100. A plurality of memory cells MC (Figure 1) are configured at a position facing the conductive layer 110 (WL) of the memory structure 100.

[0035] The memory structure 100 is arranged in a predetermined pattern in the X and Y directions, as shown in Figure 4, for example. The semiconductor layer 120 in the memory structure 100 functions, for example, as a channel region for multiple memory cells. The semiconductor layer 120 is, for example, a semiconductor layer made of polycrystalline silicon (Si). The semiconductor layer 120 has a substantially bottomed cylindrical shape, as shown in Figure 5, for example, and an insulating layer 125 made of silicon oxide or the like is provided in the central part. The outer surface of the semiconductor layer 120 faces the conductive layer 110. A gate insulating film 130 is provided between the semiconductor layer 120 and the conductive layer 110.

[0036] A conductive layer 112 made of polycrystalline silicon (Si) or the like is provided on top of the uppermost insulating layer 101. An impurity region containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is provided at the upper end of the semiconductor layer 120. The upper end of the semiconductor layer 120 is covered by a gate insulating film 130. A portion of the gate insulating film 130 is removed, exposing a part of the side surface of the upper end of the semiconductor layer 120, which is electrically connected to the conductive layer 112.

[0037] An impurity region containing N-type impurities such as phosphorus (P) is provided at the lower end of the semiconductor layer 120. This impurity region covers the lower end of the insulating layer 125. This impurity region is also electrically connected to the bit line BL. The bit line BL is connected to the first bonding electrode P described above. I1 via chip C P It is electrically connected to the internal components.

[0038] The gate insulating film 130 has a substantially cylindrical shape that covers the outer circumferential surface of the semiconductor layer 120. The gate insulating film 130 comprises a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110, as shown in Figure 6, for example. The tunnel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a charge-storing film such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and are stretched in the Z direction along the outer circumferential surface of the semiconductor layer 120.

[0039] Figure 6 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0040] The interblock structure ST extends in the X and Z directions, as shown in Figures 4 and 5, for example, and divides the multiple conductive layers 110 and multiple insulating layers 101 in the Y direction for each memory block MB. The interblock structure ST comprises, for example, a conductive layer 141 extending in the X and Z directions, and an insulating layer 142 made of silicon oxide (SiO2) or the like provided on the Y-direction side of the conductive layer 141. The conductive layer 141 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 141 functions, for example, as part of the source line. The upper end of the conductive layer 141 is located above the upper surface of the uppermost insulating layer 101. The upper end of the conductive layer 141 is also electrically connected to the conductive layer 112.

[0041] The conductive layer 112 may contain, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The conductive layer 112 functions, for example, as part of the source wire. The conductive layer 112 is in contact with the upper surface of the insulating layer 101, the upper end of the semiconductor layer 120, and the upper end of the conductive layer 141.

[0042] The conductive layer 112 and the conductive layer 110 (SGS) are divided into two in the Y direction along with the conductive layer 112 by the source-side dividing insulating layer SHE2 at the center of the memory block MB in the Y direction. Therefore, the width of the conductive layer 110 (SGS) in the Y direction is approximately half the width of the memory block MB in the Y direction. Each conductive layer 110 (SGS) is electrically independent on one side of the Y direction of a single memory block MB.

[0043] On the other hand, the conductive layer 110 (SGD) is divided in the Y direction for each string unit SU by the inter-string unit insulating layer SHE1. Therefore, the conductive layer 110 (SGD) has a smaller width in the Y direction than the other conductive layers 110 (SGS) and 110 (WL). Each conductive layer 110 (SGD) is electrically independent for each string unit SU.

[0044] In this example, as shown in Figure 4, five inter-string unit insulating layers SHE1 are provided between the inter-block structures ST. The central inter-string unit insulating layer SHE1 in the Y direction is provided so as to overlap with a row of dummy memory structures 100 aligned in the X direction at the center of the memory block MB in the Y direction. The other inter-string unit insulating layers SHE1 are provided between rows of memory structures 100 aligned in the X direction that are adjacent to each other in the Y direction, so as to be in contact with these rows of memory structures 100. Furthermore, the source-side split insulating layer SHE2 is provided so as to overlap with a row of dummy memory structures 100 aligned in the X direction at the center of the memory block MB in the Y direction, as shown in Figure 4.

[0045] [Chip C P [Structure] Chip C P As shown in Figure 5, for example, the device comprises a substrate 200 and a plurality of transistors Tr provided on the surface of the substrate 200. These plurality of transistors Tr are connected to the second bonding electrode P described above. I2 via chip C MIt is connected to the internal configuration and functions as a peripheral circuit PC used to control the memory cell array MCA. For example, in a read operation, this peripheral circuit PC supplies voltage to the current path including the bit line BL, semiconductor layer 120, conductive layer 110, conductive layer 112, and conductive layer 141, and determines the data recorded in the memory cell depending on whether or not current is flowing.

[0046] When reading (or writing) data to a memory cell MC, the peripheral circuit PC applies a drive voltage to the conductive layer 110 (SGD) corresponding to the string unit SU to be accessed, turning on only the drain selection transistor STD of the selected string unit SU. Furthermore, when reading (or writing) data to a memory cell MC, the peripheral circuit PC applies a drive voltage to one of the conductive layers 110 (SGS) containing the selected string unit SU, turning off the source selection transistor STS connected to the other conductive layer (SGS). This causes memory cells MC not involved in the read operation to be in a floating state.

[0047] As shown in Figure 7, the memory structure 100 has a tapered shape in which its width in the Y direction narrows as it moves away from the substrate 200 (Figure 5). More specifically, the width w1 in the Y direction at the lower end of the memory structure 100 is greater than the width w2 in the Y direction at the upper end. Also, as shown in Figure 7, the source-side divided insulating layer SHE2 has a tapered shape in which its width in the Y direction narrows as it approaches the substrate 200 (Figure 5). More specifically, the width w3 in the Y direction at the upper end of the source-side divided insulating layer SHE2 is greater than the width w4 in the Y direction at the lower end.

[0048] [Manufacturing method] Next, the manufacturing method for memory dies (MD) will be explained with reference to Figures 8 to 24. Figures 8 to 24 are schematic cross-sectional views illustrating the manufacturing method, and show the cross-section corresponding to Figure 5.

[0049] In manufacturing the memory die MD according to this embodiment, an insulating layer 102 made of silicon oxide (SiO2) or the like is formed on a substrate 300, for example, as shown in Figure 8. This step is carried out by a method such as CVD (Chemical Vapor Deposition). Next, a conductive layer 112A made of silicon, a sacrificial layer 103A made of silicon oxide (SiO2), a sacrificial layer 103B made of silicon nitride (SiN), a sacrificial layer 103C made of silicon oxide (SiO2), and a conductive layer 112B made of silicon are formed on the insulating layer 102. The conductive layers 112A and 112B may contain polycrystalline silicon containing, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). Next, a plurality of insulating layers 101 made of silicon oxide (SiO2) or the like, and a plurality of sacrificial layers 110A made of silicon nitride (SiN) or the like are alternately formed on the conductive layer 112B. These steps are carried out by a method such as CVD. Next, a resist is formed on the uppermost insulating layer 101, and a mask 104 is formed by photoetching.

[0050] Next, as shown in Figure 9, for example, a mask 104 is used to form multiple memory holes 100A at positions corresponding to the memory structure 100. The memory holes 100A extend in the Z direction, penetrating multiple insulating layers 101, multiple sacrificial layers 110A, conductive layer 112B, and sacrificial layers 103C, 103B, and 103A, reaching partway through the conductive layer 112A. This process is carried out by a method such as RIE (Reactive Ion Etching).

[0051] Next, as shown in Figure 10, for example, a gate insulating film 130, a semiconductor layer 120, and an insulating layer 125 are formed on the upper surface of the uppermost insulating layer 101 and the inner circumferential surface of the memory hole 100A to form the memory structure 100B. When forming the semiconductor layer 120, for example, film deposition is performed by CVD or the like to form an amorphous silicon (Si) film inside the memory hole 100A. Alternatively, the crystal structure of this amorphous silicon (Si) film may be modified by, for example, annealing. Furthermore, prior to forming the gate insulating film 130 on the inner circumferential surface of the memory hole 100A, an insulating layer such as silicon oxide (SiO2) may be formed on the portions of the conductive layer 112A and conductive layer 112B that are exposed to the memory hole 100A, for example, by thermal oxidation.

[0052] Next, as shown in Figure 11, for example, a portion of the insulating layer 125, semiconductor layer 120, and gate insulating film 130 is removed to expose the uppermost insulating layer 101. Furthermore, the upper ends of the semiconductor layer 120 and insulating layer 125 are excavated below the upper surface of the insulating layer 101. This process is carried out, for example, by a method such as RIE.

[0053] Next, as shown in Figure 12, for example, a semiconductor layer 121 is formed on the upper end of the semiconductor layer 120 and the insulating layer 125. The semiconductor layer 121 contains amorphous silicon containing, for example, N-type impurities such as phosphorus (P). This step is carried out by, for example, a method such as CVD. Next, a portion of the semiconductor layer 121 is removed by, for example, a method such as RIE to expose the insulating layer 101 located at the top layer. Next, an insulating layer 105 is formed on the insulating layer 101 and the semiconductor layer 121. This step is carried out by, for example, a method such as CVD.

[0054] Next, as shown in Figure 13, for example, a groove STA is formed at the position where the interblock structure ST is formed. The groove STA extends in the Z and X directions, dividing the insulating layer 101, sacrificial layer 110A, conductive layer 112B, sacrificial layer 113C, and sacrificial layer 113B in the Y direction, and exposing the upper surface of the sacrificial layer 113A. This step is performed, for example, by a method such as RIE. Next, a protective film 140B such as silicon nitride is formed on the Y-direction side surface of the groove STA. This step is performed, for example, by forming an insulating film such as silicon nitride on the Y-direction side surface and bottom surface of the groove STA by a method such as CVD, and then removing the portion of this insulating film that covers the bottom surface of the groove STA by a method such as RIE.

[0055] Next, as shown in Figure 14, for example, a portion of the sacrificial layers 113A, 113B, 113C and the gate insulating film 130 is removed, exposing a portion of the semiconductor layer 120. This step is performed, for example, by a method such as wet etching.

[0056] Next, as shown in Figure 15, for example, a semiconductor layer is formed in the area where the sacrificial layers 113A, 113B, 113C and a portion of the gate insulating film 130 have been removed, and a conductive layer 112 is formed with the newly formed semiconductor layer and conductive layers 112A, 112B. Furthermore, the semiconductor layer formed in the groove STA is removed. This process is carried out, for example, by methods such as epitaxial growth and RIE.

[0057] Next, as shown in Figure 16, for example, the protective film 140B is removed, and the sacrificial layer 110A is removed via the groove STA. This step is performed by a method such as wet etching. As a result, a hollow structure is formed which includes a plurality of insulating layers 101 arranged in the Z direction and a memory structure 100B that supports these insulating layers 101.

[0058] Next, a conductive layer 110 is formed in the hollow portion, for example, as shown in Figure 17. This step is carried out by a method such as CVD. Next, an insulating layer 142 constituting the interblock structure ST is formed in the groove STA. Next, a conductive layer 141 is formed in the center of the insulating layer 142 in the Y direction, and a contact 161 is formed. These steps are carried out by a method such as CVD and RIE. The insulating layer 142 extends from the insulating layer 105 to the conductive layer 112. The conductive layer 141 penetrates the insulating layer 105, and its lower end is electrically connected to the conductive layer 112. The contact 161 penetrates the insulating layer 105 and is electrically connected to the semiconductor layer 121 of the memory structure 100B.

[0059] Next, as shown in Figure 18, for example, a resist is formed on the insulating layer 105, and a mask 106 is formed by a photoetching method. Using the mask 106, grooves SHE1A are formed that divide the insulating layer 105, the insulating layer 101, and the conductive layer 110 (SGD) in the Y direction. This step is performed by a method such as RIE.

[0060] Next, as shown in Figure 19, for example, an insulating layer SHE1 is formed in the groove SHE1A between string units. Then, another insulating layer 105 is laminated on top of the first insulating layer 105. Next, the insulating layer 105 is etched in a predetermined pattern to form contacts 162 and bit lines BL that are connected to contacts 161.

[0061] Next, as shown in Figure 20, for example, an insulating layer 105 is laminated on the bit line BL, and contact 163, wiring 164, contact 165, and the first bonding electrode P are attached. I1 This process is carried out by methods such as CVD, photolithography, and etching. This forms the chip C. M It is manufactured.

[0062] Next, as shown in Figure 21, for example, chip C in the above process M A wafer in which chip C is formed, and chip C in a separate process. P The wafer on which the first bonding electrode P is formed 11 and the second bonded electrode P 12The two wafers are aligned and bonded together so that they are connected. In this bonding process, for example, one wafer is pressed against the other wafer to bring them into close contact, and then heat treatment is performed. As a result, the first bonding electrode P I1 and second bonded electrode P I2 via chip C M A wafer on which chip C is formed P It is bonded to the wafer on which it is formed.

[0063] Next, as shown in Figure 22, for example, chip C M Remove the substrate 300 included in the substrate.

[0064] Next, as shown in Figure 23, for example, a resist is formed on the insulating layer 102, and a mask 107 is formed by a photoetching method. Using the mask 107, grooves SHE2A are formed that divide the insulating layer 102, the conductive layer 112, and the conductive layer (SGS) into two in the Y direction. This step is performed by a method such as RIE.

[0065] Next, as shown in Figure 24, for example, a source-side divided insulating layer SHE2 is formed in the groove SHE2A. Then, a wiring layer 170 and an insulating layer 108 are formed on top of the insulating layer 102. After that, a bonding pad electrode P is placed above this structure. X A memory die (MD) is formed by dicing a structure created by forming various elements and bonding wafers together.

[0066] [effect] According to this embodiment, by dividing the source selection gate line SGS within one memory block MB into two and selectively driving only one of them, the load capacity during driving of the memory cell MC can be reduced and the lead time can be improved. The source-side dividing insulating layer SHE2 for dividing the source selection gate line SGS is located on the chip C M , C P Since it can be formed from the top side after bonding, manufacturing is easy. In addition, although the conductive layer 112 is separated by the source-side dividing insulating layer SHE2, each conductive layer 112 is connected to the conductive layer 141 of the interblock structure ST, so it functions as a common source.

[0067] Furthermore, as shown in Figure 7, the memory structure 100 has a tapered shape in which its width in the Y direction narrows as it moves away from the substrate 200, and the source-side divided insulating layer SHE2 has a tapered shape in which its width in the Y direction narrows as it approaches the substrate 200. Therefore, the minimum gap g1 between the memory structure 100 and the source-side divided insulating layer SHE2 can be made wider compared to the case where both have the same tapered shape.

[0068] [Second Embodiment] Next, the configuration of the semiconductor memory device according to the second embodiment will be described with reference to Figure 25. Figure 25 is a schematic cross-sectional view illustrating the configuration of the semiconductor memory device according to the second embodiment.

[0069] The semiconductor memory device according to the second embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the second embodiment has five source-side divided insulating layers SHE2 provided in one memory block MB. The source-side divided insulating layer SHE2, like the inter-string unit insulating layer SHE1, divides the conductive layer 110 (SGS) for each string unit SU.

[0070] The conductive layers 112, separated by the source-side dividing insulating layer SHE2, are connected to each other, for example, by a wiring layer 170, and thus function as a common source.

[0071] According to this embodiment, the source selection gate line SGS and the drain selection gate line SGD can be controlled similarly, thus simplifying control. Furthermore, since the number of source selection transistors STS that are ON is reduced compared to the first embodiment, the load capacity during driving the memory cell MC can be further reduced, and the lead time can be improved.

[0072] [Third Embodiment] Next, the configuration of the semiconductor memory device according to the third embodiment will be described with reference to Figure 26. Figure 26 is a schematic cross-sectional view illustrating the configuration of the semiconductor memory device according to the third embodiment.

[0073] The semiconductor memory device according to the third embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, in the semiconductor memory device according to the third embodiment, an insulating layer 109 made of silicon oxide (SiO2) or the like is provided in the center of the conductive layer 112 in the Y direction in the memory block MB, extending in the X and Z directions. The source-side dividing insulating layer SHE2 divides the insulating layer 109, the insulating layer 101, and the conductive layer 110 (SGS) in the Y direction.

[0074] Figure 27 is a diagram illustrating the manufacturing method of the third embodiment. In this embodiment, after forming an insulating layer 102, sacrificial layers 103A, 103B, 103C, and a conductive layer 112B on a substrate 300, an insulating layer 109 is pre-formed in the center of the memory block MB in the Y direction. This step is performed, for example, by methods such as photolithography, etching, or CVD.

[0075] According to the third embodiment, when forming grooves for forming the source-side divided insulating layer SHE2, only the insulating layers 109, 101 and the conductive layer 110 (SGS) are considered, and the polycrystalline silicon conductive layer 112 is not etched, thus simplifying the etching conditions.

[0076] [Fourth Embodiment] Next, a method for manufacturing a semiconductor memory device according to the fourth embodiment will be described with reference to Figure 28. Figure 28 is a schematic cross-sectional view illustrating the semiconductor memory device according to the fourth embodiment.

[0077] The method for manufacturing a semiconductor memory device according to this embodiment is basically the same as the method for manufacturing a semiconductor memory device according to the first embodiment. However, in this embodiment, the conductive layer 112 is used as a mask for creating the source-side divided insulating layer SHE2. In this case, as shown in the figure, depending on the etching conditions, the taper angle of the conductive layer 112 and the taper angle of the conductive layer 110 (SGS) are different. In other words, the source-side divided insulating layer SHE2 has a first portion located on the substrate 200 side that divides the conductive layer 110 (SGS), and a second portion located on the opposite side of the substrate 200 that divides the conductive layer 112, with the second portion having a larger taper than the first portion. More specifically, if the width in the Y direction at the lower end of the source-side divided insulating layer SHE2 is w11, the width in the Y direction at the lower surface of the conductive layer 112 is w12, the width in the Y direction at the upper end is w13, the height from the lower end to the lower surface of the conductive layer 112 is h1, and the distance from the lower surface to the upper end of the conductive layer 112 is h2, then these relationships are: (w12-w11) / h1<(W13-w12) / h2 This is the result.

[0078] According to this embodiment, the manufacturing process is simplified because the conductive layer 112 is used as a mask.

[0079] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0080] 110...conductive layer, 112...conductive layer, 120...semiconductor layer, 125...insulating layer, 130...gate insulating film.

Claims

1. circuit board and A plurality of first conductive layers arranged in a first direction intersecting the surface of the substrate, A memory structure including a first semiconductor layer extending in the first direction and facing the plurality of first conductive layers, and a gate insulating layer provided between the first semiconductor layer and the plurality of first conductive layers, A first wiring is connected to the end of the first semiconductor layer on the side closer to the substrate and extends in a second direction intersecting the first direction, A second conductive layer connected to the end of the first semiconductor layer furthest from the substrate, A first insulating layer extending in the first direction and a third direction intersecting the first and second directions, which divides the plurality of first conductive layers in the second direction, A second insulating layer extending in the first and third directions divides one or more of the first conductive layers, which are arranged on the side closest to the substrate, in the second direction, A third insulating layer extending in the first and third directions divides one or more of the first conductive layers and second conductive layers located on the side furthest from the substrate among the plurality of first conductive layers in the second direction, A third wiring layer connecting the second conductive layers that are separated in the second direction, Equipped with, The memory structure has a tapered shape in which the width in the second direction decreases as it moves away from the substrate. The third insulating layer has a tapered shape, with its width in the second direction decreasing as it approaches the substrate. Semiconductor memory device.

2. The end of the memory structure furthest from the substrate has an exposed portion where a portion of the gate insulating layer on the side surface has been removed, exposing the side surface of the first semiconductor layer, and this exposed portion is electrically connected to the second conductive layer. The semiconductor memory device according to claim 1.

3. The third wiring layer is provided along the first insulating layer and has a third conductive layer extending in the first and third directions, with one end connected to the second conductive layer. The semiconductor memory device according to claim 1.

4. The number of second insulating layers provided between the first insulating layers is greater than the number of third insulating layers provided between the first insulating layers. The semiconductor memory device according to claim 1.

5. There is one third insulating layer provided between the first insulating layers. The semiconductor memory device according to claim 4.

6. The number of second insulating layers provided between the first insulating layers is equal to the number of third insulating layers provided between the first insulating layers. The semiconductor memory device according to claim 1.

7. The width in the second direction of the end of the memory structure on the substrate side is greater than the width in the second direction of the end of the memory structure on the opposite side of the substrate. The width of the third insulating layer at the substrate-side end in the second direction is smaller than the width of the third insulating layer at the substrate-side end in the second direction. The semiconductor memory device according to claim 1.

8. The third insulating layer has a first portion located on the substrate side that separates the first conductive layer, and a second portion that separates the second conductive layer. The second portion has a greater taper than the first portion. The semiconductor memory device according to claim 1.

9. The third wiring layer is formed on a side further from the substrate than the second conductive layer. The semiconductor memory device according to claim 1.

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