Methods for reducing the surface roughness of a material

Abstract

To provide a method for depositing a material with reduced surface roughness.SOLUTION: A deposition method includes delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber, and providing a hydrogen-containing precursor to the silicon-containing precursor and the boron-containing precursor. A flow ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor is about 2:1 or greater. The method further includes forming a plasma of all the precursors in the processing region of the semiconductor processing chamber, and depositing the silicon and boron material on a substrate disposed in the processing region of the semiconductor processing chamber. The method also optionally includes thermally annealing the formed silicon and boron-containing material, and optionally etching the material.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit of priority of U.S. Patent Application No. 62 / 933,012, filed on November 8, 2019, the content of which is hereby incorporated by reference in its entirety for all purposes.

[0002] Technical Field

[0002] This technology relates to semiconductor deposition processes. More specifically, this technology relates to a method for depositing a material with reduced surface roughness.

Background Art

[0003]

[0003] Integrated circuits are enabled by processes that create complexly patterned material layers on a substrate surface. To create a patterned material on a substrate, a controlled method for forming and removing exposed materials is required. As device sizes continue to shrink, the material uniformity can affect subsequent operation. For example, the surface roughness of a masking material can affect the uniformity of subsequent etching.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used in the manufacture of high - quality devices and structures. This technology addresses these and other needs.

Summary of the Invention

[0005]

[0005] An exemplary deposition method may include delivering silicon-containing precursors and boron-containing precursors to a processing area of ​​a semiconductor processing chamber. This method may include providing hydrogen-containing precursors to the silicon-containing precursors and boron-containing precursors. The flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor may be about 2:1 or greater. This method may include forming a plasma of all precursors within the processing area of ​​the semiconductor processing chamber. This method may include depositing silicon and boron materials on a substrate placed within the processing area of ​​the semiconductor processing chamber.

[0006]

[0006] In some embodiments, the silicon and boron materials may be characterized by a deposited surface roughness of about 2 nm or less. The plasma power density is about 0.5 W / cm² while forming the plasma of all precursors within the processing area of ​​the semiconductor processing chamber. 2 The temperature can be maintained above the above. The substrate temperature can be maintained above about 400°C while depositing silicon and boron materials on the substrate. The pressure can be maintained below about 10 Torr while depositing silicon and boron materials on the substrate. This method may include providing an argon precursor to the silicon-containing precursor and the boron-containing precursor. This method may include performing thermal annealing of the silicon and boron materials following the deposition. The silicon-containing precursor may be or include silane. The boron-containing precursor may be or include diborane.

[0007]

[0007] Some embodiments of the present technology may include a deposition method. This method may include delivering silicon-containing precursors and boron-containing precursors to a processing area of ​​a semiconductor processing chamber. This method may include forming a plasma of silicon-containing precursors and boron-containing precursors within the processing area of ​​the semiconductor processing chamber. This method may include depositing silicon and boron materials on a substrate placed within the processing area of ​​the semiconductor processing chamber. The silicon and boron materials may be characterized by an as-deposited surface roughness of about 1.5 nm or less.

[0008]

[0008] In some embodiments, this method may include providing a hydrogen-containing precursor to a silicon-containing precursor and a boron-containing precursor. The flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor may be about 2:1 or higher. This method may include providing an argon precursor to a silicon-containing precursor and a boron-containing precursor. The flow rate ratio of the argon precursor to the hydrogen-containing precursor may be about 1:1 or lower. This method may include thermal annealing of the silicon and boron materials for a first period following deposition. The substrate may be maintained at a first temperature during deposition. The substrate may be maintained at a second temperature while thermal annealing of the silicon and boron materials, and the second temperature may be higher than the first temperature. The second temperature may be about 500°C or higher. The plasma output may be maintained at about 2.0 kW or higher while forming the plasma of the silicon-containing precursor and the boron-containing precursor within the processing area of ​​the semiconductor processing chamber.

[0009]

[0009] Some embodiments of the present technology may encompass a deposition method. This method may include delivering silicon-containing precursors and boron-containing precursors to a processing area of ​​a semiconductor processing chamber. This method may include forming a plasma of all precursors within the processing area of ​​the semiconductor processing chamber. The plasma output may be maintained at about 1.0 kW or higher while forming a plasma of all precursors within the processing area of ​​the semiconductor processing chamber. This method may include depositing silicon and boron materials on a substrate placed within the processing area of ​​the semiconductor processing chamber.

[0010]

[0010] In some embodiments, this method may include providing a hydrogen-containing precursor to a silicon-containing precursor and a boron-containing precursor. The flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor may be about 2:1 or higher. This method may include providing an argon precursor to a silicon-containing precursor and a boron-containing precursor. The flow rate ratio of the argon precursor to the hydrogen-containing precursor may be about 1:1 or lower. This method may include performing thermal annealing of the silicon and boron materials for a first period following deposition. The substrate may be maintained at a first temperature during deposition. The substrate may be maintained at a second temperature during the thermal annealing of the silicon and boron materials, and the second temperature may be higher than the first temperature.

[0011]

[0011] Such technologies may offer numerous advantages over conventional systems and techniques. For example, this process may produce films characterized by reduced surface roughness. Furthermore, the operation of embodiments of this technology may produce improved mask materials that facilitate processing operations. These embodiments and other embodiments, along with their many advantages and features, are described in detail in the following description and accompanying drawings.

[0012]

[0012] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1]

[0013] A schematic cross-sectional view of an exemplary processing chamber according to several embodiments of the present technology is shown. [Figure 2]

[0014] The following describes the exemplary operation of a deposition method according to several embodiments of this technology. [Figure 3]

[0015] Schematic diagrams of substrates before deposition according to several embodiments of this technology are shown. [Figure 4A-4B]

[0016] A schematic diagram of an exemplary substrate during deposition according to several embodiments of this technology is shown. [Figure 5A-5B]

[0017] A schematic diagram of an exemplary substrate during deposition according to several embodiments of this technology is shown. [Modes for carrying out the invention]

[0014]

[0018] Some drawings are included as schematic diagrams. It should be understood that drawings are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to realistic depictions, and may include exaggerated material for illustrative purposes.

[0015]

[0019] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished according to their reference numerals by letters that distinguish between similar components. Where only a first reference numeral is used in this specification, its description is applicable to any of the similar components having the same first reference numeral, regardless of the letters used.

[0016]

[0020] During semiconductor manufacturing, structures can be formed on a substrate using various deposition and etching operations. Masking materials can be used to partially etch the material or to etch the entire substrate to create feature areas. As device sizes continue to shrink and material selectivity improves, structure formation may become easier, and thus, the use of improved hard masks may facilitate manufacturing. For example, compared to a thermally produced amorphous silicon hard mask, a boron-incorporated silicon film may feature improved hardness and other material properties, facilitating the use of the film as a masking material. However, while thermally produced silicon may feature a substantially smooth surface, a boron-incorporated silicon film may feature improved surface roughness.

[0017]

[0021] This technique can overcome these limitations by performing surface treatment during deposition by adjusting deposition parameters and materials. For example, this technique may include etching exposed feature areas of the film layer during deposition. This may facilitate a more uniform surface profile, thereby reducing or limiting surface roughness during deposition. After describing a general configuration of a chamber according to embodiments of this application in which the plasma treatment operations described later may be performed, specific methods and component configurations may be discussed. It should be understood that this technique is not intended to be limited to the specific films and treatments discussed, as the described technique can be used to improve many film formation processes and may be applicable to various treatment chambers and operations.

[0018]

[0022] Figure 1 shows a schematic cross-sectional view of an exemplary processing chamber 100 according to several embodiments of the present technology. This figure can schematicly illustrate a system incorporating one or more aspects of the present technology and / or it can perform one or more operations according to embodiments of the present technology. Further details of the chamber 100 or the method to be carried out may be described further below. While the chamber 100 may be used to form a film layer according to several embodiments of the present technology, it should be understood that the method can be similarly carried out in any chamber in which film formation may occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 connected to the chamber body 102 and enclosing the substrate support 104 in a processing space 120. A substrate 103 may be provided to the processing space 120 through an opening 126. The opening 126 may be conventionally sealed for processing using a slit valve or a door. The substrate 103 may be mounted on the surface 105 of the substrate support during processing. The substrate support 104 is rotatable along the axis 147, as indicated by the arrow 145, where the shaft 144 of the substrate support 104 may be positioned. Alternatively, the substrate support 104 may be lifted and rotated as needed during the deposition process.

[0019]

[0023] The plasma profile modulator 111 may be disposed within the processing chamber 100 to control the plasma distribution across the entire substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108, which may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member and may be a ring electrode. The first electrode 108 may be a continuous loop along the periphery of the processing chamber 100 surrounding the processing space 120 or may be discontinuous at selected locations as desired. The first electrode 108 may be a perforated electrode such as a perforated ring or mesh electrode or may be a plate electrode such as, for example, a secondary gas distributor.

[0020]

[0024] One or more insulators 110a, 110b may be dielectric materials such as ceramic or metal oxide, for example, aluminum oxide and / or aluminum nitride, contact the first electrode 108, and may electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define apertures 118 for distributing the process precursors into the processing space 120. The gas distributor 112 may be coupled to a first power source 142 such as an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power source that may be coupled to the processing chamber. In some embodiments, the first power source 142 may be an RF power supply.

[0021]

[0025] The gas distributor 112 can be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 can also be formed of conductive and non-conductive components. For example, the body of the gas distributor 112 can be conductive while the faceplate of the gas distributor 112 can be non-conductive. The gas distributor 112 can be powered by a first power source 142 as shown in, for example, FIG. 1, or the gas distributor 112 can be connected to ground in some embodiments.

[0022]

[0026] The first electrode 108 can be connected to a first tuning circuit 128 that can control the ground path of the processing chamber 100. The first tuning circuit 128 can include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 can be or include a variable capacitor or other circuit element. The first tuning circuit 128 can be or include one or more inductors 132. The first tuning circuit 128 can be any circuit that allows for a variable or controllable impedance under the plasma conditions present in the processing space 120 during processing. In some embodiments as shown, the first tuning circuit 128 can include a first circuit leg and a second circuit leg connected in parallel between ground and the first electronic sensor 130. The first circuit leg can include a first inductor 132A. The second circuit leg can include a second inductor 132B connected in series with the first electronic controller 134. The second inductor 132B can be disposed between the first electronic controller 134 and the node connecting both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 can be a voltage or current sensor and can be connected to the first electronic controller 134. Thereby, a certain degree of closed-loop control of the plasma conditions inside the processing space 120 can be obtained.

[0023]

[0027] The second electrode 122 may be connected to the substrate support 104. The second electrode 122 may be incorporated into the substrate support 104 or connected to the surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other dispersed structure of conductive elements. The second electrode 122 may be a tuning electrode and may be connected to a second tuning circuit 136 by a conduit 146 (e.g., a cable with a selected resistance (e.g., 50 ohms)) located within the shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140 which may be a second variable capacitor. The second electronic sensor 138 may be a voltage sensor or a current sensor and may be connected to the second electronic controller 140 to provide further control over the plasma conditions in the processing space 120.

[0024]

[0028] A third electrode 124, which may be a bias electrode and / or an electrostatic chuck electrode, may be connected to the substrate support 104. The third electrode may be connected to a second power source 150 through a filter 148. The filter 148 may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power.

[0025]

[0029] The lid assembly 106 and substrate support 104 in Figure 1 can be used with any processing chamber for plasma or heat treatment. During operation, the processing chamber 100 can provide real-time control of the plasma conditions within the processing space 120. The substrate 103 can be placed on the substrate support 104. The processing gas can be flowed through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gas can be discharged from the processing chamber 100 through the outlet 152. Power can be connected to the gas distributor 112 to establish the plasma within the processing space 120. In some embodiments, the substrate can be electrically biased using a third electrode 124.

[0026]

[0030] When the plasma is excited in the processing space 120, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. Subsequently, electronic controllers 134 and 140 can be used to adjust the flow characteristics of the ground path represented by two tuning circuits 128 and 136. Setpoints can be provided for the first tuning circuit 128 and the second tuning circuit 136 to provide independent control of the deposition rate and the uniformity of the plasma density from the center to the edge of the substrate. In embodiments where both electronic controllers are variable capacitors, these variable capacitors can be independently adjusted by electronic sensors to maximize the deposition rate and minimize thickness non-uniformity.

[0027]

[0031] The tuning circuits 128 and 136 may each have a variable impedance that can be adjusted using the corresponding electronic controllers 134 and 140. If the electronic controllers 134 and 140 are variable capacitors, the capacitance range of each variable capacitor, and the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, and the capacitance range of each variable capacitor may be minimized. Therefore, when the capacitance of the first electronic controller 134 is at its minimum or maximum, the impedance of the first tuning circuit 128 is high, resulting in a plasma shape with minimal space or lateral coverage above the substrate support. When the capacitance of the first electronic controller 134 reaches a value that minimizes the impedance of the first tuning circuit 128, the spatial coverage of the plasma can grow to its maximum, effectively covering the entire working area of ​​the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber wall, and the spatial coverage of the substrate support may decrease. The second electronic controller 140 has a similar effect, and as the capacitance of the second electronic controller 140 changes, the spatial coverage of the plasma above the substrate support may increase or decrease.

[0028]

[0032] Electronic sensors 130 and 138 may be used to tune corresponding circuits 128 and 136 in a closed loop. Depending on the type of sensor used, a setpoint for current or voltage may be attached to each sensor, and the sensors may be provided with control software that determines adjustments to the corresponding electronic controllers 134 and 140 to minimize deviation from the setpoint. As a result, the plasma shape can be selected and dynamically controlled during processing. The foregoing description is based on electronic controllers 134 and 140, which may be variable capacitors, but it should be understood that any electronic component with adjustable characteristics can be used to provide tuning circuits 128 and 136 with adjustable impedance.

[0029]

[0033] Figure 2 illustrates an exemplary operation of the deposition method 200 according to an embodiment of the present technology. This method may be carried out in various processing chambers, including the processing chamber 100 described above. Method 200 may include several arbitrary operations, which may or may not be specifically associated with certain embodiments of the method according to the present technology. For example, many operations are described to provide a broader range of structure formation, but may not be critical to the technology or may be performed by alternative methodologies for ease of understanding. Method 200 may illustrate the operations schematically shown in Figure 3-5B. These drawings are explained in conjunction with the operations of Method 200. It should be understood that the drawings are only partial schematics, and the substrate may include any number of additional materials and features having various properties and characteristics, as shown in the drawings.

[0030]

[0034] Method 200 may include additional operations before commencing the enumerated operations. For example, additional processing operations may include forming a structure on the semiconductor substrate, which may include both forming and removing material. Before delivering the substrate into the semiconductor processing chamber in which Method 200 may be carried out, processing operations may be carried out within the chamber in which Method 200 may be carried out, or within one or more other processing chambers. In any case, Method 200 may, in some cases, include delivering the semiconductor substrate to a processing area of ​​a semiconductor processing chamber, such as the processing chamber 100 described above, or another chamber that may include the components described above. The substrate may be deposited on a substrate support. The substrate support may be a pedestal, such as the substrate support 104, and may be located within a processing area of ​​a chamber, such as the processing space 120 described above. Before commencing deposition, an exemplary substrate 305 is shown in Figure 3.

[0031]

[0035] The substrate 305 can be any number of materials on which material can be deposited. The substrate may be a dielectric material containing silicon, germanium, silicon oxide, or silicon nitride, a metallic material, or any number of combinations of these materials (which may be the substrate 305, or the material formed on the substrate 305). In some embodiments, optional processing operations, such as pretreatment, may be performed to prepare the surface of the substrate 305 for deposition. For example, pretreatment may be performed to provide specific ligand ends on the surface of the substrate, which may facilitate the nucleation of the film to be deposited. Other molecular ends, such as amidogen or other functional groups, as an example not limited to hydrogen, oxygen, carbon, nitrogen, or any combination of these atoms or radicals, may be adsorbed, reacted, or formed on the surface of the substrate 305. Furthermore, any other operations may be performed to remove material, such as reduction of native oxides or etching of the material, or to prepare one or more exposed surfaces of the substrate 305 for deposition.

[0032]

[0036] In operation 205, one or more precursors may be delivered to the processing area of ​​the chamber. For example, in an exemplary embodiment in which a boron-incorporated silicon film may be formed, silicon-containing precursors and boron-containing precursors may be delivered to the processing area of ​​the processing chamber. In some embodiments of the art, plasma deposition may be carried out, which may facilitate the reaction and deposition of the material. As described above, some embodiments of the application may involve the formation or deposition of silicon and boron materials, which may be characterized by increased surface roughness compared to conventional silicon films, for example, thermally produced. The nucleation of these silicon and boron materials may, in some embodiments as shown in Figure 4A, form islands 405a on the substrate 305. These islands may be formed three-dimensionally to different heights during initial film formation, which may be maintained during film growth.

[0033]

[0037] Some embodiments of this technology may include further provision of a hydrogen-containing precursor in operation 210, which is provided as a silicon-containing precursor and a boron-containing precursor. The delivered precursors may all be used in operation 215 to form a plasma within the processing area of ​​the semiconductor processing chamber. In operation 220, the silicon and boron materials may be deposited on the substrate 305. In some embodiments, the incorporation of the hydrogen-containing precursor can reduce or limit the number of islands formed during nucleation.

[0034]

[0038] For example, as shown in Figure 4B, island 405b may form to a lower or lesser extent than island 405a. By incorporating an additional hydrogen source, film modification or profile etching may be carried out simultaneously with material deposition. For example, hydrogen radicals may trim island formation while a more uniform formation profile is generated through reactions and / or physical interactions with features formed in silicon and boron materials. As a result, the islands may not expand as much compared to conventional processes. To provide sufficient hydrogen radicals for processing, hydrogen-containing precursors may be included at a higher flow rate than one or both of the silicon-containing precursors or boron-containing precursors. For example, in some embodiments, the flow rate ratio of the hydrogen-containing precursor to either or both of the silicon-containing precursor and / or boron-containing precursor may be about 1:1 or greater, and in some embodiments, it may be about 2:1 or greater, about 3:1 or greater, about 4:1 or greater, about 5:1 or greater, about 6:1 or greater, about 8:1 or greater, about 10:1 or greater, about 15:1 or greater, about 20:1 or greater, about 25:1 or greater, about 30:1 or greater, about 35:1 or greater, about 40:1 or greater, about 45:1 or greater, about 50:1 or greater, or greater. As will be further described below, in some embodiments, further dilution may be carried out, and the ratio of hydrogen to the silicon and / or boron precursor may be about 100:1 or greater, about 500:1 or greater, about 1,000:1 or greater, about 1,500:1 or greater, about 2,000:1 or greater, about 2,500:1 or greater, or greater.

[0035]

[0039] For example, depending on the precursor used, silicon-containing precursors may be delivered at flow rates of approximately 500 sccm or less, approximately 400 sccm or less, approximately 300 sccm or less, approximately 200 sccm or less, approximately 100 sccm or less, approximately 90 sccm or less, approximately 80 sccm or less, approximately 70 sccm or less, approximately 60 sccm or less, approximately 50 sccm or less, or less. Similarly, boron-containing precursors may be delivered at flow rates of approximately 1,000 sccm or less, approximately 800 sccm or less, approximately 600 sccm or less, approximately 500 sccm or less, approximately 450 sccm or less, approximately 400 sccm or less, approximately 350 sccm or less, approximately 300 sccm or less, approximately 250 sccm or less, approximately 200 sccm or less, or less. Additional ranges may be used within these ranges, or in combinations of the numbers listed or not listed.

[0036]

[0040] Hydrogen-containing precursors may be delivered at flow rates of approximately 1,000 sccm or more, and may be delivered at flow rates of approximately 1,200 sccm or more, approximately 1,400 sccm or more, approximately 1,600 sccm or more, approximately 1,800 sccm or more, approximately 2,000 sccm or more, approximately 2,200 sccm or more, approximately 2,400 sccm or more, approximately 2,600 sccm or more, approximately 2,800 sccm or more, approximately 3,000 sccm or more, or higher. Increasing the amount of hydrogen-containing precursor may make the surface of the deposited membrane smoother, but it may also increase hydrogen uptake within the deposited membrane. Therefore, in some embodiments, the hydrogen-containing precursor may be delivered at a flow rate of about 4,000 sccm or less, and may be delivered at a flow rate of about 3,800 sccm or less, about 3,600 sccm or less, about 3,400 sccm or less, about 3,200 sccm or less, about 3,000 sccm or less, about 2,800 sccm or less, about 2,600 sccm or less, or less. Furthermore, in some embodiments where higher dilution may be performed, the hydrogen-containing precursor may be delivered at a flow rate of about 5,000 sccm or more, and may be delivered at a flow rate of about 10,000 sccm or more, about 15,000 sccm or more, about 20,000 sccm or more, about 25,000 sccm or more, or more. In some embodiments, the flow rate of the silicon or boron precursor may be further reduced to about 200 sccm or less, or to about 150 sccm or less, about 100 sccm or less, about 50 sccm or less, about 30 sccm or less, about 20 sccm or less, about 10 sccm or less, or less.

[0037]

[0041] The film can be deposited on the substrate 305 to any thickness. The surface roughness of the resulting film may not be limited to problems during film nucleation as described above. For example, film growth and plasma termination may also affect surface roughness in some aspects of this technique. For example, once sufficient film growth has occurred, the process may be stopped by extinguishing the plasma in the processing chamber, for example, by cutting off power to the plasma generating electrode. Plasma termination may also increase surface roughness by causing physical interactions of a certain amount of residual ions after deposition is complete. It can be assumed that both the effects of nucleation and plasma termination are consistent regardless of the thickness of the formed film. However, tests have shown that the roughness of the deposited film increases with increasing film thickness. Consequently, the effect of roughness also occurs during film growth, and as film thickness increases, the film roughness may further increase. As shown in Figure 5A, islands 405a formed during nucleation may not only be maintained but may also grow or expand during deposition without one or more of the properties described throughout this technique. Therefore, the resulting film 505a may be characterized by an increase in roughness, which can affect the uniformity of subsequent etching.

[0038]

[0042] For example, thermally generated silicon, such as polysilicon or other silicon materials, may be characterized by a relatively low average roughness of about 0.5 nm or less, or about 0.2 nm or less. The film may also be characterized by a relatively low range of roughness, such as the difference between the highest and lowest peaks on the formed film. For example, the roughness range may be about 1.5 nm or less, or about 1 nm or less. However, for silicon and boron films produced without using one or more embodiments of this technique, as described, the roughness may increase with increasing film thickness, but for films of similar thickness, the average roughness may be about 2 nm or more, about 3 nm or more, or greater. Furthermore, the range of roughness of the generated silicon and boron materials may also be about 10 nm or more, or about 15 nm or more, depending on the film thickness. During subsequent etching operations, these greater imbalances across the film may pose a challenge to the uniformity of the etching operation, and additional operations, such as additional chemical mechanical polishing operations, may be required.

[0039]

[0043] However, this technique can reduce or significantly reduce both the average roughness and the roughness range of the resulting silicon and boron films by performing substantially simultaneous etching using an additional hydrogen-containing precursor, or by performing one or more additional adjustments detailed below. As shown in Figure 5B, the resulting film 505b may feature an average roughness of about 2 nm or less, and may feature an average roughness of about 1.5 nm or less, about 1.0 nm or less, about 0.9 nm or less, about 0.8 nm or less, about 0.7 nm or less, about 0.6 nm or less, about 0.5 nm or less, about 0.4 nm or less, about 0.3 nm or less, about 0.2 nm or less, or less. Furthermore, roughness can be substantially controlled regardless of film thickness in some embodiments. Since the as-deposited film may feature any of the indicated average roughness ranges, this may allow for the avoidance of additional chemical mechanical polishing operations. Furthermore, the overall roughness range of the deposited film may be approximately 10 nm or less, and may be approximately 9 nm or less, approximately 8 nm or less, approximately 7 nm or less, approximately 6 nm or less, approximately 5 nm or less, approximately 4 nm or less, approximately 3 nm or less, approximately 2 nm or less, approximately 1 nm or less, or even smaller. As a result, improved materials can be manufactured, not only providing advantages in film and mask compared to conventional materials and processes, but also potentially reducing manufacturing operations by limiting or reducing the number of polishing operations in the sequence.

[0040]

[0044] With respect to silicon-containing precursors and boron-containing precursors, any number of precursors can be used in this technology. For example, silicon-containing precursors may include any silicon-containing material such as silanes, disilanes, and organosilanes that may contain other materials. Additional silicon-containing materials may include silicon, carbon, oxygen, or nitrogen, such as trisilylamines. Boron-containing materials may include boranes such as boranes, diboranes, or other multicenter-bonded boron materials, as well as any other boron-containing materials that can be used to produce silicon and boron-containing materials. The incorporation of boron into the silicon film may be based on the incorporation of any percentage. For example, the resulting film may contain approximately 5% or more boron uptake, and in some embodiments, it may contain approximately 10% or more boron uptake, approximately 15% or more boron uptake, approximately 20% or more boron uptake, approximately 25% or more boron uptake, approximately 30% or more boron uptake, approximately 35% or more boron uptake, approximately 40% or more boron uptake, approximately 45% or more boron uptake, approximately 50% or more boron uptake, approximately 55% or more boron uptake, approximately 60% or more boron uptake, approximately 65% ​​or more boron uptake, approximately 70% or more boron uptake, approximately 75% or more boron uptake, approximately 80% or more boron uptake, approximately 85% or more boron uptake, approximately 90% or more boron uptake, approximately 95% or more boron uptake, or more boron uptake.

[0041]

[0045] One or more additional aspects of the deposition can also be adjusted to improve the deposition aspect being implemented. For example, plasma power can affect the degree of hydrogen dissociation. Any number of hydrogen-containing precursors may be used, and in some embodiments, diatomic hydrogen may be included. For some silicon and boron-containing materials, minimal plasma enhancement may be included, as the material is sufficiently reactive at the deposition temperature. For example, some conventional techniques utilize plasma power of about 200 watts or less. This technique can utilize higher or much higher plasma power (which can promote hydrogen dissociation) and increase hydrogen radicals (which can reduce roughness as previously described).

[0042]

[0046] For example, in some embodiments, the plasma output may be maintained at approximately 1,000 watts or more, approximately 1,200 watts or more, approximately 1,400 watts or more, approximately 1,600 watts or more, approximately 1,800 watts or more, approximately 2,000 watts or more, approximately 2,200 watts or more, approximately 2,400 watts or more, approximately 2,600 watts or more, approximately 2,800 watts or more, approximately 3,000 watts or higher. This enhanced plasma output may also improve the dissociation and activation of other precursors, which may similarly increase the deposition rate. As a result, despite the simultaneous etching of the material during deposition, the film deposition rate may be comparable to, if not improved compared to, conventional deposition. Next, deposition and simultaneous etching for profile correction may be maintained continuously or sequentially until the target film thickness is achieved. Depending on the plasma treatment being performed, the plasma power density may also be maintained, which may allow for adjustment of frequency and output. For example, in some embodiments, the plasma power density is approximately 0.25 W / cm² 2 The level may be maintained above approximately 0.5 W / cm². 2 Above, approximately 1.0W / cm 2 Above, approximately 1.5W / cm 2 Above, approximately 2.0W / cm 2 Above, approximately 2.5W / cm 2 It may be maintained at or above that level.

[0043]

[0047] The substrate temperature can further affect deposition. For example, in some embodiments, the substrate may be maintained at a temperature of about 400°C or higher, and may be maintained at about 420°C or higher, about 440°C or higher, about 460°C or higher, about 480°C or higher, about 500°C or higher, or higher. By carrying out deposition according to some embodiments of the art, hydrogen etching may be performed during deposition to reduce the roughness of the formed film. However, the amount of hydrogen radicals generated by enhanced plasma and hydrogen delivery may also increase the amount of hydrogen uptake into the resulting film. This can increase the compressive stress within the film. For example, the as-deposited film may be characterized by a compressive stress of about -800 MPa or higher, which may be partly due to hydrogen uptake. Consequently, in some embodiments, method 200 may include actions to reduce hydrogen uptake into the film.

[0044]

[0048] For example, in some embodiments, method 200 may include, in an optional operation 225, thermal annealing of the formed silicon and boron-containing material. While deposition may be carried out at a first temperature, thermal annealing may be carried out at a second temperature higher than the first temperature. For example, thermal annealing may be carried out at a temperature of about 480°C or higher, and may be carried out at a temperature of about 500°C or higher, about 510°C or higher, about 520°C or higher, about 530°C or higher, about 540°C or higher, about 550°C or higher, about 560°C or higher, about 570°C or higher, about 580°C or higher, about 590°C or higher, about 600°C or higher, or higher. Thermal annealing may be carried out for a period of time that may be about 0.5 minutes or more, about 1 minute or more, about 2 minutes or more, about 3 minutes or more, about 4 minutes or more, about 5 minutes or more, about 6 minutes or more, or longer.

[0045]

[0049] By performing thermal annealing, a certain amount of hydrogen incorporated into the membrane may be removed, which can relieve compressive stress. For example, in some embodiments, after thermal annealing, the compressive stress in the membrane may be maintained at approximately -700 MPa or less, approximately -650 MPa or less, approximately -600 MPa or less, approximately -550 MPa or less, approximately -500 MPa or less, approximately -450 MPa or less, approximately -400 MPa or less, approximately -350 MPa or less, approximately -300 MPa or less, approximately -250 MPa or less, approximately -200 MPa or less, approximately -150 MPa or less, approximately -100 MPa or less, or less.

[0046]

[0050] The pressure within the processing area can affect the amount of ionization and physical interactions that occur during deposition. Reducing the processing pressure can lead to an increase in ionic interactions. Therefore, in some embodiments, the processing pressure during deposition may be maintained at or below about 50 Torr, or at or below about 40 Torr, 30 Torr, 20 Torr, 15 Torr, 10 Torr, 9 Torr, 8 Torr, 7 Torr, 6 Torr, 5 Torr, 4 Torr, 3 Torr, 2 Torr, or less.

[0047]

[0051] Tests have shown that argon incorporation can increase roughness, and therefore, limiting or excluding argon can improve film roughness. However, when argon is excluded from the treatment precursor, tests have shown that film delamination can increase. Therefore, in some embodiments, argon may be included in silicon-containing and boron-containing precursors. To limit the effect on roughness, the flow rate ratio of the argon precursor to the hydrogen-containing precursor may be maintained at about 2:1 or less, and may be maintained at about 1:1 or less, about 0.8:1 or less, about 0.7:1 or less, about 0.6:1 or less, about 0.5:1 or less, about 0.4:1 or less, about 0.3:1 or less, about 0.2:1 or less, about 0.1:1 or less, or less.

[0048]

[0052] Combinations or further adjustments of processing parameters may also affect and improve additional aspects of the resulting film. Incorporating boron into the hard mask film can improve selectivity for many films. Since the film stack contains more material related to both the hard mask opening operation and subsequent film etching, providing improved selectivity can further reduce the number of additional operations performed. Increasing the crystallinity of the film can also increase etching selectivity; however, in conventional techniques, increased crystallinity has resulted in decreased or worsened line edge roughness and line width roughness. As a result, many techniques attempt to maintain the film as amorphous silicon. This technique may at least partially increase the crystallinity of the formed film, which may increase etching selectivity, but by limiting the crystallinity, this technique can maintain line edge roughness and line width roughness.

[0049]

[0053] Compared to silicon and boron precursors, the degree of crystallinity can be increased when the increased hydrogen flow rate ratio according to the embodiment of this technology is utilized. However, by utilizing the aforementioned processing parameters, the degree of crystallinity may be maintained at approximately 50 Å or less, approximately 40 Å or less, approximately 30 Å or less, approximately 20 Å or less, approximately 15 Å or less, approximately 10 Å or less, approximately 7 Å or less, approximately 5 Å or less, approximately 3 Å or less, but when the degree of crystallinity increases to approximately 2 Å or more, improved etching selectivity can be obtained.

[0050]

[0054] However, increased hydrogen inclusion in the plasma can also increase hydrogen uptake into the film. This can affect film stress, as mentioned earlier, and may further affect other film properties. For example, hard mask films may feature different extinction coefficients at different wavelengths, which can affect lithography operation. Amorphous silicon materials may feature extinction coefficients at a specific parameter of about 0.2, which can enable lithography at film thicknesses up to about 800 nm based on lower reflectivity and affect visibility through the mask. Silicon and boron films may feature increased extinction coefficients at similar parameters, but increased hydrogen uptake can at least partially decrease the extinction coefficient. For example, increased boron uptake can increase the extinction coefficient to about 0.3 or higher, about 0.35 or higher, about 0.4 or higher, about 0.45 or higher, or significantly more.

[0051]

[0055] The effect of a higher extinction coefficient of light is that lithography may become difficult and may require additional processing. For example, these increases in extinction coefficients may limit the visibility of lithography to approximately 400 nm or less, approximately 300 nm or less, or even lower. However, by utilizing the increased plasma density to increase hydrogen uptake, the extinction coefficient may decrease to approximately 0.35 or less, approximately 0.33 or less, approximately 0.30 or less, approximately 0.28 or less, approximately 0.25 or even lower. This may allow lithography to be extended to thicknesses of approximately 400 nm or more, approximately 450 nm or more, approximately 500 nm or more, or even greater, without performing additional alignment key release operations. By increasing the temperature and plasma properties, even with increased hydrogen uptake, film structures may be formed to improve properties such as extinction coefficient and etching selectivity. Hydrogen uptake can also be increased by processing at lower temperatures, such as below 400°C or approximately below 350°C; however, differences in the resulting membrane properties may lead to additional hydrogen gas release in subsequent processing, as mentioned above. By performing processing at higher temperatures, increased thermal stability can be obtained in the membrane that has incorporated the increased hydrogen as described above.

[0052]

[0056] Plasma properties can be adjusted in some embodiments by both power and frequency. For example, at lower frequencies such as below approximately 20 MHz, including 13.56 MHz, the described film properties can be produced by plasma powers of, for example, above approximately 2000 W or above approximately 2500 W. It should be understood that other plasma properties may also be used. For example, plasma power can also be adjusted by adjusting the plasma frequency. As the plasma frequency increases, for example above approximately 40 MHz, above approximately 60 MHz, and even into the microwave frequency range, the plasma power decreases accordingly, and the stability and resilience of the chamber can be improved. FTIR analysis has shown that with these plasma properties, the peaks related to boron and hydrogen may increase in transmittance and shift slightly to higher wavelengths. This may indicate improved stability of the structure, thereby allowing for increased thermal stability of the film during subsequent processing. As a result, in some embodiments, a lower extinction coefficient and improved thermal stability can also be obtained by increasing the crystallinity. By carrying out deposition according to embodiments of this technique, the roughness of silicon and boron-containing films may be reduced, thereby improving the effectiveness of the hard mask. During subsequent etching in the optional operation 230, the etching limit dimensions can be maintained more uniformly with this technique than when the technique is not implemented. By reducing surface roughness, improved etching and structural development can be obtained.

[0053]

[0057] The above description provides numerous details for illustrative purposes to facilitate understanding of various embodiments of this technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented without some of these details, or with additional details.

[0054]

[0058] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the above description should not be considered to limit the scope of the Art. Moreover, while methods or processes may be described sequentially or stepwise, it should be understood that the operations may be performed simultaneously or in a different order than described.

[0055]

[0059] Where a range of values ​​is provided, unless explicitly stated otherwise in the context, each intermediary value between the upper and lower limits of that range is, of course, specifically disclosed down to the smallest unit of the lower limit. Any narrow range between any stated or unstated intermediary values ​​within the stated range, and any other stated or intermediary values ​​within that stated range are also included. The upper and lower limits of these smaller ranges may be included in or excluded from the range individually, and each range that includes one, neither, or both of the limit values ​​is also included in this technical scope, subject to any explicitly excluded limit values ​​in the stated range. Where one or both limit values ​​are included in the stated range, the range that excludes one or both of these included limit values ​​is also included.

[0056]

[0060] As used herein and in the claims, the singular forms “a,” “an,” and “the” include multiple references unless the context clearly indicates otherwise. Thus, for example, “a precursor” refers to multiple such precursors, and “the layer” refers to one or more layers and equivalents well known to those skilled in the art, and the same applies to other forms.

[0057]

[0061] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described features, integers, components, or steps, but not to exclude the presence or addition of one or more other features, integers, components, actions, functions, or groups.

Claims

1. A method for depositing material such that surface roughness is reduced, The silicon-containing precursor and the boron-containing precursor are delivered to the processing area of ​​the semiconductor processing chamber. The present invention provides a hydrogen-containing precursor together with the silicon-containing precursor and the boron-containing precursor, wherein the flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor is approximately 1:1 or greater. Forming plasma of all precursors within the processing region of the semiconductor processing chamber, Depositing silicon and boron materials on a substrate placed within the processing area of ​​the semiconductor processing chamber. Includes, A method in which the plasma power density is maintained at about 1.5 W / cm² or higher while the plasma of all precursors is formed within the processing region of the semiconductor processing chamber.

2. The method according to claim 1, characterized in that the silicon and boron materials have a surface roughness of about 2 nm or less while deposited.

3. While forming the plasma of all precursors within the processing region of the semiconductor processing chamber, the plasma power density is approximately 2.0 W / cm². ２ The method according to claim 1, which is maintained as described above.

4. The method according to claim 1, wherein the substrate temperature is maintained at approximately 400°C or higher while the silicon and boron materials are deposited on the substrate.

5. The method according to claim 1, wherein the pressure is maintained at about 10 Torr or less while depositing the silicon and boron materials on the substrate.

6. The method according to claim 1, further comprising providing an argon precursor together with the silicon-containing precursor and the boron-containing precursor.

7. The method according to claim 1, further comprising performing thermal annealing of the silicon and boron materials after the deposition.

8. The method according to claim 1, wherein the silicon-containing precursor contains silane and the boron-containing precursor contains diborane.

9. A method for depositing material such that surface roughness is reduced, The silicon-containing precursor and the boron-containing precursor are delivered to the processing area of ​​the semiconductor processing chamber. Plasma of the silicon-containing precursor and the boron-containing precursor is formed within the processing area of ​​the semiconductor processing chamber. The method involves depositing silicon and boron materials on a substrate placed within the processing area of ​​the semiconductor processing chamber, wherein the silicon and boron materials are characterized by having a surface roughness of approximately 2 nm or less while deposited. Includes, A method in which the plasma power density is maintained at approximately 1.5 W / cm² or higher while the plasma of all precursors is formed within the processing region of the semiconductor processing chamber.

10. The method according to claim 9, further comprising providing a hydrogen-containing precursor together with the silicon-containing precursor and the boron-containing precursor, wherein the flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor is approximately 2:1 or greater.

11. The method according to claim 10, further comprising providing an argon precursor together with the silicon-containing precursor and the boron-containing precursor, wherein the flow rate ratio of the argon precursor to the hydrogen-containing precursor is about 1:1 or less.

12. The method according to claim 9, further comprising thermal annealing the silicon and boron materials for a first period after the deposition.

13. The method according to claim 12, wherein during the deposition, the substrate is maintained at a first temperature, and while the silicon and boron materials are thermally annealed, the substrate is maintained at a second temperature, the second temperature being higher than the first temperature.

14. The method according to claim 13, wherein the second temperature is approximately 500°C or higher.

15. The method according to claim 9, wherein the plasma output is maintained at approximately 2.0 kW or more while the plasma of the silicon-containing precursor and the boron-containing precursor is formed in the processing region of the semiconductor processing chamber.

16. A method for depositing material such that surface roughness is reduced, The silicon-containing precursor and the boron-containing precursor are delivered to the processing area of ​​the semiconductor processing chamber. The process involves forming a plasma of all precursors within the processing region of the semiconductor processing chamber, wherein the plasma power density is approximately 1.5 W / cm² during the formation of the plasma of all precursors within the processing region of the semiconductor processing chamber. ２ To maintain the above, to form a plasma, Depositing silicon and boron materials on a substrate placed within the processing area of ​​the semiconductor processing chamber. Methods that include...

17. The method according to claim 16, further comprising providing a hydrogen-containing precursor together with the silicon-containing precursor and the boron-containing precursor, wherein the flow rate ratio of the hydrogen-containing precursor to either the silicon-containing precursor or the boron-containing precursor is about 2:1 or more.

18. The method according to claim 17, further comprising providing an argon precursor together with the silicon-containing precursor and the boron-containing precursor, wherein the flow rate ratio of the argon precursor to the hydrogen-containing precursor is about 1:1 or less.

19. The method according to claim 16, further comprising performing thermal annealing of the silicon and boron materials for a first period after the deposition.

20. The method according to claim 19, wherein during the deposition, the substrate is maintained at a first temperature, and during the thermal annealing of the silicon and boron materials, the substrate is maintained at a second temperature, the second temperature being higher than the first temperature.

Images