Capacitor, memory, and method for manufacturing memory

The gradient Sr/(Sr+Ti) ratio in the strontium titanate dielectric layer addresses the challenge of achieving high memory density and low leakage in DRAM chips, enhancing signal resolution and reducing capacitor size.

JP7868194B2Active Publication Date: 2026-06-01SWAYSURE TECHNOLOGY CO LTD
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
SWAYSURE TECHNOLOGY CO LTD
Filing Date
2024-05-20
Publication Date
2026-06-01

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Abstract

The present application relates to a capacitor, a memory, and a method for manufacturing a memory, the capacitor including a first electrode layer, a second electrode layer, and a strontium titanate dielectric layer formed between the first electrode layer and the second electrode layer, wherein the Sr / (Sr+Ti) ratio in the strontium titanate dielectric layer gradually decreases from the center of the strontium titanate dielectric layer toward both opposing sides of the strontium titanate dielectric layer, one of the opposing sides of the strontium titanate dielectric layer being closer to the first electrode layer and the other being closer to the second electrode layer.
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