Semiconductor equipment

Abstract

To provide a semiconductor device with a built-in control circuit.SOLUTION: A main element includes a first electrode, a second electrode located away from the first electrode in a first direction along a first surface of a support, a first semiconductor layer provided between the first and second electrodes in the first direction and forming a first Schottky junction with the second electrode, and a first gate electrode facing the first Schottky junction in a second direction. A control element includes a third electrode, a fourth electrode located away from the third electrode in a fourth direction, a second semiconductor layer provided between the third and fourth electrodes in the fourth direction and forming a second Schottky junction with the fourth electrode, and a second gate electrode facing the second Schottky junction in a fifth direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] There is a demand for a chip incorporating a control circuit in a power semiconductor device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention aim to provide a semiconductor device incorporating a control circuit.

Means for Solving the Problems

[0005] According to an embodiment of the present invention, a semiconductor device includes a support having a first surface, a main element provided on the support, and a control element provided on the support for controlling the main element. The main element has a first electrode, a second electrode located away from the first electrode in a first direction along the first surface, a first semiconductor layer provided between the first electrode and the second electrode in the first direction and forming a first Schottky junction with the second electrode, and a first gate electrode facing the first Schottky junction in a second direction intersecting the first direction along the first surface. The control element has a third electrode, a fourth electrode located away from the third electrode in a fourth direction along the first surface, a second semiconductor layer provided between the third electrode and the fourth electrode in the fourth direction and forming a second Schottky junction with the fourth electrode, and a second gate electrode facing the second Schottky junction in a fifth direction intersecting the fourth direction along the first surface. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic cross-sectional view of the semiconductor device according to the embodiment. [Figure 2] This is a schematic perspective view of the main element of the semiconductor device according to the embodiment. [Figure 3] This is a schematic perspective view of the main element of the semiconductor device according to the embodiment. [Figure 4] This is a schematic cross-sectional view of the main element of the semiconductor device according to the embodiment. [Figure 5] (a) and (b) are schematic perspective views of the main elements of the semiconductor device according to the embodiment. [Figure 6] This is a schematic perspective view of the control element of the semiconductor device according to the embodiment. [Figure 7] This is a schematic cross-sectional view of the control element of the semiconductor device according to the embodiment. [Figure 8] (a) is a circuit diagram of the control circuit of the semiconductor device according to the embodiment, and (b) is a schematic cross-sectional view of the control elements forming the control circuit. [Figure 9] (a) is a circuit diagram of the control circuit of the semiconductor device according to the embodiment, and (b) is a schematic cross-sectional view of the control elements forming the control circuit. [Figure 10] (a) is a circuit diagram of the control circuit of the semiconductor device according to the embodiment, and (b) is a schematic cross-sectional view of the control elements forming the control circuit. [Figure 11] (a) is a circuit diagram of the control circuit of the semiconductor device according to the embodiment, and (b) is a schematic cross-sectional view of the control elements forming the control circuit. [Modes for carrying out the invention]

[0007] Each embodiment will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. Furthermore, identical or similar elements are assigned the same symbol.

[0008] As shown in Figure 1, the semiconductor device 1 of the embodiment comprises a main element 110 and a control element 120. The main element 110 is a power semiconductor element that controls or converts power. The control element 120 controls the main element 110. For example, a control circuit that controls the main element 110 is formed by a plurality of control elements 120.

[0009] The semiconductor device 1 further comprises a support 100. As shown in Figure 2, the main element 110 is provided on the support 100. As shown in Figure 6, the control element 120 is provided on the support 100.

[0010] As shown in Figure 2, the support 100 has a first surface 100A. One direction parallel to the first surface 100A is defined as the X-axis direction. A direction parallel to the first surface 100A and perpendicular to the X-axis direction is defined as the Y-axis direction. A direction perpendicular to both the X-axis and Y-axis directions is defined as the Z-axis direction. The first surface 100A is perpendicular to the Z-axis direction. For example, in this specification, the direction along the Y-axis is defined as the first direction Y, the direction along the X-axis is defined as the second direction X, and the direction along the Z-axis is defined as the third direction Z.

[0011] The main element 110 will be described with reference to Figures 2 to 5(b). Figure 3 shows the state in which the second conductive part 22b and the second insulating member 42 have been removed.

[0012] The support 100 has a substrate 101. For example, a silicon substrate can be used as the substrate 101. The main element 110 has a first semiconductor layer 11 provided on the substrate 101 in a third direction Z. The support 100 may further have an insulating layer 102 provided between the substrate 101 and the first semiconductor layer 11 in a third direction Z. In this example, the upper surface of the insulating layer 102 becomes the first surface 100A of the support 100. For example, a silicon oxide layer can be used as the insulating layer 102.

[0013] The conductivity type of the first semiconductor layer 11 is the first conductivity type. The first conductivity type is one of n-type and p-type. Hereinafter, the first conductivity type is assumed to be n-type. The first semiconductor layer 11 is, for example, a silicon layer. The first semiconductor layer 11 may be a silicon carbide layer or a gallium nitride layer.

[0014] The main element 110 further includes a first electrode 21 and a second electrode 22. The first electrode 21 and the second electrode 22 are located apart from each other in the first direction Y. The first semiconductor layer 11 is provided between the first electrode 21 and the second electrode 22 in the first direction Y and is electrically connected to the first electrode 21 and the second electrode 22. The first electrode 21, the second electrode 22, and the first semiconductor layer 11 extend in the third direction Z above the first surface 100A. Above is the direction from the substrate 101 toward the first semiconductor layer 11. Above is the direction from the second surface 101B toward the first surface 100A. Below is the opposite direction of above. Above and below are directions independent of the gravitational direction. With such a configuration, the density of the main element 110 can be increased on the first surface 100A of the support 100, and for example, the on-resistance per unit area can be lowered.

[0015] The first electrode 21 can include, for example, at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt.

[0016] The second electrode 22 has a first conductive portion 22a and a second conductive portion 22b. The first conductive portion 22a is in contact with the first semiconductor layer 11. The first semiconductor layer 11 and the first conductive portion 22a form a first Schottky junction S1. The first conductive portion 22a is located between the first semiconductor layer 11 and the second conductive portion 22b in the first direction Y. The second conductive portion 22b is electrically connected to the first conductive portion 22a.

[0017] The first conductive portion 22a can include, for example, at least one selected from the group consisting of Ti, W, Mo, Ta, Zr, Al, Sn, V, Re, Os, Ir, Pt, Pd, Rh, Ru, Nb, Sr, and Hf. The second conductive portion 22b can include, for example, at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt.

[0018] The main element 110 further has a first gate electrode 31. A plurality of first gate electrodes 31 are arranged in the second direction X. The first gate electrode 31 faces the first Schottky junction S1 in the second direction X. As the material of the first gate electrode 31, for example, polycrystalline silicon can be used. As shown in FIG. 3, the first gate electrode 31 extends in the third direction Z. With such a configuration, transistors can be provided at a high density on the first surface 100A of the support 100, and the channel area per unit area can be increased. Thereby, for example, the on-resistance can be reduced. In the main element 110, since no current flows through the support 100, even if the thickness of the support 100 in the third direction Z is increased to enhance mechanical strength, the on-resistance does not increase.

[0019] A potential higher than the potential of the second electrode 22 is applied to the first electrode 21, and a potential lower than the potential of the first electrode 21 (for example, a ground potential) is applied to the second electrode 22. The first electrode 21 functions as a drain electrode, and the second electrode 22 functions as a source electrode. In addition, the n-type impurity concentration in the region of the first semiconductor layer 11 in contact with the first electrode 21 may be made higher than the n-type impurity concentration in other regions. Thereby, the contact resistance between the first electrode 21 and the first semiconductor layer 11 can be reduced.

[0020] The thickness of the Schottky barrier (distance in the first direction Y) at the first Schottky junction S1 can be controlled by the potential of the first gate electrode 31. When the Schottky barrier is thick, current does not substantially flow between the second electrode 22 and the first semiconductor layer 11. Thereby, an off state is obtained. In the off state, a depletion layer spreads from the first Schottky junction S1 into the first semiconductor layer 11, and the breakdown voltage can be maintained.

[0021] By controlling the potential of the first gate electrode 31, the Schottky barrier is thinned, allowing a tunnel current to flow between the second electrode 22 and the first semiconductor layer 11. The flow of this tunnel current results in an ON state.

[0022] The main element 110 may further include a field plate electrode 51, a first insulating member 41, and a second insulating member 42.

[0023] The field plate electrode 51 is provided within a trench formed in the first semiconductor layer 11 and extends in the first direction Y and the third direction Z. The field plate electrode 51 is electrically connected to, for example, the second electrode 22. The field plate electrode 51 can mitigate the electric field applied to the first semiconductor layer 11 in the first direction Y, thereby increasing the breakdown voltage. For example, polycrystalline silicon can be used as the material for the field plate electrode 51.

[0024] The first insulating member 41 is provided between the first gate electrode 31 and the first semiconductor layer 11, between the field plate electrode 51 and the first semiconductor layer 11, between the first gate electrode 31 and the field plate electrode 51, and between adjacent first gate electrodes 31 in the second direction X, and extends in the third direction Z. The first insulating member 41 has a first gate insulating portion 41a. The first gate insulating portion 41a is provided between the first gate electrode 31 and the first semiconductor layer 11, between the first gate electrode 31 and the first Schottky junction S1, and between the first gate electrode 31 and the first conductive portion 22a. The first gate electrode 31 faces the first Schottky junction S1 in the second direction X via the first gate insulating portion 41a. For example, silicon oxide can be used as the material for the first insulating member 41.

[0025] The second insulating member 42 is provided between the first gate electrode 31 and the second conductive portion 22b, and between the first insulating member 41 and the second conductive portion 22b, and extends in the third direction Z. For example, silicon oxide can be used as the material for the second insulating member 42.

[0026] As shown in Figure 5(a), the substrate 101 has a second surface 101B located opposite the first surface 100A in the third direction Z. An interlayer insulating layer (shown by a dashed line) 300 is provided so as to be in contact with the upper part of the first semiconductor layer 11. A first wiring section D is provided on the second surface 101B of the substrate 101, which is electrically connected to the first electrode 21. The first electrode 21 can be electrically connected to an external circuit via the first wiring section D. A portion of the first wiring section D is located below the semiconductor device 1 and is exposed. A portion of the first wiring section D extends parallel to the first direction Y and the second direction X. The substrate 101 is located between the first wiring section D and the first semiconductor layer 11. In the third direction Z, a second wiring section S can be provided above the first semiconductor layer 11, above the first gate electrode 31, and above the field plate electrode 51, via the interlayer insulating layer. The second wiring section S is electrically connected to the second conductive portion 22b of the second electrode 22. The second electrode 22 can be electrically connected to an external circuit via the second wiring section S. A portion of the second wiring section S is located above the semiconductor device 1 and is exposed. The portion of the second wiring section S extends parallel to the first direction Y and the second direction X. An interlayer insulating layer 300 is located between the portion of the second wiring section S and the first semiconductor layer 11. Exposure refers to being present on the surface of the semiconductor element and not necessarily on the surface of the package material such as resin or ceramic. A first gate wiring G1 extending in the second direction X is provided on a plurality of first gate electrodes 31 aligned in the second direction X, and the plurality of first gate electrodes 31 can be electrically connected to the first gate wiring G1. The first gate wiring G1 is located in the interlayer insulating layer 300. The first gate wiring G1 may be located above the semiconductor device 1 and may be exposed. The semiconductor device 1 can be placed, for example, with the second wiring section S in contact with the electrodes of an external circuit. The wiring sections of the semiconductor device 1, other than the second wiring section S, are exposed from above the semiconductor device 1 and connected to external circuits by means of wire bonding or the like. In the semiconductor device 1, the exposed area of ​​the first wiring section D and the second wiring section S, which are the main current paths, and thus the contact area with external circuits can be increased.

[0027] Alternatively, as shown in Figure 5(b), a second wiring section S electrically connected to the second conductive portion 22b of the second electrode 22 may be provided on the second surface 101B of the substrate 101. In the third direction Z, a first wiring section D electrically connected to the first electrode 21 via an interlayer insulating layer can be provided above the first semiconductor layer 11, above the first gate electrode 31, and above the field plate electrode 51. A portion of the first wiring section D is located above the semiconductor device 1 and is exposed. A portion of the first wiring section D extends parallel to the first direction Y and the second direction X. A portion of the second wiring section D is located below the semiconductor device 1 and is exposed. A portion of the second wiring section S extends parallel to the first direction Y and the second direction X.

[0028] As shown in Figure 1, the area of ​​the region where the main element 110 is provided is larger than the area of ​​the region where the control element 120 is provided. In the region where the main element 110 of the semiconductor device 1 is provided, multiple cell groups (first to fourth cell groups 71 to 74) are provided. A cell group refers to a group of cells of the main element 110 that share the first semiconductor layer 11. In the first direction Y, the second cell group 72 is located between the first cell group 71 and the fourth cell group 74, and the third cell group 73 is located between the second cell group 72 and the fourth cell group 74. In each cell group, the structure shown in Figures 2 to 4 described above is repeated multiple times in the second direction X.

[0029] The direction from the first electrode 21 of the first cell group 71 to the second electrode 22 of the first cell group 71 is the opposite of the direction from the first electrode 21 of the second cell group 72 to the second electrode 22 of the second cell group 72. The direction from the first electrode 21 of the third cell group 73 to the second electrode 22 of the third cell group 73 is the opposite of the direction from the first electrode 21 of the fourth cell group 74 to the second electrode 22 of the fourth cell group 74. The direction from the first electrode 21 of the first cell group 71 to the second electrode 22 of the first cell group 71 is the same as the direction from the first electrode 21 of the third cell group 73 to the second electrode 22 of the third cell group 73. The direction from the first electrode 21 of the second cell group 72 to the second electrode 22 of the second cell group 72 is the same as the direction from the first electrode 21 of the fourth cell group 74 to the second electrode 22 of the fourth cell group 74.

[0030] In the second cell group 72 and the third cell group 73, the first electrode 21 is shared. In the first cell group 71 and the second cell group 72, the second electrode 22 is shared. In the third cell group 73 and the fourth cell group 74, the second electrode 22 is shared.

[0031] The main element 110 can, for example, constitute a high-side switching element and a low-side switching element in a voltage converter.

[0032] Next, the control element 120 will be described with reference to Figures 6 and 7.

[0033] For example, the control element 120 is provided on the same substrate 101 as the main element 110, the fourth direction of the control element 120 coincides with the first direction Y of the main element 110, the fifth direction of the control element 120 coincides with the second direction X of the main element 110, and the sixth direction of the control element 120 coincides with the third direction Z of the main element 110. The control element 120 is located apart from the main element 110 in the XY plane. The control element 120 has a second semiconductor layer 12 provided on the substrate 101 in the third direction (sixth direction) Z. The conductivity type of the second semiconductor layer 12 is the first conductivity type. The material of the second semiconductor layer 12 can be the same material as the first semiconductor layer 11 of the main element 110.

[0034] The control element 120 further comprises a third electrode 23 and a fourth electrode 24. The third electrode 23 and the fourth electrode 24 are located apart from each other in one direction on the XY plane, for example, in the first direction (fourth direction) Y. The second semiconductor layer 12 is provided between the third electrode 23 and the fourth electrode 24 in the first direction (fourth direction) Y and is electrically connected to the third electrode 23 and the fourth electrode 24. The third electrode 23, the fourth electrode 24, and the second semiconductor layer 12 extend in the third direction (sixth direction) Z above the first surface 100A of the support 100.

[0035] The fourth electrode 24 has a third conductive portion 24a and a fourth conductive portion 24b. The third conductive portion 24a is in contact with the second semiconductor layer 12. The second semiconductor layer 12 and the third conductive portion 24a form a second Schottky junction S2. The third conductive portion 24a is located between the second semiconductor layer 12 and the fourth conductive portion 24b in the first direction (fourth direction) Y. The fourth conductive portion 24b is electrically connected to the third conductive portion 24a.

[0036] The material of the third electrode 23 can be the same as the material of the first electrode 21 of the main element 110. The material of the third conductive part 24a can be the same as the material of the first conductive part 22a of the main element 110. The material of the fourth conductive part 24b can be the same as the material of the second conductive part 22b of the main element 110.

[0037] The control element 120 further has a second gate electrode 32. Multiple second gate electrodes 32 are arranged in one direction on the XY plane, for example, in the second direction (fifth direction) X. The second gate electrodes 32 face the second Schottky junction S2 in the second direction (fifth direction) X. The second gate electrodes 32 extend in the third direction (sixth direction) Z. The material of the second gate electrodes 32 can be the same material as the first gate electrode 31 of the main element 110.

[0038] The potential of the second gate electrode 32 controls the thickness of the Schottky barrier (distance in the first direction (fourth direction) Y) in the second Schottky junction S2. When the Schottky barrier is thick, virtually no current flows between the fourth electrode 24 and the second semiconductor layer 12. This results in an off state. By controlling the potential of the second gate electrode 32, the Schottky barrier becomes thinner, and a tunnel current, for example, flows between the fourth electrode 24 and the second semiconductor layer 12. The flow of this tunnel current results in an on state.

[0039] The control element 120 may further include a third insulating member 43 and a fourth insulating member 44.

[0040] The third insulating member 43 is provided between the second gate electrode 32 and the second semiconductor layer 12 and extends in the third direction (sixth direction) Z. As shown in Figure 7, the third insulating member 43 has a second gate insulating portion 43a. The second gate insulating portion 43a is provided between the second gate electrode 32 and the second semiconductor layer 12, between the second gate electrode 32 and the second Schottky junction S2, and between the second gate electrode 32 and the third conductive portion 24a. The second gate electrode 32 faces the second Schottky junction S2 in the second direction (fifth direction) X via the second gate insulating portion 43a. The material of the third insulating member 43 can be the same material as the first insulating member 41 of the main element 110.

[0041] The fourth insulating member 44 is provided between the second gate electrode 32 and the fourth conductive part 24b, and between the third insulating member 43 and the fourth conductive part 24b, and extends in the third direction (sixth direction) Z. The material of the fourth insulating member 44 can be the same as the material of the second insulating member 42 of the main element 110.

[0042] According to this embodiment, the main element 110 and the control element 120 can be formed using the same process simply by changing the mask patterns used during film deposition and etching for forming each component of the main element 110 and the control element 120. For example, the first semiconductor layer 11 and the second semiconductor layer 12 can be formed on the same substrate 101, and the main element 110 and the control element 120 can be configured as a single chip. This makes it possible to integrate a power semiconductor device with a built-in control element 120 into a single chip at a low cost. When the main element 110 and the control element 120 are integrated into a single chip, it becomes possible to reduce the parasitic inductance of the wiring that electrically connects the main element 110 and the control element 120.

[0043] On the substrate 101, a fifth insulating member 60 can be provided between the main element 110 and the control element 120, as shown in Figure 1. The fifth insulating member 60 can also be provided between multiple control elements 120. For example, silicon oxide can be used as the material for the fifth insulating member 60.

[0044] Alternatively, the first semiconductor layer 11 and the second semiconductor layer 12 may be formed on the same substrate 101, and then separated into a chip for the main element 110 and a chip for the control element 120. In that case, the chip for the main element 110 and the chip for the control element 120 can be mounted on the same wiring board and packaged. In this case, the wiring board can be included as a support for the main element 110 and the control element 120.

[0045] The third electrode 23 of the control element 120 can be electrically connected to an external circuit via a third wiring section provided above the second semiconductor layer 12 in the third direction (sixth direction) Z. The fourth electrode 24 can be electrically connected to an external circuit via a fourth wiring section provided above the second semiconductor layer 12 in the third direction (sixth direction) Z. The second gate electrode 32 is provided on the second gate electrode 32 and can be electrically connected to a second gate wiring G2 extending in the second direction (fifth direction) X. The third wiring section, the fourth wiring section, and the second gate wiring G2 can be connected to an external circuit by being exposed to the outside of the semiconductor device 1 from above. An interlayer insulating layer is provided on the second semiconductor layer 12. The third wiring section, the fourth wiring section, and the second gate wiring G2 are provided in the interlayer insulating layer. The third wiring section, the fourth wiring section, and the second gate wiring G2 can be connected to the wiring of the main element 110 and the wiring of other control elements 120 within the interlayer insulating layer. Compared to wire bonding, for example, parasitic inductance can be reduced. The area of ​​the electrode pads of the main element 110, i.e., each wiring section, can be increased.

[0046] This makes it possible to suppress leakage current between the first wiring section D or the second wiring section S of the main element 110 and the main electrodes (third electrode 23 and fourth electrode 24) of the control element 120.

[0047] The voltage applied between the first electrode 21 and the second electrode 22 of the main element 110 is higher than the voltage applied between the third electrode 23 and the fourth electrode 24 of the control element 120. For example, the voltage applied between the first electrode 21 and the second electrode 22 of the main element 110 is 100V or more, while the voltage applied between the third electrode 23 and the fourth electrode 24 of the control element 120 is only a few volts. Therefore, in order to increase the breakdown voltage of the main element 110, it is preferable that the thickness of the first semiconductor layer 11 of the main element 110 in the first direction Y is greater than the thickness of the second semiconductor layer 12 of the control element 120 in the first direction Y.

[0048] At least one of the third electrode 23 and the fourth electrode 24 of the control element 120 is electrically connected to the first gate electrode 31 of the main element 110. The control element 120 forms a control circuit that controls the potential of the first gate electrode 31 of the main element 110.

[0049] An example of a control circuit formed by multiple control elements 120 will be described with reference to Figures 8(a) to 11(b).

[0050] Figures 8(a) and 8(b) show an example in which multiple control elements 120 form a NOT circuit 201. As an example, the case in which the multiple control elements 120 are MOSFETs in which the N-type semiconductor layer and the electrode are Schottky junctions is described. The multiple control elements 120 may also be MOSFETs having a MOS-type gate electrode in an NPN junction or PNP junction semiconductor structure. As another example, the configuration of a logic circuit using only one polarity MOSFET, for example, an N-type MOSFET, is described. The logic circuit can be replaced with a circuit including a CMOS having both N-type and P-type MOSFETs. The NOT circuit 201 has a first control element Q1(120) and a second control element Q2(120). The second electrode of the first control element Q1 and the first electrode of the second control element Q2 form a common electrode 25 shared by the first control element Q1 and the second control element Q2. The second gate wiring G2, which is electrically connected to the second gate electrode 32 of the first control element Q1, is electrically connected to the first electrode 21 of the first control element Q1. A power supply voltage is applied to the first electrode 21 of the first control element Q1, and the second electrode 22 of the second control element Q2 is grounded. A signal "A" is input to the second gate wiring G2 which is electrically connected to the second gate electrode 32 of the second control element Q2, and a signal "Y", which is the inverted signal "A", is output to the common electrode 25 (output terminal).

[0051] When configuring a circuit by connecting the third electrode 23 or fourth electrode 24 of one control element Q1(120) to the third electrode 23 or fourth electrode 24 of another control element Q2(120), the connected third electrode 23 or fourth electrode 24 is configured as a single unit. In this case, the direction from the third electrode 23 of one control element Q1(120) toward the fourth electrode 24 is aligned with the direction from the third electrode 23 of the other control element Q2(120) toward the fourth electrode 24. The area of ​​each wiring connecting the control elements 120 can be reduced. The mounting area of ​​the control elements 120 themselves can be reduced. The area occupied by the control elements 120 on the first surface 100A of the support 100 is reduced, and the channel area of ​​the main element 110 per unit area can be increased.

[0052] Figures 9(a) and 9(b) show an example in which multiple control elements 120 form a NOR circuit 202. The NOR circuit 202 has a first control element Q1(120), a second control element Q2(120), and a third control element Q3(120). The second electrode of the third control element Q3 and the first electrode of the second control element Q2 form a first common electrode 26 shared by the third control element Q3 and the second control element Q2. The second electrode of the second control element Q2 and the first electrode of the first control element Q1 form a second common electrode 27 shared by the second control element Q2 and the first control element Q1. The second gate wiring G2, which is electrically connected to the second gate electrode 32 of the third control element Q3, is electrically connected to the first electrode 21 of the third control element Q3. A power supply voltage is applied to the first electrode 21 of the third control element Q3, and the second electrode 22 of the first control element Q1 is grounded. Signal "A" is input to the second gate wiring G2 which is electrically connected to the second gate electrode 32 of the second control element Q2, and signal "B" is input to the second gate wiring G2 which is electrically connected to the second gate electrode 32 of the first control element Q1, and signal "Y", which is the inverted signal "A+B", is output to the first common electrode 26 (output terminal).

[0053] Figures 10(a) and 10(b) show an example in which multiple control elements 120 form a NAND circuit 203. The NAND circuit 203 has a first control element Q1(120), a second control element Q2(120), and a third control element Q3(120). The second electrode of the third control element Q3 and the first electrode of the second control element Q2 form a first common electrode 26 shared by the third control element Q3 and the second control element Q2. The second electrode of the second control element Q2 and the first electrode of the first control element Q1 form a second common electrode 27 shared by the second control element Q2 and the first control element Q1. The second gate wiring G2, which is electrically connected to the second gate electrode 32 of the third control element Q3, is electrically connected to the first electrode 21 of the third control element Q3. A power supply voltage is applied to the first electrode 21 of the third control element Q3, and the second electrode 22 of the first control element Q1 is grounded. Signal "A" is input to the second gate wiring G2 which is electrically connected to the second gate electrode 32 of the second control element Q2, and signal "B" is input to the second gate wiring G2 which is electrically connected to the second gate electrode 32 of the first control element Q1, and signal "Y", which is the inverted signal "A" and "B", is output to the second common electrode 27 (output terminal).

[0054] By simply changing the mask pattern, it is possible to create NOT gate 201, NOR gate 202, and NAND gate 203.

[0055] Multiple control elements 120 can form a delay circuit 204, as shown in Figures 11(a) and (b). The delay circuit 204 includes two NOT gates 201 connected in series and a capacitor C connected between the connection node of the two NOT gates 201 and ground.

[0056] Capacitor C has a fifth electrode 121, a sixth electrode 151, a third semiconductor layer 111, and a sixth insulating member 141. The fifth electrode 121, the sixth electrode 151, the third semiconductor layer 111, and the sixth insulating member 141 extend in a third direction Z on the first surface 100A of the support 100. The fifth electrode 121 and the sixth electrode 151 are located apart in a first direction Y and a second direction X, via the third semiconductor layer 111 and the sixth insulating member 141. For example, in the XY plane, the fifth electrode 121 continuously surrounds the third semiconductor layer 111, the third semiconductor layer 111 continuously surrounds the sixth insulating member 141, and the sixth insulating member 141 continuously surrounds the sixth electrode 151.

[0057] The fifth electrode 121, the sixth electrode 151, the third semiconductor layer 111, and the sixth insulating member 141 can be formed using the same process as the main element 110 and control element 120 described above, simply by changing the mask pattern. For example, the fifth electrode 121 can be formed using the same process as any of the first to fourth electrodes 21 to 24. The sixth electrode 151 can be formed using the same process as the field plate electrode 51. The third semiconductor layer 111 can be formed using the same process as the first semiconductor layer 11 and the second semiconductor layer 12. The sixth insulating member 141 can be formed using the same process as the first insulating member 41 and the third insulating member 43.

[0058] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0059] 1... Semiconductor device, 11... First semiconductor layer, 12... Second semiconductor layer, 21... First electrode, 22... Second electrode, 22a... First conductive part, 22b... Second conductive part, 23... Third electrode, 24... Fourth electrode, 24a... Third conductive part, 24b... Fourth conductive part, 31... First gate electrode, 32... Second gate electrode, 41... First insulating member, 42... Second insulating member, 43... Third insulating member, 44... Fourth insulating member, 51... Field plate electrode, 60...Fifth insulating member, 100...Support, 100A...First surface, 101...Substrate, 101B...Second surface, 110...Main element, 120...Control element, 201...NOT circuit, 202...NOR circuit, 203...NAND circuit, 204...Delay circuit, 300...Interlayer insulating layer, S1...First Schottky junction, S2...Second Schottky junction, D...First wiring section, S...Second wiring section, G1...First gate wiring, G2...Second gate wiring

Claims

1. A support having a first surface, A main element provided on the support, A control element provided on the support for controlling the main element, Equipped with, The main component is First electrode and, A second electrode located away from the first electrode in a first direction along the first surface, A first semiconductor layer is provided between the first electrode and the second electrode in the first direction, and forms a first Schottky junction with the second electrode, In a second direction intersecting the first direction along the first surface, a first gate electrode facing the first Schottky junction and It has, The control element is The third electrode and A fourth electrode located away from the third electrode in a fourth direction along the first surface, A second semiconductor layer is provided between the third electrode and the fourth electrode in the fourth direction, and forms a second Schottky junction with the fourth electrode, In a fifth direction intersecting the fourth direction along the first surface, a second gate electrode facing the second Schottky junction and It has, A semiconductor device in which multiple control elements form a NOT circuit.

2. A support having a first surface, A main element provided on the support, A control element provided on the support for controlling the main element, Equipped with, The main component is First electrode and, A second electrode located away from the first electrode in a first direction along the first surface, A first semiconductor layer is provided between the first electrode and the second electrode in the first direction, and forms a first Schottky junction with the second electrode, In a second direction intersecting the first direction along the first surface, a first gate electrode facing the first Schottky junction and It has, The control element is The third electrode and A fourth electrode located away from the third electrode in a fourth direction along the first surface, A second semiconductor layer is provided between the third electrode and the fourth electrode in the fourth direction, and forms a second Schottky junction with the fourth electrode, In a fifth direction intersecting the fourth direction along the first surface, a second gate electrode facing the second Schottky junction and It has, A semiconductor device in which multiple control elements form a NOR circuit.

3. A support having a first surface, A main element provided on the support, A control element provided on the support for controlling the main element, Equipped with, The main component is First electrode and, A second electrode located away from the first electrode in a first direction along the first surface, A first semiconductor layer is provided between the first electrode and the second electrode in the first direction, and forms a first Schottky junction with the second electrode, In a second direction intersecting the first direction along the first surface, a first gate electrode facing the first Schottky junction and It has, The control element is The third electrode and A fourth electrode located away from the third electrode in a fourth direction along the first surface, A second semiconductor layer is provided between the third electrode and the fourth electrode in the fourth direction, and forms a second Schottky junction with the fourth electrode, In a fifth direction intersecting the fourth direction along the first surface, a second gate electrode facing the second Schottky junction and It has, A semiconductor device in which multiple control elements form a NAND circuit.

4. The support has a substrate, The semiconductor device according to any one of claims 1 to 3, wherein the first semiconductor layer and the second semiconductor layer are provided on the same substrate.

5. The substrate has a second surface located on the opposite side of the first surface in a third direction intersecting the first and second directions, The semiconductor device according to claim 4, wherein the third electrode and the fourth electrode of the control element are located on the first surface and not on the second surface.

6. The semiconductor device according to any one of claims 1 to 3, wherein the thickness of the first semiconductor layer in the first direction is greater than the thickness of the second semiconductor layer in the fourth direction.

7. The semiconductor device according to any one of claims 1 to 3, wherein at least one of the third electrode and the fourth electrode of the control element is electrically connected to the first gate electrode of the main element.

8. The semiconductor device according to claim 5, wherein the main element further comprises an interlayer insulating layer in contact with the upper part of the first semiconductor layer in the third direction.

9. The semiconductor device according to claim 8, wherein the main element has a first gate wiring portion connected to the first gate electrode in the interlayer insulating layer.

10. The control elements comprises a plurality of the aforementioned control elements, The plurality of control elements include at least a first control element and a second control element located in the fourth direction relative to the first control element. The semiconductor device according to claim 5, wherein the fourth electrode of the first control element is integrally connected with the third electrode of the second control element.

11. The semiconductor device according to claim 10, wherein the second gate electrode of the first control element is connected to the third electrode of the first control element.

12. A support having a first surface, A main element provided on the support, A control element provided on the support for controlling the main element, Equipped with, The main component is First electrode and, A second electrode located away from the first electrode in a first direction along the first surface, A first semiconductor layer is provided between the first electrode and the second electrode in the first direction, and forms a first Schottky junction with the second electrode, In a second direction intersecting the first direction along the first surface, a first gate electrode facing the first Schottky junction and It has, The control element is The third electrode and A fourth electrode located away from the third electrode in a fourth direction along the first surface, A second semiconductor layer is provided between the third electrode and the fourth electrode in the fourth direction, and forms a second Schottky junction with the fourth electrode, In a fifth direction intersecting the fourth direction along the first surface, a second gate electrode facing the second Schottky junction and It has, The support has a substrate, The first semiconductor layer and the second semiconductor layer are provided on the same substrate. The substrate has a second surface located on the opposite side of the first surface in a third direction intersecting the first and second directions, The third and fourth electrodes of the control element are located on the first surface and not on the second surface. The main component is In the third direction, an interlayer insulating layer in contact with the upper part of the first semiconductor layer, The interlayer insulating layer includes a first gate wiring portion connected to the first gate electrode, A semiconductor device further having [a certain feature].

13. A support having a first surface, A main element provided on the support, A control element provided on the support for controlling the main element, Equipped with, The main component is First electrode and, A second electrode located away from the first electrode in a first direction along the first surface, A first semiconductor layer is provided between the first electrode and the second electrode in the first direction, and forms a first Schottky junction with the second electrode, In a second direction intersecting the first direction along the first surface, a first gate electrode facing the first Schottky junction and It has, The control element is The third electrode and A fourth electrode located away from the third electrode in a fourth direction along the first surface, A second semiconductor layer is provided between the third electrode and the fourth electrode in the fourth direction, and forms a second Schottky junction with the fourth electrode, In a fifth direction intersecting the fourth direction along the first surface, a second gate electrode facing the second Schottky junction and It has, The support has a substrate, The first semiconductor layer and the second semiconductor layer are provided on the same substrate. The substrate has a second surface located on the opposite side of the first surface in a third direction intersecting the first and second directions, The third and fourth electrodes of the control element are located on the first surface and not on the second surface. The control elements comprises a plurality of the aforementioned control elements, The plurality of control elements include at least a first control element and a second control element located in the fourth direction relative to the first control element. The fourth electrode of the first control element is integrally connected with the third electrode of the second control element. The second gate electrode of the first control element is a semiconductor device connected to the third electrode of the first control element.

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