Indication device

Abstract

To provide a display device in which resistance to water is enhanced.SOLUTION: A display device according to an embodiment, comprises: a substrate; an insulation layer that is arranged to an upper direction of the substrate; a lower electrode that is arranged to the upper direction of the insulation layer in a display region containing a pixel; a rib that includes an open overlapped with the lower electrode; a barrier wall that is arranged to the upper direction of the rib in the display region; an upper electrode that is opposite to the lower electrode, and is connected to the barrier wall; an organic layer that is arranged between the lower electrode and the upper electrode, and emits a light in accordance with a potential difference of the lower electrode and the upper electrode; a dam structure that contains at least one convex part arranged in a peripheral region between an end part of the substrate and the display region; and a conductive layer that is arranged in the peripheral region, covers at least one part of the dam structure, and is connected to the barrier wall. The barrier wall and the conductive layer include: a lower part having a conductivity; and an upper part projected from a side surface of the lower part. The end part of the conductive layer is positioned between the convex part and the end part of the substrate in a plan view.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. This display element includes a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0003] Generally, the organic layer has low resistance to moisture. If moisture reaches the organic layer for some reason, it may contribute to a decrease in display quality, such as a decrease in the luminance of the display element during light emission. Further, if moisture infiltrates into the drive circuit disposed in the peripheral region around the display region, the elements constituting the drive circuit deteriorate, and malfunctions may occur in the operation of the display device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a display device with enhanced resistance to moisture.

Means for Solving the Problems

[0006] A display device according to one embodiment includes a substrate, an insulating layer disposed above the substrate, a lower electrode disposed above the insulating layer in a display area including pixels, a rib having an opening overlapping the lower electrode, a partition wall disposed above the rib in the display area, an upper electrode facing the lower electrode and connected to the partition wall, an organic layer disposed between the lower electrode and the upper electrode and emitting light in accordance with the potential difference between the lower electrode and the upper electrode, a dam structure including at least one protrusion disposed in the peripheral region between the edge of the substrate and the display area, and a conductive layer disposed in the peripheral region, covering at least a part of the dam structure and connected to the partition wall. A power supply line arranged in the peripheral region, and a relay wiring connected to the power supply line at a first contact portion located in the peripheral region and connected to the conductive layer at a second contact portion located in the peripheral region, The partition wall and the conductive layer have a conductive lower portion and an upper portion that protrudes from the side surface of the lower portion. The end of the conductive layer is located between the protrusion and the end of the substrate in a plan view. The relay wiring is covered by the rib. The second contact portion includes a plurality of contact holes provided in the rib. The conductive layer is in contact with the relay wiring through the plurality of contact holes. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of a display device according to one embodiment. [Figure 2] Figure 2 shows an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of the partition wall and its vicinity, magnified. [Figure 5] Figure 5 is a schematic cross-sectional view showing another example of a structure that can be applied to a partition wall. [Figure 6] Figure 6 is a schematic plan view of some of the elements of the display device. [Figure 7] Figure 7 is a schematic plan view of other elements of the display device. [Figure 8] Figure 8 is an enlarged view of the area enclosed by the dashed line frame in Figure 6. [Figure 9]Figure 9 is a schematic cross-sectional view of the display device along the IX-IX line in Figure 8. [Figure 10] Figure 10 is a schematic cross-sectional view of the vicinity of the edge of the conductive layer. [Modes for carrying out the invention]

[0008] One embodiment will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0009] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction, the direction along the Y axis as the second direction, and the direction along the Z axis as the third direction. Viewing the various elements parallel to the third direction Z is called a plan view.

[0010] The display device according to this embodiment is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted in televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and the like.

[0011] Figure 1 shows an example configuration of a display device DSP according to this embodiment. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. Note that the pixel PX may include sub-pixels SP of other colors such as white, either together with the sub-pixels SP1, SP2, SP3 or in place of any of the sub-pixels SP1, SP2, SP3.

[0014] The sub-pixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements constituted by, for example, thin film transistors.

[0015] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power supply line PL and the capacitor 4, and the other is connected to the display element 20.

[0016] The display element 20 is an organic light emitting diode (OLED) as a light emitting element. For example, the sub-pixel SP1 includes a display element 20 that emits light in a red wavelength region, the sub-pixel SP2 includes a display element 20 that emits light in a green wavelength region, and the sub-pixel SP3 includes a display element 20 that emits light in a blue wavelength region.

[0017] Note that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP1 and SP2 are aligned in the second direction Y. Furthermore, sub-pixels SP1 and SP2 are aligned with sub-pixel SP3 in the first direction X.

[0019] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0020] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. Another example is that the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.

[0021] The display area DA has ribs 5 and partition walls 6. Ribs 5 have pixel apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel aperture AP2 is larger than pixel aperture AP1, and pixel aperture AP3 is larger than pixel aperture AP2.

[0022] The partition wall 6 is positioned at the boundary between adjacent subpixels SP and overlaps with the rib 5 in a plan view. The partition wall 6 has a plurality of first partition walls 6x extending in the first direction X and a plurality of second partition walls 6y extending in the second direction Y. The plurality of first partition walls 6x are positioned between adjacent pixel apertures AP1 and AP2 in the second direction Y, and between two adjacent pixel apertures AP3 in the second direction Y. The second partition walls 6y are positioned between adjacent pixel apertures AP1 and AP3 in the first direction X, and between adjacent pixel apertures AP2 and AP3 in the first direction X.

[0023] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole forms a grid surrounding the pixel apertures AP1, AP2, and AP3. It can also be said that the partition wall 6, like the rib 5, has apertures in the sub-pixels SP1, SP2, and SP3.

[0024] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3. In the example in Figure 2, the outer shapes of the upper electrode UE1 and organic layer OR1 match, the outer shapes of the upper electrode UE2 and organic layer OR2 match, and the outer shapes of the upper electrode UE3 and organic layer OR3 match.

[0025] The lower electrode LE1, upper electrode UE1, and organic layer OR1 constitute the display element 20 of the sub-pixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 constitute the display element 20 of the sub-pixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 constitute the display element 20 of the sub-pixel SP3.

[0026] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0027] In the example in Figure 2, contact holes CH1 and CH2 completely overlap with the first partition wall 6x between adjacent pixel apertures AP1 and AP2 in the second direction Y. Contact hole CH3 completely overlaps with the first partition wall 6x between two adjacent pixel apertures AP3 in the second direction Y. In another example, at least a portion of contact holes CH1, CH2, and CH3 may not overlap with the first partition wall 6x.

[0028] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11. Although not shown in the cross-section of Figure 3, the contact holes CH1, CH2, and CH3 described above are provided in the organic insulating layer 12.

[0029] The lower electrodes LE1, LE2, and LE3 are positioned on top of the organic insulating layer 12. The ribs 5 are positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5.

[0030] The partition wall 6 includes a conductive lower section 61 positioned on the rib 5 and an upper section 62 positioned on top of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, in Figure 3, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of the partition wall 6 can also be described as overhanging.

[0031] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3.

[0032] In the example shown in Figure 3, cap layer CP1 is placed on organic layer OR1, cap layer CP2 is placed on organic layer OR2, and cap layer CP3 is placed on organic layer OR3. Cap layers CP1, CP2, and CP3 adjust the optical properties of the light emitted by organic layers OR1, OR2, and OR3, respectively.

[0033] A portion of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is located above the upper section 62. This portion is separated from the other portions of the organic layer OR1, the upper electrode UE1, and the cap layer CP1. Similarly, a portion of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 is located above the upper section 62, and this portion is separated from the other portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2. Furthermore, a portion of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 is located above the upper section 62, and this portion is separated from the other portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3.

[0034] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE1, SE2, and SE3, respectively. Sealing layer SE1 continuously covers the cap layer CP1 and the partition wall 6. Sealing layer SE2 continuously covers the cap layer CP2 and the partition wall 6. Sealing layer SE3 continuously covers the cap layer CP3 and the partition wall 6.

[0035] In the example shown in Figure 3, the organic layer OR1, upper electrode UE1, cap layer CP1, and sealing layer SE1 on the partition wall 6 between sub-pixels SP1 and SP3 are separated from the organic layer OR3, upper electrode UE3, cap layer CP3, and sealing layer SE3 on the same partition wall 6. Similarly, the organic layer OR2, upper electrode UE2, cap layer CP2, and sealing layer SE2 on the partition wall 6 between sub-pixels SP2 and SP3 are separated from the organic layer OR3, upper electrode UE3, cap layer CP3, and sealing layer SE3 on the same partition wall 6.

[0036] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 13. The resin layer 13 is covered by a sealing layer 14. Furthermore, the sealing layer 14 is covered by a resin layer 15.

[0037] The organic insulating layer 12 and the resin layers 13 and 15 are formed from organic materials. The ribs 5 and the sealing layers 14, SE1, SE2, SE3 are formed from inorganic materials such as silicon nitride (SiNx). The ribs 5 and the sealing layers 14, SE1, SE2, SE3 may be formed as single layers of silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Alternatively, the ribs 5 and the sealing layers 14, SE1, SE2, SE3 may be formed as laminates of at least two combinations of silicon nitride layers, silicon oxide layers, silicon oxynitride layers, and aluminum oxide layers.

[0038] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material, such as a magnesium-silver alloy (MgAg). When the potential of the lower electrodes LE1, LE2, and LE3 is relatively higher than the potential of the upper electrodes UE1, UE2, and UE3, the lower electrodes LE1, LE2, and LE3 act as the anode, and the upper electrodes UE1, UE2, and UE3 act as the cathode. Also, when the potential of the upper electrodes UE1, UE2, and UE3 is relatively higher than the potential of the lower electrodes LE1, LE2, and LE3, the upper electrodes UE1, UE2, and UE3 act as the anode, and the lower electrodes LE1, LE2, and LE3 act as the cathode.

[0039] The organic layers OR1, OR2, and OR3 include a pair of functional layers and an emissive layer disposed between these functional layers. As an example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in that order.

[0040] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of multiple transparent thin films. The multilayer structure may include thin films formed from inorganic materials and thin films formed from organic materials. These multiple thin films have different refractive indices. The materials of the thin films constituting the multilayer structure are different from the materials of the upper electrodes UE1, UE2, and UE3, and also different from the materials of the sealing layers SE1, SE2, and SE3. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0041] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the side surface of the lower part 61. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0042] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the blue wavelength range.

[0043] Figure 4 is a schematic, enlarged cross-sectional view of the partition wall 6 located at the boundary between sub-pixels SP1 and SP2 and its vicinity. In this figure, the substrate 10, circuit layer 11, resin layer 13, sealing layer 14, and resin layer 15 are omitted.

[0044] The lower part 61 of the partition wall 6 has sides F1 and F2. The upper part 62 of the partition wall 6 has an end E1 protruding from side F1 and an end E2 protruding from side F2. The upper electrodes UE1 and UE3 are in contact with sides F1 and F2, respectively.

[0045] In the example shown in Figure 4, the lower part 61 has a first metal layer 611 and a second metal layer 612 that is thinner than the first metal layer 611. The second metal layer 612 is located between the rib 5 and the first metal layer 611. The upper part 62 has a first thin film 621 placed on top of the first metal layer 611 and a second thin film 622 placed on top of the first thin film 621.

[0046] The first metal layer 611 is formed of, for example, aluminum (Al). The first metal layer 611 may be formed of an aluminum alloy, or it may have a laminated structure of aluminum and an aluminum alloy. The second metal layer 612 is formed of, for example, molybdenum (Mo).

[0047] The first thin film 621 is formed of, for example, titanium (Ti). The first thin film 621 may also be formed of an inorganic material such as silicon oxide. The second thin film 622 is formed of a transparent conductive oxide such as ITO (IndiumTin Oxide), IZO (IndiumZinc Oxide), and IGZO (IndiumGalliumZinc Oxide). The upper part 62 may have a single-layer structure of titanium or silicon oxide.

[0048] In the example shown in Figure 4, the lower electrode LE1 has a first conductive oxide layer L1, a second conductive oxide layer L2, and an intermediate layer L3 between these conductive oxide layers L1 and L2. The first conductive oxide layer L1 covers the upper surface of the intermediate layer L3, and the second conductive oxide layer L2 covers the lower surface of the intermediate layer L3.

[0049] The conductive oxide layers L1 and L2 are formed of, for example, ITO. That is, the upper and lower surfaces of the lower electrode LE1 are formed of ITO. As another example, the conductive oxide layers L1 and L2 may be formed of IZO or IGZO, etc. The intermediate layer L3 is formed of a metallic material such as silver (Ag). The lower electrodes LE2 and LE3 have a similar configuration to the lower electrode LE1.

[0050] Figure 5 is a schematic cross-sectional view showing another example of a structure that may be applied to the partition wall 6. In this example, the lower part 61 does not have the second metal layer 612 shown in Figure 4. That is, the lower part 61 is formed by the first metal layer 611. The first metal layer 611 is in contact with the upper surface of the rib 5.

[0051] In the example shown in Figure 5, the first metal layer 611 may be formed of aluminum or an aluminum alloy, or it may have a laminated structure of aluminum and an aluminum alloy.

[0052] Next, we will explain the structures that can be applied to the surrounding SA region. Figure 6 is a schematic plan view of the display device DSP. The display device DSP includes a first gate drive circuit GD1, a second gate drive circuit GD2, a selector circuit ST, and a terminal section T as elements arranged in the peripheral region SA. The first gate drive circuit GD1, the second gate drive circuit GD2, and the selector circuit ST are examples of drive circuits that supply signals to the pixel circuit 1, and are included in the circuit layer 11 shown in Figure 3.

[0053] The first gate drive circuit GD1 and the second gate drive circuit GD2 supply scanning signals to the scanning line GL shown in Figure 1. A flexible circuit board, for example, is connected to the terminal T. The selector circuit ST supplies the video signal input from this flexible circuit board to the signal line SL shown in Figure 1.

[0054] The substrate 10 has a first end E1, a second end E2, a third end E3, and a fourth end E4. The first end E1 and the second end E2 extend parallel to the second direction Y. The third end E3 and the fourth end E4 extend parallel to the first direction X.

[0055] In the example shown in Figure 6, the first gate drive circuit GD1 is located between the display area DA and the first end E1, the second gate drive circuit GD2 is located between the display area DA and the second end E2, and the selector circuit ST and terminal section T are located between the display area DA and the third end E3.

[0056] Furthermore, the display device DSP includes a conductive layer CL (the part with a dot pattern) and a dam structure DS (the part with a diagonal line pattern) located in the peripheral region SA. In the example in Figure 6, the conductive layer CL surrounds the display region DA. The dam structure DS also surrounds the conductive layer CL. The conductive layer CL and the dam structure DS partially overlap. For example, the dam structure DS plays a role in damming the resin layer 13 shown in Figure 2.

[0057] The conductive layer CL is connected to the partition wall 6 located in the display area DA. In a plan view, the conductive layer CL overlaps with the first gate drive circuit GD1, the second gate drive circuit GD2, and the selector circuit ST.

[0058] Furthermore, the conductive layer CL does not necessarily have to have a shape that surrounds the display area DA. For example, the conductive layer CL does not need to be placed between the display area DA and the third end E3, or between the display area DA and the fourth end E4.

[0059] Figure 7 is a schematic plan view showing other elements located in the peripheral region SA. The peripheral region SA contains the power supply line PW (indicated by the diagonal lines) and the relay wiring RL (indicated by the dotted lines).

[0060] In Figure 7, the power supply line PW and relay wiring RL surround the display area DA, but this is not the only example. The power supply line PW and relay wiring RL partially overlap.

[0061] The power supply line PW has a pair of pads PD located near the third end E3. These pads PD are electrically connected to terminal T. A common voltage is supplied to the power supply line PW through terminal T and each pad PD. Furthermore, the common voltage of the power supply line PW is supplied to the relay wiring RL.

[0062] Figure 8 is an enlarged view of the area enclosed by the dashed-line frame VIII in Figure 6. Figure 9 is a schematic cross-sectional view of the display device DSP along the line IX-IX in Figure 8. In Figure 8, the area with the dot pattern corresponds to the conductive layer CL and the partition wall 6 (first partition wall 6x and second partition wall 6y). The conductive layer CL and the partition wall 6 are integrally formed from the same material using the same manufacturing process.

[0063] As shown in Figures 8 and 9, the dam structure DS has a first protrusion R1, a second protrusion R2, a third protrusion R3, and a fourth protrusion R4. The first protrusion R1 encloses the display area DA, the second protrusion R2 encloses the first protrusion R1, the third protrusion R3 encloses the second protrusion R2, and the fourth protrusion R4 encloses the third protrusion R3. Note that the number of protrusions in the dam structure DS is not limited to four, and may be three or fewer, or five or more.

[0064] As shown in Figure 9, the protrusions R1, R2, R3, and R4 are located between the end 12a of the organic insulating layer 12 and the first end E1 of the substrate 10. The protrusions R1, R2, R3, and R4 are also located between the end 12a and the second end E2, between the end 12a and the third end E3, and between the end 12a and the fourth end E4. The protrusions R1, R2, R3, and R4 are formed, for example, from the same material and using the same process as the organic insulating layer 12.

[0065] The distance between any two adjacent protrusions R1, R2, R3, and R4 is greater than the width of each protrusion R1, R2, R3, and R4. For example, the width of each protrusion R1, R2, R3, and R4 is 15-25 μm, and the distance between any two adjacent protrusions R1, R2, R3, and R4 is 25-35 μm. Also, the height of each protrusion R1, R2, R3, and R4 is 3-4 μm.

[0066] In the example shown in Figure 9, the circuit layer 11 comprises insulating layers 31, 32, 33 and metal layers 41, 42, 43. The insulating layer 31 covers the substrate 10. The metal layer 41 is placed on top of the insulating layer 31 and covered by the insulating layer 32. The metal layer 42 is placed on top of the insulating layer 32 and covered by the insulating layer 33. The metal layer 43 is placed on top of the insulating layer 33 and covered by the organic insulating layer 12.

[0067] The insulating layers 31, 32, and 33 are formed of inorganic materials such as silicon nitride and silicon oxide. The metal layers 41, 42, and 43 have a single-layer or multi-layer structure of metallic materials such as molybdenum (Mo), tungsten (W), molybdenum-tungsten alloy (MoW), aluminum (Al), and copper (Cu).

[0068] The first gate drive circuit GD1 is formed by metal layers 41, 42, 43 and semiconductor layers. Similarly, the second gate drive circuit GD2 and selector circuit ST shown in Figure 6, and the pixel circuit 1 shown in Figure 1, are also formed by metal layers 41, 42, 43 and semiconductor layers. Furthermore, the scan line GL, signal line SL, and power line PL shown in Figure 1 are formed by any of the metal layers 41, 42, or 43.

[0069] The protrusions R1, R2, R3, and R4 are located on the insulating layer 33. Ribs 5 are also located in the surrounding region SA. In the example in Figure 9, ribs 5 are not located on the dam structure DS.

[0070] The conductive layer CL covers the rib 5 in the peripheral region SA. The conductive layer CL includes a lower section 61 and an upper section 62, similar to the partition wall 6 shown in Figures 3 to 5. In the conductive layer CL as well, the end of the upper section 62 protrudes beyond the side surface of the lower section 61.

[0071] As shown in Figures 8 and 9, the conductive layer CL covers a portion of the dam structure DS. The end CLa of the conductive layer CL is located between the first protrusion R1 and the first end E1 of the substrate 10. The end CLa of the conductive layer CL is also located between the first protrusion R1 and the second end E2, between the first protrusion R1 and the third end E3, and between the first protrusion R1 and the fourth end E4. In other words, the end CLa is located between the first protrusion R1 and the end of the substrate 10 around the entire circumference. Furthermore, as shown in Figure 6, the end CLa is located between the first gate drive circuit GD1 and the first end E1, between the second gate drive circuit GD2 and the second end E2, and between the selector circuit ST and the third end E3.

[0072] In the example shown in Figure 9, the conductive layer CL covers the first protrusion R1, and the end portion CLa is located on the insulating layer 33 between the protrusions R1 and R2. The example is not limited to this; the end portion CLa may also be located between the protrusions R2 and R3, or between the protrusions R3 and R4.

[0073] In the example shown in Figure 9, the power supply line PW has a first portion P1 formed by a metal layer 42 and a second portion P2 formed by a metal layer 43. The second portion P2 is in contact with the first portion P1. For example, in the power supply line PW shown in Figure 7, the pad PD is formed by the first portion P1, and the portion surrounding the display area DA is formed by at least the second portion P2.

[0074] The intermediate wiring RL is mostly placed on top of the organic insulating layer 12 and covered by the ribs 5. The intermediate wiring RL is formed from the same material and using the same manufacturing process as the lower electrodes LE1, LE2, and LE3. Therefore, the intermediate wiring RL has the same first conductive oxide layer L1, second conductive oxide layer L2, and intermediate layer L3 as the lower electrodes LE1, LE2, and LE3.

[0075] The relay wiring RL is connected to the power supply line PW at the first contact section CN1 and to the conductive layer CL at the second contact section CN2. As a result, the common voltage of the power supply line PW is supplied to the conductive layer CL via the relay wiring RL. Furthermore, the common voltage of the conductive layer CL is supplied to the partition wall 6 and upper electrodes UE1, UE2, and UE3 of the display area DA.

[0076] The first contact portion CN1 is located between the end portion 12a of the organic insulating layer 12 and the first protrusion R1. In the first contact portion CN1, the lower surface of the relay wiring RL is in contact with the second portion P2 of the power supply line PW.

[0077] In the example shown in Figure 9, the upper surface of the relay wiring RL is in contact with the lower part 61 of the conductive layer CL at the first contact portion CN1. As a result, the power supply line PW and the conductive layer CL are electrically connected at the first contact portion CN1 as well.

[0078] The first contact area CN1 corresponds, for example, to the area where the power supply line PW and the relay wiring RL overlap in Figure 7, and surrounds the display area DA. However, the first contact area CN1 may be interrupted at least one point around the display area DA.

[0079] As shown in Figures 8 and 9, the second contact portion CN2 has a plurality of contact holes CHa provided in the rib 5. The lower part 61 of the conductive layer CL is in contact with the upper surface of the relay wiring RL through these contact holes CHa.

[0080] In the example shown in Figure 8, multiple contact holes CHa all extend elongated in the first direction X and are aligned in the second direction Y. The shape and arrangement of the contact holes CHa are not limited to this example and can be modified in various ways.

[0081] As shown in Figure 8, the second contact portion CN2 is located between the first contact portion CN1 and the display area DA in a plan view. The edge CLa of the conductive layer CL is located between the first contact portion CN1 and the first edge E1 of the substrate 10 in a plan view. The edge CLa is also located between the first contact portion CN1 and the second edge E2, between the first contact portion CN1 and the third edge E3, and between the first contact portion CN1 and the fourth edge E4.

[0082] The conductive layer CL has multiple apertures APa arranged at regular intervals in the first direction X and the second direction Y. In the example in Figure 8, some of these apertures APa are located between adjacent contact holes CHa in the second direction Y. The apertures APa are smaller than the contact holes CHa, for example, in a plan view.

[0083] In forming the conductive layer CL and partition wall 6, the base layers for the lower 61 and upper 62 are first formed over the entire display area DA and surrounding area, and these layers are then patterned into the shapes of the conductive layer CL and partition wall 6 by etching. In the display area DA, there are many openings corresponding to each sub-pixel SP1, SP2, SP3 (areas enclosed by the first partition wall 6x and the second partition wall 6y). If the density of such openings differs between the display area DA and the surrounding area SA, it may not be possible to achieve uniform etching. In contrast, by providing multiple openings APa in the conductive layer CL, the etching process can be made uniform between the display area DA and the surrounding area SA.

[0084] As shown in Figure 9, the peripheral region SA contains organic layers ORs, upper electrodes UEs, cap layers CPs, and sealing layers SEs. In the example in Figure 9, the organic layers ORs, upper electrodes UEs, and cap layers CPs are shown as a single layer, but in reality, the upper electrodes UEs cover the organic layers ORs, and the cap layers CPs cover the upper electrodes UEs. The organic layers ORs, upper electrodes UEs, and cap layers CPs cover the conductive layer CL and the dam structure DS. The sealing layers SEs cover the organic layers ORs, upper electrodes UEs, and cap layers CPs.

[0085] The organic layers ORs are formed using the same material and process as any of the organic layers OR1, OR2, or OR3. The upper electrodes UEs are formed using the same material and process as any of the upper electrodes UE1, UE2, or UE3. The cap layers CPs are formed using the same material and process as any of the cap layers CP1, CP2, or CP3. The sealing layers SEs are formed using the same material and process as any of the sealing layers SE1, SE2, or SE3. In one example, the organic layers ORs, upper electrodes UEs, cap layers CPs, and sealing layers SEs are formed using the same material and process as organic layer OR3, upper electrode UE3, cap layer CP3, and sealing layer SE3, respectively.

[0086] The resin layer 13 is formed, for example, by an inkjet method. The unevenness of the sealing layer SEs caused by the protrusions R1, R2, R3, and R4 suppresses the spreading of the resin layer 13 before curing. In Figure 9, the edge of the resin layer 13 is located near the second protrusion R2, but this is not the only example. The sealing layer 14 is in contact with the sealing layer SEs on the outside of the edge of the resin layer 13. The resin layer 15 completely covers the sealing layer 14.

[0087] Figure 10 is a schematic cross-sectional view of the conductive layer CL near its end CLa. The conductive layer CL has a lower section 61 and an upper section 62. The layer configuration of the lower section 61 and upper section 62 of the conductive layer CL is the same as that of the partition wall 6 shown in Figures 4 and 5.

[0088] At the end Cla, the lower part 61 of the conductive layer CL has a side surface F3. The upper part 62 of the conductive layer CL protrudes beyond the side surface F3. In other words, the shape of the conductive layer CL at the end Cla is overhanging, similar to the partition wall 6.

[0089] When organic layers ORs, upper electrodes UEs, and cap layers CPs are formed on a conductive layer CL of this shape, these organic layers ORs, upper electrodes UEs, and cap layers CPs are separated at the end CLa, as shown in Figure 10.

[0090] The sealing layer SEs covers the organic layers ORs, upper electrodes UEs, and cap layer CPs located above and below the conductive layer CL, respectively, and also covers the side surface F3 of the lower part 61.

[0091] Although Figures 8 to 10 focus on the structure between the display area DA and the first end E1, a similar structure can be applied between the display area DA and the second end E2, between the display area DA and the third end E3, and between the display area DA and the fourth end E4. Preferably, the organic layers ORs, upper electrodes UEs, and cap layers CPs are separated around the entire circumference of the end CLa.

[0092] In the DSP display device according to this embodiment, a partition wall 6 located in the display area DA is connected to a conductive layer CL located in the peripheral area SA. Furthermore, the partition wall 6 is connected to the upper electrodes UE1, UE2, and UE3 of the sub-pixels SP1, SP2, and SP3, and the conductive layer CL is connected to the power supply line PW. In such a structure, the common voltage of the power supply line PW can be supplied to the upper electrodes UE1, UE2, and UE3 via the conductive layer CL and the partition wall 6.

[0093] As shown in the example in Figure 9, when organic layers ORs, upper electrodes UEs, and cap layers CPs are arranged in the peripheral region SA, moisture may penetrate into the DSP of the display device through these layers. If this moisture reaches the gate drive circuits GD1, GD2, selector circuit ST, power supply line PW, pixel circuit 1, and display element 20, it may cause malfunction of the DSP.

[0094] In contrast, in the DSP display device according to this embodiment, the end CLa of the conductive layer CL is located between the first protrusion R1 of the dam structure DS and the ends E1, E2, E3, E4 of the substrate 10. As a result, as shown in Figure 10, the organic layer ORs, the upper electrode UEs, and the cap layer CPs are separated, and the intrusion of moisture into the interior of the DSP display device through these layers can be suppressed. As a result, the moisture resistance of the DSP display device is improved. If the end CLa is located outside the contact portions CN1, CN2, as in the example in Figure 9, the intrusion of moisture through these contact portions CN1, CN2 is suppressed, making it even more preferable.

[0095] Since the upper surfaces of the protrusions R1, R2, R3, and R4 of the dam structure DS can be curved, if the end portion CLa of the conductive layer CL is located above the protrusions R1, R2, R3, and R4 of the dam structure DS, the end portion CLa may not be formed in a good overhang shape.

[0096] In contrast, as shown in the example in Figure 9, if the end CLa is located between the protrusions R1 and R2, the end CLa can be formed in a good overhang shape. Similar effects can be obtained even when the end CLa is located between the protrusions R2 and R3 or between the protrusions R3 and R4.

[0097] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0098] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of any of the above-described embodiments, or to add, omit, or change the conditions of any process, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0099] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0100] DSP...Display device, DA...Display area, SA...Peripheral area, PX...Pixel, SP1, SP2, SP3...Sub-pixel, LE1, LE2, LE3...Lower electrode, UE1, UE2, UE3, UEs...Upper electrode, OR1, OR2, OR3, ORs...Organic layer, CP1, CP2, CP3, CPs...Cap layer, SE1, SE2, SE3, SEs...Sealing layer, CL...Conductive layer, PW...Power supply line, RL...Relay wiring, DS...Dam structure, R1, R2, R3, R4...Protrusion, CN1...First contact part, CN2...Second contact part, APa...Opening, CHa...Contact hole, 1...Pixel circuit, 5...Rib, 6...Partition, 10...Substrate, 12...Organic insulating layer, 61...Lower part of partition, 62...Upper part of partition.

Claims

1. circuit board and An insulating layer disposed above the substrate, A lower electrode positioned above the insulating layer in a display area including a pixel, A rib having an opening that overlaps with the lower electrode, A partition wall positioned above the rib in the aforementioned display area, An upper electrode, which is opposite the lower electrode and connected to the partition wall, An organic layer is placed between the lower electrode and the upper electrode and emits light in accordance with the potential difference between the lower electrode and the upper electrode, A dam structure including at least one protrusion arranged in the peripheral region between the edge of the substrate and the display area, A conductive layer is arranged in the surrounding region, covering at least a part of the dam structure and connected to the partition wall, Power supply lines arranged in the aforementioned peripheral region, A relay wiring connected to the power supply line at a first contact portion located in the peripheral region, and connected to the conductive layer at a second contact portion located in the peripheral region, Equipped with, The partition wall and the conductive layer have a conductive lower portion and an upper portion that protrudes from the side surface of the lower portion. The end of the conductive layer is located between the protrusion and the end of the substrate in a plan view. The relay wiring is covered by the rib, The second contact portion includes a plurality of contact holes provided in the rib, The conductive layer is in contact with the relay wiring through the plurality of contact holes. Display device.

2. The aforementioned organic layer is also arranged in the surrounding region, The organic layer is divided by the end of the conductive layer. The display device according to claim 1.

3. The conductive layer and the protrusion surround the display area. The end of the conductive layer is located between the protrusion and the end of the substrate over its entire circumference. The display device according to claim 1 or 2.

4. The aforementioned protrusion is formed of the same material as the insulating layer. The display device according to any one of claims 1 to 3.

5. The dam structure includes a first protrusion surrounding the display area and a second protrusion surrounding the first protrusion. The end of the conductive layer is located between the first protrusion and the second protrusion in a plan view. The display device according to any one of claims 1 to 4.

6. A pixel circuit arranged in the display area and supplying voltage to the lower electrode, The system further comprises a drive circuit arranged in the peripheral region and supplying signals to the pixel circuit, The edge of the conductive layer is located between the drive circuit and the edge of the substrate in a plan view. The display device according to any one of claims 1 to 5.

7. In the first contact portion, the lower surface of the relay wiring is in contact with the power supply line, and the upper surface of the relay wiring is in contact with the conductive layer. The display device according to any one of claims 1 to 6.

8. The plurality of contact holes extend elongated in a first direction and are arranged in a second direction intersecting the first direction. The display device according to any one of claims 1 to 7.

9. The conductive layer has a plurality of openings that are smaller than each of the plurality of contact holes. The display device according to any one of claims 1 to 8.

10. The end of the conductive layer is located between the first contact portion and the end of the substrate in a plan view. The display device according to any one of claims 1 to 9.

11. The second contact portion is located between the first contact portion and the display area in a plan view. The display device according to any one of claims 1 to 10.

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