Power conversion device and power conversion method, and elevator

Abstract

To provide a power conversion device capable of balancing operation of a plurality of power conversion units in advance, even not having information on switching element characteristics.SOLUTION: A power conversion device includes a first and a second power conversion units (101, 102), common output configured with parallel connection of output of each power conversion unit, and a control device for controlling each power conversion unit, driver circuits (113 to 124) of switching elements configuring the first and the second power conversion circuits are configured to be capable of adjusting delay amount of drive signals, and when the delay amount of the driver circuit is set, the control device sets delay amount at the driver circuit for driving a switching element of a first phase or at the driver circuit for driving a switching element of a second phase according to current unbalance between a first phase (109) and a second phase (112) for each of the plurality of pairs mutually different two phases in the power conversion circuit.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a power conversion device in which multiple power conversion units are connected in parallel, a power conversion method by connecting multiple power conversion units in parallel, and an elevator using the power conversion device. [Background technology]

[0002] Power converters can convert DC power to AC power or AC power to DC power through the switching operation of semiconductor elements, and are widely applied in fields ranging from low-power applications such as home appliances to medium and high-power applications such as elevators, automobiles, and railways.

[0003] One way to increase the capacity of a power converter is to connect the outputs of multiple power converter units in parallel to increase the total capacity. However, variations in the characteristics of semiconductor elements in multiple power converter units can lead to an imbalance in the output current of each power converter unit. This imbalance in the output current of each power converter unit can result in the power converter not being able to obtain a capacity commensurate with the number of power converter units connected in parallel, or it can cause malfunctions in the operation of the power converter.

[0004] Conventional techniques for suppressing imbalances in the output currents of multiple power conversion units connected in parallel are known, as described in Patent Documents 1 and 2.

[0005] In the technology described in Patent Document 1, the deviation between the average value of the output currents of multiple inverters connected in parallel and the output current of each inverter is detected, and the on-pulse width of the PWM control signal applied to the switching element is shortened so that this deviation becomes zero.

[0006] In the technology described in Patent Document 2, each power conversion unit has characteristic map information that represents the relationship between the element characteristics of a semiconductor switching element and the control drive voltage. In each power conversion unit, a drive voltage is set for a common element characteristic target value that is shared by multiple power conversion units, based on the characteristic map information. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 10-94258 [Patent Document 2] Japanese Patent Publication No. 2019-4558 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] The technology described in Patent Document 1 controls the switching element of a power conversion unit when an imbalance occurs in the output current of multiple power conversion units. However, the above-mentioned prior art described in Patent Document 1 does not pre-balance the operation of each of the multiple power conversion units when the power conversion device is operating.

[0009] The technology described in Patent Document 2 allows for balancing the operation of multiple power conversion units, but it is necessary to obtain characteristic map information for multiple switching elements in advance through actual measurements or other means.

[0010] Therefore, the present invention provides a power conversion device and a power conversion method that can pre-balance the operations of multiple power conversion units even without information on the characteristics of multiple switching elements, as well as an elevator equipped with such a power conversion device. [Means for solving the problem]

[0011] In order to solve the above problems, a power conversion device according to the present invention includes a first power conversion unit having a first power conversion circuit, a second power conversion unit having a second power conversion circuit, an output of the first power conversion unit, and an output of the power conversion unit are connected in parallel to form a common output connected to a load, and a control device that controls the load by controlling the first power conversion unit and the second power conversion unit, and further has the following means. It includes a plurality of drive circuits that drive and control a plurality of switching elements constituting the first power conversion circuit and the second power conversion circuit, and each of the plurality of drive circuits is configured to be able to adjust the delay amount of the drive signal applied to the switching element to be driven. The control device sets a delay amount for each of the plurality of drive circuits. When setting the delay amount, the control device Of the three phases , in each of a plurality of sets of two different phases Either the first power conversion circuit or the second power conversion circuit First phase Upper arm and Either the first power conversion circuit or the second power conversion circuit Second phase The upper arm, and the lower arm of the third phase of either the first power conversion circuit or the second power conversion circuit, energize the switching elements in each of them, Alternatively, energize the switching elements in the lower arm of the first phase of either the first power conversion circuit or the second power conversion circuit, the lower arm of the second phase of either the first power conversion circuit or the second power conversion circuit, and the upper arm of the third phase of either the first power conversion circuit or the second power conversion circuit. between the energized switching elements of the first phase and the second phase Current difference Current imbalance as detect, and according to the detected current imbalance, To reduce current imbalance, set the delay amount in the drive circuit that drives the switching element of the first phase or the delay amount in the drive circuit that drives the switching element of the second phase.

[0012] In order to solve the above problems, a power conversion method according to the present invention is a method of performing power conversion by connecting in parallel an output of a first power conversion unit including a first power conversion circuit and an output of a second power conversion unit of a second power conversion circuit, and in the first power conversion circuit and the second power conversion circuit Of the three phases , in each of a plurality of sets of two different phases Either the first power conversion circuit or the second power conversion circuit First phase Upper arm and Either the first power conversion circuit or the second power conversion circuit Second phase The upper arm, and the lower arm of the third phase of either the first power conversion circuit or the second power conversion circuit, energize the switching elements in each of them, Alternatively, energize the switching elements in the lower arm of the first phase of either the first power conversion circuit or the second power conversion circuit, the lower arm of the second phase of either the first power conversion circuit or the second power conversion circuit, and the upper arm of the third phase of either the first power conversion circuit or the second power conversion circuit. between the energized switching elements of the first phase and the second phase Current difference Current imbalance as Detect and, according to the detected current imbalance, To reduce current imbalance, The switching timing of the first-phase or second-phase switching element is adjusted.

[0013] To solve the above problems, the elevator according to the present invention comprises a car and a counterweight, a main rope for suspending the car and counterweight in the hoistway, a hoisting machine for driving the main rope, an electric motor for driving the hoisting machine, and a power converter for supplying power to the electric motor, wherein the power converter is the power converter according to the present invention. [Effects of the Invention]

[0014] According to the present invention, even without information on the characteristics of multiple switching elements, the operations of multiple power conversion units can be pre-balanced.

[0015] Other issues, configurations, and effects not mentioned above will be clarified by the following description of the embodiments. [Brief explanation of the drawing]

[0016] [Figure 1] This is a configuration diagram showing the overall configuration of an elevator system, which is one embodiment of the system. [Figure 2] Figure 1 is a circuit diagram showing the configuration of the inverse converter. [Figure 3] This circuit diagram shows an example of the current path of the power conversion unit when the motor control unit performs drive signal delay adjustment control. [Figure 4] This is a functional block diagram showing the operating section during drive signal delay adjustment control in the power conversion device of the embodiment. [Figure 5] This is a schematic flowchart of the drive signal delay adjustment control performed by the control device 9 (Figure 1). [Figure 6] This circuit diagram shows an example of the current path of the power conversion unit when the motor control unit 106 performs drive signal delay adjustment control. [Figure 7]This circuit diagram shows an example of the current path of the power conversion unit when the motor control unit 106 performs drive signal delay adjustment control. [Figure 8] This circuit diagram shows an example of the current path of the power conversion unit when the motor control unit 106 performs drive signal delay adjustment control. [Figure 9] This flowchart shows the process for reducing the output current imbalance of power conversion units 101 and 102. [Figure 10] This waveform diagram shows an example of the operating current and operating voltage before current imbalance reduction when the X-phase semiconductor switching device and the Y-phase semiconductor switching device are energized in drive signal delay adjustment control. [Figure 11] The waveform diagram in Figure 10 shows an example of operating current and operating voltage when the current imbalance is reduced by drive signal delay adjustment control. [Figure 12] This waveform diagram shows an example of operating current and operating voltage when current imbalance is reduced by drive signal delay adjustment control. [Modes for carrying out the invention]

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings, using the following examples.

[0018] In each figure, elements with the same reference number represent the same or similar functional components.

[0019] Figure 1 is a diagram showing the overall configuration of an elevator system that is one embodiment of the present invention.

[0020] In elevator system 1, an elevator car 6 and a counterweight 7 are connected to one end and the other end of a main rope 5, respectively. The main rope 5 is wound around a traction sheave on a hoisting machine driven by a three-phase synchronous motor 105. As a result, the elevator car 6 and counterweight 7 are suspended within the hoistway. When the hoisting machine is driven by the three-phase synchronous motor 105, the traction sheave rotates, and the main rope 5 is frictionally driven, causing the elevator car 6 and counterweight 7 to move in opposite directions within the hoistway. For example, a permanent magnet synchronous motor is used as the three-phase synchronous motor 105.

[0021] The three-phase synchronous motor 105 is supplied with three-phase AC power of variable voltage and variable frequency by the following power conversion device.

[0022] This power converter includes a forward converter 10 having multiple (two in Figure 1) forward conversion units 12, 13 (AC / DC conversion units), and a reverse converter 11 having multiple (two in Figure 1) reverse conversion units 14, 15 (DC / AC conversion units).

[0023] The AC inputs of forward conversion units 12 and 13 are connected in parallel to each other, forming the AC inputs of the forward conversion device 10. Similarly, the DC outputs of forward conversion units 12 and 13 are connected in parallel to each other, forming the DC outputs of the forward conversion device 10.

[0024] The DC inputs of the inverter units 14 and 15 are connected in parallel to each other, forming the DC inputs of the inverter device 11. The AC outputs of the inverter units 14 and 15 are also connected in parallel to each other, forming the AC outputs of the inverter device 11.

[0025] The forward converter 10 receives three-phase AC power from the commercial three-phase AC power supply 2 via the filter circuit 3. The forward converter 10 converts the input three-phase AC power into DC power and outputs this DC power.

[0026] The inverse converter 11 receives DC power from the forward converter 10. The inverse converter 11 converts the input DC power into three-phase AC power and outputs this three-phase AC power.

[0027] The three-phase AC power output by the inverter 11 is supplied to the three-phase synchronous motor 105 via the filter circuit 4.

[0028] The operation of the elevator car 6 is controlled by the control device 9, which controls the power converter and the brake device 30. The control device 9 detects the travel speed of the elevator car 6 based on the detection signal from the rotation detector 300, which detects the rotation of the three-phase synchronous motor 105, and controls the three-phase synchronous motor 105 by controlling the power converter so that the detected travel speed matches a predetermined speed command value. At this time, the control device 9 generates a current command value from the speed command value and controls the power converter so that the motor current detected by the current detectors 125, 126, and 127 (in Figure 1, for convenience, the three current detectors for the three phases are shown as one current detector) matches the current command value.

[0029] When the moving elevator car 6 comes to a stop, the control device 9 transitions the brake device 30 from the released state to the braking state. The braking state of the brake device 30 is maintained while the elevator car 6 is stopped. When the stopped elevator car 6 starts moving, that is, when the elevator car 6 starts up, the control device 9 transitions the brake device 30 from the braking state to the released state.

[0030] When the elevator car 6 is started, the control device 9 performs so-called starting torque compensation control from the time the doors of the elevator car 6 begin to close until the brake device 30 transitions from the braking state to the release state. In the starting torque compensation control, the control device 9 calculates an unbalanced torque due to the weight difference between the elevator car 6 and the counterweight 7, based on the load of the elevator car 6 detected by the load sensor 200 provided on the elevator car 6. Furthermore, the control device 9 controls the power converter so that the three-phase synchronous motor 105 generates a motor torque that balances the calculated unbalanced torque. As a result, when the elevator car 6 is started, the sudden movement of the elevator car 6 when the brake device 30 transitions from the braking state to the release state is prevented.

[0031] As will be described later, the control device 9 has a function to adjust the switching operation of the multiple semiconductor switching elements that make up the inverse conversion units 14 and 15 in order to balance the output currents of the inverse conversion units 14 and 15.

[0032] Figure 2 is a circuit diagram showing the configuration of the inverse converter (11) shown in Figure 1.

[0033] Power conversion units 101 and 102 correspond to the inverse conversion units 14 and 15 in Figure 1, respectively.

[0034] Each of the power conversion units 101 and 102 has a three-phase inverse conversion circuit. The three-phase AC output of the three-phase inverse conversion circuit of power conversion unit 101 and the three-phase AC output of the three-phase inverse conversion circuit of power conversion unit 102 are connected in parallel to each other via the wiring impedance 103 on the power conversion unit 101 side and the wiring impedance 104 on the power conversion unit 102 side. The common three-phase AC outputs U, V, and W of power conversion units 101 and 102 are connected to the U-phase winding, V-phase winding, and W-phase winding of the three-phase synchronous motor 105, respectively.

[0035] The DC input of the three-phase inverse converter circuit of power conversion unit 101 and the DC input of the three-phase inverse converter circuit of power conversion unit 102 are connected in parallel to each other. A DC power supply and a smoothing capacitor are connected to the DC input of the three-phase inverse converter circuit of power conversion unit 101, as shown in Figure 2. The DC power supply and smoothing capacitor shown in Figure 2 correspond to the forward converter 10 shown in Figure 1.

[0036] The three-phase inverse conversion circuit of the power conversion unit 101 consists of a U-phase semiconductor switching device 107, a V-phase semiconductor switching device 109, and a W-phase semiconductor switching device 111. The U-phase semiconductor switching device 107 constitutes the U-phase upper arm and the U-phase lower arm. The V-phase semiconductor switching device 109 constitutes the V-phase upper arm and the V-phase lower arm. The W-phase semiconductor switching device 111 constitutes the W-phase upper arm and the W-phase lower arm.

[0037] The three-phase inverse conversion circuit of the power conversion unit 102 consists of a U-phase semiconductor switching device 108, a V-phase semiconductor switching device 110, and a W-phase semiconductor switching device 112. The U-phase semiconductor switching device 108 constitutes the U-phase upper arm and the U-phase lower arm. The V-phase semiconductor switching device 110 constitutes the V-phase upper arm and the V-phase lower arm. The W-phase semiconductor switching device 112 constitutes the W-phase upper arm and the W-phase lower arm.

[0038] Examples of the semiconductor switching devices mentioned above include power semiconductor modules (e.g., IGBT modules).

[0039] Each arm in power conversion units 101 and 102 is a circuit portion consisting of a parallel connection of a semiconductor switching element and a freewheeling diode. In this embodiment 1, an IGBT (insulated gate bipolar transistor) is used as the semiconductor switching element.

[0040] Each semiconductor switching element in the U-phase upper arm, V-phase upper arm, W-phase upper arm, U-phase lower arm, V-phase lower arm, and W-phase lower arm of the power conversion unit 101 is driven on and off by the U-phase upper arm drive circuit 113, the V-phase upper arm drive circuit 114, the W-phase upper arm drive circuit 115, the U-phase lower arm drive circuit 116, the V-phase lower arm drive circuit 117, and the W-phase lower arm drive circuit 118, respectively.

[0041] The semiconductor switching elements in the U-phase upper arm, V-phase upper arm, W-phase upper arm, U-phase lower arm, V-phase lower arm, and W-phase lower arm of the power conversion unit 102 are each driven on and off by the drive circuit 119 for the U-phase upper arm, the drive circuit 120 for the V-phase upper arm, the drive circuit 121 for the W-phase upper arm, the drive circuit 122 for the U-phase lower arm, the drive circuit 123 for the V-phase lower arm, and the drive circuit 124 for the W-phase lower arm, respectively.

[0042] Each drive circuit in the power conversion units 101 and 102 drives the semiconductor switching elements connected to each drive circuit on and off in response to the on / off control signal from the motor control unit 106. The motor control unit 106 is included in the control device 9 shown in Figure 1.

[0043] Each drive circuit in the power conversion units 101 and 102 has a variable delay unit, which allows the timing of the drive signal supplied to the semiconductor switching element to be delayed compared to the timing of the on / off control signal from the motor control unit 106.

[0044] In this embodiment, the current imbalance of each semiconductor switching element is reduced by adjusting the timing delay of the drive signal using a variable delay unit for each drive circuit. This reduces the output current imbalance of the power conversion units 101 and 102.

[0045] The motor control unit 106 has, as operating modes, motor speed control, the aforementioned starting torque compensation control, and adjustment of the timing delay of the drive signal (hereinafter referred to as "drive signal delay adjustment control").

[0046] In drive signal delay adjustment control, the motor control unit 106 energizes two semiconductor switching elements in either the upper arm of one of the two different phases or the lower arm of one of the two different phases in either the power conversion unit 101 or 102. At this time, the motor control unit 106 selectively applies ON control signals to two drive circuits among the drive circuits 113 to 124 that drive the two energized semiconductor switching elements. These two semiconductor switching elements are the semiconductor switching elements for which current imbalance is to be reduced.

[0047] The motor control unit 106 turns on a semiconductor switching element in an arm opposite to the arm equipped with these two semiconductor switching elements, in order to energize the two semiconductor switching elements, the semiconductor switching element in a different phase from the two semiconductor switching elements in the arm located on the upper and lower sides of the arm.

[0048] Hereinafter, the arms equipped with these two semiconductor switching elements will be referred to as the X-phase A arm and the Y-phase A arm. X and Y are either U, V, or W, and are different from each other. A is either "up" or "down". Furthermore, the arm equipped with a semiconductor switching element that is turned on to energize these two semiconductor switching elements will be referred to as the Z-phase B arm. Z is either U, V, or W, and is different from X and Y. B is either "up" or "down", and is different from A.

[0049] The motor control unit 106 keeps the semiconductor switching elements in the arms other than the X-phase A arm, Y-phase A arm, and Z-phase B arm of either the power conversion unit 101 or 102, as well as the upper and lower arms of the three-phase semiconductor devices in the other power conversion unit 101 or 102, in the OFF state.

[0050] The currents flowing through the semiconductor switching elements of the X-phase A-arm and Y-phase A-arm in the same power conversion unit are equal to the X-phase motor current and the Y-phase motor current, respectively, and are therefore detected by two of the current detectors 125, 126, and 127, namely the current detectors for detecting the X-phase motor current and the current detectors for detecting the Y-phase motor current.

[0051] The current imbalance detection unit 128 detects the current imbalance in each semiconductor switching element of the X-phase A-arm and Y-phase A-arm in the same power conversion unit based on the detected X-phase motor current and Y-phase motor current. The variable delay unit in the drive circuit that provides a drive signal to each semiconductor switching element adjusts the amount of delay of the drive signal relative to the control signal in order to reduce the current imbalance, according to the current imbalance detected by the current imbalance detection unit 128.

[0052] The current imbalance detection unit 128, along with the motor control unit 106, is included in the control device 9 shown in Figure 1.

[0053] Furthermore, in the drive signal delay adjustment control, the motor control unit 106 energizes one phase semiconductor switching element (X-phase A-arm) in either the upper arm or the lower arm of the power conversion unit 101, and the other phase semiconductor switching element (Y-phase A-arm) in the same arm of the power conversion unit 102. At this time, the motor control unit 106 selectively provides ON control signals to two drive circuits from among the drive circuits 113 to 124 that drive the two energized semiconductor switching elements. These two semiconductor switching elements are the semiconductor switching elements targeted for reducing operational imbalance.

[0054] In order to energize the two semiconductor switching elements, the motor control unit 106 turns on a semiconductor switching element (Z-phase B-arm) in an arm opposite to the arm equipped with these two semiconductor switching elements, in one of the power conversion units 101 and 102, which is in a different phase from the two semiconductor switching elements.

[0055] The motor control unit 106 keeps the semiconductor switching elements in the arms of power conversion units 101 and 102 in the OFF state, except for the X-phase A arm in power conversion unit 101, the Y-phase A arm in power conversion unit 102, and the Z-phase B arm in either power conversion unit 101 or 102.

[0056] The currents flowing through the semiconductor switching elements of the X-phase A-arm in power conversion unit 101 and the Y-phase A-arm in power conversion unit 102 are equal to the X-phase motor current and the Y-phase motor current, respectively, and are detected by two of the current detectors 125, 126, and 127, namely the current detectors for detecting the X-phase motor current and the current detectors for detecting the Y-phase motor current.

[0057] The current imbalance detection unit 128 detects the current imbalance in each semiconductor switching element of the X-phase A-arm in the power conversion unit 101 and the Y-phase A-arm in the power conversion unit 102, based on the detected X-phase motor current and Y-phase motor current. The variable delay unit in the drive circuit that provides a drive signal to each semiconductor switching element adjusts the amount of delay of the drive signal relative to the control signal in order to reduce the current imbalance, according to the current imbalance detected by the current imbalance detection unit 128.

[0058] By sequentially reducing the imbalance in the operation of semiconductor switching elements in multiple sets of X-phase A-arms and Y-phase A-arms in the U-phase upper and lower arms, V-phase upper and lower arms, and W-phase upper and lower arms of the power conversion units 101 and 102, as described above, the imbalance in the output current of the power conversion units 101 and 102 can be reduced.

[0059] Figure 3 is a circuit diagram showing an example of the current path of the power conversion unit when the motor control unit 106 performs drive signal delay adjustment control.

[0060] This example shows the current path when reducing the current imbalance between the V-phase semiconductor switching device 109 and the W-phase semiconductor switching device 111 provided in the power conversion unit 101. In this case, the current imbalance between semiconductor switching elements in the V-phase upper arm and the W-phase upper arm is reduced, as is the current imbalance between semiconductor switching elements in the V-phase lower arm and the W-phase lower arm. Figure 3 shows the current path in the latter case.

[0061] In Figure 3, the motor control unit 106 turns on the semiconductor switching elements of the V-phase lower arm and W-phase lower arm to reduce current imbalance, and also turns on the semiconductor switching element of the U-phase upper arm in the U-phase semiconductor switching device of the power conversion unit 101 in order to energize these semiconductor switching elements. The motor control unit 106 keeps the other semiconductor switching elements in the power conversion unit 101, namely the semiconductor switching elements in the U-phase lower arm, V-phase upper arm, and W-phase upper arm, in the OFF state.

[0062] The motor control unit 106 repeatedly turns on and off the semiconductor switching elements of the U-phase upper arm, V-phase lower arm, and W-phase lower arm. At this time, after turning on the semiconductor switching element of the U-phase upper arm, the motor control unit 106 sends an ON control signal to the V-phase lower arm drive circuit 117 and the W-phase lower arm drive circuit 118 at the same timing. The motor control unit 106 also sends an OFF control signal to the V-phase lower arm drive circuit 117 and the W-phase lower arm drive circuit 118 at the same timing to turn off the semiconductor switching elements of the V-phase lower arm and the W-phase lower arm, and then turns off the semiconductor switching element of the U-phase upper arm.

[0063] Furthermore, the adjustment of the drive signal delay amount to reduce the current imbalance, as described later, is performed for each ON period of the semiconductor switching element in the V-phase lower arm and the W-phase lower arm.

[0064] Furthermore, the motor control unit 106 does not operate the U-phase semiconductor switching device 108, the V-phase semiconductor switching device 110, and the W-phase semiconductor switching device 112 provided in the power conversion unit 102. In other words, the motor control unit 106 keeps the semiconductor switching elements of each upper and lower arm in these semiconductor switching devices in the OFF state. In Figure 3, the semiconductor switching devices that do not operate (108, 110, 112) are marked with an "X".

[0065] As shown by the dashed lines in Figure 3, in the power conversion unit 101, the current flowing through the semiconductor switching element in the V-phase lower arm and the current flowing through the semiconductor switching element in the W-phase lower arm are equal to the V-phase motor current and the W-phase motor current, respectively. Therefore, in the power conversion unit 101, the currents flowing through the semiconductor switching elements in the V-phase lower arm and the W-phase lower arm are detected by the current detectors 126 and 127, respectively.

[0066] Figure 4 is a functional block diagram showing the operating section during drive signal delay adjustment control in the power converter of this embodiment.

[0067] Figure 4 shows the operating section when reducing the current imbalance between the semiconductor switching elements of the V-phase lower arm and W-phase lower arm of the power conversion unit 101 (see Figure 3).

[0068] The motor control unit 106 provides the power converter with a group of control signals S for adjusting the drive signal delay. In the case of Figure 4, the control signals S provided to the drive circuits 113, 117, and 118 are part of the control signal group S. 113 ,S 117 ,S 118 This is an ON control signal. Control signals S are given to the other drive circuits 114-116, 119-124. 114 ~S 116 ,S 119 ~S 124 This is an off control signal.

[0069] When the semiconductor switching elements in the lower arm of the V-phase semiconductor switching device 109 and the semiconductor switching elements in the lower arm of the W-phase semiconductor switching device 111 are turned on, the V-phase motor current and the W-phase motor current flowing through them are detected by current detectors 126 and 127, respectively.

[0070] The current imbalance detection unit 128 calculates, using an adder-subtractor, the current difference (I V ) between the V-phase motor current (I W ) detected by the current detector 126 and the W-phase motor current (I V -I W ), that is, the current imbalance. Further, the current imbalance detection unit 128 calculates, using the PI controller 402, a delay amount that reduces the calculated current difference (I V -I W ), for example, a delay amount that approaches zero. The current imbalance detection unit 128 sets the calculated delay amount in the variable delay unit of the drive circuit 117.

[0071] The drive circuit 117 outputs a drive signal whose on / off timing of the control signal S117 is shifted by the variable delay unit according to the delay amount set in the variable delay unit. Thereby, the turn-on timing or turn-off timing of the semiconductor switching element in the lower arm of the V-phase semiconductor switching device 109 is adjusted so that the current imbalance between the semiconductor switching element in the lower arm of the V-phase semiconductor switching device 109 and the semiconductor switching element in the lower arm of the W-phase semiconductor switching device 111 is reduced.

[0072] In this embodiment, when the V-phase motor current (I V ) detected by the current detector 126 is greater than the W-phase motor current (I W ) detected by the current detector 127, that is, when the current difference (I V -I WIf ) is positive, the PI controller 402 calculates a delay amount that delays the turn-on timing of the semiconductor switching element of the lower arm of the V-phase semiconductor switching device 109. At this time, the W-phase motor current (I W ) is the V-phase motor current (I V ) is smaller than the current difference (I W -I V Since ) is negative, the PI controller 403 calculates a delay amount that advances the turn-on timing of the semiconductor switching element of the lower arm of the W-phase semiconductor switching device 111. Alternatively, one of the delay amounts may be set.

[0073] Furthermore, the current imbalance detection unit 128 detects the W-phase motor current (I) detected by the current detector 127. W ) and the V-phase motor current (I) detected by the current detector 126 V ) current difference (I W -I V ), that is, the current imbalance is calculated by an adder / subtractor. Furthermore, the current imbalance detection unit 128 uses the PI controller 403 to calculate the current difference (I W -I V Depending on the current imbalance, the current imbalance detection unit 128 calculates a delay amount that reduces this current difference, for example, by bringing it close to zero. The current imbalance detection unit 128 sets the calculated delay amount in the variable delay unit of the drive circuit 118.

[0074] The drive circuit 118 outputs a drive signal in which the on / off timing of the control signal S118 is shifted by the variable delay unit according to the delay amount set in the variable delay unit. As a result, the turn-on timing or turn-off timing of the semiconductor switching element on the lower arm of the W-phase semiconductor switching device 111 is adjusted so as to reduce the current imbalance between the semiconductor switching element on the lower arm of the W-phase semiconductor switching device 111 and the semiconductor switching element on the lower arm of the V-phase semiconductor switching device 109.

[0075] The motor control unit 106 repeatedly performs the drive signal delay adjustment control described above at a predetermined period. At this time, the motor control unit 106 calculates the current difference (I) calculated by the current imbalance detection unit 128. V -I W ,I W -I V The system monitors the current difference, and when it determines that the magnitude of the current difference has been reduced to a predetermined value or less, it terminates the drive signal delay adjustment control that reduces the current imbalance between the semiconductor switching element of the lower arm of the V-phase semiconductor switching device 109 and the semiconductor switching element of the lower arm of the W-phase semiconductor switching device 111.

[0076] The motor control unit 106 sequentially performs the same drive signal delay adjustment control on multiple sets of X-phase A arms and Y-phase A arms in the upper and lower arms of two power conversion units. These multiple sets include sets of X-phase A arms and Y-phase A arms in the same power conversion unit, and sets of X-phase A arms in power conversion unit 101 and Y-phase A arms in power conversion unit 102. This reduces the imbalance in the output current of power conversion units 101 and 102.

[0077] The current imbalance detection unit 128 selects the X-phase motor current and the Y-phase motor current in response to a command signal from the motor control unit 106, such as a control signal S, calculates the current difference, i.e., current imbalance, and selects a drive circuit to set the delay amount.

[0078] Figure 5 is a schematic flowchart of the drive signal delay adjustment control performed by the control device 9 (Figure 1) in this embodiment.

[0079] When processing begins, first, in step S501, the control device 9 is set to DC current mode.

[0080] The DC current mode is a control operation mode that causes the three-phase inverse converter circuit in power conversion units 101 and 102 to operate in DC mode. For example, in the case of PWM control, the DC current mode is set by switching the voltage command compared with the carrier wave to a DC voltage command.

[0081] In this embodiment, in the drive signal delay adjustment control, a DC current mode is set in order to supply DC current to the X-phase A arm and the Y-phase A arm.

[0082] Furthermore, the starting torque compensation control, which is performed just before the elevator car departs from a stopping floor and before the brake device is released, is performed in DC current mode. Therefore, in this embodiment, when the elevator car starts up, the drive signal delay adjustment control is performed before the starting torque compensation control is performed. Consequently, since the drive signal delay adjustment control is performed while the elevator car 6 is stopped by the brake device 30, the ride comfort of passengers inside the elevator car 6 is not compromised. In addition, since the drive signal delay adjustment control is performed each time the elevator car starts up, the current imbalance of the power conversion units 101 and 102 can be kept low.

[0083] Next, in step S502, the control device 9 energizes the semiconductor switching elements of the X-phase A-arm and Y-phase A-arm via the motor control unit 106, and detects the X-phase motor current and Y-phase motor current using current detectors (125, 126, 127).

[0084] Next, in step S503, the control device 9 calculates the current imbalance of the X-phase motor current and Y-phase motor current detected by the current imbalance detection unit 128.

[0085] Next, in step S504, the control device 9 determines, based on the motor control unit 106, whether the current imbalance calculated in step S503 is less than or equal to a specified value pre-set in the control device 9. If the control device 9 determines that the current imbalance is less than or equal to the specified value (Yes in step S504), it terminates the drive signal delay adjustment control and then executes step S506. If the control device 9 determines that the current imbalance is not less than or equal to the specified value (No in step S504), that is, if it determines that it is greater than the specified value, it then executes step S505.

[0086] In step S505, the control device 9 uses the current imbalance detection unit 128 to calculate a delay amount that reduces the current imbalance calculated in step S503, and adjusts the delay amount set in the variable delay section of the drive circuit for the semiconductor switching elements of the X-phase A-arm and Y-phase A-arm to the calculated delay amount. After executing step S505, the control device 9 executes step S502 again.

[0087] In step S505, the control device 9 performs starting torque compensation control. At this time, the operating mode of the control device 9 is the DC current mode, the same as when the drive signal delay adjustment control is performed (S502 to S505). After executing step S505, the control device 9 terminates the series of processes.

[0088] Although not shown in the diagram, the processes S502 to S505 are executed sequentially for multiple sets of X-phase A-arms and Y-phase A-arms.

[0089] Figure 6 is a circuit diagram showing an example of the current path of the power conversion unit when the motor control unit 106 performs drive signal delay adjustment control.

[0090] This example, similar to the example in Figure 3, shows the current path when reducing the current imbalance between the V-phase semiconductor switching device 109 and the W-phase semiconductor switching device 111 provided in the power conversion unit 101. In this case, the current imbalance between semiconductor switching elements in the V-phase upper arm and the W-phase upper arm is reduced, as is the current imbalance between semiconductor switching elements in the V-phase lower arm and the W-phase lower arm. Figure 6 shows the current path in the former case.

[0091] In Figure 6, the motor control unit 106 turns on the semiconductor switching elements of the V-phase upper arm and W-phase upper arm to reduce current imbalance, and also turns on the semiconductor switching element of the U-phase lower arm in the U-phase semiconductor switching device 107 of the power conversion unit 101 in order to energize these semiconductor switching elements. The motor control unit 106 keeps the other semiconductor switching elements in the power conversion unit 101, namely the semiconductor switching elements of the U-phase upper arm, V-phase lower arm, and W-phase lower arm, in the OFF state.

[0092] The motor control unit 106 repeatedly turns on and off the semiconductor switching elements of the U-phase lower arm, V-phase upper arm, and W-phase upper arm. At this time, after turning on the semiconductor switching element of the U-phase lower arm, the motor control unit 106 sends an ON control signal to the V-phase upper arm drive circuit 114 and the W-phase upper arm drive circuit 115 at the same timing. Also, after turning on the semiconductor switching element of the U-phase lower arm, the motor control unit 106 sends an OFF control signal to the V-phase upper arm drive circuit 114 and the W-phase upper arm drive circuit 115 at the same timing to turn off the semiconductor switching elements of the V-phase upper arm and the W-phase upper arm, and then turns off the semiconductor switching element of the U-phase lower arm.

[0093] Furthermore, the adjustment of the drive signal delay amount to reduce current imbalance, as described later, is performed for each on-period of the semiconductor switching elements of the V-phase upper arm and the W-phase upper arm.

[0094] Furthermore, the motor control unit 106 does not operate the U-phase semiconductor switching device 108, the V-phase semiconductor switching device 110, and the W-phase semiconductor switching device 112 provided in the power conversion unit 102. In other words, the motor control unit 106 keeps the semiconductor switching elements of each upper and lower arm in these semiconductor switching devices in the OFF state. In Figure 6, the semiconductor switching devices that do not operate (108, 110, 112) are marked with an "X".

[0095] As shown by the dashed lines in Figure 6, in the power conversion unit 101, the current flowing through the semiconductor switching elements in the V-phase upper arm and the W-phase upper arm are equal to the V-phase motor current and the W-phase motor current, respectively. Therefore, in the power conversion unit 101, the currents flowing through the semiconductor switching elements in the V-phase upper arm and the W-phase upper arm are detected by the current detectors 126 and 127, respectively.

[0096] Figure 7 is a circuit diagram showing an example of the current path of the power conversion unit when the drive signal delay adjustment control of the motor control unit 106 is executed.

[0097] This example shows the current path when reducing the current imbalance between the V-phase semiconductor switching device 109 of the power conversion unit 101 and the W-phase semiconductor switching device 112 of the power conversion unit 102. In this case, the current imbalance between the semiconductor switching elements in the V-phase upper arm (hereinafter referred to as "V-phase upper arm (101)") of the V-phase semiconductor switching device 109 of the power conversion unit 101 and the W-phase upper arm (hereinafter referred to as "W-phase upper arm (102)") of the W-phase semiconductor switching device 112 of the power conversion unit 102 is reduced, as is the current imbalance between the semiconductor switching elements in the V-phase lower arm (hereinafter referred to as "V-phase lower arm (101)") of the V-phase semiconductor switching device 109 of the power conversion unit 101 and the W-phase lower arm (hereinafter referred to as "W-phase lower arm (102)") of the W-phase semiconductor switching device 112 of the power conversion unit 102. Figure 7 shows the current path in the latter case.

[0098] In Figure 7, the motor control unit 106 turns on the semiconductor switching elements of the V-phase lower arm (101) and W-phase lower arm (102) to reduce current imbalance, and also turns on the semiconductor switching element of the U-phase upper arm (hereinafter referred to as "U-phase upper arm (101)") in the U-phase semiconductor switching device 107 of the power conversion unit 101 in order to energize these semiconductor switching elements. Hereinafter, the X-phase A arms in the power conversion units 101 and 102 will be referred to as "X-phase A arm (101)" and "X-phase A arm (102)," respectively.

[0099] The motor control unit 106 keeps the other semiconductor switching elements in the power conversion units 101 and 102, namely the U-phase lower arm (101), V-phase upper arm (101), W-phase upper arm (101), W-phase lower arm (101), U-phase upper arm (102), U-phase lower arm (102), V-phase upper arm (102), V-phase lower arm (102), and W-phase upper arm (102), in the OFF state. Therefore, the motor control unit 106 does not operate the W-phase semiconductor switching device 111 in the power conversion unit 101, and the U-phase semiconductor switching device 108 and V-phase semiconductor switching device 110 in the power conversion unit 102. In Figure 7, the semiconductor switching devices that do not operate (111, 108, 110) are marked with an "X".

[0100] The motor control unit 106 repeatedly turns on and off the semiconductor switching elements of the U-phase upper arm (101), V-phase lower arm (101), and W-phase lower arm (102). At this time, after turning on the semiconductor switching element of the U-phase upper arm (101), the motor control unit 106 provides ON control signals to the drive circuit 117 for the V-phase lower arm (101) and the drive circuit 124 for the W-phase lower arm (102) at the same timing.

[0101] Furthermore, before turning off the semiconductor switching element of the U-phase upper arm (101), the motor control unit 106 simultaneously provides off control signals to the drive circuit 117 for the V-phase lower arm (101) and the drive circuit 124 for the W-phase lower arm (102) to turn off the semiconductor switching elements of the V-phase lower arm (101) and the W-phase lower arm (102), and then turns off the semiconductor switching element of the U-phase upper arm (101).

[0102] Furthermore, the delay amount of the drive signal to reduce current imbalance is adjusted for each ON period of the semiconductor switching elements of the V-phase lower arm (101) and the W-phase lower arm (102).

[0103] As shown by the dashed lines in Figure 7, the current flowing through the semiconductor switching element in the V-phase lower arm (101) and the current flowing through the semiconductor switching element in the W-phase lower arm (102) are equal to the V-phase motor current and the W-phase motor current, respectively. Therefore, the currents flowing through the semiconductor switching elements in the V-phase lower arm (101) and the W-phase lower arm (102) are detected by the current detectors 126 and 127, respectively.

[0104] Figure 8 is a circuit diagram showing an example of the current path of the power conversion unit when the motor control unit 106 performs drive signal delay adjustment control.

[0105] This example, similar to the example in Figure 7, shows the current path when reducing the current imbalance between the V-phase semiconductor switching device 109 in the power conversion unit 101 and the W-phase semiconductor switching device 112 in the power conversion unit 102. In this case, the current imbalance between semiconductor switching elements in the V-phase upper arm (hereinafter referred to as "V-phase upper arm (101)") of the V-phase semiconductor switching device 109 of the power conversion unit 101 and the W-phase upper arm (hereinafter referred to as "W-phase upper arm (102)") of the W-phase semiconductor switching device 112 of the power conversion unit 102 is reduced, as is the current imbalance between semiconductor switching elements in the V-phase lower arm (hereinafter referred to as "V-phase lower arm (101)") of the V-phase semiconductor switching device 109 of the power conversion unit 101 and the W-phase lower arm (hereinafter referred to as "W-phase lower arm (102)") of the W-phase semiconductor switching device 112 of the power conversion unit 102. Figure 8 shows the current path in the former case.

[0106] In Figure 8, the motor control unit 106 turns on the semiconductor switching elements of the V-phase upper arm (101) and W-phase upper arm (102) to reduce current imbalance, and also turns on the semiconductor switching element of the U-phase lower arm (hereinafter referred to as "U-phase lower arm (101)") in the U-phase semiconductor switching device 107 of the power conversion unit 101 in order to energize these semiconductor switching elements. Hereinafter, the X-phase A arms in the power conversion units 101 and 102 will be referred to as "X-phase A arm (101)" and "X-phase A arm (102)," respectively.

[0107] The motor control unit 106 keeps the other semiconductor switching elements in the power conversion units 101 and 102, namely the U-phase upper arm (101), V-phase lower arm (101), W-phase upper arm (101), W-phase lower arm (101), U-phase upper arm (102), U-phase lower arm (102), V-phase upper arm (102), V-phase lower arm (102), and W-phase lower arm (102), in the OFF state. Therefore, the motor control unit 106 does not operate the W-phase semiconductor switching device 111 in the power conversion unit 101, and the U-phase semiconductor switching device 108 and V-phase semiconductor switching device 110 in the power conversion unit 102. In Figure 8, the semiconductor switching devices that do not operate (111, 108, 110) are marked with an "X".

[0108] The motor control unit 106 repeatedly turns on and off the semiconductor switching elements of the U-phase lower arm (101), V-phase upper arm (101), and W-phase upper arm (102). At this time, after turning on the semiconductor switching element of the U-phase lower arm (101), the motor control unit 106 provides ON control signals to the drive circuit 114 for the V-phase upper arm (101) and the drive circuit 121 for the W-phase upper arm (102) at the same timing.

[0109] Furthermore, before turning off the semiconductor switching element of the U-phase lower arm (101), the motor control unit 106 provides off control signals to the drive circuit 114 for the V-phase upper arm (101) and the drive circuit 121 for the W-phase upper arm (102) at the same timing to turn off the semiconductor switching elements of the V-phase upper arm (101) and the W-phase upper arm (102), and then turns off the semiconductor switching element of the U-phase lower arm (101).

[0110] Furthermore, the delay amount of the drive signal to reduce current imbalance is adjusted for each ON period of the semiconductor switching elements of the V-phase upper arm (101) and the W-phase upper arm (102).

[0111] As shown by the dashed lines in Figure 8, the current flowing through the semiconductor switching element in the V-phase upper arm (101) and the current flowing through the semiconductor switching element in the W-phase upper arm (102) are equal to the V-phase motor current and the W-phase motor current, respectively. Therefore, the currents flowing through the semiconductor switching elements in the V-phase upper arm (101) and the W-phase upper arm (102) are detected by the current detectors 126 and 127, respectively.

[0112] Alternatively, the semiconductor switching element of the U-phase lower arm (102) may be turned on instead of the U-phase lower arm (101).

[0113] Figure 9 is a flowchart showing the process for reducing the output current imbalance of power conversion units 101 and 102.

[0114] In each step, the current imbalance in the X-phase semiconductor switching device (M) in power conversion unit M (where M is 101 or 102) and the Y-phase semiconductor switching device (N) in power conversion unit N (where N is 101 or 102) is reduced. Note that M and N include the case where M=N, i.e., both are 101 or 102.

[0115] When reducing the current imbalance of the X-phase semiconductor switching device (M) and the Y-phase semiconductor switching device (N), the current imbalance between semiconductor switching elements in the X-phase upper arm (hereinafter referred to as "X-phase upper arm (M)") of the X-phase semiconductor switching device (M) and the Y-phase upper arm (hereinafter referred to as "Y-phase upper arm (N)") of the Y-phase semiconductor switching device (N) is reduced, as is the current imbalance between semiconductor switching elements in the X-phase lower arm (hereinafter referred to as "X-phase lower arm (M)") of the X-phase semiconductor switching device (M) and the Y-phase lower arm (hereinafter referred to as "Y-phase lower arm (N)") of the Y-phase semiconductor switching device (N).

[0116] Therefore, the motor control unit 106 performs the aforementioned drive signal delay adjustment control (see Figures 3 and 5) on the semiconductor switching elements in the X-phase upper arm (M) and the Y-phase upper arm (N), and also performs the aforementioned drive signal delay adjustment control (see Figures 3 and 5) on the semiconductor switching elements in the X-phase lower arm (M) and the Y-phase lower arm (N).

[0117] The following describes the process for reducing the output current imbalance of the power conversion units 101 and 102, as shown in Figure 9.

[0118] In step S701, the current imbalance between the V-phase semiconductor switching device (101) (labeled "109" in Figure 2) and the W-phase semiconductor switching device (101) (labeled "111" in Figure 2) is reduced.

[0119] In step S701, the motor control unit 106 performs the aforementioned drive signal delay adjustment control on the semiconductor switching elements in the V-phase upper arm (101) and the W-phase upper arm (101), and also performs the aforementioned drive signal delay adjustment control on the semiconductor switching elements in the V-phase lower arm (101) and the W-phase lower arm (101).

[0120] Next, in step S702, the current imbalance between the V-phase semiconductor switching device (101) and the W-phase semiconductor switching device (102) (labeled "112" in Figure 2) is reduced.

[0121] In step S702, the motor control unit 106 performs the aforementioned drive signal delay adjustment control on the semiconductor switching elements in the V-phase upper arm (101) and the W-phase upper arm (102), and also performs the aforementioned drive signal delay adjustment control on the semiconductor switching elements in the V-phase lower arm (101) and the W-phase lower arm (102).

[0122] Next, in step S703, the current imbalance between the W-phase semiconductor switching device (101) and the V-phase semiconductor switching device (102) (labeled "110" in Figure 2) is reduced.

[0123] In step S703, the motor control unit 106 performs the aforementioned drive signal delay adjustment control on the semiconductor switching elements in the W-phase upper arm (101) and the V-phase upper arm (102), and also performs the aforementioned drive signal delay adjustment control on the semiconductor switching elements in the W-phase lower arm (101) and the V-phase lower arm (102).

[0124] Steps S701 to S703 reduce the relative current imbalances of the V-phase semiconductor switching device (101), the W-phase semiconductor switching device (101), the V-phase semiconductor switching device (102), and the W-phase semiconductor switching device (102).

[0125] Next, in step S704, the current imbalance between the U-phase semiconductor switching device (101) (labeled "107" in Figure 2) and the V-phase semiconductor switching device (101) (labeled "109" in Figure 2) is reduced.

[0126] In step S704, the motor control unit 106 performs the aforementioned drive signal delay adjustment control on the semiconductor switching elements in the U-phase upper arm (101) and the V-phase upper arm (101), and also performs the aforementioned drive signal delay adjustment control on the semiconductor switching elements in the U-phase lower arm (101) and the V-phase lower arm (101).

[0127] Next, in step S705, the current imbalance between the U-phase semiconductor switching device (102) (labeled "108" in Figure 2) and the V-phase semiconductor switching device (101) is reduced.

[0128] In step S705, the motor control unit 106 performs the aforementioned drive signal delay adjustment control on the semiconductor switching elements in the U-phase upper arm (102) and the V-phase upper arm (101), and also performs the aforementioned drive signal delay adjustment control on the semiconductor switching elements in the U-phase lower arm (102) and the V-phase lower arm (101).

[0129] Steps S701 to S703 reduce the current imbalance between the V-phase semiconductor switching device (101) and the V-phase semiconductor switching device (102). Therefore, steps S704 and S705 further reduce the current imbalance between the U-phase semiconductor switching device (101), the V-phase semiconductor switching device (101), the W-phase semiconductor switching device (101), the U-phase semiconductor switching device (102), the V-phase semiconductor switching device (102), and the W-phase semiconductor switching device (102).

[0130] This reduces the current imbalance between the three phases (U phase, V phase, and W phase) of power conversion unit 101 and power conversion unit 102.

[0131] Next, the effect of reducing current imbalance according to this embodiment will be explained.

[0132] Figure 10 is a waveform diagram showing an example of the operating current and operating voltage before current imbalance reduction when the X-phase semiconductor switching device (101 or 102) and the Y-phase semiconductor switching device (101 or 102) are energized in drive signal delay adjustment control. Note that in Figure 10, the names of the current and voltage are written without distinguishing between power conversion units 101 and 102.

[0133] In Figure 10, from top to bottom: X-phase upper arm gate voltage, X-phase lower arm gate voltage, X-phase output voltage, This shows the current imbalance represented by the Y-phase upper arm gate voltage, Y-phase lower arm gate voltage, Y-phase output voltage, the voltage difference between the X-phase output voltage and the Y-phase output voltage (referred to as "X-phase output voltage - Y-phase output voltage" in Figure 10), the X-phase output current, the Y-phase output current, and the difference between the X-phase output current and the Y-phase output current (X-phase output current - Y-phase output current).

[0134] In the example shown in Figure 10, the on-voltage of the semiconductor switching element in the Y-phase upper arm is greater than the on-voltage of the semiconductor switching element in the X-phase upper arm, and the turn-off timing of the semiconductor switching element in the Y-phase upper arm is faster than the turn-off timing of the semiconductor switching element in the X-phase upper arm. As a result, a voltage difference occurs between the X-phase output voltage and the Y-phase output voltage, and a current imbalance occurs according to this voltage difference.

[0135] Figure 11 is a waveform diagram showing an example of operating current and operating voltage when the current imbalance is reduced by drive signal delay adjustment control, as in the example in Figure 10.

[0136] As shown in Figure 11, the rise times of the X-phase upper arm gate voltage and the Y-phase upper arm gate voltage, or the rise times of the X-phase output voltage and the Y-phase output voltage, indicate that the turn-on timing of the semiconductor switching element in the X-phase upper arm is delayed compared to the turn-on timing of the semiconductor switching element in the Y-phase upper arm due to the drive signal delay adjustment control. As a result, a voltage difference is generated in the opposite direction to the voltage difference caused by differences in on-voltage or turn-off timing. This reduces current imbalance.

[0137] As shown in Figure 10, the semiconductor switching elements of the X-phase upper arm and the X-phase lower arm are switched on and off complementaryly. Similarly, the semiconductor switching elements of the Y-phase upper arm and the Y-phase lower arm are switched on and off complementaryly. The semiconductor switching elements of the Z-phase lower arm, which are the counterparts of the Z-phase lower arm that are turned on to energize the semiconductor switching elements of the X-phase upper arm and the Y-phase upper arm that are subject to drive signal delay adjustment control, remain in the off state while the drive signal delay adjustment control is being performed for the semiconductor switching elements of the X-phase upper arm and the Y-phase upper arm.

[0138] Therefore, after the turn-off of each semiconductor switching element in the X-phase upper arm and Y-phase upper arm, X-phase and Y-phase output currents flow in freewheel mode. These X-phase and Y-phase output currents flowing in freewheel mode are affected by variations in the on-voltage and turn-off characteristics of each semiconductor switching element in the X-phase upper arm and Y-phase upper arm. Consequently, the current imbalance detected at this time reflects the effects of variations in on-voltage and turn-off characteristics.

[0139] Figure 12 is a waveform diagram showing an example of operating current and operating voltage when current imbalance is reduced by drive signal delay adjustment control.

[0140] In Figure 12, from top to bottom, the X-phase output voltage, Y-phase output voltage, X-phase output current, and Y-phase output current are shown.

[0141] In this example, similar to the examples in Figures 10 and 11, the on-voltage of the semiconductor switching element in the Y-phase A-arm is greater than the on-voltage of the semiconductor switching element in the X-phase A-arm. Also, unlike the examples in Figures 10 and 11, the turn-off timing of the semiconductor switching element in the Y-phase A-arm is the same as the turn-off timing of the semiconductor switching element in the X-phase A-arm.

[0142] As shown in Figure 12, the drive signal delay adjustment control controls the turn-on timing t of the semiconductor switching element in the X-phase upper arm. SW (X phase) is the turn-on timing t of the semiconductor switching element in the Y phase upper arm. SW (Y phase) Δt ON Only the (X phase) is delayed. This reduces the current imbalance. Furthermore, the X phase output current and the Y phase output current are, respectively, t SW (X phase) and t SW In the Y phase, a minimum value is reached. This reduces the power loss generated by the power conversion units 101 and 102.

[0143] In the above embodiment, the currents flowing through the X-phase A-arm and Y-phase A-arm for drive signal delay adjustment control are equal to the X-phase motor current and Y-phase motor current, respectively, and can be detected by the three current detectors 125, 126, and 127 (Figure 2) for detecting the three-phase motor current. Moreover, during normal operation of the power converter, the current detectors 125, 126, and 127 are used for current control. Therefore, in this embodiment, current imbalance can be reduced while suppressing an increase in the number of current detectors.

[0144] Instead of current detectors 125, 126, and 127 (Figure 2), current detectors can be provided at the outputs of power conversion units 101 and 102 to detect the current flowing through the X-phase A-arm and Y-phase A-arm. In this case, current detectors may be provided at only two of the three-phase outputs, and the output current of the other phase may be calculated by the current imbalance detection unit 128. This can suppress an increase in the number of current detectors. Similarly, in the above embodiment, only the motor current of two of the three-phase motor currents may be detected by current detectors, and the motor current of the other phase may be calculated.

[0145] According to the above embodiment, in each inverse conversion circuit of power conversion units 101 and 102, the switching elements in the first phase and the second phase of each of the multiple sets of two phases that are different from each other are energized, the current imbalance between the energized first phase and second phase switching elements is detected, and the delay amount in the drive circuit that drives the first phase switching element or the drive circuit that drives the second phase switching element is set according to the detected current imbalance. This makes it possible to pre-balance the operations of multiple power conversion units even without information on the characteristics of the multiple switching elements.

[0146] According to the above embodiment, in each inverse conversion circuit of power conversion units 101 and 102, the switching elements in the first phase and the second phase of each of the multiple sets of two phases that are different from each other are energized, the current imbalance between the energized first phase and second phase switching elements is detected, and the delay amount in the drive circuit that drives the first phase switching element or the drive circuit that drives the second phase switching element is set according to the detected current imbalance. This makes it possible to pre-balance the operations of multiple power conversion units even without information on the characteristics of the multiple switching elements.

[0147] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are described in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. In addition, it is possible to add, delete, or replace some of the configurations of each embodiment with other configurations.

[0148] For example, the number of power conversion units in parallel is not limited to two; it can be any number of units depending on the power capacity of each power conversion unit and the desired power capacity of the power conversion device. In this case, the above-described drive signal delay adjustment control is performed on pairs of two of the multiple power conversion units. By performing the drive signal delay adjustment control on multiple pairs, the current imbalance between the multiple power conversion units is reduced.

[0149] Furthermore, the above-mentioned drive signal delay adjustment control may be performed when the elevator is installed. In this case, each drive circuit is pre-set with an arbitrary initial value (for example, zero) as the delay amount.

[0150] Furthermore, the semiconductor switching elements that constitute the inverse conversion circuit in the power conversion unit are not limited to IGBTs; power MOSFETs and other types of elements may also be used.

[0151] Furthermore, the power converter may supply power to other three-phase AC loads, not just three-phase synchronous motors.

[0152] Furthermore, the drive signal delay adjustment control is not limited to the starting torque compensation control described above, but may also be performed in conjunction with rotor positioning control in position sensorless control of a synchronous motor. In other words, it is preferable that the drive signal delay adjustment control in this embodiment be performed before the normal operation of the load, in conjunction with the control performed by the control device in DC operation mode. [Explanation of Symbols]

[0153] 1. Elevator System 2 Commercial three-phase AC power supply 3,4 Filter Circuit 5 Main rope 6. 7 Counterweight 8 motors 9 Control device 10. Forward conversion device 11 Inverse converter 12,13 Forward conversion unit 14,15 Inverse conversion unit 30 Brake system 101,102 Power Conversion Unit 103,104 Wiring impedance 105 Three-phase synchronous motor 106 Motor Control Unit 107,108 Semiconductor switching device for U-phase 109,110 V phase semiconductor switching device 111,112 W-phase semiconductor switching device 113 Drive circuit for U-phase upper arm 114 V-phase upper arm drive circuit 115 W upper arm drive circuit 116 U-phase lower arm drive circuit 117 V-phase lower arm drive circuit 118 W-phase lower arm drive circuit 119 Drive circuit for U-phase upper arm 120V phase upper arm drive circuit 121 W-phase upper arm drive circuit 122 U-phase lower arm drive circuit 123V phase lower arm drive circuit 124 W-phase lower arm drive circuit 125, 126, 127 Current detectors 128 Current imbalance detection unit 200 Load Sensor 300 RPM detector 402,403 PI controllers

Claims

1. A first power conversion unit having a first power conversion circuit, A second power conversion unit having a second power conversion circuit, The output of the first power conversion unit and the output of the second power conversion unit are connected in parallel, and a common output is connected to the load. A control device that controls the load by controlling the first power conversion unit and the second power conversion unit, In a power conversion device equipped with, The system comprises multiple drive circuits for driving and controlling multiple switching elements that constitute the first power conversion circuit and the second power conversion circuit, Each of the plurality of drive circuits is configured to adjust the delay amount of the drive signal supplied to the switching element being driven. The control device sets the delay amount for each of the plurality of drive circuits, When the control device sets the delay amount, In each of the multiple pairs of two different phases of the three phases in the first power conversion circuit and the second power conversion circuit, the switching element in each of the upper arm of the first phase of either the first power conversion circuit or the second power conversion circuit, the upper arm of the second phase of either the first power conversion circuit or the lower arm of the third phase of either the first power conversion circuit or the lower arm of the first phase of either the first power conversion circuit or the second power conversion circuit, the lower arm of the second phase of either the first power conversion circuit or the upper arm of the third phase of either the first power conversion circuit or the second power conversion circuit, The current difference between the energized first-phase switching element and the energized second-phase switching element is detected as a current imbalance. A power conversion device characterized by setting the delay amount in the drive circuit that drives the first phase switching element or the delay amount in the drive circuit that drives the second phase switching element in accordance with the detected current imbalance, so as to reduce the current imbalance.

2. In the power conversion device according to claim 1, A power conversion device characterized by turning off the switching elements in the first power conversion circuit and the second power conversion circuit, other than the switching elements of the first phase, the switching elements of the second phase, and the switching elements of the third phase.

3. In the power conversion device according to claim 1, The system includes a plurality of current sensors corresponding to the number of phases, for detecting the load current flowing through the load, The control device is a power conversion device characterized by detecting the current imbalance based on the detection values ​​of the current sensor that detects the load current of the first phase and the current sensor that detects the load current of the second phase.

4. In the power conversion device according to claim 1, A power conversion device characterized in that the load is a three-phase synchronous motor.

5. In the power conversion device according to claim 1, The control device is The delay amount in the drive circuit that drives the first phase switching element, or the delay amount in the drive circuit that drives the second phase switching element, is repeatedly set. A power conversion device characterized in that the setting of the delay amount is terminated when the current imbalance falls below a predetermined value.

6. In the power conversion device according to claim 1, The control device is characterized in that it sets a delay amount in the drive circuit of the switching element of the first phase and the second phase, whichever has a larger current, to delay the turn-on timing.

7. In the power conversion device according to claim 1, The control device is characterized in that it sets a delay amount in the drive circuit of the switching element of the first phase and the second phase, whichever has a smaller current, to advance the turn-on timing.

8. In a power conversion method that performs power conversion by connecting in parallel the output of a first power conversion unit equipped with a first power conversion circuit and the output of a second power conversion unit equipped with a second power conversion circuit, In each of the multiple pairs of two different phases of the three phases in the first power conversion circuit and the second power conversion circuit, the switching elements in each of the upper arm of the first phase of either the first power conversion circuit or the second power conversion circuit, the upper arm of the second phase of either the first power conversion circuit or the lower arm of the third phase of either the first power conversion circuit or the lower arm of the first phase of either the first power conversion circuit or the second power conversion circuit, the lower arm of the second phase of either the first power conversion circuit or the upper arm of the third phase of either the first power conversion circuit or the second power conversion circuit, The current difference between the energized first-phase switching element and the energized second-phase switching element is detected as a current imbalance. A power conversion method characterized by adjusting the switching timing of the first phase switching element or the second phase switching element in order to reduce the current imbalance in accordance with the detected current imbalance.

9. A boat cage and counterweight, Within the elevator shaft, the main rope suspends the elevator car and the counterweight, A hoisting machine that drives the main rope, The electric motor that drives the hoisting machine, A power converter that supplies power to the aforementioned electric motor, In an elevator equipped with, An elevator characterized in that the power conversion device is the power conversion device described in claim 1.

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