Electronic module

Abstract

The electronic module of the present invention comprises a substrate 10 having a power wiring section 14, a plurality of semiconductor elements 20a, 20b arranged side by side on the substrate 10 and having gate electrode sections 24 formed on their surfaces, a signal substrate 30 arranged on the substrate 10 and having an insulating substrate 32 and gate wiring sections 34 formed on the surface of the insulating substrate 32, and gate pin terminals 40a, 40b erected on the gate wiring section 34, wherein the wiring lengths from the gate pin terminals 40a, 40b to the gate electrode sections 24a, 24b of each semiconductor element 20a, 20b are equal. According to the electronic module of the present invention, inductance can be reduced, and switching timing can be synchronized even when semiconductor elements are connected in parallel.

Description

Technical Field

[0001] The present invention relates to an electronic module.

Background Art

[0002] Conventionally, an electronic module in which pin terminals stand on a substrate has been known (for example, see Patent Document 1).

[0003] [[ID=E16]]For example, as shown in FIGS. 9 and 10, the electronic module 900 described in Patent Document 1 includes a substrate 910, a semiconductor element 920, and a gate pin terminal 940. On the surface of the substrate 910, a power wiring portion 912 and a gate wiring portion 914 are formed. The semiconductor element 920 is disposed on the substrate 910, and a main electrode 922 and a gate electrode portion 924 are formed on the surface. The gate pin terminal 940 stands on the gate wiring portion 914.

[0004] A lead frame LF is disposed on the main electrode 922 of the semiconductor element 920, and the lead frame LF is connected to an internal connection terminal 966 that stands from the semiconductor element 920. A lead frame 963 is also disposed at an intermediate position of the gate pin terminal 940. The gate electrode portion 924 and the gate wiring portion 914 are connected via a wire 980.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in conventional electronic modules 900, the power wiring section 912 and the gate wiring section 914 are wired on a single substrate 910. To avoid interference from the current flowing through the power wiring section 912, the gate wiring section 914 must be wired to bypass the power wiring section 912. This results in a longer wiring length from the gate pin terminal 940 to the gate electrode section 924, making it difficult to reduce the inductance.

[0007] Incidentally, with the increasing currents of electronic devices in recent years, multiple semiconductor elements are connected in parallel to reduce the load on a single semiconductor element. In this case, it is necessary to switch each semiconductor element simultaneously, and it is desirable that the wiring length to the gate electrode portion of each semiconductor element be equal. However, in conventional electronic modules 900, as described above, it is necessary to wire the gate wiring portion 914 in a way that bypasses the power wiring portion 912. Therefore, when multiple semiconductor elements are connected in parallel, it is difficult to make the wiring length to the gate electrode portion 924 of the semiconductor element 920 equal, and it is difficult to synchronize the switching timing of the semiconductor elements 920. This problem is particularly pronounced when performing high-speed switching control.

[0008] Therefore, the present invention has been made to solve the above-mentioned problems, and aims to provide an electronic module that makes it easy to reduce inductance and can synchronize the switching timing even when multiple semiconductor elements are connected in parallel. [Means for solving the problem]

[0009] The electronic module of the present invention comprises a substrate having a power wiring section, a plurality of semiconductor elements arranged side by side on the substrate and having gate electrodes formed on their surfaces, a signal substrate disposed on the substrate and having an insulating substrate and gate wiring sections formed on the surface of the insulating substrate, and gate pin terminals erected on the gate wiring sections, wherein the wiring length from the gate pin terminals to the gate electrodes of each semiconductor element is equal. [Effects of the Invention]

[0010] According to the electronic module of the present invention, since it comprises a substrate having a power wiring section, an insulating substrate, and a signal substrate having a gate wiring section, the power wiring section and the gate wiring section can be formed on separate substrates. Therefore, it is not necessary to route the gate wiring section to bypass the power wiring section, and the wiring length from the gate pin terminal to the gate electrode section does not tend to become long. As a result, it becomes easier to lower the inductance of the gate wiring section.

[0011] Furthermore, the electronic module of the present invention comprises a substrate having a power wiring section and a signal substrate having a gate wiring section. Since the wiring length from the gate pin terminal to the gate electrode section of each semiconductor element is equal, the switching timing of each semiconductor element can be synchronized even when multiple semiconductor elements are connected in parallel.

[0012] Incidentally, when forming power wiring and gate wiring on the same substrate, as in conventional electronic modules, a metal film is generally formed uniformly on an insulating substrate, and then the power wiring and gate wiring are formed together by etching or other methods. However, because the relatively thick power wiring and the relatively thin gate wiring are formed simultaneously from the same metal film, there is a risk that the power wiring may not be completely etched if etching is done to match the gate wiring, or that the gate wiring may be etched too much if etching is done to match the power wiring, potentially causing variations in the shape and dimensions of the gate wiring ends, making it difficult to form the gate wiring with high precision. Even when attempting to place small components, such as small chip resistors, on such gate wiring, it is difficult to place them with high positional accuracy. In contrast, the electronic module of the present invention comprises a substrate having a power wiring section and a signal substrate having a gate wiring section, so the power wiring section and the gate wiring section are formed separately. Therefore, the gate wiring section can be formed with high precision without being affected by the formation of the power wiring section, and even when small chip resistors or the like are placed on the gate wiring section, they can be positioned with high positional accuracy. [Brief explanation of the drawing]

[0013] [Figure 1] This is a plan view showing the electronic module 1 according to Embodiment 1. [Figure 2] This is a cross-sectional view of the electronic module 1 according to Embodiment 1. [Figure 3] This is a perspective view showing the electronic module 1 according to Embodiment 2. [Figure 4] This figure illustrates the outer lead frame 70 in Embodiment 2. [Figure 5] This is a cross-sectional view illustrating the electronic module 2 according to Embodiment 2. [Figure 6] This figure illustrates the inner lead frame 60 in Embodiment 2. [Figure 7] This figure illustrates the semiconductor elements 20a to 20h, signal substrates 30a to 30d, gate pin terminals 40a to 40h, and sense pin terminals 50a to 50d in Embodiment 2. [Figure 8] This figure illustrates the gate wiring sections 34a to 34h and sense wiring sections 36a to 36d in Embodiment 2. [Figure 9] This is a plan view illustrating a conventional electronic module 900. Reference numeral 950 indicates a pin terminal. [Figure 10] This is a schematic, enlarged cross-sectional view of a key part illustrating a conventional electronic module 900. [Modes for carrying out the invention]

[0014] Hereinafter, the electronic module of the present invention will be described based on the embodiments shown in the figures. Note that the embodiments described below do not limit the invention according to the claims. Also, not all of the elements and their combinations described in the embodiments are essential for the solution means of the present invention.

[0015] [Embodiment 1] 1. Configuration of the electronic module 1 according to Embodiment 1 As shown in FIGS. 1 and 2, the electronic module 1 according to the embodiment includes a substrate 10, semiconductor elements 20a and 20b, a signal substrate 30, gate pin terminals 40a and 40b, a sense pin terminal 50, a lead frame LF, and connection members 80 and 81, and is sealed with a mold resin (not shown). On the surface of the substrate 10, as shown in FIG. 1, two semiconductor elements , 20a and 20b are arranged side by side, and a rectangular signal substrate 30 is arranged parallel to the direction in which the semiconductor elements 20a and 20b are arranged side by side. [[ID=⑨]] [[ID=⑩]]

[0016] [[ID=⑪]] [[ID=⑫]]In the electronic module 1, the two semiconductor elements 20a and 20b are connected in parallel. Specifically, the two semiconductor elements 20a and 20b are arranged on the common power wiring portion 14 of the substrate 10, and each drain electrode (not shown) is connected to the common power wiring portion 14 and has the same potential. Also, the source electrode portions 22a and 22b of the two semiconductor elements 20a and 20b are connected by a common lead frame LF via internal connection terminals 66, and these also have the same potential part of the lead frame LF extends outside the mold resin (not shown) and constitutes an external terminal.

[0017] The substrate 10 is a DCB substrate (Direct Copper Bonding substrate) having an insulating substrate 12 (ceramic substrate), a power wiring portion 14 formed on one surface (upper surface) of the insulating substrate 12, and a heat-radiating metal plate 16 formed on the other surface (lower surface) of the insulating substrate 12. In the first embodiment, a DCB substrate is used as the substrate 10, but an appropriate substrate such as a printed substrate may be used. The power wiring portion 14 is made of a metal film. The power wiring portion 14 has two die pads, on which semiconductor elements 20a and 20b are respectively mounted.

[0018] The semiconductor elements 20a and 20b are vertical MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) on whose surfaces (surfaces opposite to the substrate 10 side), source electrode portions 22a and 22b (main electrodes), gate electrode portions 24a and 24b, and sense electrode portions 26a and 26b are formed, and on whose back surfaces (surfaces on the substrate 10 side), drain electrodes are formed. Note that the semiconductor elements 20a and 20b may be the same semiconductor elements or different semiconductor elements. Further, as the semiconductor elements 20a and 20b, not limited to MOSFETs, appropriate semiconductor elements having gate electrodes such as IGBTs, thyristors, and triacs can be used.

[0019] The source electrode portions 22a and 22b occupy most of the surfaces of the semiconductor elements 20a and 20b and are divided into two in a plan view as shown in FIG. 1. The gate electrode portions 24a and 24b are formed on the outer edge on one side (the lower side in FIG. 1) of the rectangle of the semiconductor elements 20a and 20b and are arranged near the center of the outer edge. The sense electrode portions 26a and 26b are also formed on the outer edge on one side (the lower side in FIG. 1) of the rectangle of the semiconductor elements 20a and 20b, and two are arranged at the corners so as to sandwich the gate electrode portions 24a and 24b. The drain electrode is formed on the entire back surface and is connected to the power wiring 14 via a conductive bonding material. The sense electrode portions 26a and 26b are connected to the source electrode portions 22a and 22b and are for detecting the current flowing through the source electrode portions 22a and 22b.

[0020] The two semiconductor elements 20a and 20b are arranged side by side such that the sides on which the gate electrode portions 24a and 24b and the sense electrode portions 26a and 26b are formed (one side of the rectangle) face the signal substrate 30.

[0021] The signal board 30 is a substantially rectangular substrate having an insulating substrate 32, gate wiring sections 34a, 34b and sense wiring section 36 formed on one side (top surface) of the insulating substrate 32, and a back electrode 38 formed on the other side (bottom surface) of the insulating substrate 32. For the signal board 30, for example, a glass epoxy substrate can be used, but any suitable substrate that can insulate one side from the other can be used. The signal board 30 is arranged parallel to the semiconductor elements 20a, 20b such that the direction in which the semiconductor elements 20a, 20b are aligned is the longitudinal direction. The signal board 30 is placed on the power wiring section 14, and the back electrode 38 and the power wiring section 14 are joined via a conductive bonding material (for example, solder).

[0022] The gate wiring sections 34a and 34b are positioned opposite each other, with the sense wiring section 36 in between. The gate wiring sections 34a and 34b extend to the vicinity of the gate electrode sections 24a and 24b of the semiconductor elements 20a and 20b, and are connected to the gate electrode sections 24a and 24b via the connecting member 80. In addition, gate pin terminals 40a and 40b are erected at predetermined positions on the gate wiring sections 34a and 34b, respectively.

[0023] The wiring length WLG1 from the gate pin terminal 40a to the gate electrode portion 24a of the semiconductor element 20a via the gate wiring section 34a and the connecting member 80 is the same length as the wiring length WLG2 from the gate pin terminal 40b to the gate electrode portion 24b of the semiconductor element 20b via the gate wiring section 34b and the connecting member 80. Furthermore, the gate wiring sections 34a and 34b are arranged symmetrically with respect to a straight line passing through the sense pin terminal 50 (a straight line passing through the center of the signal board 30).

[0024] The sense wiring section 36 extends from near the center of the signal board 30 to the vicinity of the sense electrode sections 26a and 26b of the semiconductor elements 20a and 20b, and is connected to one of the sense electrode sections 26a and 26b (the central sense electrode section) via a connecting member 81. A sense pin terminal 50 is erected near the center of the sense wiring section 36.

[0025] The wiring length WLS1 from the sense pin terminal 50 to the sense electrode portion 26a of the semiconductor element 20a via the sense wiring section 36 and connecting member 81 is the same length as the wiring length WLS2 from the sense pin terminal 50 to the sense electrode portion 26b of the semiconductor element 20b via the sense wiring section 36 and connecting member 81. Furthermore, the sense wiring section 36 is arranged symmetrically with respect to a straight line passing through the sense pin terminal 50. Note that the sense wiring section 36 has a separated portion between the sense pin terminal 50 and each connecting member 81, and this portion is connected via a resistor R.

[0026] The gate pin terminals 40a, 40b and the sense pin terminal 50 are columnar members made of a conductive material (e.g., a metal material), with their tips exposed to the outside of the molded resin, thus forming the terminals. The gate pin terminals 40a, 40b (and the sense pin terminal 50) have a main body portion 41 (51) and a ring-shaped flange portion 42 (52) provided at an intermediate position in the height direction. Below the flange portion 42 (52) is a pin terminal fixing portion 63 made of a lead frame, and the gate pin terminals 40a, 40b (and the sense pin terminal 50) are joined to the pin terminal fixing portion 63 via the flange portion 42 (52).

[0027] The gate pin terminals 40a and 40b are erected on the two gate wiring sections 34a and 34b, respectively. The sense pin terminal 50 is erected on the sense wiring section 36.

[0028] The lead frame LF is a flat conductive member placed on the semiconductor elements 20a and 20b. The lead frame LF is connected to the source electrode portions 22a and 22b of the semiconductor elements 20a and 20b via internal connection terminals 66. The ends of the lead frame LF extend to the outside of the molded resin, and these ends constitute external terminals.

[0029] The connecting members 80 and 81 are formed by cutting and bending a plate-shaped conductive member.

[0030] 2. Effects of the electronic module 1 according to Embodiment 1 According to the electronic module 1 of Embodiment 1, since it comprises a substrate 10 having a power wiring section 14 and a signal substrate 30 having gate wiring sections 34a and 34b, the power wiring section 14 and the gate wiring sections 34a and 34b can be formed on separate substrates. Therefore, it is not necessary to route the gate wiring sections to bypass the power wiring section 14, and the wiring length is less likely to become long. As a result, it becomes easier to lower the inductance of the gate wiring sections 34a and 34b.

[0031] Furthermore, according to the electronic module 1 of Embodiment 1, the module comprises a substrate 10 having a power wiring section 14 and a signal substrate 30 having gate wiring sections 34a and 34b. Since the wiring lengths WLG1 and WLG2 from the gate pin terminals 40a and 40b to the gate electrode sections 24a and 24b of each semiconductor element 20a and 20b are equal, the switching timing of each semiconductor element 20a and 20b can be synchronized even when the semiconductor elements 20a and 20b are connected in parallel.

[0032] Furthermore, according to the first embodiment of the electronic module 1, since it comprises a substrate 10 having a power wiring section 14 and a signal substrate 30 having gate wiring sections 34a and 34b, the power wiring section 14 and the gate wiring sections 34a and 34b can be formed separately. Therefore, the gate wiring sections 34a and 34b can be formed with high precision, and even when small chip resistors or the like are placed on the gate wiring sections 34a and 34b, they can be positioned with high positional accuracy.

[0033] Furthermore, according to the electronic module 1 of Embodiment 1, the wiring lengths WLS1 and WLS2 from the sense pin terminal 50 to the sense electrode portions 26a and 26b of each semiconductor element 20a and 20b are equal. Therefore, it is not necessary to route the sense wiring to bypass the power wiring, and the wiring length is less likely to become long. As a result, it becomes easier to lower the inductance of the sense wiring portion 36.

[0034] Furthermore, according to the electronic module 1 of Embodiment 1, since the multiple semiconductor elements 20a and 20b are connected in parallel with each other, the current flowing through each semiconductor element and the heat generated can be reduced, making it possible to create an electronic module that can use high currents and an electronic module with a relatively long lifespan due to the reduced burden on the semiconductor elements.

[0035] Furthermore, according to the electronic module 1 of Embodiment 1, since the signal board 30 is placed on the power wiring section 14, the contact area of ​​the signal board and wiring can be reduced, resulting in a miniaturized electronic module. In addition, since the signal board 30 has an insulating substrate 32, even if the power wiring section 14 and the signal board 30 overlap, the impact on the gate wiring sections 34a, 34b and the sense wiring section 36 can be reduced.

[0036] Furthermore, according to the electronic module 1 of Embodiment 1, the module includes an even number (2) pairs of semiconductor elements 20a, 20b, and the gate electrode portions 24a, 24b of the paired semiconductor elements 20a, 20b are positioned symmetrically with respect to a straight line passing through the sense pin terminal 50 (or a straight line passing through the center of the signal board). This makes it easier to make the wiring lengths from the gate pin terminals 40a, 40b to the gate electrode portions 24a, 24b of each semiconductor element 20a, 20b equal.

[0037] Furthermore, according to the electronic module 1 of Embodiment 1, the gate wiring section 34a from the gate pin terminal 40a to the gate electrode portion 24a of one semiconductor element 20a is arranged to be symmetric with respect to a straight line passing through the midpoint between the semiconductor elements 20a and 20b, and the gate wiring section 34b from the gate pin terminal 40b to the gate electrode portion 24b of the other semiconductor element 20b. From this viewpoint as well, it is easier to make the wiring lengths equal from the gate pin terminals 40a and 40b to the gate electrode portions 24a and 24b of each semiconductor element 20a and 20b.

[0038] Furthermore, according to the electronic module 1 of Embodiment 1, the sense wiring section 36 from the sense pin terminal 50 to the sense electrode portion 26a of one semiconductor element 20a is arranged to be symmetric with respect to a straight line passing through the midpoint between the semiconductor elements 20a and 20b, and the sense wiring section 36 from the sense pin terminal 50 to the sense electrode portion 26b of the other semiconductor element 20b. This makes it easier to make the wiring lengths equal from the sense pin terminal 50 to the sense electrode portions 26a and 26b of each semiconductor element 20a and 20b.

[0039] Furthermore, according to the electronic module 1 of Embodiment 1, the thickness of the gate wiring sections 34a and 34b and the thickness of the sense wiring section 36 are thinner than the thickness of the power wiring section 14. Therefore, the gate wiring sections 34a and 34b and the sense wiring section 36 can be formed with high precision, and when small chip resistors or the like are placed on the gate wiring sections 34a and 34b, they can be positioned with high positional accuracy.

[0040] [Embodiment 2] The electronic module 2 according to Embodiment 2 has basically the same configuration as the electronic module 1 according to Embodiment 1, but differs from the electronic module 1 according to Embodiment 1 in that it has multiple semiconductor element groups, each having an even number of semiconductor elements paired together.

[0041] As shown in Figure 3, the electronic module 2 according to Embodiment 2 is resin-sealed with molded resin 90, with terminals T1, T2, and T3 protruding from one side and terminal T4 protruding from the other side opposite to the first side. In addition, gate pin terminals 40a to 40h, sense pin terminals 50a to 50d, and other pin terminals 46 protrude from one main surface.

[0042] To simplify the explanation below, the direction from the side with external terminal T1 to the side with external terminal T3 (among the sides without external terminals T1 to T4) will be defined as the +X direction, the direction from the side with external terminal T4 to the side with external terminals T1 to T3 will be defined as the +Y direction, and the direction from the opposite main surface of one main surface to the main surface on which the pin terminals are located will be defined as the +Z direction.

[0043] As shown in Figures 4 to 8, the electronic module 2 according to Embodiment 2 comprises a substrate 10, eight semiconductor elements 20a to 20h, signal boards 30a to 30d, gate pin terminals 40a to 40h, sense pin terminals 50a to 50d, an inner lead frame 60, an outer lead frame 70, and connecting members 80 and 81. In the electronic module 2 according to Embodiment 2, semiconductor elements 20a to 20d are connected in parallel, and semiconductor elements 20e to 20h are also connected in parallel, forming a half-bridge circuit in which semiconductor elements 20a to 20d and semiconductor elements 20e to 20h are connected in series.

[0044] As shown in Figure 7, two power wiring sections 14a and 14b are spaced apart on the surface side of the substrate 10. Semiconductor elements 20a to 20d are arranged along the -X direction on the power wiring section 14a, and rectangular signal boards 30a and 30b are arranged along the X direction on the external terminal T4 side (-Y direction side) of the semiconductor elements 20a to 20d. Semiconductor elements 20e to 20h are arranged along the -X direction on the power wiring section 14b, and rectangular signal boards 30c and 30d are arranged along the X direction on the external terminal T2 side (+Y direction side) of the semiconductor elements 20e to 20h.

[0045] As shown in Figures 7 and 8, the signal boards 30a to 30d have a rectangular shape and are arranged so that their longitudinal direction is aligned with the X direction. Signal boards 30a and 30b are arranged alongside semiconductor elements 20a to 20d, and signal boards 30c and 30d are arranged alongside semiconductor elements 20e to 20h. Signal boards 30a and 30b are placed on the power wiring section 14a, and signal boards 30c and 30d are placed on the power wiring section 14b. Gate wiring sections 34a to 34h and sense wiring sections 36a to 36d are formed on the signal boards 30a to 30d. The gate wiring sections 34a to 34h and sense wiring sections 36a to 36d are formed to be symmetrical with respect to a line passing through the center of the rectangle of the signal boards 30a to 30d.

[0046] As shown in Figures 7 and 8, the sense wiring sections 36a to 36d extend from near the center of each signal board 30a to 30d to the vicinity of the sense electrode sections 26a to 26d of each semiconductor element, and are connected to the sense electrode sections 26a and 26b via a connecting member 81. Sense pin terminals 50a to 50d are erected near the center of each of the sense wiring sections 36a to 36d. The sense wiring sections 36a to 36d are separated on the terminal side and the semiconductor element side, and are connected via a resistor R.

[0047] The gate wiring sections 34a to 34h are arranged in pairs on each signal board, positioned opposite the sense wiring sections 36a to 36d. The gate wiring sections 34a to 34h extend to the vicinity of the gate electrode sections 24a to 24h of the semiconductor elements 20a to 20d and are connected to the gate electrode sections 24a to 24h via a connecting member 80. In addition, gate pin terminals 40a to 40h are erected at predetermined positions on the gate wiring sections 34a to 34h.

[0048] In the electronic module 2 according to Embodiment 2, one semiconductor element group is formed by two semiconductor elements, one signal board, two gate pin terminals, one sense pin terminal, and connecting members 80 and 81. In Embodiment 2, as shown in Figure 7, four semiconductor element groups are configured: semiconductor element group G1 related to semiconductor elements 20a and 20b, semiconductor element group G2 related to semiconductor elements 20c and 20d, semiconductor element group G3 related to semiconductor elements 20e and 20f, and semiconductor element group G4 related to semiconductor elements 20g and 20h.

[0049] Groups G1 to G4 all have the same shape and are configured to be symmetrical with respect to a line passing through the sense pin terminals 50a to 50d. Therefore, the wiring length from each gate pin terminal 40a to 40h to the gate electrode portion 24a to 24h of each semiconductor element 20a to 20h is equal. Also, the wiring length from each sense pin terminal 50a to 50d to the sense electrode portion 26a to 26h of each semiconductor element 20a to 20h is equal.

[0050] Groups G1 to G4 are positioned symmetrically with respect to a line passing through the center of the substrate 10. Specifically, Group G1 and Group G2, and Group G3 and Group G4 are positioned symmetrically with respect to a line passing through the center of the substrate 10 and extending vertically in Figure 7; Group G1 and Group G3, and Group G2 and Group G4 are positioned symmetrically with respect to a line passing through the center of the substrate 10 and extending horizontally in Figure 7; and Group G1 and Group G4, and Group G2 and Group G3 are positioned symmetrically with respect to the center of the substrate 10.

[0051] As shown in Figures 5 and 6, the source electrodes 22a to 22d of semiconductor elements 20a to 20d are connected by a common long connector 62, which will be described later. In addition, the source electrodes 22e to 22h of semiconductor elements 20e to 20h are connected by a common inner lead section 61, which will be described later.

[0052] As shown in Figures 5 and 6, an inner lead frame 60 is positioned above the substrate 10. The inner lead frame 60 has an inner lead portion 61, a long connector 62, and a pin terminal fixing portion 63, and the inner lead portion 61, the long connector 62, and the pin terminal fixing portion 63 are formed at the same height.

[0053] Each component of the inner lead frame 60 is provided with a lead portion L extending in either the +X or -X direction. During the manufacturing process, the lead portion L constituted a suspension lead that connected to a frame portion (not shown). The tips of the lead portions L are all located inside the molded resin 90.

[0054] The inner lead portion 61 is connected to the source electrode portions 22e to 22h of the semiconductor elements 20e to 20h. The inner lead portion 61 extends toward the power wiring portion 14a and is connected to the power wiring portion 14a via the internal connection terminal 64.

[0055] The elongated connector 62 is connected to the source electrode portions 22a to 22d of the semiconductor elements 20a to 20d. The elongated connector 62 extends along the X direction when viewed in plan, and although not shown in the figure, it has a shape that protrudes in the -Z direction at a position where it overlaps with the semiconductor elements 20a to 20d.

[0056] The first outer lead portion 71 and the long connector 62, as described later, are connected by an internal connection terminal 72. The internal connection terminal 72 is located in a position that does not overlap with the positions of the semiconductor elements 20a to 20d when viewed in plan view. Specifically, it is located midway between the electrodes of adjacent semiconductor elements 20a to 20d when viewed in plan view.

[0057] The pin terminal fixing section 63 is positioned at an intermediate position between each gate pin terminal 40a to 40h and each sense pin terminal 50a to 50d. Each pin terminal fixing section 63 has a through hole through which the pin terminal passes.

[0058] As shown in Figures 4 and 5, an outer lead frame 70 is positioned above the substrate 10 and the inner lead frame 60. The outer lead frame 70 has a first outer lead portion 71, a second outer lead portion 73 (external terminal T2), and a third outer lead portion 74 (external terminal T4), each formed at the same height. The first outer lead portion 71 of the outer lead frame 70 overlaps with the inner lead frame 60 (specifically, the inner lead portion 61) in a planar view, and as shown in Figure 5, current flows in opposite directions (in the -Y direction for the inner lead portion 61 and in the +Y direction for the first outer lead portion 71) at relatively close positions.

[0059] The first outer lead portion 71 is a flat, roughly U-shaped member, with an elongated hole formed in the region where the internal connection terminal 64 is formed (the region where the inner lead portion 61 and the power wiring portion 14a are connected). The first outer lead portion 71 extends in the +Y direction on both the +X and -X sides, and extends to the outside of the molded resin 90. The portions extending to the outside of the molded resin 90 constitute the external terminals T1 and T3, respectively.

[0060] The second outer lead section 73 is connected to the power wiring section 14a via an internal connection terminal 75, extends in the +Y direction, and extends to the outside of the molded resin 90. The portion extending to the outside of the molded resin 90 constitutes the external terminal T2.

[0061] The third outer lead section 74 is connected to the power wiring section 14b via an internal connection terminal 76, extends in the -Y direction, and extends to the outside of the molded resin 90. The portion extending to the outside of the molded resin 90 constitutes the external terminal T4.

[0062] Thus, the electronic module 2 according to Embodiment 2 differs from the electronic module 1 according to Embodiment 1 in that it has multiple semiconductor element groups, each having an even number of semiconductor elements paired together. However, similar to the electronic module 1 according to Embodiment 1, it comprises a substrate 10 having power wiring sections 14a and 14b, and signal substrates 30a to 30d having gate wiring sections 34a to 34h. Therefore, the power wiring sections 14a and 14b and the gate wiring sections 34a to 34h can be formed on separate substrates. Consequently, it is not necessary to route the gate wiring sections 34a to 34h around the power wiring sections 14a and 14b, making it easier to reduce the wiring length. As a result, it becomes easier to lower the inductance of the gate wiring sections 34a to 34h.

[0063] Furthermore, according to the electronic module 2 of Embodiment 2, the module comprises a substrate 10 having power wiring sections 14a and 14b, and a signal substrate 30 having gate wiring sections 34a to 34h. Since the wiring lengths from the gate pin terminals 40a to 40h to the gate electrode sections 24a to 24h of each semiconductor element 20a to 20h are equal, the switching timing of each semiconductor element 20a to 20d and 20e to 20h can be synchronized even when semiconductor elements 20a to 20d and 20e to 20h are connected in parallel.

[0064] Furthermore, according to the electronic module 2 of Embodiment 2, there are semiconductor element groups G1 to G4, each having two semiconductor elements paired together, and the semiconductor element groups G1 to G4 are arranged symmetrically with respect to a straight line passing through the center of the substrate 10. As a result, the bias in inductance is small, and the switching timing of each semiconductor element can be synchronized. In addition, because each component is arranged symmetrically, there is less bias in the heat dissipation from the semiconductor elements, etc., and it is possible to prevent localized high temperatures.

[0065] Furthermore, the electronic module 2 according to Embodiment 2 has the same configuration as the electronic module 1 according to Embodiment 1, except that it has multiple semiconductor element groups, each having an even number of semiconductor elements paired together. Therefore, it has the corresponding effects of the electronic module 1 according to Embodiment 1.

[0066] Although the present invention has been described above based on the embodiments described above, the present invention is not limited to the embodiments described above. It can be implemented in various forms without departing from the spirit of the invention, and for example, the following modifications are also possible.

[0067] (1) The positions, connections, number, circuit configuration, terminals, etc. described in each of the above embodiments are illustrative examples and can be changed within the scope that does not impair the effects of the present invention.

[0068] (2) In each of the above embodiments, one sense pin terminal and two gate pin terminals are provided on one signal board, but the present invention is not limited thereto. There may be two sense pin terminals or one gate pin terminal.

[0069] (3) In each of the above embodiments, two semiconductor elements are connected to one signal board, but the present invention is not limited thereto. Three or more semiconductor elements may be connected to one signal board. In order to make the wiring length between the gate pin terminal and the gate electrode portion of each semiconductor element equal, it is preferable to have multiple semiconductor elements.

[0070] (4) In the above embodiment 2, two of the four parallel-connected semiconductor elements were connected to one signal board, but the present invention is not limited thereto. All four parallel-connected semiconductor elements may be connected to one signal board. [Explanation of symbols]

[0071] 1,2…Electronic module, 10…Substrate, 14,14a,14b…Power wiring section, 20,20a,20b,20c,20d,20e,20f,20g,20h…Semiconductor element, 24a~24h…Gate electrode section, 26a~26h…Sense electrode section, 30,30a,30b,30c,30d…Signal board, 32…Insulating substrate, 34a~34f…Gate wiring section, 36,36a~36d…Sense wiring section, 40a~40h…Gate pin terminals, 50,50a~50d…Sense pin terminals, G1~G4…Semiconductor element group

Claims

1. A circuit board having a power wiring section, A first semiconductor element, viewed in plan view, is arranged in a plurality on the substrate, with a gate electrode portion provided in the center of one edge of each surface, and a sense electrode portion arranged alongside the gate electrode portion on one edge of the surface. Viewed in plan, a plurality of second semiconductor elements are arranged side by side on the substrate at a distance from the first semiconductor element, and each second semiconductor element has a gate electrode portion provided in the center of one edge of its surface, and a sense electrode portion arranged alongside the gate electrode portion on one edge of its surface. A signal substrate having an insulating substrate, a gate wiring portion formed on the surface of the insulating substrate, and a sense wiring portion formed on the surface of the insulating substrate, respectively, which are arranged on one side of the plurality of first semiconductor elements on the substrate and on one side of the plurality of second semiconductor elements on the substrate, A sense pin terminal erected on the aforementioned sense wiring section, It comprises a first gate pin terminal and a second gate pin terminal erected at symmetrical positions on the gate wiring section, with respect to the sense pin terminal, The gate electrodes of the first and second semiconductor elements are each positioned symmetrically with respect to a line passing through the center of the signal substrate. If we define the direction of the axis in which the first semiconductor element or the second semiconductor element is arranged side by side as the +X direction, and the opposite direction as the -X direction, The aforementioned sense wiring section is A first land is provided in the center of the signal board and is connected to the sense pin terminal, A first protrusion extending in the +X direction from the first land along the edge of the signal substrate opposite to the side of the first semiconductor element or the second semiconductor element, A second protrusion extends from the first land toward the -X direction along the edge of the signal substrate opposite to the side of the first semiconductor element or the second semiconductor element, A first wiring portion extends along the edge of the signal substrate on the side of the first semiconductor element or the second semiconductor element, with one end located at a position corresponding to the first protruding portion and the other end located at a position corresponding to the sense electrode portion of the first semiconductor element or the second semiconductor element, It is composed of a second wiring portion that is separated from the first wiring portion, extends along the edge of the signal substrate on the side of the first semiconductor element or the second semiconductor element, with one end located at a position corresponding to the second protrusion and the other end located at a position corresponding to the sense electrode portion of the first semiconductor element or the second semiconductor element, The first protruding portion and the first wiring portion, and the second protruding portion and the second wiring portion are connected via resistors. The other end of the first wiring section and the sense electrode portion of the first semiconductor element or the second semiconductor element, and the other end of the second wiring section and the sense electrode portion of the first semiconductor element or the second semiconductor element are connected by a connecting member. The wiring length from the sense pin terminal to the sense wiring portion of one of the adjacent first semiconductor elements or second semiconductor elements is equal to the wiring length from the sense pin terminal to the sense wiring portion of the other adjacent first semiconductor element or second semiconductor element. The sense wiring section from the sense pin terminal to the sense electrode portion of one of the adjacent first semiconductor elements or second semiconductor elements, and the sense wiring section from the sense pin terminal to the sense electrode portion of the other adjacent first semiconductor element or second semiconductor element, are arranged symmetrically with respect to a line passing through the midpoint between adjacent first semiconductor elements or the midpoint between adjacent second semiconductor elements. The gate wiring section is composed of a first gate wiring section and a second gate wiring section. The first gate wiring portion, viewed in plan, has a second land connected to the first gate pin terminal, extends from the second land along the +X-direction edge of the signal terminal to a position facing the gate electrode portion of the first or second semiconductor element, and is connected to the gate electrode portion via a connecting member. The second gate wiring section, viewed in plan, has a third land connected to the second gate pin terminal, extends from the third land along the -X-direction edge of the signal terminal to a position facing the gate electrode portion of the first or second semiconductor element, and is connected to the gate electrode portion via a connecting member. The wiring length from the first gate pin terminal to the first gate electrode portion of one of the adjacent first or second semiconductor elements is equal to the wiring length from the second gate pin terminal to the second gate electrode portion of the other adjacent first or second semiconductor element. The electronic module is characterized in that the first gate wiring section and the second gate wiring section are arranged symmetrically with respect to a line passing through the midpoint between adjacent first semiconductor elements or the midpoint between adjacent second semiconductor elements.

2. The electronic module according to claim 1, characterized in that the plurality of semiconductor elements are connected in parallel with one another.

3. The electronic module according to claim 1 or 2, characterized in that the signal board is arranged on the power wiring section.

4. The plurality of semiconductor elements include a plurality of semiconductor element groups, each having an even number of semiconductor elements paired together. The electronic module according to claim 1 or 2, characterized in that the plurality of semiconductor element groups are arranged in positions symmetrical with respect to a line passing through the center of the substrate.

5. The electronic module according to claim 1, characterized in that the thickness of the gate wiring section and the thickness of the sense wiring section are thinner than the thickness of the power wiring section.

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