Vertical FET replacement gate formation with variable fin pitch

Abstract

The semiconductor structure includes a first set of fins and a second set of fins, a dielectric pillar disposed between the first set of fins and the second set of fins, a lower source / drain (S / D) region directly contacting a lower surface of the first and second sets of fins, and an upper S / D region directly contacting a top surface of the first and second sets of fins. A high-k metal gate (HKMG) is disposed between the fins of the first set of fins and between the fins of the second set of fins. The HKMG directly contacts the sidewalls of the dielectric pillar. A width of the HKMG between the first set of fins is equal to a width of the HKMG between the second set of fins.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more particularly to forming a vertical field effect transistor (VFET) replacement metal gate (RMG) with variable fin pitch and self-aligned isolation.

Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric layers, conductive layers, and semiconductive layers of materials on a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon. The semiconductor industry has experienced rapid growth due to improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). Most of this improvement in integration density has resulted from shrinking semiconductor processing nodes. With the increasing demand for miniaturization, higher speed, larger bandwidth, lower power consumption, and lower latency, chip layout has become increasingly complex and difficult to achieve in the production of semiconductor dies.

Summary of the Invention

[0003] According to an embodiment, a semiconductor structure is provided. The semiconductor structure includes a first set of fins and a second set of fins, a dielectric pillar disposed between the first set of fins and the second set of fins, a lower source / drain (S / D) region in direct contact with the lower surfaces of the first and second sets of fins, and an upper S / D region in direct contact with the upper surfaces of the first and second sets of fins.

[0004] Another embodiment provides a method for forming a semiconductor device. This method includes forming a first set of fins and a second set of fins; forming sacrificial material adjacent to the first and second sets of fins; separating the first set of fins from the second set of fins with dielectric pillars to create self-aligned isolation; recessing the sacrificial material to define a concave sacrificial gate pillar; successively forming an upper spacer, an upper source / drain (S / D) region, and an epitaxial cap; forming a trench opening to expose the concave sacrificial material; removing the concave sacrificial material to define the opening; and forming a high-k metal gate (HKMG) within the opening.

[0005] In yet another embodiment, a semiconductor structure is provided. The semiconductor structure includes a set of first fins defining a plurality of first fins having a first pitch between them, a set of second fins defining a plurality of second fins having a second pitch between them, a dielectric pillar disposed between the set of first fins and the set of second fins, and a high-k metal gate (HKMG) disposed between the set of first fins and between the set of second fins. A third pitch is defined between a first fin of a plurality of first fins adjacent to the dielectric pillar and a second fin of a plurality of second fins adjacent to the dielectric pillar.

[0006] It should be noted that exemplary embodiments are described with reference to different subject matter. In particular, some embodiments are described with reference to method-type claims, while others are described with reference to apparatus-type claims. However, those skilled in the art will infer from the above and below descriptions that, unless otherwise stated, any combination of features belonging to one type of subject matter, as well as any combination of features relating to different subject matter, in particular, any combination of features of method-type claims and features of apparatus-type claims, are also described herein.

[0007] These and other features and advantages will become apparent from the following detailed description of the illustrative embodiments, which should be read in conjunction with the accompanying drawings.

[0008] The present invention provides further details in the following description of preferred embodiments with reference to the following figures. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention, which includes a plurality of fins formed adjacent to a sacrificial liner on a semiconductor substrate. [Figure 2] This is a cross-sectional view of the semiconductor structure shown in Figure 1, in which a conformal dielectric liner is deposited according to an embodiment of the present invention. [Figure 3] Figure 2 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention, in which a conformal dielectric liner is etched back to form a conformal dielectric pillar. [Figure 4] This is a cross-sectional view of the semiconductor structure shown in Figure 3, on which interlayer dielectrics (ILDs) are deposited, according to an embodiment of the present invention. [Figure 5] This is a cross-sectional view of the semiconductor structure shown in Figure 4, in which the hard mask has been removed according to an embodiment of the present invention. [Figure 6] Figure 5 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention, in which the sacrificial liner is recessed to expose the upper portions of several fins. [Figure 7] Figure 6 is a cross-sectional view of a semiconductor structure in which an upper spacer, an upper source / drain region, and an upper epitaxial cap are deposited according to an embodiment of the present invention. [Figure 8] This is a cross-sectional view of the semiconductor structure shown in Figure 7, in which an upper replacement metal gate (RMG) trench is opened according to an embodiment of the present invention. [Figure 9] Figure 8 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention, in which a sacrificial gate is removed to create an opening between multiple fins. [Figure 10]This is a cross-sectional view of the semiconductor structure shown in Figure 9, in which a substitution gate (RMG) is generated (formation of a high-k metal gate (HKMG)) according to an embodiment of the present invention. [Figure 11] This is a cross-sectional view of the semiconductor structure shown in Figure 10, in which metal recess processing is performed according to an embodiment of the present invention. [Figure 12] This is a cross-sectional view of the semiconductor structure shown in Figure 11, in which a contact point is formed, according to an embodiment of the present invention. [Modes for carrying out the invention]

[0010] Throughout the drawing, the same or similar reference numbers represent the same or similar elements.

[0011] Embodiments of the present invention provide a method and device for forming a vertical field-effect transistor (VFET) with variable fin pitch such that self-aligned isolation can be formed in wider fin-to-fin space between different devices. Thus, the exemplary embodiment focuses on the formation of self-aligned isolation for the VFET. The spacing between devices is increased to ensure work function metal (WFM) and isolation without affecting density. As a result, all fins see the same WFM stack.

[0012] Vertical FET devices employ doped source and drain regions, where the doped source / drain regions for the vertical FET may be formed on or below vertical semiconductor fins. In addition, the vertical source / drain (S / D) contacts of the vertical FET device may be arranged adjacent to the vertical semiconductor fins as elongated bar contacts. The vertical S / D contacts may be formed to contact the upper surface of the underlying S / D region, and may be positioned at a sufficient distance from the vertical semiconductor fins to prevent electrical short circuits with the vertical metal gate structure formed on the vertical semiconductor fins. What this effectively means is that the current path through the doped S / D region between the vertical contact / S / D region interface and the S / D region / channel coupling interface can be constructed entirely of doped semiconductor material. This current path through the doped S / D region, if relatively long, can result in increased series resistance of the S / D, which reduces the total drive current of the vertical FET device. Therefore, contact resistance is a factor as transistor device scaling continues beyond the 5 nanometer (nm) technology node. Additionally, the current scheme for VFETs involves a high-k / metal gate with an upper S / D thermal budget, hence, T inv Furthermore, it is not ideal because it carries the risk of not meeting the thickness scaling requirements for the threshold voltage (Vt).

[0013] Embodiments of the present invention further reduce contact resistance and allow for closer positioning of fins between devices, T inv To satisfy the Vt requirement, the present invention provides methods and devices using techniques for manufacturing or constructing VFETs with variable fin pitch such that self-aligned isolation can be formed in wider fin-to-fin spaces between different devices. Closer fin positioning between devices is made possible by forming variable fin pitch VFETs by a robust substitution metal gate (RMG) process with self-aligned isolation (e.g., conformal dielectric pillars).

[0014] Examples of semiconductor materials that can be used to form such a structure include silicon (Si), germanium (Ge), silicon-germanium alloy (SiGe), carbon-doped silicon (Si:C), carbon-doped silicon-germanium carbide (SiGe:C), III-V compound semiconductors, or II-VI compound semiconductors or combinations thereof. III-V compound semiconductors are materials that contain at least one element from Group III of the periodic table and at least one element from Group V of the periodic table. II-VI compound semiconductors are materials that contain at least one element from Group II of the periodic table and at least one element from Group VI of the periodic table.

[0015] Although the present invention is described with respect to a given exemplary architecture, it should be understood that other architectures, structures, substrate materials, as well as process features and steps / blocks can be varied within the scope of the present invention. Note that specific features are not shown in all figures for the purpose of clarity. This is not intended to be construed as a limitation of any particular embodiment, or illustration, or the scope of the claims.

[0016] FIG. 1 is a cross-sectional view of a semiconductor structure including a plurality of fins formed adjacent to a sacrificial liner on a semiconductor substrate, according to an embodiment of the present invention.

[0017] Within the structure 5, a plurality of fins 18 are formed on the substrate 10. A hard mask 20 is formed on the plurality of fins 18. The plurality of fins 18 can be in direct contact with source / drain (S / D) regions 12 (or lower S / D regions 12) formed within the substrate 10. A shallow trench isolation (STI) region 14 can separate the S / D regions 12 from each other. Additionally, lower spacers 16 can be formed adjacent to the bottom portions of the plurality of fins 18. The lower spacers 16 are in direct contact with the upper surfaces of the lower S / D regions 12 and the STI region 14.

[0018] The plurality of fins 18 are in direct contact with the sacrificial liner 22. In one example, the sacrificial liner 22 can be, for example, a thin layer of silicon dioxide (SiO2) followed by conformal amorphous silicon-germanium (a-SiGe) (two-layer deposition).

[0019] The plurality of fins 18 can include a first set of fins 18A and a second set of fins 18B. As shown in the top view, the first set of fins 18A can be referred to as the first device, and the second set of fins 18B can be referred to as the second device.

[0020] The first set of fins 18A is separated from the second set of fins 18B by the opening 24.

[0021] The structure 5’ illustrates the Y-Y’ perspective.

[0022] The top view illustrates the X-X' axis and the Y-Y' axis. The X-X' axis extends horizontally through all the fins, while the Y-Y' axis extends vertically through the fins. A first set of fins 18A and a second set of fins 18B are described. The first set of fins 18A is separated from the second set of fins 18B by conformal dielectric pillars 30 (Figure 3). The pitch between the first set of fins 18A (first pitch) may be, for example, 20 nm (or 15-30 nm). The pitch between the second set of fins 18B (second pitch) may be, for example, 20 nm (or 15-30 nm). In other exemplary embodiments, the first and second pitches may differ from each other. Furthermore, the pitch between the fins of the first set of fins 18A (adjacent to the conformal dielectric pillar 30) and the fins of the second set of fins 18B (adjacent to the conformal dielectric pillar 30) can be defined as a third pitch of, for example, 42 nm (or 32-60 nm). Thus, the first and second devices may have variable fin pitches. The conformal dielectric pillar 30 (or isolation structure) is therefore formed substantially in the middle of fins having wider pitches (for example, between the fins of the first set of fins and the fins of the second set of fins).

[0023] Furthermore, the first set of fins 18A has a common lower S / D region 12, and the second set of fins 18B also has a common lower S / D region 12. Therefore, there is a fused lower S / D region 12 for fins with smaller pitches. Fins with wider pitches do not share a common S / D region. For example, the rightmost fin of the first set of fins 18A does not share a common S / D region with the leftmost fin of the second set of fins 18B.

[0024] The substrate 10 may be crystalline, semicrystalline, microcrystalline, or amorphous. The substrate 10 may be essentially (e.g., excluding contaminants) a single element (e.g., silicon), primarily (e.g., with doping) a single atom (e.g., silicon (Si) or germanium (Ge)), or the substrate 10 may contain compounds (e.g., Al2O3, SiO2, GaAs, SiC, or SiGe). The substrate 10 may also have multiple material layers. In some embodiments, the substrate 10 contains semiconductor materials including, but not limited to, silicon (Si), silicon-germanium (SiGe), Si:C (carbon-doped silicon), carbon-doped silicon-germanium (SiGe:C), carbon-doped silicon-germanium (SiGe:C), Group III-V semiconductors (e.g., GaAs, AlGaAs, InAs, InP, etc.), Group II-V compound semiconductors (e.g., ZnSe, ZnTe, ZnCdSe, etc.), or other similar semiconductors. In addition, multiple layers of semiconductor material can be used as the semiconductor material of the substrate 10. In some embodiments, the substrate 10 includes both semiconductor material and dielectric material.

[0025] The lower spacer 16 may include any one or more of the following: a SiN film, a SiBN film, a SiCN film, or a SiBCN film, or a combination thereof.

[0026] Other non-limiting examples of materials for the lower spacer 16 include oxides (e.g., silicon oxide), dielectric nitrides (e.g., silicon nitride), dielectric oxynitrides, or any combination thereof. The lower spacer 16 is initially formed as a layer on the substrate 10 by a deposition process, e.g., chemical vapor deposition (CVD) or physical vapor deposition (PVD). In some embodiments, the lower spacer 16 is determined by directional deposition (e.g., high-density plasma chemical vapor deposition) followed by an etch-back process.

[0027] The plurality of fins 18 may be formed from semiconductor materials including, but not limited to, Si, strained Si, Si:C, SiGe, SiGe:C, Si alloys, Ge, Ge alloys, GaAs, InAs, InP, and other III / V and II / VI compound semiconductors. The plurality of fins 18 may be etched, for example, using reactive ion etching (RIE) or similar methods. In other embodiments, etching may include dry etching processes such as reactive ion etching, plasma etching, ion etching, or laser ablation. Etching may further include wet chemical etching processes in which one or more chemical etching solutions are used to remove portions of the layer.

[0028] The hard mask 20 may be manufactured, for example, from silicon nitride (SiN) deposited using low-pressure chemical vapor deposition (LPCVD). In other embodiments, the hard mask 20 may include, but is not limited to, hafnium oxide (HfO2), tantalum nitride (TaN), or titanium nitride (TiN). In some embodiments, the hard mask 20 may include multiple layers, for example, silicon nitride on silicon oxide. The hard mask 20 may be formed by any suitable patterning technique, including, but not limited to, sidewall image transfer (SIT), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), lithography, and subsequent etching.

[0029] The terms “epitaxial growth” and “epitaxial deposition” refer to the growth of semiconductor material on a deposition surface, where the growing semiconductor material has substantially the same crystalline properties as the semiconductor material on the deposition surface. The term “epitaxial material” refers to a material formed using epitaxial growth. In some embodiments, when the chemical reactants are controlled and the system parameters are correctly set, the deposited atoms move around on the surface and reach the deposition surface with sufficient energy to determine their own position in the crystalline arrangement of atoms on the deposition surface. Thus, in some examples, an epitaxial film deposited on a {100} crystalline surface will exhibit a {100} orientation.

[0030] Figure 2 is a cross-sectional view of the semiconductor structure shown in Figure 1, on which a conformal dielectric liner is deposited, according to an embodiment of the present invention.

[0031] A conformal dielectric 28 is deposited on a plurality of fins 18 accompanied by a hard mask 20. In one example, the conformal dielectric 28 may be, for example, silicon carbide (SiC).

[0032] Figure 3 is a cross-sectional view of the semiconductor structure of Figure 2, according to an embodiment of the present invention, in which a conformal dielectric liner is etched back to form conformal dielectric pillars.

[0033] The conformal dielectric 28 is isotropically etched back in order to expose the upper surface of the sacrificial liner 22 and to define the conformal dielectric pillar 30. In one example, the conformal dielectric pillar 30 is formed between a first set of fins 18A and a second set of fins 18B.

[0034] Figure 4 is a cross-sectional view of the semiconductor structure shown in Figure 3, on which an interlayer dielectric (ILD) is deposited, according to an embodiment of the present invention.

[0035] ILD32 is deposited. ILD32 is shown along the Y-Y' viewpoint.

[0036] ILD32 may include any material known in the art, such as porous silica, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric materials. ILD32 may be formed using any method known in the art, such as chemical vapor deposition, plasma-accelerated chemical vapor deposition, atomic layer deposition, or physical vapor deposition. ILD32 may have a thickness ranging from about 25 nm to about 200 nm. After ILD32 deposition, a CMP process is subsequently performed to flatten the ILD to a fin hard mask 20.

[0037] Figure 5 is a cross-sectional view of the semiconductor structure shown in Figure 4, with the hard mask removed, according to an embodiment of the present invention.

[0038] The hard mask 20 is removed to expose the upper surfaces of the multiple fins 18. The removal of the hard mask 20 results in the formation of an opening 34. The conformal dielectric pillar 30 remains unchanged.

[0039] Figure 6 is a cross-sectional view of the semiconductor structure of Figure 5, according to an embodiment of the present invention, in which the sacrificial liner is recessed to expose the upper portions of several fins.

[0040] The two-layer sacrificial liner 22 is recessed to expose the upper portions 19 of the multiple fins 18. The sacrificial liner 22 is recessed so that the sacrificial liner portion 22' remains between the multiple fins 18.

[0041] The recessing process can be carried out by vapor-phase HCl dry etching or wet etching to initially recess the sacrificial SiGe layer. In one example, vertical wet etching may be used to define the channel length. Non-limiting examples of wet etching processes that may be used to form the recesses include hydrogen peroxide (H2O2), potassium hydroxide (KOH), ammonium hydroxide (ammonia), tetramethylammonium hydroxide (TMAH), hydrazine, or ethylene diamine pyrocatechol (EDP), or any combination thereof. Subsequently, another wet or dry etching process is used to remove the thin SiO2 liner, for example, by DHF water washing or SiCoNi oxide removal.

[0042] Figure 7 is a cross-sectional view of the semiconductor structure of Figure 6, in which the upper spacer, upper source / drain region, and upper epitaxial cap are deposited according to an embodiment of the present invention.

[0043] An upper spacer 40 is deposited, followed by an upper S / D region 42, and then an upper epi cap 44. The upper spacer 40 is formed adjacent to the upper portion 19 of the multiple fins 18. The upper S / D region 42 is formed on the multiple fins 18 such that the S / D region 42 is in direct contact with the upper surface of the multiple fins 18.

[0044] The side walls of the upper spacer 40, the side walls of the upper S / D region 42, and the side walls of the upper epi cap 44 are in direct contact with the side walls of the conformal dielectric pillar 30.

[0045] The upper spacer 40 may include any one or more of the following: a SiN film, a SiBN film, a SiCN film, or a SiBCN film, or a combination thereof.

[0046] Other non-limiting examples of materials for the upper spacer 40 include oxides (e.g., silicon oxide), dielectric nitrides (e.g., silicon nitride), dielectric oxynitrides, or any combination thereof. The upper spacer 40 is first formed as a layer on the substrate 10 by a deposition process, e.g., ALD, chemical vapor deposition (CVD), or physical vapor deposition (PVD). In some embodiments, the upper spacer 40 is formed by an ALD deposition process to pinch off a cavity formed on the concave sacrificial liner 22, and subsequently by an isotropic etch-back process to remove the upper spacer liner in all areas except the pinched-off region.

[0047] It should be understood that, as used herein, the term "source / drain region" means that a given source / drain region may be either a source region or a drain region, depending on the application.

[0048] Examples of various epitaxial growth processes include, for example, rapid thermochemical deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical deposition (UHVCVD), atmospheric pressure chemical deposition (APCVD), liquid-phase epitaxy (LPE), molecular beam epitaxy (MBE), and metal-organic chemical deposition (MOCVD). The temperature for the epitaxial growth process can range, for example, from 550°C to 900°C, but is not necessarily limited to this range and can be higher or lower as needed.

[0049] Figure 8 is a cross-sectional view of the semiconductor structure of Figure 7, in which an upper replacement metal gate (RMG) trench is opened according to an embodiment of the present invention.

[0050] An organic planarization layer (OPL) 46 is deposited, and the trench opening 48 is defined by a lithography and patterning process so that the upper surface of the lower spacer 16 is exposed, and the side walls 25 and upper surface 23 of the sacrificial liner portion 22' are exposed. Additionally, the ILD 32 may be patterned into the ILD area 32'.

[0051] The thickness of OPL46 can be in the range of approximately 50 nm to approximately 300 nm. In one example, the thickness of OPL46 is approximately 100 nm. The OPL layer 46 may contain organic materials such as polymers.

[0052] Figure 9 is a cross-sectional view of the semiconductor structure of Figure 8, according to an embodiment of the present invention, in which the sacrificial gate is removed to create an opening between multiple fins.

[0053] The sacrificial liner portion 22' is completely removed to create a gap or opening 50.

[0054] Removal can be carried out by a wet etching process. The vertical height of the cavity remaining when the sacrificial liner 22' is removed defines the gate length of the device. Non-limiting examples of wet etching processes that can be used to remove the sacrificial two-layer liner 22' include hydrogen peroxide (H2O2), potassium hydroxide (KOH), ammonium hydroxide (ammonia), tetramethylammonium hydroxide (TMAH), hydrazine, or ethylene diamine pyrocatechol (EDP), or any combination thereof, followed by a DHF rinse.

[0055] Figure 10 is a cross-sectional view of the semiconductor structure shown in Figure 9, in which a replacement gate (RMG) is generated (formation of a high-k metal gate (HKMG)) according to an embodiment of the present invention.

[0056] The HKMG gate stack 52 is deposited within the gap or opening 50. The conformal dielectric pillar 30 extends above the upper surface of the HKMG gate stack 52.

[0057] RMG52 is positioned between the fins of the first fin set 18A and between the fins of the second fin set 18B. RMG52 is in direct contact with the sidewall of the conformal dielectric pillar 30. The width 76 of RMG52 between the first fin set 18A (Figure 12) is equal to the width of RMG76 between the second fin set 18B. The width 76 of RMG52 between the fins of the first fin set 18A and the conformal dielectric pillar 30 is equal to the width of RMG52 between the fins of the second fin set 18B and the conformal dielectric pillar 30.

[0058] RMG52 includes HKMG materials. Examples of high-k dielectrics include HfO2, HfSiOx, HfAlOx, ZrO2, and TaOx, and examples of metal gates include work function metals such as TiN, TiAlC, TiC, and TaN, and optionally conductive metal fills such as W and Al. The HKMG deposition process is highly conformal and can be achieved using atomic layer deposition (ALD) processes.

[0059] Figure 11 is a cross-sectional view of the semiconductor structure shown in Figure 10, in which metal recess processing is performed according to an embodiment of the present invention.

[0060] The metal recessing occurs where a portion of the RMG 52 is removed so that the RMG segment 53 remains adjacent to the fin 18. An opening is created below the ILD area 32'.

[0061] Figure 12 is a cross-sectional view of the semiconductor structure of Figure 11, in which contacts are formed, according to an embodiment of the present invention.

[0062] Contacts 60, 62, and 64 are formed within the final structures 80 and 80'. The CA contact 60 is formed on the upper surface of the upper S / D region 40. The CB contact 62 is formed on the upper surface of the RMG 52. The TS contact 64 is formed on the upper surface of the lower S / D region 12. Further ILD 70 is deposited adjacent to the contacts 60, 62, and 64.

[0063] The X-X' viewpoint explains the self-aligning pillar 76.

[0064] The width 76 of each RMG52 is equal among the fins of the first fin set 18A, and the width 76 of each RMG52 is equal among the fins of the second fin set 18B. Therefore, there is an equal gate stack between the inner and outer edges of the fins. Thus, the spacing between devices becomes larger to ensure work function metal (WFM) and isolation without affecting density. Furthermore, all fins see the same WFM stack.

[0065] As a result, variable fin pitch with self-aligned isolation pillars allows for closer positioning of fins in adjacent devices. Therefore, fin pitches of less than 36 nm can be achieved.

[0066] In conclusion, exemplary embodiments form variable-fin pitch VFETs by a robust substitution metal gate process with self-aligned isolation. The exemplary integrated circuit (IC) includes a vertical transistor (VFET) having a device with variable-fin pitch, an isolation structure formed substantially in the middle between fins having wider pitches, fused lower S / D epitaxials and fused upper S / D epitaxials for fins having smaller pitches, where the gate stack thickness between the smaller pitch fins is the same as the gate stack thickness between the fins and the intermediate isolation structure. The exemplary method includes forming a hard mask and a vertical FIN with variable pitch, and forming sacrificial material to pinch off the smaller pitches while the larger pitches leave space between them, where the thickness of the sacrificial material between the smaller pitch fins is the same as the thickness of the sacrificial material between the fins and the space. Further steps include forming a self-separation in space, removing the fin hard mask, recessing the sacrificial material to form a concave sacrificial gate pillar, forming an upper spacer, a fused upper epi, and an epi cap, forming a trench opening to expose the sacrificial material, removing the sacrificial material, and forming a replacement gate.

[0067] Regarding Figures 1 to 12, deposition is any process of growing, coating, or separately transferring a material onto a wafer. Available technologies are not limited to, but include thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). As used herein, “depositing” may include, but is not limited to, any currently known or subsequently developed techniques suitable for the material to be deposited, including, for example, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-accelerated CVD (PECVD), semi-atmospheric CVD (SACVD), and high-density plasma CVD (HDPCVD), fast thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), restricted-reaction CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser deposition, thermal oxidation, thermal nitriding, spin-on method, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and evaporation.

[0068] The term “processing,” as used herein, includes deposition, patterning, exposure, development, etching, washing, stripping, embedding, doping, stressing, lamination, or removal of material or photoresist, or any combination thereof, as required to form the described structure.

[0069] Removal is any process that removes material from a wafer, and examples include etching processes (either wet or dry) and chemical mechanical planarization (CMP).

[0070] Patterning is the shaping or modification of deposited materials and is generally referred to as lithography. For example, in conventional lithography, a wafer is coated with a chemical called photoresist, and then a machine called a stepper focuses on, aligns, and moves a mask to expose a selected portion of the wafer below with short-wavelength light, and the exposed area is washed away with a developer. After etching or other processing, any remaining photoresist is removed. Patterning also includes electron beam lithography.

[0071] Modification of electrical properties may generally involve doping, such as doping the transistor source and drain by diffusion, ion implantation, or a combination thereof. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing plays a role in activating the implanted dopants.

[0072] While the present invention is described in relation to a given illustrative architecture, it should be understood that other architectures, structures, substrate materials, and process features and steps / blocks may be varied within the scope of the invention.

[0073] When an element such as a layer, region, or substrate is described as being "on" or "over" another element, it should be understood that it can be directly on top of the other element, or there may be an intervening element. In contrast, when an element is described as being "directly on" or "directly over" another element, there is no intervening element. When an element is described as being "connected" or "joined" to another element, it should be understood that it can be directly connected or joined to the other element, or there may be an intervening element. In contrast, when an element is described as being "directly connected" or "directly joined" to another element, there is no intervening element.

[0074] This embodiment may include a design for an integrated circuit chip, which may be created in a graphical computer programming language and stored on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive, such as within a storage access network). If the designer does not manufacture the chip or the photolithography mask used to manufacture the chip, the designer may transmit the resulting design directly or indirectly to such an entity, either by a physical mechanism (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing a photolithography mask containing multiple copies of the chip design to be formed on a wafer. The photolithography mask is used to define areas of the wafer to be etched or otherwise processed.

[0075] The methods described herein may be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer as raw material wafers (i.e., a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other high-level carrier) or a microchip package (such as a ceramic carrier with either surface-mounted or embedded wiring, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices or combinations thereof as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product may be any product containing an integrated circuit chip, ranging from toys and other low-end applications to displays, keyboards or other input devices, and advanced computer products with a central processor.

[0076] It should also be understood that the material compounds are described with respect to the listed elements, for example, SiGe. These compounds contain different proportions of elements within the compound; for example, SiGe contains Si where x is less than or equal to 1. x Ge 1-x This includes, for example, other elements. In addition, other elements may be included in the compound and it will still function according to this embodiment. Compounds having additional elements are referred to herein as alloys. Any reference herein to “one embodiment” or “embodiment” of the present invention, and to other variations thereof, means that certain features, structures, properties, etc., described in relation to that embodiment are included in at least one embodiment of the present invention. Thus, any appearance of the phrase “in one embodiment” or “in an embodiment” and any other variations throughout this specification does not necessarily refer to the same embodiment.

[0077] Please understand that the use of any of the following " / ", "or... or a combination thereof", and "at least one of the following" is intended to include, for example, "A / B", "A or B or a combination thereof", and "at least one of A and B", the selection of only the first enumerated option (A), only the second enumerated option (B), or the selection of both options (A and B). As a further example, in the case of "A, B, or C or a combination thereof", and "at least one of A, B, and C", such expressions are intended to include the selection of only the first enumerated option (A), only the second enumerated option (B), only the third enumerated option (C), only the first and second enumerated options (A and B), only the first and third enumerated options (A and C), only the second and third enumerated options (B and C), or the selection of all three options (A, B, and C). This can be expanded to the same number of items as listed, as will be readily apparent to those skilled in the art.

[0078] The terms used herein are for the sole purpose of describing specific embodiments and are not intended to be an limitation of the embodiments. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context explicitly indicates otherwise. The terms “equip,” “equip,” “include,” or “include,” or any combination thereof, where used herein, describe the presence of the described feature, integer, step, action, element, or component or combination thereof, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components or groups thereof or combination thereof.

[0079] Spatial terms such as “beneath,” “below,” “downward,” “up,” “above,” and similar terms may be used herein to facilitate explanation in describing the relationship of one element or feature to another, as illustrated in the figures. It should be understood that spatial terms are intended to encompass different orientations of a device in use or operation, in addition to the orientation depicted in the figures. For example, if a device is inverted in the figure, an element described as “below” or “beneath” another element or feature will be oriented “above” the other element or feature. Thus, the term “below” may encompass both up and down orientations. A device may be oriented separately (rotated 90 degrees or to other orientations), and spatial descriptions used herein may be interpreted accordingly. Furthermore, it should be understood that when a layer is referred to as being “between” two layers, it may be the sole layer between the two layers, or there may be one or more intervening layers.

[0080] Terms such as "First," "Second," etc., may be used herein to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. Therefore, the first element discussed below may be named the second element without deviating from the scope of this concept.

[0081] Preferred embodiments (intended to be illustrative and not limiting) of a method for forming a vertical field-effect transistor (VFET) substituted metal gate (RMG) with variable fin pitch and self-aligned isolation have been described, but it should be noted that modifications and changes can be made by those skilled in the art in view of the above teachings. Therefore, it should be understood that modifications within the scope of the invention, as outlined by the appended claims, can be made in the particular embodiments described. While aspects of the invention have thus been described with detail and as particularly required by patent law, those claimed and for which patent protection is desired are specified in the appended claims.

Claims

1. The first set of fins and the second set of fins, A dielectric pillar is disposed between the first set of fins and the second set of fins, A lower source / drain (S / D) region that directly contacts the lower surface of the first and second sets of fins, An upper S / D region that directly contacts the upper surfaces of the first and second sets of fins, Equipped with, The first set of fins has a first fin pitch, the second set of fins has a second fin pitch, and the first fin pitch is different from the second fin pitch. Semiconductor structure.

2. The semiconductor structure according to claim 1, wherein high-k metal gates (HKMG) are formed between the fins of a first set of fins and between the fins of a second set of fins.

3. The semiconductor structure according to claim 2, wherein the HKMG is in direct contact with the side wall of the dielectric pillar.

4. The semiconductor structure according to claim 3, wherein the width of the HKMG between the first set of fins is equal to the width of the HKMG between the second set of fins.

5. The semiconductor structure according to claim 3, wherein the width of the HKMG between the fins of the first set of fins and the dielectric pillar is equal to the width of the HKMG between the fins of the second set of fins and the dielectric pillar.

6. The semiconductor structure according to claim 3, wherein the dielectric pillar extends onto the upper surface of the HKMG.

7. The semiconductor structure according to any one of claims 1 to 6, wherein the pitch between the fins of the first set of fins and the fins of the second set of fins is different from the pitch between the fins of the first set of fins and different from the pitch between the fins of the second set of fins.

8. To form a first set of fins and a second set of fins, To form sacrificial material adjacent to the first and second sets of fins, The dielectric pillar separates the first set of fins from the second set of fins, thereby generating self-aligned isolation. The aforementioned sacrificial material is processed to create a recess, thereby defining a concave sacrificial material gate pillar. The upper spacer, upper source / drain (S / D) region, and epi cap are formed in a continuous manner, Forming a trench opening to expose the concave sacrificial material, The aforementioned concave sacrificial material is removed to define the opening, A method comprising forming a high-k metal gate (HKMG) in the opening.

9. A first set of fins defining a plurality of first fins having a first pitch in between, A second set of fins defining a plurality of second fins having a second pitch in between, Between the first set of fins and the second set of fins, a dielectric pillar is erected vertically, exceeding the height of the first and second fins. The system comprises high-k metal gates (HKMG) disposed between the first set of fins and between the second set of fins, The HKMG has a width between the first set of fins that is equal to the width of the HKMG between the second set of fins, A third pitch is defined between the first fin of the plurality of first fins adjacent to the dielectric pillar and the second fin of the plurality of second fins adjacent to the dielectric pillar. The HKMG adjacent to the dielectric pillar is in direct contact with the dielectric pillar. Semiconductor structure.

10. The semiconductor structure according to claim 9, wherein the width of the HKMG between the fins of the first set of fins and the dielectric pillar is equal to the width of the HKMG between the fins of the second set of fins and the dielectric pillar.

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