Components for semiconductor manufacturing equipment and methods for recycling them.

Abstract

To provide a semiconductor manufacturing equipment member that can suppress heat generation when RF is applied and also has other required performance characteristics.SOLUTION: A semiconductor manufacturing equipment member includes a first ceramic portion having an upper surface that has a wafer mounting surface and a lower surface located opposite the upper surface, a second ceramic portion bonded to the lower surface of the first ceramic portion, an amorphous layer present at the bonding interface between the first ceramic portion and the second ceramic portion, and a high-frequency electrode disposed inside the first ceramic portion or between the first ceramic portion and the second ceramic portion, and the first ceramic part has a smaller dielectric tangent (tanδ) than the second ceramic portion.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to components for semiconductor manufacturing equipment and a method for regenerating the same. [Background technology]

[0002] Conventionally, semiconductor manufacturing equipment components used for wafer holding, temperature control, and transport are known. These types of semiconductor manufacturing equipment components are also called wafer stands, electrostatic chucks, susceptors, etc., and generally have the function of attracting wafers by electrostatic force by applying electrostatic power to the built-in electrodes. In addition, some semiconductor manufacturing equipment components have high-frequency electrodes (RF electrodes) embedded in a ceramic substrate, and plasma is generated using these RF electrodes.

[0003] As such components for semiconductor manufacturing equipment, for example, there is known to be a ceramic substrate having an upper surface with a wafer mounting surface and a lower surface located on the opposite side of the upper surface, and incorporating RF electrodes. The wafer mounting surface can be, for example, the upper end surfaces of a plurality of protrusions provided on the upper surface of the ceramic substrate.

[0004] In recent years, high-power and high-speed etching equipment has been used in the manufacturing of multilayer 3D NAND and other semiconductors to perform high-aspect-ratio microfabrication. The materials used in semiconductor manufacturing equipment components for such etching equipment are required to have low RF loss, high dielectric constant, and resistance to dielectric breakdown. Furthermore, a small tanδ (i.e., dielectric loss tangent) is required to suppress heat generation when RF is applied.

[0005] Therefore, Patent Document 1 proposes using a composite sintered body comprising aluminum oxide, silicon carbide, and a magnesium-aluminum composite oxide having a spinel-type crystal structure as a material for a ceramic substrate of a semiconductor manufacturing equipment component.

[0006] Patent Document 2 states that the dielectric loss tangent tanδ at frequencies of 1 to 20 GHz is 1 × 10⁻¹⁰-4 The following yttria sintered bodies are described.

[0007] Patent Document 3 states that the dielectric loss tangent tanδ at a frequency of 1 MHz is 5 × 10 -4 The following alumina-based sintered bodies are described below. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Patent No. 7227954 [Patent Document 2] Patent No. 5466831 [Patent Document 3] Patent No. 5421092 [Overview of the Initiative] [Problems that the invention aims to solve]

[0009] The materials proposed in Patent Documents 1 to 3 have a small dielectric loss tangent, which can suppress heat generation when RF is applied. On the other hand, semiconductor manufacturing equipment components sometimes require performance other than a small dielectric loss tangent, such as high heat uniformity and high heat dissipation. The materials described in Patent Documents 1 to 3 also have a high relative permittivity and high dielectric strength in addition to a small dielectric loss tangent, but there are limits to the properties that can be combined.

[0010] Furthermore, if the quality of semiconductor manufacturing equipment components deteriorates, these components can be discarded. However, from the perspective of reducing waste and promoting a circular economy through the effective use of resources, it is desirable that semiconductor manufacturing equipment components can be repaired and recycled.

[0011] In view of the above circumstances, an object of the present invention in one embodiment is to provide a member for a semiconductor manufacturing apparatus that can suppress heat generation when RF is applied and also satisfy other required performance. Another object of the present invention in another embodiment is to provide a method for regenerating a member for a semiconductor manufacturing apparatus.

Means for Solving the Problems

[0012] The present inventor has intensively studied to solve the above problems and created the present invention exemplified below. [Aspect 1] A first ceramic part having an upper surface with a wafer mounting surface and a lower surface located on the opposite side of the upper surface, a second ceramic part joined to the lower surface of the first ceramic part, a first amorphous layer present at the joining interface between the first ceramic part and the second ceramic part, and a high-frequency electrode disposed inside the first ceramic part or between the first ceramic part and the second ceramic part, wherein the first ceramic part has a smaller dielectric loss tangent (tanδ) than the second ceramic part, a member for a semiconductor manufacturing apparatus. [Aspect 2] The dielectric loss tangent (tanδ) of the first ceramic part at a measurement frequency of 1 MHz is 1×10 -3 The member for a semiconductor manufacturing apparatus according to Aspect 1 below. [Aspect 3] The member for a semiconductor manufacturing apparatus according to Aspect 1 or 2, wherein the first ceramic part is a plate having a plurality of protrusions with the wafer mounting surface on the upper surface. [Aspect 4] The member for a semiconductor manufacturing apparatus according to any one of Aspects 1 to 3, wherein the second ceramic part has a higher thermal conductivity than the first ceramic part. [Aspect 5] The member for a semiconductor manufacturing apparatus according to any one of Aspects 1 to 4, [[ID=3I]]a first altered layer present on the side of the first ceramic part that contacts the first amorphous layer, a second altered layer present on the side of the second ceramic part that contacts the first amorphous layer, A member for a semiconductor manufacturing apparatus having the same. [Aspect 6] A member for a semiconductor manufacturing apparatus according to any one of Aspects 1 to 5, a third ceramic part joined to the lower surface of the second ceramic part, a second amorphous layer present at the bonding interface between the second ceramic part and the third ceramic part, A member for a semiconductor manufacturing apparatus having the same. [Aspect 7] In the position of the second ceramic part facing the second amorphous layer or in the position of the third ceramic part facing the second amorphous layer, a refrigerant flow path through which refrigerant flows or a gas flow path for supplying gas to the wafer placement surface is provided. A member for a semiconductor manufacturing apparatus according to Aspect 6. [Aspect 8] A member for a semiconductor manufacturing apparatus according to Aspect 6 or 7, a third altered layer present on the side of the second ceramic part contacting the second amorphous layer, a fourth altered layer present on the side of the third ceramic part contacting the second amorphous layer, A member for a semiconductor manufacturing apparatus having the same. [Aspect 9] A step of processing the upper surface of the first ceramic part of the member for a semiconductor manufacturing apparatus according to any one of Aspects 1 to 8 to form a processed surface with the wafer placement surface removed on the first ceramic part, A step of further processing the processed surface to form a new wafer placement surface, a method for regenerating a member for a semiconductor manufacturing apparatus including the same. [Aspect 10] A step of processing the upper surface of the first ceramic part of the member for a semiconductor manufacturing apparatus according to any one of Aspects 1 to 8 to form a processed surface with the wafer placement surface removed on the first ceramic part, A step of directly bonding a regenerative ceramic part having a smaller dielectric loss tangent (tanδ) than the second ceramic part to the processed surface, A method for regenerating a member for a semiconductor manufacturing apparatus including the same. [Aspect 11] A step of processing the first ceramic portion of the semiconductor manufacturing apparatus component described in any of embodiments 1 to 8, removing it so that the second ceramic portion is exposed, and forming a processed surface on the second ceramic portion, A step of directly bonding a regenerative ceramic portion having a smaller dielectric loss tangent (tanδ) than the second ceramic portion to the processed surface of the second ceramic portion, A method for regenerating semiconductor manufacturing equipment components, including those mentioned above. [Effects of the Invention]

[0013] A semiconductor manufacturing equipment component according to one embodiment of the present invention is equipped with a first ceramic portion having a small dielectric loss tangent (tanδ), thereby suppressing heat generation when RF is applied. Furthermore, the semiconductor manufacturing equipment component is equipped with a second ceramic portion having a large dielectric loss tangent (tanδ), which can exhibit different properties from the first ceramic portion. The material of the second ceramic portion can be appropriately changed according to the required performance. Therefore, in addition to suppressing heat generation when RF is applied, the semiconductor manufacturing equipment component can also possess other required performance. For example, by composing the second ceramic portion with a material with high thermal conductivity, it is possible to achieve both high heat uniformity and high heat dissipation.

[0014] Furthermore, even if the quality of the semiconductor manufacturing equipment components deteriorates due to factors such as detachment of ceramic particles constituting the protrusions on the wafer mounting surface, they can be repaired and recycled without having to manufacture new semiconductor manufacturing equipment components from scratch. Therefore, this recycling method greatly contributes to reducing waste, effectively utilizing resources, and promoting a circular economy. [Brief explanation of the drawing]

[0015] [Figure 1A] This is an example of a schematic partial longitudinal cross-sectional view of a semiconductor manufacturing apparatus component according to Embodiment A of the present invention. [Figure 1B-1] This is an example of a schematic partial longitudinal section view of a semiconductor manufacturing apparatus component according to Embodiment B of the present invention. [Figure 1B-2] This is another example of a schematic partial longitudinal cross-sectional view of a semiconductor manufacturing apparatus component according to Embodiment B of the present invention. [Figure 2] This is a schematic close-up of the area enclosed by the thick border shown in Figure 1A. [Figure 3] This is a schematic plan view of the wafer mounting surface of a semiconductor manufacturing apparatus component according to Embodiment A of the present invention. [Figure 4] This is a diagram illustrating an example of a manufacturing method for components used in semiconductor manufacturing equipment. [Figure 5A] This is a diagram illustrating a regeneration method A according to one embodiment of the present invention. [Figure 5B] This is a diagram illustrating a regeneration method B according to one embodiment of the present invention. [Figure 5C] This is a diagram illustrating a regeneration method C according to one embodiment of the present invention. [Figure 6] This is a schematic perspective view of a polishing apparatus for performing lapping. [Modes for carrying out the invention]

[0016] Next, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments, and it should be understood that appropriate design changes, improvements, etc., may be made based on the ordinary knowledge of those skilled in the art, without departing from the spirit of the invention. Furthermore, in this specification, "up" and "down" are for convenience's purposes to represent the relative positional relationship when the semiconductor manufacturing equipment component is placed on a horizontal plane with the wafer mounting surface facing upwards, and do not represent an absolute positional relationship. Therefore, depending on the orientation of the semiconductor manufacturing equipment component, "up" and "down" may become "down" and "up," or "left" and "right," or "front" and "back."

[0017] <1. Basic Configuration of Components for Semiconductor Manufacturing Equipment> A semiconductor manufacturing apparatus component according to one embodiment of the present invention comprises a first ceramic portion having an upper surface on which a wafer is mounted and a lower surface located opposite to the upper surface, a second ceramic portion bonded to the lower surface of the first ceramic portion, a first amorphous layer present at the bonding interface between the first and second ceramic portions, and a high-frequency electrode disposed inside the first ceramic portion or between the first and second ceramic portions, wherein the first ceramic portion has a smaller dielectric loss tangent (tanδ) than the second ceramic portion. This semiconductor manufacturing apparatus component can be used, for example, when performing processes such as CVD or etching on a wafer W using plasma.

[0018] In one embodiment, the first ceramic portion can be provided in the form of a plate having a plurality of protrusions on its upper surface that have a wafer mounting surface.

[0019] In the first ceramic portion, the dielectric loss tangent (tanδ) (typically at measurement frequencies of 1 MHz and 13.56 MHz) is smaller compared to the second ceramic portion, which makes it possible to suppress heat generation when high frequency is applied to the high-frequency electrode. Since the first ceramic portion has a wafer mounting surface, the heat generation in the first ceramic portion is suppressed, thereby suppressing the temperature rise of the wafer.

[0020] Since high-frequency electrodes tend to generate heat when placed in the second ceramic portion, which has a large dielectric loss tangent (tanδ), it is preferable that they be placed inside the first ceramic portion or between the first and second ceramic portions, and from the viewpoint of suppressing heat generation, it is more preferable that they be built inside the first ceramic portion.

[0021] The upper limit of the dielectric loss tangent (tanδ) of the first ceramic part is 1 × 10⁻¹⁰ at a measurement frequency of 1 MHz. -3 The following is preferable: 5 × 10 -4 More preferably, the following is true: 2 × 10 -4It is even more preferable that the following conditions are met. There is no particular limitation on the lower limit of the dielectric loss tangent (tanδ) of the first ceramic part. From the perspective of ease of acquisition, it is preferably 1×10 -4 or more at a measurement frequency of 1 MHz. Therefore, the dielectric loss tangent (tanδ) of the first ceramic part is, for example, 1×10 -4 or more and 1×10 -3 or less at a measurement frequency of 1 MHz, preferably 1×10 -4 or more and 5×10 -4 or less, more preferably 1×10 -4 or more and 2×10 -4 or less.

[0022] The dielectric loss tangent (tanδ) at a measurement frequency of 1 MHz is measured by the resonance method in accordance with JIS C2138:2007 under the conditions of a temperature of 25°C and a relative humidity of 50%. For example, a DAC-ASM-7 device manufactured by Soken Electric Co., Ltd. can be used. The measurement of the dielectric loss tangent (tanδ) is carried out on test pieces collected from the first ceramic part and the second ceramic part. When it is difficult to collect test pieces, test pieces made of the same material as the first ceramic part and the second ceramic part may be prepared for measurement.

[0023] As the ceramics with a dielectric loss tangent (tanδ) of 1×10 -3 or less at a measurement frequency of 1 MHz, any known ceramics that meet the conditions of the dielectric loss tangent can be used. For example, the ceramics described in Patent Documents 1 to 3 can be mentioned. More specifically, alumina, aluminum nitride, yttria, and quartz with a low dielectric loss tangent can be mentioned. The first ceramic part may contain one kind of ceramic or a combination of two or more kinds. Note that the dielectric loss tangent (tanδ) of the first ceramic part at a measurement frequency of 1 MHz only needs to be smaller than that of the second ceramic part as a whole. Even if a ceramic with a larger dielectric loss tangent (tanδ) than the second ceramic part is partially blended in the first ceramic part, it is acceptable.

[0024] The second ceramic section has a larger dielectric loss tangent (tanδ) than the first ceramic section (typically the dielectric loss tangent (tanδ) at a measurement frequency of 1 MHz). For example, the dielectric loss tangent (tanδ) of the second ceramic section at a measurement frequency of 1 MHz is 1 × 10⁻¹⁰. -3 It can be supernumerable, 1 x 10 -3 super 1×10 -2 The following is also acceptable: 1 × 10 -3 super 1×10 -1 The following is also acceptable: 1 × 10 -3 It can be greater than or equal to 1.

[0025] Furthermore, from the viewpoint of facilitating the release of heat generated in the first ceramic part, it is preferable that the second ceramic part has a higher thermal conductivity than the first ceramic part. Specifically, it is preferable that the thermal conductivity at 20°C be 50 W / (m·K) or higher, more preferably 70 W / (m·K) or higher, and even more preferably 90 W / (m·K) or higher. There is no particular upper limit to the thermal conductivity of the second ceramic part, but from the viewpoint of availability, it is preferable that the thermal conductivity at 20°C be 150 W / (m·K) or lower, more preferably 120 W / (m·K) or lower, and even more preferably 100 W / (m·K) or lower. Therefore, the thermal conductivity of the second ceramic part at 20°C is preferably, for example, 50 to 150 W / (m·K), more preferably 70 to 120 W / (m·K), and even more preferably 90 to 100 W / (m·K).

[0026] The thermal conductivity is measured using the laser flash method (JIS R1611-2010).

[0027] Examples of ceramics constituting the second ceramic portion include alumina and aluminum nitride. The second ceramic portion may contain one type of ceramic or a combination of two or more types.

[0028] Furthermore, the dielectric loss tangent (tanδ) of the second ceramic portion only needs to be greater than that of the first ceramic portion overall, and the second ceramic portion may partially contain ceramics with a dielectric loss tangent (tanδ) equal to or smaller than that of the first ceramic portion.

[0029] Preferably, the first ceramic portion and the second ceramic portion are joined via a first amorphous layer. In this case, the joining layer between the first ceramic portion and the second ceramic portion can be made extremely thin, thereby reducing the thermal resistance between the first ceramic portion and the second ceramic portion. In this case, the first ceramic portion may have a first altered layer on the side in contact with the first amorphous layer, and the second ceramic portion may have a second altered layer on the side in contact with the first amorphous layer.

[0030] Furthermore, a third ceramic portion may be joined to the lower surface of the second ceramic portion. In this case as well, it is preferable that the second ceramic portion and the third ceramic portion are joined via a second amorphous layer. In this case, the second ceramic portion may have a third altered layer on the side in contact with the second amorphous layer, and the third ceramic portion may have a fourth altered layer on the side in contact with the second amorphous layer.

[0031] There are no particular restrictions on the dielectric loss tangent (tanδ) of the third ceramic part, but from the viewpoint of ease of availability, it is acceptable for its dielectric loss tangent (tanδ) (typically at a measurement frequency of 1 MHz) to be larger than that of the first ceramic part. For example, the dielectric loss tangent (tanδ) of the third ceramic part at a measurement frequency of 1 MHz is 1 × 10⁻⁶. -3 It's perfectly fine.

[0032] Examples of ceramics constituting the third ceramic portion include alumina and aluminum nitride. Among these, aluminum nitride is preferred because it has high thermal conductivity. The third ceramic portion may contain one type of ceramic or a combination of two or more types. It is preferable that the dielectric loss tangent (tanδ) of the third ceramic portion as a whole is greater than that of the first ceramic portion, but the third ceramic portion may partially contain ceramics with a dielectric loss tangent (tanδ) equal to or smaller than that of the first ceramic portion.

[0033] In one embodiment, a refrigerant channel through which a refrigerant flows or a gas channel for supplying gas to the wafer mounting surface can be provided in the second ceramic portion facing the second amorphous layer and / or in the third ceramic portion facing the second amorphous layer.

[0034] When the first ceramic portion and the second ceramic portion are joined via a first amorphous layer, it is preferable that the first amorphous layer contains at least one element constituting the first ceramic portion and at least one element constituting the second ceramic portion. Similarly, when the second ceramic portion and the third ceramic portion are joined via a second amorphous layer, it is preferable that the second amorphous layer contains at least one element constituting the second ceramic portion and at least one element constituting the third ceramic portion.

[0035] When a longitudinal section near the interface between the first ceramic part and the second ceramic part (the second ceramic part and the third ceramic part) of a semiconductor manufacturing equipment component is observed at 4 million times magnification using a transmission electron microscope (TEM), the first amorphous layer (second amorphous layer) is observed as a narrow band. The first amorphous layer (second amorphous layer) may be formed as a single layer, or as multiple layers (e.g., three layers). The average thickness of the first amorphous layer (second amorphous layer) is preferably 0.1 nm or more, and more preferably 1 nm or more, in order to increase the bonding strength between the first ceramic part and the second ceramic part (the second ceramic part and the third ceramic part). Furthermore, the average thickness of the first amorphous layer (second amorphous layer) is preferably 30 nm or less, and more preferably 20 nm or less, in order to prevent the inclusion of dissimilar materials. Therefore, the average thickness of the first amorphous layer (second amorphous layer) is preferably, for example, 0.1 nm or more and 30 nm or less, and more preferably 1 nm or more and 20 nm or less. Note that when the first amorphous layer (second amorphous layer) is composed of multiple layers, the thickness of the first amorphous layer (second amorphous layer) refers to the total thickness of those multiple layers.

[0036] The average thickness of the first amorphous layer (second amorphous layer) at the bonding interface between the first ceramic part and the second ceramic part (the second ceramic part and the third ceramic part), as observed by TEM, is measured using the following procedure: On a single field-of-view TEM image (magnification: 4,000,000x) of a longitudinal section encompassing the bonding interface, the thickness of the first amorphous layer (second amorphous layer) is measured at five locations at 10 nm intervals along the bonding interface, and the average value of the thickness of the first amorphous layer (second amorphous layer) in that field-of-view is calculated. This thickness measurement by TEM observation is performed without bias in five fields of view, including near the center, near the outer edge, and near the center of the radius when viewing the semiconductor manufacturing equipment component in plan view. The average value of the thickness of the first amorphous layer (second amorphous layer) in the five fields of view is then taken as the measured value.

[0037] The fact that the narrow, band-shaped region observed by TEM is an amorphous layer can be confirmed by obtaining an X-ray diffraction pattern of the narrow, band-shaped region using XRD. This pattern shows a broader peak inside the narrow, band-shaped region than the first ceramic region (second ceramic region) which is sufficiently far from the bonding interface.

[0038] The fact that the first amorphous layer (second amorphous layer) contains at least one element constituting the first ceramic portion and the second ceramic portion (second ceramic portion and third ceramic portion) and at least one element constituting the ceramic plate 70 can be confirmed by methods such as EDS (Energy Dispersive X-ray Spectroscopy) or EPMA (Electron Probe Microanalyzer). In a preferred embodiment, the first amorphous layer (second amorphous layer) contains at least one amorphous material (e.g., amorphous yttria, amorphous aluminum nitride, amorphous alumina, etc.) constituting the first ceramic portion and the second ceramic portion (second ceramic portion and third ceramic portion).

[0039] The first altered layer is located on the side of the first ceramic portion that is in contact with the first amorphous layer, and the second altered layer is located on the side of the second ceramic portion that is in contact with the first amorphous layer. In the TEM images mentioned above, these are observed as layered discolored areas adjacent to the aforementioned narrow band-shaped portion. The thickness of the first and second altered layers is preferably 10 nm or more, and more preferably 100 nm or more and 1 μm or less. The presence of the first (and second) altered layer can be confirmed by obtaining an X-ray diffraction pattern by XRD near the bonding interface, where a peak is observed adjacent to the aforementioned narrow band-shaped portion, which is sharper than the first amorphous layer but broader than the peak of the first (and second) ceramic portion that is sufficiently far from the bonding interface.

[0040] The third altered layer is located on the side of the second ceramic portion that is in contact with the second amorphous layer, and the fourth altered layer is located on the side of the third ceramic portion that is in contact with the second amorphous layer. In the TEM image mentioned above, it is observed as a layered discolored area adjacent to the narrow band-shaped portion described above. The thickness of the third and fourth altered layers is preferably 10 nm or more, and more preferably 100 nm or more and 1 μm or less. The presence of the third (fourth) altered layer can be confirmed by obtaining an X-ray diffraction pattern by XRD near the bonding interface, where a peak is observed adjacent to the narrow band-shaped portion described above, which is sharper than the second amorphous layer but broader than the peak of the second ceramic portion (third ceramic portion) that is sufficiently far from the bonding interface.

[0041] <2. Specific Embodiments of Components for Semiconductor Manufacturing Equipment> (2-1. Embodiment A) Referring to the partial longitudinal cross-sectional view shown in Figure 1A, the semiconductor manufacturing equipment component 10A comprises a ceramic plate 70 having an upper surface 71 on which a wafer W can be placed and a lower surface 73 located on the opposite side of the upper surface 71; a ceramic substrate 20 bonded to the lower surface 73 of the ceramic plate 70; an amorphous layer 80 present at the bonding interface between the ceramic plate 70 and the ceramic substrate 20; an electrostatic adsorption electrode 26a embedded in the ceramic plate 70; and a high-frequency electrode 26b positioned inside the ceramic plate 70 or between the ceramic plate 70 and the ceramic substrate 20. The semiconductor manufacturing equipment component 10A also includes a base plate 30 located on the lower surface 23 side of the ceramic substrate 20 and incorporating a refrigerant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded via a bonding layer 40.

[0042] In Embodiment A, the ceramic plate 70 corresponds to the first ceramic portion described above, and the ceramic substrate 20 corresponds to the second ceramic portion described above. Also, the amorphous layer 80 corresponds to the first amorphous layer described above. Since the ceramic plate 70 has a smaller dielectric loss tangent (tanδ) than the ceramic substrate 20, it can suppress heat generation when a high frequency is applied to the high-frequency electrode 26b.

[0043] The ceramic substrate 20 comprises a central portion 201 having a circular top surface 21 in plan view, and an outer peripheral portion 202 on the outer periphery of the central portion 201 having an annular top surface 27 in plan view. The central portion 201 of the ceramic substrate 20 can have, for example, a diameter of 130 to 450 mm and a thickness of 1 to 5 mm. The height of the protrusion 72 can be, for example, 5 to 100 μm. A wafer W can be placed on the top surface 71 of the ceramic plate 70 which is bonded to the top surface 21 of the central portion 201. A focus ring (not shown) can be placed on the top surface 27 of the outer peripheral portion 202 of the ceramic substrate 20. The top surface 27 of the outer peripheral portion 202 is lower than the top surface 21 of the central portion 201. The bottom surfaces 23 of the central portion 201 and the outer peripheral portion 202 may be on the same plane. The ceramic substrate 20 may have a central portion 201 but no outer peripheral portion 202, that is, it may not have a lower upper surface 27.

[0044] The upper surface 71 of the ceramic plate 70 is provided with a plurality of protrusions 72 for placing a wafer W, and the upper surface 71a of the protrusions 72 constitutes the wafer mounting surface. The upper surface 71 may also have a seal band 75 formed along its outer edge, in which case the upper surface 71c of the seal band 75 can also constitute the wafer mounting surface. It is preferable that the seal band 75 and the plurality of protrusions 72 be of the same height. As shown in Figure 3, in one embodiment, an annular seal band 75 is formed along the outer edge of the upper surface 71 of the ceramic plate 70, and a plurality of protrusions 72 are formed over the entire inner surface of the seal band 75.

[0045] Figure 2 is a schematic magnified view of the area enclosed by the thick frame in Figure 1A, showing the schematic structure of the protrusions 72 provided on the upper surface 71 of the ceramic plate 70. The number density of the protrusions 72 per unit area in a plan view is, for example, 1 to 150 protrusions / mm². 2 It can be done at a rate of 10-150 pieces / mm 2 This can be done. The shape of the projection 72 is not limited, but can be a columnar shape such as a cylinder or a rectangular prism. The height h of the projection 72 is, for example, 5 to 100 μm, and can typically be 10 to 30 μm. The diameter d of the projection 72 is, for example, 0.3 to 3.0 mm, and can typically be 0.8 to 2.2 mm. Here, the diameter d of the projection 72 refers to the equivalent diameter of a circle when the projection 72 is viewed from above. The portion of the upper surface 71 of the ceramic plate 70 that does not have the seal band 75 or projection 72 is referred to as the reference surface 71b.

[0046] The multiple protrusions 72 may have at least their upper surfaces 71a covered with a coating film. Similarly, at least the upper surface 71c of the seal band 75 may be covered with a coating film. Examples of the coating film include a coating film comprising at least one selected from silicon carbide, diamond-like carbon, amorphous silicon, molybdenum, chromium, and tantalum.

[0047] The electrostatic adsorption electrode 26a is a planar electrode used as an electrostatic adsorption electrode and is connected to an external DC power supply via a power supply member (not shown). The electrode 26a is formed of a material containing, for example, W, Mo, WC, MoC, etc. A low-pass filter (LPF) may be placed in the middle of the power supply member. The power supply member is electrically insulated from the bonding layer 40 and the base plate 30. When a DC voltage is applied to the electrode 26a, the wafer W is adsorbed and fixed to the wafer mounting surface, specifically the upper surface 71c of the seal band 75 and the upper surface 71a of the projection 72, by electrostatic adsorption force, and when the application of the DC voltage is removed, the adsorption and fixation of the wafer W to the wafer mounting surface is released. The electrode 26a may be embedded in either the ceramic plate 70 or the ceramic substrate 20, but it is preferable to embed it in a position where the electrode 26a remains without being removed when the semiconductor manufacturing equipment component 10A is regenerated.

[0048] The high-frequency electrode 26b is an RF electrode for plasma generation and is connected to an external RF power supply via a power supply member (not shown). The electrode 26b is formed from a material containing, for example, W, Mo, WC, MoC, etc. A high-pass filter (HPF) may be placed in the middle of the power supply member.

[0049] In addition to these electrodes, other electrodes may be embedded in the ceramic plate 70 or ceramic substrate 20. For example, a heater electrode (resistive heating element) may be embedded. In this case, a heater power supply is connected to the heater electrode. The other electrodes may be embedded as a single layer, or as two or more layers with gaps in between.

[0050] The base plate 30 can be, for example, disc-shaped. The base plate 30 may have an annular flange on its lower side used to clamp the semiconductor manufacturing equipment component 10A to a jig inside the chamber. The thickness of the base plate 30 can be 20 to 40 mm, typically 25 to 35 mm. The base plate 30 can be connected to a radio frequency (RF) power supply and used as an RF electrode.

[0051] The base plate 30 can be a disc with good electrical and thermal conductivity (a disc with the same diameter as or larger than the ceramic substrate 20). A refrigerant channel 32 through which the refrigerant circulates may be formed inside the base plate 30. The refrigerant flowing through the refrigerant channel 32 is preferably a liquid and preferably electrically insulating. Examples of electrically insulating liquids include fluorine-based inert liquids. The refrigerant channel 32 can be formed, for example, in a single continuous line from one end (inlet) to the other end (outlet) across the entire base plate 30 in a plan view. A supply port and a recovery port of an external refrigerant device (not shown) are connected to one end and the other end of the refrigerant channel 32, respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant channel 32 passes through the refrigerant channel 32, returns to the recovery port of the external refrigerant device from the other end of the refrigerant channel 32, is temperature-adjusted, and then supplied again from the supply port to one end of the refrigerant channel 32.

[0052] The base plate 30 can be made of, for example, a metallic material or a composite material of metal and ceramics. Examples of metallic materials include Al, Ti, Mo, or alloys thereof. Examples of composite materials of metal and ceramics include metal matrix composites (MMC) and ceramic matrix composites (CMC). Specific examples of such composite materials include materials containing Si, SiC, and Ti (also called SiSiCTi), materials in which Al and / or Si are impregnated into a porous SiC body, and composite materials of Al2O3 and TiC. A material in which Al is impregnated into a porous SiC body is called AlSiC, and a material in which Si is impregnated into a porous SiC body is called SiSiC. It is preferable to select a material for the base plate 30 that has a thermal expansion coefficient close to that of the ceramic substrate 20. For example, if the ceramic substrate 20 is made of alumina, it is preferable that the base plate 30 be made of SiSiCTi or AlSiC, which have a thermal expansion coefficient close to that of alumina.

[0053] As shown in Figure 1A, the upper surface 31 of the base plate 30 is bonded to the lower surface 23 of the ceramic substrate 20 via a bonding layer 40. The bonding layer 40 bonds the lower surface 23 of the ceramic substrate 20 to the upper surface 31 of the base plate 30. The bonding layer 40 may be composed of a metal layer formed from, for example, solder or metal brazing material. The bonding layer 40 is formed, for example, by TCB (Thermal Compression Bonding). TCB is a known method in which a metal bonding material is sandwiched between two members to be bonded, and the two members are pressed together while heated to a temperature below the solidus temperature of the metal bonding material. The bonding layer 40 is not limited to a metal layer. For example, a resin bonding layer may be used instead of a metal layer. The resin bonding layer can be composed of, for example, a cured product of a silicone resin adhesive, epoxy resin adhesive, acrylic resin adhesive, or urethane resin adhesive. Furthermore, by directly joining the lower surface 23 of the ceramic substrate 20 and the upper surface 31 of the base plate 30, the bonding layer 40 can also be made of an amorphous layer.

[0054] At least one of the sides of the ceramic substrate 20, the outer periphery of the bonding layer 40, and the sides of the base plate 30 can be covered with an insulating film 35. Examples of insulating films 35 include thermal spray films of alumina and yttria.

[0055] The semiconductor manufacturing equipment component 10A may have multiple holes that penetrate vertically through the ceramic plate 70 and the ceramic substrate 20. Such holes include multiple gas holes 50 opening in the upper surface 71 and lift pin holes for inserting lift pins to move the wafer W up and down through the upper surface 21. Multiple gas holes 50 can be provided at appropriate positions when the upper surface 21 is viewed from above (see Figure 3). The gas holes 50 communicate with a gas channel provided inside the base plate 30 and can supply a heat conductive gas such as He gas that has passed through the gas channel. Typically, the gas holes 50 can be provided to open in a location (reference surface 71b) where the seal band 75 and multiple protrusions 72 are not provided on the upper surface 71 where the seal band 75 and multiple protrusions 72 are provided. Also, the gas holes 50 are formed in a position that does not overlap with the electrodes 26a and 26b. When heat conductive gas is supplied to the gas holes 50, the heat conductive gas fills the space on the back side of the wafer W placed on the upper surface 71. A plug 55 having a gas passage may be embedded in the gas hole 50. Multiple lift pin holes can be provided at equal intervals along the concentric circles of the upper surface 71 when the upper surface 71 is viewed from above.

[0056] (2-2. Embodiment B) Referring to the partial longitudinal cross-sectional views shown in Figures 1B-1 and 1B-2, the semiconductor manufacturing equipment component 10B has a two-layer structure of a first ceramic substrate 20a and a second ceramic substrate 20b, whereas the ceramic substrate 20 in the semiconductor manufacturing equipment component 10A was composed of a single layer. More specifically, the semiconductor manufacturing equipment component 10B comprises a first ceramic substrate 20a bonded to the lower surface 73 of the ceramic plate 70, a first amorphous layer 80a present at the bonding interface between the ceramic plate 70 and the first ceramic substrate 20a, a second ceramic substrate 20b bonded to the lower surface 23a of the first ceramic substrate 20a, a second amorphous layer 80b present at the bonding interface between the first ceramic substrate 20a and the second ceramic substrate 20b, an electrostatic adsorption electrode 26a embedded in the ceramic plate 70, and a high-frequency electrode 26b positioned inside the ceramic plate 70 or between the ceramic plate 70 and the ceramic substrate 20. Furthermore, the semiconductor manufacturing equipment component 10B is located on the lower surface 23b side of the second ceramic substrate 20b and includes a base plate 30 that incorporates a refrigerant flow path 32. The ceramic substrate 20 and the base plate 30 can be joined via a bonding layer 40.

[0057] In Embodiment B, the ceramic plate 70 corresponds to the first ceramic portion described above, the first ceramic substrate 20a corresponds to the second ceramic portion described above, and the second ceramic substrate 20b corresponds to the third ceramic portion described above. Also, the first amorphous layer 80a corresponds to the first amorphous layer described above, and the second amorphous layer 80b corresponds to the second amorphous layer described above. Since the ceramic plate 70 has a smaller dielectric loss tangent (tanδ) than the ceramic substrate 20a, it can suppress heat generation when a high frequency is applied to the high-frequency electrode 26b.

[0058] Furthermore, in Embodiment B, as shown in Figure 1B-1, a refrigerant channel 28 through which refrigerant flows may be provided at a position on the first ceramic substrate 20a facing the second amorphous layer 80b and / or at a position on the second ceramic substrate 20b facing the second amorphous layer 80b. The refrigerant channel 28 can be formed, for example, in a single continuous line from one end (inlet) to the other end (outlet) across the entire wafer mounting surface in a plan view. A supply port and a recovery port of an external refrigerant device (not shown) can be connected to one end and the other end of the refrigerant channel 28, respectively. Refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant channel 28 passes through the refrigerant channel 28, returns to the recovery port of the external refrigerant device from the other end of the refrigerant channel 28, is temperature-adjusted, and can then be supplied again from the supply port to one end of the refrigerant channel 28.

[0059] Furthermore, in Embodiment B, as shown in Figure 1B-2, a gas channel 29 for supplying gas to the wafer mounting surface may be provided at a position on the first ceramic substrate 20a facing the second amorphous layer 80b and / or at a position on the second ceramic substrate 20b facing the second amorphous layer 80b. The gas channel 29 can be an annular channel in plan view that is concentric with the first ceramic substrate 20a. In this case, the semiconductor manufacturing apparatus member 10B may include a gas introduction passage 29a provided to communicate with the gas channel 29 from the lower surface of the base plate 30, and gas supply passages 29b that communicate with gas supply ports 74 provided on the reference surface 71b from multiple locations in the gas channel 29. The gas supplied to the gas channel 29 from the gas introduction passage 29a (for example, a thermal conductive gas such as He gas) is filled into the space on the lower side of the wafer W through the gas supply passage 29b. The filled gas improves heat conduction between the wafer W and the wafer mounting surface.

[0060] Of the reference numerals shown in Figures 1B-1 and 1B-2, those that are the same as those in Figures 1A and 2 are as described in the description of Embodiment A, so redundant explanations will be omitted.

[0061] <2. Method of using components for semiconductor manufacturing equipment> Next, a method for using a semiconductor manufacturing equipment component according to one embodiment of the present invention will be described using semiconductor manufacturing equipment component 10A as an example. First, the semiconductor manufacturing equipment component 10A is placed in a chamber (not shown). A focus ring is placed on the upper surface 27 of the semiconductor manufacturing equipment component 10A, and a disc-shaped wafer W is placed on the wafer mounting surface, that is, the upper surface 71a of the projection 72 and the upper surface 71c of the seal band 75. Then, the pressure inside the chamber is reduced using a vacuum pump to adjust to a predetermined vacuum level, and a voltage is applied to the electrode 26a to generate electrostatic adsorption force, thereby adsorbing and fixing the wafer W to the wafer mounting surface.

[0062] Next, process gas is supplied from a showerhead (not shown) to create a reaction gas atmosphere inside the chamber at a predetermined pressure (tens to hundreds of Pa). In this state, a high-frequency voltage such as an RF voltage is applied between an upper electrode (not shown) located on the ceiling of the chamber and the high-frequency electrode 26b of the semiconductor manufacturing equipment component 10A. Plasma is then generated between the wafer W and the showerhead. The wafer W is then processed using this plasma (such as performing CVD film deposition or etching).

[0063] Refrigerant circulates through the refrigerant flow path 32 of the base plate 30. A supply port and a recovery port of an external refrigerant device (not shown) are connected to one end and the other end of the refrigerant flow path 32 via refrigerant piping. Refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns to the recovery port of the external refrigerant device from the other end of the refrigerant flow path 32, is temperature-adjusted, and then supplied again from the supply port to one end of the refrigerant flow path 32.

[0064] A gas channel (not shown) is formed inside the base plate 30, allowing backside gas to be introduced from a gas cylinder (not shown). A thermal conductive gas (e.g., He gas) can be used as the backside gas. After passing through the gas channel inside the base plate 30, the backside gas flows out through the gas hole 50 and fills the space on the back side of the wafer W.

[0065] As the wafer W is plasma-treated, the focus ring also wears down. However, since the focus ring is thicker than the wafer W, it is replaced only after processing multiple wafers W.

[0066] The semiconductor manufacturing equipment component 10B can also be used in the same manner.

[0067] <3. Method for manufacturing components for semiconductor manufacturing equipment> Next, a method for manufacturing a semiconductor manufacturing apparatus component according to one embodiment of the present invention will be described using the semiconductor manufacturing apparatus component 10A shown in Figure 1A as an example, with reference to Figure 4. First, a disc-shaped ceramic sintered body 120, which will be the basis for the ceramic plate 70, and a disc-shaped ceramic sintered body 121, which will be the basis for the ceramic substrate 20, are each manufactured by hot-press sintering a molded body of ceramic powder (Figure 4A). The ceramic sintered body 120 has a smaller dielectric loss tangent (tanδ) than the ceramic sintered body 121. The molded body may be manufactured by stacking multiple tape molded bodies, by mold casting, or by compressing ceramic powder. The ceramic sintered body 120 contains electrodes 26a and 26b.

[0068] Next, the lower surface of the ceramic sintered body 120 and the upper surface of the ceramic sintered body 121 are polished to form a flat surface. There are no particular restrictions on the polishing method, but for example, lapping is preferred. The flat surface is preferably such that the surface roughness (arithmetic mean roughness) Ra, measured with a non-contact surface roughness meter in accordance with ISO 25178, is 1 nm or less (e.g., 0.2 to 1 nm).

[0069] For lapping, for example, the polishing apparatus 60 shown in Figure 6 can be used. The polishing apparatus 60 comprises a large-diameter, disc-shaped polishing platen 62 equipped with a polishing pad 64, a small-diameter, disc-shaped carrier 66, and a pipe 68 for supplying a slurry containing abrasive particles to the polishing pad 64. The polishing platen 62 has a shaft 67 at the center of its lower surface, and rotates axially (on its own axis) when the shaft 67 is rotated by a drive motor (not shown). The carrier 66 has a shaft 69 at the center of its upper surface, and rotates axially (on its own axis) when the shaft 69 is rotated by a drive motor (not shown). The carrier 66 is positioned offset from the center of the polishing platen 62.

[0070] To polish the underside of the ceramic sintered body 120 with this polishing device 60, the ceramic sintered body 120 is mounted on the underside of the carrier 66, and the ceramic sintered body 120 is sandwiched between the polishing pad 64 of the polishing platen 62 and the carrier 66 so that the underside of the ceramic sintered body 120 is in contact with the polishing pad 64. Then, a slurry containing abrasive particles is supplied to the polishing pad 64 from the pipe 68. As a result, slurry is supplied between the ceramic sintered body 120 and the polishing pad 64 of the polishing platen 62. In this state, the ceramic sintered body 120 is pressed against the polishing pad 64 by the carrier 66, and polishing is performed by rotating the polishing platen 62 and the carrier 66. Polishing forms an altered layer on the underside of the ceramic sintered body 120.

[0071] The upper surface of the ceramic sintered body 121 can also be lapped using the same method. Polishing forms an altered layer on the upper surface of the ceramic sintered body 121.

[0072] Next, the lower surface of the ceramic sintered body 120 and the upper surface of the ceramic sintered body 121 are subjected to surface activation treatment (fast atomic beam (FAB) or plasma activation treatment) under high vacuum. For example, the FAB conditions are set to a voltage of 0.5 to 2 kV, a current of 50 to 200 mA, and an irradiation time of 30 to 300 seconds. This removes oxides and adsorbed molecules from the lower surface of the ceramic sintered body 120 and the upper surface of the ceramic sintered body 121, and activates these surfaces by forming an amorphous layer. Then, while maintaining the high vacuum conditions, the two ceramic sintered bodies are stacked so that the lower surface of the ceramic sintered body 120 and the upper surface of the ceramic sintered body 121 face each other, and are directly joined under pressure, preferably at room temperature. The load during pressing can be set to, for example, 0.1 to 50 kN. This yields a ceramic joint 122 in which the ceramic sintered body 120 and the ceramic sintered body 121 are joined via an amorphous layer (Figure 4B).

[0073] Next, multiple protrusions 72 and sealing bands 75 are formed on the upper surface of the ceramic joint 122 by laser processing (Figure 4C). The timing of forming the multiple protrusions 72 and sealing bands 75 may be after the joining of the ceramic joint 122 and the base plate 30.

[0074] In parallel with this, two MMC disc members 131 and 136 are manufactured (Figure 4D). Then, a groove 132, which will ultimately become the refrigerant flow path 32, is formed on the lower surface of the upper MMC disc member 131 by machining (Figure 4E). A through hole 133 for refrigerant introduction and a through hole 134 for refrigerant discharge are made in the lower MMC disc member 136. If the ceramic sintered body 121 that constitutes the lower layer of the ceramic joint 122 is made of alumina, it is preferable that the MMC disc members 131 and 136 are made of SiSiCTi or AlSiC. This is because the thermal expansion coefficient of alumina is approximately the same as that of SiSiCTi or AlSiC.

[0075] A disc-shaped member made of SiSiCTi can be manufactured, for example, as follows: First, a powder mixture is prepared by mixing silicon carbide, metallic Si, and metallic Ti. Next, a disc-shaped molded body is formed from the obtained powder mixture by uniaxial pressure molding, and this molded body is hot-press sintered in an inert atmosphere to obtain a disc-shaped member made of SiSiCTi.

[0076] Next, a metal bonding material 135 is placed between the lower surface of the upper MMC disc member 131 and the upper surface of the lower MMC disc member 136, and a metal bonding material 137 is placed on the upper surface of the upper MMC disc member 131. Then, the ceramic bonded body 122 is placed on top of the metal bonding material 137 placed on the upper surface of the upper MMC disc member 131. This results in a laminated body 110 in which the lower MMC disc member 136 and metal bonding material 135, the upper MMC disc member 131 and metal bonding material 137, and the ceramic bonded body 122 are stacked in this order from bottom to top (Figure 4F). By heating and pressurizing this laminated body 110 (TCB), a bonded body is obtained. The bonded body is formed by joining the ceramic bonded body 122 to the upper surface of the MMC block 130, which will be the base plate 30, via a metal bonding layer. The MMC block 130 is formed by joining an upper MMC disc member 131 and a lower MMC disc member 136 via a metal bonding layer. The MMC block 130 has a refrigerant flow path 32, a refrigerant introduction section 36, and a refrigerant discharge section 38.

[0077] TCB (Temperature-Correcting Bonding) is performed, for example, as follows: The laminate is pressed and bonded at a temperature below the solidus temperature of the metal bonding material (for example, between 20°C below the solidus temperature and the solidus temperature), and then returned to room temperature. This causes the metal bonding material to become a metal bonding layer. As the metal bonding material, Al-Mg-based bonding materials or Al-Si-Mg-based bonding materials can be used. For example, when performing TCB using an Al-Si-Mg-based bonding material, the laminate is pressed while heated in a vacuum atmosphere. It is preferable to use a metal bonding material with a thickness of around 100 μm.

[0078] Next, the outer periphery of the ceramic bonded body 122 is machined to form a step, thereby creating a ceramic substrate 20 having a central portion 201 and an outer peripheral portion 202. This yields a semiconductor manufacturing equipment component 10A (Figure 4G).

[0079] Although the base plate 30 in Figure 1 is shown as a single piece, it may also be a structure in which two members are joined by a metal bonding layer, as shown in Figure 4G, or a structure in which three or more members are joined by a metal bonding layer. Furthermore, when the bonding layer 40 is formed using the metal bonding material 137, the insulating film 35 can be formed on the base plate 30 by thermal spraying either before or after bonding with the ceramic substrate 20. When the bonding layer 40 is formed using a resin adhesive sheet, the resin will melt, so the insulating film 35 is formed by thermal spraying before bonding with the ceramic bonded body 122.

[0080] The manufacturing method of the semiconductor manufacturing equipment component 10A shown in Figure 1A has been described exemplarily. When manufacturing the semiconductor manufacturing equipment component 10B shown in Figures 1B-1 and 1B-2, instead of the disc-shaped ceramic sintered body 121 that will become the ceramic substrate 20, a disc-shaped first ceramic sintered body that will become the first ceramic substrate 20a and a disc-shaped second ceramic sintered body that will become the second ceramic substrate 20b are prepared. Then, grooves that will become refrigerant passages 28 or gas passages 29 are formed in the first ceramic sintered body and / or the second ceramic sintered body by machining, and then the two are directly joined together in the procedure described above to produce a ceramic joint. Furthermore, through holes that will become gas supply passages 29b can be formed in the ceramic sintered body 120 and the ceramic joint by machining. Furthermore, during the manufacturing of the base plate 30, through holes that serve as gas introduction passages 29a can be formed in the upper MMC disc member 131 and the lower MMC disc member 136 by machining.

[0081] <4. Method for regenerating components for semiconductor manufacturing equipment> One embodiment of the present invention provides a method for regenerating components for semiconductor manufacturing equipment. Even if the quality of the components deteriorates due to detachment of ceramic particles constituting the protrusions on the wafer mounting surface of the semiconductor manufacturing equipment components, the components can be reused without being discarded by using this regeneration method. Several examples of the method for regenerating components for semiconductor manufacturing equipment according to the present invention will be described with reference to the drawings.

[0082] (4-1. Playback method A) A regeneration method A according to one embodiment of the present invention comprises a step 1 of processing the upper surface of a first ceramic portion of a semiconductor manufacturing apparatus component according to one embodiment of the present invention to form a processed surface on the first ceramic portion from which the wafer mounting surface has been removed, The process includes step 2, which involves further processing the aforementioned processed surface to form a new wafer mounting surface.

[0083] Referring to Figure 5A, for example, when the semiconductor manufacturing equipment component 10A shown in Figure 1A is regenerated by the regeneration method A, first, the upper surface 71 of the ceramic plate 70 is processed to form a processed surface 90 on the ceramic plate 70 from which the wafer mounting surface has been removed (step 1). There are no particular restrictions on the processing method, but grinding or polishing can be used as examples. Another processing method is blasting. By performing blasting after masking the reference surface 71b, the multiple protrusions 72 and seal bands 75 that constitute the wafer mounting surface can be selectively removed. In step 1, electrodes 26a and even electrodes 26b may be removed, but since this increases the effort required for regeneration, it is preferable not to remove any electrodes unless there is a special reason such as the purpose of providing electrodes with different specifications.

[0084] Next, multiple protrusions 72 and sealing bands 75 (wafer mounting surface) are formed on the processed surface 90 by laser processing or blast processing (step 2). The position, shape, and dimensions of the multiple protrusions 72 and sealing bands 75 (wafer mounting surface) may be the same as those of the semiconductor manufacturing equipment component 10A before reprocessing, but may be changed as appropriate.

[0085] Method A is advantageous because it allows for the simple regeneration of semiconductor manufacturing equipment components. It also offers the advantage of completely maintaining the material properties before and after regeneration. However, the thickness of the regenerated ceramic plate 70 is thinner than that of the original plate. Therefore, there is a limit to the number of regeneration cycles.

[0086] (4-2. Playback method B) A regeneration method B according to one embodiment of the present invention includes a step 1 of processing the upper surface of a first ceramic portion of a semiconductor manufacturing equipment component according to one embodiment of the present invention to form a processed surface on the first ceramic portion from which the wafer mounting surface has been removed, Step 2 involves directly bonding a regenerative ceramic part, which has a smaller dielectric loss tangent (tanδ) compared to the second ceramic part, to the processed surface. Includes.

[0087] Referring to Figure 5B, for example, when the semiconductor manufacturing equipment component 10A shown in Figure 1A is regenerated by the regeneration method B, first, the upper surface 71 of the ceramic plate 70 is processed to form a processed surface 90 on the ceramic plate 70 from which the wafer mounting surface has been removed (step 1). There are no particular restrictions on the processing method, but grinding or polishing can be used as examples. Other processing methods include blasting and laser processing. Blasting can also be performed by masking the reference surface 71b beforehand to selectively remove the multiple protrusions 72 and seal bands 75 that constitute the wafer mounting surface.

[0088] Next, the processed surface 90 of the ceramic plate 70 and the lower surface of the regenerated ceramic plate 79 are directly joined (preferably by room temperature joining) (step 2). The method of direct joining is as described above. For the regenerated ceramic plate 79, it is acceptable as long as the dielectric loss tangent (tanδ) is smaller than that of the ceramic substrate 20, but in order to reproduce the performance of the semiconductor manufacturing equipment component 10A, it is preferable that the regenerated ceramic plate 79 be made of the same material as the ceramic plate 70.

[0089] Prior to direct bonding, it is preferable to polish the machined surface 90 of the ceramic plate 70 and the lower surface of the recycled ceramic plate 79. There are no particular restrictions on the polishing method, but for example, lapping is preferred. It is preferable that the surface roughness (arithmetic mean roughness) Ra of the machined surface 90 of the ceramic plate 70 and the lower surface of the recycled ceramic plate 79, as measured by a non-contact surface roughness meter in accordance with ISO 25178 standard, is 1 nm or less (e.g., 0.2 to 1 nm).

[0090] Multiple protrusions 72 and sealing bands 75 (wafer mounting surface) can be formed on the upper surface of the refurbished ceramic plate 79 by laser processing before or after direct bonding. The position, shape, and dimensions of the multiple protrusions 72 and sealing bands 75 (wafer mounting surface) may be the same as those of the semiconductor manufacturing equipment component 10A before refurbishment, but may be changed as appropriate.

[0091] According to regeneration method B, since a regenerated ceramic plate 79 of a desired thickness can be used, it is possible to make the sum of the thicknesses of the ceramic plate 70 and the regenerated ceramic plate 79 in the semiconductor manufacturing equipment component 10A after regeneration match the thickness of the ceramic plate 70 before regeneration. For this reason, there is no particular limit on the number of regeneration cycles.

[0092] (4-3. Playback method C) A regeneration method C according to one embodiment of the present invention includes a step 1 of processing a first ceramic portion of a semiconductor manufacturing equipment component according to one embodiment of the present invention to remove it so that a second ceramic portion is exposed, and forming a processed surface on the second ceramic portion, Step 2 involves directly bonding a regenerative ceramic portion, which has a smaller dielectric loss tangent (tanδ) than the second ceramic portion, to the processed surface of the second ceramic portion. Includes.

[0093] Referring to Figure 5C, for example, when the semiconductor manufacturing equipment component 10A shown in Figure 1A is regenerated by the regeneration method C, the ceramic plate 70 is first processed and removed to expose the ceramic substrate 20. This creates a processed surface 90 on the ceramic substrate 20 (step 1). Step 1 also removes electrodes 26a and 26b. There are no particular restrictions on the processing method, but grinding or polishing are examples. Other processing methods include blasting and laser processing.

[0094] Next, the processed surface 90 of the ceramic substrate 20 and the lower surface of the regenerated ceramic plate 79 are directly joined (preferably by room temperature joining) (step 2). The method of direct joining is as described above. The regenerated ceramic plate 79 incorporates electrodes 26a and 26b. The electrodes 26a and 26b incorporated in the regenerated ceramic plate 79 can be the same specifications as the ceramic plate 70 before regeneration, or they may be of different specifications. It is acceptable for the regenerated ceramic plate 79 to have a smaller dielectric loss tangent (tanδ) than the ceramic substrate 20, but in order to reproduce the performance of the semiconductor manufacturing equipment component 10A, it is preferable that the regenerated ceramic plate 79 be made of the same material as the ceramic plate 70.

[0095] Prior to direct bonding, it is preferable to polish the processed surface 90 of the ceramic substrate 20 and the lower surface of the recycled ceramic plate 79. There are no particular restrictions on the polishing method, but for example, lapping is preferred. The processed surface 90 of the ceramic plate 70 and the lower surface of the recycled ceramic plate 79 preferably have a surface roughness (arithmetic mean roughness) Ra of 1 nm or less (e.g., 0.2 to 1 nm) as measured by a non-contact surface roughness meter in accordance with ISO 25178 standard.

[0096] Multiple protrusions 72 and sealing bands 75 (wafer mounting surface) can be formed on the upper surface of the refurbished ceramic plate 79 by laser processing before or after direct bonding. The position, shape, and dimensions of the multiple protrusions 72 and sealing bands 75 (wafer mounting surface) may be the same as those of the semiconductor manufacturing equipment component 10A before refurbishment, but may be changed as appropriate.

[0097] According to regeneration method C, since the ceramic plate 70 is completely removed from the semiconductor manufacturing equipment component 10A before regeneration, the ceramic plate 79 for regeneration does not need to be selected considering the material of the ceramic plate 70 in the semiconductor manufacturing equipment component 10A before regeneration. Therefore, the options for the ceramic plate 79 for regeneration can be increased. Accordingly, regeneration method C is advantageous when a semiconductor manufacturing equipment component with different performance from the semiconductor manufacturing equipment component 10A before regeneration is desired. [Explanation of Symbols]

[0098] 10A: Components for semiconductor manufacturing equipment 10B: Components for semiconductor manufacturing equipment 20: Ceramic substrate 20a: First ceramic substrate 20b: Second ceramic substrate 21:Top surface 23: Bottom surface 23a: Bottom surface 23b: Bottom surface 26a: Electrostatic adsorption electrode 26b: High-frequency electrode 27:Top surface 28: Refrigerant flow path 29: Gas flow path 29a: Gas introduction path 29b: Gas supply route 30: Base plate 31:Top surface 32: Refrigerant flow path 35: Insulating film 36: Refrigerant inlet 38: Refrigerant discharge part 40: Bonding layer 50: Gas hole 55: Plug 60: Polishing equipment 62: Polishing surface plate 64: Polishing pad 66: Career 67: Shaft 68: Pipe 69: Shaft 70: Ceramic plate 71:Top surface 71a:Top surface 71b: Reference plane 71c:Top surface 72: Protrusion 73: Bottom surface 74: Gas supply port 75: Seal Band 79: Reusable ceramic plate 80: Amorphous layer 80a: First amorphous layer 80b: Second amorphous layer 90: Machining surface 110: Laminate 120: Ceramic sintered body 121: Ceramic sintered body 122: Ceramic joint 130: MMC Block 131:MMC disc member 132: Groove 133: Through hole 134: Through hole 135: Metal bonding material 136:MMC disk member 137:Metal bonding material 201: Central part 202: Outer perimeter

Claims

1. A semiconductor manufacturing apparatus component comprising: a first ceramic portion having an upper surface on which a wafer is mounted and a lower surface located opposite to the upper surface; a second ceramic portion bonded to the lower surface of the first ceramic portion; a first amorphous layer present at the bonding interface between the first ceramic portion and the second ceramic portion; and a high-frequency electrode disposed inside the first ceramic portion or between the first ceramic portion and the second ceramic portion, wherein the first ceramic portion has a smaller dielectric loss tangent (tanδ) than the second ceramic portion.

2. The dielectric loss tangent (tanδ) of the first ceramic part at a measurement frequency of 1 MHz is 1 × 10⁻¹⁰. -3 The semiconductor manufacturing apparatus component according to claim 1, which is as follows:

3. The semiconductor manufacturing apparatus component according to claim 1 or 2, wherein the first ceramic portion is a plate having a plurality of protrusions on its upper surface that have the wafer mounting surface.

4. The semiconductor manufacturing apparatus component according to claim 1 or 2, wherein the second ceramic portion has a higher thermal conductivity than the first ceramic portion.

5. A semiconductor manufacturing apparatus component according to claim 1 or 2, The first altered layer located on the side of the first ceramic portion that is in contact with the first amorphous layer, The second altered layer located on the side of the second ceramic portion that is in contact with the first amorphous layer, A component for semiconductor manufacturing equipment, equipped with the following features.

6. A semiconductor manufacturing apparatus component according to claim 1 or 2, A third ceramic part is bonded to the lower surface of the second ceramic part, A second amorphous layer present at the bonding interface between the second ceramic portion and the third ceramic portion, A component for semiconductor manufacturing equipment, equipped with the following features.

7. A refrigerant channel through which a refrigerant flows or a gas channel for supplying gas to the wafer mounting surface is provided in the second ceramic portion facing the second amorphous layer or in the third ceramic portion facing the second amorphous layer. The semiconductor manufacturing apparatus component according to claim 6.

8. A semiconductor manufacturing apparatus component according to claim 6, The third altered layer located on the side of the second ceramic portion that is in contact with the second amorphous layer, The fourth altered layer located on the side of the third ceramic portion that is in contact with the second amorphous layer, A component for semiconductor manufacturing equipment, equipped with the following features.

9. A step of processing the upper surface of the first ceramic portion of the semiconductor manufacturing apparatus member according to claim 1 to form a processed surface on the first ceramic portion from which the wafer mounting surface has been removed, A method for regenerating a component for semiconductor manufacturing equipment, comprising the step of further processing the aforementioned processed surface to form a new wafer mounting surface.

10. A step of processing the upper surface of the first ceramic portion of the semiconductor manufacturing apparatus member according to claim 1 to form a processed surface on the first ceramic portion from which the wafer mounting surface has been removed, A step of directly bonding a regenerative ceramic portion having a smaller dielectric loss tangent (tanδ) than the second ceramic portion to the processed surface, A method for regenerating semiconductor manufacturing equipment components, including those mentioned above.

11. A step of processing the first ceramic portion of the semiconductor manufacturing apparatus member according to claim 1, removing it so that the second ceramic portion is exposed, and forming a processed surface on the second ceramic portion, A step of directly bonding a regenerative ceramic portion having a smaller dielectric loss tangent (tanδ) than the second ceramic portion to the processed surface of the second ceramic portion, A method for regenerating semiconductor manufacturing equipment components, including those mentioned above.

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