Power supply architecture for high-power portable devices

Abstract

To provide a power delivery architecture for high power portable devices.SOLUTION: A power architecture uses an efficient intermediate power conversion stage between an AC adaptor (and battery charger) and subsequent voltage regulators (VRs) (e.g., core VR) for processors for higher overall efficiency allowing for higher performance in a given thermal envelope and iso-system input power. Power losses from both the charger and the core VR are reduced by splitting the power as power to sustained high-power rails, and power to the rest of the platform power rails that have low residency in high-power states. The sustained high-power rails are placed under an intermediate power conversion topology which is directly powered by the adaptor. The rest of the rails along with charging of the battery are powered by the battery charger.SELECTED DRAWING: Figure 1A

Description

Background Art

[0001] For example, the power requirements for high-performance portable devices such as creator laptops and gaming laptops are increasing ever higher. The power supply design in such systems depends on the selected battery configuration and charger architecture. The battery configuration in such systems is usually either 3S (9V - 13.2V) or 4S (12V - 17.6V) based on state-of-the-art LiCoO2 chemistry, but can vary up to and including voltages similar to or higher than those shown. The charger architecture can follow either the battery voltage (here, NVDC) or a hybrid-power buck-boost (here, HPBB) architecture.

Brief Description of the Drawings

[0002] The disclosed embodiments will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which should not be construed as limiting the disclosure to the specific embodiments, but are for illustration and understanding only. [Figure 1A] Illustrates a power supply architecture for a portable device according to some embodiments. [Figure 1B] Illustrates a power supply architecture for a portable device having an isolation transistor according to some embodiments. [Figure 1C] Illustrates a schematic diagram of a power supply architecture for a portable device according to some embodiments. [Figure 2A] Figures 2A - 2B illustrate plots showing efficiency and absolute power loss in AC mode in a comparison between a traditional high-power buck-boost (HPBB) converter architecture and a proposed power supply architecture for a portable device according to some embodiments. [Figure 2B]Figures 2A-2B illustrate plots showing efficiency and absolute power loss in AC mode, comparing a traditional high-power buck-boost (HPBB) converter architecture with a proposed power supply architecture for portable devices, according to some embodiments. [Figure 3A] Figures 3A-3B illustrate plots showing efficiency and absolute power loss in DC mode, comparing a traditional high-power buck-boost (HPBB) converter architecture with a proposed power supply architecture for portable devices, according to some embodiments. [Figure 3B] Figures 3A-3B illustrate plots showing efficiency and absolute power loss in DC mode, comparing a traditional high-power buck-boost (HPBB) converter architecture with a proposed power supply architecture for portable devices, according to some embodiments. [Figure 4A] Figures 4A-4B illustrate plots showing efficiency and absolute power loss in AC mode, comparing a traditional NVDC battery power architecture with a proposed power supply architecture for portable devices, according to some embodiments. [Figure 4B] Figures 4A-4B illustrate plots showing efficiency and absolute power loss in AC mode, comparing a traditional NVDC battery power architecture with a proposed power supply architecture for portable devices, according to some embodiments. [Figure 5A] Figures 5A-5B illustrate plots showing efficiency and absolute power loss in DC mode, comparing a traditional NVDC battery power architecture with a proposed power supply architecture for portable devices, according to some embodiments. [Figure 5B] Figures 5A-5B illustrate plots showing efficiency and absolute power loss in DC mode, comparing a traditional NVDC battery power architecture with a proposed power supply architecture for portable devices, according to some embodiments. [Figure 6]This illustrates a system-on-a-chip (SoC) powered by a power supply system according to certain embodiments. [Modes for carrying out the invention]

[0003] Existing PD architectures are designed for either low or high system power. Low system power designs are suited to portable devices such as phones and tablets, where the system voltage is the battery voltage (NVDC), which requires all power to be delivered through a charger, resulting in a larger charger area with a larger inductor and double conversion losses. High system power designs are used for portable devices such as gaming laptops and creative devices, which are systems that normally operate on AC power (e.g., an adapter connected to a wall socket) but are powered by battery for short periods. High system power designs require the high-voltage adapter input to be supplied directly to the downstream VR (HPBB), and when designed for higher efficiency, they incur higher real estate, height, and / or bill-of-materials (BOM) costs, while lower efficiency occurs if the VR is at a higher operating frequency to optimize for real estate, height, and / or BOM.

[0004] Both NVDC and HPBB architectures have certain advantages and disadvantages. In the NVDC architecture, the input voltage to the core rail that powers the system-on-chip (SOC) is 2S, 3S, or higher, so the operating switching frequency (f) selected for the VR is necessary to meet thermal requirements. opIt is expected that the frequency (e.g., 500kHz-700kHz) will be lowered. For core VR design, this results in a larger inductor size, larger output capacitance, and larger core area. The charging inductor will be larger because the entire downstream load and battery are supported by power from the charger. When in adapter mode, all VRs suffer double conversion power losses. In the case of HPBB architecture, the input voltage to the core rail (e.g., power rail to the SoC and other high-performance integrated circuits) can be as high as the 20V adapter voltage, so it is expected that the operating frequency selected for the VR will be even lower (e.g., 300kHz-400kHz) to ensure acceptable efficiency in power conversion. However, only the battery receives the power-converted output, and the rest of the system receives 20V through a bypass path. Therefore, the inductor size, output capacitance, and core area of ​​downstream VRs will be even larger. Also, the power available to downstream VRs is limited by the size of the adapter, while the size of the charger inductor for the battery charging path is reduced. The total power available in an NVDC architecture (battery-based power architecture) is lower than that available in an HPBB architecture (hybrid voltage power adapter-based power architecture), even when considering a barrel connector adapter (due to power loss in the charger). When the requirements for compact board design and reduced power loss must be met, efficiency in power conversion is compromised regardless of whether an NVDC or HPBB is used.

[0005] Some embodiments disclose a power architecture that uses the best of NVDC architecture and HPBB, along with an efficient intermediate power conversion stage between the AC adapter (and battery charger) and the subsequent processor voltage regulator (VR) (e.g., core VR) for higher overall efficiency, enabling higher performance with a given thermal envelope and isosystem input power. Power losses from both the charger and the core VR are reduced by dividing the power into a) power to a power rail that is continuously high-power and b) power to the remaining power rail that is not in a high-power state. In some embodiments, the power rail that is continuously high-power is placed under an intermediate power conversion topology that is directly powered by the adapter in AC mode and powered by the battery in DC mode. According to some embodiments, the remaining rail is powered by the power conversion output of the charger, which is at battery voltage in AC mode, and powered by the battery in DC mode, along with charging the battery.

[0006] Numerous technical benefits exist for various embodiments. For example, the power architecture enables higher efficiency with respect to isosystem performance, and smaller real estate and lower z-height for downstream solutions. The power architecture in some embodiments results in lower thermal losses for continuously high-power VR rails. The new architecture results in higher Tau for power level 2 (PL2) under the same thermal constraints due to lower losses in preceding sustained power states (e.g., preceding PL2 events). The power architecture results in a better customer experience with higher performance due to a higher thermal budget available to the SoC under the same thermal envelope. The availability of z-height and real estate in the core region can potentially be used to provide a better thermal solution that will enable higher performance within the limits of previous system constraints. For example, the reduction in z-height and real estate may enable a more compact system design. By using an intermediate regulator to divide the power across the aforementioned power rails, and by supplying the remaining rail with narrow-voltage power output from the charger, battery charging becomes faster, thus improving the user experience. The size of the inductors and capacitors for the downstream core VR is smaller in this new architecture (compared to HPBB), resulting in a smaller real estate and even lower losses due to power reduction, ultimately leading to better overall efficiency. Other technical effects become apparent from various figures and embodiments.

[0007] The following description details numerous details in order to provide a more complete description of the embodiments of the disclosure. However, as will be apparent to those skilled in the art, the embodiments of the disclosure can be carried out without these specific details. Also, to avoid obscuring the embodiments of the disclosure, well-known structures and devices are shown in block diagrams rather than in detail.

[0008] In the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more constituent signal paths and / or may have arrows at one or both ends to indicate the main direction of information flow. Such indications are not intended to be limiting; rather, they are used to facilitate understanding of the circuit or logic unit in relation to one or more exemplary embodiments. The signals represented are determined by the needs or preferences of the design and may actually consist of one or more signals that can travel in any direction and may be implemented in any preferred type of signal scheme.

[0009] Figure 1A illustrates a power supply architecture 100 for a portable device according to some embodiments. The architecture 100 comprises, coupled as shown, a battery charger 101, an adapter 102 (e.g., an AC adapter, a Universal Serial Bus (USB) Type-C power connector, etc.), a plug 103 (e.g., for powering the adapter), a battery 104 (e.g., 2S1P, 3S1P, 3S2P, 4S1P, etc.), a bypass path circuit 105, a battery field-effect transistor (BatFET), an intermediate voltage regulator (VR) 106, split rails Vin1 and Vin2, and a processor (e.g., a central processing unit (CPU) core V The platform comprises R107 and associated core load 108, graphics processor (e.g., dGFx) core VR109 and associated load 110, and the rest of the platform 111 (e.g., peripheral components including a display, sensors, cameras, microphones, etc.). In some embodiments, an additional intermediate VR (e.g., VR106a coupled to a subsequent VR107a) can be coupled to the supply rail Vin1. The battery 104 can be any series-configured battery cells (e.g., 3S1P, 3S2P, 4S1P, etc.).

[0010] The Hybrid Power Back Boost (HPBB) architecture is used in most high-power systems (e.g., a 118W PL2 with a main SoC at 45W thermal design power (TDP) and a dGfx at 80W total graphics power (TGP)). The main advantage of HPBB is that the charger inductor is simply sized for battery charging and therefore occupies a smaller volume compared to the NVDC architecture. In the HPBB architecture, the system is powered directly from adapter 102 in AC mode and directly from battery 104 in DC mode. One drawback of the HPBB architecture is that all downstream VRs 107, 109, the remaining VRs on platform 111, VR 106a etc. (assuming VR 106 is absent and Vin1 is shorted to Vin2) must be designed to match the maximum adapter voltage (e.g., 20V), which increases the z height, real estate, and BOM cost in the downstream VR implementation due to the low operating frequency while maintaining high efficiency. In HPBB, the frequency selection for VR operation is based on the following trade-off: lower frequencies reduce switching losses but lead to larger inductance and output capacitance Cout, increasing z height, real estate, and BOM cost. Poor transient response due to lower duty cycles can impair SoC performance, requiring higher capacitance to compensate. An alternative trade-off is that higher frequencies help reduce real estate, z height, and BOM cost, but result in lower efficiency and more heat (wasted energy) due to higher crossover losses in the MOSFET when operating at high input voltages (20V).

[0011] In some embodiments, the remaining power rails are powered by legacy NVDC outputs, while an intermediate stage converter or VR106 is added for the sustained high-power rail. Powering different rails differently reduces overall losses compared to the HPBB architecture. In some embodiments, the intermediate stage converter or VR106 is a switch-capacitor VR (SCVR) or a hybrid SCVR, or any other high-efficiency (e.g., above 85%) power conversion topology (e.g., a resonant converter). For example, the SCVR can be replaced with a multilevel converter (MLC). In some embodiments, the SCVR has no inductor and therefore does not add a large area. In some embodiments, the hybrid SCVR has an inductor, but thanks to the topology, it does not add a large area. The input to VR106 is Vin1, which is generated by adapter 102 or from battery 104, depending on the operating mode, which is AC mode or DC mode. Here, the reference names of the nodes and the signals on those nodes are used interchangeably. For example, depending on the context, Vin1 may refer to a voltage on a node or supply rail Vin1, or it may refer to a Vin1 power rail. In various embodiments, power from adapter 102 goes to the Vin supply rail via two possible paths, which are a first path and a second path.

[0012] The first path passes through a bypass path, where a transistor in the bypass path circuit 105 is turned on to bypass the battery charger 101. The power supplied from the adapter 102 is then downconverted to a lower voltage by VR 106 and supplied to the sustained high-power rail as Vin2. Vin2 is then converted to Vout1, Vout2, and other possible output voltages for various loads, such as the CPU core load 108 and the graphics core load 110. The second path from the adapter 102 supplies power to the remaining rails (e.g., the rest of the platform 111) after being buckconverted to charge the battery 104.

[0013] In various embodiments, a sustained high-power rail is a power rail provided for a VR that powers a processor or CPU, including a graphics processor, which has an end-use where the load is expected to be very likely to be in a high-power state (e.g., a C0 state as defined by the ACPI specification). Conversely, a non-sustained high-power rail is a rail provided for any VR that powers the rest of the platform or for parts of the SoC that are more likely to be in a low-power state (e.g., an idle or sleep state). In some embodiments, some sustained high-power rails may require a different power source than that provided by VR106. In one such case, a VR106a is provided that powers another VR107a, which in turn powers another processor.

[0014] Figure 1B illustrates a power supply architecture 120 for a portable device having an isolated transistor, according to one embodiment. Architecture 120 is similar to architecture 100, except for the isolated FET (iFET). The iFET is coupled to the supply rail Vin1 and BatFET to separate the power path for VR106 from the power path for the rest of the platform 111.

[0015] Figure 1C illustrates a schematic diagram 130 of a power supply architecture for a portable device according to some embodiments. Here, two possible power sources are shown, including an AC adapter 102 and a USB Type-C power supply 122. However, many suitable power sources, including USB mini-B or micro-B, can be used. In various embodiments, the battery charger 101 includes a buck converter having a high-side n-type switch MN1 and a low-side n-type switch MN2 coupled in series. In some embodiments, the battery charger 101 may support buck-boost operation by including two sets of switches: MN1 and MN1A (not shown) for the high-side n-type switches and MN2 and MN2A (not shown) as low-side n-type switches. In one example, transistor MN2A is coupled in series with MN1, and transistor MN2A is coupled in series with MN2. Input power to the charger is supplied by the AC adapter 102 or an alternative power source (e.g., USB Type-C power supply 122). A common coupling node for switches MN1 and MN2 is coupled to an inductor L, which is coupled to a load capacitor C1 on node V1. The output of inductor L is coupled to a BatFET via a battery current sensor. The BatFET is controlled by a controller. The battery is connected to this BatFET. An isolation FET (isoFET) is coupled to the Vin1 supply rail and the V1 node. The V1 node provides power to the rest of the platform 111. In various embodiments, the isoFET is controlled by a controller. In some embodiments, the isoFET is turned off to isolate or isolate the Vin1 rail from the V1 rail. Currents through the buck converter driver (e.g., high-side and low-side switches) and the BatFET are sensed via a sensor (e.g., series impedance) and provided to the controller. The controller also senses voltage V1 to control the turn-on and turn-off times of switches MN1 and MN2.

[0016] In various embodiments, power from adapter 102 (i.e., AC mode) passes through two possible paths, which are a first path and a second path. The first path passes through a bypass path, where a transistor in the bypass path circuit 105 is turned on to bypass the battery charger 101. The supply from adapter 102 is then downconverted to a lower voltage by VR 106 and supplied to the sustained rail as Vin2. Vin2 is then converted to Vout1, Vout2, and other possible output voltages for various loads, such as the CPU core load 108 and the graphics core load 110. The second path from adapter 102 supplies power to the remaining rail (e.g., the rest of the platform 111) via a buck conversion to charge the battery 104. The buck conversion is performed by a controller and a buck converter having switches MN1 and MN2, an inductor L, and a capacitor C1.

[0017] In some embodiments, VR106 is a 2:1 SCVR with very high efficiency (e.g., above 98%) and can be used to downconvert either the adapter voltage or the 4S battery voltage to a sustained high-power rail input downstream (Vin2). Various embodiments will be described with reference to the SCVR, but the SCVR can be replaced with a multilevel converter (MLC). In some embodiments, in adapter (AC) mode, the SCVR receives an input of approximately 20V from adapter 102, and assuming a conversion ratio of 2:1 but not limited to this, it downconverts to a 10V input to subsequent VRs (e.g., VR107 and / or VR109). In this approach, the power supply architectures of various embodiments have the following advantages compared to the HPBB architecture: Subsequent VRs (e.g., VR107 and / or VR109) can be designed to match higher frequencies without affecting overall efficiency, which helps reduce real estate and provides greater flexibility in placement (by removing some capacitors). Subsequent VRs (e.g., VR107 and / or VR109) can be designed to match higher frequencies without affecting overall efficiency, which helps reduce z height (from approximately 3mm to potentially 1.2mm) and also lowers BOM costs due to reduced capacitors. In this improved power supply architecture, thermal hotspots are distributed between the charger subsystem, SCVR subsystem, and core rails beneath the SCVR, when considering iso-efficiency. In some embodiments of the improved power supply architecture, the charger inductor L is smaller in size than those for battery charging and the rest of the rails. Furthermore, the design capability for the Vin / 2 maximum value eases expectations for various components.

[0018] Figures 2A-2B illustrate plots 200 and 220 showing efficiency and absolute power loss in AC mode in a comparison between a traditional hybrid power back boost (HPBB) converter architecture and a proposed power supply architecture for a portable device according to some embodiments. The efficiency of VR107 and / or 109 is improved by the new power supply architecture having VR106. For example, the efficiency of VR107 and 109 increases by 10% over HPBB at the same operating frequency of 1300 kHz. Even at a typical lower operating frequency of 800 kHz for VR107 and / or 109, the new power supply architecture having VR106 has a higher (e.g., 3%) efficiency compared to HPBB.

[0019] Figures  3A-3B illustrate plots 300 and 320 showing efficiency and absolute power loss in DC mode in a comparison between a traditional HPBB converter architecture and a proposed power supply architecture for a portable device according to some embodiments. In DC mode (where adapter 102 is disconnected), SCVR106 receives the 4S battery voltage and down-converts it to +VBATA / 2 for supply to the inputs of VR107 and / or 109. Analysis shows that the new power supply architecture having SCVR106 has lower losses (SCVR106 plus VR107) compared to directly supplying the 4S voltage to VR107 and 109. The new power supply architecture having SCVR106 shows an efficiency improvement of up to 6% compared to the HPBB power architecture. The new power supply architecture has overall even less loss as the 4S voltage is halved before being supplied to VR107 and / or 109 compared to directly supplying the 4S voltage to VR107 and / or 109 in the HPBB power supply architecture. Even at a typical lower operating frequency of 800 kHz for VR107 and / or 109, the new power supply architecture has a 3% efficiency improvement while operating the downstream VR107 and / or 109 at 1300 kHz.

[0020] Figures 4A-4B illustrate plots 400 and 420, respectively, showing efficiency and absolute power loss in AC mode, comparing a traditional battery power architecture (NVDC architecture using a 4S battery configuration) with a power supply architecture for portable devices according to some embodiments. The same implementation as in the HPBB architecture described here is used (e.g., a 118W PL2 with a main SoC at 45W TDP and a dGfx at 80W TGP). In the NVDC architecture, the charger receives the adapter input voltage, converts it down to the battery voltage, and supplies that power to both the battery and the system. One drawback of the NVDC architecture is that the charger inductor L and MOSFETs MN1 and MN2 are sized to match the total system power plus the battery charging power. Therefore, the inductors have higher z and larger real estate. Also, during AC mode, overall losses are higher due to the double conversion of adapter power. The analysis shows that the new power supply architecture has lower overall power loss compared to the NVDC architecture and solves the z-height challenge in charger inductor selection. The plots here show that the efficiency of VR107 and 109 in the new architecture is approximately 8% more efficient than NVDC at the same operating frequency of 1300kHz for VR107 and 109. Even at the typical lower operating frequency of 800kHz for VR107 and 109, the new architecture shows a 6% efficiency improvement when the downstream VR107 and 109 are operating at 1300kHz.

[0021] Figures 5A-5B illustrate plots 500 and 520 showing efficiency and absolute power loss in DC mode, respectively, in a comparison between a traditional battery power architecture (NVDC architecture) and a power supply architecture for portable devices according to some embodiments. The new architecture shows that VR107 and 109 have an efficiency improvement of about 6.1% over NVDC at the same operating frequency of 1300 kHz. Even at a typical lower operating frequency of 800 kHz for VR107 and 109, there is a 2.5% efficiency improvement in the new architecture while operating the downstream VR107 and 109 at 1300 kHz.

[0022] Table 1 shows a comparison of area and z-height for charger implementation in the new architecture and the NVDC architecture.

Table 1

[0023] From Table 1, the charger section benefits from the new architecture in terms of both real estate (165 mm vs. 284 mm 2 and Z-height (3.1 mm vs. 4 mm). 2 )

[0024] Figure 6 illustrates a system-on-chip (SoC) powered by a power supply system according to some embodiments. It should be noted that elements of Figure 6 having the same reference numerals (or names) as elements in other figures can operate or function in a similar manner as described, but are not so limited. In some embodiments, the voltage regulator of the SoC is powered by VR106.

[0025] In some embodiments, the device 5500 represents a suitable computing device, such as a computing tablet, mobile phone or smartphone, laptop, desktop, Internet of Things (IoT) device, server, wearable device, set-top box, wireless e-reader, or similar. It is understood that certain components are shown schematically, and not all components of such a device are shown in the device 5500.

[0026] In one example, the device 5500 has a System-on-a-Chip (SoC) 5501. An example of the boundaries of the SoC 5501 is shown in Figure 6 using dotted lines, and while some examples of components are shown to be included within the SoC 5501, the SoC 5501 may include any suitable components of the device 5500.

[0027] In some embodiments, the device 5500 includes a processor 5504. The processor 5504 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, processing core, or other processing implementations, such as a disaggregated combination of multiple compute, graphics, accelerator, I / O, and / or other processing chips. The processing operations performed by the processor 5504 include the execution of an operating platform or operating system on which applications and / or device functions are run. These processing operations include operations related to I / O (input / output) with human users or other devices, operations related to power management, operations related to connecting the computing device 5500 to other devices, and / or similar operations. These processing operations may also include operations related to audio I / O and / or display I / O.

[0028] In some embodiments, the processor 5504 includes a plurality of processing cores (also referred to as cores) 5508a, 5508b, and 5508c. Although Figure 6 simply shows three cores 5508a, 5508b, and 5508c, the processor 5504 may include any other preferred number of processing cores, such as tens or hundreds of processing cores. The processor cores 5508a, 5508b, and 5508c may be implemented on a single integrated circuit (IC) chip. Furthermore, that chip may include one or more shared caches and / or private caches, buses or interconnects, graphics controllers and / or memory controllers, or other components.

[0029] In some embodiments, the processor 5504 includes a cache 5506. In one example, sections of the cache 5506 may be dedicated to individual cores 5508 (for example, a first section of the cache 5506 may be dedicated to core 5508a, a second section of the cache 5506 may be dedicated to core 5508b, and so on). In one example, one or more sections of the cache 5506 may be shared among two or more of the cores 5508. The cache 5506 may be divided into different hierarchies, such as a Level 1 (L1) cache, a Level 2 (L2) cache, a Level 3 (L3) cache, and so on.

[0030] In some embodiments, the processor core 5504 may include a fetch unit that fetches instructions (including instructions with conditional branches) for execution by the core 5504. Instructions may be fetched from any storage device, such as memory 5530. The processor core 5504 may also include a decode unit that decodes the fetched instructions. For example, the decode unit may decode the fetched instructions into a number of microoperations. The processor core 5504 may also include a schedule unit that performs various operations associated with storing the decoded instructions. For example, the schedule unit may hold data from the decode unit until the instructions are ready for dispatch (for example, until all source values ​​of the decoded instructions are available). In one embodiment, the schedule unit may schedule and / or issue (or dispatch) the decoded instructions to an execution unit for execution.

[0031] An execution unit may execute dispatched instructions that have been decoded (e.g., by a decoding unit) and dispatched (e.g., by a scheduling unit). In one embodiment, an execution unit may include two or more execution units (e.g., an imaging calculation unit, a graphics calculation unit, a general-purpose calculation unit, etc.). An execution unit may also include one or more arithmetic logic units (ALUs), and may perform various arithmetic operations such as addition, subtraction, multiplication, and / or division. In one embodiment, a coprocessor (not shown) may perform various arithmetic operations together with the execution unit.

[0032] Furthermore, the execution unit may issue instructions in no particular order. Thus, in one embodiment, the processor core 5504 may be an out-of-order processor core. The processor core 5504 may also include a retirement unit. The retirement unit may reclaim executed instructions after they have been committed. In one embodiment, the reclaiming of executed instructions may result in the processor state being committed from the execution of the instructions, and the physical registers used by the instructions being deallocated. The processor core 5504 may also include a bus unit that enables communication between components of the processor core 5504 and other components via one or more buses. The processor core 5504 may also include one or more registers that store data accessed by various components of the core 5504 (e.g., values ​​related to assigned application priorities and / or subsystem state (mode) associations).

[0033] In some embodiments, the device 5500 includes a connection circuit 5531. For example, the connection circuit 5531 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and / or software components (e.g., drivers, protocol stacks) that enable the device 5500 to communicate with external devices. The device 5500 may be isolated from external devices such as other computing devices, wireless access points, or base stations.

[0034] In one example, connection circuit 5531 may include several different types of connections. Generally speaking, connection circuit 5531 may include cellular connection circuits, wireless connection circuits, etc. The cellular connection circuit of connection circuit 5531 generally refers to cellular network connections provided by wireless communication carriers, such as GSM (global system for mobile communications) or its variations or derivatives, CDMA (code division multiplexing) or its variations or derivatives, TDM (time division multiplexing) or its variations or derivatives, the 3rd Generation Partnership Project (3GPP) UMTS (Universal Mobile Telecommunications Systems) system or its variations or derivatives, the 3GPP Long-Term Evolution (LTE) system or its variations or derivatives, the 3GPP LTE Advanced (LTE-A) system or its variations or derivatives, the 5th generation (5G) wireless system or its variations or derivatives, the 5G mobile network system or its variations or derivatives, the 5G New Radio (NR) system or its variations or derivatives, or those provided via other cellular service standards. The wireless connection circuit (or wireless interface) of connection circuit 5531 refers to a non-cellular wireless connection and may include personal area networks (e.g., Bluetooth®, near-field, etc.), local area networks (e.g., Wi-Fi, etc.), and / or wide area networks (e.g., WiMAX, etc.), and / or other wireless communications. In one example, connection circuit 5531 may include a network interface, such as a wired or wireless interface, so that the system embodiment can be incorporated into a wireless device such as a mobile phone or personal digital assistant.

[0035] In some embodiments, the device 5500 includes a control hub 5532 which represents hardware devices and / or software components involved in interaction with one or more I / O devices. For example, the processor 5504 may communicate with one or more of the following via the control hub 5532: a display 5522, one or more peripheral devices 5524, a storage device 5528, one or more other external devices 5529, etc. The control hub 5532 may be a chipset, a platform control hub (PCH), and / or similar.

[0036] For example, the control hub 5532 illustrates one or more connection points for additional devices connected to the device 5500, through which, for example, a user can interact with the system. For example, devices that can be attached to the device 5500 (e.g., device 5529) include microphone devices, speakers or stereo systems, audio devices, video systems or other display devices, keyboards or keypad devices, or other I / O devices used in a particular application, such as card readers or other devices.

[0037] As described above, the control hub 5532 can interact with audio devices, displays 5522, and the like. For example, input via a microphone or other audio device can provide input or commands for one or more applications or functions of the device 5500. Furthermore, it can provide audio output in place of, or in addition to, display output. In another example, if the display 5522 includes a touchscreen, the display 5522 also functions as an input device which can be managed at least partially by the control hub 5532. The computing device 5500 may also have additional buttons or switches to provide I / O functions managed by the control hub 5532. In one embodiment, the control hub 5532 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware which may be included in the device 5500. Inputs can be part of direct user interaction and can also provide environmental input to the system to influence its operation (e.g., noise filtering, display adjustment for brightness detection, flash application for cameras, or other mechanisms).

[0038] In some embodiments, the control hub 5532 can be coupled to various devices using any suitable communication protocol, such as PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, High Definition Multimedia Interface (HDMI®), FireWire, etc.

[0039] In some embodiments, the display 5522 represents hardware (e.g., display device) and software (e.g., driver) components that provide a visual and / or haptic display for the user to interact with the device 5500. The display 5522 may include a display interface, a display screen, and / or hardware devices used to provide a display to the user. In some embodiments, the display 5522 includes a touchscreen (or touchpad) device that provides both output and input to the user. In one example, the display 5522 may communicate directly with the processor 5504. The display 5522 may be one or more of an internal display, such as in a mobile electronics device or laptop device, or an external display device attached via a display interface (e.g., DisplayPort). In one embodiment, the display 5522 may be a head-mounted display (HMD), such as a stereoscopic display used in a virtual reality (VR) or augmented reality (AR) application.

[0040] In some embodiments, although not shown in the figures, in addition to (or instead of) the processor 5504, the device 5500 may include a graphics processing unit (GPU) which includes one or more graphics processing cores capable of controlling one or more modes of displaying content on the display 5522.

[0041] The control hub 5532 (or platform controller hub) may include hardware interfaces and connectors, and software components (e.g., drivers, protocol stacks) for making peripheral connections to peripheral devices such as the peripheral device 5524.

[0042] It should be understood that device 5500 may be a peripheral device to other computing devices, or may have peripheral devices connected to it. Device 5500 may have a “docking” connector for connecting to other computing devices for purposes such as managing content on device 5500 (e.g., downloading and / or uploading, modifying, synchronizing). In addition, the docking connector may allow device 5500 to connect to certain peripheral devices that enable computing device 5500 to control content output to, for example, an audiovisual system or other systems.

[0043] In addition to a dedicated docking connector or other dedicated connection hardware, the device 5500 can make peripheral connections via common or standard-based connectors. Common types may include a Universal Serial Bus (USB) connector (which may include any of a number of different hardware interfaces), Mini DisplayPort (MDP), High Definition Multimedia Interface (HDMI®), FireWire, or other types.

[0044] In some embodiments, the connection circuit 5531 may be coupled to a control hub 5532, in addition to, or instead of, being directly coupled to a processor 5504, for example. In some embodiments, the display 5522 may be coupled to a control hub 5532, in addition to, or instead of, being directly coupled to a processor 5504, for example.

[0045] In some embodiments, the device 5500 includes a memory 5530 coupled to a processor 5504 via a memory interface 5534. The memory 5530 includes a memory device for storing information within the device 5500.

[0046] In some embodiments, the memory 5530 includes a device for maintaining and managing stable clock generation, as described with reference to various embodiments. The memory may include non-volatile (state does not change when power to the memory device is interrupted) and / or volatile (state becomes uncertain when power to the memory device is interrupted) memory devices. The memory device 5530 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or any other memory device having performance suitable for functioning as process memory. In one embodiment, the memory 5530 may operate as the system memory of the device 5500 for storing data and instructions used when one or more processors 5504 execute an application or process. The memory 5530 may store application data, user data, music, photographs, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of the device 5500.

[0047] Elements of various embodiments and examples are also provided as machine-readable media (e.g., memory 5530) for storing computer executable instructions (e.g., instructions for executing any other process described herein). The machine-readable media (e.g., memory 5530) may include, but is not limited to, flash memory, optical discs, CD-ROMs, DVD-ROMs, RAM, EPROMs, EEPROMs, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for storing electronic instructions or computer executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) that can be transferred by data signals from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem or network connection).

[0048] In some embodiments, the device 5500 includes a temperature measuring circuit 5540 for measuring the temperatures of various components of the device 5500, for example. In one example, the temperature measuring circuit 5540 may be built into, coupled to, or mounted on various components whose temperatures should be measured and monitored. For example, the temperature measuring circuit 5540 may measure the temperature (or the temperature within) one or more of the cores 5508a, 5508b, 5508c, voltage regulator 5514, memory 5530, the motherboard of the SoC 5501, and / or any suitable component of the device 5500. In some embodiments, the temperature measurement circuit 5540 includes a low-power hybrid reverse (LPHR) bandgap reference (BGR) and a digital temperature sensor (DTS), which utilize subthreshold metal-oxide-semiconductor (MOS) transistors and PNP parasitic bipolar junction (BJT) devices to form a reverse BGR that serves as the base for configurable BGR or DTS operating modes. The LPHR architecture uses low-cost MOS transistors and standard parasitic PNP devices. Based on the reverse bandgap voltage, the LPHR can operate as a configurable BGR. By comparing the configurable BGR with a scaled base-emitter voltage, the circuit can also function as a DTS with a linear transfer function via a high-precision single temperature trim.

[0049] In some embodiments, the device 5500 includes a power measurement circuit 5542 for measuring, for example, the power consumed by one or more components of the device 5500. In one example, in addition to, or instead of, measuring power, the power measurement circuit 5542 may measure voltage and / or current. In one example, the power measurement circuit 5542 may be built into, coupled to, or attached to various components whose power, voltage, and / or current should be measured and monitored. For example, the power measurement circuit 5542 may measure power, current, and / or voltage supplied by one or more voltage regulators 5514, power supplied to the SoC 5501, power supplied to the device 5500, power consumed by the processor 5504 (or other components) of the device 5500, and so on.

[0050] In some embodiments, the device 5500 includes one or more voltage regulator circuits, generally referred to as voltage regulator (VR) 5514. VR 5514 generates a signal of an appropriate voltage level that can be supplied to operate any appropriate component of the device 5500. As just one example, VR 5514 is illustrated supplying a signal to the processor 5504 of the device 5500. In some embodiments, VR 5514 receives one or more Voltage Identification (VID) signals and, based on the VID signals, generates a voltage signal at an appropriate level. Various types of VRs can be used for VR 5514. For example, VR 5514 may include “buck” VRs, “boost” VRs, combinations of buck and boost VRs, low dropout (LDO) regulators, switching DC-DC regulators, constant on-time controller-based DC-DC regulators, and the like. Buck VRs are generally used in power supply applications where an input voltage needs to be converted to an output voltage at a ratio of less than 1. Boost VRs are generally used in power supply applications where an input voltage needs to be converted to an output voltage at a ratio greater than 1. In some embodiments, each processor core has its own VR, which is controlled by the PCU5510a / b and / or PMIC5512. In some embodiments, each core has a distributed network of LDOs to provide efficient control for power management. The LDOs can be digital LDOs, analog LDOs, or a combination of digital and analog LDOs. In some embodiments, VR5514 includes a current tracking device that measures the current through one or more power rails.

[0051] In some embodiments, the VR5514 includes a digital control scheme for managing the state of a proportional-integral-derivative (PID) filter (also known as a digital type III compensator). This digital control scheme controls the integrator of the PID filter to implement nonlinear control that saturates the duty cycle, during which the proportional and derivative terms of the PID are set to 0, and the integrator and its internal state (previous values ​​or memory) are set to a duty cycle that is the sum of the current nominal duty cycle plus delta D. Delta D is the maximum duty cycle increment used to regulate the voltage regulator from ICCmin to ICCmax and is a setting register that can be set after the silicon process. The state machine transitions from a nonlinear all-on state (returning the output voltage Vout to the regulation window) to an open-loop duty cycle that maintains the output voltage slightly above the required reference voltage Vref. After a certain period in this open-loop state at the commanded duty cycle, the state machine ramps down the open-loop duty cycle value until the output voltage approaches the commanded Vref. Therefore, output chatter on the output supply from the VR5514 is completely (or substantially) eliminated, and only a single undershoot transition exists, which can lead to a guaranteed Vmin based on the di / dt of the load with comparator delay and available output decoupling capacitance.

[0052] In some embodiments, the VR5514 includes a separate self-start controller that operates without fuse and / or trim information. The self-start controller protects the VR5514 from large inrush currents and voltage overshoots while being able to follow a variable VID (Voltage Identification) reference ramp provided by the system. In some embodiments, the self-start controller uses a relaxation oscillator built into the controller to set the switching frequency of the buck converter. This oscillator can be initialized using either a clock or a current reference to approach the desired operating frequency. The output of the VR5514 is weakly coupled to this oscillator to set the duty cycle for closed-loop operation. The controller is naturally biased so that the output voltage is always slightly above the setpoint, eliminating the need for trim imposed by process, voltage, and / or temperature (PVT).

[0053] In some embodiments, the device 5500 includes one or more clock generator circuits, which are generally referred to as clock generator 5516. Clock generator 5516 generates a clock signal of an appropriate frequency level that can be supplied to any appropriate component of the device 5500. As just one example, clock generator 5516 is illustrated to be supplying a clock signal to processor 5504 of the device 5500. In some embodiments, clock generator 5516 receives one or more frequency identification (FID) signals and generates a clock signal at an appropriate frequency based on the FID signals.

[0054] In some embodiments, the device 5500 includes a battery 5518 that supplies power to various components of the device 5500. As just one example, the battery 5518 is illustrated to be supplying power to the processor 5504. Although not shown in the figure, the device 5500 may include a charging circuit for recharging the battery, for example, based on alternating current (AC) power received from an AC adapter.

[0055] In some embodiments, the battery 5518 is charged to a preset voltage (e.g., 4.1V) and periodically checks the actual battery capacity or energy. The battery then determines the battery capacity or energy. If the capacity or energy is insufficient, the battery or a device coupled to the battery slightly increases the charging voltage until the capacity is sufficient (e.g., from 4.1V to 4.11V). This process of periodically checking and slightly increasing the charging voltage is continued until the charging voltage reaches the specification limit (e.g., 4.2V). The scheme described herein has benefits such as extending battery life, reducing the risk of insufficient energy storage, allowing burst power to be used for as long as possible, and / or even higher burst power.

[0056] In some embodiments, battery 5518 is a multi-battery system with a workload-dependent load-sharing mechanism. This mechanism is an energy management system that operates in three modes: energy-saving mode, balancer mode, and turbo mode. Energy-saving mode is the normal mode in which multiple batteries (collectively referred to as battery 5518) supply power to their own load sets with minimum resistance dissipation. In balancer mode, batteries are connected to each other via switches operating in active mode such that the shared current is inversely proportional to the corresponding battery charge state. In turbo mode, both batteries are connected in parallel via switches (e.g., on switches) to supply maximum power to the processor or load. In some embodiments, battery 5518 is a hybrid battery having a fast-charging battery and a high-energy-density battery. A fast-charging battery (FC) means a battery that can be charged faster than a high-energy-density battery (HE). Since today's lithium-ion batteries can be charged faster than HEs, the FC may be one of them. In some embodiments, the controller (part of the battery 5518) optimizes the sequence and charging speed of the hybrid battery to maximize both the battery charging current and charging speed while enabling a longer battery life.

[0057] In some embodiments, the charging circuit (e.g., 5518) includes a buck-boost converter. This buck-boost converter has a DrMOS or DrGaN device used instead of the half-bridge in the case of a traditional buck-boost converter. Here, various embodiments will be described with reference to DrMOS. However, the embodiments are also applicable to DrGaN. DrMOS devices enable better efficiency in power conversion due to reduced parasitic components and optimized MOSFET packaging. Dead time management is more precise than in traditional buck-boost converters because dead time management is inherent in DrMOS, leading to higher conversion efficiency. Higher operating frequencies allow for smaller inductor sizes, which in turn reduces the z height of chargers with DrMOS-based buck-boost converters. Buck-boost converters in various embodiments have a double-folded bootstrap for DrMOS devices. In some embodiments, in addition to the traditional bootstrap capacitor, a folded bootstrap capacitor is added that cross-couples the inductor node to two sets of DrMOS switches.

[0058] In some embodiments, the device 5500 includes a power control unit (PCU) 5510 (also referred to as a power management unit (PMU), power management controller (PMC), power unit (p-unit), etc.). In one example, some sections of the PCU 5510 may be implemented by one or more processing cores 5508, and these sections of the PCU 5510 are symbolically illustrated with a dotted box labeled PCU 5510a. In one example, other sections of the PCU 5510 may be implemented outside of the processing cores 5508, and these sections of the PCU 5510 are symbolically illustrated with a dotted box labeled PCU 5510b. The PCU 5510 can implement various power management operations for the device 5500. To implement various power management operations for the device 5500, the PCU 5510 may include hardware interfaces, hardware circuits, connectors, registers, etc., and software components (e.g., drivers, protocol stacks).

[0059] In various embodiments, the PCU or PMU5510 is hierarchically organized to form hierarchical power management (HPM). In various embodiments, the HPM builds the capability and infrastructure to enable package-level management for the platform, while still accommodating the islands of autonomy that may exist across the dies of the components within the package. The HPM does not assume a predetermined mapping of physical partitions to domains. HPM domains can be aligned with functions integrated within a diet, aligned with a diet boundary, aligned with one or more diets, aligned with a companion die, or even aligned with a discrete CXL device. The HPM addresses the integration of multiple instances of the same die, mixed with proprietary or third-party functions integrated on the same die or separate dies, and even with accelerators connected via CXLs (e.g., Flexbus) that may be within the package, or in discrete form factors.

[0060] HPMs enable designers to meet the goals of scalability, modularity, and late binding. HPMs also allow leveraging PMU functions that may already exist on other dies, instead of being disabled in flat schemes. HPMs enable the management of any set of functions, regardless of their level of integration. Various embodiments of HPMs are scalable, modular, and work with symmetric multi-chip processors (MCPs) and asymmetric MCPs. For example, HPMs do not require signal PM controllers and package infrastructure to grow beyond reasonable scaling limits. HPMs allow adding dies to a package later without changing the infrastructure of the base die. HPMs address the need for non-aggregated solutions that combine dies from different process technology nodes within a single package. HPMs also address the need for companion die integration solutions both on and off the package.

[0061] In various embodiments, each die (or dielet) includes a power management unit (PMU) or p-unit. For example, a processor die may have a supervisor p-unit, a supervised p-unit, or a dual-role supervisor / supervised p-unit. In some embodiments, an I / O die may have its own dual-role p-unit, such as a supervisor and / or supervised p-unit. A p-unit within each die may be an instance of a general p-unit. In one such example, all p-units have the same capabilities and circuitry but are configured (dynamically or statically) to assume the roles of supervisor, supervised, and / or both. In some embodiments, a p-unit on a compute die is an instance of a compute p-unit, and a p-unit on an I / O die is an instance of an I / O p-unit distinct from the compute p-unit. Depending on its role, a p-unit takes on specific responsibilities for managing the power of a multi-chip module and / or computing platform. While various p-units have been described in relation to dies in a multi-chip module or system-on-a-chip, a p-unit can also be part of an external device, such as an I / O device.

[0062] Here, various p-units do not need to be the same. The HPM architecture can operate many different types of p-units. One common function of p-units is that they are expected to receive and understand HPM messages. In some embodiments, p-units on an IO die may differ from p-units on a compute die. For example, the number of register instances for each class of registers in an IO p-unit may differ from that in a compute die p-unit. An IO die may have the ability to be the HPM supervisor for CXL-connected devices, while a compute die does not need to have that ability. IO dies and compute dies also have different firmware flows and may have different firmware images. These are choices that implementations can make. The HPM architecture can choose to have a single superset firmware image, and the firmware can selectively execute flows that correspond to the type of die it is associated with. Alternatively, there can be custom firmware for each p-unit type, which allows for more efficient sizing of firmware storage requirements for each p-unit type.

[0063] Each p-unit within a die can be configured as a supervisor p-unit, a supervised p-unit, or to have both supervisor and supervised roles. Thus, a p-unit can play the role of supervisor or supervised for various domains. In various embodiments, each instance of a p-unit can autonomously manage local dedicated resources and includes a structure that aggregates data and communicates between instances to enable shared resource management by instances configured as shared resource supervisors. A message and wire-based infrastructure is provided that can be configured redundantly to facilitate management and flow between multiple p-units.

[0064] In some embodiments, power and thermal thresholds are communicated from a supervisor p-unit to a supervised p-unit. For example, the supervisor p-unit knows the workload (current and future) of each die, the power measurement of each die, and other parameters (e.g., platform-level power boundaries) to determine a new power limit for each die. These power limits are then communicated from the supervisor p-unit to the supervised p-unit via one or more interconnects and fabrics. In some embodiments, the fabric refers to a group of fabrics and interconnects, including a first fabric, a second fabric, and a fast-response interconnect. In some embodiments, the first fabric is used for general communication between the supervisor p-unit and the supervised p-unit. This general communication includes changes in the voltage, frequency, and / or power state of the dies, planned based on a number of factors (e.g., future workload, user behavior, etc.). In some embodiments, the second fabric is used for higher-priority communication between the supervisor p-unit and the supervised p-unit. Examples of higher-priority communications include messages indicating that throttling should occur due to potential thermal runaway conditions, reliability issues, etc. In some embodiments, a fast response interconnect is used to communicate fast throttling or hard throttling for all dies. In this case, a supervisor p-unit may, for example, send fast throttling messages to all other p-units. In some embodiments, the fast response interconnect is a legacy interconnect whose function can be performed by a second fabric.

[0065] HPM architectures in various embodiments enable scalability, modularity, and later coupling of symmetric and / or asymmetric dies, where symmetric dies are dies of the same size, type, and / or function, and asymmetric dies are dies of different sizes, types, and / or functions. The hierarchical approach also allows for the utilization of PMU functions that may already be present on other dies, instead of being disabled in traditional flat power management schemes. HPM does not assume a predetermined mapping of physical partitions to domains. HPM domains can be aligned with functions integrated within a dielet, aligned to a dielet boundary, aligned to one or more dielets, aligned to a companion die, or even aligned to a discrete CXL device. HPM enables the management of any set of functions, regardless of their level of integration. In some embodiments, a p-unit declares a supervisor p-unit based on one or more factors, including memory size, physical constraints (e.g., number of pinouts), and sensor locations that determine the physical limits of the processor (e.g., temperature, power consumption, etc.).

[0066] Various embodiments of the HPM architecture provide a means of scaling power management so that a single p-unit instance does not need to be aware of the entire processor. This enables power management at a finer granularity, improving response time and efficiency. The hierarchical structure maintains a monolithic view for the user. For example, at the operating system (OS) level, the HPM architecture gives the OS a single PMU view, even if its PMUs are physically distributed in one or more supervisor-supervised configurations.

[0067] In some embodiments, the HPM architecture is centralized, with one supervisor controlling all supervisors. In some embodiments, the HPM architecture is decentralized, with various p-units within various dies controlling the entire power management through peer-to-peer communication. In some embodiments, the HPM architecture is distributed, with different supervisors in different domains. An example of a distributed architecture is a tree-like architecture.

[0068] In some embodiments, the device 5500 includes a power management integrated circuit (PMIC) 5512 to implement various power management operations relating to the device 5500, for example. In some embodiments, the PMIC 5512 is a reconfigurable power management IC (RPMIC) and / or IMVP (Intel® Mobile Voltage Positioning). In one example, the PMIC resides on a separate IC die from the processor 5504. It can implement various power management operations relating to the device 5500. The PMIC 5512 may include hardware interfaces, hardware circuits, connectors, registers, etc., and software components (e.g., drivers, protocol stacks) to implement various power management operations relating to the device 5500.

[0069] In one example, the apparatus 5500 includes either or both of the PCU 5510 and / or PMIC 5512. In one example, either the PCU 5510 or the PMIC 5512 may not be present in the apparatus 5500, and therefore these components are illustrated using dotted lines.

[0070] Various power management operations of the device 5500 can be performed by the PCU 5510, by the PMIC 5512, or by a combination of the PCU 5510 and the PMIC 5512. For example, the PCU 5510 and / or the PMIC 5512 can select power states (e.g., P states) for various components of the device 5500. For example, the PCU 5510 and / or the PMIC 5512 can select power states for various components of the device 5500 (e.g., according to the ACPI (Advanced Configuration and Power Interface) specification). As just one example, the PCU 5510 and / or the PMIC 5512 can transition various components of the device 5500 to sleep state, active state, appropriate C state (e.g., C0 state according to the ACPI specification, or other appropriate C state), etc. In one example, the PCU5510 and / or PMIC5512 can control the voltage output by the VR5514 and / or the frequency of the clock signal output by the clock generator, for example, by outputting a VID signal and / or FID signal, respectively. In another example, the PCU5510 and / or PMIC5512 can control functions related to battery power consumption, charging of the battery 5518, and power saving operations.

[0071] The clock generator 5516 may have a phase-locked loop (PLL), a frequency-locked loop (FLL), or any preferred clock source. In some embodiments, each core of the processor 5504 has its own clock source. Thus, each core can operate at a frequency independent of the operating frequencies of the other cores. In some embodiments, the PCU 5510 and / or PMIC 5512 perform adaptive or dynamic frequency scaling or adjustment. For example, the clock frequency of a processor core may be increased if that core is not operating at its maximum power consumption threshold or limit. In some embodiments, the PCU 5510 and / or PMIC 5512 determine the operating conditions of each core of the processor, and when the PCU 5510 and / or PMIC 5512 determines that a core is operating below a target performance level, it takes the opportunity to adjust the frequency and / or power supply voltage of that core without losing lock on its clock source (e.g., its PLL). For example, if a core is drawing less current from the power supply rail than the total current allocated to that core or processor 5504, the PCU 5510 and / or PMIC 5512 may temporarily increase the power draw to that core or processor 5504 (for example, by increasing the clock frequency and / or power supply voltage level) so that the core or processor 5504 can achieve a higher performance level. Thus, the voltage and / or frequency to the processor 5504 can be temporarily increased without compromising product reliability.

[0072] In one example, the PCU 5510 and / or PMIC 5512 may perform power management operations, at least in part, based on receiving, for example, measurement results from a power measurement circuit 5542, a temperature measurement circuit 5540, the charge level of a battery 5518, and / or other appropriate information that may be used for power management. For this purpose, the PMIC 5512 is communicatively coupled to one or more sensors to detect / detect various values / variations in one or more factors that affect the power / thermal behavior of the system / platform. Examples of one or more factors include current, voltage droop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be located in physical proximity (and / or thermally in contact with) one or more components or logic / IP blocks of the computing system. Furthermore, in at least one embodiment, by directly coupling (one or more) sensors to the PCU5510 and / or PMIC5512, the PCU5510 and / or PMIC5512 may be enabled to manage processor core energy at least in part on (one or more) values ​​detected by one or more of those sensors.

[0073] An example of the software stack of device 5500 is also illustrated (however, not all elements of the software stack are illustrated). As a mere example, the processor 5504 may execute an application program 5550, an operating system 5552, one or more power management (PM) application programs (for example, generally referred to as PM application 5558), and / or similar. PM application 5558 may also be executed by the PCU 5510 and / or PMIC 5512. OS 5552 may also include one or more PM applications 5556a, 5556b, 5556c. OS 5552 may also include various drivers 5554a, 5554b, 5554c, etc., some of which may be specific to power management purposes. In some embodiments, device 5500 may further include a basic input / output system (BIOS) 5520. BIOS5520 may communicate with OS5552 (for example, via one or more drivers 5554), communicate with processor 5504, and so on.

[0074] For example, one or more of the PM applications 5558, 5556, driver 5554, BIOS 5520, etc., can be used to implement power management tasks such as controlling the voltage and / or frequency of various components of the device 5500, controlling the wake-up state, sleep state, and / or other appropriate power states of various components of the device 5500, and controlling functions related to battery power usage, battery 5518 charging, and power saving operations.

[0075] In some embodiments, the battery 5518 is a Li-metal battery equipped with a pressure chamber that enables uniform pressure on the battery. The pressure chamber is supported by a metal plate (e.g., a pressure equalizing plate) used to apply uniform pressure to the battery. The pressure chamber may include pressurized gas, elastic material, spring plates, etc. The outer sheath of the pressure chamber is constrained at its edges by a (metal) film and can bend freely, yet still applies uniform pressure to the plate that is pressing against the battery cells. The pressure chamber is used to apply uniform pressure to the battery, which enables a high-energy-density battery, for example, with a 20% longer battery life.

[0076] In some embodiments, the battery 5518 incorporates hybrid technology. For example, a mixture of a high-energy-density charge-carrying device (e.g., a Li-ion battery) and a low-energy-density charge-carrying device (e.g., a supercapacitor) is used as the battery or storage device. In some embodiments, a controller (e.g., hardware, software, or a combination thereof) is used to analyze the peak power pattern to minimize the impact on the overall lifespan of the high-energy-density charge-carrying device-based battery cell while maximizing service time for peak power shaving functionality. The controller may be part of the battery 5518 or part of the p-unit 5510b.

[0077] In some embodiments, the pCode running on the PCU5510a / b has the capability to enable additional computational and telemetry resources for runtime support of the pCode. Here, pCode refers to the firmware run by the PCU5510a / b to manage the performance of the SoC5501. For example, the pCode may set the frequency and appropriate voltage for the processor. Parts of the pCode are accessible via the OS5552. In various embodiments, mechanisms and methods are provided for dynamically changing the Energy Performance Preference (EPP) based on the workload, user behavior, and / or system conditions. A clearly defined interface may exist between the OS5552 and the pCode. This interface may enable or facilitate the software configuration of several parameters and / or provide hints to the pCode. As an example, the EPP parameters may inform the pCode algorithm whether performance or battery life is more important.

[0078] This support can also be provided by the OS, including machine learning support as part of OS5552, and either by adjusting EPP values ​​that the OS uses to hint to hardware (e.g., various components of the SoC5501) based on machine learning predictions, or by delivering machine learning predictions to the pCode in a similar manner to how it is done by the Dynamic Tuning Technology (DTT) driver. In this model, OS5552 can see the same set of telemetry that is available to DTT. As a result of the DTT machine learning hint setting, the pCode can adjust its internal algorithms to achieve optimal power and performance results according to the activated type of machine learning prediction. For example, the pCode can increase its bias towards energy saving by either increasing its responsibility for changes in processor utilization to enable faster responses to user activity, or by decreasing its responsibility for processor utilization, or by increasing the performance lost by adjusting energy saving optimizations to save more power. This approach can facilitate saving more battery life when the type of activity enabled causes a loss of performance levels beyond what the system allows. The pCode may include an algorithm for dynamic EPP, which takes two inputs, one from OS5552 and another from software such as DTT, and may selectively choose to provide higher performance and / or responsiveness. As part of this method, the pCode may enable an option in DTT to adjust its response to DTT for multiple different types of activity.

[0079] In some embodiments, pCode improves SoC performance in battery mode. In some embodiments, pCode enables dramatically higher SoC peak power limit levels (and thus higher turbo performance) in battery mode. In some embodiments, pCode implements power throttling and is part of Intel's Dynamic Tuning Technology (DTT). In various embodiments, the peak power limit is referred to as PL4. However, embodiments are applicable to other peak power limits as well. In some embodiments, pCode sets a Vth threshold voltage (the voltage level at which the platform will throttle the SoC) to prevent the system from unexpectedly shutting down (or going black screen). In some embodiments, pCode calculates the Psoc,pk SoC peak power limit (e.g., PL4) according to the threshold voltage (Vth). These are two dependent parameters, and once one is set, the other can be calculated. pCode is used to optimally set one of the parameters (Vth) based on system parameters and operational history. In some embodiments, pCode provides a scheme for dynamically calculating the throttling level (Psoc,th) based on available battery power (which changes slowly) to set the SoC throttling peak power (Psoc,th). In some embodiments, pCode determines the frequency and voltage based on Psoc,th. In this case, the throttling event has little negative impact on SoC performance. Various embodiments provide schemes that enable the maximum performance (Pmax) framework to operate.

[0080] In some embodiments, the VR5514 includes a current sensor for sensing and / or measuring the current through the high-side switch of the VR5514. In some embodiments, the current sensor uses an amplifier, which has a feedback-coupled input to sense the amplifier's input offset, which can be compensated for during measurement. In some embodiments, the amplifier with a feedback-coupled input is used to operate the amplifier in a region where the input common-mode specification is relaxed so that the feedback loop gain and / or bandwidth is higher. In some embodiments, the amplifier with a feedback-coupled input is used to operate the sensor from the converter input voltage by using a high PSRR (power supply rejection ratio) regulator to generate a localized, clean supply voltage that reduces disruption to the power system in the switch area. In some embodiments, using a design modification, the difference between the input voltage and the controller supply can be sampled to reproduce the difference in drain voltage between the power switch and the replica switch. This allows the sensor not to be exposed to the supply voltage. In some embodiments, an amplifier with a feedback-coupled input is used to compensate for power grid-related (PDN-related) changes in the input voltage during current sensing.

[0081] Some embodiments use three components to adjust the peak power of the SoC5501 based on the state of the USB TYPE-C device 5529. These components include an OS peak power manager (part of OS5552), a USB TYPE-C connector manager (part of OS5552), and a USB TYPE-C protocol device driver (e.g., one of drivers 5554a, 5554b, or 5554c). In some embodiments, the USB TYPE-C connector manager sends a synchronization request to the OS peak power manager when the USB TYPE-C power sink device is attached to or detached from the SoC5501, and the USB TYPE-C protocol device driver sends a synchronization request to the peak power manager when the power sink transitions between device states. In some embodiments, the peak power manager receives a power budget from the CPU when the USB TYPE-C connector is attached to the power sink and active (e.g., in a high-power device state). In some embodiments, the peak power manager returns the power budget to the CPU for performance purposes when the USB Type-C connector is disconnected, or when the USB Type-C connector is connected and the power sink device is idle (lowest device state).

[0082] In some embodiments, logic is provided for dynamically selecting the best operating processing core for the BIOS power-up flow and sleep termination flow (e.g., S3, S4, and / or S5). The bootstrap processor (BSP) selection is shifted to the early power-up time, instead of a fixed hardware selection at any given time. For maximum boot performance, the logic selects the core that is capable of being the fastest as the BSP during the early power-up time. For maximum power savings, the logic selects the most power-efficient core as the BSP. The processor or switching for BSP selection occurs during the boot-up and power-up flow (e.g., S3, S4, and / or S5 flow).

[0083] In some embodiments, the memory is organized in a multi-level memory architecture, and its performance is governed by a decentralized scheme. This decentralized scheme includes a p-unit 5510 and a memory controller. In some embodiments, this scheme dynamically balances multiple parameters, such as power, heat, cost, latency, and performance, for memory levels that move progressively further away from the processor within the platform 5500, based on how applications utilize memory levels that are farther from the processor core. In some examples, decisions regarding the state of far memory (FM) are decentralized. For example, a processor power management unit (p-unit), a near memory controller (NMC), and / or a far memory host controller (FMHC) make decisions regarding the power and / or performance state of the FM at their respective levels. These decisions work together to provide an optimal power and / or performance state for the FM at a given point in time. The power and / or performance state of memory adaptively changes to adapt to changing workloads and other parameters, even when one or more processors are in a particular power state.

[0084] In some embodiments, a hardware-software coordinated processor power state policy (e.g., a policy for state C) is implemented to provide optimal power state selection by taking into account the performance and / or responsiveness needs of threads expected to be scheduled to enter an idle state, in order to achieve improved instruction executions per cycle (IPC) and performance for cores performing user-critical tasks. This scheme provides the ability to deliver responsiveness gains to critical and / or user-critical threads running on the system-on-chip. A p-unit 5510 coupled to multiple processing cores receives hints from the operating system 5552 indicating a bias to the power state or performance state for at least one of the multiple processing cores, based on thread priority in context switching.

[0085] References in the specification to “a certain embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” mean that a particular mechanism, structure, or feature described in relation to those embodiments is included in at least some embodiments, but not necessarily in all embodiments. The various appearances of “a certain embodiment,” “one embodiment,” or “some embodiments” do not necessarily all refer to the same embodiment. Where the specification states that a component, mechanism, structure, or feature “may,” “may,” or “may be,” that particular component, mechanism, structure, or feature is not required to be included. When the specification or claims refer to an element with “a” or “an,” it does not mean that there is only one of those elements. When the specification or claims refer to an element with “an additional,” it does not exclude the possibility that there are two or more of those additional elements.

[0086] Throughout the specification and in the claims, the term “connected” means a direct connection between connected objects, such as an electrical, mechanical, or magnetic connection, without an intermediate device.

[0087] The term “connected” means direct or indirect connections, such as direct electrical, mechanical, or magnetic connections between connected objects, or indirect connections via one or more passive or active intermediate devices.

[0088] The term “adjacent” in this context generally refers to a position where one object is next to another (e.g., immediately next to, or in close proximity with one or more objects in between) or where they share a boundary (e.g., touching).

[0089] The terms “circuit” or “module” may refer to one or more passive and / or active components configured to work together to provide a desired function.

[0090] The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of “a,” “an,” and “the” include plural references. The meaning of “in” includes both “in” and “on.”

[0091] The term "analog signal" here generally refers to a continuous signal whose time-varying characteristics (variables) represent some other time-varying quantity, that is, a signal that is similar to another time-varying signal.

[0092] The term "digital signal" refers to a physical signal that represents a series of discrete values ​​(quantified discrete-time signals), such as an arbitrary bitstream or a digitized (sampled and analog-to-digital converted) analog signal.

[0093] The term "scaling" generally refers to the conversion of a design (circuit diagram and layout) from one process technology to another, which may subsequently reduce the layout area. In some cases, scaling can also involve enlarging a design from one process technology to another, which may subsequently increase the layout area. The term "scaling" generally also refers to the miniaturization or enlargement of layouts and devices within the same technology node. The term "scaling" can also refer to adjusting signal frequencies relative to other parameters, such as power supply levels (e.g., slowing down or speeding up, i.e., scaling down or scaling up, respectively).

[0094] The terms “substantially,” “near,” “approximately,” “almost,” and “about” generally refer to being within ±10% of the target value.

[0095] Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” “third,” etc., to describe a common object simply indicates that different instances of a similar object are being referred to, and is not intended to imply that the objects described in this way must be in a given sequence, temporally, spatially, in rank, or in any other way.

[0096] For the purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0097] In the specification and claims, where present, the terms “left,” “right,” “front,” “back,” “top,” “bottom,” “up,” “down,” and similar terms are used for descriptive purposes and not necessarily to describe permanent relative positions.

[0098] It should be noted that a figure element having the same reference numeral (or name) as an element in another figure may, but is not limited to, behave or function in the same way as described.

[0099] For the purposes of the embodiments, the transistors in the various circuits and logic blocks described herein are metal-oxide-semiconductor (MOS) transistors or derivatives thereof, where a MOS transistor includes drain, source, gate, and bulk terminals. Transistors and / or MOS transistor derivatives also include tri-gate and FinFET transistors, gate-all-around cylindrical transistors, tunneling FETs (TFETs), square-wire or rectangular ribbon transistors, ferroelectric FETs (FeFETs), or other devices that realize transistor functions, such as carbon nanotube or spintronic devices. The symmetrical source and drain terminals of a MOSFET are, in other words, equivalent terminals and are used interchangeably here. TFET devices, on the other hand, have asymmetrical source and drain terminals. As those skilled in the art will understand, without departing from the scope of the disclosure, other transistors such as bipolar junction transistors (BJT PNP / NPN), BiCMOS, CMOS, etc., may also be used.

[0100] Here, the term “die” generally refers to a continuous single piece of semiconductor material (e.g., silicon) on which transistors or other components constituting the processor core may be present. A multicore processor may have two or more processors on a single die, or conversely, two or more processors may be provided on two or more separate dies. Each die has its own dedicated power controller or power control unit (p-unit), or a power controller or power control unit (p-unit) that may be dynamically or statically configured as supervisor or supervisor. In some examples, the dies are of the same size and function, i.e., symmetrical cores. However, dies can also be asymmetrical. For example, some dies may have different sizes and / or functions from other dies. Each processor may also be a dielet or chiplet. Here, the term “dielet” or “chiplet” generally refers to a physically separate semiconductor die, typically connected to an adjacent die in such a way that a fabric crossing the die boundary can function as a single fabric rather than two separate fabrics. Thus, at least some dies may be dielets. Each dirette may contain one or more p units that can be dynamically or statically configured as supervisor, supervisor, or both.

[0101] Here, the term “fabric” generally refers to a communication mechanism having a known set of sources, destinations, routing rules, topology, and other properties. The sources and destinations can be any type of data handling functional unit, such as a power management unit. The fabric can be two-dimensional, extending along the xy-plane of the dies, and / or three-dimensional (3D), extending along the xyz-plane of a stack of dies arranged vertically and horizontally. A single fabric may extend across multiple dies. The fabric can take any topology, such as a mesh topology, star topology, or daisy-chain topology. The fabric may also be part of a network-on-a-chip (NoC) with multiple agents, which can be any functional unit.

[0102] Here, the term “processor core” generally refers to an independent execution unit capable of executing one program thread at a time in parallel with other cores. A processor core may include a dedicated power controller or power control unit (p-unit) that can be configured dynamically or statically as a supervisor or supervised unit. This dedicated p-unit is also referred to as an autonomous p-unit in some examples. In some examples, all processor cores are of the same size and functionality, i.e., symmetric cores. However, processor cores may be asymmetric. For example, some processor cores may have different sizes and / or functionality than other processor cores. A processor core may be a virtual processor core or a physical processor core.

[0103] Here, the term “interconnect” refers to a communication link or channel between two or more points or nodes. An interconnect may have one or more distinct conductive paths, such as wires, vias, waveguides, passive components, and / or active components. An interconnect may also have a fabric.

[0104] Here, the term “interface” generally refers to the software and / or hardware used to communicate with an interconnect. An interface may include logic and I / O drivers / receivers for sending and receiving data over an interconnect or one or more wires.

[0105] Here, the term “domain” generally refers to a logical or physical boundary that shares similar characteristics (e.g., supply voltage, operating frequency, circuit or logic type, and / or workload type) and / or is controlled by a specific agent. For example, a domain can be a group of logic or functional units controlled by a specific supervisor. A domain may also be referred to as an Autonomous Perimeter (AP). A domain can be an entire system-on-a-chip (SoC) or a part of an SoC, and is governed by a p-unit.

[0106] Here, the term “supervisor” generally refers to a power controller or power management unit (“p-unit”) that monitors and manages power and performance-related parameters for one or more related power domains, either alone or in cooperation with one or more other p-units. Power / performance-related parameters may include, but are not limited to, domain power, platform power, voltage, voltage domain current, die current, load line, temperature, device latency, utilization, clock frequency, processing efficiency, current / future workload information, and other parameters. It may determine new power or performance parameters (limits, mean operation, etc.) for its one or more domains. These parameters may then be communicated to the supervised p-unit, or directly to the controlled or monitored entity, such as a VR or clock throttle control register, via one or more fabrics and / or interconnects. The supervisor knows the workload (current and future) of one or more dies, the power measurements of one or more dies, and other parameters (e.g., platform-level power boundaries), and determines new power limits for one or more dies. These power limits are then communicated by the supervisor p-unit to the supervised p-units via one or more fabrics and / or interconnects. In examples where a die has one p-unit, the supervisor (Svor) p-unit is also referred to as the supervisor die.

[0107] Here, the term “supervisee” generally refers to a power controller or power management unit (“p-unit”) that, either alone or in cooperation with one or more other p-units, monitors and manages power and performance-related parameters for one or more related power domains, and receives instructions from the supervisor to set power and / or performance parameters (e.g., supply voltage, operating frequency, maximum current, throttling threshold, etc.) for those related power domains. In examples where a die has one p-unit, the p-unit of the supervisee (Svee) is also referred to as the supervisee die. Note that a p-unit can function as either a Svor, a Svee, or both a Svor / Svee p-unit.

[0108] Furthermore, specific mechanisms, structures, functions, or features may be combined as suitable in one or more embodiments. For example, a first embodiment may be combined with a second embodiment if the specific mechanisms, structures, functions, or features related to these two embodiments are not mutually exclusive.

[0109] While the disclosure has been described in relation to its specific embodiments, numerous modifications, alterations, and variations of these embodiments will become apparent to those skilled in the art in light of the above description. The embodiments of the disclosure are intended to encompass all such modifications, alterations, and variations that fall within the broad scope of the appended claims.

[0110] In addition, for the sake of simplicity in illustration and explanation, and to avoid obscuring the disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented diagrams. Furthermore, configurations may be shown in the form of block diagrams, to avoid obscuring the disclosure, and in light of the fact that details relating to the implementation of such block diagram configurations are largely dependent on the platform in which this disclosure will be implemented (i.e., such details should be well within the scope of the involvement of those skilled in the art). Where certain details (e.g., circuits) are described to illustrate an example of an embodiment of the disclosure, it should be obvious to those skilled in the art that the disclosure can be carried out without those specific details or using variations thereof. Such descriptions are therefore intended to be illustrative rather than limiting.

[0111] Various embodiments are described as examples. These examples can be combined as appropriate. For example, Example 5 can be combined with Example 3 and / or Example 7.

[0112] Example 1: A device comprising: a battery transistor coupled to a battery; a battery charger for controlling the battery transistor; a circuit for bypassing the battery charger; a first voltage regulator having inputs coupled to the circuit and the battery transistor, wherein some platform components are directly coupled to the battery transistor; and a second voltage regulator having inputs coupled to the output of the first voltage regulator, which provides power to a processor core.

[0113] Example 2: The apparatus of Example 1, wherein the first voltage regulator has a switch-capacitor voltage regulator or a high-efficiency (e.g., above 85%) intermediate converter.

[0114] Example 3: The device of Example 1, wherein the battery charger includes a buck converter or a buck boost converter.

[0115] Example 4: The battery charger is the device of Example 1, which receives input from an external source.

[0116] Example 5: The apparatus of Example 1, wherein the apparatus has a third voltage regulator having an input coupled to the output of the first voltage regulator, and the third voltage regulator provides power to a graphics processor.

[0117] Example 6: The apparatus of Example 1, wherein the battery charger is coupled to an adapter.

[0118] Example 7: The apparatus of Example 1, wherein the first voltage regulator does not include an inductor.

[0119] Example 8: The apparatus of Example 1, wherein the first voltage regulator includes an inductor.

[0120] Example 9: The device of Example 1, wherein the battery is a series-configured battery cell.

[0121] Example 10: A device comprising: a voltage regulator that supplies power to a downstream power regulator that supplies power to a processor core and a graphics processor; a battery charger coupled to a battery and supplying power to the battery, the battery charger including a buck converter or buck boost converter; and a battery transistor coupled to the battery and the voltage regulator, the battery transistor controllable by the battery charger.

[0122] Example 11: The apparatus of Example 10, wherein the voltage regulator has a switch-capacitor voltage regulator or another high-efficiency (e.g., above 85%) power conversion topology (resonant converter).

[0123] Example 12: The device of Example 10, wherein the battery charger is coupled to an adapter.

[0124] Example 13: The apparatus of Example 10, wherein the voltage regulator includes an inductor.

[0125] Example 14: The apparatus of Example 10, wherein the voltage regulator does not include an inductor.

[0126] Example 15: The apparatus of Example 10, wherein the battery is a series-configured battery cell.

[0127] Example 16: A system comprising a processor, a graphics processor, a battery transistor coupled to a battery, a battery charger for controlling the battery transistor, wherein some platform components are directly coupled to the battery transistor, a circuit for bypassing the battery charger, a first voltage regulator having inputs coupled to the circuit and the battery transistor, a second voltage regulator having inputs coupled to the output of the first voltage regulator and supplying power to the processor, a third voltage regulator having inputs coupled to the output of the first voltage regulator and supplying power to the graphics processor, and a wireless interface enabling the processor to communicate with another device.

[0128] Example 17: The system of Example 16, wherein the first voltage regulator has a switch-capacitor voltage regulator, and the first voltage regulator supplies power to either the processor or the graphics processor.

[0129] Example 18: The system of Example 16, wherein the battery charger includes a buck converter.

[0130] Example 19: The system of Example 16, wherein the buck converter receives input from an external source.

[0131] Example 20: The system of Example 16, wherein the battery charger is coupled to an adapter, and the battery is a series-configured battery cell system.

[0132] An abstract is provided to allow readers to confirm the nature and essence of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are incorporated into the detailed description, and each claim stands alone as a separate embodiment.

Claims

1. A battery transistor coupled to the battery, A battery charger that controls the aforementioned battery transistor, A circuit that bypasses the aforementioned battery charger, A first voltage regulator having an input coupled to the circuit and the battery transistor, wherein some platform components are directly coupled to the battery transistor, A second voltage regulator having an input coupled to the output of the first voltage regulator, the second voltage regulator providing power to the processor core, A device having.

2. The apparatus according to claim 1, wherein the first voltage regulator has a switch capacitor voltage regulator or a high-efficiency intermediate converter.

3. The apparatus according to claim 1 or 2, wherein the battery charger includes a buck converter or a buck boost converter.

4. The battery charger is the device according to any one of claims 1 to 3, wherein the battery charger receives input from an external source.

5. The apparatus according to any one of claims 1 to 4, further comprising a third voltage regulator having an input coupled to the output of the first voltage regulator, wherein the third voltage regulator provides power to a graphics processor.

6. The apparatus according to any one of claims 1 to 5, wherein the battery charger is coupled to an adapter.

7. The apparatus according to any one of claims 1 to 6, wherein the first voltage regulator does not include an inductor.

8. The apparatus according to any one of claims 1 to 6, wherein the first voltage regulator includes an inductor.

9. The apparatus according to any one of claims 1 to 8, wherein the battery is a series-configured battery cell.

10. Processor and Graphics processor, A battery transistor coupled to the battery, A battery charger that controls the aforementioned battery transistor, wherein some platform components are directly coupled to the aforementioned battery transistor, A circuit that bypasses the aforementioned battery charger, The circuit and a first voltage regulator having an input coupled to the battery transistor, A second voltage regulator having an input coupled to the output of the first voltage regulator, the second voltage regulator supplying power to the processor, A third voltage regulator having an input coupled to the output of the first voltage regulator, the third voltage regulator supplying power to the graphics processor, A wireless interface that enables the processor to communicate with another device, A system that has

11. The system according to claim 10, wherein the first voltage regulator has a switch capacitor voltage regulator, and the first voltage regulator supplies power to either the processor or the graphics processor.

12. The system according to claim 10 or 11, wherein the battery charger includes a buck converter.

13. The system according to claim 12, wherein the buck converter receives input from an external source.

14. The system according to any one of claims 10 to 13, wherein the battery charger is coupled to an adapter, and the battery is a series-configured battery cell.

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