Semiconductor Device

Abstract

Provided is a semiconductor device having good electrical characteristics. Provided is a highly reliable semiconductor device. This semiconductor device has a first transistor and a second transistor. The first transistor has a first semiconductor layer, a first insulation layer, a second insulation layer, and a first gate electrode laminated in this order. The first gate electrode has a region that overlaps the first semiconductor layer. The second transistor has a second semiconductor layer, a second insulation layer, and a second gate electrode laminated in this order. The second gate electrode has a region that overlaps the second semiconductor layer.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] As a semiconductor material applicable to transistors, oxide semiconductors using metal oxides have attracted attention. For example, Patent Literature 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer serving as a channel contains indium and gallium, and the proportion of indium is made larger than the proportion of gallium, thereby increasing field-effect mobility (sometimes simply referred to as mobility or μFE).

[0004] Metal oxides can be formed using a sputtering method, so they can be used for the semiconductor layers of transistors that make up large display devices. Furthermore, they can be used by modifying part of the production equipment for transistors that use polycrystalline silicon or amorphous silicon, reducing capital investment. Furthermore, transistors that use metal oxides have higher field-effect mobility than transistors that use amorphous silicon, so they can be used to realize high-performance display devices equipped with gate drivers.

[0005] JP 2014-7399 A

[0006] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with stable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device including different transistors over the same substrate.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0007] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0008] One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. The first transistor includes a first semiconductor layer, a first insulating layer, a second insulating layer, and a first gate electrode, which are stacked in this order. The first gate electrode has a region overlapping with the first semiconductor layer. The second transistor includes a second semiconductor layer, a second insulating layer, and a second gate electrode, which are stacked in this order. The second gate electrode has a region overlapping with the second semiconductor layer.

[0009] In the semiconductor device described above, the first insulating layer preferably has a region in contact with the upper surface of the first semiconductor layer, and the first insulating layer preferably has a region in contact with the lower surface of the second semiconductor layer.

[0010] In the semiconductor device, the first semiconductor layer and the second semiconductor layer each preferably contain indium, and the ratio of the number of indium atoms to the number of atoms of the metal element contained in the second semiconductor layer is preferably higher than that of the first semiconductor layer.

[0011] In the above-described semiconductor device, the second semiconductor layer preferably has a ratio of the number of indium atoms to the number of atoms of the contained metal element of 30 atomic % or more and 100 atomic % or less.

[0012] In the semiconductor device, the first semiconductor layer and the second semiconductor layer each preferably contain indium, and the ratio of the number of indium atoms to the number of atoms of the metal element contained in the first semiconductor layer is preferably higher than that in the second semiconductor layer.

[0013] In the above-described semiconductor device, the first semiconductor layer preferably has a ratio of the number of indium atoms to the number of atoms of the contained metal element of 30 atomic % or more and 100 atomic % or less.

[0014] In the semiconductor device described above, the second semiconductor layer preferably contains an element M, and the element M is one or more elements selected from gallium, aluminum, yttrium, and tin. The second semiconductor layer preferably has a higher ratio of the number of atoms of the element M to the number of atoms of the contained metal element than the first semiconductor layer.

[0015] In the above-described semiconductor device, the second semiconductor layer preferably has a ratio of the number of atoms of element M to the number of atoms of the contained metal element of 20 atomic % or more and 60 atomic % or less.

[0016] In the semiconductor device described above, the first semiconductor layer preferably contains an element M, and the element M is one or more elements selected from gallium, aluminum, yttrium, and tin. The first semiconductor layer preferably has a higher ratio of the number of atoms of the element M to the number of atoms of the contained metal element than the second semiconductor layer.

[0017] In the above-described semiconductor device, the first semiconductor layer preferably has a ratio of the number of atoms of element M to the number of atoms of the contained metal element of 20 atomic % or more and 60 atomic % or less.

[0018] In the semiconductor device, the first transistor preferably includes a third insulating layer and a third gate electrode. The third gate electrode preferably has a region overlapping with the first gate electrode through the first semiconductor layer. The third gate electrode preferably has a region overlapping with the first semiconductor layer through the third insulating layer.

[0019] In the semiconductor device, the second transistor preferably includes a first insulating layer, a third insulating layer, and a fourth gate electrode. The fourth gate electrode preferably has a region overlapping with the second gate electrode through the second semiconductor layer. The fourth gate electrode preferably has a region overlapping with the second semiconductor layer through the first insulating layer and the third insulating layer.

[0020] One embodiment of the present invention is a method for manufacturing a semiconductor device, including: forming an island-shaped first semiconductor layer over a substrate; forming a first insulating layer over the substrate and the first semiconductor layer; forming an island-shaped second semiconductor layer over the first insulating layer; forming a second insulating layer over the first insulating layer and the second semiconductor layer; and forming a first gate electrode and a second gate electrode over the second insulating layer. The first gate electrode has a region overlapping with the first semiconductor layer with the first insulating layer and the second insulating layer interposed therebetween, and the second gate electrode has a region overlapping with the second semiconductor layer with the second insulating layer interposed therebetween.

[0021] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device with stable electrical characteristics can be provided. Alternatively, a semiconductor device including different transistors over the same substrate can be provided. Alternatively, a novel semiconductor device can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0023] FIGS. 1A and 1B are diagrams showing an example of a configuration of a semiconductor device. FIGS. 2A to 2D are diagrams showing an example of a configuration of a semiconductor device. FIGS. 3A to 3D are diagrams showing an example of a configuration of a semiconductor device. FIGS. 4A to 4D are diagrams showing an example of a configuration of a semiconductor device. FIGS. 5A to 5D are diagrams showing an example of a configuration of a semiconductor device. FIGS. 6A and 6B are diagrams showing an example of a configuration of a semiconductor device. FIGS. 7A and 7B are diagrams showing an example of a configuration of a semiconductor device. FIGS. 8A and 8B are diagrams showing an example of a configuration of a semiconductor device. FIGS. 9A and 9B are diagrams showing an example of a configuration of a semiconductor device. FIGS. 10A to 10D are diagrams showing an example of a configuration of a semiconductor device. FIGS. 11A and 11B are diagrams showing an example of a configuration of a semiconductor device. FIGS. 12A to 12D are diagrams showing an example of a configuration of a semiconductor device. FIGS. 13A and 13B are diagrams showing an example of a configuration of a semiconductor device. FIGS. 14A to 14D are diagrams showing an example of a configuration of a semiconductor device. FIGS. 15A and 15B are diagrams showing an example of a configuration of a semiconductor device. FIGS. 16A and 16B are diagrams showing an example of a configuration of a semiconductor device. FIGS. 17A and 17B are diagrams illustrating a structural example of a semiconductor device. FIGS. 18A and 18B are diagrams illustrating a structural example of a semiconductor device. FIGS. 19A and 19B are diagrams illustrating a structural example of a semiconductor device. FIGS. 20A to 20C are diagrams illustrating a structural example of a semiconductor device. FIGS. 21A to 21C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 22A to 22C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 23A to 23C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 24A to 24C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 25A to 25C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 26A and 26B are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 27A and 27B are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 28A and 28B are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 29A and 29B are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 30A to 30C are diagrams illustrating a method for manufacturing a semiconductor device. 31A and 31B are diagrams illustrating a manufacturing method of a semiconductor device. FIG. 32 is a diagram illustrating a structural example of a display device. FIG. 33A and 33B are diagrams illustrating a structural example of a display device. FIG. 34 is a diagram illustrating a structural example of a display device.35A to 35D are diagrams showing example pixel arrangements. FIG. 36A is a top view showing an example of a display device. FIG. 36B is a cross-sectional view showing an example of a display device. FIGS. 37A to 37C are cross-sectional views showing an example of a display device. FIGS. 38A and 38B are cross-sectional views showing an example of a display device. FIGS. 39A to 39C are cross-sectional views showing an example of a display device. FIGS. 40A to 40F are cross-sectional views showing an example of a display device. FIG. 41 is a perspective view showing an example of a display device. FIG. 42 is a cross-sectional view showing an example of a display device. FIGS. 43A to 43F are diagrams showing example configurations of light-emitting devices. FIGS. 44A and 44B are diagrams showing an example of an electronic device. FIGS. 45A to 45D are diagrams showing an example of an electronic device. FIGS. 46A to 46F are diagrams showing an example of an electronic device. FIG. 47 is a diagram showing measurement results of Id-Vg characteristics. FIG. 48 is a diagram showing measurement results of reliability. FIGS. 49A and 49B are diagrams showing measurement results of reliability. 50A and 50B are diagrams showing the measurement results of Id-Vg characteristics.

[0024] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0026] In each figure described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, is not necessarily limited to that scale.

[0027] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0028] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0029] The functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0030] In this specification and the like, either the source or the drain of a transistor may be referred to as a “first electrode,” and the other of the source or the drain may be referred to as a “second electrode.” The gate may also be referred to as a “gate” or a “gate electrode.”

[0031] In this specification, "electrically connected" includes a connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, capacitive elements, and other elements with various functions.

[0032] In this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" may be interchangeable with the terms "conductive film" and "insulating film."

[0033] In this specification, the EL layer refers to a layer (also referred to as a light-emitting layer) that is provided between a pair of electrodes of a light-emitting device (also referred to as a light-emitting element) and contains at least a light-emitting substance, or a stack including a light-emitting layer.

[0034] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface, and therefore the display panel is one aspect of an output device.

[0035] In this specification and the like, a display panel having a connector such as an FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package) attached to its substrate, or a substrate having an IC mounted on it using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, a display module, or simply a display panel.

[0036] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described.

[0037] A semiconductor device according to one embodiment of the present invention includes at least two types of transistors (a first transistor and a second transistor) over a substrate. The first transistor has a channel formation region in a first semiconductor layer, and the second transistor has a channel formation region in a second semiconductor layer. The first semiconductor layer and the second semiconductor layer can each be formed using a metal oxide. The first semiconductor layer and the second semiconductor layer can each be formed using a metal oxide containing indium.

[0038] The first semiconductor layer and the second semiconductor layer preferably contain metal oxides that differ in one or more of composition, thickness, crystallinity, carrier concentration, and film quality. In particular, the first semiconductor layer and the second semiconductor layer preferably contain metal oxides that differ in composition. The compositions of the first semiconductor layer and the second semiconductor layer significantly affect the electrical characteristics and reliability of the first transistor and the second transistor, respectively.

[0039] For example, the ratio of the number of indium atoms to the number of atoms of the metal element contained in the second semiconductor layer is preferably higher than that in the first semiconductor layer. With such a structure, the second transistor can have a higher operating speed and a larger on-state current than the first transistor. When the semiconductor device according to one embodiment of the present invention is applied to a display device, the second transistor can be used in a source driver (also referred to as a source line driver circuit or a signal line driver circuit) or a demultiplexer circuit, which require high-speed switching operation.

[0040] On the other hand, pixel circuits and gate drivers (also referred to as gate line driver circuits or scanning line driver circuits) of display devices are not required to have high-speed switching operations compared to source drivers or demultiplexer circuits. Furthermore, if these circuits are configured using second transistors, the transistors must be large (e.g., their channel lengths must be long) to obtain appropriate electrical characteristics, resulting in a large circuit area. Therefore, by configuring the pixel circuits and gate drivers using first transistors with smaller on-state currents than the second transistors, the areas occupied by the pixel circuits and gate drivers can be reduced. The reduced area occupied by the pixel circuits allows for a high-resolution display device. Furthermore, the reduced area occupied by the gate drivers allows for a display device with a narrow frame. In this way, a so-called on-panel display device can be realized, in which pixel circuits and driver circuits having multiple types of transistors are fabricated on the same substrate.

[0041] A more specific example will be described below with reference to the drawings.

[0042] 1A and 1B are schematic cross-sectional views of a transistor 100 and a transistor 200, which are provided over a substrate 102. FIG. 1A is a schematic cross-sectional view of the transistor 100 and the transistor 200 in the channel length direction, and FIG. 1B is a schematic cross-sectional view of the transistor 100 and the transistor 200 in the channel width direction.

[0043] The transistor 100 includes a semiconductor layer 108, an insulating layer 117, an insulating layer 110, and a conductive layer 112 stacked in this order. Parts of the insulating layer 117 and the insulating layer 110 function as gate insulating layers of the transistor 100. The conductive layer 112 functions as a gate electrode of the transistor 100. The transistor 100 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer 108.

[0044] The transistor 200 includes a semiconductor layer 208, an insulating layer 110, and a conductive layer 212 stacked in this order. Part of the insulating layer 110 functions as a gate insulating layer of the transistor 200. The conductive layer 212 functions as a gate electrode of the transistor 200. The transistor 200 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer 208. The transistor 200 differs from the transistor 100 in the surface where the semiconductor layer is formed. Furthermore, the transistor 200 differs from the transistor 100 in the configuration of the gate insulating layer.

[0045] The components of the transistor 100 and the transistor 200 other than the semiconductor layers can be formed in the same process, which can prevent an increase in the number of processes even when two types of transistors are mixed.

[0046] The semiconductor layer 108 is provided on and in contact with the substrate 102. An insulating layer 117 is provided in contact with the top surface of the substrate 102 and the top surface and side surfaces of the semiconductor layer 108. A semiconductor layer 208 is provided on and in contact with the insulating layer 117. That is, the semiconductor layer 208 is provided on a surface different from that of the semiconductor layer 108. The insulating layer 117 functions as a base film in the transistor 200. An insulating layer 110 is provided in contact with the top surface of the insulating layer 117 and the top surface and side surfaces of the semiconductor layer 208. A conductive layer 112 and a conductive layer 212 are provided on and in contact with the insulating layer 110. The conductive layer 112 has a region overlapping with the semiconductor layer 108 with the insulating layer 117 and the insulating layer 110 interposed therebetween. The conductive layer 212 has a region overlapping with the semiconductor layer 208 with the insulating layer 110 interposed therebetween.

[0047] 1A, the transistor 100 and the transistor 200 preferably further include an insulating layer 118. The insulating layer 118 is provided to cover the insulating layer 110, the conductive layer 112, and the conductive layer 212 and functions as a protective layer to protect the transistor 100 and the transistor 200.

[0048] The transistor 100 may include a conductive layer 120a and a conductive layer 120b over the insulating layer 118. The conductive layer 120a functions as one of a source electrode and a drain electrode of the transistor 100, and the conductive layer 120b functions as the other of the source electrode and the drain electrode of the transistor 100. The conductive layer 120a and the conductive layer 120b are electrically connected to the low-resistance region 108N of the semiconductor layer 108 through an opening 141a or an opening 141b provided in the insulating layer 118, the insulating layer 110, and the insulating layer 117, respectively.

[0049] The transistor 200 may include a conductive layer 220a and a conductive layer 220b over the insulating layer 118. The conductive layer 220a functions as one of a source electrode and a drain electrode of the transistor 200, and the conductive layer 220b functions as the other of the source electrode and the drain electrode of the transistor 200. The conductive layer 220a and the conductive layer 220b are electrically connected to the low-resistance region 208N of the semiconductor layer 208 through an opening 241a and an opening 241b provided in the insulating layer 118 and the insulating layer 110, respectively.

[0050] The semiconductor layer 108 of the transistor 100 and the semiconductor layer 208 of the transistor 200 each preferably contain a metal oxide (also referred to as an oxide semiconductor). That is, the transistor 100 and the transistor 200 preferably use transistors in which a channel formation region is formed using a metal oxide (hereinafter also referred to as OS transistors). Alternatively, the semiconductor layer 108 and the semiconductor layer 208 may each contain silicon. Examples of silicon include amorphous silicon and crystalline silicon (for example, low-temperature polysilicon and single-crystal silicon). Note that the semiconductor layer 108 and the semiconductor layer 208 may be made of different materials.

[0051] The band gap of each of the metal oxides in the semiconductor layer 108 and the semiconductor layer 208 is preferably 2.0 eV or more, more preferably 2.5 eV or more. Using a metal oxide with a wide band gap allows the OS transistor to have an extremely small off-state current. For example, charge accumulated in a capacitor connected in series with the OS transistor can be held for a long period of time. Furthermore, the use of an OS transistor enables a semiconductor device with low power consumption.

[0052] OS transistors have small variations in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include X-rays and neutron rays.

[0053] Here, a description will be given of the composition of a metal oxide that can be applied to the semiconductor layer 108 and the semiconductor layer 208. Note that the composition of a metal oxide may be substituted for the composition of a semiconductor layer.

[0054] The metal oxide preferably contains at least indium or zinc. The metal oxide more preferably contains indium and zinc. For example, the metal oxide preferably contains indium, an element M (wherein M is one or more elements selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc.

[0055] Examples of metal oxides that can be used include indium oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide), and indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, indium tin oxide containing silicon can be used.

[0056] The element M is preferably one or more elements selected from gallium, aluminum, yttrium, and tin, and more preferably gallium. Note that in this specification and the like, a metal oxide having indium, the element M, and zinc may be referred to as an In-M-Zn oxide.

[0057] Here, the compositions of the semiconductor layer 108 and the semiconductor layer 208 greatly affect the electrical characteristics and reliability of the transistor 100 and the transistor 200, respectively.

[0058] For example, by increasing the content of indium in the semiconductor layer, a transistor with a large on-state current can be realized.

[0059] When an In-Zn oxide is used for the semiconductor layer, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, metal oxides in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or any of these approximate values, can be used.

[0060] When an In-Sn oxide is used for the semiconductor layer, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than that of tin. For example, metal oxides in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or any of these approximate values, can be used.

[0061] When an In-Sn-Zn oxide is used for the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than that of tin can be used.Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of tin.For example, the atomic ratios of metal elements may be In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn=6:1:6, In :Sn:Zn=10:1:3, In:Sn:Zn=10:1:6, In:Sn:Zn=10:1:7, In:Sn:Zn=10:1:8, In:Sn:Zn=5:2:5, In:Sn:Zn=10:1:10, In:Sn:Zn=20:1:10, In:Sn:Zn=40:1:10, or metal oxides thereof having a ratio close to these can be used.

[0062] When an In-Al-Zn oxide is used for the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than that of aluminum can be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of aluminum. For example, the atomic ratios of metal elements may be In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=6:1:6, In In:Al:Zn=10:1:3, In:Al:Zn=10:1:6, In:Al:Zn=10:1:7, In:Al:Zn=10:1:8, In:Al:Zn=5:2:5, In:Al:Zn=10:1:10, In:Al:Zn=20:1:10, In:Al:Zn=40:1:10, or metal oxides thereof having a similar ratio can be used.

[0063] When an In-Ga-Zn oxide is used for the semiconductor layer, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of gallium can be used.Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium.For example, the semiconductor layer may have an atomic ratio of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, or In:Ga:Zn=6:1:6. , In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides in the vicinity of these can be used.

[0064] When an In-M-Zn oxide is used for the semiconductor layer, a metal oxide can be used in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of element M. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M. For example, the semiconductor layer may have atomic ratios of metal elements of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, or In:M:Zn=6:1:6. , In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides in the vicinity of these can be used.

[0065] When a plurality of metal elements are contained as the element M, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned ranges.

[0066] The semiconductor layer preferably uses a metal oxide in which the ratio of the number of indium atoms to the number of atoms of the contained metal elements is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In-Ga-Zn oxide is used for the semiconductor layer, the ratio of the number of indium atoms to the total number of indium, gallium, and zinc atoms is preferably in the above-mentioned range.

[0067] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0068] By increasing the content of indium in the semiconductor layer, a transistor with a large on-state current can be obtained. By applying the transistor to a transistor that is required to have a high on-state current, a semiconductor device with excellent electrical characteristics can be obtained.

[0069] The composition of the metal oxide can be analyzed by, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0070] In this specification, a "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio is described as In:M:Zn = 4:2:3 or a composition thereabout, this includes a case where, when the atomic ratio of indium is 4, the atomic ratio of M is 1 or more and 3 or less, and the atomic ratio of zinc is 2 or more and 4 or less. Furthermore, when an atomic ratio is described as In:M:Zn = 5:1:6 or a composition thereabout, this includes a case where, when the atomic ratio of indium is 5, the atomic ratio of M is more than 0.1 and 2 or less, and the atomic ratio of zinc is 5 or more and 7 or less. Furthermore, when an atomic ratio is described as In:M:Zn = 1:1:1 or a composition thereabout, this includes a case where, when the atomic ratio of indium is 1, the atomic ratio of M is more than 0.1 and 2 or less, and the atomic ratio of zinc is more than 0.1 and 2 or less.

[0071] When a metal oxide is formed by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be about 40% to 90% of the atomic ratio of zinc contained in the target.

[0072] Now, the reliability of the transistor will be described.

[0073] One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which the transistor is held in a state in which an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate relative to the source potential and drain potential and the transistor is held at a high temperature is called a Positive Bias Temperature Stress (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate and the transistor is held at a high temperature is called a Negative Bias Temperature Stress (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and an NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0074] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows). Therefore, the amount of variation in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0075] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS test can be obtained. Furthermore, when using a metal oxide that contains gallium, it is preferable to make the gallium content lower than the indium content. This allows for a highly reliable transistor to be realized.

[0076] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The higher the defect level density, the more significant the degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0077] The following is a possible reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in the semiconductor layer has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage.

[0078] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than that of gallium can be used for the semiconductor layer. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In > Ga and Zn > Ga for the semiconductor layer.

[0079] For example, the semiconductor layer may have the following atomic ratios of metal elements: In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1: In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides thereof can be used.

[0080] For the semiconductor layer, it is preferable to use a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is more than 0 atomic % and 50 atomic % or less, preferably 0.1 atomic % to 40 atomic % or less, more preferably 0.1 atomic % to 35 atomic % or less, more preferably 0.1 atomic % to 30 atomic % or less, more preferably 0.1 atomic % to 25 atomic % or less, more preferably 0.1 atomic % to 20 atomic % or less, more preferably 0.1 atomic % to 15 atomic % or less, and more preferably 0.1 atomic % to 10 atomic % or less. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be obtained. Note that by including gallium in the semiconductor layer, oxygen deficiency (V Ｏ ) is less likely to occur.

[0081] A metal oxide that does not contain gallium may be used for the semiconductor layer. For example, In—Zn oxide may be used for the semiconductor layer. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide results in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Furthermore, a metal oxide that does not contain gallium or zinc, such as indium oxide, may be used for the semiconductor layer. By using a metal oxide that does not contain gallium, fluctuations in threshold voltage, particularly in a PBTS test, can be made extremely small.

[0082] For example, the semiconductor layer can be made of an oxide containing indium and zinc, in which the atomic ratio of the metal elements is, for example, In:Zn=2:3, In:Zn=4:1, or a ratio close to these values.

[0083] Although gallium has been used as a representative example in the description, the present invention can also be applied to a case where element M is used instead of gallium. For the semiconductor layer, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.

[0084] By reducing the content of element M in the semiconductor layer, a transistor having high reliability against application of a positive bias can be obtained. By applying the transistor to a transistor that is required to have high reliability against application of a positive bias, a semiconductor device having high reliability can be obtained.

[0085] Next, the reliability of the transistor against light will be described.

[0086] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0087] Increasing the content of element M in the semiconductor layer can provide a transistor with high reliability against light. That is, a transistor with a small variation in threshold voltage in an NBTIS test can be provided. Specifically, a metal oxide in which the atomic ratio of element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in an NBTIS test. The band gap of the metal oxide in the semiconductor layer is preferably 2.0 eV or more, more preferably 2.5 eV or more, even more preferably 3.0 eV or more, still more preferably 3.2 eV or more, even more preferably 3.3 eV or more, still more preferably 3.4 eV or more, and even more preferably 3.5 eV or more.

[0088] For example, the semiconductor layer can be made of metal oxides having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or similar ratios.

[0089] For the semiconductor layer, a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0090] When an In—Ga—Zn oxide is used for the semiconductor layer, a metal oxide having an atomic ratio of indium to gallium equal to or less than that of gallium can be used. For example, metal oxides having an atomic ratio of metal elements of In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or similar can be used.

[0091] For the semiconductor layer, a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is 20 atomic % or more and 60 atomic % or less, preferably 20 atomic % or more and 50 atomic % or less, more preferably 30 atomic % or more and 50 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0092] By increasing the content of the element M in the semiconductor layer, a transistor with high reliability against light can be obtained. By applying the transistor to a transistor that is required to have high reliability against light, a semiconductor device with high reliability can be obtained.

[0093] Here, the semiconductor layer 108 and the semiconductor layer 208 preferably contain metal oxides having different compositions. The semiconductor layer 108 and the semiconductor layer 208 can be formed by processing metal oxide films having different compositions. A semiconductor device according to one embodiment of the present invention includes a plurality of transistors having semiconductor layers with different compositions over the same substrate, and components other than the semiconductor layers can be formed in the same process.

[0094] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0095] The following describes an example in which the transistor 200 is used as a transistor that requires a large on-state current. For example, when In—Ga—Zn oxide is used for both the semiconductor layer 108 and the semiconductor layer 208, the semiconductor layer 208 can be made of a metal oxide in which the ratio of the number of indium atoms to the number of atoms of metal elements contained therein is higher than that of the semiconductor layer 108.

[0096] Similarly, when an In—Ga—Zn oxide is used for the semiconductor layer 108 and a metal oxide containing indium other than an In—Ga—Zn oxide is used for the semiconductor layer 208, a metal oxide having a higher ratio of the number of indium atoms to the number of atoms of the metal element compared to the semiconductor layer 108 can be used for the semiconductor layer 208.

[0097] A metal oxide containing indium other than In—Ga—Zn oxide can also be used for the semiconductor layer 108. In this case, similarly, the semiconductor layer 208 can be made of a metal oxide in which the ratio of the number of indium atoms to the number of metal element atoms is higher than that of the semiconductor layer 108.

[0098] Alternatively, the semiconductor layer 108 may be formed using a metal oxide in which the ratio of the number of indium atoms to the number of atoms of the metal element contained therein is higher than that of the semiconductor layer 208 .

[0099] The following describes an example in which the transistor 200 is used as a transistor that requires high reliability when a positive bias is applied. For example, when In—Ga—Zn oxide is used for both the semiconductor layer 108 and the semiconductor layer 208, the semiconductor layer 208 can be made of a metal oxide having a lower ratio of gallium atoms to the number of atoms of metal elements contained therein than the semiconductor layer 108. For example, the semiconductor layer 108 may be made of In—Ga—Zn oxide, and the semiconductor layer 208 may be made of a metal oxide that does not contain gallium.

[0100] The semiconductor layer 208 may be made of a metal oxide in which the ratio of the number of indium atoms to the number of atoms of the contained metal element is higher and the ratio of the number of atoms of the element M is lower than that of the semiconductor layer 108. With such a structure, the transistor 200 can have a large on-state current and high reliability against a positive bias.

[0101] Alternatively, the semiconductor layer 108 may use a metal oxide in which the ratio of the number of atoms of the element M to the number of atoms of the contained metal element is lower than that of the semiconductor layer 208. Furthermore, the semiconductor layer 108 may use a metal oxide in which the ratio of the number of atoms of indium to the number of atoms of the contained metal element is higher and the ratio of the number of atoms of the element M is lower than that of the semiconductor layer 208.

[0102] The following describes an example in which the transistor 200 is used as a transistor that is required to have high reliability against light. The semiconductor layer 208 can be made of a metal oxide having a higher ratio of the number of atoms of element M to the number of atoms of the metal element contained therein, compared to the semiconductor layer 108. For example, the semiconductor layer 208 can be made of In—Ga—Zn oxide, and the semiconductor layer 108 can be made of a metal oxide that does not contain gallium.

[0103] Alternatively, the semiconductor layer 108 may be made of a metal oxide in which the ratio of the number of atoms of the element M to the number of atoms of the contained metal element is higher than that of the semiconductor layer 208 .

[0104] An example will be described in which the transistor 100 is used as a transistor that requires high reliability against light, and the transistor 200 is used as a transistor that requires a large on-state current. The semiconductor layer 108 can be made of a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the metal element contained therein is higher than that in the semiconductor layer 208. The semiconductor layer 208 can be made of a metal oxide in which the ratio of the number of atoms of indium to the number of atoms of the metal element contained therein is higher than that in the semiconductor layer 108.

[0105] The semiconductor layer 108 and the semiconductor layer 208 are not limited to being of the same composition, and metal oxides that differ in one or more of thickness, crystallinity, carrier concentration, and film quality may be used. For example, the semiconductor layer 108 and the semiconductor layer 208 may have different compositions, thicknesses, or film formation conditions so that the on-state current of the transistor 200 is larger than that of the transistor 100.

[0106] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a pair of low-resistance regions 108N sandwiching the region. The region of the semiconductor layer 108 overlapping with the conductive layer 112 functions as a channel formation region of the transistor 100. The pair of low-resistance regions 108N function as a source region and a drain region of the transistor 100. Similarly, the semiconductor layer 208 has a channel formation region overlapping with the conductive layer 212 and a pair of low-resistance regions 208N sandwiching the channel formation region.

[0107] In the transistor 100, the low-resistance region 108N can also be referred to as a region having lower resistance, a region having a higher carrier concentration, a region having a higher oxygen vacancy density, a region having a higher impurity concentration, or an n-type region than the channel formation region of the transistor 100. Similarly, in the transistor 200, the low-resistance region 208N can also be referred to as a region having lower resistance, a region having a higher carrier concentration, a region having a higher oxygen vacancy density, a region having a higher impurity concentration, or an n-type region than the channel formation region of the transistor 200.

[0108] The low-resistance region 108N and the low-resistance region 208N are regions containing impurity elements. Examples of such impurity elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. The low-resistance region 108N and the low-resistance region 208N preferably contain boron or phosphorus. The low-resistance region 108N and the low-resistance region 208N may contain two or more of the above elements. The low-resistance region 108N and the low-resistance region 208N may contain different impurity elements.

[0109] The low resistance region 108N and the low resistance region 208N can be formed by adding impurities through the insulating layer 110 using the conductive layer 112 or the conductive layer 212 as a mask, for example.

[0110] The low resistance region 108N and the low resistance region 208N each have an impurity concentration of 1×10 １９ atoms / cm ３ That's it, 1 x 10 ２３ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ That's it, 5 x 10 ２２ atoms / cm ３ or less, more preferably 1 × 10 ２０ atoms / cm ３ That's it, 1 x 10 ２２ atoms / cm ３ It is preferred to include a region in which:

[0111] The concentrations of impurities contained in the low-resistance region 108N and the low-resistance region 208N can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), etc. When XPS analysis is used, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front side or the back side with XPS analysis.

[0112] An enlarged view of a region P indicated by a dashed line in Fig. 1A is shown in Fig. 2A. An enlarged view of a region Q indicated by a dashed line in Fig. 1A is shown in Fig. 2B.

[0113] The insulating layer 110 and the insulating layer 117 in contact with the semiconductor layer 108 or the semiconductor layer 208 preferably contain an oxide or an oxynitride. The insulating layer 110 and the insulating layer 117 may each have a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 and the insulating layer 117 may each include an insulating film capable of releasing oxygen. For example, oxygen can be supplied to the insulating layer by forming the insulating layer in an oxygen atmosphere, performing heat treatment in an oxygen atmosphere after the insulating layer is formed, performing plasma treatment in an oxygen atmosphere after the insulating layer is formed, or forming an oxide film or an oxynitride film on the insulating layer in an oxygen atmosphere. Note that in each of the above treatments for supplying oxygen, an oxidizing gas (e.g., one or more of nitrous oxide and ozone) may be used instead of or in addition to oxygen.

[0114] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0115] The insulating layer 110 and the insulating layer 117 can be formed by, for example, sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like. CVD methods include, for example, plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD). In particular, it is preferable to form the insulating layer 110 by plasma enhanced CVD (PECVD).

[0116] The insulating layer 110 and the insulating layer 117 can each be an insulating film containing one or more of, for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. Note that the insulating layer 110 may have a stacked structure of two layers or a stacked structure of three or more layers. Similarly, the insulating layer 117 may have a stacked structure of two layers or a stacked structure of three or more layers. Furthermore, different materials may be used for the insulating layer 110 and the insulating layer 117.

[0117] The insulating layer 110 and the insulating layer 117 can be made of a material having a higher dielectric constant than silicon oxide and silicon oxynitride, respectively. For example, hafnium oxide can be used as a material having a high dielectric constant. This allows the insulating layer 110 and the insulating layer 117 to have a thicker film thickness, thereby suppressing leakage current due to tunnel current. In particular, crystalline hafnium oxide is preferable because it has a higher dielectric constant than amorphous hafnium oxide.

[0118] 2A , in the transistor 100, the thickness TT100 of the gate insulating layer is the sum of the thicknesses of the insulating layer 110 and the insulating layer 117. As shown in FIG. 2B , in the transistor 200, the thickness TT200 of the gate insulating layer is the thickness of the insulating layer 110. In other words, the thickness TT100 of the gate insulating layer of the transistor 100 is thicker than the thickness TT200 of the gate insulating layer of the transistor 200. In other words, the thickness TT200 of the gate insulating layer of the transistor 200 is thinner than the thickness TT100 of the gate insulating layer of the transistor 100.

[0119] Here, by increasing the thickness of the gate insulating layer, the gate breakdown voltage of the transistor can be increased. On the other hand, by decreasing the thickness of the gate insulating layer, the on-state current of the transistor can be increased and the operating speed can be increased. That is, the transistor 100 having a high gate breakdown voltage and the transistor 200 having a high on-state current and a high operating speed can be fabricated on the same substrate. For example, by applying the transistor 100 to a transistor to which a high voltage is applied and the transistor 200 to a transistor that requires high-speed operation, a semiconductor device that achieves both high-speed operation and high reliability can be obtained.

[0120] The thickness TT200 of the gate insulating layer of transistor 200 is preferably 50% or more and less than 100% of the thickness TT100 of the gate insulating layer of transistor 100, more preferably 60% or more and less than 100%, even more preferably 60% or more and 95% or less, even more preferably 70% or more and 95% or less, even more preferably 80% or more and 95% or less, and even more preferably 80% or more and 90% or less.

[0121] As described above, the composition of the semiconductor layer significantly affects the electrical characteristics and reliability of the transistor 100 or the transistor 200. For example, by using a metal oxide with a high indium content for the semiconductor layer 208 of the transistor 200, which has a thin gate insulating layer, the on-state current of the transistor 200 can be further increased. Furthermore, it is preferable that the indium content of the metal oxide used for the semiconductor layer 208 be higher than that of the semiconductor layer 108. In this way, the electrical characteristics and reliability of the transistor can be further improved by combining the composition of the semiconductor layer and the thickness of the gate insulating layer, and a semiconductor device with excellent electrical characteristics and high reliability can be obtained.

[0122] Alternatively, by using a metal oxide having a high indium content for the semiconductor layer 108 of the transistor 100 having a thick gate insulating layer, the transistor can have a high gate withstand voltage and a large on-state current. Furthermore, the indium content of the metal oxide used for the semiconductor layer 108 is preferably higher than that of the semiconductor layer 208.

[0123] For example, by using a metal oxide having a low content of element M in the semiconductor layer 208 of the transistor 200 having a thin gate insulating layer, the transistor can have a large on-state current and high reliability against application of a positive bias. Furthermore, the content of element M in the metal oxide used in the semiconductor layer 208 is preferably lower than that of the semiconductor layer 108.

[0124] Alternatively, by using a metal oxide having a low content of the element M for the semiconductor layer 108 of the transistor 100 having a thick gate insulating layer, the transistor can have a high gate withstand voltage and high reliability against application of a positive bias. Furthermore, the content of the element M in the metal oxide used for the semiconductor layer 108 is preferably lower than that of the semiconductor layer 208.

[0125] For example, by using a metal oxide having a high content of element M in the semiconductor layer 208 of the transistor 200 having a thin gate insulating layer, the transistor can have a large on-state current and high reliability against light. Furthermore, the content of element M in the metal oxide used in the semiconductor layer 208 is preferably higher than that of the semiconductor layer 108.

[0126] Alternatively, by using a metal oxide having a high content of element M in the semiconductor layer 108 of the transistor 100 having a thick gate insulating layer, the transistor can have a high gate breakdown voltage and high reliability against light. Furthermore, the content of element M in the metal oxide used in the semiconductor layer 108 is preferably higher than that in the semiconductor layer 208.

[0127] Increasing the thickness of the insulating layer 117 can increase the difference between the thickness TT100 of the gate insulating layer of the transistor 100 and the thickness TT200 of the gate insulating layer of the transistor 200. On the other hand, decreasing the thickness of the insulating layer 117 can reduce the difference between the thickness TT100 of the gate insulating layer of the transistor 100 and the thickness TT200 of the gate insulating layer of the transistor 200. In this way, the thicknesses of the gate insulating layers of the transistors 100 and 200 can be easily adjusted according to the characteristics required of the transistors 100 and 200 without significantly increasing the number of processes.

[0128] The thicknesses of the gate insulating layers of the transistors 100 and 200 can also be adjusted by the thickness of the insulating layer 110. By reducing the thickness of the insulating layer 110, the difference between the thickness TT100 of the gate insulating layer of the transistor 100 and the thickness TT200 of the gate insulating layer of the transistor 200 can be increased. On the other hand, by increasing the thickness of the insulating layer 110, the difference between the thickness TT100 of the gate insulating layer of the transistor 100 and the thickness TT200 of the gate insulating layer of the transistor 200 can be reduced.

[0129] Metal oxides having the same composition may be used for the semiconductor layer 108 and the semiconductor layer 208. As described above, the electrical characteristics (e.g., on-state current) and reliability (e.g., gate breakdown voltage) vary depending on the thickness of the gate insulating layer. Therefore, by differentiating the thicknesses of the gate insulating layers of the transistors 100 and 200 depending on the desired electrical characteristics and reliability, a semiconductor device with excellent electrical characteristics and good reliability can be obtained.

[0130] 2C and 2D , the thickness of the insulating layer 110 in a region that does not overlap with the conductive layer 112 may be thinner than the thickness of the insulating layer 110 in a region that overlaps with the conductive layer 112. For example, when forming the conductive layer 112, the surface of the insulating layer 110 in a region that does not overlap with the conductive layer 112 may be removed, thereby reducing the thickness of the insulating layer 110 in that region. Similarly, the thickness of the insulating layer 110 in a region that does not overlap with the conductive layer 212 may be thinner than the thickness of the insulating layer 110 in a region that overlaps with the conductive layer 212. For example, when forming the conductive layer 212, the surface of the insulating layer 110 in a region that does not overlap with the semiconductor layer 208 may be removed, thereby reducing the thickness of the insulating layer 110 in that region.

[0131] In this specification and the like, the thickness of the gate insulating layer refers to the thickness of a region overlapping with a gate electrode. For example, the thickness TT100 of the gate insulating layer of the transistor 100 refers to the thickness of the gate insulating layer in a region overlapping with the conductive layer 112, that is, the sum of the thicknesses of the insulating layer 110 and the insulating layer 117 in the regions overlapping with the conductive layer 112. The thickness TT200 of the gate insulating layer of the transistor 200 refers to the thickness of the gate insulating layer in a region overlapping with the conductive layer 212, that is, the thickness of the insulating layer 110 in the region overlapping with the conductive layer 212.

[0132] The insulating layer 117 can function as an etching stopper to prevent the semiconductor layer 108 from being removed when the semiconductor layer 208 is formed. The insulating layer 117 preferably has a thickness that functions as an etching stopper, that is, a thickness that is sufficient to prevent the insulating layer 117 from being removed when the semiconductor layer 208 is formed. The thickness of the insulating layer 117 is preferably 2 nm to 200 nm, more preferably 2 nm to 150 nm, even more preferably 2 nm to 100 nm, still more preferably 5 nm to 100 nm, even more preferably 5 nm to 50 nm, still more preferably 5 nm to 30 nm, still more preferably 5 nm to 20 nm, even more preferably 5 nm to 15 nm, still more preferably 7 nm to 15 nm, and still more preferably 7 nm to 10 nm. Note that in this specification and the like, the thickness of the insulating layer 117 refers to the thickness of a region overlapping with the conductive layer 112.

[0133] An enlarged view of a region R indicated by a dashed line in Fig. 1A is shown in Fig. 3A. An enlarged view of a region S indicated by a dashed line in Fig. 1A is shown in Fig. 3B.

[0134] 3A and 3B , the insulating layer 117 has a region in contact with the top surface and side surface of the semiconductor layer 108. Because the insulating layer 117 is formed on the semiconductor layer 108, it is preferably formed under conditions that cause as little damage to the semiconductor layer 108 as possible. The insulating layer 110 has a region in contact with the top surface and side surface of the semiconductor layer 208. Because the insulating layer 110 is formed on the semiconductor layer 208, it is preferably formed under conditions that cause as little damage to the semiconductor layer 208 as possible.

[0135] The insulating layer 117 and the insulating layer 110 can each be formed under conditions where the film formation rate (also referred to as the film formation rate) is sufficiently low. By forming the insulating layer 117 under conditions that do not damage the semiconductor layer 108, the density of defect states at the interface between the semiconductor layer 108 and the insulating layer 117 can be reduced, thereby providing a highly reliable transistor 100. By forming the insulating layer 110 under conditions that do not damage the semiconductor layer 208, the density of defect states at the interface between the semiconductor layer 208 and the insulating layer 110 can be reduced, thereby providing a highly reliable transistor 200. Furthermore, damage to the semiconductor layer 108 through the insulating layer 117 can also be suppressed.

[0136] For example, when the insulating layer 117 and the insulating layer 110 are formed by a plasma CVD method, damage to the semiconductor layer 108 and the semiconductor layer 208 can be significantly reduced by forming them under low-power conditions. Furthermore, by reducing the ratio of the flow rate of the deposition gas to the total flow rate of the deposition gas (hereinafter simply referred to as the flow rate ratio), the film formation rate can be reduced, and a dense film with few defects can be formed. The insulating layer 117 can be formed under the same conditions as those for forming the insulating layer 110. Note that the insulating layer 117 may be formed under conditions different from those for forming the insulating layer 110.

[0137] 3C , the thickness of the substrate 102 in a region that does not overlap with the semiconductor layer 108 may be thinner than the thickness of the substrate 102 in a region that overlaps with the semiconductor layer 108. For example, when forming the semiconductor layer 108, the surface of the substrate 102 in a region that does not overlap with the semiconductor layer 108 may be removed, thereby reducing the thickness of the substrate 102 in that region. Also, as shown in FIG. 3D , the thickness of the insulating layer 117 in a region that does not overlap with the semiconductor layer 208 may be thinner than the thickness of the insulating layer 117 in a region that overlaps with the semiconductor layer 208. For example, when forming the semiconductor layer 208, the surface of the insulating layer 117 in a region that does not overlap with the semiconductor layer 208 may be removed, thereby reducing the thickness of the insulating layer 117 in that region.

[0138] 1A and the like show an example in which the thickness of the semiconductor layer 108 in the opening 141a is equal to the thickness of the semiconductor layer 108 in a region that does not overlap with the opening 141a, that is, the thickness of the semiconductor layer 108 in a region that is in contact with the conductive layer 120a is equal to the thickness of the semiconductor layer 108 in a region that is not in contact with the conductive layer 120a, but one embodiment of the present invention is not limited to this. The thickness of the semiconductor layer 108 in the opening 141a may be thinner than the thickness of the semiconductor layer 108 in a region that is not in contact with the conductive layer 120a, that is, the thickness of the semiconductor layer 108 in a region that is in contact with the conductive layer 120a may be thinner than the thickness of the semiconductor layer 108 in a region that is not in contact with the conductive layer 120a. The same applies to the thickness of the semiconductor layer 108 in the opening 141b.

[0139] The thickness of the semiconductor layer 208 in the opening 241a may be thinner than the thickness of the semiconductor layer 208 in a region that does not overlap with the opening 241a, that is, the thickness of the semiconductor layer 208 in a region that contacts the conductive layer 220a may be thinner than the thickness of the semiconductor layer 208 in a region that does not contact the conductive layer 220a. The same applies to the thickness of the semiconductor layer 208 in the opening 241b.

[0140] The conductive layers 112 and 212, which function as gate electrodes, are preferably formed using a low-resistance material. By using a low-resistance material for the gate electrode, parasitic resistance can be reduced, and a transistor having a large on-state current can be obtained. For example, it is preferable to use a conductive film containing a metal or an alloy as the conductive layers 112 and 212 because the electrical resistance can be reduced. Note that a conductive film containing an oxide may be used for the conductive layers 112 and 212. For example, when the semiconductor device according to one embodiment of the present invention is applied to a large display device or a high-resolution display device, signal delay can be suppressed by reducing wiring resistance, and high-speed driving can be achieved.

[0141] The conductive layer 112 and the conductive layer 212 can each be made of one or more selected from chromium, copper, aluminum, gold, silver, zinc, niobium, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt. The conductive layer 112 and the conductive layer 212 can each be made of an alloy containing the above-mentioned metal elements or an alloy combining the above-mentioned metal elements. Copper is particularly preferable because it has low resistance and is suitable for mass production.

[0142] The conductive layer 112 and the conductive layer 212 may each have a stacked structure. When the conductive layer 112 and the conductive layer 212 have a stacked structure, a second conductive layer is provided on the top or bottom, or both, of the low-resistance first conductive layer. The second conductive layer is preferably made of a conductive material that is less susceptible to oxidation (has oxidation resistance) than the first conductive layer. Furthermore, the second conductive layer is preferably made of a material that suppresses the diffusion of components of the first conductive layer. For example, the second conductive layer can be made of a metal oxide such as indium oxide, indium zinc oxide, indium tin oxide (ITO), silicon-containing indium tin oxide (ITSO), or zinc oxide, or a metal nitride such as titanium nitride, tantalum nitride, molybdenum nitride, or tungsten nitride.

[0143] The conductive layer 112 and the conductive layer 212 can each be formed using an oxide conductor or a metal oxide film such as In—Sn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Zn oxide, In—Sn—Si oxide, or In—Ga—Zn oxide.

[0144] Here, oxide conductors (OC) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is supplied to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0145] The conductive layer 112 and the conductive layer 212 may each have a stacked structure of a conductive film containing an oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced. In this case, a conductive film containing an oxide conductor is preferably used on the side in contact with the insulating layer that functions as a gate insulating film.

[0146] The conductive layer 112 can be formed using the same material as the conductive layer 212. The conductive layer 112 and the conductive layer 212 can be formed by processing a conductive film formed over the insulating layer 110. That is, the conductive layer 112 can be formed through the same process as the conductive layer 212. Note that the conductive layer 112 may be formed using a different material from the conductive layer 212. The conductive layer 112 may be formed through a different process from the conductive layer 212.

[0147] The conductive layers 120a, 120b, 220a, and 220b, which function as source and drain electrodes, can be formed using the same materials as those used for the conductive layer 112 or 212. The conductive layers 120a, 120b, 220a, and 220b can be formed using one or more materials selected from titanium, tungsten, tantalum, niobium, and molybdenum. In particular, a tantalum nitride film can be preferably used for the conductive layers 120a, 120b, 220a, and 220b. A tantalum nitride film is conductive, has high barrier properties against copper, oxygen, or hydrogen, and releases little hydrogen from itself. Therefore, the tantalum nitride film can be preferably used as a conductive film in contact with the semiconductor layer 108 or 208 or as a conductive film in the vicinity of the semiconductor layer 108 or 208.

[0148] The conductive layers 120a and 120b can be formed using the same material as the conductive layers 220a and 220b. The conductive layers 120a, 120b, 220a, and 220b can be formed by processing a conductive film formed over the insulating layer 118. That is, the conductive layers 120a and 120b can be formed through the same process as the conductive layers 220a and 220b. The conductive layers 120a and 120b may be formed using a different material from the conductive layers 220a and 220b. The conductive layers 120a and 120b may be formed through a different process from the conductive layers 220a and 220b.

[0149] The insulating layer 118, which functions as a protective layer, can be formed using one or both of an inorganic material and an organic material. Examples of inorganic materials that can be used include one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate. Examples of organic materials that can be used include one or more of an acrylic resin and a polyimide resin. Photosensitive materials may also be used as the organic material.

[0150] The insulating layer 118 can prevent impurities from outside the transistors 100 and 200 from diffusing into the transistors 100 and 200. Examples of such impurities include water and hydrogen. The insulating layer 118 can be preferably formed using an inorganic insulating material such as an oxide, an oxynitride, a nitride oxide, or a nitride.

[0151] 4A and 4B show a structure example different from the above-described transistors 100 and 200. Fig. 4A shows a cross-sectional view of the transistor 100A and the transistor 200A in the channel length direction, and Fig. 4B shows a cross-sectional view of the transistor 100A and the transistor 200A in the channel width direction.

[0152] The transistor 100A differs from the transistor 100 mainly in that the transistor 100A includes a conductive layer 106 and an insulating layer 103 between the substrate 102 and the semiconductor layer 108. Similarly, the transistor 200A differs from the transistor 200 mainly in that the transistor 200A includes a conductive layer 206, an insulating layer 103, and an insulating layer 117 between the substrate 102 and the semiconductor layer 208. The conductive layer 106 has a region that overlaps with the semiconductor layer 108 with the insulating layer 103 interposed therebetween and a region that overlaps with the conductive layer 112 with the semiconductor layer 108 interposed therebetween. The conductive layer 206 has a region that overlaps with the semiconductor layer 208 with the insulating layer 103 and the insulating layer 117 interposed therebetween and a region that overlaps with the conductive layer 212 with the semiconductor layer 208 interposed therebetween.

[0153] In the transistor 100A, the conductive layer 112 functions as a first gate electrode (also referred to as a top gate electrode), and the conductive layer 106 functions as a second gate electrode (also referred to as a bottom gate electrode). In the transistor 100A, the insulating layer 117 and part of the insulating layer 110 function as a first gate insulating layer, and part of the insulating layer 103 functions as a second gate insulating layer. The insulating layer 103 can be formed using a material that can be used for the insulating layer 110 or the insulating layer 117. The insulating layer 117 is provided in contact with a top surface of the insulating layer 103 and a top surface and side surfaces of the semiconductor layer 108.

[0154] In the transistor 200A, the conductive layer 212 functions as a first gate electrode (also referred to as a top gate electrode), and the conductive layer 206 functions as a second gate electrode (also referred to as a bottom gate electrode). In the transistor 200A, part of the insulating layer 110 functions as a first gate insulating layer, and parts of the insulating layer 117 and the insulating layer 103 function as second gate insulating layers.

[0155] A portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region of the transistor 100A. Note that for ease of explanation, the portion of the semiconductor layer 108 that overlaps with the conductive layer 112 will sometimes be referred to as a channel formation region hereinafter. However, in reality, a channel can also be formed in a portion that does not overlap with the conductive layer 112 but overlaps with the conductive layer 106 (a portion including the low-resistance region 108N). The same applies to the semiconductor layer 208 of the transistor 200A.

[0156] 4B , in the transistor 100A, the conductive layer 106 may be electrically connected to the conductive layer 112 through an opening 142 provided in the insulating layer 110, the insulating layer 117, and the insulating layer 103. This allows the conductive layer 106 and the conductive layer 112 to be applied with the same potential. Similarly, in the transistor 200A, the conductive layer 206 may be electrically connected to the conductive layer 212 through an opening 242 provided in the insulating layer 110, the insulating layer 117, and the insulating layer 103.

[0157] The conductive layer 106 and the conductive layer 206 can be formed using the same material as the conductive layer 112, the conductive layer 212, the conductive layer 120a, the conductive layer 120b, the conductive layer 220a, or the conductive layer 220b. In particular, it is preferable to use a material containing copper for the conductive layer 106 and the conductive layer 206 because this can reduce wiring resistance. The conductive layer 106 and the conductive layer 206 can be formed using the same material. The conductive layer 106 and the conductive layer 206 can be formed by processing the same conductive film. Note that the conductive layer 106 and the conductive layer 206 may be formed using different materials.

[0158] 4B , the conductive layer 112 and the conductive layer 106 preferably protrude outward beyond the end portions of the semiconductor layer 108 in the channel width direction of the transistor 100A. In this case, as shown in FIG. 4B , the entire semiconductor layer 108 in the channel width direction is covered with the conductive layer 112 and the conductive layer 106 via the insulating layer 110 and the insulating layer 103. Similarly, the semiconductor layer 208 of the transistor 200A is also covered with the conductive layer 212 and the conductive layer 206. Note that a transistor structure in which a channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode can be referred to as a surrounded channel (S-channel) structure.

[0159] The S-channel structure allows the semiconductor layer to be electrically surrounded by an electric field generated by a pair of gate electrodes. In this case, it is particularly preferable to apply the same potential to the pair of gate electrodes. This allows an electric field for inducing a channel in the semiconductor layer to be effectively applied, thereby increasing the on-state current of the transistor 100A and the transistor 200A. This also enables miniaturization of the transistor 100A and the transistor 200A. Furthermore, the transistors can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0160] Note that a structure in which the pair of gate electrodes is not connected may be used. In this case, a constant potential may be applied to one of the pair of gate electrodes, and a signal for driving the transistor 100A or the transistor 200A may be applied to the other. In this case, the threshold voltage when the transistor 100A or the transistor 200A is driven by the other gate electrode can also be controlled by the potential applied to one gate electrode.

[0161] FIG. 4C shows an enlarged view of region P indicated by the dashed-dotted line in FIG. 4A . FIG. 4D shows an enlarged view of region Q indicated by the dashed-dotted line in FIG. 4A . As shown in FIG. 4C , in transistor 100A, the thickness TT100 of the first gate insulating layer is the sum of the thicknesses of insulating layer 110 and insulating layer 117. The thickness TB100 of the second gate insulating layer is the thickness of insulating layer 103. As shown in FIG. 4D , in transistor 200A, the thickness TT200 of the first gate insulating layer is the thickness of insulating layer 110. The thickness TB200 of the second gate insulating layer is the sum of the thicknesses of insulating layer 103 and insulating layer 117.

[0162] The thickness TT100 of the first gate insulating layer of the transistor 100A is thicker than the thickness TT200 of the first gate insulating layer of the transistor 200A. On the other hand, the thickness TB100 of the second gate insulating layer of the transistor 100A is thinner than the thickness TB200 of the second gate insulating layer of the transistor 200A.

[0163] The thickness TB100 of the second gate insulating layer of transistor 100A is preferably 50% or more and less than 100% of the thickness TB200 of the second gate insulating layer of transistor 200A, more preferably 60% or more and less than 100%, even more preferably 60% or more and 95% or less, even more preferably 70% or more and 95% or less, even more preferably 80% or more and 95% or less, and even more preferably 80% or more and 90% or less.

[0164] Increasing the thickness of the insulating layer 117 can increase the difference between the thickness TT100 of the first gate insulating layer of the transistor 100A and the thickness TT200 of the first gate insulating layer of the transistor 200A. In addition, increasing the thickness of the insulating layer 117 can increase the difference between the thickness TB100 of the second gate insulating layer of the transistor 100A and the thickness TB200 of the second gate insulating layer of the transistor 200A.

[0165] On the other hand, by reducing the thickness of the insulating layer 117, the difference between the thickness TT100 of the first gate insulating layer of the transistor 100A and the thickness TT200 of the first gate insulating layer of the transistor 200A can be reduced. Furthermore, by reducing the thickness of the insulating layer 117, the difference between the thickness TB100 of the second gate insulating layer of the transistor 100A and the thickness TB200 of the second gate insulating layer of the transistor 200A can be reduced. In this way, the thicknesses of the first gate insulating layer and the second gate insulating layer of the transistor 100A and the transistor 200A can be easily adjusted according to the characteristics required for the transistors 100A and 200A without significantly increasing the number of processes.

[0166] The thicknesses of the second gate insulating layers of transistors 100A and 200A can also be adjusted by the thickness of insulating layer 103. By reducing the thickness of insulating layer 103, the difference between the thickness TB100 of the second gate insulating layer of transistor 100 and the thickness TB200 of the second gate insulating layer of transistor 200 can be increased. On the other hand, by increasing the thickness of insulating layer 103, the difference between the thickness TB100 of the second gate insulating layer of transistor 100 and the thickness TB200 of the second gate insulating layer of transistor 200 can be reduced.

[0167] 5A is an enlarged view of a region R indicated by a dashed-dotted line in FIG. 4A . FIG. 5B is an enlarged view of a region S indicated by a dashed-dotted line in FIG. 4A . As shown in FIG. 5A and FIG. 5B , the insulating layer 117 has regions in contact with the upper surface and side surfaces of the semiconductor layer 108, the lower surface of the semiconductor layer 208, the lower surface of the insulating layer 110, and the upper surface of the insulating layer 103.

[0168] 5C and 5D , the thickness of the insulating layer 103 in a region that does not overlap with the semiconductor layer 108 may be thinner than the thickness of the insulating layer 103 in a region that overlaps with the semiconductor layer 108. For example, when forming the semiconductor layer 108, the surface of the insulating layer 103 in a region that does not overlap with the semiconductor layer 108 may be removed, thereby reducing the thickness of the insulating layer 103 in that region. Furthermore, the thickness of the insulating layer 117 in a region that does not overlap with the semiconductor layer 208 may be thinner than the thickness of the insulating layer 117 in a region that overlaps with the semiconductor layer 208.

[0169] In the manufacturing process of the transistor 100A and the transistor 200A, a transistor not including the conductive layer 106 and a transistor not including the conductive layer 206 can be manufactured over the same substrate at the same time. Figure 6A shows a cross-sectional view in the channel length direction of a transistor 100B which does not include the conductive layer 106 of the transistor 100A, and a transistor 200B which does not include the conductive layer 206 of the transistor 200A, and Figure 6B shows a cross-sectional view in the channel width direction of the transistor 100B which does not include the conductive layer 206 of the transistor 200A.

[0170] A semiconductor device according to one embodiment of the present invention can be realized as a semiconductor device including four types of transistors, namely, a transistor 100A, a transistor 100B, a transistor 200A, and a transistor 200B. Alternatively, a semiconductor device including one or both of the transistor 100A and the transistor 100B and one or both of the transistor 200A and the transistor 200B can be realized.

[0171] 7A and 7B show a structure example different from the above-described transistors 100A and 200A. Fig. 7A shows a cross-sectional view of the transistors 100C and 200C in the channel length direction, and Fig. 7B shows a cross-sectional view of the transistors 100C and 200C in the channel width direction.

[0172] The transistor 100C and the transistor 200C differ from the transistor 100A and the transistor 200A mainly in that the transistor 100C and the transistor 200C each have an insulating layer 130 over the insulating layer 118.

[0173] The insulating layer 130 functions as a planarization film. An organic material can be suitably used for the insulating layer 130. For example, one or more of an acrylic resin and a polyimide resin can be used for the insulating layer 130. A photosensitive material may also be used as the organic material.

[0174] By providing the insulating layer 130 that functions as a planarizing film, the step coverage of the layers formed on the insulating layer 130 (e.g., the conductive layer 120a, the conductive layer 120b, the conductive layer 220a, and the conductive layer 220b) can be improved, and defects such as discontinuities or voids in the layers can be suppressed.

[0175] The conductive layer 120a and the conductive layer 120b are electrically connected to the low-resistance region 108N of the semiconductor layer 108 through the opening 141a or the opening 141b provided in the insulating layer 130, the insulating layer 118, the insulating layer 110, and the insulating layer 117.

[0176] The conductive layer 220a and the conductive layer 220b are electrically connected to the low-resistance region 208N of the semiconductor layer 208 through an opening 241a or an opening 241b provided in the insulating layer 130, the insulating layer 118, and the insulating layer 110.

[0177] 8A and 8B show a structure example different from the above-described transistors 100C and 200C. Fig. 8A shows a cross-sectional view of the transistors 100C and 200D in the channel length direction, and Fig. 8B shows a cross-sectional view of the transistors 100C and 200D in the channel width direction.

[0178] The transistor 100D and the transistor 200D differ from the transistor 100C and the transistor 200C mainly in that the transistor 100D and the transistor 200D have an insulating layer 132 over the insulating layer 130, respectively.

[0179] The insulating layer 132 is provided to cover the top surface and side surfaces of the insulating layer 130. The insulating layer 132 has an opening 143a inside the opening 141a, an opening 143b inside the opening 141b, an opening 243a inside the opening 241a, and an opening 243b inside the opening 241b. Furthermore, the insulating layer 132 may have a region in contact with the top surface of the semiconductor layer 108 and the top surface of the semiconductor layer 208.

[0180] The conductive layer 120 a and the conductive layer 120 b are electrically connected to the low-resistance region 108 N of the semiconductor layer 108 through an opening 143 a or an opening 143 b provided in the insulating layer 132 .

[0181] The conductive layer 220 a and the conductive layer 220 b are electrically connected to the low-resistance region 208 N of the semiconductor layer 208 through an opening 243 a or an opening 243 b provided in the insulating layer 132 .

[0182] The insulating layer 132 can be formed using a material that can be used for the insulating layer 118. By providing the insulating layer 132 between the insulating layer 130 and the conductive layer 120a, the conductive layer 120b, the conductive layer 220a, and the conductive layer 220b, and by configuring the conductive layer 120a, the conductive layer 120b, the conductive layer 220a, and the conductive layer 220b to be in contact with the insulating layer 132, the adhesion of the conductive layer 120a, the conductive layer 120b, the conductive layer 220a, and the conductive layer 220b can be improved.

[0183] 9A and 9B show a structure example different from the above-described transistors 100A and 200A. Fig. 9A shows a cross-sectional view of the transistors 100E and 200E in the channel length direction, and Fig. 9B shows a cross-sectional view of the transistors 100E and 200E in the channel width direction.

[0184] The transistor 100E differs from the transistor 100A mainly in the shape of the insulating layer 103 that functions as the second gate insulating layer, and the transistor 200E differs from the transistor 200A mainly in the structure of the insulating layer that functions as the second gate insulating layer.

[0185] The insulating layer 103 has a region overlapping with the semiconductor layer 108, and edges of the insulating layer 103 coincide or substantially coincide with edges of the semiconductor layer 108. In other words, the insulating layer 103 has a top surface shape that coincides or substantially coincides with that of the semiconductor layer 108. For example, an insulating film that becomes the insulating layer 103 is formed, and a region of the insulating film that does not overlap with the semiconductor layer 108 is removed, thereby forming an island-shaped insulating layer 103 whose top surface shape coincides or substantially coincides with that of the semiconductor layer 108. The insulating layer 103 can be formed, for example, by processing the insulating layer 103 using a resist mask for processing the semiconductor layer 108.

[0186] In this specification, the phrase "top surface shapes that match or roughly match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes that match or roughly match" also applies.

[0187] 10A shows an enlarged view of a region P indicated by a dashed-dotted line in FIG. 9A . FIG. 10B shows an enlarged view of a region Q indicated by a dashed-dotted line in FIG. 9A . In the transistor 100E, parts of the insulating layer 110 and the insulating layer 117 function as a first gate insulating layer, and part of the insulating layer 103 functions as a second gate insulating layer. In the transistor 200E, part of the insulating layer 110 functions as the first gate insulating layer, and part of the insulating layer 117 functions as a second gate insulating layer.

[0188] As shown in FIG. 10A , in transistor 100E, the thickness TT100 of the first gate insulating layer is the sum of the thicknesses of insulating layer 110 and insulating layer 117. The thickness TB100 of the second gate insulating layer is the thickness of insulating layer 103. As shown in FIG. 10B , in transistor 200E, the thickness TT200 of the first gate insulating layer is the thickness of insulating layer 110. The thickness TB200 of the second gate insulating layer is the thickness of insulating layer 117. Therefore, the thickness TT100 of the first gate insulating layer of transistor 100E is thicker than the thickness TT200 of the first gate insulating layer of transistor 200E. Meanwhile, the thickness TB100 of the second gate insulating layer of transistor 100E and the thickness TB200 of the second gate insulating layer of transistor 200E can be adjusted by the thicknesses of insulating layer 103 and insulating layer 117, respectively.

[0189] Fig. 10C is an enlarged view of region R indicated by the dashed-dotted line in Fig. 9A. Fig. 10D is an enlarged view of region S indicated by the dashed-dotted line in Fig. 9A. As shown in Fig. 10C and 10D, insulating layer 117 has regions in contact with the upper surface and side surfaces of semiconductor layer 108, the lower surface of semiconductor layer 208, the lower surface of insulating layer 110, the side surfaces of insulating layer 103, and the upper surface of substrate 102.

[0190] 11A and 11B show a structure example different from the above-described transistors 100A and 200A. Fig. 11A shows a cross-sectional view of the transistors 100F and 200F in the channel length direction, and Fig. 11B shows a cross-sectional view of the transistors 100F and 200F in the channel width direction.

[0191] The transistors 100F and 200F differ mainly from the transistors 100A and 200A in that the insulating layer 103 has a stacked-layer structure.

[0192] The insulating layer 103 has a laminated structure of an insulating layer 103a and an insulating layer 103b on the insulating layer 103a.

[0193] The insulating layer 103a located on the conductive layer 106 and the conductive layer 206 side preferably functions as a barrier film that suppresses diffusion of components of the conductive layer 106 and the conductive layer 206 toward the semiconductor layer 108 and the semiconductor layer 208. An insulating film containing nitrogen can be suitably used for the insulating layer 103a. For example, an insulating layer containing one or more of a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, and a hafnium nitride film can be used for the insulating layer 103a.

[0194] On the other hand, an insulating film containing oxygen is preferably used for the insulating layer 103b located on the semiconductor layer 108 and the semiconductor layer 208 side. An insulating film containing oxygen is preferably used for the insulating layer 103b. The insulating layer 103b can be formed using a material that can be used for the insulating layer 110 or the insulating layer 117.

[0195] An enlarged view of a region P indicated by a dashed line in Fig. 11A is shown in Fig. 12A. An enlarged view of a region Q indicated by a dashed line in Fig. 11A is shown in Fig. 12B.

[0196] 12A , in transistor 100F, the thickness TT100 of the first gate insulating layer is the sum of the thicknesses of insulating layer 110 and insulating layer 117. The thickness TB100 of the second gate insulating layer is the sum of the thicknesses of insulating layer 103a and insulating layer 103b. As shown in FIG. 12B , in transistor 200F, the thickness TT200 of the first gate insulating layer is the thickness of insulating layer 110. The thickness TB200 of the second gate insulating layer is the sum of the thicknesses of insulating layer 117, insulating layer 103a, and insulating layer 103b.

[0197] An enlarged view of region R indicated by the dashed-dotted line in FIG. 11A is shown in FIG. 12C . An enlarged view of region S indicated by the dashed-dotted line in FIG. 11A is shown in FIG. 12D . As shown in FIGS. 12C and 12D , insulating layer 117 has regions in contact with the upper and side surfaces of semiconductor layer 108, the lower surface of semiconductor layer 208, the lower surface of insulating layer 110, and the upper surface of insulating layer 103b. Insulating layer 103a has a region in contact with the lower surface of insulating layer 103b. Insulating layer 103b has regions in contact with the lower surface of semiconductor layer 108 and the lower surface of insulating layer 117.

[0198] Note that the thickness of the insulating layer 103b in a region that does not overlap with the semiconductor layer 108 may be thinner than the thickness of the insulating layer 103b in a region that overlaps with the semiconductor layer 108. For example, when the semiconductor layer 108 is formed, the surface of the insulating layer 103b in a region that does not overlap with the semiconductor layer 108 is removed, which may result in a thinner thickness of the insulating layer 103b in that region.

[0199] 13A and 13B show a structure example different from the above-described transistors 100F and 200F. Fig. 13A shows a cross-sectional view of the transistors 100G and 200G in the channel length direction, and Fig. 13B shows a cross-sectional view of the transistors 100G and 200G in the channel width direction.

[0200] The transistor 100G differs from the transistor 100F mainly in the shape of the insulating layer 103b, and the transistor 200G differs from the transistor 200F mainly in the configuration of the second gate insulating layer.

[0201] The insulating layer 103b has a region overlapping with the semiconductor layer 108, and edges of the insulating layer 103b coincide or substantially coincide with edges of the semiconductor layer 108. In other words, the insulating layer 103b has a top surface shape that coincides or substantially coincides with that of the semiconductor layer 108. For example, an insulating film that becomes the insulating layer 103b is formed, and a region of the insulating film that does not overlap with the semiconductor layer 108 is removed, thereby forming an island-shaped insulating layer 103b whose top surface shape coincides or substantially coincides with that of the semiconductor layer 108. The insulating layer 103b can be formed, for example, by processing the insulating layer 103b using a resist mask for processing the semiconductor layer 108.

[0202] FIG. 14A shows an enlarged view of a region P indicated by a dashed-dotted line in FIG. 13A . FIG. 14B shows an enlarged view of a region Q indicated by a dashed-dotted line in FIG. 13A . In the transistor 100G, parts of the insulating layer 110 and the insulating layer 117 function as a first gate insulating layer, and parts of the insulating layer 103a and the insulating layer 103b function as a second gate insulating layer. In the transistor 200G, part of the insulating layer 110 functions as a first gate insulating layer, and parts of the insulating layer 117 and the insulating layer 103a function as a second gate insulating layer.

[0203] 14A, in transistor 100G, the thickness TT100 of the first gate insulating layer is the sum of the thicknesses of insulating layer 110 and insulating layer 117. The thickness TB100 of the second gate insulating layer is the sum of the thicknesses of insulating layer 103a and insulating layer 103b. As shown in FIG. 14B, in transistor 200G, the thickness TT200 of the first gate insulating layer is the thickness of insulating layer 110. The thickness TB200 of the second gate insulating layer is the sum of the thicknesses of insulating layer 117 and insulating layer 103a.

[0204] The thickness TT100 of the first gate insulating layer of the transistor 100G is thicker than the thickness TT200 of the first gate insulating layer of the transistor 200G. Meanwhile, the thickness TB100 of the second gate insulating layer of the transistor 100G and the thickness TB200 of the second gate insulating layer of the transistor 200G can be adjusted by the thicknesses of the insulating layers 103a, 103b, and 117, respectively.

[0205] FIG. 14C shows an enlarged view of region R indicated by a dashed-dotted line in FIG. 13A . FIG. 14D shows an enlarged view of region S indicated by a dashed-dotted line in FIG. 13A . As shown in FIGS. 14C and 14D , insulating layer 117 has regions in contact with the upper and side surfaces of semiconductor layer 108, the lower surface of semiconductor layer 208, the lower surface of insulating layer 110, the side surfaces of insulating layer 103b, and the upper surface of insulating layer 103a. Insulating layer 103a has regions in contact with the lower surface of insulating layer 103b and the lower surface of insulating layer 117. Insulating layer 103b has a region in contact with the lower surface of semiconductor layer 108. In addition, insulating layer 103b may have a region in contact with the lower surface of insulating layer 117.

[0206] 15A and 15B show a structure example different from the above-described transistors 100A and 200A. Fig. 15A shows a cross-sectional view of the transistors 100H and 200H in the channel length direction, and Fig. 15B shows a cross-sectional view of the transistors 100H and 200H in the channel width direction.

[0207] The transistor 100H and the transistor 200H are different from the transistor 100A and the transistor 200A mainly in that the insulating layer 110 has a stacked structure.

[0208] 15A and 15B show an example in which the insulating layer 110 has a three-layer structure in which an insulating layer 110A, an insulating layer 110B, and an insulating layer 110C are stacked in this order from the semiconductor layer 108 and semiconductor layer 208 side.

[0209] The first gate insulating layer of the transistor 100H has a stacked-layer structure of the insulating layer 117, the insulating layer 110A, the insulating layer 110B, and the insulating layer 110C. The first gate insulating layer of the transistor 200H has a stacked-layer structure of the insulating layer 110A, the insulating layer 110B, and the insulating layer 110C.

[0210] The insulating layer 110A, the insulating layer 110B, and the insulating layer 110C can each be made of a material that can be used for the insulating layer 110. The insulating layer 110A, the insulating layer 110B, and the insulating layer 110C can be formed using a method similar to that for forming the insulating layer 110.

[0211] The insulating layers 110A, 110B, and 110C are preferably formed successively using the same film formation apparatus without exposure to the atmosphere. By forming the layers successively, it is possible to prevent impurities such as water from adhering to the interfaces of the insulating layers 110A, 110B, and 110C. A plasma CVD method can be suitably used to form the insulating layers 110A, 110B, and 110C.

[0212] Since the insulating layer 110A is formed over the semiconductor layer 208, it is preferable that the insulating layer 110A be a film formed under conditions that minimize damage to the semiconductor layer 208. For example, the insulating layer 110A can be formed under conditions that minimize damage to the semiconductor layer 208. By forming the insulating layer 110A under conditions that minimize damage to the semiconductor layer 208, the density of defect states at the interface between the semiconductor layer 208 and the insulating layer 110 can be reduced, and the transistor 200H can have high reliability. Similarly, damage to the semiconductor layer 108 through the insulating layer 117 can be suppressed, and the transistor 100H can have high reliability.

[0213] For example, when the insulating layer 110A is formed by a plasma CVD method, low power conditions can significantly reduce damage to the semiconductor layer 108 and the semiconductor layer 208. Furthermore, a smaller ratio of the flow rate of the deposition gas to the total flow rate of the deposition gas (hereinafter simply referred to as the flow rate ratio) can reduce the film formation rate, allowing a dense film with fewer defects to be formed.

[0214] Note that, like the insulating layer 110A, the insulating layer 117 in contact with the semiconductor layer 108 is preferably a film formed under conditions that minimize damage to the semiconductor layer 108. For example, the insulating layer 117 can be formed under the conditions that can be used for forming the insulating layer 110A.

[0215] The insulating layer 110B is preferably a film formed under conditions where the film formation rate is higher than that of the insulating layer 110A, thereby improving productivity.

[0216] For example, the deposition rate of the insulating layer 110B can be increased by increasing the flow rate ratio of the deposition gas compared to that of the insulating layer 110A.

[0217] The insulating layer 110C is preferably an extremely dense film with reduced surface defects and low adsorption of impurities contained in the air, such as water. For example, similar to the insulating layer 110A, the insulating layer 110C can be formed under conditions where the film formation rate is sufficiently low.

[0218] Because the insulating layer 110C is formed on the insulating layer 110B, the insulating layer 110C has a smaller effect on the semiconductor layer 108 and the semiconductor layer 208 during deposition than the insulating layer 110A. Therefore, the insulating layer 110C can be formed under higher power conditions than the insulating layer 110A. By reducing the flow rate ratio of the deposition gas and forming the insulating layer 110C at high power, a dense film with reduced surface defects can be obtained.

[0219] That is, a stacked film formed under conditions in which the film formation rate is fastest for insulating layer 110B, followed by insulating layer 110A and then insulating layer 110C, can be used as insulating layer 110. Furthermore, for insulating layer 110, the etching rate under the same wet etching or dry etching conditions is fastest for insulating layer 110B, followed by insulating layer 110A and then insulating layer 110C, in that order.

[0220] The insulating layer 110B is preferably formed thicker than the insulating layer 110A and the insulating layer 110C. By forming the insulating layer 110B, which has the fastest film formation speed, thick, the time required for the film formation process of the insulating layer 110 can be shortened.

[0221] Because insulating layers 110A, 110B, and 110C can be made of the same material, the boundaries between insulating layer 110A and insulating layer 110B and between insulating layer 110B and insulating layer 110C may not be clearly visible. Therefore, in Figure 15A and other figures, these boundaries are indicated by dashed lines. Because insulating layer 110A and insulating layer 110B have different film densities, their boundaries may be observed as differences in contrast in transmission electron microscope (TEM) images of a cross section of insulating layer 110. Similarly, the boundary between insulating layer 110B and insulating layer 110C may also be observed as differences in contrast.

[0222] 16A and 16B show a structure example different from the above-described transistors 100A and 200A. Fig. 16A shows a cross-sectional view of the transistor 100I and the transistor 200I in the channel length direction, and Fig. 16B shows a cross-sectional view of the transistor 100I and the transistor 200I in the channel width direction.

[0223] The transistors 100I and 200I differ from the transistors 100A and 200A mainly in that the shapes of the insulating layers 117 and 110 are different.

[0224] The transistor 100I has a stacked-layer structure of an insulating layer 117a and an insulating layer 110a over the insulating layer 117a as a first gate insulating layer. Ends of the insulating layer 117a and the insulating layer 110a each coincide with or substantially coincide with an end of the conductive layer 112. In other words, the top surfaces of the insulating layer 117a and the insulating layer 110a each coincide with or substantially coincide with the conductive layer 112. The insulating layer 117a and the insulating layer 110a can be formed by processing the insulating layer 117a and the insulating layer 110a, for example, using a resist mask for processing the conductive layer 112. The transistor 100I has an insulating layer 103 as a second gate insulating layer.

[0225] The transistor 200I includes an insulating layer 110b as a first gate insulating layer. Ends of the insulating layer 110b coincide or substantially coincide with ends of the conductive layer 212. In other words, the top surface shape of the insulating layer 110b coincides or substantially coincides with that of the conductive layer 212. The insulating layer 110b can be formed by processing the conductive layer 212 using a resist mask for processing the conductive layer 212, for example. The transistor 200I includes an insulating layer 103 and an insulating layer 117b as second gate insulating layers.

[0226] The insulating layers 117a and 117b can be formed by processing a first insulating film provided over the semiconductor layer 108 and the insulating layer 103. The insulating layers 110a and 110b can be formed by processing a second insulating film provided over the semiconductor layer 208 and the first insulating film.

[0227] In the transistor 100I, the insulating layer 118 is provided in contact with the top surface and side surface of the semiconductor layer 108 that are not covered with the conductive layer 112, the insulating layer 110a, and the insulating layer 117a. In the transistor 200I, the insulating layer 118 is provided in contact with the conductive layer 212 of the semiconductor layer 208 that are not covered with the insulating layer 110b. The insulating layer 118 is provided to cover the top surface of the insulating layer 103, the side surfaces of the insulating layer 117a, the side surfaces of the insulating layer 110a, the top surface and side surfaces of the conductive layer 112, the side surfaces of the insulating layer 117b, the side surfaces of the insulating layer 110b, and the top surface and side surfaces of the conductive layer 212.

[0228] The insulating layer 118 has a function of lowering the resistance of the low-resistance region 108N and the low-resistance region 208N. As such an insulating layer 118, an insulating film that can supply impurities into the low-resistance region 108N and the low-resistance region 208N by heating the insulating layer 118 during or after its formation can be used. Alternatively, an insulating film that can supply impurities into the low-resistance region 108N and the low-resistance region 208N by heating the insulating layer 118 during or after its formation can be used. Ｏ ) can be used.

[0229] For example, the insulating layer 118 can be an insulating film that functions as a supply source for supplying impurities to the low-resistance regions 108N and 208N. In this case, the insulating layer 118 is preferably a film that releases hydrogen when heated. By forming such an insulating layer 118 in contact with the semiconductor layer 108 and the semiconductor layer 208, impurities such as hydrogen can be supplied to the low-resistance regions 108N and 208N, thereby reducing the resistance of the low-resistance regions 108N and 208N.

[0230] The insulating layer 118 is preferably formed using a deposition gas containing an impurity element such as a hydrogen element.

[0231] For example, nitride oxides or nitrides such as silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, and aluminum nitride oxide can be suitably used for the insulating layer 118. In particular, silicon nitride has a blocking property against hydrogen and oxygen, and can therefore prevent both diffusion of hydrogen from the outside to the semiconductor layer and desorption of oxygen from the semiconductor layer to the outside, thereby realizing a highly reliable transistor.

[0232] The insulating layer 118 can also be formed using an oxide or an oxynitride such as silicon oxide, silicon oxynitride, aluminum oxide, or hafnium oxide.

[0233] 17A and 17B show a structure example different from the above-described transistors 100I and 200I. Fig. 17A shows a cross-sectional view of the transistors 100J and 200J in the channel length direction, and Fig. 17B shows a cross-sectional view of the transistors 100J and 200J in the channel width direction.

[0234] The transistor 100J and the transistor 200J are different from the transistor 100I and the transistor 200I mainly in that the shapes of the insulating layers that function as the first gate insulating layers are different.

[0235] In the transistor 100J, the end of the conductive layer 112 is located inside the end of the insulating layer 110a and the end of the insulating layer 117a. In other words, the insulating layer 110 and the insulating layer 117 have portions that protrude outside the end of the conductive layer 112 at least over the semiconductor layer 108.

[0236] The semiconductor layer 108 has a pair of regions 108L between the channel formation region and the pair of low-resistance regions 108N. The regions 108L are regions of the semiconductor layer 108 that overlap with the insulating layer 110a and the insulating layer 117a but do not overlap with the conductive layer 112.

[0237] In the transistor 200J, the end of the conductive layer 212 is located inside the end of the insulating layer 110b. In other words, the insulating layer 110b has a portion that protrudes outside the end of the conductive layer 212 at least over the semiconductor layer 208.

[0238] The semiconductor layer 208 has a pair of regions 208L between the channel formation region and the pair of low-resistance regions 208N. The regions 208L are regions of the semiconductor layer 208 that overlap with the insulating layer 110b but do not overlap with the conductive layer 212.

[0239] The regions 108L and 208L each function as a buffer region for alleviating a drain electric field. The regions 108L and 208L do not overlap with either the conductive layer 112 or the conductive layer 212, and therefore are regions in which a channel is hardly formed even when a gate voltage is applied to the conductive layer 112 or the conductive layer 212. The regions 108L and 208L each preferably have a higher carrier concentration than the channel formation region. This allows the regions 108L and 208L to function as LDD (lightly doped drain) regions.

[0240] Region 108L can also be described as a region with the same or lower resistance, the same or higher carrier concentration, the same or higher oxygen vacancy density, or the same or higher impurity concentration compared to the channel formation region of transistor 100J.

[0241] Similarly, compared to the channel formation region of transistor 200J, region 208L can also be described as a region with the same or lower resistance, a region with the same or higher carrier concentration, a region with the same or higher oxygen vacancy density, or a region with the same or higher impurity concentration.

[0242] Compared to the low resistance region 108N, the region 108L can also be described as a region with the same or higher resistance, a region with the same or lower carrier concentration, a region with the same or lower oxygen vacancy density, and a region with the same or lower impurity concentration.

[0243] Similarly, compared to the low resistance region 208N, the region 208L can also be described as a region with the same or higher resistance, a region with the same or lower carrier concentration, a region with the same or lower oxygen vacancy density, and a region with the same or lower impurity concentration.

[0244] In this way, by providing the region 108L or the region 208L that functions as an LDD region between the channel formation region and the low-resistance region 108N or the low-resistance region 208N that functions as a source region or a drain region, a highly reliable transistor that combines a high drain breakdown voltage and a large on-current can be realized.

[0245] The low-resistance region 108N functions as a source region or a drain region, and is the region with the lowest resistance compared to other regions of the semiconductor layer 108. Alternatively, the low-resistance region 108N can also be said to be the region with the highest carrier concentration, the highest oxygen vacancy density, or the highest impurity concentration compared to other regions of the semiconductor layer 108.

[0246] Similarly, the low-resistance region 208N functions as a source region or a drain region, and is the region with the lowest resistance compared to other regions of the semiconductor layer 208. Alternatively, the low-resistance region 208N can also be said to be the region with the highest carrier concentration, the highest oxygen vacancy density, or the highest impurity concentration compared to other regions of the semiconductor layer 208.

[0247] The lower the electrical resistance of the low resistance region 108N and the low resistance region 208N, the more preferable. The sheet resistance values ​​of the low resistance region 108N and the low resistance region 208N are each 1 Ω / □ or more and 1×10 ３ Less than Ω / □, preferably 1 Ω / □ or more 8×10 ２ It can be made Ω / □ or less.

[0248] The higher the electrical resistance of the channel formation region in a state where a channel is not formed, the more preferable. The sheet resistance value of the channel formation region is 1×10 ９ Ω / □ or more, preferably 5×10 ９ Ω / □ or more, more preferably 1×10 １０ It can be made Ω / □ or more.

[0249] Since the electrical resistance of the channel formation region in a state where a channel is not formed is preferably as high as possible, there is no need to set an upper limit. However, if an upper limit is set, the sheet resistance of the channel formation region may be, for example, 1×10 ９ Ω / □ or more 1×10 １２ Ω / □ or less, preferably 5×10 ９ Ω / □ or more 1×10 １２ Ω / □ or less, more preferably 1×10 １０ Ω / □ or more 1×10 １２ It can be made Ω / □ or less.

[0250] The sheet resistance values ​​of the regions 108L and 208L are each 1×10 ３ Ω / □ or more 1×10 ９ Ω / □ or less, preferably 1×10 ３ Ω / □ or more 1×10 ８ Ω / □ or less, more preferably 1×10 ３ Ω / □ or more 1×10 ７ Ω / □ or less. By setting the resistance in this range, a transistor with good electrical characteristics and high reliability can be obtained. Note that the sheet resistance can be calculated from the resistance value. By providing such regions 108L and 208L between the low-resistance region 108N or the low-resistance region 208N and the channel formation region, the source-drain breakdown voltage of the transistor 100J or the transistor 200J can be increased.

[0251] In the transistor 100J, the electrical resistance of the channel formation region in a state where a channel is not formed is 1×10 of the electrical resistance of the low resistance region 108N. ６ More than 1x10 １２ times or less, preferably 1×10 ６ More than 1x10 １１ times or less, more preferably 1×10 ６ More than 1x10 １０ It can be twice or less.

[0252] In the transistor 100J, the electrical resistance of the channel formation region in a state where a channel is not formed is 1×10 of the electrical resistance of the region 108L. ０ More than 1x10 ９ times or less, preferably 1×10 １ More than 1x10 ８ times or less, more preferably 1×10 ２ More than 1x10 ７ It can be twice or less.

[0253] The electrical resistance of the region 108L is 1×10 of the electrical resistance of the low resistance region 108N. ０ More than 1x10 ９ times or less, preferably 1×10 １ More than 1x10 ８ times or less, more preferably 1×10１ More than 1x10 ７ It can be twice or less.

[0254] Similarly, in the transistor 200J, the electrical resistance of the channel formation region in a state where a channel is not formed is 1×10 of the electrical resistance of the low resistance region 208N. ６ More than 1x10 １２ times or less, preferably 1×10 ６ More than 1x10 １１ times or less, more preferably 1×10 ６ More than 1x10 １０ It can be twice or less.

[0255] In the transistor 200J, the electrical resistance of the channel formation region in a state where a channel is not formed is 1×10 of the electrical resistance of the region 208L. ０ More than 1x10 ９ times or less, preferably 1×10 １ More than 1x10 ８ times or less, more preferably 1×10 ２ More than 1x10 ７ It can be twice or less.

[0256] The electrical resistance of the region 208L is 1×10 of the electrical resistance of the low resistance region 208N. ０ More than 1x10 ９ times or less, preferably 1×10 １ More than 1x10 ８ times or less, more preferably 1×10 １ More than 1x10 ７ It can be twice or less.

[0257] The carrier concentration of the semiconductor layer 108 preferably has a distribution in which the channel formation region is lowest and the carrier concentration increases in the order of the region 108L and the low-resistance region 108N. By providing the region 108L between the channel formation region and the low-resistance region 108N, the carrier concentration of the channel formation region can be kept extremely low even if impurities such as hydrogen diffuse from the low-resistance region 108N during the manufacturing process. Similarly, the carrier concentration of the semiconductor layer 208 preferably has a distribution in which the channel formation region is lowest and the carrier concentration increases in the order of the region 208L and the low-resistance region 208N.

[0258] The lower the carrier concentration in the channel formation region, the better. １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is 1×10 or less. １６ cm −３ More preferably, it is 1×10 or less. １３ cm −３ More preferably, it is 1×10 or less. １２ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably 1×10 −９ cm −３ It can be said that:

[0259] On the other hand, the carrier concentration of the low resistance region 108N and the low resistance region 208N is, for example, 5×10 １８ cm −３ or more, preferably 1×10 １９ cm −３ or more, more preferably 5 × 10 １９ cm −３ The upper limit of the carrier concentration of the low resistance region 108N and the low resistance region 208N is not particularly limited, but may be, for example, 5×10 ２１ cm −３ , or 1 × 10 ２２ cm −３ It can be said that:

[0260] The carrier concentration of the region 108L may be a value between that of the channel formation region and that of the low-resistance region 108N of the transistor 100J. The carrier concentration of the region 208L may be a value between that of the channel formation region and that of the low-resistance region 208N of the transistor 200J. The carrier concentrations of the regions 108L and 208L may each be, for example, 1×10 １４ cm −３ 1x10 or more ２０ cm −３ It is sufficient to set the value in the range below.

[0261] The carrier concentration in the region 108L may not be uniform, and may have a gradient such that the carrier concentration decreases from the low-resistance region 108N side toward the channel formation region. For example, either one or both of the hydrogen concentration and the oxygen vacancy concentration in the region 108L may have a gradient such that the concentration decreases from the low-resistance region 108N side toward the channel formation region. The same applies to the region 208L.

[0262] 18A and 18B show a structure example different from the above-described transistors 100A and 200A. Fig. 18A shows a cross-sectional view of the transistors 100K and 200K in the channel length direction, and Fig. 18B shows a cross-sectional view of the transistors 100K and 200K in the channel width direction.

[0263] The transistor 100K differs from the transistor 100A mainly in that it has a metal oxide layer 114 between the insulating layer 110 and the conductive layer 112. The transistor 200K differs from the transistor 200A mainly in that it has a metal oxide layer 214 between the insulating layer 110 and the conductive layer 212.

[0264] An edge of the metal oxide layer 114 coincides with or substantially coincides with an edge of the conductive layer 112. In other words, the top surface shape of the metal oxide layer 114 coincides with or substantially coincides with that of the conductive layer 112. Similarly, an edge of the metal oxide layer 214 coincides with or substantially coincides with that of the conductive layer 212. In other words, the top surface shape of the metal oxide layer 214 coincides with or substantially coincides with that of the conductive layer 212. The metal oxide layer 114 and the metal oxide layer 214 can be formed, for example, by processing using a resist mask for processing the conductive layer 112 and the conductive layer 212.

[0265] The top surface shapes of the metal oxide layer 114 and the conductive layer 112 do not have to match. The top surface shapes of the metal oxide layer 214 and the conductive layer 212 do not have to match. For example, the end of the metal oxide layer 114 may be located outside the end of the conductive layer 112, and the end of the metal oxide layer 214 may be located outside the end of the conductive layer 212. Alternatively, the end of the metal oxide layer 114 may be located inside the end of the conductive layer 112, and the end of the metal oxide layer 214 may be located inside the end of the conductive layer 212.

[0266] The metal oxide layer 114 and the metal oxide layer 214 have a function of supplying oxygen to the insulating layer 110. When a conductive film containing a metal or alloy that is easily oxidized is used for the conductive layer 112 and the conductive layer 212, the metal oxide layer 114 and the metal oxide layer 214 can also function as a barrier layer that prevents the conductive layer 112 and the conductive layer 212 from being oxidized by oxygen in the insulating layer 110.

[0267] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film that prevents oxygen contained in the insulating layer 110 from diffusing toward the conductive layer 112. Similarly, the metal oxide layer 214 located between the insulating layer 110 and the conductive layer 212 functions as a barrier film that prevents oxygen contained in the insulating layer 110 from diffusing toward the conductive layer 212. Furthermore, the metal oxide layer 114 and the metal oxide layer 214 also function as barrier films that prevent impurities containing hydrogen elements contained in the conductive layer 112 or the conductive layer 212 from diffusing toward the insulating layer 110. Note that examples of impurities containing hydrogen elements include hydrogen and water. For the metal oxide layer 114 and the metal oxide layer 214, it is preferable to use a material that is less permeable to oxygen and hydrogen than, for example, the insulating layer 110.

[0268] Even when a metal material that easily absorbs oxygen is used for the conductive layer 112 and the conductive layer 212, providing the metal oxide layer 114 and the metal oxide layer 214 can prevent oxygen from diffusing from the insulating layer 110 to the conductive layer 112 or the conductive layer 212. Furthermore, even when the conductive layer 112 and the conductive layer 212 contain hydrogen, it can prevent hydrogen from diffusing from the conductive layer 112 or the conductive layer 212 to the semiconductor layer 108 or the semiconductor layer 208 through the insulating layer 110. As a result, the carrier concentration in the channel formation region of the semiconductor layer 108 and the semiconductor layer 208 can be made extremely low. Note that examples of metal materials that easily absorb oxygen include aluminum and copper.

[0269] An insulating material or a conductive material can be used for the metal oxide layer 114 and the metal oxide layer 214. When the metal oxide layer 114 and the metal oxide layer 214 have insulating properties, the metal oxide layer 114 and the metal oxide layer 214 each function as a part of a gate insulating layer. On the other hand, when the metal oxide layer 114 and the metal oxide layer 214 have conductive properties, the metal oxide layer 114 and the metal oxide layer 214 each function as a part of a gate electrode.

[0270] An insulating material having a higher dielectric constant than silicon oxide is preferably used for the metal oxide layer 114 and the metal oxide layer 214. In particular, an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like is preferably used because the driving voltage can be reduced.

[0271] For example, a conductive oxide such as indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the metal oxide layer 114 and the metal oxide layer 214. In particular, a conductive oxide containing indium is preferable because of its high conductivity.

[0272] The metal oxide layer 114 and the metal oxide layer 214 can be made of the same material. Furthermore, the metal oxide layer 114 and the metal oxide layer 214 can be formed by processing the same metal oxide film. However, different materials may be used for the metal oxide layer 114 and the metal oxide layer 214. Furthermore, the metal oxide layer 114 and the metal oxide layer 214 may be formed through different processes.

[0273] For the metal oxide layer 114 and the metal oxide layer 214, it is preferable to use an oxide material containing one or more elements contained in the semiconductor layer 108 or the semiconductor layer 208. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108 or the semiconductor layer 208. In this case, by using a metal oxide film formed using the same sputtering target as that for the semiconductor layer 108 or the semiconductor layer 208 as the metal oxide layer 114 and the metal oxide layer 214, it is possible to use a common device and improve productivity.

[0274] The metal oxide layer 114 and the metal oxide layer 214 are preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering apparatus, oxygen can be suitably added to the insulating layer 110 by forming the oxide film in an atmosphere containing oxygen gas. Note that oxygen may be added not only to the insulating layer 110 but also to the insulating layer 117, the semiconductor layer 108, and the semiconductor layer 208.

[0275] 18B , in the transistor 100K, the conductive layer 106 may be electrically connected to the conductive layer 112 through an opening 142 provided in the metal oxide layer 114, the insulating layer 110, the insulating layer 117, and the insulating layer 103. This allows the conductive layer 106 and the conductive layer 112 to be applied with the same potential. Similarly, in the transistor 200K, the conductive layer 206 may be electrically connected to the conductive layer 212 through an opening 242 provided in the metal oxide layer 214, the insulating layer 110, the insulating layer 117, and the insulating layer 103.

[0276] Note that the metal oxide layer 114 and the metal oxide layer 214 may be removed before the conductive layer 112 and the conductive layer 212 are formed, so that the conductive layer 112 and the conductive layer 212 are in contact with the insulating layer 110. Note that the metal oxide layer 114 and the metal oxide layer 214 may not be provided if they are not required.

[0277] 19A and 19B show a structure example different from the above-described transistors 100J and 200J. Fig. 19A shows a cross-sectional view of the transistors 100L and 200L in the channel length direction, and Fig. 19B shows a cross-sectional view of the transistors 100L and 200L in the channel width direction.

[0278] The transistor 100L differs from the transistor 100J mainly in that the transistor 100L has a metal oxide layer 114 between the insulating layer 110a and the conductive layer 112. The transistor 200L differs from the transistor 200J mainly in that the transistor 200L has a metal oxide layer 214 between the insulating layer 110b and the conductive layer 212.

[0279] 20A shows a structure example different from the above-described transistors 100A and 200A. FIG. 20A shows cross-sectional views of the transistors 100M and 200M in the channel length direction. For a cross-sectional view in the channel width direction, refer to FIG. 4B.

[0280] The transistor 100M differs from the transistor 100A mainly in that the conductive layer 120a and the conductive layer 120b are provided over the insulating layer 110. The transistor 200M differs from the transistor 200A mainly in that the conductive layer 220a and the conductive layer 220b are provided over the insulating layer 110.

[0281] The conductive layer 120a and the conductive layer 120b are electrically connected to the low-resistance region 108N of the semiconductor layer 108 through an opening 141a or an opening 141b provided in the insulating layer 110 and the insulating layer 117, respectively. The conductive layer 220a and the conductive layer 220b are electrically connected to the low-resistance region 208N of the semiconductor layer 208 through an opening 241a or an opening 241b provided in the insulating layer 110, respectively.

[0282] The conductive layer 120a, the conductive layer 120b, the conductive layer 220a, and the conductive layer 220b can be formed using the same material as the conductive layer 112 and the conductive layer 212. The conductive layer 120a, the conductive layer 120b, the conductive layer 220a, and the conductive layer 220b can be formed in the same process as the conductive layer 112 and the conductive layer 212. For example, after the openings 141a, 141b, 241a, and 241b are provided in the insulating layer 110, a conductive film covering the insulating layer 110, the openings 141a, 141b, 241a, and 241b is formed and then processed, whereby the conductive layer 112, the conductive layer 212, the conductive layer 120a, the conductive layer 120b, the conductive layer 220a, and the conductive layer 220b can be formed.

[0283] An insulating layer 118 may be provided to cover the conductive layers 120 a , 120 b , 220 a , 220 b , 112 , and 212 .

[0284] After the insulating layer 110 is formed, a resist mask is formed in regions that will become channel formation regions of the transistor 100M and the transistor 200M, and an impurity element is added using the resist mask as a mask, thereby forming the low-resistance region 108N and the low-resistance region 208N. After the resist mask is removed, openings 141a, 141b, 241a, and 241b are provided in the insulating layer 110, and then the conductive layer 112, the conductive layer 212, the conductive layer 120a, the conductive layer 120b, the conductive layer 220a, and the conductive layer 220b can be formed.

[0285] 20B shows a configuration example different from the transistors 100M and 200M described above. FIG. 20B shows a cross-sectional view of the transistors 100N and 200N in the channel length direction. For a cross-sectional view in the channel width direction, refer to FIG. 17B.

[0286] The transistor 100N differs from the transistor 100M mainly in that the insulating layer 110 and the insulating layer 117 are not provided between the conductive layer 120a and the semiconductor layer 108 and the conductive layer 120b. That is, the conductive layer 120a and the conductive layer 120b each have regions in contact with the top surface and side surface of the semiconductor layer 108. The transistor 200N differs from the transistor 200M mainly in that the insulating layer 110 is not provided between the conductive layer 220a and the semiconductor layer 208 and the conductive layer 220b. That is, the conductive layer 220a and the conductive layer 220b each have regions in contact with the top surface and side surface of the semiconductor layer 208.

[0287] 20B , in the transistor 100N, the end of the conductive layer 112 may be located inside the end of the insulating layer 110a and the end of the insulating layer 117a. In other words, the insulating layers 110a and 117a have portions that protrude outward from the end of the conductive layer 112 at least on the semiconductor layer 108. Similarly, in the transistor 200N, the end of the conductive layer 212 may be located inside the end of the insulating layer 110b. In other words, the insulating layer 110b has a portion that protrudes outward from the end of the conductive layer 212 at least on the semiconductor layer 208.

[0288] After the insulating layer 110a, the insulating layer 117a, and the insulating layer 110b are formed, resist masks are formed in regions that will become channel formation regions of the transistor 100N and the transistor 200N, and impurity elements are added using the resist masks as masks, thereby forming the low-resistance regions 108N, 108L, 208N, and 208L. After the resist masks are removed, the conductive layers 112, 212, 120a, 120b, 220a, and 220b can be formed.

[0289] 20C shows a configuration example different from the transistors 100N and 200N described above. FIG. 20C shows a cross-sectional view of the transistors 100P and 200P in the channel length direction. For a cross-sectional view of the transistors 100P and 200P in the channel width direction, refer to FIG. 17B.

[0290] The transistor 100P differs from the transistor 100N mainly in that the transistor 100P includes insulating layers 110a and 117a between the conductive layers 120a and 120b and the semiconductor layer 108. That is, the insulating layer 117a has a region in contact with the top surface and side surface of the semiconductor layer 108. The transistor 200N differs from the transistor 200N mainly in that the transistor 200N includes insulating layer 110b between the conductive layers 220a and 220b and the semiconductor layer 208. That is, the insulating layer 110b has a region in contact with the top surface and side surface of the semiconductor layer 208.

[0291] <Manufacturing Method Example 1> An example of a manufacturing method of a transistor of one embodiment of the present invention will be described below. The transistor 100A and the transistor 200A described in Structure Example 2 will be used as examples. Note that the description here will be given taking a structure in which a metal oxide is used for a semiconductor layer as an example.

[0292] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc.

[0293] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0294] When processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0295] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0296] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0297] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0298] 21A to 26B show schematic cross-sectional views at various stages in the manufacturing process of the transistors 100A and 200A shown in Fig. 4A and 4B. Note that in each figure, a schematic cross-sectional view in the channel length direction is shown on the left side, and a schematic cross-sectional view in the channel width direction is shown on the right side.

[0299] In the following, for matters common to components (such as conductive layers 106 and 206, conductive layers 112 and 212) that can be formed in the same process between transistor 100A and transistor 200A, only one of them may be described, assuming that they have the same functions and effects, and the description of the other may be omitted and taken into consideration.

[0300] [Formation of Conductive Layer 106 and Conductive Layer 206] A conductive film is formed over the substrate 102 and processed by etching to form the conductive layer 106 and the conductive layer 206 which function as gate electrodes (FIG. 21A).

[0301] 21A, it is preferable to process the conductive layer 106 and the conductive layer 206 so that their ends have a tapered shape, thereby improving the step coverage of the insulating layer 103 to be formed next.

[0302] In this specification, the term "tapered shape" refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a surface on which the structure is to be formed. For example, the structure preferably has a region in which the angle between the inclined side surface and the surface on which the structure is to be formed (also referred to as the taper angle) is less than 90°.

[0303] By using a conductive film containing copper as the conductive film to be the conductive layer 106 and the conductive layer 206, it is possible to reduce wiring resistance. For example, when the device is applied to a large display device or a display device with high resolution, it is preferable to use a conductive film containing copper. Even when a conductive film containing copper is used for the conductive layer 106 or the like, the insulating layer 103 prevents copper from diffusing toward the semiconductor layer 108 or the like, so that a highly reliable transistor can be realized.

[0304] [Formation of Insulating Layer 103] Subsequently, the insulating layer 103 is formed to cover the substrate 102, the conductive layer 106, and the conductive layer 206 (FIG. 21A). The insulating layer 103 can be formed by a PECVD method, an ALD method, a sputtering method, or the like.

[0305] In particular, it is preferable that the insulating layer 103 be formed by the PECVD method.

[0306] The insulating layer 103 preferably has a stacked structure of two or more insulating films. In this case, an insulating film containing nitrogen is preferably used as the insulating film located on the conductive layer 106 side. An insulating film containing oxygen is preferably used as the insulating film located on the semiconductor layer 108 and the semiconductor layer 208 side. Each insulating film constituting the insulating layer 103 is preferably formed successively without exposure to air using a plasma CVD apparatus.

[0307] When the insulating layer 103 is formed using a plasma CVD apparatus, after the insulating layer 103 is formed, plasma treatment may be performed in a treatment chamber at a lower power than that used for forming the insulating layer 103 to remove static electricity accumulated on the substrate 102. This plasma treatment can be called a static elimination treatment. The static elimination treatment can be performed in an atmosphere containing one or more of nitrogen, nitrous oxide, nitrogen dioxide, hydrogen, ammonia, and noble gases. For example, an argon gas atmosphere can be suitably used for the static elimination treatment. Alternatively, a mixed gas containing the above-mentioned gases may be used for the static elimination treatment.

[0308] After the insulating layer 103 is formed, the surface of the insulating layer 103 may be removed. The above-described static elimination treatment may cause defects on the surface of the insulating layer 103. Defects in the insulating layer 103, which functions as a second gate insulating layer of the transistors 100A and 200A, may become carrier trap sites, which may deteriorate the reliability of the transistors 100A and 200A. Therefore, removing the surface of the insulating layer 103 having defects can improve the reliability of the transistors 100A and 200A. The surface of the insulating layer 103 can be removed by, for example, cleaning using a cleaning solution containing hydrofluoric acid. For example, the etching depth of the surface of the insulating layer 103 is preferably 2 nm to 20 nm, more preferably 3 nm to 15 nm, and even more preferably 5 nm to 10 nm. Typically, the etching depth of the surface of the insulating layer 103 is about 10 nm.

[0309] Heat treatment may be performed after the insulating layer 103 is formed. The heat treatment can reduce defects in the insulating layer 103. Furthermore, impurities including hydrogen elements in the insulating layer 103 can be reduced.

[0310] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 250° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 450° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA) may be used. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. By using an atmosphere containing as little hydrogen, water, or the like as possible, it is possible to prevent hydrogen, water, or the like from being taken into the insulating layer 103. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) apparatus, or the like. The use of an RTA apparatus can shorten the heat treatment time.

[0311] The heat treatment may be performed after the surface of the insulating layer 103 is removed.

[0312] Subsequently, treatment for supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere may be used for the oxygen supply treatment. Alternatively, plasma ion doping or ion implantation may be used for the oxygen supply treatment.

[0313] [Formation of Metal Oxide Film 108f] Subsequently, a metal oxide film 108f is formed on the insulating layer 103 (FIG. 21C).

[0314] The metal oxide film 108f is a film that will later become the semiconductor layer 108, and is preferably formed by a sputtering method using a metal oxide target.

[0315] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film in which impurities such as hydrogen and water are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0316] It is preferable to use oxygen gas when forming the metal oxide film 108f. FIG. 21B shows a schematic cross-sectional view of the inside of a sputtering apparatus when forming the metal oxide film 108f on the insulating layer 103. FIG. 21B also shows a target 193 installed inside the sputtering apparatus and a plasma 194 formed below the target 193. By using oxygen gas when forming the metal oxide film 108f, oxygen can be suitably supplied into the insulating layer 103. For example, when an oxide is used for the insulating layer 103, oxygen can be suitably supplied into the insulating layer 103. In FIG. 21B, the oxygen supplied to the insulating layer 103 is indicated by an arrow.

[0317] Here, if hydrogen exists in the semiconductor layer 108, oxygen vacancies (V Ｏ ) with hydrogen (hereinafter referred to as V Ｏ H) may be formed. Ｏ H can be a carrier generation source and may adversely affect the electrical characteristics and reliability of a transistor.Ｏ ), and V Ｏ It is preferable that H is small.

[0318] By supplying oxygen to the insulating layer 103, oxygen is supplied to the semiconductor layer 108 and the semiconductor layer 208 in a later step, and oxygen vacancies (V Ｏ ), and V Ｏ H can be reduced.

[0319] When forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and the higher the on-current of the transistor can be.

[0320] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0321] The substrate temperature during deposition of the metal oxide film may be from room temperature to 250° C., preferably from room temperature to 200° C., and more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to less than 140° C. is preferable because productivity is increased. Furthermore, by depositing the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0322] Before forming the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 103 and a treatment for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment may be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２Oxygen may be supplied to the insulating layer 103 by plasma treatment in an atmosphere containing an oxidizing gas such as nitrogen monoxide (NO). When plasma treatment containing nitrous oxide gas is performed, oxygen can be supplied while organic substances on the surface of the insulating layer 103 are suitably removed. After such treatment, it is preferable to form the metal oxide film 108f continuously without exposing the surface of the insulating layer 103 to the air.

[0323] In addition, when the semiconductor layer 108 has a stacked structure in which a plurality of semiconductor layers are stacked, it is preferable to form a metal oxide film first, and then form a next metal oxide film in succession without exposing the surface of the first metal oxide film to the air.

[0324] [Formation of Semiconductor Layer 108] Subsequently, a resist mask 135 is formed on the metal oxide film 108f (FIG. 22A).

[0325] Next, the metal oxide film 108f in the region not covered with the resist mask 135 is removed by etching to form the semiconductor layer 108 and to expose part of the top surface of the insulating layer 103 (FIG. 22B). The metal oxide film 108f can be etched by either or both of a wet etching method and a dry etching method. The wet etching method is preferable for etching the metal oxide film 108f because it can reduce etching damage to the semiconductor layer 108.

[0326] As a result, an island-shaped semiconductor layer 108 is formed.

[0327] The insulating layer 103 is preferably made of a material having a large etching selectivity with respect to the metal oxide film 108f. That is, the etching rate with respect to the metal oxide film 108f is preferably higher than the etching rate with respect to the insulating layer 103. By reducing the etching amount of the insulating layer 103, the step between the insulating layer 103 and the semiconductor layer 108 is reduced, the step coverage of a layer (e.g., the insulating layer 117) formed on the insulating layer 103 and the semiconductor layer 108 is improved, and defects such as step discontinuities or voids in the layer can be suppressed.

[0328] When the metal oxide film 108f is etched by a wet etching method, an etchant containing one or more of oxalic acid, phosphoric acid, acetic acid, nitric acid, hydrofluoric acid, and tetramethylammonium hydroxide (TMAH) can be used. Alternatively, an etchant containing phosphoric acid, acetic acid, and nitric acid can be preferably used.

[0329] Note that when the semiconductor layer 108 is formed, the thickness of the insulating layer 103 in a region that does not overlap with the semiconductor layer 108 may be thinner than the thickness of the insulating layer 103 in a region that overlaps with the semiconductor layer 108. Alternatively, the insulating layer 103 in a region that does not overlap with the semiconductor layer 108 may be removed. By removing the insulating layer 103 in the region that does not overlap with the semiconductor layer 108, the transistor 100E shown in FIG. 9A and the like can be formed.

[0330] Thereafter, the resist mask 135 is removed. The resist mask 135 can be removed by wet etching or dry etching, or both.

[0331] [Formation of Insulating Layer 117] Subsequently, the insulating layer 117 is formed to cover the insulating layer 103 and the semiconductor layer 108 ( FIG. 22C ). The insulating layer 117 can be formed by the same method as that for the insulating layer 103. The insulating layer 117 can be preferably formed by PECVD.

[0332] Before the insulating layer 117 is formed, it is preferable to perform plasma treatment on the surfaces of the insulating layer 103 and the semiconductor layer 108. The plasma treatment can reduce impurities such as water adsorbed to the surfaces of the insulating layer 103 and the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 103 can be reduced, thereby realizing a highly reliable transistor. This is particularly suitable when the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating layer 117. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. It is also preferable that the plasma treatment and the formation of the insulating layer 117 are performed successively without exposure to the air.

[0333] [Formation of Metal Oxide Film 208f] Subsequently, a metal oxide film 208f is formed on the insulating layer 117 (FIG. 23B).

[0334] The metal oxide film 208f is a film that will later become the semiconductor layer 208, and is preferably formed by a sputtering method using a metal oxide target. The metal oxide film 208f can be formed using a sputtering target different from that used for the metal oxide film 108f. The description of the metal oxide film 108f can be applied to the formation of the metal oxide film 208f.

[0335] It is preferable to use oxygen gas when forming the metal oxide film 208f. FIG. 23A shows a schematic cross-sectional view of the inside of a sputtering apparatus when forming the metal oxide film 208f on the insulating layer 117. FIG. 23A also shows a target 195 installed inside the sputtering apparatus and a plasma 196 formed below the target 195. By using oxygen gas when forming the metal oxide film 208f, oxygen can be suitably supplied into the insulating layer 117. In FIG. 23A, the arrows indicate oxygen supplied to the insulating layer 117. Note that oxygen may also be supplied into the insulating layer 103.

[0336] By supplying oxygen to the insulating layer 117, oxygen is supplied to the semiconductor layer 108 and the semiconductor layer 208 in a later step, and oxygen vacancies (V Ｏ ), and V Ｏ H can be reduced.

[0337] [Formation of Semiconductor Layer 208] Subsequently, a resist mask 136 is formed on the metal oxide film 108f (FIG. 23C).

[0338] Next, the metal oxide film 208f in the region not covered with the resist mask 136 is removed by etching to form the semiconductor layer 208 and to expose a part of the top surface of the insulating layer 117 ( FIG. 24A ). The metal oxide film 208f can be etched by either or both of a wet etching method and a dry etching method. The wet etching method is preferable for etching the metal oxide film 208f because it can reduce etching damage to the semiconductor layer 208.

[0339] The insulating layer 117 is preferably made of a material that has a high etching selectivity with respect to the metal oxide film 208f. That is, the etching rate for the metal oxide film 208f is preferably faster than the etching rate for the insulating layer 117. By reducing the etching amount of the insulating layer 117, the step between the insulating layer 117 and the semiconductor layer 208 is reduced, the step coverage of layers (e.g., the insulating layer 110) formed on the insulating layer 117 and the semiconductor layer 208 is improved, and defects such as step discontinuities or voids in the layers can be suppressed. The metal oxide film 208f can be etched by a method that can be used for etching the metal oxide film 108f.

[0340] Note that when the semiconductor layer 208 is formed, the thickness of the insulating layer 117 in a region that does not overlap with the semiconductor layer 208 may be thinner than the thickness of the insulating layer 117 in a region that overlaps with the semiconductor layer 208 .

[0341] Thereafter, the resist mask 136 is removed (FIG. 24B).

[0342] Through the above steps, the semiconductor layer 108 and the semiconductor layer 208 having different compositions can be formed.

[0343] Although the structure in which the semiconductor layer 108 is formed first and then the semiconductor layer 208 is formed is shown here, the order is not particularly limited. The semiconductor layer 208 may be formed first and then the semiconductor layer 108 may be formed.

[0344] Although this embodiment has described a structure in which two types of semiconductor layers, the semiconductor layer 108 and the semiconductor layer 208, are separately formed, one embodiment of the present invention is not limited to this. By repeating the formation of the insulating layer and the formation of the semiconductor layer as described above, three or more types of semiconductor layers can be separately formed. In other words, a semiconductor device including three or more types of transistors can be manufactured without significantly increasing the number of steps.

[0345] [Heat Treatment] Heat treatment is preferably performed after the formation of the semiconductor layer 108 and the semiconductor layer 208. The heat treatment can remove hydrogen or water contained in or adsorbed to the surface of the semiconductor layer 108 and the semiconductor layer 208. Furthermore, the heat treatment may improve the film quality of the semiconductor layer 108 and the semiconductor layer 208 (for example, reduce defects or improve crystallinity).

[0346] By the heat treatment, oxygen can also be supplied from the insulating layer 103 to the semiconductor layer 108 and the semiconductor layer 208 .

[0347] The temperature of the heat treatment can typically be 150° C. or higher and lower than the strain point of the substrate, or 200° C. or higher and 500° C. or lower, or 250° C. or higher and 450° C. or lower, or 300° C. or higher and 450° C. or lower.

[0348] The heat treatment can be performed in an atmosphere containing a noble gas or nitrogen. Alternatively, the heat treatment can be performed in the atmosphere containing noble gas or nitrogen, followed by heating in an atmosphere containing oxygen. Alternatively, the heat treatment can be performed in a dry air atmosphere. Note that it is preferable that the heat treatment atmosphere contains as little hydrogen, water, or the like as possible. The heat treatment can be performed using an electric furnace, an RTA apparatus, or the like. Using an RTA apparatus can shorten the heat treatment time.

[0349] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, there are cases where a high-temperature treatment in a later step (e.g., a film formation step) can also serve as the heat treatment.

[0350] [Formation of Insulating Layer 110] Subsequently, the insulating layer 110 is formed to cover the insulating layer 117 and the semiconductor layer 208 (FIG. 24C).

[0351] The insulating layer 110 can be formed by the same method as that for the insulating layer 103. The insulating layer 110 can be preferably formed by a PECVD method.

[0352] Before the insulating layer 110 is formed, plasma treatment is preferably performed on the surfaces of the insulating layer 117 and the semiconductor layer 208. The plasma treatment can reduce impurities such as water adsorbed to the surfaces of the insulating layer 117 and the semiconductor layer 208. Therefore, impurities at the interface between the semiconductor layer 208 and the insulating layer 110 can be reduced, thereby realizing a highly reliable transistor. This is particularly suitable when the surface of the semiconductor layer 208 is exposed to the air between the formation of the semiconductor layer 208 and the formation of the insulating layer 110. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. The plasma treatment and the formation of the insulating layer 110 are preferably performed successively without exposure to the air.

[0353] Here, heat treatment is preferably performed after the insulating layer 110 is formed. The heat treatment can remove hydrogen or water contained in or adsorbed to the surface of the insulating layer 110. Furthermore, defects in the insulating layer 110 can be reduced.

[0354] The conditions for the heat treatment may be as described above.

[0355] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, there are cases where a high-temperature treatment in a later step (e.g., a film formation step) can also serve as the heat treatment.

[0356] [Formation of Openings 142 and 242] Subsequently, portions of the insulating layer 110, the insulating layer 117, and the insulating layer 103 are etched to form openings 142 reaching the conductive layer 106 and openings 242 reaching the conductive layer 206 ( FIG. 25A ). This allows the conductive layer 106 to be electrically connected to the conductive layer 112, which will be formed later, via the openings 142. The conductive layer 206 and the conductive layer 212, which will be formed later, can be electrically connected to each other via the openings 142.

[0357] [Formation of Conductive Layer 112 and Conductive Layer 212] Subsequently, a conductive film 112f that will become the conductive layer 112 and the conductive layer 212 is formed on the insulating layer 110 (FIG. 25B).

[0358] The conductive film 112f is preferably formed using a low-resistance metal or alloy material, a material that does not easily release hydrogen and from which hydrogen does not easily diffuse, and a material that does not easily oxidize.

[0359] The conductive film 112f is preferably formed by, for example, a sputtering method using a sputtering target containing a metal or an alloy.

[0360] For example, the conductive film 112f is preferably a stacked film in which a conductive film that is resistant to oxidation and through which hydrogen does not easily diffuse and a conductive film with low resistance are stacked.

[0361] Subsequently, the conductive film 112f is partially etched to form the conductive layer 112 and the conductive layer 212 (FIG. 25C).

[0362] It is particularly preferable to use a wet etching method for etching the conductive film 112f.

[0363] In this way, by forming a structure in which the top surface and side surface of the semiconductor layer 108, the top surface and side surface of the semiconductor layer 208, and the insulating layer 103 are covered without etching the insulating layer 110 and the insulating layer 117, it is possible to prevent the semiconductor layer 108, the semiconductor layer 208, and the insulating layer 103 from being etched and becoming thin when the conductive film 112f and the like are etched.

[0364] [Treatment for Supplying Impurity Element] Subsequently, a treatment for supplying (also referred to as adding or injecting) the impurity element 140 to the semiconductor layer 108 and the semiconductor layer 208 is performed using the conductive layer 112 and the conductive layer 212 as masks ( FIG. 26A ). The impurity element 140 is supplied to the semiconductor layer 108 through the insulating layer 110 and the insulating layer 117. The impurity element 140 is supplied to the semiconductor layer 208 through the insulating layer 110.

[0365] By supplying the impurity element 140, a low-resistance region 108N can be formed in a region of the semiconductor layer 108 that is not covered with the conductive layer 112. Similarly, a low-resistance region 208N can be formed in the semiconductor layer 208. At this time, it is preferable to determine conditions for the supplying process of the impurity element 140 in consideration of the material and thickness of the conductive layer 112, the conductive layer 212, and the like that serve as masks so that the impurity element 140 is not supplied as much as possible to a region of the semiconductor layer 108 that overlaps with the conductive layer 112 and a region of the semiconductor layer 208 that overlaps with the conductive layer 212. As a result, a channel formation region with a sufficiently reduced impurity concentration can be formed in the region of the semiconductor layer 108 that overlaps with the conductive layer 112 and a region of the semiconductor layer 208 that overlaps with the conductive layer 212.

[0366] Note that the amount of the impurity element 140 added to the low-resistance region 108N and the low-resistance region 208N can be made different by adjusting the film thickness of the insulating layer 117. For example, by increasing the film thickness of the insulating layer 117, the amount of the impurity element 140 added to the low-resistance region 108N can be made smaller than that of the low-resistance region 208N. On the other hand, by decreasing the film thickness of the insulating layer 117, the amount of the impurity element 140 added to the low-resistance region 108N and the low-resistance region 208N can be made approximately the same.

[0367] The impurity element 140 can be preferably supplied by plasma ion doping or ion implantation. These methods allow the concentration profile in the depth direction to be controlled with high precision by adjusting the ion acceleration voltage, dose, etc. The use of plasma ion doping can increase productivity. Furthermore, the use of ion implantation using mass separation can increase the purity of the supplied impurity element.

[0368] In the supplying treatment of the impurity element 140, it is preferable to control the treatment conditions so that the concentration is highest at the interface between the semiconductor layer 108 and the insulating layer 117, the interface between the semiconductor layer 208 and the insulating layer 110, and in the semiconductor layer or in the insulating layer near these interfaces. In this way, the impurity element 140 at an optimum concentration can be supplied to the semiconductor layer 108, the semiconductor layer 208, the insulating layer 110, and the insulating layer 117 in one treatment.

[0369] The impurity element 140 can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, or a noble gas. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to use one or more of boron, phosphorus, aluminum, magnesium, and silicon as the impurity element 140.

[0370] The source gas of the impurity element 140 can be a gas containing the above impurity element. ２ H ６ Gas or BF ３ When phosphorus is supplied, a typical example is a PH ３ It is also possible to use a mixed gas in which these source gases are diluted with a noble gas.

[0371] Other raw material gases include CH ４ , N ２ , N.H. ３ , AlH ３ , AlCl ３ , SiH ４ , Si ２ H ６ , F ２ , H.F., H. ２ , (C ５ H ５ ) ２ Mg, noble gases, etc. can be used. The ion source is not limited to gas, and a solid or liquid vaporized by heating may also be used.

[0372] The addition of the impurity element 140 can be controlled by setting conditions such as acceleration voltage or dose amount in consideration of the composition, density, thickness, and the like of the insulating layer 110, the semiconductor layer 108, and the semiconductor layer 208.

[0373] For example, when adding boron or phosphorus by ion implantation or plasma ion doping, the dose is, for example, 1×10 １３ ions / cm ２ 1x10 or more １７ ions / cm ２ Below 1 × 10, preferably １４ ions / cm ２ 5x10 or more １６ ions / cm ２ or less, more preferably 1 × 10 １５ ions / cm ２ 3x10 or more １６ ions / cm ２ The range can be as follows:

[0374] The method for supplying the impurity element 140 is not limited to this, and for example, a treatment using thermal diffusion by heating, a plasma treatment, or the like may be used. In the case of the plasma treatment, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing the plasma treatment. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like may be used.

[0375] In one embodiment of the present invention, the impurity element 140 can be supplied to the semiconductor layer 108 through the insulating layer 110 and the insulating layer 117, and can be supplied to the semiconductor layer 208 through the insulating layer 110. Therefore, even when the semiconductor layer 108 or the semiconductor layer 208 has crystallinity, damage to the semiconductor layer 108 or the semiconductor layer 208 when the impurity element 140 is supplied can be reduced, and loss of crystallinity can be suppressed. Therefore, this is suitable for a case where electrical resistance increases due to a decrease in crystallinity.

[0376] [Formation of Insulating Layer 118] Subsequently, the insulating layer 118 is formed to cover the insulating layer 110, the conductive layer 112, and the conductive layer 212 (FIG. 26B).

[0377] When the insulating layer 118 is formed by plasma CVD, if the substrate temperature during film formation is too high, impurities contained in the low-resistance region 108N and the like may diffuse into the peripheral portion including the channel formation region of the semiconductor layer 108, or the electrical resistance of the low-resistance region 108N may increase. Therefore, the substrate temperature during film formation of the insulating layer 118 may be determined taking these factors into consideration.

[0378] For example, the substrate temperature during deposition of the insulating layer 118 is preferably 150° C. to 400° C., preferably 180° C. to 360° C., more preferably 200° C. to 250° C. By depositing the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0379] After the insulating layer 118 is formed, heat treatment may be performed. The heat treatment may reduce the resistance of the low-resistance region 108N and the low-resistance region 208N more stably. For example, the heat treatment may cause the impurity element 140 to diffuse appropriately and become locally uniform, thereby forming the low-resistance region 108N and the low-resistance region 208N having an ideal impurity element concentration gradient. Note that if the temperature of the heat treatment is too high (for example, 500° C. or higher), the impurity element 140 may diffuse into the channel formation region, which may result in deterioration of the electrical characteristics and reliability of the transistor.

[0380] The conditions for the heat treatment may be as described above.

[0381] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, if there is a high-temperature treatment (e.g., a film formation step) in a later step, this heat treatment may be combined with the heat treatment.

[0382] [Formation of openings 141a, 141b, 241a, and 241b] Next, portions of insulating layer 118, insulating layer 110, and insulating layer 117 are etched to form openings 141a and 141b that reach low-resistance region 108N, and openings 241a and 241b that reach low-resistance region 208N.

[0383] [Formation of Conductive Layer 120a, Conductive Layer 120b, Conductive Layer 220a, and Conductive Layer 220b] Subsequently, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a, 141b, 241a, and 241b, and the conductive film is processed into a desired shape, thereby forming the conductive layers 120a, 120b, 220a, and 220b ( FIGS. 4A and 4B ).

[0384] Through the above steps, the transistor 100A and the transistor 200A can be manufactured. For example, when the transistor 100A is used in a pixel of a display device, a subsequent step of forming one or more of a protective insulating layer, a planarization layer, a pixel electrode, and a wiring may be added.

[0385] The above is the description of the first example of the manufacturing method.

[0386] 7A and 7B will be described. Note that descriptions of parts that overlap with the above-described Manufacturing Method Example 1 will be omitted, and only differences will be described.

[0387] First, in the same manner as in Fabrication Method Example 1, the insulating layer 118 is formed (FIG. 26B).

[0388] [Formation of Insulating Layer 130] Subsequently, the insulating layer 130 is formed on the insulating layer 118 (FIG. 27A). The insulating layer 130 has openings in areas that do not overlap with the semiconductor layer 108 or the semiconductor layer 208.

[0389] For example, when a photosensitive organic material is used for the insulating layer 130, a composition containing the organic material can be applied by spin coating, followed by selective exposure and development to form the insulating layer 130. As other formation methods, one or more of a sputtering method, a vapor deposition method, a droplet discharge method (inkjet method), screen printing, and offset printing may be used.

[0390] Heat treatment is preferably performed after the insulating layer 130 is formed. When an organic material is used for the insulating layer 130, the organic material can be cured by the heat treatment.

[0391] The temperature of the heat treatment is preferably lower than the heat resistance temperature of the organic material. For example, the temperature of the heat treatment is preferably 150°C or higher and 350°C or lower, more preferably 180°C or higher and 300°C or lower, even more preferably 200°C or higher and 270°C or lower, even more preferably 200°C or higher and 250°C or lower, and even more preferably 220°C or higher and 250°C or lower.

[0392] The heat treatment can be performed in an atmosphere containing a noble gas or nitrogen. Alternatively, the heat treatment can be performed in a dry air atmosphere. Note that it is preferable that the heat treatment atmosphere contains as little hydrogen, water, or the like as possible. For example, an electric furnace or an RTA apparatus can be used for the heat treatment.

[0393] [Formation of openings 141a, 141b, 241a, and 241b] Next, portions of insulating layer 118, insulating layer 110, and insulating layer 117 are etched to form openings 141a and 141b that reach low-resistance region 108N, and openings 241a and 241b that reach low-resistance region 208N (Figure 27B).

[0394] [Formation of Conductive Layers 120a, 120b, 220a, and 220b] Subsequently, a conductive film is formed on the insulating layer 130 so as to cover the openings 141a, 141b, 241a, and 241b, and the conductive film is processed into a desired shape to form the conductive layers 120a, 120b, 220a, and 220b ( FIGS. 7A and 7B ).

[0395] Through the above steps, the transistor 100C and the transistor 200C can be manufactured.

[0396] 8A and the like, an insulating film to be the insulating layer 132 may be formed after the insulating layer 130 is formed, and the openings 143a, 143b, 243a, and 243b may be formed in the insulating film. Thereafter, the conductive layers 120a, 120b, 220a, and 220b may be formed. After the insulating layer 130 is formed and before the insulating film to be the insulating layer 132 is formed, heat treatment is preferably performed.

[0397] The above is the description of the second manufacturing method example.

[0398] 17A and 17B will be described. Note that descriptions of parts that overlap with the above-described Manufacturing Method Example 1 will be omitted, and only differences will be described.

[0399] First, similarly to Manufacturing Method Example 1, the conductive film 112f is formed (FIG. 25B).

[0400] [Formation of insulating layers 110a, 110b, 117a, 117b, conductive layer 112, and conductive layer 212] Next, a resist mask 137a and a resist mask 137b are formed over the conductive film 112f (FIG. 28A). After that, the conductive film 112f is removed in regions not covered with the resist mask 137a and the resist mask 137b, thereby forming the conductive layer 112 and the conductive layer 212 (FIG. 28B).

[0401] When the conductive layer 112 and the conductive layer 212 are formed, the conductive layer 112 is processed so that an end of the conductive layer 112 is positioned inside the outline of the resist mask 137a, and similarly, an end of the conductive layer 212 is positioned inside the outline of the resist mask 137b. A wet etching method can be suitably used to form the conductive layer 112 and the conductive layer 212. For example, an etchant containing hydrogen peroxide can be used for the wet etching method. For example, an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, and sulfuric acid can be used. In particular, when a material containing copper is used for the conductive layer 112 and the conductive layer 212, an etchant containing phosphoric acid, acetic acid, and nitric acid can be suitably used. The widths of the region 108L and the region 208L can be controlled by adjusting the etching time.

[0402] The conductive layer 112 and the conductive layer 212 may be formed by etching the conductive film 112f by anisotropic etching and then etching the side surfaces of the conductive film 112f by isotropic etching to recess the end faces (also referred to as side etching). This allows the conductive layer 112 located inside the insulating layer 110a and the conductive layer 212 located inside the insulating layer 110b in a plan view to be formed.

[0403] Subsequently, the insulating layer 110 and the insulating layer 117 are removed from the regions not covered with the resist mask 137a and the resist mask 137b, thereby forming the insulating layer 110a, the insulating layer 117a, and the insulating layer 110b (FIG. 29A). At this time, the insulating layer 117 is also removed from the region not covered with the semiconductor layer 208, and the insulating layer 117b may be formed so that the top surface shape thereof coincides or substantially coincides with that of the semiconductor layer 208.

[0404] The insulating layers 110a, 110b, 117a, and 117b can be formed by either a wet etching method or a dry etching method, or both. Note that the insulating layers 110a, 110b, 117a, and 117b may be formed after removing the resist masks 137a and 137b. However, by leaving the resist masks 137a and 137b, the thicknesses of the conductive layers 112 and 212 can be prevented from becoming thin.

[0405] Thereafter, the resist masks 137a and 137b are removed.

[0406] [Impurity Element Supplying Treatment] Next, a process of supplying (also referred to as adding or injecting) the impurity element 140 to the semiconductor layer 108 and the semiconductor layer 208 is performed using the conductive layer 112 and the conductive layer 212 as masks (FIG. 29B).

[0407] By supplying the impurity element 140, a low-resistance region 108N can be formed in a region of the semiconductor layer 108 that is not covered by the conductive layer 112, the insulating layer 117a, or the insulating layer 110a. A region 108L can be formed in a region of the semiconductor layer 108 that does not overlap with the conductive layer 112 and is covered by the insulating layer 117a and the insulating layer 110a. The impurity element 140 is supplied to the region 108L via the insulating layer 110a and the insulating layer 117a. Similarly, a low-resistance region 208N and a region 208L can be formed in the semiconductor layer 208. Note that the impurity element 140 is supplied to the region 208L via the insulating layer 110b.

[0408] Note that the amount of the impurity element 140 added to the region 108L can be made different from that of the region 208L by adjusting the thickness of the insulating layer 117. For example, by increasing the thickness of the insulating layer 117, the amount of the impurity element 140 added to the region 108L can be made smaller than that of the region 208L. On the other hand, by decreasing the thickness of the insulating layer 117, the amount of the impurity element 140 added to the region 108L can be made approximately the same as that of the region 208L.

[0409] Subsequently, the insulating layer 118 is formed. Steps after the formation of the insulating layer 118 may be performed in a manner similar to that of Manufacturing Method Example 1.

[0410] Through the above steps, the transistor 100J and the transistor 200J can be manufactured.

[0411] This concludes the description of the third example of manufacturing method.

[0412] 18A and 18B will be described. Note that descriptions of parts that overlap with the above-described Manufacturing Method Example 1 will be omitted, and only differences will be described.

[0413] First, in the same manner as in Fabrication Method Example 1, the insulating layer 110 is formed (FIG. 24C).

[0414] [Formation of Metal Oxide Film 114f] Subsequently, a metal oxide film 114f is formed on the insulating layer 110 (FIG. 30B).

[0415] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. This allows oxygen to be supplied to the insulating layer 110 during the formation of the metal oxide film 114f. Note that oxygen may be supplied to the insulating layer 117, the semiconductor layer 108, and the semiconductor layer 208 during the formation of the metal oxide film 114f.

[0416] It is preferable to use oxygen gas when forming the metal oxide film 114f. FIG. 30A shows a schematic cross-sectional view of the inside of a sputtering apparatus when forming the metal oxide film 114f on the insulating layer 110. FIG. 30A also shows a target 197 installed inside the sputtering apparatus and plasma 198 formed below the target 197. By using oxygen gas when forming the metal oxide film 114f, oxygen can be suitably supplied into the insulating layer 110. In FIG. 30A, the oxygen supplied to the insulating layer 110 is indicated by an arrow.

[0417] By supplying oxygen to the insulating layer 110, oxygen is supplied to the semiconductor layer 108 and the semiconductor layer 208 in a later step, and oxygen vacancies (V Ｏ ), and V Ｏ H can be reduced.

[0418] When the metal oxide film 114f is formed by a sputtering method using an oxide target containing a metal oxide similar to that in the case of the semiconductor layer 108 or the semiconductor layer 208, the above description of the semiconductor layer 108 and the semiconductor layer 208 can be used.

[0419] For example, the metal oxide film 114f may be formed by reactive sputtering using oxygen as a deposition gas and a metal target. When aluminum, for example, is used as the metal target, an aluminum oxide film can be formed.

[0420] During the deposition of the metal oxide film 114f, the higher the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus (oxygen flow rate ratio) or the higher the oxygen partial pressure in the deposition chamber, the more oxygen can be supplied to the insulating layer 110. The oxygen flow rate ratio or the oxygen partial pressure is, for example, 20% to 100%, preferably 30% to 100%, more preferably 40% to 100%, more preferably 50% to 100%, more preferably 65% ​​to 100%, more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% and to set the oxygen partial pressure in the deposition chamber as close to 100% as possible.

[0421] In this way, by forming the metal oxide film 114f by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating layer 110 during the formation of the metal oxide film 114f, and oxygen can be prevented from being released from the insulating layer 110. As a result, an extremely large amount of oxygen can be trapped in the insulating layer 110.

[0422] Heat treatment is preferably performed after the formation of the metal oxide film 114f. By the heat treatment, oxygen contained in the insulating layer 110 can be supplied to the semiconductor layer 108 and the semiconductor layer 208. By performing heating while the insulating layer 110 is covered with the metal oxide film 114f, oxygen is prevented from being released from the insulating layer 110 to the outside, and a large amount of oxygen can be supplied to the semiconductor layer 108 and the semiconductor layer 208. As a result, oxygen vacancies in the semiconductor layer 108 and the semiconductor layer 208 can be reduced, and a highly reliable transistor can be realized.

[0423] As for the heat treatment, the above description can be referred to, and therefore a detailed description thereof will be omitted.

[0424] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, there are cases where a high-temperature treatment in a later step (e.g., a film formation step) can also serve as the heat treatment.

[0425] After the metal oxide film 114f is formed or after the heat treatment, the metal oxide film 114f may be removed.

[0426] [Formation of Openings 142 and 242] Subsequently, the metal oxide film 114f, the insulating layer 110, the insulating layer 117, and the insulating layer 103 are partially etched to form openings 142 and 242 that reach the conductive layer 106 or the conductive layer 206 ( FIG. 30C ). This allows the conductive layer 106 to be electrically connected to the conductive layer 112, which will be formed later, through the openings 142. The conductive layer 206 and the conductive layer 212, which will be formed later, can be electrically connected to each other through the openings 142.

[0427] [Formation of Conductive Layer 112, Conductive Layer 212, Metal Oxide Layer 114, and Metal Oxide Layer 214] Subsequently, a conductive film 112f to be the conductive layer 112 and the conductive layer 212 is formed on the metal oxide film 114f.

[0428] The conductive film 112f is preferably formed using a low-resistance metal or alloy material, a material that does not easily release hydrogen and does not easily diffuse hydrogen, and a material that is not easily oxidized.

[0429] The conductive film 112f is preferably formed by, for example, a sputtering method using a sputtering target containing a metal or an alloy.

[0430] For example, the conductive film 112f is preferably a stacked film in which a conductive film that is resistant to oxidation and through which hydrogen does not easily diffuse and a conductive film with low resistance are stacked.

[0431] Subsequently, a resist mask 137a and a resist mask 137b are formed over the conductive film 112f (FIG. 31A).

[0432] Next, the conductive film 112f and the metal oxide film 114f in the regions not covered with the resist mask 137a and the resist mask 137b are removed to form the conductive layer 112, the conductive layer 212, the metal oxide layer 114, and the metal oxide layer 214 (FIG. 31B). The conductive film 112f and the metal oxide film 114f can be preferably etched by wet etching.

[0433] This allows the conductive layer 112 and the metal oxide layer 114, and the conductive layer 212 and the metal oxide layer 214, to be formed so that their top surface shapes are roughly the same.

[0434] In this way, by forming a structure in which the top surface and side surfaces of the semiconductor layer 208 and the insulating layer 117 are covered without etching the insulating layer 110, it is possible to prevent the semiconductor layer 208 and the insulating layer 117 from being etched and the film thickness from being reduced when the conductive film 112f and the like are etched.

[0435] Thereafter, the resist masks 137a and 137b are removed.

[0436] Next, a process of supplying (also referred to as adding or injecting) an impurity element to the semiconductor layer 108 and the semiconductor layer 208 is performed. Steps after the supply of the impurity element may be performed in the same manner as in Manufacturing Method Example 1.

[0437] This concludes the description of the fourth manufacturing method example.

[0438] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0439] Embodiment Mode 2 In this embodiment mode, a structural example of a display device to which the semiconductor device described in Embodiment Mode 1 can be applied will be described.

[0440] 32 shows a block diagram of the display device 10. The display device 10 has a display unit 11, a first drive circuit 12, and a second drive circuit 13.

[0441] A plurality of pixels PIX are arranged in a matrix in the display section 11. Each pixel includes at least one display element and one transistor. The display element may typically be an organic EL element or a liquid crystal element.

[0442] The first driver circuit 12 includes a circuit that functions as a source driver. The first driver circuit 12 has a function of generating a gray scale signal based on a video signal input from the outside and supplying the gray scale signal to the pixels of the display unit 11.

[0443] The second driver circuit 13 includes a circuit that functions as a gate driver. The second driver circuit 13 has a function of generating a selection signal based on a signal input from the outside and supplying the selection signal to the pixels of the display unit 11.

[0444] The pixel PIX in the display portion 11 and the second driver circuit 13 can be formed using the transistor 100 or the like described in Embodiment 1. The first driver circuit 12 can be formed using the transistor 200 or the like described in Embodiment 1. Note that the pixel PIX and the second driver circuit 13 can be formed using the transistor 200 or the like, or the first driver circuit 12 can be formed using the transistor 100, as needed.

[0445] The display section 11 is provided with a plurality of source lines SL connected to a first drive circuit 12 and a plurality of gate lines GL connected to a second drive circuit 13 .

[0446] <Configuration Example of First Drive Circuit> A more specific configuration example of the first drive circuit 12 included in the display device 10 will be described below.

[0447] The first drive circuit 12 includes a shift register circuit 31, a latch circuit section 41, a level shifter circuit section 42, a DA conversion section 43, an analog buffer circuit section 44, and the like.

[0448] The latch circuit section 41 has a plurality of latch circuits 32 and a plurality of latch circuits 33. The level shifter circuit section 42 has a plurality of level shifter circuits 34. The D-A conversion section 43 has a plurality of DAC circuits 35. The analog buffer circuit section 44 has a plurality of analog buffer circuits 36.

[0449] A clock signal CLK and a start pulse signal SP are input to the shift register circuit 31. The shift register circuit 31 generates a timing signal for sequentially shifting pulses in accordance with the clock signal CLK and the start pulse signal SP, and outputs the timing signal to each latch circuit 32 of the latch circuit unit 41.

[0450] The latch circuit section 41 receives the video signal S ０ , and a latch signal LAT are input.

[0451] When a timing signal is input to the latch circuit 32, the video signal S ０ is sampled and written in turn to each latch circuit 32. At this time, the video signal S ０ The period until the writing is completed can be called a line period.

[0452] When one line period is completed, the video signals held in each latch circuit 32 are simultaneously written into and held in each latch circuit 33 in accordance with the pulse of the latch signal LAT input to each latch circuit 33. After sending out the video signal to the latch circuit 33, the latch circuit 32 sequentially writes the next video signal in accordance with the timing signal from the shift register circuit 31. During this second one line period, the video signals written into and held in the latch circuit 33 are output to each level shifter circuit 34 of the level shifter circuit section 42.

[0453] The video signals input to each level shifter circuit 34 in the level shifter circuit section 42 have their voltage amplitudes amplified by the level shifter circuits 34, and are then sent to each DAC circuit 35 in the D-A conversion section 43. The group of video signals input to the DAC circuits 35 are converted to analog signals and output as one analog signal to the analog buffer circuit section 44. The video signals input to the analog buffer circuit section 44 are output to each source line SL via each analog buffer circuit 36.

[0454] On the other hand, the second drive circuit 13 sequentially selects each gate line GL. A video signal input from the first drive circuit 12 to the display unit 11 via the source line SL is input to each pixel PIX connected to the gate line GL selected by the second drive circuit 13.

[0455] Instead of the shift register circuit 31, other circuits capable of outputting signals in which pulses are shifted sequentially may be used.

[0456] <Modification of the first drive circuit> The first drive circuit 12 illustrated in FIG. 32 is configured to convert a digital signal into an analog signal and output it to the display unit 11. However, by using an analog signal as the input signal, the configuration of the first drive circuit 12 can be further simplified.

[0457] 33A includes a shift register circuit 31, a latch circuit section 41, and a source follower circuit section 45. The source follower circuit section 45 includes a plurality of source follower circuits 37.

[0458] The latch circuit 32 outputs the analog video signal S in accordance with the timing signal from the shift register circuit 31. ０ The latch circuits 32 simultaneously output the video signals held in the latch circuits 33 in accordance with the latch signal LAT.

[0459] The video signal held in the latch circuit 33 is output to one source line SL via a source follower circuit 37. The source follower circuit 37 may be replaced by the analog buffer circuit described above.

[0460] The first drive circuit 12b shown in FIG. 33B includes a shift register circuit 31 and a demultiplexer circuit 46.

[0461] The demultiplexer circuit 46 has a plurality of sampling circuits 38. Each sampling circuit 38 receives a plurality of analog video signals S from a plurality of wires. ０ is input, and video signals are simultaneously output to a plurality of source lines SL in accordance with a timing signal input from the shift register circuit 31. The shift register circuit 31 outputs a timing signal so as to sequentially select a plurality of sampling circuits 38.

[0462] For example, the number of source lines SL connected to the display unit 11 is 2160, and the number of video signal lines S ０ When the number of wirings through which the signal is supplied is 54, by providing 40 sampling circuits 38 in the demultiplexer circuit 46, one line period can be divided into 40 parts, and video signals can be output simultaneously to 54 source lines SL within each period.

[0463] The above is the description of the first driving circuit.

[0464] <Configuration Example of Display Unit> The display unit 11 can be configured to include at least one display element and a plurality of pixels PIX, each having one transistor, arranged in a matrix.

[0465] An example of a circuit diagram of the display unit 11 in the case where a light-emitting device is used as a display element is shown in Fig. 34. As shown in Fig. 34, the display unit 11 has m (m is an integer of 2 or more) gate lines GL (gate lines GL[1] to GL[m]) and n (n is an integer of 2 or more) source lines SL (source lines SL[1] to SL[n]) electrically connected thereto.

[0466] Each pixel PIX included in the display unit 11 includes a transistor 51, a transistor 52, a capacitor 53, and a light-emitting device 54. A source line SL, a gate line GL, and wirings VL1 and VL2 to which a power supply potential is supplied are connected to the pixel PIX.

[0467] The transistor 51 and the transistor 52 can be the transistor 100 or the like described in Embodiment 1. Note that the transistor 200 or the like described in Embodiment 1 may be used as one of the transistors 51 and 52 as needed.

[0468] The transistor 51 has a gate connected to a gate line GL, one of a source or a drain connected to a source line SL, and the other connected to one electrode of a capacitor 53 and the gate of the transistor 52. The transistor 52 has one of a source or a drain connected to one electrode of the light-emitting device 54, and the other connected to a wiring VL1. The capacitor 53 has the other electrode connected to a wiring VL1. The light-emitting device 54 has the other electrode connected to a wiring VL2.

[0469] The pixel PIX is selected by a signal supplied from the gate line GL. The light emission luminance of the light emitting device 54 can be controlled by controlling the current flowing through the light emitting device 54 using a potential written from the source line SL to a node to which the gate of the transistor 52 is connected via the transistor 51.

[0470] As the light-emitting device 54, it is preferable to use an EL device such as an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode). Examples of light-emitting materials that the EL device may have include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials). The TADF material may be a material that is in thermal equilibrium between a singlet excited state and a triplet excited state. Such TADF materials have a short emission lifetime (excitation lifetime), which can suppress a decrease in efficiency in the high-brightness region of the light-emitting device. The light-emitting device 54 is not limited to this, and may be an inorganic EL element containing an inorganic material, a light-emitting diode, etc. An LED such as a micro LED (Light Emitting Diode) may also be used as the light-emitting device.

[0471] Note that transistors having different semiconductor layer compositions may be mixed in the pixel PIX of the display unit 11. For example, the composition of the semiconductor layer of the transistor 51 may be different from the composition of the semiconductor layer of the transistor 52. Also, transistors having gate insulating layers with different thicknesses may be mixed.

[0472] Compared to the transistor 51 functioning as a selection transistor for controlling the selection state of the pixel PIX, the transistor 52 functioning as a drive transistor for controlling the current flowing through the light-emitting device 54 is in an environment in which a positive potential is applied to the gate, and therefore it is preferable to use a transistor with a small amount of variation in threshold voltage in a PBTS test. On the other hand, it is preferable to use a transistor with a small amount of variation in threshold voltage in an NBTIS test for the transistor 51. It is preferable to use a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer of the transistor 52. It is preferable to use a metal oxide that has a higher gallium content than the transistor 52 for the semiconductor layer of the transistor 51. Such a configuration can provide a highly reliable display device.

[0473] The above is a description of an example of the configuration of the display unit.

[0474] Note that transistors having different semiconductor layer compositions may be mixed in the first driver circuit 12. Also, transistors having different semiconductor layer compositions may be mixed in the second driver circuit 13. By configuring the transistors in accordance with the required electrical characteristics and reliability, a display device that has both excellent electrical characteristics and high reliability can be obtained.

[0475] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0476] Third Embodiment A specific configuration example of a display device will be described below.

[0477] When a pixel of a display device has three types of subpixels that exhibit different colors, the three subpixels include, for example, subpixels of three colors: red (R), green (G), and blue (B), and subpixels of three colors: yellow (Y), cyan (C), and magenta (M). When a pixel of a display device has four subpixels, the four subpixels include, for example, subpixels of four colors: red (R), green (G), blue (B), and white (W), and subpixels of four colors: red (R), green (G), blue (B), and yellow (Y). Each subpixel has a light-emitting device.

[0478] The layout of pixels in a display device will now be described. The arrangement of sub-pixels in a pixel is not particularly limited, and various methods can be applied. Examples of sub-pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0479] Examples of the top surface shape of the subpixel include a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon or a hexagon, a polygon with rounded corners, an ellipse, or a circle. Here, the top surface shape of the subpixel corresponds to the top surface shape of the light-emitting region of the light-emitting device.

[0480] The pixel 310 shown in Figure 35A has a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B). The pixel 310 shown in Figure 35A is arranged in a stripe pattern. The arrangement order of the sub-pixels is not limited to the configuration shown in Figure 35A. Although Figure 35A shows a configuration in which the sub-pixels have the same area, the sub-pixels may have different areas. Here, the area of ​​the sub-pixel corresponds to the area of ​​the light-emitting region of the light-emitting device. In Figure 35A, the symbols R, G, and B are assigned within the area of ​​each sub-pixel light-emitting element to easily distinguish between the sub-pixels.

[0481] The pixel 310 shown in Figure 35B has a configuration in which an S-stripe arrangement is applied. The pixel 310 shown in Figure 35B is configured with two rows and two columns, with the left column (first column) having two subpixels (subpixel (R) and subpixel (G)) and the right column (second column) having one subpixel (subpixel (B)). In other words, the pixel 310 has two subpixels (subpixel (R) and subpixel (B)) in the top row (first row) and two subpixels (subpixel (G) and subpixel (B)) in the bottom row (second row), with the subpixel (B) spanning these two rows.

[0482] 35B shows an example in which the area of ​​the subpixel (B) is larger than the areas of the subpixels (R) and (G). This configuration is suitable for use when the life of the light-emitting device emitting blue light is shorter than the life of the light-emitting device emitting red light and the light-emitting device emitting green light. In the subpixel (B) with a larger light-emitting area, the current density applied to the light-emitting device emitting blue light is lower, and therefore the life of the light-emitting device can be extended. In other words, a highly reliable display device can be obtained.

[0483] 35B shows a configuration in which the area of ​​the subpixel (B) is larger than the areas of the subpixels (R) and (G); however, one embodiment of the present invention is not limited to this. The area of ​​a subpixel can be determined depending on the lifetime of a light-emitting device included in the subpixel. It is preferable to make the area of ​​a subpixel having a light-emitting device with a short lifetime larger than the areas of the other subpixels.

[0484] Figure 35C shows two pixels. The pixels shown in Figure 35C have subpixels of different colors arranged in a zigzag pattern. Specifically, in each column, subpixels of different colors are arranged in odd-numbered rows and even-numbered rows.

[0485] FIG. 35D shows a pixel to which a Pentile arrangement is applied. The pixel shown in FIG. 35D has two pixels, pixel 310A and pixel 310B, each having three subpixels: a red subpixel (R), a green subpixel (G), and a blue subpixel (B). The two pixels, pixel 310A and pixel 310B, each have one subpixel (R), two subpixels (G), and one subpixel (B). This configuration allows the area of ​​the subpixels to be increased while maintaining a pseudo-high resolution, thereby reducing the required processing accuracy. In other words, compared with the same processing accuracy, it is possible to manufacture a display device with higher resolution. Furthermore, the number of transistors per area can be reduced, thereby improving productivity. Therefore, a pseudo-high-resolution display device can be manufactured with high productivity.

[0486] 36A and 36B illustrate a display device according to one embodiment of the present invention.

[0487] Fig. 36A shows a top view of a display device 300. The display device 300 has a display section in which a plurality of pixels 310 are arranged in a matrix, and a connection section 340 on the outside of the display section. One pixel 310 is composed of three subpixels: subpixel 310a, subpixel 310b, and subpixel 310c. Note that the pixel is not limited to the configuration shown in Fig. 36A.

[0488] 36A shows an example in which the connection portion 340 is located below the display portion when viewed from above, but this is not particularly limited. The connection portion 340 only needs to be located in at least one of the upper, right, left, and lower sides of the display portion when viewed from above, and may be located so as to surround all four sides of the display portion. Furthermore, the connection portion 340 may be singular or plural.

[0489] Fig. 36B shows cross-sectional views taken along dashed lines X1-X2 and Y1-Y2 in Fig. 36A. As modified examples, Figs. 37A to 37C, 38A and 38B, and 39A to 39C show cross-sectional views taken along dashed lines X1-X2 and Y1-Y2 in Fig. 36A.

[0490] 36B , display device 300 has light-emitting devices 330a, 330b, and 330c provided on transistor-containing layer 301, and protective layer 331 provided to cover these light-emitting devices. Substrate 320 is bonded to protective layer 331 with resin layer 322. In addition, insulating layer 325 and insulating layer 327 on insulating layer 325 are provided in the region between two adjacent light-emitting devices.

[0491] The display device of one embodiment of the present invention may be any of a top emission type that emits light in a direction opposite to a substrate on which a light-emitting device is formed, a bottom emission type that emits light toward a substrate on which a light-emitting device is formed, and a dual emission type that emits light from both sides.

[0492] The layer 301 including transistors can have, for example, a stacked structure in which a plurality of transistors are provided on a substrate and an insulating layer is provided to cover these transistors. The layer 301 including transistors may have a recess between two adjacent devices. For example, a recess may be provided in an insulating layer located on the top surface of the layer 301 including transistors. The transistor described in Embodiment 1 can be used as the transistor.

[0493] A light-emitting device has an EL layer between a pair of electrodes, one of which may be referred to as a pixel electrode and the other as a common electrode in this specification and the like.

[0494] A light-emitting device has a pair of electrodes, one of which functions as an anode and the other as a cathode. In the following, an example will be described in which the pixel electrode functions as the anode and the common electrode functions as the cathode.

[0495] The light-emitting device 330a includes a conductive layer 311a on the layer 301 including the transistor, a first layer 313a on the conductive layer 311a, a fourth layer 314 on the first layer 313a, and a common electrode 315 on the fourth layer 314. The conductive layer 311a functions as a pixel electrode. In the light-emitting device 330a, the first layer 313a and the fourth layer 314 can be collectively referred to as an EL layer.

[0496] The first layer 313a may include, for example, a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer, or may include, for example, a first light-emitting unit, a charge generation layer, and a second light-emitting unit.

[0497] The fourth layer 314 may include, for example, an electron injection layer, or may include a stack of an electron transport layer and an electron injection layer.

[0498] The light-emitting device 330b includes a conductive layer 311b on the layer 301 including the transistor, an island-shaped second layer 313b on the conductive layer 311b, a fourth layer 314 on the island-shaped second layer 313b, and a common electrode 315 on the fourth layer 314. The conductive layer 311b functions as a pixel electrode. In the light-emitting device 330b, the second layer 313b and the fourth layer 314 can be collectively referred to as an EL layer.

[0499] The light-emitting device 330c includes a conductive layer 311c on the layer 301 including the transistor, an island-shaped third layer 313c on the conductive layer 311c, a fourth layer 314 on the island-shaped third layer 313c, and a common electrode 315 on the fourth layer 314. The conductive layer 311c functions as a pixel electrode. In the light-emitting device 330c, the third layer 313c and the fourth layer 314 can be collectively referred to as an EL layer.

[0500] The fourth layer 314 is a layer shared by all the light-emitting devices. As described above, the fourth layer 314 includes, for example, an electron injection layer. Alternatively, the fourth layer 314 may include a stack of an electron transport layer and an electron injection layer.

[0501] The common electrode 315 is electrically connected to the conductive layer 323 provided in the connection portion 340. As a result, the same potential is supplied to the common electrode 315 of each light-emitting device. Note that FIG. 36B shows an example in which a fourth layer 314 is provided on the conductive layer 323, and the conductive layer 323 and the common electrode 315 are electrically connected via the fourth layer 314. The fourth layer 314 does not have to be provided in the connection portion 340. For example, FIG. 37C shows an example in which the fourth layer 314 is not provided on the conductive layer 323, and the conductive layer 323 and the common electrode 315 are directly connected.

[0502] For example, by using a mask for defining a deposition area (also called an area mask or a rough metal mask), the regions where the fourth layer 314 and the common electrode 315 are deposited can be changed.

[0503] The side surfaces of the conductive layers 311a to 311c, the first layer 313a, the second layer 313b, and the third layer 313c are covered with the insulating layer 325 and the insulating layer 327. This prevents the fourth layer 314 (or the common electrode 315) from contacting any of the side surfaces of the conductive layers 311a to 311c, the first layer 313a, the second layer 313b, and the third layer 313c, thereby preventing short circuits in the light-emitting device. This improves the reliability of the light-emitting device.

[0504] The insulating layer 325 preferably covers at least the side surfaces of the conductive layers 311a to 311c. Furthermore, the insulating layer 325 preferably covers the side surfaces of the first layer 313a, the second layer 313b, and the third layer 313c. The insulating layer 325 can be in contact with the side surfaces of the conductive layers 311a to 311c, the first layer 313a, the second layer 313b, and the third layer 313c.

[0505] The insulating layer 327 is provided over the insulating layer 325 so as to fill recesses formed in the insulating layer 325. The insulating layer 327 can overlap with side surfaces of the conductive layers 311a to 311c, the first layer 313a, the second layer 313b, and the third layer 313c with the insulating layer 325 interposed therebetween.

[0506] By providing the insulating layers 325 and 327, the gap between adjacent island-shaped layers can be filled, which reduces the unevenness of the surface on which a layer (such as a common electrode) is formed on the island-shaped layer, making the surface flatter. Therefore, coverage of the common electrode can be improved, and discontinuity of the common electrode can be prevented.

[0507] The insulating layer 325 or the insulating layer 327 can be provided so as to be in contact with the island-shaped layer. This can prevent the island-shaped layer from peeling off. The insulating layer and the island-shaped layer are in close contact with each other, which has the effect of fixing or bonding the adjacent island-shaped layers together.

[0508] An organic resin film is suitable for the insulating layer 327. If the side surface of the EL layer and the photosensitive organic resin film are in direct contact with each other, organic solvents that may be contained in the photosensitive organic resin film may damage the EL layer. By using an aluminum oxide film formed by atomic layer deposition (ALD) for the insulating layer 325, it is possible to prevent the photosensitive organic resin film used for the insulating layer 327 from being in direct contact with the side surface of the EL layer. This makes it possible to prevent the EL layer from being dissolved by an organic solvent.

[0509] Note that either the insulating layer 325 or the insulating layer 327 does not necessarily have to be provided. For example, by forming the insulating layer 325 to have a single-layer structure using an inorganic material, the insulating layer 325 can be used as a protective insulating layer for the EL layer. This can improve the reliability of the display device. Furthermore, by forming the insulating layer 327 to have a single-layer structure using an organic material, for example, the insulating layer 327 can fill the gap between adjacent EL layers and achieve planarization. This can improve the coverage of a common electrode (upper electrode) formed over the EL layer and the insulating layer 327.

[0510] The fourth layer 314 and the common electrode 315 are provided over the first layer 313a, the second layer 313b, the third layer 313c, the insulating layer 325, and the insulating layer 327. Before the insulating layer 325 and the insulating layer 327 are provided, a step is generated between a region where the pixel electrode and the EL layer are provided and a region where the pixel electrode and the EL layer are not provided (a region between light-emitting devices). In the display device of one embodiment of the present invention, the insulating layer 325 and the insulating layer 327 can flatten the step, thereby improving the coverage of the fourth layer 314 and the common electrode 315. Therefore, poor connection due to a step can be suppressed. Alternatively, an increase in electrical resistance caused by a local thinning of the common electrode 315 due to the step can be suppressed.

[0511] In order to improve the flatness of the surfaces on which the fourth layer 314 and the common electrode 315 are formed, it is preferable that the height of the upper surface of the insulating layer 325 and the upper surface of the insulating layer 327 be equal to or approximately equal to the height of the upper surface of at least one of the first layer 313a, the second layer 313b, and the third layer 313c. The upper surface of the insulating layer 327 preferably has a flat shape, and may have a convex portion, a convex curved surface, a concave curved surface, or a concave portion.

[0512] The insulating layer 325 has regions in contact with side surfaces of the first layer 313 a, the second layer 313 b, and the third layer 313 c, and functions as a protective insulating layer for the first layer 313 a, the second layer 313 b, and the third layer 313 c. By providing the insulating layer 325, impurities (oxygen, moisture, and the like) can be prevented from entering the inside from the side surfaces of the first layer 313 a, the second layer 313 b, and the third layer 313 c, thereby providing a highly reliable display device.

[0513] If the width (thickness) of the insulating layer 325 in the region in contact with the side surfaces of the first layer 313 a, the second layer 313 b, and the third layer 313 c is large in a cross-sectional view, the distance between the first layer 313 a, the second layer 313 b, and the third layer 313 c increases, which may result in a low aperture ratio. Also, if the width (thickness) of the insulating layer 325 is small, the effect of suppressing impurities from penetrating into the interior from the side surfaces of the first layer 313 a, the second layer 313 b, and the third layer 313 c may be reduced. The width (thickness) of the insulating layer 325 in the region in contact with the side surfaces of the first layer 313 a, the second layer 313 b, and the third layer 313 c is preferably 3 nm to 200 nm, more preferably 3 nm to 150 nm, further preferably 5 nm to 150 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, and further preferably 10 nm to 50 nm. By setting the width (thickness) of the insulating layer 325 in the above range, a display device having a high aperture ratio and high reliability can be obtained.

[0514] The insulating layer 325 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulating layer 325. The insulating layer 325 may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, aluminum oxide is preferable because it has a high etching selectivity with respect to the EL layer and functions to protect the EL layer in the formation of the insulating layer 327 described below. In particular, by using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an ALD method as the insulating layer 325, it is possible to form an insulating layer 325 with few pinholes and excellent protection of the EL layer. The insulating layer 325 may also have a stacked structure of a film formed by an ALD method and a film formed by a sputtering method. For example, the insulating layer 325 may have a stacked structure of an aluminum oxide film formed by an ALD method and a silicon nitride film formed by a sputtering method.

[0515] The insulating layer 325 can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a pulsed laser deposition (PLD) method, an ALD method, or the like. The insulating layer 325 is preferably formed by an ALD method, which has good coverage.

[0516] The insulating layer 327 provided on the insulating layer 325 has the function of planarizing recesses formed in the insulating layer 325 between adjacent light-emitting devices. In other words, the insulating layer 327 has the effect of improving the flatness of the surface on which the common electrode 315 is formed. An insulating layer containing an organic material can be suitably used as the insulating layer 327. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins can be used as the insulating layer 327. Alternatively, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can be used as the insulating layer 327. Alternatively, a photosensitive resin can be used as the photosensitive resin. The photosensitive resin can be a positive-type material or a negative-type material.

[0517] The difference in height between the top surface of the insulating layer 327 and the top surface of any of the first layer 313a, the second layer 313b, and the third layer 313c is, for example, preferably 0.5 times or less, more preferably 0.3 times or less, the thickness of the insulating layer 327. For example, the insulating layer 327 may be provided so that the top surface of any of the first layer 313a, the second layer 313b, and the third layer 313c is higher than the top surface of the insulating layer 327. For example, the insulating layer 327 may be provided so that the top surface of the insulating layer 327 is higher than the top surface of the light-emitting layer included in the first layer 313a, the second layer 313b, or the third layer 313c.

[0518] 37A shows an example in which the insulating layer 325 is not provided. In the case where the insulating layer 325 is not provided, the insulating layer 327 can be in contact with the side surfaces of the conductive layers 311a to 311c, the first layer 313a, the second layer 313b, and the third layer 313c. The insulating layer 327 can be provided to fill the spaces between the EL layers of the light-emitting devices.

[0519] In this case, it is preferable to use an organic material that causes less damage to the first layer 313 a, the second layer 313 b, and the third layer 313 c for the insulating layer 327. For example, it is preferable to use an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin for the insulating layer 327.

[0520] FIG. 37B shows an example in which the insulating layer 327 is not provided.

[0521] It is preferable to provide a protective layer 331 on the light emitting devices 330a, 330b, and 330c. By providing the protective layer 331, the reliability of the light emitting devices can be improved.

[0522] There is no restriction on the conductivity of the protective layer 331. The protective layer 331 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film.

[0523] By having the protective layer 331 be an inorganic film, it is possible to prevent oxidation of the common electrode 315 and to prevent impurities (moisture, oxygen, etc.) from entering the light-emitting devices 330a, 330b, and 330c, thereby suppressing deterioration of the light-emitting devices and improving the reliability of the display device.

[0524] The protective layer 331 can be made of an inorganic insulating film such as an insulating oxide film, an insulating nitride film, an insulating oxynitride film, or an insulating nitride oxide film. Examples of the insulating oxide film include a silicon oxide film, an aluminum oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film and an aluminum oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film.

[0525] The protective layer 331 preferably includes an insulating nitride film or an insulating nitride oxide film, and more preferably includes an insulating nitride film.

[0526] An inorganic film containing In—Sn oxide (also referred to as ITO), In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), or the like can also be used for the protective layer 331. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 315. The inorganic film may further contain nitrogen.

[0527] When light emitted from the light-emitting device is extracted through the protective layer 331, it is preferable that the protective layer 331 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0528] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 331. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0529] Furthermore, the protective layer 331 may include an organic film. For example, the protective layer 331 may include both an organic film and an inorganic film.

[0530] Since the upper end portions of the conductive layers 311 a to 311 c are not covered with an insulating layer, the distance between adjacent light-emitting devices can be made extremely narrow, thereby enabling a high-definition or high-resolution display device.

[0531] As shown in FIGS. 38A and 38B, the ends of the conductive layers 311a to 311c may be covered with an insulating layer 321.

[0532] The insulating layer 321 can have a single-layer structure or a stacked-layer structure using one or both of an inorganic insulating film and an organic insulating film.

[0533] Examples of organic insulating materials that can be used for the insulating layer 321 include acrylic resins, epoxy resins, polyimide resins, polyamide resins, polyimideamide resins, polysiloxane resins, benzocyclobutene-based resins, and phenolic resins. In addition, as an inorganic insulating film that can be used for the insulating layer 321, an inorganic insulating film that can be used for the protective layer 331 can be used.

[0534] When an inorganic insulating film is used as the insulating layer 321 covering the edge of the pixel electrode, impurities are less likely to enter the light-emitting device than when an organic insulating film is used, thereby improving the reliability of the light-emitting device. When an organic insulating film is used as the insulating layer 321 covering the edge of the pixel electrode, step coverage is higher and the insulating layer is less affected by the shape of the pixel electrode than when an inorganic insulating film is used. Therefore, short circuits in the light-emitting device can be prevented. Specifically, when an organic insulating film is used as the insulating layer 321, the insulating layer 321 can be processed into a tapered shape or the like. Note that, in this specification, a tapered shape refers to a shape in which at least a portion of the side surface of the structure is inclined with respect to the substrate surface. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface (also referred to as the taper angle) is less than 90°.

[0535] Note that the insulating layer 321 does not necessarily have to be provided. By not providing the insulating layer 321, the aperture ratio of the sub-pixels can be increased in some cases. Alternatively, the distance between the sub-pixels can be narrowed, and the definition or resolution of the display device can be improved in some cases.

[0536] Note that while Figure 38A shows an example in which the fourth layer 314 penetrates into the region between the first layer 313a and the second layer 313b, a void 334 may be formed in that region as shown in Figure 38B.

[0537] The void 334 contains, for example, one or more selected from air, nitrogen, oxygen, carbon dioxide, and a Group 18 element (typically, helium, neon, argon, xenon, krypton, etc.). Alternatively, a resin or the like may be embedded in the void 334.

[0538] 36A and the like show an example in which the end of the conductive layer 311a and the end of the first layer 313a are aligned or substantially aligned. In other words, the top surface shapes of the conductive layer 311a and the first layer 313a are aligned or substantially aligned.

[0539] There is no particular limitation on the size relationship between the conductive layer 311a and the first layer 313a, the conductive layer 311b and the second layer 313b, the conductive layer 311c and the third layer 313c, etc. Figure 39A shows an example in which the end of the first layer 313a is located inside the end of the conductive layer 311a. In Figure 39A, the end of the first layer 313a is located on the conductive layer 311a. Also, Figure 39B shows an example in which the end of the first layer 313a is located outside the end of the conductive layer 311a. In Figure 39B, the first layer 313a is provided so as to cover the end of the conductive layer 311a.

[0540] In addition, when the edges are aligned or approximately aligned, and when the top surface shapes are the same or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap when viewed from above. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, it is also said that the edges are approximately aligned, or the top surface shapes are approximately aligned.

[0541] Fig. 39C shows a modified example of insulating layer 327. In Fig. 39C, the upper surface of insulating layer 327 has a shape that gently bulges toward the center, i.e., a convex curved surface, in a cross-sectional view, and a shape that is recessed in the center and its vicinity, i.e., a concave curved surface.

[0542] 40A to 40F show the cross-sectional structure of a region 139 including the insulating layer 327 and its surroundings.

[0543] FIG. 40A shows an example in which the first layer 313a and the second layer 313b have different thicknesses. The height of the top surface of the insulating layer 325 on the first layer 313a side is the same as or approximately the same as the top surface of the first layer 313a, and the height of the top surface of the second layer 313b on the second layer 313b side is the same as or approximately the same as the top surface of the second layer 313b. The top surface of the insulating layer 327 has a gentle slope, with the first layer 313a side being higher and the second layer 313b side being lower. In this way, the heights of the insulating layers 325 and 327 are preferably the same as the top surfaces of the adjacent EL layers. Alternatively, the top surface may have a flat portion that is the same as the top surface of one of the adjacent EL layers.

[0544] 40B , the upper surface of insulating layer 327 has a region that is higher than the upper surface of first layer 313 a and the upper surface of second layer 313 b. As shown in FIG. 40B , the upper surface of insulating layer 327 can be configured to have a shape in which the center and its vicinity bulge in cross section, that is, a shape having a convex curve.

[0545] 40C , the upper surface of insulating layer 327 has a shape that gradually bulges toward the center, i.e., a convex curved surface, and a shape that is recessed in the center and its vicinity, i.e., a concave curved surface, in a cross-sectional view. Insulating layer 327 has a region that is higher than the upper surface of first layer 313a and the upper surface of second layer 313b. In addition, in region 139, the display device includes at least one of sacrificial layer 318a and sacrificial layer 319a, and insulating layer 327 has a first region that is higher than the upper surfaces of first layer 313a and second layer 313b and located outside insulating layer 325, and the first region is located on at least one of sacrificial layer 318a and sacrificial layer 319a. In addition, in region 139, the display device has at least one of sacrificial layer 318b and sacrificial layer 319b, and has a second region in which insulating layer 327 is higher than the top surface of the first layer 313a and the top surface of the second layer 313b and is located outside insulating layer 325, and the second region is located on at least one of sacrificial layer 318b and sacrificial layer 319b.

[0546] 40D , the upper surface of insulating layer 327 has an area that is lower than the upper surfaces of first layer 313 a and second layer 313 b. In addition, the upper surface of insulating layer 327 has a recessed shape in the center and its vicinity, that is, a shape having a concave curved surface, in cross-sectional view.

[0547] 40E, the upper surface of the insulating layer 325 has a region higher than the upper surface of the first layer 313a and the upper surface of the second layer 313b. That is, the insulating layer 325 protrudes from the surface on which the fourth layer 314 is to be formed, forming a convex portion.

[0548] When forming the insulating layer 325, for example, if the insulating layer 325 is formed so that its height is aligned or approximately aligned with that of the sacrificial layer, the insulating layer 325 may be formed in a protruding shape as shown in FIG. 40E.

[0549] 40F, the upper surface of the insulating layer 325 has an area lower than the upper surfaces of the first layer 313a and the second layer 313b. That is, the insulating layer 325 forms a recess on the surface where the fourth layer 314 is to be formed.

[0550] In this way, the insulating layer 325 and the insulating layer 327 can be applied to various shapes.

[0551] As the sacrificial layer, for example, a metal film, an alloy film, a metal oxide film, a semiconductor film, or an inorganic film such as an inorganic insulating film can be used.

[0552] The sacrificial layer can be made of a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium, and tantalum, or an alloy material containing such a metal material.

[0553] The sacrificial layer can be made of a metal oxide such as In—Ga—Zn oxide. For example, an In—Ga—Zn oxide film can be formed as the sacrificial layer by sputtering. Furthermore, indium oxide, In—Zn oxide, In—Sn oxide, indium titanium oxide (In—Ti oxide), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide), etc. can also be used. Alternatively, indium tin oxide containing silicon can also be used.

[0554] Instead of the gallium, an element M (wherein M is one or more elements selected from aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) may be used. In particular, it is preferable that M is one or more elements selected from gallium, aluminum, and yttrium.

[0555] The sacrificial layer can be made of any of various inorganic insulating films that can be used for the protective layer 331. In particular, an oxide insulating film is preferable because it has higher adhesion to the EL layer than a nitride insulating film. For example, the sacrificial layer can be made of an inorganic insulating material such as aluminum oxide, hafnium oxide, or silicon oxide. For example, an aluminum oxide film can be formed as the sacrificial layer by using the ALD method. The ALD method is preferable because it can reduce damage to the base (particularly the EL layer, etc.). For example, a silicon nitride film can be formed as the sacrificial layer by using the sputtering method.

[0556] For example, the sacrificial layer may be a stacked structure of an inorganic insulating film (e.g., an aluminum oxide film) formed by ALD and an In—Ga—Zn oxide film formed by sputtering, or a stacked structure of an inorganic insulating film (e.g., an aluminum oxide film) formed by ALD and an aluminum film, a tungsten film, or an inorganic insulating film (e.g., a silicon nitride film) formed by sputtering.

[0557] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0558] In this specification and the like, a structure in which different light-emitting layers are fabricated or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting device, increasing the freedom of material and configuration selection and facilitating improvements in brightness and reliability.

[0559] In this specification and the like, a light-emitting device capable of emitting white light may be referred to as a white light-emitting device. Note that a white light-emitting device can be combined with a colored layer (for example, a color filter) to realize a full-color display device.

[0560] Light-emitting devices can be broadly divided into single structures and tandem structures. A single-structure device has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, light-emitting layers can be selected so that the emission colors of the light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration in which the light-emitting device as a whole emits white light can be obtained. Furthermore, when three or more light-emitting layers are used to obtain white light emission, the emission colors of the light-emitting layers can be combined to produce a configuration in which the light-emitting device as a whole emits white light.

[0561] A tandem-structure device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, light from the light-emitting layers of the light-emitting units may be combined to obtain white light emission. The configuration for obtaining white light emission is the same as that of the single-structure device. In a tandem-structure device, it is preferable to provide an intermediate layer such as a charge-generating layer between the light-emitting units.

[0562] When the above-described white light-emitting device (single structure or tandem structure) is compared with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. When it is desired to reduce power consumption, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, and therefore the manufacturing cost can be reduced or the manufacturing yield can be increased, making it preferable.

[0563] The display device of this embodiment can reduce the distance between light-emitting devices. Specifically, the distance between light-emitting devices, the distance between EL layers, or the distance between pixel electrodes can be less than 10 μm, 5 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the distance between the side surface of the first layer 313 a and the side surface of the second layer 313 b or the distance between the side surface of the second layer 313 b and the side surface of the third layer 313 c has a region of 1 μm or less, preferably a region of 0.5 μm (500 nm) or less, and more preferably a region of 100 nm or less.

[0564] A light-shielding layer may be provided on the surface of substrate 320 facing resin layer 322. Various optical components may be disposed on the outside of substrate 320. Examples of optical components include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. The outside of substrate 320 may also be provided with an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses scratches during use, an impact absorbing layer, and the like.

[0565] The substrate 320 can be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting device is extracted. Using a flexible material for the substrate 320 can increase the flexibility of the display device. Alternatively, a polarizing plate may be used as the substrate 320.

[0566] The substrate 320 may be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. The substrate 320 may be made of glass having a thickness sufficient to provide flexibility.

[0567] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has small birefringence (or a small amount of birefringence).

[0568] The absolute value of the retardation (phase difference) of a substrate having high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0569] Examples of films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0570] When a film is used as a substrate, the film may absorb water, which may cause changes in shape, such as wrinkles, in the display panel. Therefore, it is preferable to use a film with low water absorption as the substrate. For example, it is preferable to use a film with a water absorption rate of 1% or less, more preferably 0.1% or less, and even more preferably 0.01% or less.

[0571] The resin layer 322 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Materials with low moisture permeability, such as epoxy resin, are particularly preferred. Two-component resins may also be used. Adhesive sheets or the like may also be used.

[0572] Materials that can be used for conductive layers such as the gate, source, and drain of a transistor, as well as various wirings and electrodes that constitute a display device include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, and alloys containing these metals as main components, etc. Films containing these materials can be used as a single layer or a stacked layer structure.

[0573] Examples of light-transmitting conductive materials include conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide containing gallium, or graphene. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, or alloy materials containing such metal materials, can be used. Alternatively, nitrides of such metal materials (e.g., titanium nitride) can be used. When using metal materials or alloy materials (or their nitrides), it is preferable to thin them sufficiently to ensure light-transmitting properties. A stacked film of the above materials can also be used as the conductive layer. For example, a stacked film of an alloy of silver and magnesium and indium tin oxide is preferable because it can enhance conductivity. These materials can also be used for conductive layers such as various wirings and electrodes constituting display devices, and conductive layers (conductive layers functioning as pixel electrodes or common electrodes) in light-emitting devices.

[0574] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0575] Next, materials that can be used in light-emitting devices will be described.

[0576] A conductive film that transmits visible light and infrared light is used for the electrode from which light is extracted, and a conductive film that reflects visible light and infrared light is preferably used for the electrode from which light is not extracted.

[0577] The light-emitting device preferably has a micro-optical resonator (microcavity) structure. Therefore, one of a pair of electrodes of the light-emitting device preferably has a transmissive and reflective electrode for visible light, and the other preferably has a reflective electrode for visible light. By having the light-emitting device have a microcavity structure, light emitted from the light-emitting layer can be resonated between the two electrodes, thereby intensifying the light emitted from the light-emitting device.

[0578] The semi-transmitting / semi-reflective electrode can have a laminated structure of an electrode that is reflective to visible light and an electrode that is transparent to visible light (also referred to as a transparent electrode).

[0579] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode with a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for a light-emitting device. The visible light reflectance of the semi-transparent / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes is 1×10 −２ The transmittance or reflectance of these electrodes for near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less) preferably satisfies the above-mentioned range, similar to the transmittance or reflectance for visible light.

[0580] The first layer 313 a, the second layer 313 b, and the third layer 313 c each have a light-emitting layer. It is preferable that the first layer 313 a, the second layer 313 b, and the third layer 313 c each have a light-emitting layer that emits light of a different color.

[0581] The light-emitting layer is a layer containing a light-emitting substance. The light-emitting layer can contain one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0582] The first layer 313 a, the second layer 313 b, and the third layer 313 c may further include a layer containing a substance with high hole-injection properties, a substance with high hole-transport properties, a hole-blocking material, a substance with high electron-transport properties, a substance with high electron-injection properties, an electron-blocking material, or a bipolar substance (a substance with high electron-transport properties and high hole-transport properties), as a layer other than the light-emitting layer.

[0583] The light-emitting device can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting device can be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, inkjet printing, or coating.

[0584] For example, the first layer 313 a, the second layer 313 b, and the third layer 313 c may each include one or more of a hole-injection layer, a hole-transport layer, a hole-blocking layer, an electron-blocking layer, an electron-transport layer, and an electron-injection layer. The first layer 313 a, the second layer 313 b, and the third layer 313 c may each include a charge-generation layer (also referred to as an intermediate layer).

[0585] The fourth layer 314 may include one or more of a hole injection layer, a hole transport layer, a hole blocking layer, an electron blocking layer, an electron transport layer, and an electron injection layer. For example, when the conductive layers 311 a to 311 c function as anodes and the common electrode 315 functions as a cathode, the fourth layer 314 preferably includes an electron injection layer.

[0586] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound and a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0587] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting display devices can be formed using a sputtering method, a CVD method, a vacuum deposition method, a PLD method, an ALD method, etc. CVD methods include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0588] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the display device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0589] In particular, vacuum processes such as vapor deposition and solution processes such as spin coating and inkjet printing can be used to fabricate light-emitting devices. Vapor deposition methods include physical vapor deposition (PVD) methods such as sputtering, ion plating, ion beam deposition, molecular beam deposition, and vacuum deposition, and chemical vapor deposition (CVD). In particular, functional layers included in the EL layer (hole injection layer, hole transport layer, light-emitting layer, electron transport layer, electron injection layer, etc.) can be formed by vapor deposition (vacuum deposition, etc.), coating methods (dip coating, die coating, bar coating, spin coating, spray coating, etc.), printing methods (inkjet printing, screen (stencil printing), offset (lithographic printing), flexography (relief printing), gravure, microcontact printing, etc.), etc.

[0590] When processing the thin film that constitutes the display device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0591] As described above, in the display device of this embodiment, the island-shaped EL layer is formed by processing the EL layer after it is formed on the entire surface, rather than by a metal mask pattern, so that the island-shaped EL layer can be formed with a uniform thickness. Furthermore, a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve until now, can be realized.

[0592] The first, second, and third layers constituting the light-emitting device of each color are formed in separate processes. Therefore, each EL layer can be fabricated with a configuration (material, film thickness, etc.) suitable for the light-emitting device of each color. This allows the fabrication of light-emitting devices with excellent characteristics.

[0593] This embodiment mode can be combined with other embodiment modes as appropriate.

[0594] Embodiment 4 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0595] The display device of the present embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of the present embodiment can be used in electronic devices having relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproducing devices.

[0596] FIG. 41 shows a perspective view of the display device 300A, and FIG. 42 shows a cross-sectional view of the display device 300A.

[0597] The display device 300A has a configuration in which a substrate 352 and a substrate 351 are bonded together. In Fig. 41, the substrate 352 is clearly indicated by a dashed line.

[0598] The display device 300A includes a display portion 362, a connection portion 340, a circuit 364, wiring 365, etc. Fig. 41 shows an example in which an IC 373 and an FPC 372 are mounted on the display device 300A. Therefore, the configuration shown in Fig. 41 can also be said to be a display module including the display device 300A, an IC (integrated circuit), and an FPC.

[0599] The connection portion 340 is provided on the outside of the display portion 362. The connection portion 340 can be provided along one side or multiple sides of the display portion 362. The connection portion 340 may be single or multiple. FIG. 41 shows an example in which the connection portion 340 is provided so as to surround the four sides of the display portion. The connection portion 340 electrically connects the common electrode of the light-emitting device and the conductive layer, and can supply a potential to the common electrode.

[0600] The circuit 364 can be, for example, a scanning line driver circuit.

[0601] The wiring 365 has a function of supplying signals and power to the display portion 362 and the circuit 364. The signals and power are input to the wiring 365 from the outside via the FPC 372 or from the IC 373.

[0602] 41 shows an example in which an IC 373 is provided on a substrate 351 by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like. The IC 373 may be, for example, an IC having a scanning line driver circuit or a signal line driver circuit. The display device 300A and the display module may not necessarily include an IC. Alternatively, the IC may be mounted on an FPC by a COF method or the like.

[0603] Figure 42 shows an example of a cross section of the display device 300A, where a portion of the area including the FPC 372, a portion of the circuit 364, a portion of the display unit 362, a portion of the connection portion 340, and a portion of the area including the end portion are cut away.

[0604] The display device 300A shown in Figure 42 has, between a substrate 351 and a substrate 352, a transistor 201, a transistor 205, a light-emitting device 330a that emits red light, a light-emitting device 330b that emits green light, and a light-emitting device 330c that emits blue light.

[0605] The light-emitting device 330a includes a conductive layer 311a, a conductive layer 312a on the conductive layer 311a, and a conductive layer 326a on the conductive layer 312a. All or some of the conductive layers 311a, 312a, and 326a may be called pixel electrodes.

[0606] The conductive layer 311a is connected to the conductive layer 222b of the transistor 205 through an opening provided in the insulating layer 324. The end of the conductive layer 312a is located outside the end of the conductive layer 311a. The end of the conductive layer 312a and the end of the conductive layer 326a are aligned or approximately aligned. For example, a conductive layer functioning as a reflective electrode can be used for the conductive layer 311a and the conductive layer 312a, and a conductive layer functioning as a transparent electrode can be used for the conductive layer 326a.

[0607] The light-emitting device 330b includes a conductive layer 311b, a conductive layer 312b on the conductive layer 311b, and a conductive layer 326b on the conductive layer 312b.

[0608] The light-emitting device 330c includes a conductive layer 311c, a conductive layer 312c on the conductive layer 311c, and a conductive layer 326c on the conductive layer 312c.

[0609] The conductive layer 311b, the conductive layer 312b, and the conductive layer 326b in the light-emitting device 330b, and the conductive layer 311c, the conductive layer 312c, and the conductive layer 326c in the light-emitting device 330c are similar to the conductive layer 311a, the conductive layer 312a, and the conductive layer 326a in the light-emitting device 330a, and therefore detailed description thereof will be omitted.

[0610] The conductive layers 311a, 311b, and 311c have recesses formed therein so as to cover openings formed in the insulating layer 324. A layer 328 is buried in the recesses.

[0611] The layer 328 has a function of planarizing recesses of the conductive layer 311a, the conductive layer 311b, and the conductive layer 311c. The conductive layers 312a, 312b, and 312c, which are electrically connected to the conductive layer 311a, the conductive layer 311b, and the conductive layer 311c, are provided over the conductive layers 311a, 311b, 311c, and the layer 328. Therefore, regions overlapping with the recesses of the conductive layers 311a, 311b, and 311c can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased.

[0612] The layer 328 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 328. In particular, the layer 328 is preferably formed using an insulating material.

[0613] An insulating layer containing an organic material can be suitably used as the layer 328. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, precursors of these resins, or the like can be used as the layer 328. Alternatively, a photosensitive resin can be used as the layer 328. The photosensitive resin can be a positive material or a negative material.

[0614] By using a photosensitive resin, the layer 328 can be formed only through exposure and development steps, and the influence of dry etching, wet etching, etc. on the surfaces of the conductive layers 311 a, 311 b, and 311 c can be reduced. Furthermore, by forming the layer 328 using a negative photosensitive resin, the layer 328 can be formed using the same photomask (exposure mask) as that used to form the openings in the insulating layer 324 in some cases.

[0615] The top and side surfaces of the conductive layer 312a and the conductive layer 326a are covered with the first layer 313a. The top and side surfaces of the conductive layer 312b and the conductive layer 326b are covered with the second layer 313b. The top and side surfaces of the conductive layer 312c and the conductive layer 326c are covered with the third layer 313c. Therefore, the entire region where the conductive layer 312a, the conductive layer 312b, or the conductive layer 312c is provided can be used as the light-emitting region of the light-emitting device 330a, the light-emitting device 330b, or the light-emitting device 330c, thereby increasing the aperture ratio of the pixel.

[0616] The side surfaces of the first layer 313a, the second layer 313b, and the third layer 313c are covered with an insulating layer 325 and an insulating layer 327, respectively. A sacrificial layer 318a is located between the first layer 313a and the insulating layer 325, a sacrificial layer 318b is located between the second layer 313b and the insulating layer 325, and a sacrificial layer 318c is located between the third layer 313c and the insulating layer 325. A fourth layer 314 is provided on the first layer 313a, the second layer 313b, the third layer 313c, the insulating layer 325, and the insulating layer 327, and a common electrode 315 is provided on the fourth layer 314. The fourth layer 314 and the common electrode 315 are each a continuous film provided in common to a plurality of light-emitting devices. In addition, a protective layer 331 is provided on the light emitting device 330a, the light emitting device 330b, and the light emitting device 330c.

[0617] The protective layer 331 and the substrate 352 are bonded via an adhesive layer 342. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light-emitting device. In FIG. 42 , the space between the substrates 352 and 351 is filled with the adhesive layer 342, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 342 may be provided so as not to overlap with the light-emitting device. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 342.

[0618] In the connection portion 340, a conductive layer 323 is provided over the insulating layer 324. The conductive layer 323 has an example of a stacked structure including a conductive film obtained by processing the same conductive film as the conductive layers 311a, 311b, and 311c, a conductive film obtained by processing the same conductive film as the conductive layers 312a, 312b, and 312c, and a conductive film obtained by processing the same conductive film as the conductive layers 326a, 326b, and 326c. Ends of the conductive layer 323 are covered with a sacrificial layer, an insulating layer 325, and an insulating layer 327. A fourth layer 314 is provided over the conductive layer 323, and a common electrode 315 is provided over the fourth layer 314. The conductive layer 323 and the common electrode 315 are electrically connected via the fourth layer 314. The fourth layer 314 does not necessarily have to be formed in the connection portion 340. In this case, the conductive layer 323 and the common electrode 315 are in direct contact with each other and electrically connected.

[0619] The display device 300A is a top-emission type. Light emitted by the light-emitting device is emitted toward the substrate 352. The substrate 352 is preferably made of a material that is highly transparent to visible light. The pixel electrode contains a material that reflects visible light, and the counter electrode (common electrode 315) contains a material that transmits visible light.

[0620] The stacked structure from the substrate 351 to the insulating layer 324 corresponds to the layer 301 including the above-described transistor. The transistors described in Embodiment 1 can be applied to the transistors 201 and 205 included in the layer 301. For example, the transistor 200A can be applied to the circuit 364, and the transistor 100A can be applied to the display portion 362. The semiconductor layers of the transistors 100A and 200A each contain indium, and the ratio of the number of indium atoms to the number of metal element atoms contained in the semiconductor layer of the transistor 200A is preferably higher than that of the transistor 100A. With this structure, a display device having both excellent electrical characteristics and high reliability can be obtained. The multiple transistors included in the circuit 364 may all have the same structure, or two or more types of transistors may be used. Similarly, the multiple transistors included in the display portion 362 may all have the same structure, or two or more types of transistors may be used.

[0621] The insulating layer 215 is provided to cover the transistor. The insulating layer 324 is provided to cover the transistor and functions as a planarization layer. Note that the number of insulating layers covering the transistor is not limited, and each insulating layer may be a single layer or two or more layers.

[0622] At least one insulating layer covering the transistor is preferably made of a material that is resistant to the diffusion of impurities such as water and hydrogen. This allows the insulating layer to function as a barrier layer. With this structure, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the display device.

[0623] An inorganic insulating film is preferably used as the insulating layer 215. Examples of inorganic insulating films that can be used include a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, and an aluminum nitride film. Alternatively, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film may also be used. Two or more of the above insulating films may be stacked.

[0624] An organic insulating film can be suitably used for the insulating layer 324, which functions as a planarization layer. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. The insulating layer 324 may also have a stacked structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 324 preferably functions as an etching protection film. This can prevent recesses from being formed in the insulating layer 324 during processing of the conductive layer 311b, the conductive layer 312b, the conductive layer 326b, or the like. Alternatively, recesses may be formed in the insulating layer 324 during processing of the conductive layer 311b, the conductive layer 312b, the conductive layer 326b, or the like.

[0625] A connection portion 204 is provided in a region of the substrate 351 where the substrate 352 does not overlap. In the connection portion 204, a wiring 365 is electrically connected to the FPC 372 via a conductive layer 366 and a connection layer 203. The conductive layer 366 has an example of a stacked structure including a conductive film obtained by processing the same conductive film as the conductive layers 311a, 311b, and 311c, a conductive film obtained by processing the same conductive film as the conductive layers 312a, 312b, and 312c, and a conductive film obtained by processing the same conductive film as the conductive layers 326a, 326b, and 326c. The conductive layer 366 is exposed on the top surface of the connection portion 204. This allows the connection portion 204 and the FPC 372 to be electrically connected via the connection layer 203.

[0626] A light-shielding layer 317 is preferably provided on the surface of the substrate 352 facing the substrate 351. The light-shielding layer 317 can be provided between adjacent light-emitting devices, on the connecting portion 340, on the circuit 364, and so on. Various optical members can be disposed on the outside of the substrate 352. Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. The outside of the substrate 352 may also be provided with an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, an impact absorbing layer, and so on.

[0627] By providing the protective layer 331 that covers the light emitting device, it is possible to prevent impurities such as water from entering the light emitting device, thereby improving the reliability of the light emitting device.

[0628] The substrate 351 and the substrate 352 can each be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting device is extracted. Using a flexible material for the substrate 351 and the substrate 352 can increase the flexibility of the display device. Alternatively, a polarizing plate may be used for the substrate 351 or the substrate 352.

[0629] Substrate 351 and substrate 352 can each be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. One or both of substrates 351 and 352 may be made of glass having a thickness sufficient to provide flexibility.

[0630] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has small birefringence (or a small amount of birefringence).

[0631] The absolute value of the retardation (phase difference) of a substrate having high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0632] Examples of films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0633] When a film is used as a substrate, the film may absorb water, which may cause changes in shape, such as wrinkles, in the display panel. Therefore, it is preferable to use a film with low water absorption as the substrate. For example, it is preferable to use a film with a water absorption rate of 1% or less, more preferably 0.1% or less, and even more preferably 0.01% or less.

[0634] The adhesive layer 342 may be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. Alternatively, a two-component resin may be used. Alternatively, an adhesive sheet or the like may be used.

[0635] The connection layer 203 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0636] Materials that can be used for conductive layers such as the gate, source, and drain of a transistor, as well as various wirings and electrodes that constitute a display device include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, and alloys containing these metals as main components, etc. Films containing these materials can be used as a single layer or a stacked layer structure.

[0637] Examples of light-transmitting conductive materials include conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide containing gallium, or graphene. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, or alloy materials containing such metal materials, can be used. Alternatively, nitrides of such metal materials (e.g., titanium nitride) can be used. When using metal materials or alloy materials (or their nitrides), it is preferable to thin them sufficiently to ensure light-transmitting properties. A stacked film of the above materials can also be used as the conductive layer. For example, a stacked film of an alloy of silver and magnesium and indium tin oxide is preferable because it can enhance conductivity. These materials can also be used for conductive layers such as various wirings and electrodes constituting display devices, and conductive layers (conductive layers functioning as pixel electrodes or common electrodes) in light-emitting devices.

[0638] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0639] Embodiment 5 In this embodiment, a light-emitting device that can be used for a display device according to one embodiment of the present invention will be described.

[0640] As shown in FIG. 43A , the light-emitting device has an EL layer 786 between a pair of electrodes (a lower electrode 772 and an upper electrode 788). The EL layer 786 can be composed of multiple layers such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can have, for example, a layer containing a substance with high electron-injection properties (electron-injection layer) and a layer containing a substance with high electron-transport properties (electron-transport layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with high hole-injection properties (hole-injection layer) and a layer containing a substance with high hole-transport properties (hole-transport layer).

[0641] A structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 43A is referred to as a single structure in this specification.

[0642] Fig. 43B shows a modified example of the EL layer 786 included in the light-emitting device shown in Fig. 43A. Specifically, the light-emitting device shown in Fig. 43B includes a layer 4431 on a lower electrode 772, a layer 4432 on the layer 4431, a light-emitting layer 4411 on the layer 4432, a layer 4421 on the light-emitting layer 4411, a layer 4422 on the layer 4421, and an upper electrode 788 on the layer 4422. For example, when the lower electrode 772 is an anode and the upper electrode 788 is a cathode, the layer 4431 functions as a hole injection layer, the layer 4432 functions as a hole transport layer, the layer 4421 functions as an electron transport layer, and the layer 4422 functions as an electron injection layer. Alternatively, when the lower electrode 772 is a cathode and the upper electrode 788 is an anode, the layer 4431 functions as an electron injection layer, the layer 4432 functions as an electron transport layer, the layer 4421 functions as a hole transport layer, and the layer 4422 functions as a hole injection layer. With such a layer structure, carriers can be efficiently injected into the light-emitting layer 4411, and the efficiency of carrier recombination in the light-emitting layer 4411 can be increased.

[0643] As shown in Figures 43C and 43D, a configuration in which multiple light-emitting layers (light-emitting layers 4411, 4412, and 4413) are provided between layer 4420 and layer 4430 is also a variation of the single structure.

[0644] As shown in Figures 43E and 43F, a configuration in which a plurality of light-emitting units (EL layer 786a, EL layer 786b) are connected in series via charge generation layer 4440 is referred to as a tandem structure in this specification. The tandem structure may also be referred to as a stack structure. The tandem structure makes it possible to provide a light-emitting device capable of emitting light with high brightness.

[0645] 43C and 43D , light-emitting materials that emit light of the same color, or even the same light-emitting material, may be used for the light-emitting layers 4411, 4412, and 4413. For example, a light-emitting material that emits blue light may be used for the light-emitting layers 4411, 4412, and 4413. A color conversion layer may be provided as the layer 785 shown in FIG.

[0646] The light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413 may each be made of a light-emitting material that emits light of a different color. When the light emitted from the light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413 has a complementary color relationship, white light can be obtained. A color filter (also referred to as a coloring layer) may be provided as the layer 785 shown in Figure 43D. When white light passes through the color filter, light of a desired color can be obtained.

[0647] 43E and 43F , the light-emitting layer 4411 and the light-emitting layer 4412 may be made of light-emitting materials that emit light of the same color, or even the same light-emitting material. Alternatively, the light-emitting layer 4411 and the light-emitting layer 4412 may be made of light-emitting materials that emit light of different colors. When the light emitted by the light-emitting layer 4411 and the light emitted by the light-emitting layer 4412 are complementary colors, white light emission is obtained. FIG. 43F shows an example in which a layer 785 is further provided. As the layer 785, one or both of a color conversion layer and a color filter (coloring layer) can be used.

[0648] 43C, 43D, 43E, and 43F, the layer 4420 and the layer 4430 may have a laminated structure consisting of two or more layers, as shown in FIG. 43B.

[0649] A structure that produces different luminescent colors (for example, blue (B), green (G), and red (R)) for each light-emitting device is sometimes called an SBS (Side By Side) structure.

[0650] The light-emitting device can emit light of red, green, blue, cyan, magenta, yellow, white, or the like, depending on the material of the EL layer 786. Furthermore, the color purity can be further improved by providing the light-emitting device with a microcavity structure.

[0651] A light-emitting device that emits white light preferably has a configuration in which two or more types of light-emitting materials are contained in the light-emitting layer. To obtain white light emission, light-emitting materials can be selected so that the light emitted from each of the two or more light-emitting materials has a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a light-emitting device that emits white light as a whole can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0652] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0653] This embodiment mode can be combined with other embodiment modes as appropriate.

[0654] Embodiment 6 In this embodiment, a metal oxide (also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0655] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0656] The metal oxide can be formed by a sputtering method, a chemical vapor deposition (CVD) method such as a metal organic chemical vapor deposition (MOCVD) method, or an atomic layer deposition (ALD) method.

[0657] <Classification of Crystal Structure> Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0658] The crystalline structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by a GIXD (Grazing-Incident XRD) measurement. The GIXD method is also called the thin film method or the Seemann-Bohlin method.

[0659] For example, in the case of a quartz glass substrate, the shape of the peak in the XRD spectrum is almost symmetrical. On the other hand, in the case of an IGZO film having a crystalline structure, the shape of the peak in the XRD spectrum is asymmetrical. The asymmetrical shape of the peak in the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the shape of the peak in the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0660] The crystalline structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, and it can be confirmed that the quartz glass is in an amorphous state. Furthermore, a spot-like pattern is observed in the diffraction pattern of an IGZO film formed at room temperature, rather than a halo. For this reason, it is estimated that the IGZO film formed at room temperature is neither crystalline nor amorphous, but is in an intermediate state, and it cannot be concluded that it is in an amorphous state.

[0661] <<Structure of Oxide Semiconductor>> Note that oxide semiconductors may be classified differently from the above when focusing on their structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0662] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0663] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0664] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nanometers.

[0665] In an In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain the element M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution transmission electron microscope (TEM) image, for example.

[0666] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the pe...

Claims

1. A first transistor and a second transistor, the first transistor has a first semiconductor layer, a first insulating layer, a second insulating layer, and a first gate electrode stacked in this order; the first gate electrode has a region overlapping the first semiconductor layer; the second transistor has a second semiconductor layer, the second insulating layer, and a second gate electrode stacked in this order; the second gate electrode has a region overlapping with the second semiconductor layer; the first insulating layer has a region in contact with an upper surface of the first semiconductor layer; the first insulating layer has a region in contact with a lower surface of the second semiconductor layer; the first semiconductor layer and the second semiconductor layer each contain indium; The second semiconductor layer has a higher ratio of the number of indium atoms to the number of atoms of a metal element contained therein than that of the first semiconductor layer.

2. In claim 1, The second semiconductor layer has a ratio of the number of indium atoms to the number of atoms of the metal element contained therein of 30 atomic % or more and 100 atomic % or less.

3. In claim 1 or claim 2, the first semiconductor layer and the second semiconductor layer each contain an element M; The element M is one or more selected from gallium, aluminum, yttrium, and tin; The first semiconductor layer has a higher ratio of the number of atoms of the element M to the number of atoms of a metal element contained therein than that of the second semiconductor layer.

4. In claim 3, The first semiconductor layer is a semiconductor device in which the ratio of the number of atoms of the element M to the number of atoms of the metal element contained therein is 20 atomic % or more and 60 atomic % or less.

5. A first transistor and a second transistor, the first transistor has a first semiconductor layer, a first insulating layer, a second insulating layer, and a first gate electrode stacked in this order; the first gate electrode has a region overlapping the first semiconductor layer; the second transistor has a second semiconductor layer, the second insulating layer, and a second gate electrode stacked in this order; the second gate electrode has a region overlapping with the second semiconductor layer; the first insulating layer has a region in contact with an upper surface of the first semiconductor layer; the first insulating layer has a region in contact with a lower surface of the second semiconductor layer; the first semiconductor layer and the second semiconductor layer each contain indium; The first semiconductor layer has a higher ratio of the number of indium atoms to the number of atoms of a metal element contained therein than that of the second semiconductor layer.

6. In claim 5, The semiconductor device according to claim 1, wherein the ratio of the number of indium atoms to the number of atoms of the metal element contained in the first semiconductor layer is equal to or greater than 30 atomic % and equal to or less than 100 atomic %.

7. In claim 5 or 6, the first semiconductor layer and the second semiconductor layer each contain an element M; The element M is one or more selected from gallium, aluminum, yttrium, and tin; The second semiconductor layer has a higher ratio of the number of atoms of the element M to the number of atoms of a metal element contained therein than that of the first semiconductor layer.

8. In claim 7, The second semiconductor layer is a semiconductor device in which the ratio of the number of atoms of the element M to the number of atoms of the metal element contained therein is 20 atomic % or more and 60 atomic % or less.

9. In any one of claims 1 to 8, the first transistor has a third insulating layer and a third gate electrode; the third gate electrode has a region overlapping with the first gate electrode via the first semiconductor layer; The third gate electrode has a region overlapping with the first semiconductor layer via the third insulating layer.

10. In claim 9, the second transistor has the first insulating layer, the third insulating layer, and a fourth gate electrode; the fourth gate electrode has a region overlapping with the second gate electrode via the second semiconductor layer; The fourth gate electrode has a region overlapping with the second semiconductor layer via the first insulating layer and the third insulating layer.