Semiconductor device

Abstract

A semiconductor device of the present invention comprises: a substrate that has a main surface facing one side in the thickness direction; a plurality of semiconductor elements that are positioned at the one side in the thickness direction with respect to the substrate, and have a switching function; in the thickness direction, a first layer that is positioned between the main surface and the plurality of semiconductor elements, and that is electrically conductive; a second layer that conductively joins the main surface and the first layer; and a third layer that conductively joins the first layer and the plurality of semiconductor elements.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, semiconductor devices equipped with semiconductor elements such as MOSFETs and IGBTs have been widely known. In recent years, there has been an increasing demand for semiconductor devices capable of passing large currents. To meet this demand, Patent Document 1 discloses an example of a semiconductor device equipped with multiple semiconductor elements such as MOSFETs. In this semiconductor device, a metal layer made of a thin metal film such as copper foil is disposed on a substrate (insulating layer) made of an electrically insulating material. Multiple semiconductor elements are conductively bonded to the metal layer via a conductive bonding layer such as solder. This semiconductor device can easily accommodate large currents by, for example, increasing the number of semiconductor elements.

[0003] When the semiconductor device disclosed in Patent Document 1 is in use, heat is generated from the multiple semiconductor elements. The thermal conductivity of the substrate (insulating layer) is lower than that of the metal layer on which the multiple semiconductor elements are mounted. Therefore, it takes time for the heat generated by the multiple semiconductor elements to dissipate to the substrate (insulating layer) on the side opposite the metal layer. As a result, the heat generated by the multiple semiconductor elements tends to remain in the metal layer, causing an increase in temperature of the metal layer or the multiple semiconductor elements.

[0004] JP 2018-182330 A

[0005] The present disclosure was conceived in light of the above-mentioned circumstances, and one of its objectives is to provide a semiconductor device that can efficiently dissipate heat generated by multiple semiconductor elements and is suitable for passing large currents.

[0006] The semiconductor device provided by the present disclosure comprises a substrate having a main surface facing one side in a thickness direction, a plurality of semiconductor elements located on one side of the substrate in the thickness direction and having a switching function, a first layer located between the main surface and the plurality of semiconductor elements in the thickness direction and having conductivity, a second layer electrically connecting the main surface and the first layer, and a third layer electrically connecting the first layer and the plurality of semiconductor elements.

[0007] According to the semiconductor device of the present disclosure, it is possible to efficiently dissipate heat generated in a plurality of semiconductor elements.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] 17 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 17 is a plan view of the semiconductor device shown in FIG. 1. FIG. 17 is a perspective view (transparent to the sealing resin and wires) of the semiconductor device shown in FIG. 1. FIG. 17 is a plan view (transparent to the sealing resin) of the semiconductor device shown in FIG. 1. FIG. 17 is a front view of the semiconductor device shown in FIG. 1. FIG. 17 is a right side view of the semiconductor device shown in FIG. 1. FIG. 17 is a left side view of the semiconductor device shown in FIG. 1. FIG. 17 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 17 is an enlarged right side view of FIG. 4. FIG. 17 is an enlarged left side view of FIG. 4. FIG. 17 is a cross-sectional view taken along line XI-XI of FIG. 4. FIG. 17 is a cross-sectional view taken along line XII-XII of FIG. 4. FIG. 17 is a cross-sectional view taken along line XIII-XIII of FIG. 4. FIG. 17 is a cross-sectional view taken along line XIV-XIV of FIG. 4. FIG. 17 is a partial enlarged view (around the first element) of FIG. 9. FIG. 17 is a cross-sectional view taken along line XVI-XVI of FIG. 15. FIG. 17 is a partial enlarged view (around the second element) of FIG. 9. FIG. 17 is a cross-sectional view taken along line XVIII-XVIII of FIG. 17. FIG. 17 is a plan view (transparent to the sealing resin) showing a semiconductor device according to a modified example of the first embodiment. 20 is a cross-sectional view taken along line XXI-XXI of FIG. 20; FIG. 21 is a cross-sectional view taken along line XXIII-XXIII of FIG. 22; FIG. 22 is a plan view (transmitted through the sealing resin) showing a semiconductor device according to a second embodiment of the present disclosure; FIG. 24 is a right-side enlarged view of FIG. 24; FIG. 24 is a cross-sectional view taken along line XXVI-XXVI of FIG. 24;

[0010] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0011] Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not necessarily intended to dictate any ordering of their objects.

[0012] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed from a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B."

[0013] A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 18. The semiconductor device A10 includes a substrate 10, a first layer 20, a second layer 21, a third layer 22, and a plurality of semiconductor elements 30. In this embodiment, the semiconductor device A10 includes a plurality of power supply terminals 23, an output terminal 24, a plurality of gate terminals 25, a plurality of element current detection terminals 26, a plurality of conductive members 40, a case 60, and a sealing resin 70. For ease of understanding, FIG. 3 shows the sealing resin 70 and wires (described below) in a see-through view. FIG. 4 shows the sealing resin 70 in a see-through view.

[0014] The semiconductor device A10 shown in FIG. 1 is a power module. The semiconductor device A10 is used in inverters for various electrical products, hybrid vehicles, and the like. As shown in FIGS. 1 and 2 , the semiconductor device A10 is rectangular (or approximately rectangular) when viewed in the thickness direction z of the substrate 10. Here, for convenience of explanation, a direction perpendicular to the thickness direction z is referred to as a first direction x. A direction perpendicular to both the thickness direction z and the first direction x is referred to as a second direction y. In the illustrated example, the semiconductor device A10 is elongated along the first direction x, but the present disclosure is not limited thereto.

[0015] 11 , the substrate 10 has a first metal layer 11, a second metal layer 12, and an insulating layer 13. The insulating layer 13 is located between the first metal layer 11 and the second metal layer 12 in the thickness direction z. The insulating layer 13 has electrical insulation properties. Examples of materials that can be used for the insulating layer 13 include ceramic epoxy.

[0016] The first metal layer 11 is laminated on the insulating layer 13. The first metal layer 11 includes a main surface 11A. The main surface 11A faces one side in the thickness direction z (the upper side in FIG. 11 ). The first metal layer 11 is made of a conductive metal material, and is configured, for example, by a metal foil made of copper (Cu) or a copper alloy.

[0017] The second metal layer 12 is located on the opposite side of the insulating layer 13 from the first metal layer 11 (the other side in the thickness direction z), and the insulating layer 13 is laminated on this second metal layer 12. The second metal layer 12 is made of the same conductive metal material as the first metal layer 11, and is configured by a metal plate made of, for example, copper or a copper alloy.

[0018] For example, the thickness of the first metal layer 11, the second metal layer 12, and the insulating layer 13 is 0.1 mm to 2.0 mm for the first metal layer 11, 0.3 mm to 2.0 mm for the second metal layer 12, and 0.12 mm to 0.18 mm for the insulating layer 13. The substrate 10 of this embodiment may be, for example, an insulated metal substrate. The substrate 10 is formed by laminating the insulating layer 13 and the first metal layer 11 on a metal plate (the second metal layer 12). Alternatively, the substrate 10 may be, for example, a direct bonded copper (DBC) substrate. The DBC substrate is formed by a ceramic plate (the insulating layer 13) and a pair of copper foils (the first metal layer 11 and the second metal layer 12) laminated on the ceramic plate on both sides in the thickness direction z.

[0019] In this embodiment, the first metal layer 11 includes a first element mounting portion 111, a second element mounting portion 112, a first conductive portion 113, a first gate portion 114, a first detection portion 115, a pair of thermistor mounting portions 116, a second gate portion 117, and a second detection portion 118. Each portion of the first metal layer 11 is formed, for example, by partially removing copper foil laminated on the insulating layer 13 using a wet etching technique. Note that the surface of each portion of the first metal layer 11 may be plated with silver (Ag).

[0020] As shown in FIGS. 4 and 9 to 12, a plurality of semiconductor elements 30 are mounted on the first element mounting portion 111. For ease of explanation, the plurality of semiconductor elements 30 mounted on the first element mounting portion 111 will be referred to as "a plurality of first elements 31." As shown in FIG. 4 and other figures, the first element mounting portion 111 is located on one end side of the substrate 10 in the second direction y (the upper side in FIG. 4). The first element mounting portion 111 has a strip shape extending in the first direction x. In the semiconductor device A10, ten first elements 31 (semiconductor elements 30) are mounted on the first element mounting portion 111, but the number of first elements 31 is not limited to this. A strip-shaped first power supply pad 111a extending in the second direction y is formed at one end (the right side in FIG. 4) of the first element mounting portion 111 in the first direction x.

[0021] As shown in FIGS. 4 , 9 , 10 , and 12 , a plurality of semiconductor elements 30 are mounted on the second element mounting portion 112. For ease of explanation, the plurality of semiconductor elements 30 mounted on the second element mounting portion 112 are referred to as “a plurality of second elements 32.” As shown in FIG. 4 and other figures, the second element mounting portion 112 is located between the first element mounting portion 111 and the first conductive portion 113 in the second direction y. The second element mounting portion 112 has a strip shape extending in the first direction x. In the semiconductor device A10, ten second elements 32 (semiconductor elements 30) are mounted on the second element mounting portion 112, but the number of second elements 32 is not limited to this. A strip-shaped output pad 112a extending in the second direction y is formed at one end (the left side in FIG. 4 ) of the second element mounting portion 112 in the first direction x. A part of the output pad 112a located on one side of the second element mounting portion 112 in the second direction y (upper side in FIG. 4) is located adjacent to the first element mounting portion 111 in the first direction x. A part of the output pad 112a located on the other side of the second element mounting portion 112 in the second direction y (lower side in FIG. 4) is located adjacent to the first conductive portion 113 in the first direction x.

[0022] As shown in FIGS. 4 , 9 , and 10 , the first conductive portion 113 is electrically connected to both the plurality of first elements 31 and the plurality of second elements 32. The first conductive portion 113 is located on the opposite side of the second element mounting portion 112 from the first element mounting portion 111 in the second direction y. The first conductive portion 113 has a strip shape extending in the first direction x. A strip-shaped second power supply pad 113a extending in the second direction y is formed at one end (the right side in FIG. 4 ) of the first conductive portion 113 in the first direction x. As shown in FIG. 4 , the first conductive portion 113 has a notch 113b extending in the first direction x. The notch 113b is located at the center of the first conductive portion 113 in the second direction y and extends from one end (the right end in FIG. 4 ) in the first direction x to the center in the first direction x.

[0023] As shown in FIGS. 4 , 9 , and 10 , the first gate portion 114 is electrically connected to a plurality of first elements 31. The first gate portion 114 has a strip shape extending in the first direction x. The first gate portion 114 is located between the first element mounting portion 111 and the case 60 in the second direction y. In the semiconductor device A10, the first gate portion 114 is folded back at one end in the first direction x (the right end in FIG. 4 ) and formed in two rows in the second direction y. The width of the first gate portion 114 (the dimension in the second direction y) is smaller than the widths of the first element mounting portion 111, the second element mounting portion 112, and the first conductive portion 113.

[0024] As shown in FIGS. 4, 9, and 10, the first detection portion 115 is electrically connected to a plurality of first elements 31. The first detection portion 115 has a strip shape extending in the first direction x. The first detection portion 115 is located between the first element mounting portion 111 and the case 60 in the second direction y. In the semiconductor device A10, the first detection portion 115 is folded back at one end in the first direction x (the left end in FIG. 4) and is formed in two rows in the second direction y. The width of the first detection portion 115 (the dimension in the second direction y) is the same as the width of the first gate portion 114.

[0025] 4 and 9 , the pair of thermistor mounting portions 116 are spaced apart from each other in the second direction y and mount the thermistor 33. The pair of thermistor mounting portions 116 are located near the corners of the substrate 10. The first element mounting portion 111, the first gate portion 114, and the first detection portion 115 are located around the pair of thermistor mounting portions 116.

[0026] As shown in FIGS. 4 , 9 , and 10 , the second gate portion 117 is electrically connected to a plurality of second elements 32. The second gate portion 117 has a strip shape extending in the first direction x. The second gate portion 117 is located between the first conductive portion 113 and the case 60 in the second direction y. In the semiconductor device A10, the second gate portion 117 is folded back at one end in the first direction x (the left end in FIG. 4 ) and formed in two rows in the second direction y. The width of the second gate portion 117 (the dimension in the second direction y) is smaller than the widths of the first element mounting portion 111, the second element mounting portion 112, and the first conductive portion 113.

[0027] As shown in FIGS. 4 , 9 , and 10 , the second detection portions 118 are electrically connected to a plurality of second elements 32. The second detection portions 118 are strip-shaped and extend in the first direction x. The second detection portions 118 are located between the first conductive portion 113 and the case 60 in the second direction y. In the semiconductor device A10, the second detection portions 118 are folded back at one end in the first direction x (the right end in FIG. 4 ) and are formed in two rows in the second direction y. The width of the second detection portions 118 (the dimension in the second direction y) is the same as the width of the second gate portions 117.

[0028] As shown in Figures 2 to 4, the multiple power supply terminals 23 are part of the external connection terminals provided on the semiconductor device A10. The multiple power supply terminals 23 are connected to a DC power supply arranged outside the semiconductor device A10. The multiple power supply terminals 23 are supported by the case 60. The multiple power supply terminals 23 are made of a metal plate. The metal plate is made of copper, for example. The multiple power supply terminals 23 have a thickness of about 1.0 mm, for example.

[0029] The multiple power supply terminals 23 include a first power supply terminal 23a and a second power supply terminal 23b. The first power supply terminal 23a is a positive electrode (P terminal). The first power supply terminal 23a is connected to a first power supply pad 111a of the first element mounting portion 111. The second power supply terminal 23b is a negative electrode (N terminal). The second power supply terminal 23b is connected to a second power supply pad 113a of the first conductive portion 113. The first power supply terminal 23a and the second power supply terminal 23b are spaced apart from each other in the second direction y.

[0030] As shown in FIGS. 9 and 13, each of the first power supply terminal 23 a and the second power supply terminal 23 b has an external connection portion 231 , an internal connection portion 232 , and an intermediate portion 233 .

[0031] The external connection portion 231 is exposed from the semiconductor device A10 and has a flat plate shape perpendicular to the thickness direction z. A DC power cable or the like is connected to the external connection portion 231. The external connection portion 231 is supported by the case 60. The external connection portion 231 is provided with a connection hole 231a that penetrates in the thickness direction z. A fastening member such as a bolt is inserted into the connection hole 231a. The surface of the external connection portion 231 may be nickel (Ni) plated.

[0032] The internal connection portion 232 has a comb-like shape, with the first power supply terminal 23a connected to the first power supply pad 111a of the first element mounting portion 111 and the second power supply terminal 23b connected to the second power supply pad 113a of the first conductive portion 113. In the semiconductor device A10, the internal connection portion 232 has three teeth, which are arranged along the second direction y. The teeth are bent in the thickness direction z. Therefore, the teeth are hook-shaped when viewed in the second direction y. All of the teeth are connected to the first power supply pad 111a and the second power supply pad 113a by ultrasonic bonding.

[0033] The intermediate portion 233 interconnects the external connection portion 231 and the internal connection portion 232. The cross section of the intermediate portion 233 in the first direction x is L-shaped. The intermediate portion 233 has a base portion 233a and an upright portion 233b. The base portion 233a extends along the first direction x and the second direction y. One end of the base portion 233a in the first direction x is connected to the internal connection portion 232. The upright portion 233b stands up from the base portion 233a in the thickness direction z. One end of the upright portion 233b in the thickness direction z is connected to the external connection portion 231.

[0034] As shown in Figures 2 to 4, the output terminal 24 is part of the external connection terminals provided on the semiconductor device A10. The output terminal 24 is connected to a power supply target (such as a motor) located outside the semiconductor device A10. The output terminal 24 is supported by the case 60 and is located on the opposite side of the substrate 10 from the multiple power supply terminals 23 in the first direction x. The output terminal 24 is made of a metal plate. The metal plate is made of copper, for example. The thickness of the output terminal 24 is 1.0 mm.

[0035] In the semiconductor device A10, the output terminal 24 is separated into two parts, a first terminal part 24a and a second terminal part 24b. Note that the output terminal 24 may be a single member that is not separated as in the semiconductor device A10. The first terminal part 24a and the second terminal part 24b are connected in parallel to the output pad 112a of the second element mounting part 112. Therefore, the output terminal 24 is connected to the second element mounting part 112. The first terminal part 24a and the second terminal part 24b are spaced apart from each other in the second direction y.

[0036] As shown in FIGS. 10 and 14, each of the first terminal portion 24 a and the second terminal portion 24 b has an external connection portion 241 , an internal connection portion 242 , and an intermediate portion 243 .

[0037] The external connection portion 241 is exposed from the semiconductor device A10 and has a flat plate shape perpendicular to the thickness direction z. A cable or the like that is electrically connected to a power supply target is connected to the external connection portion 241. The external connection portion 241 is supported by the case 60. A connection hole 241a that penetrates the external connection portion 241 in the thickness direction z is provided. A fastening member such as a bolt is inserted into the connection hole 241a. The surface of the external connection portion 241 may be nickel plated.

[0038] The internal connection portion 242 has a comb-like shape that is connected to the output pad 112a of the second element mounting portion 112. In the semiconductor device A10, the internal connection portion 242 has three teeth, and these multiple teeth are arranged along the second direction y. The multiple teeth are bent in the thickness direction z. Therefore, the multiple teeth are hook-shaped when viewed in the second direction y. All of the multiple teeth are connected to the output pad 112a by ultrasonic bonding.

[0039] The intermediate portion 243 interconnects the external connection portion 241 and the internal connection portion 242. The cross section of the intermediate portion 243 in the first direction x is L-shaped. The intermediate portion 243 has a base portion 243a and an upright portion 243b. The base portion 243a extends along the first direction x and the second direction y. One end of the base portion 243a in the first direction x is connected to the internal connection portion 242. The upright portion 243b stands up from the base portion 243a in the thickness direction z. One end of the upright portion 243b in the thickness direction z is connected to the external connection portion 241.

[0040] As shown in FIGS. 2 to 5 , the gate terminals 25 are part of external connection terminals provided on the semiconductor device A10. The gate terminals 25 are electrically connected to either the first gate portion 114 or the second gate portion 117. The gate terminals 25 are connected to an external drive circuit (e.g., a gate driver) for the semiconductor device A10. The gate terminals 25 are supported by a case 60. The gate terminals 25 are made of metal rods. The metal rods may be made of copper, for example. The surfaces of the gate terminals 25 may be plated with tin (Sn) or nickel and tin. As shown in FIG. 12 , the gate terminals 25 have an L-shaped cross section in the first direction x. A portion of each of the gate terminals 25 protrudes from the case 60 in the thickness direction z toward the main surface 11A of the first metal layer 11 (substrate 10).

[0041] The multiple gate terminals 25 include a first gate terminal 25a and a second gate terminal 25b. As shown in Fig. 10 , the first gate terminal 25a is adjacent to the first gate portion 114 in the second direction y. As shown in Fig. 9 , the second gate terminal 25b is located on the opposite side of the first metal layer 11 (substrate 10) from the first gate terminal 25a in the second direction y. The second gate terminal 25b is adjacent to the second gate portion 117.

[0042] As shown in FIGS. 2 to 5 , the device current detection terminals 26 are part of external connection terminals provided on the semiconductor device A10. The device current detection terminals 26 are electrically connected to either the first detection unit 115 or the second detection unit 118. The device current detection terminals 26 are connected to an externally disposed control circuit of the semiconductor device A10. The device current detection terminals 26 are supported by a case 60. The device current detection terminals 26 are made of metal rods. The metal rods may be made of copper, for example. The surfaces of the device current detection terminals 26 may be tin-plated or nickel-plated and tin-plated. As shown in FIG. 12 , the device current detection terminals 26 have an L-shaped cross section in the first direction x. A portion of each of the device current detection terminals 26 protrudes from the case 60 in the thickness direction z toward the main surface 11A of the first metal layer 11 (substrate 10).

[0043] The multiple device current detection terminals 26 include a first detection terminal 26 a and a second detection terminal 26 b. The first detection terminal 26 a is located adjacent to the first gate terminal 25 a in the first direction x, as shown in Fig. 10 . The second detection terminal 26 b is located adjacent to the second gate terminal 25 b in the first direction x, as shown in Fig. 9 .

[0044] As shown in FIGS. 2 to 5 and 10 , the semiconductor device A10 includes a power supply current detection terminal 27. The power supply current detection terminal 27 is part of an external connection terminal provided on the semiconductor device A10. The power supply current detection terminal 27 is connected to an externally disposed control circuit for the semiconductor device A10. The power supply current detection terminal 27 is supported by a case 60. The power supply current detection terminal 27 is made of a metal rod. The metal rod may be made of copper, for example. The surface of the power supply current detection terminal 27 may be tin-plated or nickel-plated and tin-plated. The shape of the power supply current detection terminal 27 is the same as that of the multiple gate terminals 25 shown in FIG. 12 . Like the gate terminals 25 shown in FIG. 12 , a portion of the power supply current detection terminal 27 protrudes from the case 60 in the thickness direction z toward the main surface 11A of the first metal layer 11 (substrate 10). In the second direction y, the position of the power supply current detection terminal 27 is the same as that of the first gate terminal 25a. The power supply current detection terminal 27 is spaced from the first gate terminal 25a toward the first terminal portion 24a (output terminal 24) in the first direction x.

[0045] 10 , the semiconductor device A10 includes a power supply current detection wire 45. The power supply current detection wire 45 is a conductive member connected to the power supply current detection terminal 27 and the first element mounting portion 111. This allows the power supply current detection terminal 27 to be electrically connected to the first element mounting portion 111. The power supply current detection wire 45 is made of, for example, aluminum.

[0046] As shown in FIGS. 2 to 5 and 9 , the semiconductor device A10 includes a pair of thermistor terminals 28. The pair of thermistor terminals 28 are part of external connection terminals provided on the semiconductor device A10. The pair of thermistor terminals 28 are connected to an externally disposed control circuit for the semiconductor device A10. The pair of thermistor terminals 28 are supported by a case 60. The pair of thermistor terminals 28 are formed from metal rods. The metal rods may be made of copper, for example. Note that the surfaces of the pair of thermistor terminals 28 may be tin-plated or nickel-plated and tin-plated. The shape of the pair of thermistor terminals 28 is the same as that of the multiple gate terminals 25 shown in FIG. 12 . Like the gate terminals 25 shown in FIG. 12 , a portion of the pair of thermistor terminals 28 protrudes from the case 60 in the thickness direction z toward the main surface 11A of the first metal layer 11 (substrate 10). In the second direction y, the position of the pair of thermistor terminals 28 is the same as that of the first gate terminals 25a. The pair of thermistor terminals 28 are spaced apart in the first direction x from the first gate terminal 25a toward the first power supply terminal 23a. The pair of thermistor terminals 28 are spaced apart from each other in the first direction x.

[0047] 9, the semiconductor device A10 includes a pair of thermistor wires 46. The pair of thermistor wires 46 are conductive members individually connected to the pair of thermistor terminals 28 and the pair of thermistor mounting portions 116. As a result, the pair of thermistor terminals 28 are electrically connected to the pair of thermistor mounting portions 116. The pair of thermistor wires 46 is made of a material such as aluminum.

[0048] Each of the multiple semiconductor elements 30 (the multiple first elements 31 and the multiple second elements 32) has a semiconductor layer containing, for example, silicon carbide (SiC) and has a switching function. The multiple semiconductor elements 30 are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) configured using a semiconductor material primarily containing silicon carbide. Note that the semiconductor elements 30 are not limited to MOSFETs and may also be IGBTs (Insulated Gate Bipolar Transistors). In the semiconductor device A10, a case in which the multiple semiconductor elements 30 are MOSFETs will be described. As shown in FIGS. 15 and 17 , the semiconductor elements 30 are rectangular (square in the semiconductor device A10) when viewed in the thickness direction z. In the semiconductor device A10, the thickness of the semiconductor elements 30 is, for example, 400 μm or less, more preferably 150 μm or less.

[0049] 15 to 18, each of the multiple semiconductor elements 30 has a source electrode 301, a drain electrode 302, and a gate electrode 303. The source electrode 301 is provided at the upper end of the semiconductor element 30, which is located on the side facing the main surface 11A of the first metal layer 11 (substrate 10) in the thickness direction z. A source current flows through the source electrode 301 from inside the semiconductor element 30.

[0050] The drain electrode 302 is provided at the lower end of the semiconductor element 30 located on the opposite side in the thickness direction z to the side to which the main surface 11A of the first metal layer 11 (substrate 10) faces. A drain current flows through the drain electrode 302 toward the inside of the semiconductor element 30.

[0051] The gate electrode 303 is provided at the upper end of the semiconductor element 30 located on the side facing the main surface 11A of the first metal layer 11 (substrate 10) in the thickness direction z. A gate voltage for driving the semiconductor element 30 is applied to the gate electrode 303. When viewed in the thickness direction z, the area of ​​the gate electrode 303 is smaller than the area of ​​the source electrode 301.

[0052] The multiple semiconductor elements 30 include multiple first elements 31 and multiple second elements 32. The multiple first elements 31 are mounted on the first element mounting portion 111, respectively. The multiple first elements 31 are arranged at predetermined intervals in the first direction x. The multiple second elements 32 are mounted on the second element mounting portion 112, respectively. The multiple second elements 32 are arranged at predetermined intervals in the first direction x.

[0053] As shown in FIGS. 11 , 12 , and 15 to 18 , the first layer 20 is located between the main surface 11A of the first metal layer 11 (the first element mounting portion 111 and the second element mounting portion 112) and the plurality of semiconductor elements 30 in the thickness direction z. The first layer 20 is made of a conductive metal material. The first layer 20 is made of a material having the same thermal conductivity as the second metal layer 12 or a material having a thermal conductivity higher than that of the second metal layer 12. The first layer 20 is made of, for example, copper or a copper alloy. When the first layer 20 is made of copper, the thermal conductivity of the first layer 20 is 398 W / mK. In addition to copper and copper alloys, examples of materials that can be used to make the first layer 20 include aluminum, iron, and carbon. The thickness of the first layer 20 is greater than the thickness of the second metal layer 12. Preferably, the thickness of the first layer 20 is 1 to 10 times the thickness of the second metal layer 12. The thickness of the first layer 20 is, for example, 1 mm to 4 mm, and more preferably 2 mm to 3 mm.

[0054] In the semiconductor device A10, the first layer 20 includes a plurality of individual units 201 that are separated from one another. In the semiconductor device A10, the plurality of individual units 201 are arranged to correspond individually to the plurality of semiconductor elements 30. Each of the plurality of semiconductor elements 30 is supported by one of the plurality of individual units 201. In the semiconductor device A10, the plurality of individual units 201 corresponding to the plurality of first elements 31 are supported by the first element mounting portion 111 and are arranged at intervals in the first direction x. The plurality of individual units 201 corresponding to the plurality of second elements 32 are supported by the second element mounting portion 112 and are arranged at intervals in the first direction x. Each individual unit 201 is larger than the semiconductor element 30 when viewed in the thickness direction z. The individual units 201 are rectangular (square in the semiconductor device A10) when viewed in the thickness direction z.

[0055] The second layer 21 is located between the first metal layer 11 (the first element mounting portion 111 and the second element mounting portion 112) and the first layer 20 (the plurality of individual portions 201) in the thickness direction z. The second layer 21 is electrically conductive and electrically connects the main surfaces 11A of the first element mounting portion 111 and the second element mounting portion 112 to the plurality of individual portions 201. The constituent material of the second layer 21 is, for example, lead-free solder containing tin as its main component. The thickness of the second layer 21 is, for example, 0.02 mm to 0.20 mm.

[0056] In the semiconductor device A10, the second layer 21 has a plurality of regions that are separated from one another. The plurality of regions of the second layer 21 correspond individually to the plurality of individual units 201. The second layer 21 may also have a region that is common to some of the plurality of individual units 201. For example, the second layer 21 may have a region that is common to the plurality of individual units 201 supported by the first element mounting portion 111 and a region that is common to the plurality of individual units 201 supported by the second element mounting portion 112.

[0057] The third layer 22 is located between the first layer 20 (the plurality of individual portions 201) and the plurality of semiconductor elements 30 in the thickness direction z. The third layer 22 is conductive and electrically connects the plurality of individual portions 201 and the plurality of semiconductor elements 30. More specifically, the drain electrode 302 of each semiconductor element 30 is electrically connected to the first layer 20 (the individual portion 201) by the third layer 22. The third layer 22 is made of a bonding material containing a metal material. In the semiconductor device A10, the material constituting the third layer 22 contains silver. In the semiconductor device A10, the third layer 22 is sintered silver. The third layer 22 may be made of a sintered metal containing a metal other than silver (e.g., sintered copper), solid-phase diffusion-bonded aluminum, solder, or a metal paste material. The thickness of the third layer 22 is, for example, 0.02 mm to 0.20 mm.

[0058] As shown in Figures 12, 15 to 18, etc., the multiple conductive members 40 are bonded to the source electrodes 301 of the multiple semiconductor elements 30 and either the second element mounting portion 112 or the first conductive portion 113. The multiple conductive members 40 are made of metal plate material. The metal is copper or a copper alloy. The multiple conductive members 40 are metal plate material that has been bent.

[0059] The multiple conductive members 40 include multiple first conductive members 41 and multiple second conductive members 42. Each of the multiple first conductive members 41 is bonded to the source electrode 301 of one of the multiple first elements 31 and to the second element mounting portion 112. The first conductive member 41 and the second element mounting portion 112 are bonded via a conductive member bonding layer 48. The first conductive member 41 and the source electrode 301 of each first element 31 are bonded via a conductive member bonding layer 49. The conductive member bonding layer 48 and the conductive member bonding layer 49 bonded to the first conductive member 41 are made of, for example, solder, a metal paste material, or a sintered metal.

[0060] Each of the multiple second conductive members 42 is bonded to the source electrode 301 of one of the multiple second elements 32 and to the first conductive portion 113. The second conductive member 42 and the first conductive portion 113 are bonded via a conductive member bonding layer 48. The second conductive member 42 and the source electrode 301 of each second element 32 are bonded via a conductive member bonding layer 49. The conductive member bonding layer 48 and the conductive member bonding layer 49 bonded to the second conductive member 42 are made of, for example, solder, a metal paste material, or a sintered metal.

[0061] As shown in FIGS. 4 and 9 , the semiconductor device A10 includes a thermistor 33. The thermistor 33 is electrically connected to a pair of thermistor mounting portions 116. In the semiconductor device A10, the thermistor 33 is an NTC (Negative Temperature Coefficient) thermistor. NTC thermistors have the characteristic of gradually decreasing resistance with increasing temperature. The thermistor 33 is used as a temperature detection sensor for the semiconductor device A10. The thermistor 33 is electrically connected to a pair of thermistor terminals 28 via the pair of thermistor mounting portions 116 and a pair of thermistor wires 46.

[0062] 9 , 10 , 15 , and 17 , the semiconductor device A10 includes a plurality of first gate wires 431, a plurality of second gate wires 432, a third gate wire 433, and a fourth gate wire 434. Each of the plurality of first gate wires 431 is a conductive member having one end connected to the gate electrode 303 of one of the plurality of first elements 31 and the other end connected to the first gate portion 114. Each of the plurality of second gate wires 432 is a conductive member having one end connected to the gate electrode 303 of one of the plurality of second elements 32 and the other end connected to the second gate portion 117. The plurality of first gate wires 431 and the plurality of second gate wires 432 are made of a material such as aluminum.

[0063] The third gate wire 433 is a conductive member connected to the first gate terminal 25a and the first gate portion 114. As a result, the first gate terminal 25a is electrically connected to the gate electrodes 303 of the multiple first elements 31 mounted on the first element mounting portion 111. The fourth gate wire 434 is a conductive member connected to the second gate terminal 25b and the second gate portion 117. As a result, the second gate terminal 25b is electrically connected to the gate electrodes 303 of the multiple second elements 32 mounted on the second element mounting portion 112. The constituent material of the third gate wire 433 and the fourth gate wire 434 is, for example, aluminum.

[0064] 9 , 10 , 15 , and 17 , the semiconductor device A10 includes a plurality of first detection wires 441, a plurality of second detection wires 442, a third detection wire 443, and a fourth detection wire 444. Each of the plurality of first detection wires 441 is a conductive member having one end connected to the source electrode 301 of one of the plurality of first elements 31 and the other end connected to the first detection unit 115. Each of the plurality of second detection wires 442 is a conductive member having one end connected to the source electrode 301 of one of the plurality of second elements 32 and the other end connected to the second detection unit 118. The plurality of first detection wires 441 and the plurality of second detection wires 442 are made of a material such as aluminum.

[0065] The third detection wire 443 is a conductive member connected to the first detection terminal 26a and the first detection unit 115. As a result, the first detection terminal 26a is electrically connected to the source electrodes 301 of the multiple first elements 31 mounted on the first element mounting unit 111. The fourth detection wire 444 is a conductive member connected to the second detection terminal 26b and the second detection unit 118. As a result, the second detection terminal 26b is electrically connected to the source electrodes 301 of the multiple second elements 32 mounted on the second element mounting unit 112. The third detection wire 443 and the fourth detection wire 444 are made of a material such as aluminum.

[0066] 3 to 7, the case 60 is an electrically insulating member that surrounds the first metal layer 11 (substrate 10) when viewed in the thickness direction z. The case 60 is made of a synthetic resin with excellent heat resistance, such as PPS (polyphenylene sulfide). The case 60 has a pair of first side walls 611, a pair of second side walls 612, multiple mounting portions 62, a power terminal block 63, and an output terminal block 64.

[0067] 2 and 4, the pair of first side walls 611 are spaced apart from each other in the first direction x. The pair of first side walls 611 are arranged along both the second direction y and the thickness direction z.

[0068] As shown in FIGS. 2 and 4 , the pair of second side walls 612 are spaced apart from each other in the second direction y. The pair of second side walls 612 are arranged along both the first direction x and the thickness direction z. Both ends of the pair of second side walls 612 in the first direction x are connected to the pair of first side walls 611. The first gate terminal 25 a, the first detection terminal 26 a, the power supply current detection terminal 27, and a pair of thermistor terminals 28 are arranged inside one of the second side walls 612. The second gate terminal 25 b and the second detection terminal 26 b are arranged inside the other second side wall 612. As shown in FIGS. 9 , 10 , and 12 , the ends of these terminals that are closest to the first metal layer 11 (substrate 10) in the thickness direction z are supported by the pair of second side walls 612.

[0069] 2 , 9 , and 10 , the multiple mounting portions 62 are portions provided at the four corners of the case 60 when viewed in the thickness direction z. Each of the multiple mounting portions 62 has a through hole formed therethrough in the thickness direction z, and a mounting member 621 is fitted into each of the through holes. Each mounting member 621 has a mounting hole 621 a formed therethrough in the thickness direction z. In the semiconductor device A10, a heat dissipation member (e.g., a heat sink) (not shown) can be attached by, for example, fitting a fastening member (not shown) into the mounting hole 621 a.

[0070] As shown in FIGS. 2 , 6 , and 9 , the power terminal block 63 protrudes outward in the first direction x from one of the first side walls 611. A plurality of power terminals 23 are supported on the power terminal block 63. The power terminal block 63 includes a first terminal block 631 and a second terminal block 632. The first terminal block 631 and the second terminal block 632 are spaced apart from each other in the second direction y. The first terminal block 631 supports the first power terminal 23 a. The external connection portion 231 of the first power terminal 23 a is exposed from the first terminal block 631. The second terminal block 632 supports the second power terminal 23 b. The external connection portion 231 of the second power terminal 23 b is exposed from the second terminal block 632. A plurality of grooves 633 extending in the first direction x are formed between the first terminal block 631 and the second terminal block 632. As shown in FIGS. 9 and 13 , a pair of nuts 634 and a pair of intermediate members 635 are disposed inside the first terminal block 631 and the second terminal block 632. The intermediate members 635 are located on the other side of the nuts 634 in the thickness direction z (the lower side in FIG. 13 ) and abut against the nuts 634. One of the nuts 634 and the intermediate member 635 is engaged with the external connection portion 231 and the intermediate portion 233 of the first power terminal 23a. The other of the nuts 634 and the intermediate member 635 is engaged with the external connection portion 231 and the intermediate portion 233 of the second power terminal 23b. A portion of each of the pair of intermediate members 635 is exposed from the power terminal block 63. The pair of nuts 634 correspond to a pair of connection holes 231a provided in the first power terminal 23a and the second power terminal 23b. Fastening members such as bolts inserted into the pair of connection holes 231a fit into the pair of nuts 634.

[0071] As shown in FIGS. 2 , 7 , and 10 , the output terminal block 64 protrudes outward in the first direction x from the other first side wall 611. The output terminal 24 is supported on the output terminal block 64. The output terminal block 64 has a first terminal block 641 and a second terminal block 642. The first terminal block 641 and the second terminal block 642 are spaced apart from each other in the second direction y. The first terminal block 641 supports the first terminal portion 24 a of the output terminal 24. The external connection portion 241 of the first terminal portion 24 a is exposed from the first terminal block 641. The second terminal block 642 supports the second terminal portion 24 b of the output terminal 24. The external connection portion 241 of the second terminal portion 24 b is exposed from the second terminal block 642. A plurality of grooves 643 extending in the first direction x are formed between the first terminal block 641 and the second terminal block 642. As shown in FIGS. 10 and 14 , a pair of nuts 644 and a pair of intermediate members 645 are disposed inside the first terminal block 641 and the second terminal block 642. The intermediate members 645 are located on the other side of the nuts 644 in the thickness direction z (the lower side in FIG. 14 ) and abut against the nuts 644. One of the nuts 644 and the intermediate member 645 is engaged with the external connection portion 241 and the intermediate portion 243 of the first terminal 24 a. The other of the nuts 644 and the intermediate member 645 is engaged with the external connection portion 241 and the intermediate portion 243 of the second terminal 24 b. A portion of each of the pair of intermediate members 645 is exposed from the output terminal block 64. The pair of nuts 644 correspond to a pair of connection holes 241 a provided in the first terminal block 24 a and the second terminal block 24 b. Fastening members such as bolts inserted into the pair of connection holes 241 a are fitted into the pair of nuts 644.

[0072] 11 and 12 , the sealing resin 70 is contained in an area surrounded by the case 60 and the substrate 10. The sealing resin 70 covers the semiconductor elements 30. The sealing resin 70 is made of, for example, a black epoxy resin. However, other materials such as silicone gel may also be selected as the sealing resin 70.

[0073] The semiconductor device A10 includes two switching circuits: an upper arm circuit and a lower arm circuit. The upper arm circuit includes a first element mounting portion 111 and a plurality of first elements 31 mounted on the first element mounting portion 111. The plurality of first elements 31 mounted on the first element mounting portion 111 are all connected in parallel between the first power supply terminal 23a and the output terminal 24. The gate electrodes 303 of the plurality of first elements 31 in the upper arm circuit are all connected in parallel to the first gate terminal 25a. A gate voltage is applied to the first gate terminal 25a by a drive circuit, such as a gate driver, external to the semiconductor device A10, thereby simultaneously driving the plurality of first elements 31 in the upper arm circuit. The source electrodes 301 of the plurality of first elements 31 in the upper arm circuit are all connected in parallel to the first detection terminal 26a. The source current flowing through the plurality of first elements 31 in the upper arm circuit is input to a control circuit of the semiconductor device A10, which is external to the semiconductor device A10, via the first detection terminal 26a.

[0074] The lower arm circuit is composed of a second element mounting portion 112 and a plurality of second elements 32 mounted on the second element mounting portion 112. The plurality of second elements 32 mounted on the second element mounting portion 112 are all connected in parallel between the output terminal 24 and the second power supply terminal 23b. The gate electrodes 303 of the plurality of second elements 32 in the lower arm circuit are all connected in parallel to the second gate terminal 25b. A gate voltage is applied to the second gate terminal 25b by a drive circuit such as a gate driver arranged outside the semiconductor device A10, thereby simultaneously driving the plurality of second elements 32 in the lower arm circuit. The source electrodes 301 of the plurality of second elements 32 in the lower arm circuit are all connected in parallel to the second detection terminal 26b. The source current flowing through the plurality of second elements 32 in the lower arm circuit is input to a control circuit of the semiconductor device A10 arranged outside the semiconductor device A10 via the second detection terminal 26b.

[0075] A DC power supply is connected to the first power supply terminal 23 a and the second power supply terminal 23 b, and the plurality of semiconductor elements 30 (the plurality of first elements 31 and the plurality of second elements 32) in the upper arm circuit and the lower arm circuit are driven, thereby outputting AC voltages of various frequencies from the output terminal 24. The AC voltages output from the output terminal 24 are supplied to a power supply target such as a motor.

[0076] Next, the effects of the semiconductor device A10 will be described.

[0077] The semiconductor device A10 includes a first layer 20, a second layer 21, and a third layer 22. The first layer 20 is located between the main surface 11A of the first metal layer 11 (the first element mounting portion 111 and the second element mounting portion 112) and the plurality of semiconductor elements 30 and has electrical conductivity. The second layer 21 electrically connects the main surface 11A of the first metal layer 11 (the first element mounting portion 111 and the second element mounting portion 112) to the plurality of semiconductor elements 30. The third layer 22 electrically connects the first layer 20 to the plurality of semiconductor elements 30. The configuration including the first layer 20 can increase the heat capacity of the region between the semiconductor elements 30 and the substrate 10, preventing the region from reaching thermal saturation. This allows heat generated in each of the plurality of semiconductor elements 30 to be diffused by the first layer 20 and quickly dissipated to the first metal layer 11 (the substrate 10). Therefore, the semiconductor device A10 can efficiently dissipate heat generated in the plurality of semiconductor elements 30. As a result, the semiconductor device A10 can suppress a rise in temperature around the plurality of semiconductor elements 30, and is suitable for cases where a large current flows through the semiconductor device A10.

[0078] The substrate 10 on which the multiple semiconductor elements 30 are mounted includes a first metal layer 11, a second metal layer 12, and an insulating layer 13. The first metal layer 11 includes a main surface 11A facing one side in the thickness direction z. The second metal layer 12 is located on the other side of the first metal layer 11 in the thickness direction z. The insulating layer 13 is interposed between the first metal layer 11 and the second metal layer 12. The substrate 10 is configured by stacking the second metal layer 12, the insulating layer 13, and the first metal layer 11 in this order. The first metal layer 11 (the first element mounting portion 111 and the second element mounting portion 112) functions as a circuit layer on which the multiple semiconductor elements 30 are mounted and has a relatively small thickness. According to the semiconductor device A10, the first layer 20 located between the multiple semiconductor elements 30 and the first metal layer 11 can quickly dissipate heat generated by the multiple semiconductor elements 30. Therefore, the retention of heat from the plurality of semiconductor elements 30 in the first metal layer 11 stacked on the insulating layer 13 can be suppressed.

[0079] The first layer 20 includes a plurality of individual parts 201 that are separated from one another. Each of the plurality of semiconductor elements 30 is supported by one of the plurality of individual parts 201. With this configuration, it is possible to prevent heat generated by the plurality of semiconductor elements 30 from interfering with each other.

[0080] The constituent material of the first layer 20 includes copper. The thickness of the first layer 20 is greater than the thickness of the second metal layer 12. With this configuration, the thermal conductivity and heat dissipation properties of the first layer 20 can be improved. In addition, as a preferred example, the thickness of the first layer 20 is 2 mm to 3 mm, which is 1 to 10 times the thickness of the second metal layer 12. With this configuration, the heat dissipation properties of the first layer 20 can be further improved.

[0081] The constituent material of the third layer 22 contains silver. The third layer 22 is sintered silver (sintered metal). With this configuration, the third layer 22 has excellent thermal conductivity. As a result, heat generated in the plurality of semiconductor elements 30 is quickly conducted to the second layer 21 via the third layer 22. This is preferable in terms of efficiently dissipating the heat generated in the plurality of semiconductor elements 30.

[0082] 19 to 23 show semiconductor devices according to modifications of the first embodiment. In the figures from Fig. 19 onwards, elements that are the same as or similar to those in the semiconductor device A10 of the above embodiment are given the same reference numerals as in the above embodiment, and descriptions thereof will be omitted where appropriate.

[0083] The semiconductor device A11 of this modification differs from the semiconductor device A10 of the above embodiment mainly in the configuration of the first layer 20. In this modification, each of the multiple individual units 201 constituting the first layer 20 has a larger dimension in the second direction y than the above embodiment, and is rectangular when viewed in the thickness direction z. As shown in FIGS. 20 and 22 , for each of the multiple individual units 201, the dimension L2 in the second direction y is larger than the dimension L1 in the first direction x. Note that in the illustrated example, the dimension L2 of each individual unit 201 in the second direction y is larger than the dimension L1 in the first direction x, but this does not necessarily mean that the dimension L2 is larger than the dimension L1. The dimensions L1 and L2 are limited by the package size of the semiconductor device A11. To efficiently dissipate heat from the semiconductor element 30 in the first layer 20, it is desirable to make both the dimension L1 in the first direction x and the dimension L2 in the second direction y larger than the planar size of the semiconductor element 30, within the limits of the package size. For example, the dimension L2 of the individual part 201 in the second direction y is 0.5 to 2.0 times the dimension L1 of the individual part 201 in the first direction x. Furthermore, the dimension L2 of the individual part 201 in the second direction y is 1.2 to 4.0 times the dimension of the semiconductor element 30 in the second direction y.

[0084] The semiconductor device A11 of this modification also achieves the same effects as the semiconductor device A10 of the above embodiment. Furthermore, in this modification, in each of the multiple individual parts 201, the dimension L2 in the second direction y is greater than the dimension L1 in the first direction x, which is the arrangement direction of the multiple semiconductor elements 30. This configuration increases the volume of the first layer 20 (the multiple individual parts 201), making it possible to further increase the heat capacity of the first layer 20. This allows heat generated in the multiple semiconductor elements 30 to be diffused in the second direction y in the multiple individual parts 201 and dissipated more efficiently.

[0085] 24 to 26 show a semiconductor device according to a second embodiment of the present disclosure. A semiconductor device A20 of this embodiment differs from the semiconductor device A10 of the first embodiment mainly in the configuration of the first layer 20.

[0086] In the semiconductor device A20, the first layer 20 includes a plurality of individual parts 201 that are separated from one another, similar to the first embodiment. However, in the semiconductor device A20, the dimension of each of the plurality of individual parts 201 in the first direction x is larger than that in the first embodiment. Each of the plurality of individual parts 201 supports a plurality of semiconductor elements 30. In the illustrated example, one individual part 201 supports two semiconductor elements 30 that are adjacent to each other in the first direction x. Note that one individual part 201 may be configured to support three or more semiconductor elements 30.

[0087] The semiconductor device A20 of this embodiment also achieves the same effects as the semiconductor device A10 of the first embodiment. Furthermore, in the semiconductor device A20, the volume of the first layer 20 is increased by the portions corresponding to the gaps between the individual units 201 adjacent to each other in the first direction x in the semiconductor device A10. This makes it possible to further increase the heat capacity of the first layer 20. This allows the heat generated in the multiple semiconductor elements 30 to be diffused in the first direction x in the first layer 20 and dissipated more efficiently.

[0088] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0089] The present disclosure includes the embodiments described in the following appendices.

[0090] Supplementary Note 1. A semiconductor device comprising: a substrate having a main surface facing one side in a thickness direction; a plurality of semiconductor elements located on one side of the substrate in the thickness direction and having a switching function; a first layer located between the main surface and the plurality of semiconductor elements in the thickness direction and having conductivity; a second layer electrically connecting the main surface to the first layer; and a third layer electrically connecting the first layer to the plurality of semiconductor elements. Supplementary Note 2. The semiconductor device according to Supplementary Note 1, wherein the substrate has a first metal layer including the main surface, a second metal layer located on the other side of the first metal layer in the thickness direction, and an insulating layer interposed between the first metal layer and the second metal layer. Supplementary Note 3. The semiconductor device according to Supplementary Note 2, wherein the first layer includes a plurality of individual parts separated from each other. Supplementary Note 4. The semiconductor device according to Supplementary Note 3, wherein each of the plurality of semiconductor elements is supported by one of the plurality of individual parts. Supplementary Note 5. The semiconductor device according to Supplementary Note 4, wherein the plurality of semiconductor elements are arranged at intervals in a first direction orthogonal to the thickness direction, and wherein each of the plurality of individual parts has a dimension in a second direction orthogonal to both the thickness direction and the first direction that is larger than its dimension in the first direction. Supplementary Note 6. The semiconductor device according to any of Supplements 2 to 5, wherein the first layer contains copper. Supplementary Note 7. The semiconductor device according to any of Supplements 2 to 6, wherein the thickness of the first layer is larger than the thickness of the second metal layer. Supplementary Note 8. The semiconductor device according to Supplementary Note 7, wherein the thickness of the first layer is 10 times or less the thickness of the second metal layer. Supplementary Note 9. The semiconductor device according to Supplementary Note 7 or 8, wherein the thickness of the first layer is 2 mm to 3 mm. Supplementary Note 10. The semiconductor device according to Supplementary Note 9, wherein the thickness of the second metal layer is 0.3 mm to 2.0 mm. Supplementary Note 11. The semiconductor device according to any of Supplements 2 to 10, wherein the thickness of the first metal layer is 0.1 mm to 2.0 mm. Supplementary Note 12. The semiconductor device according to any one of claims 2 to 11, wherein the first layer is made of a material having the same thermal conductivity as the second metal layer or a material having a thermal conductivity higher than that of the second metal layer.Appendix 14. The semiconductor device according to any one of Appendixes 1 to 13, wherein the third layer includes a sintered metal. Appendix 15. The semiconductor device according to any one of Appendixes 1 to 14, wherein each of the plurality of semiconductor elements has a semiconductor layer including SiC. Appendix 16. The semiconductor device according to any one of Appendixes 1 to 15, wherein each of the plurality of semiconductor elements has a gate electrode, a source electrode, and a drain electrode, and the drain electrode and the first layer are electrically connected by the third layer.

[0091] A10, A11, A20: semiconductor device 10: substrate 11: first metal layer 11A: main surface 111: first element mounting portion 111a: first power supply pad 112: second element mounting portion 112a: output pad 113: first conductive portion 113a: second power supply pad 113b: notch 114: first gate portion 115: first detection portion 116: thermistor mounting portion 117: second gate portion 118: second detection portion 12: second metal layer 13: insulating layer 20: first layer 201: individual portion 21: second layer 22: third layer 23: power supply terminal 23a: first power supply terminal 23a 23b: second power supply terminal 23b 231: external connection portion 231a: connection hole 232: internal connection portion 233: Intermediate portion 233a: Base portion 233b: Upright portion 24: Output terminal 24a: First terminal portion 24b: Second terminal portion 241: External connection portion 241a: Connection hole 242: Internal connection portion 243: Intermediate portion 243a: Base portion 243b: Upright portion 25: Gate terminal 25a: First gate terminal 25b: Second gate terminal 26: Element current detection terminal 26a: First detection terminal 26b: Second detection terminal 27: Power supply current detection terminal 28: Thermistor terminal 30: Semiconductor element 301: Source electrode 302: Drain electrode 303: Gate electrode 31: First element 32: Second element 40: Conductive member 41: First conductive member 42: Second conductive member 431: First gate wire 432: Second gate wire 433: Third gate wire 434: Fourth gate wire 441: First detection wire 442: Second detection wire 443: Third detection wire 444: Fourth detection wire 45: Power supply current detection wire 46: Thermistor wire 48,49: Conductive member bonding layer 60: Case 611: First side wall 612: Second side wall 62: Mounting portion 621: Mounting member 621a: Mounting hole 63: Power terminal block 631: First terminal block 632: Second terminal block 633: Groove portion 634: Nut 635: Intermediate member 64: Power terminal block 641: First terminal block 642: Second terminal block 643: Groove portion 644: Nut 645: Intermediate member 70: Sealing resin L1: Dimension (dimension of individual part in first direction) L2: Dimension (dimension of individual part in second direction) x: First direction y: Second direction z: Thickness direction

Claims

1. A substrate having a main surface facing one side in a thickness direction; a plurality of semiconductor elements located on one side of the substrate in the thickness direction and having a switching function; a first layer located between the main surface and the semiconductor elements in the thickness direction and having electrical conductivity; a second layer electrically connecting the main surface and the first layer; a third layer that electrically connects the first layer and the plurality of semiconductor elements.

2. 2. The semiconductor device according to claim 1, wherein the substrate has a first metal layer including the main surface, a second metal layer located on the other side of the thickness direction relative to the first metal layer, and an insulating layer interposed between the first metal layer and the second metal layer.

3. The semiconductor device according to claim 2 , wherein the first layer includes a plurality of individual parts separated from each other.

4. The semiconductor device according to claim 3 , wherein each of said plurality of semiconductor elements is supported by one of said plurality of individual parts.

5. The semiconductor elements are arranged at intervals in a first direction perpendicular to the thickness direction, 5 . The semiconductor device according to claim 4 , wherein each of said plurality of individual portions has a dimension in a second direction perpendicular to both said thickness direction and said first direction that is greater than a dimension in said first direction.

6. 6. The semiconductor device according to claim 2, wherein said first layer contains copper.

7. 6. The semiconductor device according to claim 2, wherein the thickness of said first layer is greater than the thickness of said second metal layer.

8. 8. The semiconductor device according to claim 7, wherein the thickness of said first layer is ten times or less than the thickness of said second metal layer.

9. 8. The semiconductor device according to claim 7, wherein the first layer has a thickness of 2 mm to 3 mm.

10. 10. The semiconductor device according to claim 9, wherein the second metal layer has a thickness of 0.3 mm to 2.0 mm.

11. 6. The semiconductor device according to claim 2, wherein the first metal layer has a thickness of 0.1 mm to 2.0 mm.

12. 6. The semiconductor device according to claim 2, wherein said first layer is made of a material having the same thermal conductivity as said second metal layer or a material having a thermal conductivity higher than that of said second metal layer.

13. 6. The semiconductor device according to claim 1, wherein said third layer contains silver.

14. 6. The semiconductor device according to claim 1, wherein the third layer includes a sintered metal.

15. The semiconductor device according to claim 1 , wherein each of the plurality of semiconductor elements has a semiconductor layer containing SiC.

16. Each of the plurality of semiconductor elements has a gate electrode, a source electrode, and a drain electrode; 6. The semiconductor device according to claim 1, wherein said drain electrode and said first layer are electrically connected to each other via said third layer.