Junction structure and semiconductor device

Abstract

A connection structure is provided with an electroconductive substrate having an electroconductive section, a terminal including an electroconductive cylindrical holder and a metal pin inserted into the holder, and an electroconductive bonding material for bonding the electroconductive section and the holder. The metal pin includes a linear section that extends along the thickness direction of the electroconductive section. The holder has a first through-hole that extends in the thickness direction and into which the linear section of the metal pin is inserted. The electroconductive section has a terminal bonding surface to which the holder is bonded, and an opening formed on the terminal bonding surface. When viewed in the thickness direction, the outer peripheral edge of the opening is at least partially located inward of the outer peripheral edge of the holder.

Description

Junction structure and semiconductor device

[0001] The present disclosure relates to a junction structure and a semiconductor device.

[0002] Conventionally, semiconductor devices including power semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have been known. Such semiconductor devices can be installed in a wide variety of electronic devices, from industrial equipment to household appliances, information terminals, and automotive equipment. Patent Document 1 (Patent Document 1) discloses a conventional semiconductor device (power semiconductor module). The power semiconductor module described in Patent Document 1 includes a ceramic circuit substrate, power semiconductor elements, a metal tube, external terminals, and transfer mold resin (see FIG. 6 of Patent Document 1). The ceramic circuit substrate includes a ceramic plate and a copper foil conductive portion (wiring pattern) provided on the ceramic plate. The power semiconductor elements and the metal tube are arranged on the wiring pattern of the ceramic circuit substrate. The metal tube is joined to the wiring pattern, for example, by soldering. The external terminals are press-fitted into the metal tube. The external terminals protrude from the upper surface of the transfer mold resin.

[0003] JP 2010-129795 A

[0004] In the power semiconductor device described in Patent Document 1, external terminals are inserted into a metal tube. In such a configuration in which the external terminals are inserted into a metal tube, there is a risk that the external terminals may come out of the metal tube if the external terminals are not inserted into the metal tube by a sufficient amount.

[0005] The present disclosure has been devised in view of the above circumstances, and has as its object to provide a joint structure between a metal tube and a conductive part that can ensure an appropriate insertion amount of an external terminal into the metal tube. Another object of the present disclosure is to provide a semiconductor device having such a joint structure.

[0006] The joining structure provided by the first aspect of the present disclosure comprises a conductive substrate having a conductive portion, a conductive cylindrical holder, a terminal including a metal pin inserted into the holder, and a conductive joining material joining the conductive portion and the holder, wherein the metal pin includes a straight portion extending along the thickness direction of the conductive portion, the holder has a first through hole extending in the thickness direction and into which the straight portion of the metal pin is inserted, the conductive portion has a terminal joining surface to which the holder is joined and an opening formed in the terminal joining surface, and when viewed in the thickness direction, at least a portion of the outer peripheral edge of the opening is inside the outer peripheral edge of the holder.

[0007] A semiconductor device provided by a second aspect of the present disclosure includes the junction structure provided by the first aspect and a semiconductor element electrically connected to the terminal.

[0008] The joining structure of the present disclosure can ensure an appropriate amount of insertion of the metal pin into the holder. Furthermore, the semiconductor device of the present disclosure includes a joining structure that ensures an appropriate amount of insertion of the metal pin into the holder, thereby preventing the metal pin from coming out of the holder.

[0009] FIG. 1 is a perspective view showing a semiconductor device according to an embodiment. FIG. 2 is a view in which a plurality of wires, a resin member, a resin portion, and a resin filling portion are omitted from the perspective view of FIG. 1 . FIG. 3 is a view in which conductive members (first conductive member and second conductive member) are omitted from the perspective view of FIG. 2 . FIG. 4 is a plan view showing a semiconductor device according to an embodiment. FIG. 5 is a view in which the resin member, the resin portion, and the resin filling portion are indicated by imaginary lines in the plan view of FIG. 4 . FIG. 6 is a partial enlarged view of a portion of FIG. 5 , in which the resin member, the resin portion, and the resin filling portion are omitted. FIG. 7 is a view in which a portion of the conductive member 5 (second conductive member) is indicated by imaginary lines in the plan view of FIG. 5 . FIG. 8 is a partial enlarged view of a portion of FIG. 7 , in which the main part of the bonding structure according to the present disclosure is shown. FIG. 9 is a front view showing a semiconductor device according to an embodiment. FIG. 10 is a bottom view showing a semiconductor device according to an embodiment. FIG. 11 is a left side view showing a semiconductor device according to an embodiment. FIG. 12 is a right side view showing a semiconductor device according to an embodiment. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 5 . FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 5 . FIG. 15 is a partially enlarged view of FIG. 14 . FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 5 . FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 5 . FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 5 . FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 5 . FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 5 . FIG. 21 is a partially enlarged view of FIG. 20 , showing an enlarged cross-sectional view of a main portion of a junction structure according to the present disclosure. FIG. 22 is a diagram showing an example circuit configuration of a semiconductor device according to an embodiment. FIG. 23 is an enlarged cross-sectional view of a main portion of another example configuration of a junction structure according to the present disclosure. FIG. 24 is an enlarged cross-sectional view of a main portion of another example configuration of a junction structure according to the present disclosure. Fig. 25 is an enlarged plan view of a main portion showing another configuration example of the joining structure of the present disclosure. Fig. 26 is an enlarged plan view of a main portion showing another configuration example of the joining structure of the present disclosure. Fig. 27 is an enlarged plan view of a main portion showing another configuration example of the joining structure of the present disclosure. Fig. 28 is an enlarged plan view of a main portion showing another configuration example of the joining structure of the present disclosure. Fig. 29 is an enlarged plan view of a main portion showing another configuration example of the joining structure of the present disclosure.Fig. 30 is an enlarged plan view of a main portion showing another example of the configuration of the joining structure of the present disclosure. Fig. 31 is a perspective view showing another example of the configuration of the semiconductor device of the present disclosure, in which a plurality of wires, a resin member, a resin portion, and a resin filling portion are omitted.

[0010] Preferred embodiments of the junction structure and semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant description will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not necessarily intended to assign any order to their objects.

[0011] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "when viewed from a certain direction, an object A overlaps an object B" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B."

[0012] 1 to 22 show an example of a semiconductor device A1 of the present disclosure. The semiconductor device A1 includes a plurality of semiconductor elements 1, a support substrate 2, a first power supply terminal 31, a second power supply terminal 32, a plurality of control terminals 33, a conductive substrate 4, a conductive member 5, a plurality of conductive bonding materials 61, 63, a plurality of wires 651 to 654, and a resin member 7. The conductive substrate 4 includes a first conductive substrate 4A and a second conductive substrate 4B. The conductive member 5 includes a first conductive member 51 and a second conductive member 52.

[0013] For convenience of explanation, the thickness direction of the semiconductor device A1 is referred to as the "thickness direction z." In the following explanation, one side of the thickness direction z may be referred to as the "upper side," and the other side may be referred to as the "lower side." Note that in the following explanation, terms such as "upper," "lower," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component in the thickness direction z and do not necessarily define the relationship with the direction of gravity. Furthermore, "plan view" refers to the view in the thickness direction z. A direction perpendicular to the thickness direction z is referred to as the "first direction x." For example, the first direction x is the left-right direction in the plan view of the semiconductor device A1 (see FIGS. 4 and 5). A direction perpendicular to the thickness direction z and the first direction x is referred to as the "second direction y." For example, the second direction y is the up-down direction in the plan view of the semiconductor device A1 (see FIGS. 4 and 5).

[0014] Each of the multiple semiconductor elements 1 is the functional core of the semiconductor device A1. The constituent material of each semiconductor element 1 includes, for example, silicon carbide (SiC). The constituent material is not limited to SiC and may include silicon (Si), gallium arsenide (GaAs), or gallium nitride (GaN). Each semiconductor element 1 is, for example, a switching element. Each semiconductor element 1 has a switching function unit Q1 (see FIG. 22 ) configured by a metal-oxide-semiconductor field-effect transistor (MOSFET). The switching function unit Q1 is not limited to a MOSFET and may be other transistors, such as a field-effect transistor including a metal-insulator-semiconductor FET (MISFET) or a bipolar transistor such as an IGBT. The multiple semiconductor elements 1 are identical to one another. Each semiconductor element 1 is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.

[0015] 3 and 7, the plurality of semiconductor elements 1 include at least one first semiconductor element 1A and at least one second semiconductor element 1B. In the illustrated example, the semiconductor device A1 includes a plurality (three) of first semiconductor elements 1A and a plurality (three) of second semiconductor elements 1B, but the numbers of the first semiconductor elements 1A and the second semiconductor elements 1B are not limited to this configuration and may be changed as appropriate depending on the performance required of the semiconductor device A1.

[0016] As shown in Fig. 22, the semiconductor device A1 is configured, for example, as a half-bridge circuit. A plurality of first semiconductor elements 1A configure an upper arm circuit of the semiconductor device A1, and a plurality of second semiconductor elements 1B configure a lower arm circuit of the semiconductor device A1. As shown in Fig. 22, in the upper arm circuit, the plurality of first semiconductor elements 1A are connected in parallel with each other, and in the lower arm circuit, the plurality of second semiconductor elements 1B are connected in parallel with each other. Each first semiconductor element 1A and each second semiconductor element 1B are connected in series. In other words, each first semiconductor element 1A is connected in series with each of the three second semiconductor elements 1B.

[0017] As shown in Figures 3, 7, and 16, each of the multiple first semiconductor elements 1A is mounted on a support substrate 2. In the examples shown in Figures 3, 7, and 16, the multiple first semiconductor elements 1A are aligned in the second direction y and spaced apart from one another. As shown in Figures 14 and 15, each of the first semiconductor elements 1A is conductively bonded to the support substrate 2 (a first conductor 24A described below) via a conductive bonding material 61 (a conductive bonding material 61A described below).

[0018] As shown in FIGS. 3, 7, and 17, the second semiconductor elements 1B are mounted on a support substrate 2. In the examples shown in FIGS. 3, 7, and 17, the second semiconductor elements 1B are aligned in the second direction y and spaced apart from one another. As shown in FIG. 14, each second semiconductor element 1B is conductively bonded to the support substrate 2 (a second conductor 24B described below) via a conductive bonding material 61 (a conductive bonding material 61B described below). As can be seen from FIG. 7, the first semiconductor elements 1A and the second semiconductor elements 1B overlap each other when viewed in the first direction x. Alternatively, the first semiconductor elements 1A may be arranged so that they do not overlap any of the second semiconductor elements 1B when viewed in the first direction x.

[0019] As shown in FIG. 15 , each of the multiple semiconductor elements 1 (multiple first semiconductor elements 1A and multiple second semiconductor elements 1B) has an element main surface 10a and an element back surface 10b. While FIG. 15 shows an example structure of each first semiconductor element 1A, each second semiconductor element 1B has a similar structure. As shown in FIG. 15 , in each semiconductor element 1, the element main surface 10a and the element back surface 10b are spaced apart in the thickness direction z. The element main surface 10a faces one side (upward) in the thickness direction z, and the element back surface 10b faces the other side (downward) in the thickness direction z. When each first semiconductor element 1A is bonded to the first conductor 24A, the element back surface 10b of each first semiconductor element 1A faces the first conductor 24A. When each second semiconductor element 1B is bonded to the second conductor 24B, the element back surface 10b of each second semiconductor element 1B faces the second conductor 24B.

[0020] As shown in FIGS. 7 and 15 , each of the multiple semiconductor elements 1 (multiple first semiconductor elements 1A and multiple second semiconductor elements 1B) has a first principal surface electrode 11, a second principal surface electrode 12, and a back surface electrode 15. The first principal surface electrode 11, the second principal surface electrode 12, and the back surface electrode 15 are configured in the same manner in each semiconductor element 1. The first principal surface electrode 11 and the second principal surface electrode 12 are disposed on the element main surface 10a of each semiconductor element 1. The first principal surface electrode 11 and the second principal surface electrode 12 are insulated by an insulating film (not shown). The back surface electrode 15 is disposed on the element back surface 10b of each semiconductor element 1.

[0021] In each semiconductor element 1, the first principal surface electrode 11 is, for example, a gate, to which a drive signal (e.g., a gate voltage) for driving the semiconductor element 1 is input. In each semiconductor element 1, the second principal surface electrode 12 is, for example, a source, through which a source current flows. The back surface electrode 15 is, for example, a drain, through which a drain current flows. The back surface electrode 15 covers the entire area (or substantially the entire area) of the element back surface 10b. The back surface electrode 15 is, for example, formed by Ag plating.

[0022] When a drive signal (gate voltage) is input to the first principal surface electrode 11 (gate) by the switching function unit Q1, each semiconductor element 1 switches between a conductive state and a cutoff state in response to the drive signal. This switching between the conductive state and the cutoff state is called a switching operation. In the conductive state, current flows from the back surface electrode 15 (drain) to the second principal surface electrode 12 (source), and in the cutoff state, this current does not flow. In other words, each semiconductor element 1 performs a switching operation by the switching function unit Q1. The semiconductor device A1 converts a first power supply voltage (e.g., a DC voltage) into a second power supply voltage (e.g., an AC voltage) by the switching function units Q1 of the multiple semiconductor elements 1. The first power supply voltage is input to a first power supply terminal 31, and the second power supply voltage is input to a second power supply terminal 32.

[0023] Some of the semiconductor elements 1 (two in the semiconductor device A1) further include a diode function unit D1 (see FIG. 22 ) in addition to the switching function unit Q1. In the example shown in FIG. 7 , one of the first semiconductor elements 1A (the first semiconductor element 1A arranged closest to one side in the second direction y in FIG. 7 ) and one of the second semiconductor elements 1B (the second semiconductor element 1B arranged closest to the other side in the second direction y in FIG. 7 ) include the diode function unit D1. The function or role of the diode function unit D1 is not particularly limited, but examples include a temperature detection diode. Note that the diode D2 shown in FIG. 22 is, for example, a parasitic diode component of the switching function unit Q1. In a configuration different from the semiconductor device A1, none of the semiconductor elements 1 may include the diode function unit D1.

[0024] 7, each semiconductor element 1 having the diode functional portion D1 further has a pair of third principal surface electrodes 13 in addition to the first principal surface electrode 11, the second principal surface electrode 12, and the back surface electrode 15. The pair of third principal surface electrodes 13 are configured in the same manner in each semiconductor element 1 having the diode functional portion D1. As can be seen from FIG. 7, the pair of third principal surface electrodes 13 are formed on the element principal surface 10a. In each semiconductor element 1 having the diode functional portion D1, each of the pair of third principal surface electrodes 13 is electrically connected to the diode functional portion D1.

[0025] The configuration of each of the plurality of semiconductor elements 1 (the plurality of first semiconductor elements 1A and the plurality of second semiconductor elements 1B) is not limited to the above example. For example, an additional electrode (e.g., a source sense) having the same potential as the second principal surface electrode 12 may be formed on the element principal surface 10a.

[0026] The support substrate 2 supports the plurality of semiconductor elements 1. The support substrate 2, together with the conductive members 5, constitutes a path for a main circuit current switched by each semiconductor element 1. The support substrate 2 includes an insulating layer 21, a main surface metal layer 22, a bonding layer 221, a back surface metal layer 23, a first conductor 24A, a second conductor 24B, and a pair of conductive bonding materials 25A, 25B.

[0027] The insulating layer 21 is made of, for example, ceramics with excellent thermal conductivity. Examples of such ceramics include AlN (aluminum nitride), SiN (silicon nitride), and Al2O3 (aluminum oxide). The insulating layer 21 may be made of an insulating resin sheet instead of ceramics. The insulating layer 21 has, for example, a rectangular shape in a plan view.

[0028] 13 to 15, the insulating layer 21 has a principal surface 21a and a rear surface 21b. The principal surface 21a and the rear surface 21b are spaced apart in the thickness direction z. The principal surface 21a faces upward in the thickness direction z, and the rear surface 21b faces downward in the thickness direction z. The principal surface 21a and the rear surface 21b are flat (or approximately flat).

[0029] 13 to 15, the main surface metal layer 22 is formed on the main surface 21a. The constituent material of the main surface metal layer 22 is, for example, Cu or a Cu alloy. The constituent material may be Al or an Al alloy instead of Cu or a Cu alloy.

[0030] 13 and 14 , the main surface metal layer 22 includes a first support portion 22A and a second support portion 22B. The first support portion 22A and the second support portion 22B are spaced apart in the first direction x. A first conductor 24A is joined to the first support portion 22A, and the first support portion 22A supports the first conductor 24A. A second conductor 24B is joined to the second support portion 22B, and the second support portion 22B supports the second conductor 24B. Each of the first support portion 22A and the second support portion 22B has a rectangular shape in a plan view, for example.

[0031] 15 , the bonding layer 221 is formed on the upper surface of the main surface metal layer 22 (each of the first support portion 22A and the second support portion 22B). The bonding layer 221 is, for example, Ag plating. The bonding layer 221 is provided, for example, to improve bonding with the conductive bonding materials 25A and 25B by solid-state diffusion.

[0032] As shown in FIGS. 13 to 15 , the back surface metal layer 23 is formed on the back surface 21b. The material of the back surface metal layer 23 is the same as the material of the main surface metal layer 22. The lower surface of the back surface metal layer 23 (the surface facing the other side in the thickness direction z) is exposed from the resin member 7, for example, as shown in FIGS. 10 and 13 to 15 . In a different configuration, the lower surface of the back surface metal layer 23 may be covered by the resin member 7. In an example in which the lower surface of the back surface metal layer 23 is exposed from the resin member 7, a heat dissipation member (for example, a heat sink) (not shown) can be attached to the lower surface. The back surface metal layer 23 overlaps both the first support portion 22A and the second support portion 22B in a plan view.

[0033] In an example in which the main surface metal layer 22 and the back surface metal layer 23 of the support substrate 2 are made of Cu or a Cu alloy, the insulating layer 21, the main surface metal layer 22, and the back surface metal layer 23 are made of, for example, a DBC (Direct Bonded Copper) substrate. In contrast to this configuration, in an example in which the main surface metal layer 22 and the back surface metal layer 23 are made of Al or an Al alloy, the insulating layer 21, the main surface metal layer 22, and the back surface metal layer 23 are made of, for example, a DBA (Direct Bonded Aluminum) substrate.

[0034] The first conductor 24A and the second conductor 24B are each a plate-shaped member made of metal. This metal is, for example, Cu or a Cu alloy. The first conductor 24A and the second conductor 24B, together with the first power supply terminal 31 and the second power supply terminal 32, form a conduction path to multiple semiconductor elements 1. As shown in FIGS. 7 , 13 , and 14 , the first conductor 24A and the second conductor 24B are spaced apart in the first direction x. As shown in FIG. 7 , the first conductor 24A and the second conductor 24B are rectangular in plan view. The first conductor 24A and the second conductor 24B overlap when viewed in the first direction x. Each of first conductor 24A and second conductor 24B has a dimension in the first direction x of 15 mm to 25 mm (preferably 20 mm), a dimension in the second direction y of 30 mm to 40 mm (preferably 35 mm), and a dimension in the thickness direction z of 1.5 mm to 3.0 mm (preferably 2.0 mm). These dimensions of first conductor 24A and second conductor 24B are not limited to the above-mentioned numerical examples and can be changed as appropriate depending on the specifications of semiconductor device A1.

[0035] As shown in FIG. 15 , the first conductor 24A includes a substrate 241, a main surface bonding layer 242, and a back surface bonding layer 243. Like the first conductor 24A, the second conductor 24B also includes a substrate 241, a main surface bonding layer 242, and a back surface bonding layer 243. The substrate 241, the main surface bonding layer 242, and the back surface bonding layer 243 are configured in the same manner in the first conductor 24A and the second conductor 24B. The substrate 241 is a metal plate-shaped member. This metal is Cu or a Cu alloy. The main surface bonding layer 242 is formed on the upper surface of the substrate 241 (the surface facing upward in the thickness direction z). The main surface bonding layer 242 is a surface layer on the upper side in the thickness direction z in each of the first conductor 24A and the second conductor 24B. The main surface bonding layer 242 is, for example, Ag plating. The back surface bonding layer 243 is formed on the lower surface (the surface facing downward in the thickness direction z) of the base material 241. The back surface bonding layer 243 is a surface layer on the lower side in the thickness direction z of each of the first conductor 24A and the second conductor 24B. Like the main surface bonding layer 242, the back surface bonding layer 243 is, for example, Ag plating.

[0036] 13 to 16 and 20, the first conductor 24A is bonded to the first support portion 22A via a conductive bonding material 25A. As shown in FIGS. 14 to 16 and 20, a plurality of first semiconductor elements 1A are bonded to the upper surface (the surface facing upward in the thickness direction z) of the first conductor 24A via a conductive bonding material 61 (a conductive bonding material 61A described below). The back surface electrodes 15 (drains) of the plurality of first semiconductor elements 1A are electrically connected to one another via the first conductor 24A.

[0037] 13 , 14 , 17 , and 18 , the second conductor 24B is bonded to the second support 22B via a conductive bonding material 25B. As shown in FIGS. 14 and 17 , a plurality of second semiconductor elements 1B are bonded to the upper surface (the surface facing upward in the thickness direction z) of the second conductor 24B via a conductive bonding material 61 (a conductive bonding material 61A described below). The back surface electrodes 15 (drains) of the plurality of second semiconductor elements 1B are electrically connected to one another via the second conductor 24B.

[0038] 7 and 13 , a plurality of recesses 240a are formed on the upper surface of each of the first conductor 24A and the second conductor 24B in the thickness direction z. Each recess 240a is recessed in the thickness direction z from the upper surface of the first conductor 24A or the upper surface of the second conductor 24B in the thickness direction z. Each recess 240a is formed during molding of the resin member 7. The two recesses 240a formed on the upper surface of the first conductor 24A in the thickness direction z are spaced apart in the second direction y and overlap when viewed in the second direction y. The two recesses 240a formed on the upper surface of the second conductor 24B in the thickness direction z are spaced apart in the second direction y and overlap when viewed in the second direction y.

[0039] As shown in Figures 13 to 15 and 20, the conductive bonding material 25A is interposed between the first support portion 22A and the first conductor 24A. The conductive bonding material 25A bonds the first conductor 24A to the first support portion 22A. As shown in Figures 13, 14, 17 and 18, the conductive bonding material 25B is interposed between the second support portion 22B and the second conductor 24B. The conductive bonding material 25B bonds the second conductor 24B to the second support portion 22B.

[0040] 15 , the conductive bonding material 25A has a base layer 251, an upper layer 252, and a lower layer 253. Like the conductive bonding material 25A, the conductive bonding material 25B also has a base layer 251, an upper layer 252, and a lower layer 253. In each of the conductive bonding materials 25A and 25B, the base layer 251, the upper layer 252, and the lower layer 253 are stacked on top of each other. The base layer 251, the upper layer 252, and the lower layer 253 are configured in the same way in each of the conductive bonding materials 25A and 25B.

[0041] The base layer 251 is made of metal, such as Al or an Al alloy, and is, for example, a sheet material.

[0042] The upper layer 252 is formed on the upper surface of the base layer 251. The upper layer 252 is formed, for example, by Ag plating. In the conductive bonding material 25A, the upper layer 252 is interposed between the base layer 251 and the first conductor 24A. The upper layer 252 of the conductive bonding material 25A is bonded to the back surface bonding layer 243 of the first conductor 24A, for example, by solid-state diffusion of metal. In the conductive bonding material 25B, the upper layer 252 is interposed between the base layer 251 and the second conductor 24B. The upper layer 252 of the conductive bonding material 25B is bonded to the back surface bonding layer 243 of the second conductor 24B, for example, by solid-state diffusion of metal. As a result, the upper layers 252 of the pair of conductive bonding materials 25A, 25B and the back surface bonding layers 243 of the first conductor 24A and the second conductor 24B are bonded in direct contact with each other at the bonding interfaces. In the present disclosure, "A and B are bonded by solid-state diffusion" means that, as a result of solid-state diffusion bonding, A and B are fixed to each other in a state of direct contact at the bonding interface, and it can be said that a solid-state diffusion bonding layer is formed by A and B. When solid-state diffusion bonding is performed under ideal conditions, the bonding interface may not be clearly present due to the diffusion of metal elements. On the other hand, if inclusions such as oxide films are present on the surfaces of A and B or if voids exist between A and B, these inclusions or voids may be present at the bonding interface.

[0043] The lower layer 253 is formed on the lower surface of the base layer 251. The lower layer 253 is formed, for example, by Ag plating. In the conductive bonding material 25A, the lower layer 253 is interposed between the base layer 251 and the first support portion 22A. The lower layer 253 of the conductive bonding material 25A is bonded to the bonding layer 221 on the first support portion 22A, for example, by solid-state diffusion of metal. In the conductive bonding material 25B, the lower layer 253 is interposed between the base layer 251 and the second support portion 22B. The lower layer 253 of the conductive bonding material 25B is bonded to the bonding layer 221 on the second support portion 22B, for example, by solid-state diffusion of metal. As a result, the lower layers 253 of the pair of conductive bonding materials 25A, 25B and the bonding layers 221 on the first support portion 22A and the second support portion 22B are bonded in direct contact with each other at the bonding interfaces.

[0044] The configuration of each of the conductive bonding materials 25A, 25B is not limited to the example having the base layer 251, the upper layer 252 and the lower layer 253 described above, but may be solder, a metal paste material, a sintered metal, or the like.

[0045] The first power supply terminal 31 and the second power supply terminal 32 are each a plate-shaped member made of metal. This metal is, for example, Cu or a Cu alloy. The first power supply terminal 31 includes an input terminal 31A and two input terminals 31B, and the second power supply terminal 32 includes two output terminals 32A. The input terminal 31A is an example of a "first input terminal," and each input terminal 31B is an example of a "second input terminal."

[0046] A first power supply voltage is applied between the input terminal 31A and the two input terminals 31B. That is, the first power supply voltage is input to the first power supply terminal 31. The input terminal 31A is, for example, a positive polarity (P terminal), and each of the two input terminals 31B is, for example, a negative polarity (N terminal). Alternatively, the input terminal 31A may be a negative polarity (N terminal), and each of the two input terminals 31B may be a positive polarity (P terminal). In this case, the wiring inside the package may be appropriately changed in accordance with the change in terminal polarity. A second power supply voltage is applied to each of the two output terminals 32A. That is, the second power supply voltage is input to the second power supply terminal 32. Each of the multiple input terminals 31A, 31B and the two output terminals 32A includes a portion covered by the resin member 7 and a portion exposed from the resin member 7.

[0047] As shown in Fig. 14 , the input terminal 31A is formed integrally with, for example, the first conductor 24A. Alternatively, the input terminal 31A may be separated from the first conductor 24A and conductively joined to the first conductor 24A. As shown in Fig. 7 and other figures, the input terminal 31A is located on the opposite side of the multiple first semiconductor elements 1A from the multiple second semiconductor elements 1B in the first direction x. The input terminal 31A is electrically connected to the first conductor 24A and, via the first conductor 24A, to the back electrode 15 (drain) of each semiconductor element 1.

[0048] As shown in Fig. 13 , the two input terminals 31B are each spaced apart from the first conductor 24A. A second conductive member 52 is joined to each of the two input terminals 31B. As shown in Fig. 7 , the two input terminals 31B are each located on the same side as the input terminal 31A with respect to the multiple first semiconductor elements 1A in the first direction x. Each of the two input terminals 31B is electrically connected to the second conductive member 52 and, via the second conductive member 52, is electrically connected to the second main surface electrode 12 (source) of each second semiconductor element 1B.

[0049] In the semiconductor device A1, the first power supply terminals 31 (input terminal 31A and two input terminals 31B) protrude from the resin member 7 in one direction in the first direction x. The input terminal 31A and the two input terminals 31B are spaced apart from each other. The two input terminals 31B are located on opposite sides of the input terminal 31A in the second direction y. The input terminal 31A and the two input terminals 31B overlap each other when viewed in the second direction y.

[0050] As can be seen from FIGS. 7 and 14 , the two output terminals 32A are each formed integrally with, for example, the second conductor 24B. Alternatively, the two output terminals 32A may each be separated from the second conductor 24B and conductively joined to the second conductor 24B. As shown in FIG. 7 and other figures, the two output terminals 32A are each located on the opposite side of the second semiconductor elements 1B from the first semiconductor elements 1A in the first direction x. Each output terminal 32A is electrically connected to the second conductor 24B and, via the second conductor 24B, to the back electrode 15 (drain) of each second semiconductor element 1B. In the semiconductor device A1, the number of output terminals 32A is not limited to two and may be, for example, one or three or more. For example, if the semiconductor device A1 has one output terminal 32A, it is desirable that this one output terminal 32A be connected to the central portion of the second conductor 24B in the second direction y in order to reduce the difference in distance of the conduction paths to the first main surface electrodes 11 (drains) of each second semiconductor element 1B that pass through the second conductor 24B.

[0051] The plurality of control terminals 33 are pin-shaped terminals for controlling the respective semiconductor elements 1. The plurality of control terminals 33 include a plurality of first control terminals 34 and a plurality of second control terminals 35, as shown in FIGS.

[0052] The plurality of first control terminals 34 are used to control the plurality of first semiconductor elements 1A. As shown in Figures 1 and 4, the plurality of first control terminals 34 include a first drive terminal 34A and a plurality of first detection terminals 34B to 34D.

[0053] 7 and 20 , the first drive terminal 34A is bonded to the first conductive substrate 4A. The first drive terminal 34A is electrically connected to each of the first principal surface electrodes 11 (gates) of the plurality of first semiconductor elements 1A. The first drive terminal 34A is an input terminal for a first drive signal. The first drive signal is an electrical signal for driving each of the plurality of first semiconductor elements 1A, and is a gate voltage in an example in which each first semiconductor element 1A is a MOSFET.

[0054] 7 and 20, the first detection terminal 34B is bonded to the first conductive substrate 4A. The first detection terminal 34B is electrically connected to each of the second principal surface electrodes 12 (sources) of the plurality of first semiconductor elements 1A. The first detection terminal 34B is an output terminal for a first detection signal. The first detection signal is an electrical signal for detecting the electrical conduction state of the plurality of first semiconductor elements 1A.

[0055] 7 and 20 , the pair of first detection terminals 34C are bonded to the first conductive substrate 4A. Each of the pair of first detection terminals 34C is electrically connected to the pair of third principal surface electrodes 13 of the first semiconductor element 1A having the diode functional portion D1. The pair of first detection terminals 34C are terminals electrically connected to the diode functional portion D1 of the first semiconductor element 1A.

[0056] 7 and 20 , the first detection terminal 34D is bonded to the first conductive substrate 4A. The first detection terminal 34D is electrically connected to each back electrode 15 (drain) of the multiple first semiconductor elements 1A. The voltage of each back electrode 15 of the multiple first semiconductor elements 1A (a voltage corresponding to the drain current) is applied to the first detection terminal 34D. The first detection terminal 34D is a terminal (drain sense terminal) for detecting drain signals of the multiple semiconductor elements 1A.

[0057] The second control terminals 35 are used to control the second semiconductor elements 1B. As shown in FIGS. 1 and 4, the second control terminals 35 include a second drive terminal 35A and second detection terminals 35B and 35C.

[0058] 7 and 18, the second drive terminal 35A is bonded to the second conductive substrate 4B. The second drive terminal 35A is electrically connected to each of the first principal surface electrodes 11 (gates) of the second semiconductor elements 1B. The second drive terminal 35A is an input terminal for a second drive signal. The second drive signal is an electrical signal for driving each of the second semiconductor elements 1B, and is a gate voltage in an example in which each second semiconductor element 1B is a MOSFET.

[0059] 7 and 18, the second detection terminal 35B is bonded to the second conductive substrate 4B. The second detection terminal 35B is electrically connected to each of the second main surface electrodes 12 (sources) of the second semiconductor elements 1B. The second detection terminal 35B is an output terminal for a second detection signal. The second detection signal is an electrical signal for detecting the electrical conduction state of the second semiconductor elements 1B.

[0060] 7 and 18, the pair of second detection terminals 35C are bonded to the second conductive substrate 4B. Each of the pair of second detection terminals 35C is electrically connected to a pair of third principal surface electrodes 13 of the second semiconductor element 1B having the diode function portion D1. The pair of second detection terminals 35C are terminals electrically connected to the diode function portion D1 of the second semiconductor element 1B.

[0061] Each of the plurality of control terminals 33 (first drive terminal 34A, the plurality of first detection terminals 34B to 34D, second drive terminal 35A, and the plurality of second detection terminals 35B and 35C) includes a holder 331 and a metal pin 333. The holder 331 and the metal pin 333 are configured in the same manner in each control terminal 33.

[0062] The holder 331 is made of a conductive material and is joined to the conductive substrate 4 (either the first conductive substrate 4A or the second conductive substrate 4B) via a conductive bonding material 63, as shown in Figures 18, 20, and 21. A metal pin 333 is inserted into the holder 331.

[0063] As shown in FIGS. 8 and 21 , the holder 331 includes a tubular portion 331a, an upper flange 331b, and a lower flange 331c. The tubular portion 331a is, for example, cylindrical and is arranged in a circular orientation in the semiconductor device A1 in a plan view. The metal pin 333 is inserted into the tubular portion 331a. The upper flange 331b and the lower flange 331c are arranged on either side of the tubular portion 331a in the thickness direction z. The upper flange 331b and the lower flange 331c are, for example, circular in plan view. Alternatively, the upper flange 331b and the lower flange 331c may be elliptical or polygonal (including rectangular) in plan view. The upper flange 331b and the lower flange 331c have the same shape and size in plan view. The upper flange 331b and the lower flange 331c are larger than the cylindrical portion 331a in a plan view. The upper flange 331b is connected to the upper edge of the cylindrical portion 331a in the thickness direction z. The upper surface of the upper flange 331b is exposed from the resin member 7 (second protrusion 752 described below) and is covered by the resin portion 77. The lower flange 331c is connected to the lower edge of the cylindrical portion 331a in the thickness direction z. The lower flange 331c is joined to the conductive substrate 4 by a conductive bonding material 63.

[0064] As shown in FIGS. 8 and 21 , the holder 331 has a through hole 332. As shown in FIG. 21 , the through hole 332 penetrates the holder 331 in the thickness direction z and straddles the cylindrical portion 331 a, the upper end flange portion 331 b, and the lower end flange portion 331 c in the thickness direction z. The metal pin 333 is inserted into the through hole 332. The through hole 332 has a circular shape in a plan view. The inner diameter of the holder 331, i.e., the diameter r1 of the through hole 332 in a plan view (see FIG. 8 ), is, for example, 0.5 mm or more and 1.0 mm or less. The through hole 332 is an example of a “first through hole.”

[0065] The metal pin 333 is a rod-shaped member extending in the thickness direction z. The metal pin 333 is supported by being press-fitted into the holder 331. The metal pin 333 is inserted into the holder 331 from above in the thickness direction z. The metal pin 333 is electrically connected to the conductive substrate 4 (main surface metal layer 42 described below) via the holder 331. The metal pin 333 is, for example, a pin for a press-fit terminal. In the semiconductor device A1, the metal pin 333 extends straight from the holder 331 in the thickness direction z, but may be partially bent above the holder 331 in the thickness direction z.

[0066] The metal pin 333 includes a straight portion 333a. The straight portion 333a extends along the thickness direction z. The straight portion 333a is a portion of the metal pin 333 that is inserted into the through hole 332. At least a portion of the straight portion 333a contacts the inner surface of the holder 331.

[0067] In each control terminal 33, the dimension d1 (see FIG. 21 ) of the straight portion 333a in the thickness direction z is 20% to 90% of the dimension of the holder 331 in the thickness direction z. For example, in an example where the dimension of the holder 331 in the thickness direction z is 2.8 mm, the dimension d1 of the straight portion 333a in the thickness direction z is 2.0 mm. The dimension d1 of the straight portion 333a in the thickness direction z corresponds to the insertion amount of the metal pin 333 into the holder 331.

[0068] The conductive substrate 4 supports a plurality of control terminals 33. The conductive substrate 4 is interposed between the support substrate 2 and the plurality of control terminals 33. The conductive substrate 4 is formed, for example, of a DBC substrate. Alternatively, the conductive substrate 4 may be formed of a DBA substrate. Furthermore, the conductive substrate 4 may be formed of a printed circuit board instead of a DBC substrate.

[0069] As shown in FIGS. 7 and 14 , the conductive substrate 4 includes a first conductive substrate 4A and a second conductive substrate 4B. The first conductive substrate 4A is disposed on the first conductor 24A of the support substrate 2. The first conductive substrate 4A supports a plurality of first control terminals 34 among the plurality of control terminals 33, i.e., the first drive terminal 34A and a plurality of first detection terminals 34B to 34D. As shown in FIGS. 15 , 20 , and 21 , the first conductive substrate 4A is bonded to the first conductor 24A via a bonding material 49. The bonding material 49 may be conductive or insulating, and is, for example, solder. The second conductive substrate 4B is disposed on the second conductor 24B of the support substrate 2. The second conductive substrate 4B supports a plurality of second control terminals 35 among the plurality of control terminals 33, i.e., the second drive terminal 35A and a plurality of second detection terminals 35B and 35C. As shown in FIG. 18, the second conductive substrate 4B is bonded to the second conductor 24B via a bonding material 49.

[0070] 18 and 20, the conductive substrate 4 (each of the first conductive substrate 4A and the second conductive substrate 4B) has an insulating layer 41, a main surface metal layer 42, and a back surface metal layer 43. Unless otherwise specified, the insulating layer 41, the main surface metal layer 42, and the back surface metal layer 43 are configured in the same manner in the first conductive substrate 4A and the second conductive substrate 4B.

[0071] The insulating layer 41 is made of, for example, ceramic. This ceramic is, for example, AlN, SiN, or Al2O3. The insulating layer 41 has, for example, a rectangular shape in a plan view. As shown in FIG. 21 , the insulating layer 41 has a main surface 41a and a back surface 41b. The main surface 41a and the back surface 41b are spaced apart in the thickness direction z. The main surface 41a faces upward in the thickness direction z, and the back surface 41b faces downward in the thickness direction z. The main surface 41a and the back surface 41b are flat (or approximately flat).

[0072] As shown in FIG. 21 , the main surface metal layer 42 is formed on the main surface 41 a of the insulating layer 41. The plurality of control terminals 33 are each provided upright on the main surface metal layer 42. The constituent material of the main surface metal layer 42 is, for example, Cu or a Cu alloy. The constituent material may be Al or an Al alloy instead of Cu or a Cu alloy. The thickness of the main surface metal layer 42 (the dimension along the thickness direction z) is, for example, 200 μm or more and 500 μm or less. As shown in FIG. 7 , the main surface metal layer 42 includes a plurality of conductive portions 421 to 424.

[0073] The multiple conductive portions 421-424 are spaced apart from one another and insulated from one another. The thickness direction of each of the conductive portions 421-424 is the same as the thickness direction z. In each of the first conductive substrate 4A and the second conductive substrate 4B, the planar shape of the multiple conductive portions 421-424 is not limited to the example shown in the figure, and can be changed as appropriate depending on the specifications of the semiconductor device A1 (such as the arrangement of each semiconductor element 1 and the arrangement of the first power supply terminals 31 and second power supply terminals 32). The conductive portions 421-424 of the first conductive substrate 4A are an example of a "first conductive portion," and the conductive portions 421-424 of the second conductive substrate 4B are an example of a "second conductive portion."

[0074] A plurality of wires 651 are joined to the conductive portion 421, and the conductive portion 421 is electrically connected to the first principal surface electrode 11 (gate) of each semiconductor element 1 via each wire 651. As shown in Figures 7, 18, and 20, a first drive terminal 34A is joined to the conductive portion 421 of the first conductive substrate 4A, and a second drive terminal 35A is joined to the conductive portion 421 of the second conductive substrate 4B.

[0075] A plurality of wires 652 are joined to the conductive portion 422, and the conductive portion 422 is electrically connected to the second principal surface electrode 12 (source) of each semiconductor element 1 via each wire 652. As shown in Figures 7, 18 and 20, a first detection terminal 34B is joined to the conductive portion 422 of the first conductive substrate 4A, and a second detection terminal 35B is joined to the conductive portion 422 of the second conductive substrate 4B.

[0076] A wire 653 is joined to each of the pair of conductive portions 423, and the pair of conductive portions 423 are electrically connected to the third principal surface electrodes 13 of the semiconductor element 1 having the diode functional portion D1 via the wire 653. As shown in Figures 7, 18 and 20, each first detection terminal 34C is joined to each conductive portion 423 of the first conductive substrate 4A, and each second detection terminal 35C is joined to each conductive portion 423 of the second conductive substrate 4B.

[0077] As shown in Fig. 7, a wire 654 is joined to the conductive portion 424 of the first conductive substrate 4A, and electrical continuity is established with the first conductor 24A via the wire 654. As shown in Figs. 7 and 20, a first detection terminal 34D is joined to the conductive portion 424 of the first conductive substrate 4A. None of the plurality of wires 641 to 645 is joined to the conductive portion 424 of the second conductive substrate 4B. Furthermore, none of the plurality of control terminals 33 is joined to the conductive portion 424 of the second conductive substrate 4B.

[0078] In each of the first conductive substrate 4A and the second conductive substrate 4B, the plurality of conductive portions 421 to 424 each have a terminal bonding surface 420a, an opening 420b, and a through-hole 420c. The terminal bonding surface 420a, the opening 420b, and the through-hole 420c are formed in the same manner in each of the conductive portions 421 to 424 of the first conductive substrate 4A and the second conductive substrate 4B.

[0079] The terminal bonding surface 420a faces upward in the thickness direction z. The holders 331 of the control terminals 33 are bonded to the terminal bonding surface 420a via conductive bonding materials 63 (described later). The terminal bonding surface 420a is flat (or approximately flat).

[0080] The opening 420b is formed in the terminal bonding surface 420a. As shown in FIG. 8 , in a plan view, at least a portion of the outer peripheral edge of the opening 420b is inside the outer peripheral edge 331d of the holder 331. The outer peripheral edge 331d of the holder 331 is the outer peripheral edge of the edge of the holder 331 that is closer to the terminal bonding surface 420a in the thickness direction z. Therefore, in a configuration in which the holder 331 has a lower end flange 331c, the outer peripheral edge 331d of the holder 331 in a plan view is the outer peripheral edge of the lower end flange 331c in a plan view. In the semiconductor device A1, as shown in FIG. 8 , the opening 420b is formed so that its outer peripheral edge in a plan view is concentric with the outer peripheral edge 331d of the holder 331 in a plan view. Furthermore, as can be seen from FIGS. 8 and 21 , the entire outer peripheral edge of the opening 420b overlaps the lower end flange 331c in a plan view. The diameter r2 of the opening 420b in plan view (see FIG. 8) is, for example, not less than 0.8 mm and not more than 1.6 mm.

[0081] The through hole 420c is connected to the opening 420b and penetrates each of the conductive portions 421 to 424 from the opening 420b in the thickness direction z. As shown in FIG. 21 , a conductive bonding material 63 is partially formed in the through hole 420c, and the inner surface of the through hole 420c is in contact with the conductive bonding material 63. In the example shown in FIG. 21 , the inner surface of the through hole 420c is tapered in the thickness direction z from the side connected to the opening 420b to the side in contact with the insulating layer 41. Alternatively, the inner surface of the through hole 420c may not be tapered. By forming the through hole 420c in each of the conductive portions 421 to 424, as shown in FIG. 21 , the insulating layer 41 includes an exposed portion 410 that overlaps the through hole 420c in a plan view and is not covered by the main surface metal layer 42. The through hole 420c is an example of a "second through hole."

[0082] As shown in Fig. 21 , the back surface metal layer 43 is formed on the back surface 41b of the insulating layer 41. As shown in Figs. 14 , 20 and 21 , the back surface metal layer 43 of the first conductive substrate 4A is bonded to the first conductor 24A via a bonding material 49. As shown in Figs. 14 and 18 , the back surface metal layer 43 of the second conductive substrate 4B is bonded to the second conductor 24B via a bonding material 49.

[0083] The conductive member 5, together with the support substrate 2, forms a path for the main circuit current switched by the multiple semiconductor elements 1. The conductive member 5 is spaced apart from the support substrate 2 in the thickness direction z and overlaps the support substrate 2 in a plan view. The conductive member 5 is made of a metal plate-shaped member. The metal is, for example, Cu or a Cu alloy. The conductive member 5 is partially bent. The conductive member 5 includes multiple first conductive members 51 and second conductive members 52. The main circuit current includes a first main circuit current and a second main circuit current. The first main circuit current is a current flowing between the input terminal 31A and the output terminal 32A. The second main circuit current is a current flowing between the output terminal 32A and the input terminal 31B.

[0084] Each of the plurality of first conductive members 51 is bonded to the second main surface electrodes 12 (sources) of the plurality of first semiconductor elements 1A and the second conductors 24B, thereby electrically connecting the second main surface electrodes 12 of the plurality of first semiconductor elements 1A and the second conductors 24B. Each of the first conductive members 51 and the second main surface electrodes 12 of the plurality of first semiconductor elements 1A, and each of the first conductive members 51 and the second conductors 24B, are bonded via a conductive bonding material 591, as shown in FIG. 14 . The conductive bonding material 591 is, for example, solder, a metal paste material, or a sintered metal. Each of the first conductive members 51 is strip-shaped and extends in the first direction x in a plan view, as shown in FIG.

[0085] In the illustrated example, the number of first conductive members 51 corresponds to the number of first semiconductor elements 1A, and is three. In contrast to this configuration, for example, one first conductive member 51 may be shared by multiple first semiconductor elements 1A, regardless of the number of multiple first semiconductor elements 1A.

[0086] The second conductive member 52 electrically connects each second principal surface electrode 12 (source) of the plurality of second semiconductor elements 1B to each input terminal 31B. The second conductive member 52 has a maximum dimension in the first direction x of, for example, 25 mm to 40 mm (preferably 32 mm) and a maximum dimension in the second direction y of, for example, 30 mm to 45 mm (preferably 38 mm). Note that these dimensions of the second conductive member 52 are not limited to the above-described numerical example and can be changed as appropriate depending on the specifications of the semiconductor device A1. As shown in FIGS. 5 and 6 , the second conductive member 52 includes a pair of first wiring portions 521, second wiring portions 522, third wiring portions 523, and a plurality of fourth wiring portions 524.

[0087] One of the pair of first wiring portions 521 is connected to one of the pair of input terminals 31B, and the other of the pair of first wiring portions 521 is connected to the other of the pair of input terminals 31B. As shown in FIGS. 6 and 13 , each of the first wiring portions 521 and each of the input terminals 31B is bonded by a conductive bonding material 592. The conductive bonding material 592 is, for example, solder, a metal paste material, or a sintered metal. As shown in FIGS. 5 and 6 , each of the pair of first wiring portions 521 has a strip shape extending in the first direction x in a plan view. The pair of first wiring portions 521 are spaced apart in the second direction y and arranged parallel (or approximately parallel).

[0088] As shown in FIGS. 5 and 6 , the second wiring portion 522 is connected to both of the pair of first wiring portions 521. In plan view, the second wiring portion 522 is a strip-shaped portion extending in the second direction y. As can be seen from FIGS. 5 and 6 , the second wiring portion 522 overlaps multiple second semiconductor elements 1B in plan view. As shown in FIG. 17 , the second wiring portion 522 is connected to each second semiconductor element 1B. As shown in FIGS. 6 and 17 , the second wiring portion 522 has multiple recessed regions 522 a. As shown in FIG. 17 , each of the multiple recessed regions 522 a protrudes downward in the thickness direction z relative to other portions of the second wiring portion 522. As can be seen from FIG. 17 , each recessed region 522 a of the second wiring portion 522 and each second principal surface electrode 12 of the multiple second semiconductor elements 1B are bonded via a conductive bonding material 593. The conductive bonding material 593 may be, for example, solder, a metal paste material, or a sintered metal.

[0089] As shown in FIGS. 5 and 6 , the third wiring portion 523 is connected to both of the pair of first wiring portions 521. In plan view, the third wiring portion 523 has a strip shape extending in the second direction y. The third wiring portion 523 is spaced apart from the second wiring portion 522 in the first direction x. The third wiring portion 523 is arranged parallel (or approximately parallel) to the second wiring portion 522. The third wiring portion 523 overlaps multiple first semiconductor elements 1A in plan view. As shown in FIGS. 6 and 16 , the third wiring portion 523 has multiple convex regions 523a. As shown in FIG. 16 , each convex region 523a protrudes upward in the thickness direction z relative to other portions of the third wiring portion 523. As shown in FIG. 6 , each convex region 523a overlaps a corresponding first semiconductor element 1A in plan view. 16 , since the third wiring portion 523 has a plurality of convex regions 523a, regions for bonding each first conductive member 51 are provided on each first semiconductor element 1A. This makes it possible to prevent the third wiring portion 523 from coming into contact with each first conductive member 51.

[0090] As shown in FIGS. 5 and 6 , each of the multiple fourth wiring portions 524 is connected to both the second wiring portion 522 and the third wiring portion 523. Each of the multiple fourth wiring portions 524 has a strip shape extending in the first direction x in a plan view. The multiple fourth wiring portions 524 are spaced apart in the second direction y and arranged parallel (or approximately parallel) in a plan view. One end of each of the multiple fourth wiring portions 524 in the first direction x is connected to a portion of the third wiring portion 523 that overlaps between two first semiconductor elements 1A adjacent to each other in the second direction y in a plan view, and the other end of each of the multiple fourth wiring portions 524 in the first direction x is connected to a portion of the second wiring portion 522 that overlaps between two second semiconductor elements 1B adjacent to each other in the second direction y in a plan view.

[0091] As shown in FIGS. 5 to 7 , an opening 53 is formed in each of the pair of first wiring portions 521 of the second conductive member 52. Each opening 53 is a partially cut-out portion in plan view. In plan view, the opening 53 overlaps the first conductor 24A but does not overlap the first semiconductor element 1A. As shown in FIG. 13 , each opening 53 is, for example, a through-hole penetrating in the thickness direction z. In plan view, each opening 53 is provided in a portion that overlaps the vicinity of at least two corners of the first conductor 24A, and is, for example, provided on the side of each first wiring portion 521 closer to the first power terminal 31 in the first direction x. The planar shape of each opening 53 is not limited and may be a hole as in the examples of FIGS. 5 to 7 , or, unlike this example, a notch.

[0092] Each of the plurality of conductive bonding materials 61 bonds each semiconductor element 1 to the support substrate 2. The plurality of conductive bonding materials 61 includes a plurality of conductive bonding materials 61A and a plurality of conductive bonding materials 61B.

[0093] As shown in Figures 14 to 16, each of the plurality of conductive bonding materials 61A is interposed between the first conductor 24A and each of the first semiconductor elements 1A. Each of the plurality of conductive bonding materials 61A bonds each of the first semiconductor elements 1A to the first conductor 24A. As shown in Figures 14 and 17, each of the plurality of conductive bonding materials 61B is interposed between the second conductor 24B and each of the second semiconductor elements 1B. Each of the plurality of conductive bonding materials 61B bonds each of the second semiconductor elements 1B to the second conductor 24B.

[0094] 15 , each of the plurality of conductive bonding materials 61 (the plurality of conductive bonding materials 61, 61B) has a base layer 611, an upper layer 612, and a lower layer 613. In each of the conductive bonding materials 61 (each of the conductive bonding materials 61A, 61B), the base layer 611, the upper layer 612, and the lower layer 613 are stacked one on top of the other. Unless otherwise specified, the base layer 611, the upper layer 612, and the lower layer 613 are configured in the same manner in each of the conductive bonding materials 61 (each of the conductive bonding materials 61A, 61B).

[0095] The base layer 611 is made of metal, such as Al or an Al alloy, and is, for example, a sheet material.

[0096] The upper layer 612 is formed on the upper surface of the base layer 611, as shown in FIG. 15 . In the conductive bonding material 61A, the upper layer 612 is interposed between the base layer 611 and the first semiconductor element 1A, as shown in FIG. 15 . The upper layer 612 of the conductive bonding material 61A is bonded to the back electrode 15 of the first semiconductor element 1A, for example, by solid-state diffusion of metal. In the conductive bonding material 61B, the upper layer 612 is interposed between the base layer 611 and the second semiconductor element 1B. The upper layer 612 of the conductive bonding material 61B is bonded to the back electrode 15 of the second semiconductor element 1B, for example, by solid-state diffusion of metal. As a result, the upper layers 612 of the pair of conductive bonding materials 61A, 61B and the back electrodes 15 of the first semiconductor element 1A and the second semiconductor element 1B are bonded in direct contact with each other at the bonding interfaces.

[0097] As shown in FIG. 15 , the lower layer 613 is formed on the lower surface of the base layer 611. In the conductive bonding material 61A, the lower layer 613 is interposed between the base layer 611 and the first conductor 24A, as shown in FIG. 15 . The lower layer 613 of the conductive bonding material 61A is bonded to the main surface bonding layer 242 of the first conductor 24A, for example, by solid-state diffusion of metal. Similarly, in the conductive bonding material 61B, the lower layer 613 is interposed between the base layer 611 and the second conductor 24B. The lower layer 613 of the conductive bonding material 61B is bonded to the main surface bonding layer 242 of the second conductor 24B, for example, by solid-state diffusion of metal. As a result, the lower layers 613 of the pair of conductive bonding materials 61A, 61B and the main surface bonding layers 242 of the first conductor 24A and the second conductor 24B are bonded in direct contact with each other at the bonding interface.

[0098] Each conductive bonding material 61 (each conductive bonding material 61A, 61B) is not limited to the configuration having the above-mentioned base layer 611, upper layer 612 and lower layer 613, but may also be solder, metal paste material, sintered metal, or the like.

[0099] The plurality of conductive bonding materials 63 electrically connect each holder 331 of each control terminal 33 to the main surface metal layer 42 of each conductive substrate 4 (first conductive substrate 4A and second conductive substrate 4B). The plurality of conductive bonding materials 63 is, for example, solder. The plurality of conductive bonding materials 63 includes a plurality of conductive bonding materials 63A and a plurality of conductive bonding materials 63B.

[0100] 20, the conductive bonding material 63A bonds each of the plurality of first control terminals 34 (the first drive terminal 34A and the plurality of first detection terminals 34B to 34D) to the respective conductive portions 421 to 424 of the main surface metal layer 42 of the first conductive substrate 4A. In the semiconductor device A1, as shown in FIG. 20, the conductive bonding material 63A bonds the holder 331 of the first drive terminal 34A to the conductive portion 421 of the main surface metal layer 42 of the first conductive substrate 4A, the holder 331 of the first detection terminal 34B to the conductive portion 422 of the main surface metal layer 42 of the first conductive substrate 4A, the holder 331 of the pair of first detection terminals 34C to the respective conductive portion 423 of the main surface metal layer 42 of the first conductive substrate 4A, and the holder 331 of the first detection terminal 34D to the conductive portion 424 of the main surface metal layer 42 of the first conductive substrate 4A.

[0101] The conductive bonding material 63B bonds each of the plurality of second control terminals 35 (the second drive terminal 35A and the plurality of second detection terminals 35B, 35C) to the respective conductive portions 421 to 424 of the main surface metal layer 42 of the second conductive substrate 4B. In the semiconductor device A1, as shown in Fig. 18 , the conductive bonding material 63B bonds the holder 331 of the second drive terminal 35A to the conductive portion 421 of the main surface metal layer 42 of the second conductive substrate 4B, bonds the second detection terminal 35B to the conductive portion 422 of the main surface metal layer 42 of the second conductive substrate 4B, and bonds the pair of second detection terminals 35C to the respective conductive portions 423 of the main surface metal layer 42 of the second conductive substrate 4B.

[0102] As shown in FIG. 15 , at least a portion of each of the plurality of conductive bonding materials 63 is sandwiched in the thickness direction z between the holder 331 (lower end flange 331c) of each control terminal 33 and the main surface metal layer 42 (each of the conductive portions 421-424) of the conductive substrate 4 (each of the first conductive substrate 4A and the second conductive substrate 4B). The thickness (dimension in the thickness direction z) of this sandwiched portion is, for example, 20 μm to 70 μm. Within this range, a suitable thinness can be ensured while ensuring a suitable bonding strength. As shown in FIG. 15 , in a plan view, the outer peripheral edges of each of the plurality of conductive bonding materials 63 are located outward from the outer peripheral edge 331d of the holder 331 of each control terminal 33.

[0103] In the example shown in FIG. 21 , each of the plurality of conductive bonding materials 63 (the plurality of conductive bonding materials 63A and the plurality of conductive bonding materials 63B) includes an inlet portion 631 and a filling portion 632. The inlet portion 631 is a portion of each conductive bonding material 63 formed within the through-hole 332 of the holder 331. For example, as shown in FIG. 21 , the upper surface of the inlet portion 631 has an arc shape when viewed in a direction perpendicular to the thickness direction z (e.g., the first direction x) and curves downward in the thickness direction z. Alternatively, the upper surface of the inlet portion 631 may be flat. The shape of the upper surface of the inlet portion 631 may be arc-shaped or flat depending on the type of surface treatment of the holder 331 and the type of conductive bonding material 63 (solder). The ratio (h1 / r1 × 100) of the dimension h1 of the inlet portion 631 in the thickness direction z to the inner diameter of the holder 331 (the diameter r1 of the through-hole 332) is, for example, 10% or more and 65% or less. The dimension h1 of the inlet portion 631 in the thickness direction z is, for example, 100 μm or more and 500 μm or less. The filling portion 632 is a portion of each conductive bonding material 63 formed inside the through hole 420c. The lower surface of the filling portion 632 is curved in an arc shape. The configuration of the conductive bonding material 63 shown in FIG. 21 is an example in which the diameter r2 of the opening 420b in a plan view is, for example, 0.8 mm.

[0104] In the semiconductor device A1, the conductive bonding materials 63 are solder and the insulating layers 41 of the first conductive substrate 4A and the second conductive substrate 4B are ceramic. Therefore, the insulating layers 41 have low affinity (low wettability) for the conductive bonding materials 63. Therefore, as shown in FIG. 21 , a gap 630 is formed between the conductive bonding materials 63 and the insulating layers 41. This is because the insulating layers 41 have low affinity for the conductive bonding materials 63, making it difficult for the conductive bonding materials 63 to come into contact with the insulating layers 41, and the gap 630 remains after the conductive bonding materials 63 harden. Due to this gap 630, at least a portion of the exposed portion 410 of the insulating layer 41 is not in contact with the conductive bonding materials 63, as shown in FIG.

[0105] In addition, in the semiconductor device A1, the conductive bonding materials 63 are solder and the main surface metal layers 42 of the first conductive substrate 4A and the second conductive substrate 4B are Cu or a Cu alloy, so that the main surface metal layers 42 have a high affinity (high wettability) for the conductive bonding materials 63. Therefore, as shown in FIG. 21 , the conductive bonding materials 63 contact the inner surfaces of the through holes 420c.

[0106] Furthermore, in the semiconductor device A1, since each conductive bonding material 63 is solder and each holder 331 of the plurality of control terminals 33 is made of Cu or a Cu alloy, each holder 331 has a high affinity (high wettability) for each conductive bonding material 63. Therefore, as shown in Fig. 21, each conductive bonding material 63 flows into the through-hole 332 of each holder 331, forming an inflow portion 631. However, depending on the amount of each conductive bonding material 63 and the volume of each through-hole 420c, the inflow portion 631 may not be formed.

[0107] Each of the wires 651 to 654 electrically connects two separate portions. Each of the wires 651 to 654 is, for example, a bonding wire. The material of each of the wires 651 to 654 includes, for example, gold (Au), aluminum, or copper.

[0108] The plurality of wires 651 include a plurality of first wires 651A and a plurality of second wires 651B. As shown in Fig. 7 , the plurality of first wires 651A are each bonded to the first main surface electrode 11 (gate) of each first semiconductor element 1A and the conductive portion 421 of the main surface metal layer 42 of the first conductive substrate 4A, thereby providing electrical continuity therebetween. As shown in Fig. 7 , the plurality of second wires 651B are each bonded to the first main surface electrode 11 (gate) of each second semiconductor element 1B and the conductive portion 421 of the main surface metal layer 42 of the second conductive substrate 4B, thereby providing electrical continuity therebetween.

[0109] The plurality of wires 652 include a plurality of first wires 652A and a plurality of second wires 652B. As shown in FIG. 7 , the plurality of first wires 652A are each bonded to the second main surface electrode 12 (source) of each first semiconductor element 1A and the conductive portion 422 of the main surface metal layer 42 of the first conductive substrate 4A, thereby establishing electrical continuity therebetween. As shown in FIG. 7 , the plurality of second wires 652B are each bonded to the second main surface electrode 12 (source) of each second semiconductor element 1B and the conductive portion 422 of the main surface metal layer 42 of the second conductive substrate 4B, thereby establishing electrical continuity therebetween. Note that if each semiconductor element 1 has an additional electrode serving as a source sense, the first wires 652A and the second wires 652B are bonded to the additional electrode serving as a source sense, instead of the second main surface electrode 12 (source).

[0110] The multiple wires 653 include a pair of first wires 653A and a pair of second wires 653B. As shown in Fig. 7 , the pair of first wires 653A are each bonded to the third main surface electrodes 13 of the first semiconductor element 1A having the diode functional portion D1 and the conductive portions 423 of the main surface metal layer 42 of the first conductive substrate 4A, thereby providing electrical continuity therebetween. As shown in Fig. 7 , the pair of second wires 654B are each bonded to the third main surface electrodes 13 of the second semiconductor element 1B having the diode functional portion D1 and the conductive portions 423 of the main surface metal layer 42 of the second conductive substrate 4B, thereby providing electrical continuity therebetween.

[0111] As shown in FIG. 7, the wire 654 is joined to the first conductor 24A and the conductive portion 424 of the first conductive substrate 4A, thereby establishing electrical continuity therebetween.

[0112] The resin member 7 covers the semiconductor elements 1, a portion of the support substrate 2, a portion of each of the first and second power terminals 31 and 32, the conductive substrate 4 (the first conductive substrate 4A and the second conductive substrate 4B), the conductive members 5 (the first conductive members 51 and the second conductive members 52), the conductive bonding materials 61 and 63, and the wires 651 to 654. The resin member 7 is made of, for example, an insulating resin material. This resin material is, for example, epoxy resin. The resin member 7 is formed, for example, by molding. The resin member 7 has, for example, a dimension in the first direction x of 35 mm to 60 mm, a dimension in the second direction y of 35 mm to 50 mm, and a dimension in the thickness direction z of 4 mm to 15 mm. These dimensions are the sizes of the largest portions along each direction. The dimensions of the resin member 7 are not limited to the above example and can be changed as appropriate depending on the specifications of the semiconductor device A1. The resin member 7 has a resin main surface 71, a resin back surface 72, and a plurality of resin side surfaces 731 to 734.

[0113] As shown in Figures 9, 11, and 12, the resin main surface 71 and the resin back surface 72 are spaced apart in the thickness direction z. The resin main surface 71 faces upward in the thickness direction z, and the resin back surface 72 faces downward in the thickness direction z. A plurality of control terminals 33 (a first drive terminal 34A, a plurality of first detection terminals 34B to 34D, a second drive terminal 35A, and a plurality of second detection terminals 35B and 35C) protrude from the resin main surface 71. As shown in Figure 10, the resin back surface 72 has a frame shape in plan view that surrounds the lower surface (the surface facing downward in the thickness direction z) of the main surface metal layer 42 of the conductive substrate 4. The lower surface of the main surface metal layer 42 is exposed from the resin back surface 72. For example, the resin back surface 72 is flush with the lower surface of the main surface metal layer 42. Each of the multiple resin side surfaces 731 to 734 is connected to both the resin main surface 71 and the resin back surface 72 and is sandwiched between them in the thickness direction z. As shown in FIGS. 4 , 9 , and 10 , the resin side surfaces 731 and 732 are spaced apart in the first direction x. The resin side surface 732 faces one side of the first direction x, and the resin side surface 731 faces the other side of the first direction x. Two output terminals 32A (second power supply terminals 32) protrude from the resin side surface 731, and three input terminals 31A and 31B (first power supply terminals 31) protrude from the resin side surface 732. As shown in FIGS. 4 , 10 to 12 , the resin side surfaces 733 and 734 are spaced apart in the second direction y. The resin side surface 734 faces one side of the second direction y, and the resin side surface 733 faces the other side of the second direction y.

[0114] As shown in FIGS. 4 and 10 , a plurality of recesses 732 a are formed on the resin side surface 732. Each recess 732 a is a portion recessed in the first direction x in a plan view. In a plan view, the plurality of recesses 732 a include one formed between the input terminal 31A and one of the pair of input terminals 31B and one formed between the input terminal 31A and the other of the pair of input terminals 31B. The plurality of recesses 732 a are provided to increase the creepage distance along the resin side surface 732 between the input terminal 31A and one of the pair of input terminals 31B and the creepage distance along the resin side surface 732 between the input terminal 31A and the other of the pair of input terminals 31B.

[0115] As shown in FIGS. 13 and 14 , the resin member 7 has a plurality of first protrusions 751 , a plurality of second protrusions 752 , and a resin void 76 .

[0116] As shown in FIG. 13 , each of the multiple first protrusions 751 protrudes from the resin main surface 71 in the thickness direction z. The multiple first protrusions 751 are arranged near the four corners of the resin member 7 in a plan view. As shown in FIG. 13 , a first protrusion end surface 751 a is formed at the tip (the upper end in the thickness direction z) of each first protrusion 751. Each of the multiple first protrusions 751 has a bottomed, hollow, truncated conical shape, for example. The multiple first protrusions 751 are used as spacers when the semiconductor device A1 is mounted on a control circuit board or other device that uses power generated by the semiconductor device A1. The shape of each first protrusion 751 may be columnar, preferably cylindrical.

[0117] As shown in FIG. 14 and other figures, the multiple second protrusions 752 protrude from the resin main surface 71 in the thickness direction z. In a plan view, the multiple second protrusions 752 overlap the multiple control terminals 33. The metal pins 333 of the multiple control terminals 33 protrude from each second protrusion 752. A portion of the holder 331 (the upper surface of the upper end flange 331b) is exposed from the upper end surface of each second protrusion 752. Each second protrusion 752 has a truncated cone shape. A resin portion 77 is disposed on each second protrusion 752.

[0118] 14 and other figures, the resin portion 77 is provided on the second protruding portion 752 of the resin member 7. In each control terminal 33, the resin portion 77 covers a portion of the holder 331 (the upper surface of the upper end flange 331b) exposed from the resin member 7 and a portion of the metal pin 333. The resin portion 77 is made of, for example, an insulating resin material (e.g., epoxy resin) similar to the resin member 7, but may be made of a material different from that of the resin member 7. The resin portion 77 is formed by, for example, resin potting after the metal pin 333 is inserted into the holder 331.

[0119] 13, the resin void portion 76 communicates with the recess 240a from the resin main surface 71 in the thickness direction z. The resin void portion 76 is formed in a tapered shape such that the cross-sectional area decreases from the resin main surface 71 toward the recess 240a in the thickness direction z.

[0120] The resin filling portion 78 fills the resin void portion 76 so as to fill the resin void portion 76. The resin filling portion 78 is made of an insulating resin material (e.g., epoxy resin) similar to the resin member 7, but may be made of a material different from that of the resin member 7. The resin filling portion 78 is formed by, for example, resin potting. The lower edge of the resin filling portion 78 in the thickness direction z contacts the recesses 240a of the first conductor 24A and the second conductor 24B.

[0121] The semiconductor device A1 has the following functions and effects.

[0122] The semiconductor device A1 has a bonding structure including a conductive substrate 4 (first conductive substrate 4A or second conductive substrate 4B), a control terminal 33, and a conductive bonding material 63. The conductive substrate 4 (first conductive substrate 4A or second conductive substrate 4B) has conductive portions 421 to 424. The control terminal 33 includes a holder 331 and a metal pin 333. The conductive bonding material 63 bonds each of the conductive portions 421 to 424 to the control terminal 33. The holder 331 has a through-hole 332. The through-hole 332 penetrates the holder 331 in the thickness direction z, and a portion (straight portion 333a) of the metal pin 333 is inserted into the through-hole 332. Each of the conductive portions 421 to 424 has a terminal bonding surface 420a to which the holder 331 is bonded, and an opening 420b formed in the terminal bonding surface 420a. In a configuration different from this joining structure, in which openings 420b are not formed in each of the conductive portions 421 to 424, the conductive bonding material 63 flows into the through holes 332 when joining the holder 331 to each of the conductive portions 421 to 424, which can prevent a sufficient amount of terminal insertion. On the other hand, in the joining structure of the semiconductor device A1, the openings 420b suppress the amount of conductive bonding material 63 flowing into the through holes 332. This makes it possible to ensure an appropriate amount of insertion of the metal pins 333 into the holder 331. As a result, the joining structure of the semiconductor device A1 allows the metal pins 333 to be appropriately inserted into the holder 331, thereby preventing the metal pins 333 from coming off the holder 331. For example, if the dimension d1 (see Figure 21) of the straight portion 333a of the metal pin 333 in the thickness direction z is 20% or more and 90% or less (preferably 60% or more and 85% or less) of the dimension of the holder 331 in the thickness direction z, it can be said that the metal pin 333 is properly inserted into the holder 331.

[0123] The inventors of the present application simulated the amount of conductive bonding material 63 creeping up into the through hole 332 when the diameter r2 of the opening 420b was 0.8 mm and the inner diameter of the holder 331 (the diameter r1 of the through hole 332) was 0.74 mm. The amount of creeping up corresponds to the dimension h1 (see FIG. 21 ) of the inflow portion 631 in the thickness direction z. As a result, when the opening 420b was not provided, the amount of creeping up of the conductive bonding material 63 was 500 μm or more, whereas when the opening 420b was provided, the amount of creeping up was 450 μm or less. In other words, it was confirmed that providing the opening 420b suppressed the amount of conductive bonding material 63 creeping up into the holder 331 (the through hole 332).

[0124] In the bonding structure of the semiconductor device A1, at least a portion of the outer peripheral edge of the opening 420b is located inside the outer peripheral edge 331d of the holder 331 in a plan view. As described above, the outer peripheral edge 331d is the outer peripheral edge of the lower edge of the holder 331 in the thickness direction z. With this configuration, at least a portion of the lower end of the holder 331 in the thickness direction z faces the terminal bonding surface 420a, and therefore the lower end does not enter the opening 420b. If the lower end of the holder 331 in the thickness direction z were to enter the opening 420b, the amount of the conductive bonding material 63 creeping up into the through hole 332 would increase, and it may be impossible to ensure an appropriate amount of insertion of the metal pin 333 into the holder 331. Therefore, in the bonding structure of the semiconductor device A1, the lower end of the holder 331 in the thickness direction z does not enter the opening 420b, so the amount of the conductive bonding material 63 creeping up into the through hole 332 is suppressed, and the amount of insertion of the metal pin 333 into the holder 331 can be ensured to be appropriate.

[0125] In the bonding structure of the semiconductor device A1, the holder 331 includes a cylindrical portion 331a and a lower flange 331c. For example, in a plan view, the entire outer periphery of the lower flange 331c is located further outward than the outer periphery of the cylindrical portion 331a. This configuration increases the volume of the through-hole 420c connecting to the opening 420b while preventing the lower end of the holder 331 in the thickness direction z from entering the opening 420b. In other words, this configuration is effective in preventing the amount of conductive bonding material 63 creeping up into the through-hole 332.

[0126] In the bonding structure of semiconductor device A1, each conductive bonding material 63 includes an inflow portion 631 formed in through hole 332 of holder 331. With this configuration, conductive bonding material 63 can increase the bonding strength between holder 331 and each conductive portion 421-424 by means of inflow portion 631. In particular, in the bonding structure of semiconductor device A1, the ratio (h1 / r1×100) of the dimension h1 of inflow portion 631 in the thickness direction z to the diameter r1 of through hole 332 is 10% or more and 65% or less. With this configuration, since this ratio is 10% or more, the bonding strength is increased, while since this ratio is 65% or less, the insertion amount of metal pin 333 into holder 331 can be appropriately ensured.

[0127] In the bonding structure of the semiconductor device A1, in a plan view, the outer periphery of each conductive bonding material 63 is located outward from the outer periphery 331d of the holder 331 of each control terminal 33. With this configuration, in the thickness direction z, the conductive bonding material 63 is interposed between the lower end flange 331c of each holder 331 and the terminal bonding surface 420a of each conductive portion 421 to 424. Therefore, the holder 331 of each control terminal 33 is appropriately bonded to each conductive portion 421 to 424.

[0128] In the semiconductor device A1, the multiple control terminals 33 are connected to a control system circuit board on which the semiconductor device A1 is mounted. In this case, the control system circuit board may be disposed, for example, above the semiconductor device A1 in the thickness direction z. Furthermore, the first power supply terminal 31 (multiple input terminals 31A, 31B) and the second power supply terminal 32 (two output terminals 32A) are connected to a power system circuit board on which the semiconductor device A1 is mounted. In this case, the power system circuit board may be disposed, for example, adjacent to the semiconductor device A1 in the first direction x. In this configuration, the power system circuit board to which the first power supply terminal 31 and the second power supply terminal 32 are connected can be disposed apart from the control system circuit board to which each control terminal 33 (metal pins 333) is connected in the thickness direction z. These features, first, improve the degree of freedom in arranging the signal terminals in the semiconductor device A1. Second, improve the degree of freedom in routing and length of signal wiring in the semiconductor device A1. Third, improve the degree of freedom in arranging the circuit board when using the semiconductor device A1.

[0129] Next, other configuration examples of the joint structure of the present disclosure will be described with reference to FIGS.

[0130] 23 shows a structural example in which the diameter r2 of the opening 420b in the semiconductor device A1 is larger than the diameter r2 of the opening 420b in the bonding structure between each of the conductive portions 421-424 and each of the control terminals 33. FIG. 23 is an enlarged cross-sectional view of a main portion corresponding to FIG. 21. FIG. 23 shows an example of the conductive bonding material 63 in which the diameter r2 of the opening 420b in plan view is, for example, approximately 1.6 mm. In the example shown in FIG. 23, the void 630 is connected to the through hole 332, so that the conductive bonding material 63 does not include the inflow portion 631. This is because the larger diameter r2 of the opening 420b increases the volume of the through hole 420c.

[0131] FIG. 24 shows a structural example in which recesses 420d are provided in each of the conductive portions 421-424 instead of through holes 420c in the bonding structure between each of the conductive portions 421-424 and each of the control terminals 33. FIG. 24 is an enlarged cross-sectional view of a main portion corresponding to FIG. 21. As shown in FIG. 24, the recesses 420d are connected to the openings 420b, similar to the through holes 420c. The depth of the recesses 420d is, for example, 50 μm or more and 200 μm or less. The depth of the recesses 420d is the dimension along the thickness direction z from the terminal bonding surface 420a to the bottom of the recesses 420d. For example, if the dimension of each of the conductive portions 421-424 in the thickness direction z (the thickness of the main surface metal layer 42) is large, the recesses 420d may be formed instead of the through holes 420c. This is because the recesses 420d can still provide an appropriate volume. For example, when the thickness of the main surface metal layer 42 (the dimension of each of the conductive portions 421 to 424 in the thickness direction z) is 200 μm or more, the depression 420d may be formed. In the example shown in Fig. 24, the conductive bonding material 63 does not contact the insulating layer 41, and therefore the filling portion 632 fills the entire depression 420d. In other words, in the joint structure shown in Fig. 24, no void 630 is formed.

[0132] 25 to 30 show configuration examples in which the shape of the opening 420b in plan view is different in the joint structure between each of the conductive portions 421 to 424 and each of the control terminals 33. Figures 25 to 30 are enlarged views of the main part corresponding to Figure 8. However, in Figures 25 to 30, the holder 331 of each of the control terminals 33 is shown by imaginary lines, and the metal pin 333 of each of the control terminals 33 and each of the conductive bonding materials 63 are omitted.

[0133] 25, the opening 420b of each of the conductive portions 421 to 424 overlaps the through hole 332 in plan view. That is, the diameter r2 of the opening 420b in plan view is smaller in the junction structure shown in FIG. 25 than in the junction structure in the semiconductor device A1.

[0134] 26, the openings 420b of the conductive portions 421 to 424 are formed in an elliptical shape in a plan view, and part of the outer periphery of the openings 420b is located outside the outer periphery 331d of the holder 331 in a plan view. In the example shown in Fig. 26, the longitudinal direction of the openings 420b in a plan view is aligned with the first direction x, but, unlike this configuration, the longitudinal direction may be aligned with any direction perpendicular to the thickness direction z.

[0135] In the example shown in FIG. 27, the openings 420b of the conductive portions 421 to 424 are formed in a rectangular shape in plan view.

[0136] In the example shown in Fig. 28, similar to the example shown in Fig. 27, the openings 420b of the conductive portions 421 to 424 are formed in a rectangular shape in plan view, but unlike the example shown in Fig. 27, part of the outer periphery of the openings 420b is located outward from the outer periphery 331d of the holder 331 in plan view. In the example shown in Fig. 28, the longitudinal direction of the openings 420b in plan view is aligned with the first direction x, but unlike this configuration, the longitudinal direction may be aligned with any direction perpendicular to the thickness direction z.

[0137] 29, each of the conductive portions 421 to 424 has a plurality of openings 420b, and the plurality of openings 420b are each formed linearly in a plan view. In each of the conductive portions 421 to 424, the plurality of openings 420b each extend in the second direction y and are arranged parallel to one another. In the example shown in FIG. 29, each of the plurality of openings 420b extends along the second direction y, but each may extend along any direction perpendicular to the thickness direction z.

[0138] In the example shown in Figure 30, the openings 420b of each of the conductive portions 421 to 424 are formed in a lattice pattern in plan view, with two stripes extending along the first direction x and two stripes extending along the second direction y intersecting each other. Unlike the example shown in Figure 30, the number of stripes extending along the first direction x and the number of stripes extending along the second direction y may each be three or more. Note that, in plan view, the stripes extending along the first direction x and the stripes extending along the second direction y are not limited to being orthogonal to each other as shown in Figure 30, as long as they intersect.

[0139] 23 to 30, similar to the joint structure between each of the conductive portions 421 to 424 and each of the control terminals 33 in the semiconductor device A1, in a plan view, at least a portion of the outer periphery of the opening 420b is located inside the outer periphery 331d of the holder 331. Therefore, it is possible to prevent the conductive bonding material 63 from creeping up into the through hole 332, and to ensure an appropriate insertion amount of the metal pin 333 into the holder 331.

[0140] In the semiconductor device A1, the multiple control terminals 33 include holders 331 and metal pins 333. However, both or one of the first power supply terminals 31 and second power supply terminals 32 may be configured similarly to the control terminals 33. For example, in the semiconductor device A1, the second power supply terminals 32 (each output terminal 32A) may include a holder and metal pin similar to the holders 331 and metal pins 333 of each control terminal 33. FIG. 31 illustrates a semiconductor device according to such a modification. In the example shown in FIG. 31 , the holders of each output terminal 32A are joined to, for example, the second conductor 24B. In this case, a through hole or recess similar to the through hole 420c or recess 420d may be formed in the portion of the second conductor 24B where the holders of each output terminal 32A are joined. Note that, as shown in FIG. 31 , because main circuit current flows through the first power supply terminals 31 and second power supply terminals 32, it is preferable that the metal pins be thicker than the metal pins 333 of the multiple control terminals 33. As described above, the joining structure of the present disclosure is not limited to signal terminals, but can also be applied to power terminals.

[0141] Although the junction structure of the present disclosure has been shown as being applied to a semiconductor device including a switching element, it can also be applied to a semiconductor device including a semiconductor element other than a switching element (e.g., a diode) or an electronic device including an electronic component other than a semiconductor element (e.g., a resistor, an inductor, a transformer, a capacitor, an integrated circuit, etc.).

[0142] The joining structure and semiconductor device according to the present disclosure are not limited to the above-described embodiments. The specific configurations of each part of the joining structure and semiconductor device according to the present disclosure can be freely designed in various ways. For example, the present disclosure includes the embodiments described in the following appendices. Appendix 1. A joining structure comprising: a conductive substrate having a conductive portion; a cylindrical holder having conductivity and a terminal including a metal pin inserted into the holder; and a conductive bonding material bonding the conductive portion and the holder, wherein the metal pin includes a straight portion extending along the thickness direction of the conductive portion, the holder has a first through hole extending in the thickness direction and into which the straight portion of the metal pin is inserted, the conductive portion has a terminal bonding surface to which the holder is bonded and an opening formed in the terminal bonding surface, and at least a portion of the outer periphery of the opening is located inside the outer periphery of the holder when viewed in the thickness direction. Appendix 2. The joining structure according to Supplementary Note 1, wherein the holder includes a cylindrical portion and an upper end flange and a lower end flange arranged on either side of the cylindrical portion in the thickness direction, the first through hole straddling the cylindrical portion, the upper end flange, and the lower end flange in the thickness direction, and the lower end flange being joined to the conductive portion.Supplementary Note 3. The joining structure according to Supplementary Note 2, wherein the outer circumferential edge of the holder is the outer circumferential edge of the lower end flange when viewed in the thickness direction.Supplementary Note 4. The joining structure according to Supplementary Note 3, wherein the entire outer circumferential edge of the opening overlaps the lower end flange when viewed in the thickness direction.Supplementary Note 5. The joining structure according to any one of Supplementary Notes 2 to 4, wherein the cylindrical portion and the first through hole are each circular when viewed in the thickness direction.Supplementary Note 6. The joining structure according to Supplementary Note 5, wherein the conductive bonding material includes an inflow portion formed in the first through hole, and the inflow portion continues in the thickness direction from a side of the holder where the conductive portion is located.Supplementary Note 7. The joining structure according to Supplementary Note 6, wherein a ratio of a dimension of the inflow portion in the thickness direction to a diameter of the first through hole is 10% or more and 65% or less.Supplementary Note 8. The joining structure according to any one of Supplementary Notes 1 to 7, wherein an outer peripheral edge of the conductive bonding material is located outward from the outer peripheral edge of the holder when viewed in the thickness direction.Appendix 9. The joining structure according to any one of Appendixes 1 to 8, wherein the conductive portion includes a second through hole connected to the opening, and the conductive bonding material is in contact with an inner surface of the second through hole. Appendix 10. The joining structure according to Appendix 9, wherein the conductive substrate includes an insulating layer, the conductive portion is laminated on one side of the insulating layer in the thickness direction, the insulating layer includes an exposed portion overlapping the second through hole when viewed in the thickness direction, and at least a portion of the exposed portion is not in contact with the conductive bonding material. Appendix 11. The joining structure according to any one of Appendixes 1 to 8, wherein the conductive portion includes a recess connected to the opening. Appendix 12. The joining structure according to Appendix 11, wherein the conductive bonding material includes a filling portion formed in the recess. Appendix 13. A semiconductor device comprising the joining structure according to any one of Appendixes 1 to 12, and a semiconductor element electrically connected to the terminal. Appendix 14. The semiconductor device according to Appendix 13, wherein the terminal is a control terminal for controlling the semiconductor element. Appendix 15. The semiconductor device according to Appendix 14, further comprising a first power supply terminal and a second power supply terminal, each electrically connected to the semiconductor element, wherein a first power supply voltage is input to the first power supply terminal, and a second power supply voltage is input to the second power supply terminal. the semiconductor device according to Appendix 15, further comprising a first conductor and a second conductor spaced apart from each other in a first direction perpendicular to the thickness direction; the semiconductor element includes a first semiconductor element bonded to the first conductor and a second semiconductor element bonded to the second conductor; the conductive substrate includes a first conductive substrate bonded to the first conductor and a second conductive substrate bonded to the second conductor; the conductive portion includes a first conductive portion of the first conductive substrate and a second conductive portion of the second conductive substrate; the first power supply terminal includes a first input terminal connected to the first conductor and a second input terminal connected to the second semiconductor element; the second power supply terminal is an output terminal connected to the second conductor; and the control terminal includes a first control terminal bonded to the first conductive portion and controlling the first semiconductor element, and a second control terminal bonded to the second conductive portion and controlling the second semiconductor element.Appendix 17. The semiconductor device according to Appendix 16, wherein each of the first semiconductor element and the second semiconductor element is a switching element that performs a switching operation, the first control terminal includes a first drive terminal for controlling the switching operation of the first semiconductor element and a first detection terminal for detecting a conductive state of the first semiconductor element, and the second control terminal includes a second drive terminal for controlling the switching operation of the second semiconductor element and a second detection terminal for detecting a conductive state of the second semiconductor element. Appendix 18. The semiconductor device according to Appendix 16 or Appendix 17, further comprising a resin member that covers each of a portion of the first control terminal and a portion of the second control terminal, the first conductive substrate and the second conductive substrate, and the first semiconductor element and the second semiconductor element, and each of the first control terminal and the second control terminal protrudes from the resin member in the thickness direction. Appendix 19. 19. The semiconductor device of claim 18, wherein the resin member has a resin main surface and a resin back surface spaced apart in the thickness direction, and a resin side surface sandwiched between the resin main surface and the resin back surface in the thickness direction, the resin side surface facing the first direction, and the first power supply terminal and the second power supply terminal protruding in the first direction from the resin side surface.

[0143] A1: semiconductor device 1: semiconductor element 1A: first semiconductor element 1B: second semiconductor element 10a: element main surface 10b: element back surface 11: first main surface electrode 12: second main surface electrode 13: third main surface electrode 15: back surface electrode Q1: switching function section D1: diode function section D2: diode 2: supporting substrate 21: insulating layer 21a: main surface 21b: back surface 22: main surface metal layer 22A: first support section 22B: second support section 221: bonding layer 23: back surface metal layer 24A: first conductor 24B: second conductor 240a: recess 241: substrate 242: main surface bonding layer 243: back surface bonding layer 25A, 25B: conductive bonding material 251: base layer 252: upper layer 253: lower layer 31: first power supply terminal 31A: Input terminal 31B: Input terminal 32: Second power supply terminal 32A: Output terminal 33: Control terminal 331: Holder 331a: Cylindrical portion 331b: Upper flange 331c: Lower flange 331d: Outer rim 332: Through hole 333: Metal pin 333a: Straight portion 34: First control terminal 34A: First drive terminal 34B, 34C, 34D: First detection terminal 35: Second control terminal 35A: Second drive terminal 35B, 35C: Second detection terminal 4: Conductive substrate 4A: First conductive substrate 4B: Second conductive substrate 41: Insulating layer 41a: Main surface 41b: Back surface 410: Exposed portion 42: Main surface metal layer 420a: Terminal bonding surface 420b: Opening 420c: Through hole 420d: Depression 421, 422, 423, 424: Conductive portion 43: Back surface metal layer 49: Bonding material 5: Conductive member 51: First conductive member 52: Second conductive member 521: First wiring portion 522: Second wiring portion 522a: Recessed region 523: Third wiring portion 523a: Convex region 524: Fourth wiring portion 53: Opening 591, 592, 593: Conductive bonding material 61, 61A, 61B: Conductive bonding material 611: Base layer 612: Upper layer 613: Lower layer 63, 63A,63B: Conductive bonding material 630: Gap 631: Inflow portion 632: Filling portion 651: Wire 651A: First wire 651B: Second wire 652: Wire 652A: First wire 652B: Second wire 653: Wire 653A: First wire 653B: Second wire 654: Wire 654B: Second wire 7: Resin member 71: Resin main surface 72: Resin back surface 731 to 734: Resin side surface 732a: Recess 751: First protruding portion 751a: First protruding end surface 752: Second protruding portion 76: Resin void portion 77: Resin portion 78: Resin filling portion,

Claims

1. A conductive substrate having a conductive portion; a conductive cylindrical holder and a terminal including a metal pin inserted into the holder; a conductive bonding material that bonds the conductive portion and the holder; It is equipped with the metal pin includes a straight portion extending along a thickness direction of the conductive portion, the holder has a first through hole extending in the thickness direction and into which the straight portion of the metal pin is inserted; the conductive portion has a terminal bonding surface to which the holder is bonded and an opening formed in the terminal bonding surface, A joining structure in which, when viewed in the thickness direction, at least a portion of the outer circumferential edge of the opening is located inside the outer circumferential edge of the holder.

2. the holder includes a cylindrical portion, and an upper end flange portion and a lower end flange portion disposed on either side of the cylindrical portion in the thickness direction; the first through hole extends across the cylindrical portion, the upper end flange portion, and the lower end flange portion in the thickness direction; The joint structure according to claim 1 , wherein the lower end flange portion is joined to the conductive portion.

3. The joining structure according to claim 2 , wherein the outer peripheral edge of the holder is an outer peripheral edge of the lower end flange portion when viewed in the thickness direction.

4. The joining structure according to claim 3 , wherein the entire outer circumferential edge of the opening overlaps with the lower end flange portion when viewed in the thickness direction.

5. The joining structure according to claim 2 , wherein each of the cylindrical portion and the first through hole is circular when viewed in the thickness direction.

6. the conductive bonding material includes an inlet portion formed in the first through hole, The joint structure according to claim 5 , wherein the inflow portion is connected in the thickness direction from a side of the holder where the conductive portion is located.

7. The joining structure according to claim 6 , wherein a ratio of a dimension of the inflow portion in the thickness direction to a diameter of the first through hole is 10% or more and 65% or less.

8. The joint structure according to claim 1 , wherein an outer periphery of the conductive joint material is located outward from an outer periphery of the holder when viewed in the thickness direction.

9. the conductive portion includes a second through hole communicating with the opening, The joint structure according to claim 1 , wherein the conductive joint material is in contact with an inner surface of the second through hole.

10. the conductive substrate includes an insulating layer; the conductive portion is laminated on one side of the insulating layer in the thickness direction, the insulating layer includes an exposed portion overlapping the second through hole when viewed in the thickness direction, The joint structure according to claim 9 , wherein at least a part of the exposed portion is not in contact with the conductive joint material.

11. The junction structure according to claim 1 , wherein the conductive portion includes a recess that is connected to the opening.

12. The joint structure according to claim 11 , wherein the conductive joint material includes a filling portion formed in the recess.

13. The joint structure according to any one of claims 1 to 12, a semiconductor element electrically connected to the terminal; A semiconductor device comprising:

14. 14. The semiconductor device according to claim 13, wherein the terminal is a control terminal for controlling the semiconductor element.

15. a first power supply terminal and a second power supply terminal each electrically connected to the semiconductor device; The first power supply terminal receives a first power supply voltage, 15. The semiconductor device according to claim 14, wherein a second power supply voltage is input to said second power supply terminal.

16. The piezoelectric element further includes a first conductor and a second conductor spaced apart from each other in a first direction perpendicular to the thickness direction, the semiconductor element includes a first semiconductor element bonded to the first conductor and a second semiconductor element bonded to the second conductor; the conductive substrate includes a first conductive substrate joined to the first conductor and a second conductive substrate joined to the second conductor; the conductive portion includes a first conductive portion included in the first conductive substrate and a second conductive portion included in the second conductive substrate, the first power supply terminal includes a first input terminal connected to the first conductor and a second input terminal connected to the second semiconductor element; the second power supply terminal is an output terminal connected to the second conductor, 16. The semiconductor device according to claim 15, wherein the control terminal includes a first control terminal joined to the first conductive portion and controlling the first semiconductor element, and a second control terminal joined to the second conductive portion and controlling the second semiconductor element.

17. each of the first semiconductor element and the second semiconductor element is a switching element that performs a switching operation; the first control terminal includes a first drive terminal for controlling a switching operation of the first semiconductor element and a first detection terminal for detecting a conductive state of the first semiconductor element; 17. The semiconductor device according to claim 16, wherein the second control terminal includes a second drive terminal for controlling a switching operation of the second semiconductor element, and a second detection terminal for detecting a conductive state of the second semiconductor element.

18. a resin member that covers each of the first control terminal and the second control terminal, the first conductive substrate and the second conductive substrate, and the first semiconductor element and the second semiconductor element; The semiconductor device according to claim 16 , wherein each of the first control terminal and the second control terminal protrudes from the resin member in the thickness direction.

19. the resin member has a resin main surface and a resin back surface spaced apart in the thickness direction, and a resin side surface sandwiched between the resin main surface and the resin back surface in the thickness direction, The resin side surface faces the first direction, The semiconductor device according to claim 18 , wherein the first power supply terminal and the second power supply terminal protrude in the first direction from a side surface of the resin.