Semiconductor apparatus

Abstract

This semiconductor apparatus comprises: an insulating layer; a support layer which is arranged on the insulating layer and contains metal; and a semiconductor device bonded to the support layer. The semiconductor device has a device metal layer facing the support layer. A solid-phase diffusion coupling layer is interposed between the support layer and the device metal layer. The Vickers hardness of the insulating layer is smaller than that of the support layer.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device in which a semiconductor element is bonded to a support layer containing a metal element in its composition.

[0002] Patent Document 1 discloses an example of a semiconductor device (power module) in which multiple semiconductor elements are bonded to a conductor layer. The multiple semiconductor elements are bonded to the conductor layer via a solder layer. As a result, when the semiconductor device is in use, heat generated from the multiple semiconductor elements is conducted to the conductor layer via the solder layer.

[0003] However, in the semiconductor device disclosed in Patent Document 1, it has been confirmed that the heat dissipation at the bonding interfaces (the interface between the conductive layer and the solder layer, and the interface between the solder layer and the plurality of semiconductor elements) between the conductor layer and the plurality of semiconductor elements decreases over the long term. Therefore, in order to improve the reliability of the semiconductor device, a measure to stabilize the heat dissipation at the bonding interfaces over the long term is desired.

[0004] JP 2016-162773 A

[0005] In view of the above circumstances, one object of the present disclosure is to provide a semiconductor device that can stabilize heat dissipation properties over the long term at the bonding interface between a support layer and a semiconductor element.

[0006] The semiconductor device provided by the present disclosure comprises an insulating layer, a support layer disposed on the insulating layer and containing a metal, and a semiconductor element bonded to the support layer, wherein the semiconductor element has an element metal layer facing the support layer, a solid-state diffusion bonding layer is interposed between the support layer and the element metal layer, and the Vickers hardness of the insulating layer is smaller than the Vickers hardness of the support layer.

[0007] According to the semiconductor device of the present disclosure, it is possible to stabilize the heat dissipation properties at the bonding interface between the support layer and the semiconductor element for a long period of time.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a plan view of the semiconductor device shown in FIG. 1, seen through a sealing resin. FIG. 4 is a front view of the semiconductor device shown in FIG. 1. FIG. 5 is a right side view of the semiconductor device shown in FIG. 1. FIG. 6 is a left side view of the semiconductor device shown in FIG. 1. FIG. 7 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 8 is a partial enlarged view of FIG. 3. FIG. 9 is a partial enlarged view of FIG. 3. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 3. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 3. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 3. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 3. FIG. 14 is a partial enlarged view of FIG. 8. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 14. FIG. 16 is a partial enlarged view of FIG. 15. FIG. 17 is a partial enlarged view of FIG. 8. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 17. FIG. 19 is a partially enlarged cross-sectional view of a modified example of the semiconductor device shown in FIG. 1. FIG. 20 is a partially enlarged cross-sectional view of a semiconductor device according to a second embodiment of the present disclosure. FIG. 21 is a partially enlarged view of FIG. 20. FIG. 21 is a partially enlarged cross-sectional view of a modified example of the semiconductor device shown in FIG. 20. FIG. 23 is a partially enlarged cross-sectional view of a semiconductor device according to a third embodiment of the present disclosure. FIG. 24 is a partially enlarged view of FIG. 23. FIG. 25 is a partially enlarged cross-sectional view of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 26 is a partially enlarged view of FIG. 25.

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0011] A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 18. The semiconductor device A10 includes an insulating layer 11, a heat dissipation layer 12, a plurality of support layers 20, a plurality of input terminals 41, an output terminal 42, a plurality of semiconductor elements 31, a plurality of buffer layers 32, and a sealing resin 70. The semiconductor device A10 also includes a plurality of gate wirings 24, a plurality of detection wirings 25, a plurality of gate terminals 43, a plurality of detection terminals 44, and a case 60. For ease of understanding, FIGS. 3, 8, and 9 are shown through the sealing resin 70. In FIG. 3, lines X-X and XI-XI are indicated by dashed lines.

[0012] The semiconductor device A10 shown in FIG. 1 is a power module. The semiconductor device A10 is used in inverters for electrical appliances, hybrid vehicles, and the like. As shown in FIGS. 1 and 2 , the semiconductor device A10 has a substantially rectangular shape when viewed in the thickness direction z. The thickness direction z refers to the direction along the thickness of the insulating layer 11. Here, for convenience of explanation, one direction perpendicular to the thickness direction z is referred to as the first direction x. A direction perpendicular to both the thickness direction z and the first direction x is referred to as the second direction y. The semiconductor device A10 is relatively elongated along the first direction x, but the present disclosure is not limited thereto.

[0013] 10 and 11 , the insulating layer 11 is supported by the heat dissipation layer 12. The insulating layer 11 has a main surface 111 and a back surface 112 that face opposite each other in the thickness direction z. The main surface 111 faces the multiple support layers 20. The back surface 112 faces the heat dissipation layer 12.

[0014] The insulating layer 11 includes a resin, such as an epoxy resin. The Vickers hardness (HV) of the insulating layer 11 is smaller than the Vickers hardness of each of the support layers 20. As shown in FIGS. 15 and 18 , the thickness t1 of the insulating layer 11 is smaller than the thickness T of each of the support layers 20.

[0015] As shown in FIGS. 10 and 11 , the heat dissipation layer 12 is located on the opposite side of the multiple support layers 20 in the thickness direction z, with the insulating layer 11 sandwiched therebetween. As shown in FIG. 7 , a portion of the heat dissipation layer 12 is exposed to the outside of the semiconductor device A10. The semiconductor device A10 is generally attached to a heat sink. The portion of the heat dissipation layer 12 exposed to the outside of the semiconductor device A10 faces the heat sink. The main element of the heat dissipation layer 12 is a flat metal plate. The metal plate contains copper. The surface of the heat dissipation layer 12 may be nickel-plated. The thickness t2 of the heat dissipation layer 12 is equal to or greater than the thickness T of each of the multiple support layers 20. Therefore, the thickness t2 of the heat dissipation layer 12 is greater than the thickness t1 of the insulating layer 11.

[0016] As shown in FIG. 3 , the multiple support layers 20 are disposed on the main surface 111 of the insulating layer 11. The multiple support layers 20 contain a metal element in their composition. The metal element includes copper. The thickness T of each of the multiple support layers 20 shown in FIGS. 15 and 18 is 1 to 60 times the thickness t1 of the insulating layer 11. The multiple support layers 20 include a first support layer 21, a second support layer 22, and a third support layer 23.

[0017] 3 , the first support layer 21, the second support layer 22, and the third support layer 23 extend in the first direction x. The second support layer 22 is located adjacent to the first support layer 21 in the second direction y. The third support layer 23 is located on the opposite side of the first support layer 21 in the second direction y, with the second support layer 22 sandwiched therebetween.

[0018] As shown in FIG. 3 , the multiple gate wirings 24 are arranged on the main surface 111 of the insulating layer 11. The multiple gate wirings 24 include a first gate wiring 241 and a second gate wiring 242. The first gate wiring 241 is located on the opposite side of the second support layer 22 in the second direction y, with the first support layer 21 sandwiched therebetween. The first gate wiring 241 extends in the first direction x. The first gate wiring 241 includes two regions spaced apart from each other in the second direction y. One ends of the two regions of the first gate wiring 241 located closest to the multiple input terminals 41 are connected to each other. The second gate wiring 242 is located on the opposite side of the second support layer 22 in the second direction y, with the third support layer 23 sandwiched therebetween. The second gate wiring 242 extends in the first direction x. The second gate wiring 242 includes two regions spaced apart from each other in the second direction y. One ends of the two regions of the second gate wiring 242 located closest to the output terminal 42 are connected to each other.

[0019] As shown in FIG. 3 , the multiple detection wirings 25 are arranged on the main surface 111 of the insulating layer 11. The multiple detection wirings 25 include a first detection wiring 251 and a second detection wiring 252. The first detection wiring 251 is located adjacent to the first gate wiring 241 in the second direction y. The first detection wiring 251 extends in the first direction x. The first detection wiring 251 includes two regions located apart from each other in the second direction y. One ends of the two regions of the first detection wiring 251 located closest to the output terminal 42 are connected to each other. The second detection wiring 252 is located adjacent to the second gate wiring 242 in the second direction y. The second detection wiring 252 extends in the first direction x. The second detection wiring 252 includes two regions located apart from each other in the second direction y. One ends of the two regions of the second detection wiring 252 located closest to the multiple input terminals 41 are connected to each other.

[0020] 8, the semiconductor device A10 includes a pair of pads 26. The pair of pads 26 are adjacent to each other in the first direction x. The pair of pads 26 are located at corners of the insulating layer 11. The pair of pads 26 are close to the first support layer 21.

[0021] As shown in Figures 2 and 3, the multiple input terminals 41 are part of the external connection terminals provided on the semiconductor device A10. The multiple input terminals 41 are connected to a DC power supply arranged outside the semiconductor device A10. The multiple input terminals 41 are supported by a case 60. The multiple input terminals 41 are made of a metal plate. The metal plate includes, for example, copper. The multiple input terminals 41 have a thickness of 1.0 mm.

[0022] The multiple input terminals 41 include a first input terminal 41A and a second input terminal 41B. The first input terminal 41A is a positive electrode (P terminal). The first input terminal 41A is bonded to a first pad portion 211 of the first support layer 21. As a result, the first input terminal 41A is electrically connected to the first support layer 21. The second input terminal 41B is a negative electrode (N terminal). The second input terminal 41B is bonded to a third pad portion 231 of the third support layer 23. As a result, the second input terminal 41B is electrically connected to the third support layer 23. The first input terminal 41A and the second input terminal 41B are adjacent to each other in the second direction y.

[0023] As shown in FIGS. 8 and 12, each of the first input terminal 41A and the second input terminal 41B has an external connection portion 411, an internal connection portion 412, and an intermediate portion 413.

[0024] The external connection portion 411 is exposed from the semiconductor device A10 and has a flat plate shape perpendicular to the thickness direction z. A DC power cable or the like is joined to the external connection portion 411. The external connection portion 411 is supported by the case 60. The external connection portion 411 is provided with a connection hole 411A that penetrates in the thickness direction z. A fastening member such as a bolt is inserted into the connection hole 411A. The surface of the external connection portion 411 may be nickel (Ni) plated.

[0025] The internal connection portion 412 has a comb-like shape, and is bonded to the first pad portion 211 of the first support layer 21 for the first input terminal 41A, and to the third pad portion 231 of the third support layer 23 for the second input terminal 41B. In the semiconductor device A10, the internal connection portion 412 has three teeth, and these multiple teeth are arranged along the second direction y. The multiple teeth are bent in the thickness direction z. Therefore, the multiple teeth are hook-shaped when viewed in the second direction y. All of the multiple teeth are bonded to the first pad portion 211 and the third pad portion 231 by ultrasonic vibration.

[0026] The intermediate portion 413 interconnects the external connection portion 411 and the internal connection portion 412. The cross section of the intermediate portion 413 in the first direction x is L-shaped. The intermediate portion 413 has a base portion 413A and an upright portion 413B. The base portion 413A extends along the first direction x and the second direction y. One end of the base portion 413A in the first direction x is connected to the internal connection portion 412. The upright portion 413B stands up from the base portion 413A in the thickness direction z. One end of the upright portion 413B in the thickness direction z is connected to the external connection portion 411.

[0027] 2 and 3, the output terminal 42 is part of the external connection terminals provided on the semiconductor device A10. The output terminal 42 is connected to a power supply target (such as a motor) arranged outside the semiconductor device A10. The output terminal 42 is supported by the case 60 and is located on the opposite side of the insulating layer 11 from the multiple input terminals 41 in the first direction x. The output terminal 42 is made of a metal plate. The metal plate includes, for example, copper. The thickness of the output terminal 42 is 1.0 mm.

[0028] In the semiconductor device A10, the output terminal 42 is separated into two parts: a first terminal portion 42A and a second terminal portion 42B. Alternatively, the output terminal 42 may be a single member in which the first terminal portion 42A and the second terminal portion 42B are integrated. The first terminal portion 42A and the second terminal portion 42B are joined to the second pad portion 221 of the second support layer 22. This establishes electrical continuity between the output terminal 42 and the second support layer 22. The first terminal portion 42A and the second terminal portion 42B are adjacent to each other in the second direction y.

[0029] As shown in FIGS. 9 and 13, each of the first terminal portion 42A and the second terminal portion 42B has an external connection portion 421, an internal connection portion 422, and an intermediate portion 423.

[0030] The external connection portion 421 is exposed from the semiconductor device A10 and has a flat plate shape perpendicular to the thickness direction z. A cable or the like that is electrically connected to a power supply target is joined to the external connection portion 421. The external connection portion 421 is supported by the case 60. A connection hole 421A that penetrates the external connection portion 421 in the thickness direction z is provided. A fastening member such as a bolt is inserted into the connection hole 421A. The surface of the external connection portion 421 may be nickel plated.

[0031] The internal connection portion 422 has a comb-like shape and is bonded to the second pad portion 221 of the second support layer 22. In the semiconductor device A10, the internal connection portion 422 has three teeth, and these multiple teeth are arranged along the second direction y. The multiple teeth are bent in the thickness direction z. Therefore, the multiple teeth are hook-shaped when viewed in the second direction y. All of the multiple teeth are bonded to the second pad portion 221 by ultrasonic vibration.

[0032] The intermediate portion 423 interconnects the external connection portion 421 and the internal connection portion 422. The cross section of the intermediate portion 423 in the first direction x is L-shaped. The intermediate portion 423 has a base portion 423A and an upright portion 423B. The base portion 423A extends along the first direction x and the second direction y. One end of the base portion 423A in the first direction x is connected to the internal connection portion 422. The upright portion 423B stands up from the base portion 423A in the thickness direction z. One end of the upright portion 423B in the thickness direction z is connected to the external connection portion 421.

[0033] When a DC voltage is applied to the first input terminal 41A and the second input terminal 41B of the input terminal 41 and the plurality of semiconductor elements 31 are driven, AC voltages of various frequencies are output from the output terminal 42. The AC voltages are supplied to a power supply target such as a motor.

[0034] As shown in FIGS. 2 to 4 , the gate terminals 43 are part of external connection terminals provided on the semiconductor device A10. The gate terminals 43 are electrically connected to the gate wirings 24. The gate terminals 43 are connected to an external drive circuit (such as a gate driver) for the semiconductor device A10. The gate terminals 43 are supported by a case 60. The gate terminals 43 are made of metal rods. The metal rods may contain, for example, copper. The surfaces of the gate terminals 43 may be plated with tin (Sn), or nickel and tin. As shown in FIG. 11 , the gate terminals 43 have an L-shaped cross section in the first direction x. A portion of each of the gate terminals 43 protrudes from the case 60 in the thickness direction z toward the main surface 111 of the insulating layer 11.

[0035] The multiple gate terminals 43 include a first gate terminal 43A and a second gate terminal 43B. As shown in Fig. 9, the first gate terminal 43A is adjacent to the first gate wiring 241 in the second direction y. As shown in Fig. 8, the second gate terminal 43B is located on the opposite side of the insulating layer 11 from the first gate terminal 43A in the second direction y. The second gate terminal 43B is adjacent to the second gate wiring 242.

[0036] As shown in FIGS. 2 to 4 , the multiple detection terminals 44 are part of the external connection terminals provided on the semiconductor device A10. The multiple detection terminals 44 are electrically connected to the multiple detection wirings 25. The multiple detection terminals 44 are connected to an externally disposed control circuit of the semiconductor device A10. The multiple detection terminals 44 are supported by the case 60. The multiple detection terminals 44 are made of metal rods. The metal rods may contain, for example, copper. Note that the surfaces of the multiple detection terminals 44 may be tin-plated or nickel-plated and tin-plated. As shown in FIG. 11 , the multiple detection terminals 44 have an L-shaped cross section in the first direction x. A portion of each of the multiple detection terminals 44 protrudes from the case 60 in the thickness direction z toward the main surface 111 of the insulating layer 11.

[0037] The plurality of detection terminals 44 include a first detection terminal 44A and a second detection terminal 44B. As shown in Fig. 9, the first detection terminal 44A is located adjacent to the first gate terminal 43A in the first direction x. As shown in Fig. 8, the second detection terminal 44B is located adjacent to the second gate terminal 43B in the first direction x.

[0038] As shown in FIGS. 2 to 4 and 9 , the semiconductor device A10 includes an input current detection terminal 45. The input current detection terminal 45 is part of an external connection terminal provided on the semiconductor device A10. The input current detection terminal 45 is connected to an externally disposed control circuit for the semiconductor device A10. The input current detection terminal 45 is supported by a case 60. The input current detection terminal 45 is made of a metal rod. The metal rod may contain, for example, copper. Note that the surface of the input current detection terminal 45 may be tin-plated or nickel-plated and tin-plated. The shape of the input current detection terminal 45 is the same as that of the multiple gate terminals 43 shown in FIG. 11 . Like the multiple gate terminals 43 shown in FIG. 11 , a portion of the input current detection terminal 45 protrudes from the case 60 in the thickness direction z toward the main surface 111 of the insulating layer 11. In the second direction y, the position of the input current detection terminal 45 is the same as that of the first gate terminal 43A. The input current detection terminal 45 is located away from the first gate terminal 43A in the first direction x on the side where the output terminal 42 is located.

[0039] 9, the semiconductor device A10 includes an input current detection wire 54. The input current detection wire 54 is joined to the input current detection terminal 45 and the first support layer 21. This allows the input current detection terminal 45 to be electrically connected to the first support layer 21. The input current detection wire 54 is made of, for example, aluminum (Al).

[0040] As shown in FIGS. 2 to 4 and 8 , the semiconductor device A10 includes a pair of thermistor terminals 46. The pair of thermistor terminals 46 are part of external connection terminals provided on the semiconductor device A10. The pair of thermistor terminals 46 are connected to an externally disposed control circuit for the semiconductor device A10. The pair of thermistor terminals 46 are supported by a case 60. The pair of thermistor terminals 46 are formed from metal rods. The metal rods may contain, for example, copper. Note that the surfaces of the pair of thermistor terminals 46 may be tin-plated or nickel-plated and tin-plated. The shape of the pair of thermistor terminals 46 is the same as that of the multiple gate terminals 43 shown in FIG. 11 . Like the multiple gate terminals 43 shown in FIG. 11 , a portion of the pair of thermistor terminals 46 protrudes from the case 60 in the thickness direction z toward the main surface 111 of the insulating layer 11. In the second direction y, the position of the pair of thermistor terminals 46 is the same as that of the first gate terminal 43A. The pair of thermistor terminals 46 are located away from the first gate terminal 43A in the first direction x on the side where the plurality of input terminals 41 are located. The pair of thermistor terminals 46 are adjacent to each other in the first direction x.

[0041] 8, the semiconductor device A10 includes a pair of thermistor wires 55. The pair of thermistor wires 55 are individually bonded to a pair of thermistor terminals 46 and a pair of pads 26. As a result, the pair of input current detection terminals 45 are electrically connected to the pair of pads 26. The pair of thermistor wires 55 is made of, for example, aluminum.

[0042] As shown in FIG. 3 , the semiconductor elements 31 are bonded to the first support layer 21 and the second support layer 22 of the support layers 20. The semiconductor elements 31 include a plurality of first semiconductor elements 31A and a plurality of second semiconductor elements 31B. The first semiconductor elements 31A are bonded to the first support layer 21 and arranged along the first direction x. The second semiconductor elements 31B are bonded to the second support layer 22 and arranged along the first direction x. The semiconductor elements 31 are metal-oxide-semiconductor field-effect transistors (MOSFETs) primarily composed of silicon (Si) or silicon carbide (SiC). Alternatively, the semiconductor elements 31 may be switching elements such as insulated gate bipolar transistors (IGBTs) or diodes. In the description of the semiconductor device A10, the semiconductor elements 31 are n-channel MOSFETs with a vertical structure. Therefore, in the semiconductor device A10, the first support layer 21 and the second support layer 22 form a conductive path across the plurality of semiconductor elements 31.

[0043] As shown in FIGS. 14, 15, 17 and 18, the plurality of semiconductor elements 31 have an element metal layer 311, a first electrode 312 and a second electrode 313.

[0044] As shown in Figures 15 and 18, the element metal layer 311 faces either the first support layer 21 or the second support layer 22. The element metal layer 311 is electrically connected to a circuit formed in the semiconductor element 31. Therefore, the element metal layer 311 corresponds to an electrode of the semiconductor element 31. Alternatively, the element metal layer 311 may not correspond to an electrode of the semiconductor element 31, as in a switching element with a horizontal structure. In this case, the first support layer 21 and the second support layer 22 do not form a conductive path across the multiple semiconductor elements 31. A current corresponding to the power before being converted by the semiconductor element 31 flows through the element metal layer 311. In other words, the element metal layer 311 corresponds to the drain electrode of the semiconductor element 31.

[0045] 15 and 18 , the first electrode 312 is located on the opposite side of the element metal layer 311 in the thickness direction z. A current corresponding to the power converted by the semiconductor element 31 flows through the first electrode 312. In other words, the first electrode 312 corresponds to the source electrode of the semiconductor element 31.

[0046] 14 and 17 , the second electrode 313 is located on the same side as the first electrode 312 in the thickness direction z. A gate voltage for driving the semiconductor element 31 is applied to the second electrode 313. That is, the second electrode 313 corresponds to the gate electrode of the semiconductor element 31. When viewed in the thickness direction z, the area of ​​the second electrode 313 is smaller than the area of ​​the first electrode 312.

[0047] As shown in FIGS. 15 and 18 , the buffer layer 32 is interposed between either the first support layer 21 or the second support layer 22 of the multiple support layers 20 and the element metal layer 311 of one of the multiple semiconductor elements 31. The buffer layer 32 contains aluminum. The Vickers hardness of the buffer layer 32 is lower than the Vickers hardness of each of the multiple support layers 20. As shown in FIGS. 14 and 17 , the buffer layer 32 overlapping one of the multiple semiconductor elements 31 protrudes outward from the semiconductor element 31 when viewed in the thickness direction z. Alternatively, the buffer layer 32 overlapping one of the multiple semiconductor elements 31 may have a periphery that coincides with the periphery of the semiconductor element 31 or be surrounded by the periphery of the semiconductor element 31 when viewed in the thickness direction z.

[0048] The element metal layer 311 of each of the multiple semiconductor elements 31 is bonded to either the first support layer 21 or the second support layer 22 by solid-phase diffusion. Solid-phase diffusion bonding is performed under relatively high temperature and pressure conditions. As a result, a solid-phase diffusion bonding layer 33 (see FIG. 16 ) is interposed between either the first support layer 21 or the second support layer 22 and the element metal layer 311. The solid-phase diffusion bonding layer 33 is a concept of a metallic bonding layer located at the interface of two adjacent metal layers formed by solid-phase diffusion bonding of the two metal layers. The solid-phase diffusion bonding layer 33 does not necessarily exist as a metallic bonding layer with a definite thickness. The solid-phase diffusion bonding layer 33 may be identified as a region where impurities or voids introduced during solid-phase diffusion bonding remain along the interface of the two metal layers.

[0049] In the semiconductor device A10, the element metal layer 311 of each of the plurality of semiconductor elements 31 is bonded to either the first support layer 21 or the second support layer 22 via the buffer layer 32 by solid-state diffusion. As a result, the element metal layer 311 of the plurality of first semiconductor elements 31A is electrically connected to the first support layer 21. Therefore, the element metal layer 311 of the plurality of first semiconductor elements 31A is electrically connected to the first input terminal 41A. In addition, the element metal layer 311 of the plurality of second semiconductor elements 31B is electrically connected to the second support layer 22. Therefore, the element metal layer 311 of the plurality of second semiconductor elements 31B is electrically connected to the output terminal 42.

[0050] 16 , in the semiconductor device A10, the solid-phase diffusion bonding layer 33 includes a first bonding layer 331 and a second bonding layer 332 that are spaced apart from each other in the thickness direction z. The first bonding layer 331 is located between the buffer layer 32 and either the first support layer 21 or the second support layer 22. In the semiconductor device A10, the first bonding layer 331 is located at the interface between the buffer layer 32 and either the first support layer 21 or the second support layer. The second bonding layer 332 is located between the buffer layer 32 and an element metal layer 311 of one of the multiple semiconductor elements 31. In the semiconductor device A10, the second bonding layer 332 is located at the interface between the buffer layer 32 and the element metal layer 311.

[0051] 15 and 18 , the buffer layer 32 has a first recess 321 recessed toward either the first support layer 21 or the second support layer 22. When viewed in the thickness direction z, the element metal layer 311 of any of the multiple semiconductor elements 31 overlaps the first recess 321. The first recess 321 is in contact with the sealing resin 70. The first recess 321 is a trace left when the element metal layer 311 of each of the multiple semiconductor elements 31 is bonded to either the first support layer 21 or the second support layer 22 by solid-state diffusion.

[0052] As shown in FIGS. 3 and 8 , the semiconductor device A10 includes a thermistor 39. The thermistor 39 is bonded to a pair of pads 26. In the semiconductor device A10, the thermistor 39 is an NTC (Negative Temperature Coefficient) thermistor. NTC thermistors have the characteristic of gradually decreasing resistance as temperature increases. The thermistor 39 is used as a temperature detection sensor for the semiconductor device A10. The thermistor 39 is electrically connected to a pair of thermistor terminals 46 via the pair of pads 26 and a pair of thermistor wires 55.

[0053] As shown in FIGS. 8 and 9 , the semiconductor device A10 includes a plurality of conductive members 51, a plurality of first gate wires 521, and a plurality of first detection wires 531. These are individually bonded to a plurality of semiconductor elements 31. The plurality of conductive members 51 are metal clips. The composition of the plurality of conductive members 51 includes copper. Alternatively, each of the plurality of conductive members 51 may be composed of a plurality of wires. The plurality of first gate wires 521 and the plurality of first detection wires 531 are made of, for example, aluminum.

[0054] 14 and 17 , the plurality of conductive members 51 have a first bonding portion 511 and a second bonding portion 512. The first bonding portion 511 is bonded to a first electrode 312 of one of the plurality of semiconductor elements 31 via a bonding layer 59. The bonding layer 59 is, for example, solder. The second bonding portion 512 is bonded to either the second support layer 22 or the third support layer 23 of the plurality of support layers 20 via the bonding layer 59.

[0055] As shown in FIGS. 8 and 9 , the plurality of conductive members 51 include a plurality of first conductive members 51A and a plurality of second conductive members 51B. As shown in FIG. 14 , the plurality of first conductive members 51A are individually bonded to the first electrodes 312 of the plurality of first semiconductor elements 31A and the second support layer 22. As a result, the first electrodes 312 of the plurality of first semiconductor elements 31A are electrically connected to the second support layer 22. Therefore, the first electrodes 312 of the plurality of first semiconductor elements 31A are electrically connected to the output terminal 42. As shown in FIG. 17 , the plurality of second conductive members 51B are individually bonded to the first electrodes 312 of the plurality of second semiconductor elements 31B and the third support layer 23. As a result, the first electrodes 312 of the plurality of semiconductor elements 31B are electrically connected to the third support layer 23. Therefore, the first electrodes 312 of the plurality of second semiconductor elements 31B are electrically connected to the second input terminal 41B.

[0056] 14 , the multiple first gate wires 521 and multiple first detection wires 531 individually bonded to the multiple first semiconductor elements 31A will be described. The multiple first gate wires 521 are individually bonded to the second electrodes 313 of the multiple first semiconductor elements 31A and the first gate wiring 241. The multiple first detection wires 531 are individually bonded to the first electrodes 312 of the multiple first semiconductor elements 31A and the first detection wiring 251.

[0057] 17 , the multiple first gate wires 521 and multiple first detection wires 531 individually bonded to the multiple second semiconductor elements 31B will be described. The multiple first gate wires 521 are individually bonded to the second electrodes 313 of the multiple second semiconductor elements 31B and the second gate wiring 242. The multiple first detection wires 531 are individually bonded to the first electrodes 312 of the multiple second semiconductor elements 31B and the second detection wiring 252.

[0058] 8 and 9, the semiconductor device A10 includes a pair of second gate wires 522. The pair of second gate wires 522 is bonded to a plurality of gate terminals 43 and a plurality of gate wirings 24. The plurality of second gate wires 522 is made of, for example, aluminum.

[0059] 9, one second gate wire 522 is joined to the first gate terminal 43A and the first gate wiring 241. As a result, the first gate terminal 43A is electrically connected to the second electrodes 313 of the plurality of first semiconductor elements 31A. As shown in FIG. 8, the other second gate wire 522 is joined to the second gate terminal 43B and the second gate wiring 242. As a result, the second gate terminal 43B is electrically connected to the second electrodes 313 of the plurality of second semiconductor elements 31B.

[0060] 8 and 9, the semiconductor device A10 includes a pair of second detection wires 532. The pair of second detection wires 532 is joined to the plurality of detection terminals 44 and the plurality of detection wirings 25. The plurality of second detection wires 532 are made of, for example, aluminum.

[0061] As shown in Fig. 9, one second detection wire 532 is joined to the first detection terminal 44A and the first detection wiring 251. As a result, the first detection terminal 44A is electrically connected to the first electrodes 312 of the plurality of first semiconductor elements 31A. As shown in Fig. 8, the other second detection wire 532 is joined to the second detection terminal 44B and the second detection wiring 252. As a result, the second detection terminal 44B is electrically connected to the first electrodes 312 of the plurality of second semiconductor elements 31B.

[0062] As shown in Figures 10 and 11 , the case 60 supports the heat dissipation layer 12. In the thickness direction z, the main surface 111 of the insulating layer 11 faces the case 60. The case 60 has electrical insulation properties. The case 60 is made of a material containing a resin with excellent heat resistance, such as PPS (polyphenylene sulfide). The case 60 has a pair of first side walls 611, a pair of second side walls 612, a plurality of mounting portions 62, an input terminal block 63, and an output terminal block 64.

[0063] 2 and 3 , the pair of first side walls 611 are spaced apart from each other in the first direction x. The pair of first side walls 611 are arranged along both the second direction y and the thickness direction z, and one end of each of the pair of first side walls 611 in the thickness direction z is in contact with the heat dissipation layer 12.

[0064] As shown in FIGS. 2 and 3 , the pair of second side walls 612 are spaced apart from each other in the second direction y. The pair of second side walls 612 are arranged along both the first direction x and the thickness direction z, and one end in the thickness direction z is in contact with the heat dissipation layer 12. Both ends of the pair of second side walls 612 in the first direction x are connected to the pair of first side walls 611. The first gate terminal 43A, the first detection terminal 44A, the input current detection terminal 45, and a pair of thermistor terminals 46 are arranged inside one of the second side walls 612. The second gate terminal 43B and the second detection terminal 44B are arranged inside the other second side wall 612. As shown in FIGS. 8 and 9 , the ends of these terminals that are close to the insulating layer 11 in the thickness direction z are supported by the pair of second side walls 612.

[0065] 2 , 8 , and 9 , the multiple mounting portions 62 are portions provided at the four corners of the case 60 when viewed in the thickness direction z. The heat dissipation layer 12 contacts the lower surfaces of the multiple mounting portions 62. Each of the multiple mounting portions 62 has a mounting hole 621 that penetrates in the thickness direction z. The semiconductor device A10 can be attached to a heat sink by inserting fastening members such as bolts into the multiple mounting holes 621.

[0066] As shown in FIGS. 2 , 5 , and 8 , the input terminal block 63 protrudes outward in the first direction x from one of the first side walls 611. A plurality of input terminals 41 are supported on the input terminal block 63. The input terminal block 63 includes a first terminal block 631 and a second terminal block 632. The first terminal block 631 and the second terminal block 632 are spaced apart from each other in the second direction y. The first terminal block 631 supports the first input terminal 41A. The external connection portion 411 of the first input terminal 41A is exposed from the first terminal block 631. The second terminal block 632 supports the second input terminal 41B. The external connection portion 411 of the second input terminal 41B is exposed from the second terminal block 632. A plurality of grooves 633 extending in the first direction x are formed between the first terminal block 631 and the second terminal block 632. As shown in FIGS. 10 and 12 , a pair of nuts 634 and a pair of intermediate members 635 are disposed inside the first terminal block 631 and the second terminal block 632. The pair of intermediate members 635 are located on the insulating layer 11 side of the pair of nuts 634 in the thickness direction z and are in contact with the pair of nuts 634. One intermediate member 635 supports the external connection portion 411 and intermediate portion 413 of the first input terminal 41A. The other intermediate member 635 supports the external connection portion 411 and intermediate portion 413 of the second input terminal 41B. A portion of each of the pair of intermediate members 635 is exposed from the input terminal block 63. The pair of nuts 634 correspond to a pair of connection holes 411A provided in the first input terminal 41A and the second input terminal 41B. Fastening members such as bolts inserted into the pair of connection holes 411A are fitted into the pair of nuts 634.

[0067] As shown in FIGS. 2 , 6 , and 9 , the output terminal block 64 protrudes outward in the first direction x from the other first side wall 611. The output terminal 42 is supported on the output terminal block 64. The output terminal block 64 has a first terminal block 641 and a second terminal block 642. The first terminal block 641 and the second terminal block 642 are spaced apart from each other in the second direction y. The first terminal block 641 supports the first terminal portion 42A of the output terminal 42. The external connection portion 421 of the first terminal portion 42A is exposed from the first terminal block 641. The second terminal block 642 supports the second terminal portion 42B of the output terminal 42. The external connection portion 421 of the second terminal portion 42B is exposed from the second terminal block 642. A plurality of grooves 643 extending in the first direction x are formed between the first terminal block 641 and the second terminal block 642. As shown in FIGS. 10 and 13 , a pair of nuts 644 and a pair of intermediate members 645 are disposed inside the first terminal block 641 and the second terminal block 642. The pair of intermediate members 645 are located on the insulating layer 11 side of the pair of nuts 644 in the thickness direction z and are in contact with the pair of nuts 644. One intermediate member 645 supports the external connection portion 421 and the intermediate portion 423 of the first terminal portion 42A. The other intermediate member 645 supports the external connection portion 421 and the intermediate portion 423 of the second terminal portion 42B. A portion of each of the pair of intermediate members 645 is exposed from the output terminal block 64. The pair of nuts 644 correspond to a pair of connection holes 421A provided in the first terminal portion 42A and the second terminal portion 42B. Fastening members such as bolts inserted into the pair of connection holes 421A are fitted into the pair of nuts 644.

[0068] 10 and 11, the sealing resin 70 covers the semiconductor elements 31. The sealing resin 70 has electrical insulating properties. The sealing resin 70 is, for example, silicone gel. Alternatively, the sealing resin 70 may be an epoxy resin.

[0069] Next, a semiconductor device A11, which is a modification of the semiconductor device A10, will be described with reference to Fig. 19. The position in Fig. 19 is the same as the position in Fig. 15.

[0070] As shown in FIG. 19 , the insulating layer 11 has a second recess 113 recessed in the same direction as the first recess 321 of the buffer layer 32. When viewed in the thickness direction z, the first recess 321 overlaps the second recess 113. The second recess 113 is formed in conjunction with the formation of the first recess 321. The second recess 113 is in contact with the sealing resin 70. When bonding the element metal layer 311 of each of the multiple semiconductor elements 31 to either the first support layer 21 or the second support layer 22 via the buffer layer 32 by solid-phase diffusion, the first recess 321 and the second recess 113 are obtained by applying a pressure higher than that in the case of the semiconductor device A10 shown in FIG. 15 . In this case, the thickness t1 of the insulating layer 11 must be equal to or approximately equal to the thickness T of each of the multiple support layers 20, and the material of the insulating layer 11 must have high toughness.

[0071] Next, the effects of the semiconductor device A10 will be described.

[0072] The semiconductor device A10 includes an insulating layer 11, a support layer 20 disposed on the insulating layer 11 and containing a metal element, and a semiconductor element 31 bonded to the support layer 20. The semiconductor element 31 has an element metal layer 311 facing the support layer 20. A solid-phase diffusion bonding layer 33 is interposed between the support layer 20 and the element metal layer 311. As a result, the bonding interface between the support layer 20 and the element metal layer 311 is formed by the solid-phase diffusion bonding layer 33. Furthermore, the Vickers hardness of the insulating layer 11 is lower than that of the support layer 20. With this configuration, when the element metal layer 311 is bonded to the support layer 20 by solid-phase diffusion, the deformation performance of the insulating layer 11 is greater than that of the support layer 20, thereby reducing bending acting on the support layer 20 around a direction perpendicular to the thickness direction z. As a result, compressive stress acts evenly on the solid-phase diffusion bonding layer 33, strengthening the metal bond in the solid-phase diffusion bonding layer 33. This results in a solid-phase diffusion bonding layer 33 with stable heat dissipation properties over the long term. Therefore, with the semiconductor device A10, it is possible to stabilize the heat dissipation properties at the bonding interface between the support layer 20 and the semiconductor element 31 over the long term.

[0073] The semiconductor device A10 further includes a buffer layer 32 interposed between the support layer 20 and the element metal layer 311 of the semiconductor element 31. The Vickers hardness of the buffer layer 32 is lower than that of the support layer 20. With this configuration, when the element metal layer 311 is bonded to the support layer 20 by solid-state diffusion, the bending stress acting on each of the support layer 20 and the element metal layer 311 can be reduced. This further strengthens the metal bond in the solid-state diffusion bonding layer 33. Therefore, the heat dissipation properties of the solid-state diffusion bonding layer 33 are further stabilized. When the buffer layer 32 contains aluminum in its composition, the bending stress acting on each of the support layer 20 and the element metal layer 311 can be more effectively reduced.

[0074] The buffer layer 32 has a first recess 321 recessed toward the support layer 20. When viewed in the thickness direction z, the element metal layer 311 of the semiconductor element 31 overlaps the first recess 321. This configuration is an indication that a relatively high pressure has been applied to the solid-phase diffusion bonding layer 33. This makes it easy to visually confirm that the metal bond in the solid-phase diffusion bonding layer 33 has become stronger.

[0075] In the semiconductor device A11, the insulating layer 11 is formed with a second recess 113 that is recessed in the same direction as the first recess 321 of the buffer layer 32. When viewed in the thickness direction z, the first recess 321 overlaps the second recess 113. This configuration is an indication that a higher pressure is applied to the solid-phase diffusion bonding layer 33 than in the case of the semiconductor device A10.

[0076] The thickness of the insulating layer 11 is preferably equal to or relatively smaller than the thickness of the support layer 20. This makes it possible to more effectively reduce bending acting on the support layer 20 about a direction perpendicular to the thickness direction z when the element metal layer 311 of the semiconductor element 31 is bonded to the support layer 20 by solid-state diffusion. From the viewpoint of effectively reducing bending acting on the support layer 20, the thickness of the support layer 20 is preferably 1 to 60 times the thickness of the insulating layer 11.

[0077] The element metal layer 311 of the semiconductor element 31 is electrically connected to the circuit formed in the semiconductor element 31. Therefore, the element metal layer 311 corresponds to an electrode of the semiconductor element 31. In this case, when the semiconductor device A10 is used, a current flows through the solid-phase diffusion bonding layer 33. When the metal bond in the solid-phase diffusion bonding layer 33 becomes stronger, long-term fluctuations in the current flowing through the solid-phase diffusion bonding layer 33 are suppressed. Therefore, long-term stability of the current flowing through the bonding interface between the support layer 20 and the semiconductor element 31 can be achieved.

[0078] The semiconductor device A10 further includes a first input terminal 41A electrically connected to the two first support layers 21 and a second input terminal 41B electrically connected to the plurality of second semiconductor elements 31B. The first input terminal 41A and the second input terminal 41B are adjacent to each other. As a result, when a voltage is applied to the first input terminal 41A and the second input terminal 41B, mutual inductance occurs between the first input terminal 41A and the second input terminal 41B. This reduces the parasitic inductance of the semiconductor device A10.

[0079] The semiconductor device A10 further includes a heat dissipation layer 12 located on the opposite side of the support layer 20 with the insulating layer 11 sandwiched therebetween. The thickness of the heat dissipation layer 12 is greater than the thickness of the insulating layer 11. This allows heat conducted from the semiconductor element 31 to the insulating layer 11 via the solid-state diffusion bonding layer 33 to be efficiently dissipated to the outside of the semiconductor device A10.

[0080] A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 20 and 21. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. Here, the position in Figure 20 is the same as the position in Figure 15 showing the semiconductor device A10.

[0081] The semiconductor device A20 differs from the previously described semiconductor device A10 in that it further includes a first metal layer 341, a second metal layer 342, a third metal layer 343, and a fourth metal layer 344. Figures 20 and 21 show the configuration between a first support layer 21 of the multiple support layers 20 and one of the multiple first semiconductor elements 31A of the multiple semiconductor elements 31. However, in the semiconductor device A20, the configuration between a second support layer 22 of the multiple support layers 20 and one of the multiple second semiconductor elements 31B of the multiple semiconductor elements 31 is similar to the configuration between the first support layer 21 and the first semiconductor element 31A. Therefore, in describing the semiconductor device A20, the configuration between the first support layer 21 and one of the multiple first semiconductor elements 31A will be described as a representative example.

[0082] 20 , the first metal layer 341 is interposed between the first support layer 21 and the buffer layer 32. The first metal layer 341 is in contact with the buffer layer 32. The first metal layer 341 contains, for example, silver (Ag). The second metal layer 342 is interposed between the buffer layer 32 and the element metal layer 311 of any one of the multiple first semiconductor elements 31A. The second metal layer 342 is in contact with the buffer layer 32. The second metal layer 342 contains, for example, silver. When the element metal layer 311 of the multiple first semiconductor elements 31A is bonded to the first support layer 21 via the buffer layer 32 by solid-state diffusion, the first metal layer 341 and the second metal layer 342 cover the buffer layer 32.

[0083] 20 , the third metal layer 343 is interposed between the first support layer 21 and the first metal layer 341. The third metal layer 343 is in contact with the first support layer 21. The composition of the third metal layer 343 includes, for example, silver. When the element metal layers 311 of the multiple first semiconductor elements 31A are bonded to the first support layer 21 via the buffer layer 32 by solid-state diffusion, the third metal layer 343 covers the first support layer 21.

[0084] 20 , the fourth metal layer 344 is interposed between the second metal layer 342 and the element metal layer 311 of any one of the plurality of first semiconductor elements 31A. The fourth metal layer 344 is in contact with the element metal layer 311. The composition of the fourth metal layer 344 includes silver, for example. When the element metal layers 311 of the plurality of first semiconductor elements 31A are bonded to the first support layer 21 by solid-state diffusion via the buffer layer 32, the fourth metal layer 344 covers any one of the element metal layers 311.

[0085] 21 , the first bonding layer 331 of the solid-state diffusion bonding layer 33 is located at the interface between the first metal layer 341 and the third metal layer 343. The second bonding layer 332 of the solid-state diffusion bonding layer 33 is located at the interface between the second metal layer 342 and the fourth metal layer 344.

[0086] Next, a semiconductor device A21, which is a modification of the semiconductor device A20, will be described with reference to Fig. 22. The position in Fig. 22 is the same as the position in Fig. 21.

[0087] 22, the semiconductor device A21 does not include the fourth metal layer 344. In this case, the second bonding layer 332 of the solid-state diffusion bonding layer 33 is located at the interface between the second metal layer 342 and the element metal layer 311 of any one of the plurality of first semiconductor elements 31A.

[0088] Next, the effects of the semiconductor device A20 will be described.

[0089] The semiconductor device A20 includes an insulating layer 11, a support layer 20 disposed on the insulating layer 11 and containing a metal element, and a semiconductor element 31 bonded to the support layer 20. The semiconductor element 31 has an element metal layer 311 facing the support layer 20. A solid-phase diffusion bonding layer 33 is interposed between the support layer 20 and the element metal layer 311. The Vickers hardness of the insulating layer 11 is lower than the Vickers hardness of the support layer 20. Therefore, the semiconductor device A20 also enables long-term stability of heat dissipation at the bonding interface between the support layer 20 and the semiconductor element 31. Furthermore, by having a configuration similar to that of the semiconductor device A10, the semiconductor device A20 also achieves the effects of that configuration.

[0090] The semiconductor device A20 further includes a first metal layer 341, a second metal layer 342, and a third metal layer 343. The first metal layer 341 and the second metal layer 342 are in contact with the buffer layer 32. The third metal layer 343 is in contact with the support layer 20. The first metal layer 341, the second metal layer 342, and the third metal layer 343 contain silver. In this case, the first bonding layer 331 of the solid-state diffusion bonding layer 33 is located at the interface between the first metal layer 341 and the third metal layer 343. When metal layers containing silver are bonded together by solid-state diffusion, the strength of the metallic bond is relatively high. Therefore, the metallic bond in the solid-state diffusion bonding layer 33 can be further strengthened.

[0091] A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to Figures 23 and 24. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. Here, the position in Figure 23 is the same as the position in Figure 15 showing the semiconductor device A10.

[0092] The semiconductor device A30 differs from the previously described semiconductor device A10 in that it does not include a buffer layer 32. Figures 23 and 24 show the configuration between a first support layer 21 of the multiple support layers 20 and one of the multiple first semiconductor elements 31A of the multiple semiconductor elements 31. However, in the semiconductor device A30, the configuration between a second support layer 22 of the multiple support layers 20 and one of the multiple second semiconductor elements 31B of the multiple semiconductor elements 31 is also similar to the configuration between the first support layer 21 and the first semiconductor element 31A. Therefore, in the description of the semiconductor device A30, the configuration between the first support layer 21 and one of the multiple first semiconductor elements 31A will be representatively described.

[0093] 23 , an element metal layer 311 of any one of the plurality of first semiconductor elements 31A is in contact with the first support layer 21. The element metal layer 311 has a composition containing, for example, silver. As shown in FIG. 24 , a solid-state diffusion bonding layer 33 is located at the interface between the first support layer 21 and the element metal layer 311. In the semiconductor device A30, the solid-state diffusion bonding layer 33 does not include a first bonding layer 331 or a second bonding layer 332.

[0094] 23 , a third recess 201 recessed toward the insulating layer 11 is formed in the first support layer 21. When viewed in the thickness direction z, the element metal layer 311 of any one of the multiple first semiconductor elements 31A overlaps the third recess 201. The third recess 201 is a trace left when the element metal layer 311 of the first semiconductor element 31A is bonded to the first support layer 21 by solid-state diffusion. Furthermore, a third recess 201 is also formed in the second support layer 22 as a trace left when the element metal layer 311 of any one of the multiple second semiconductor elements 31B is bonded to the second support layer 22 by solid-state diffusion.

[0095] 23 , a fourth recess 114 is formed in the insulating layer 11, recessed in the same direction as the third recess 201 in the first support layer 21. When viewed in the thickness direction z, the third recess 201 overlaps the fourth recess 114. The fourth recess 114 is formed in conjunction with the formation of the third recess 201. The third recess 201 and the fourth recess 114 may also be formed in the semiconductor device A10. The condition in this case is that, when viewed in the thickness direction z, the periphery of the buffer layer 32 overlapping one of the multiple semiconductor elements 31 coincides with the periphery of the semiconductor element 31 or is surrounded by the periphery of the semiconductor element 31.

[0096] As shown in FIG. 23 , the sealing resin 70 contacts the third recess 201 of the first support layer 21 and the fourth recess 114 of the insulating layer 11 .

[0097] Next, the effects of the semiconductor device A30 will be described.

[0098] The semiconductor device A30 includes an insulating layer 11, a support layer 20 disposed on the insulating layer 11 and containing a metal element, and a semiconductor element 31 bonded to the support layer 20. The semiconductor element 31 has an element metal layer 311 facing the support layer 20. A solid-phase diffusion bonding layer 33 is interposed between the support layer 20 and the element metal layer 311. The Vickers hardness of the insulating layer 11 is lower than the Vickers hardness of the support layer 20. Therefore, the semiconductor device A30 also enables long-term stability of heat dissipation at the bonding interface between the support layer 20 and the semiconductor element 31. Furthermore, by having a configuration similar to that of the semiconductor device A10, the semiconductor device A30 also achieves the effects of that configuration.

[0099] In the semiconductor device A30, the element metal layer 311 of the semiconductor element 31 contains silver. With this configuration, when the element metal layer 311 is bonded to the support layer 20 by solid-state diffusion, the element metal layer 311 takes over the function of the buffer layer 32. This makes the buffer layer 32 unnecessary.

[0100] A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to Figures 25 and 26. In these figures, elements that are the same as or similar to those of the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. Here, the position in Figure 25 is the same as the position in Figure 15 showing the semiconductor device A10.

[0101] The semiconductor device A40 differs from the previously described semiconductor device A30 in that it further includes a lower metal layer 351 and an upper metal layer 352. Figures 25 and 26 show the configuration between a first support layer 21 of the multiple support layers 20 and one of the multiple first semiconductor elements 31A of the multiple semiconductor elements 31. However, in the semiconductor device A40, the configuration between a second support layer 22 of the multiple support layers 20 and one of the multiple second semiconductor elements 31B of the multiple semiconductor elements 31 is also similar to the configuration between the first support layer 21 and the first semiconductor element 31A. Therefore, in the description of the semiconductor device A40, the configuration between the first support layer 21 and one of the multiple first semiconductor elements 31A will be representatively described.

[0102] 25 , the lower metal layer 351 is interposed between the first support layer 21 and the element metal layer 311 of any one of the multiple first semiconductor elements 31A. The lower metal layer 351 is in contact with the first support layer 21. The composition of the lower metal layer 351 includes silver, for example. When the element metal layer 311 of the multiple first semiconductor elements 31A is bonded to the first support layer 21 by solid-state diffusion, the lower metal layer 351 covers the first support layer 21.

[0103] 25 , the upper metal layer 352 is interposed between the lower metal layer 351 and the element metal layer 311 of any one of the plurality of first semiconductor elements 31A. The upper metal layer 352 is in contact with the element metal layer 311. The composition of the upper metal layer 352 includes silver, for example. When the element metal layers 311 of the plurality of first semiconductor elements 31A are bonded to the first support layer 21 by solid-state diffusion, the upper metal layer 352 covers any one of the element metal layers 311. As shown in FIG. 26 , the solid-state diffusion bonding layer 33 is located at the interface between the lower metal layer 351 and the upper metal layer 352.

[0104] Next, the effects of the semiconductor device A40 will be described.

[0105] The semiconductor device A40 includes an insulating layer 11, a support layer 20 disposed on the insulating layer 11 and containing a metal element, and a semiconductor element 31 bonded to the support layer 20. The semiconductor element 31 has an element metal layer 311 facing the support layer 20. A solid-state diffusion bonding layer 33 is interposed between the support layer 20 and the element metal layer 311. The Vickers hardness of the insulating layer 11 is lower than the Vickers hardness of the support layer 20. Therefore, the semiconductor device A40 also enables long-term stability of heat dissipation at the bonding interface between the support layer 20 and the semiconductor element 31. Furthermore, by having a configuration similar to that of the semiconductor device A10, the semiconductor device A40 also achieves the effects of that configuration.

[0106] The semiconductor device A40 further includes a lower metal layer 351 and an upper metal layer 352. The lower metal layer 351 is in contact with the support layer 20. The upper metal layer 352 is in contact with the element metal layer 311 of the semiconductor element 31. The composition of the lower metal layer 351 and the upper metal layer 352 includes silver. In this case, the solid-phase diffusion bonding layer 33 is located at the interface between the lower metal layer 351 and the upper metal layer 352. Therefore, the semiconductor device A40 exhibits the same effects as the semiconductor device A20, and the metal bond in the solid-phase diffusion bonding layer 33 can be further strengthened.

[0107] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0108] The present disclosure includes embodiments described in the following appendices. Appendix 1. A semiconductor device comprising: an insulating layer; a support layer disposed on the insulating layer and containing a metal; and a semiconductor element bonded to the support layer, wherein the semiconductor element has an element metal layer facing the support layer, a solid-state diffusion bonding layer is interposed between the support layer and the element metal layer, and the Vickers hardness of the insulating layer is lower than the Vickers hardness of the support layer. Appendix 2. The semiconductor device according to Appendix 1, wherein the insulating layer contains a resin. Appendix 3. The semiconductor device according to Appendix 2, wherein the metal contains copper. Appendix 4. The semiconductor device according to any one of Appendixes 1 to 3, further comprising a buffer layer interposed between the support layer and the element metal layer, wherein the solid-state diffusion bonding layer includes a first bonding layer located between the support layer and the buffer layer and a second bonding layer located between the buffer layer and the element metal layer, and the Vickers hardness of the buffer layer is lower than the Vickers hardness of the support layer. Appendix 5. The semiconductor device according to Appendix 4, wherein the buffer layer contains aluminum. Appendix 6. The semiconductor device according to Appendix 4 or 5, further comprising: a first metal layer interposed between the support layer and the buffer layer; a second metal layer interposed between the buffer layer and the element metal layer; and a third metal layer interposed between the support layer and the first metal layer, wherein the first metal layer and the second metal layer are in contact with the buffer layer, the third metal layer is in contact with the support layer, the first bonding layer is located at the interface between the first metal layer and the third metal layer, and the second bonding layer is located between the second metal layer and the element metal layer. Appendix 7. The semiconductor device according to Appendix 6, wherein the first metal layer, the second metal layer, and the third metal layer each contain silver. Appendix 8. The semiconductor device described in Appendix 6 or 7, further comprising a fourth metal layer interposed between the second metal layer and the element metal layer, the fourth metal layer being in contact with the element metal layer, and the second bonding layer being located at the interface between the second metal layer and the fourth metal layer.Appendix 9. The semiconductor device according to any one of Appendixes 4 to 8, wherein a first recess recessed toward the support layer is formed in the buffer layer, and the element metal layer overlaps the first recess when viewed in the thickness direction of the insulating layer. Appendix 10. The semiconductor device according to Appendix 9, wherein a second recess recessed in the same direction as the first recess is formed in the insulating layer, and the first recess overlaps the second recess when viewed in the thickness direction. Appendix 11. The semiconductor device according to Appendix 9 or 10, further comprising a sealing resin covering the semiconductor element, the sealing resin being in contact with the first recess. Appendix 12. The semiconductor device according to any one of Appendixes 1 to 3, wherein the element metal layer contains silver. Appendix 13. The semiconductor device according to claim 12, further comprising: a lower metal layer interposed between the support layer and the element metal layer; and an upper metal layer interposed between the lower metal layer and the element metal layer, wherein the lower metal layer is in contact with the support layer, the upper metal layer is in contact with the element metal layer, and the solid-state diffusion bonding layer is located at the interface between the lower metal layer and the upper metal layer. Appendix 14. The semiconductor device according to any of claims 1 to 13, wherein the thickness of the insulating layer is equal to or smaller than the thickness of the support layer. Appendix 15. The semiconductor device according to claim 14, wherein the thickness of the support layer is between 1 and 60 times the thickness of the insulating layer. Appendix 16. The semiconductor device according to any of claims 1 to 15, further comprising a heat dissipation layer located on the opposite side of the support layer with the insulating layer sandwiched therebetween, wherein the thickness of the heat dissipation layer is greater than the thickness of the insulating layer. Appendix 17. The semiconductor device according to any of claims 1 to 16, wherein the element metal layer is electrically connected to a circuit formed in the semiconductor element.

[0109] A10, A20, A30, A40: semiconductor device 11: insulating layer 111: main surface 112: back surface 113: second recess 114: fourth recess 12: heat dissipation layer 20: support layer 201: third recess 21: first support layer 211: first pad portion 22: second support layer 221: second pad portion 23: third support layer 231: third pad portion 24: gate wiring 241: first gate wiring 242: second gate wiring 25: detection wiring 251: first detection wiring 252: second detection wiring 26: pad 31: semiconductor element 31A: first semiconductor element 31B: second semiconductor element 311: element metal layer 312: first electrode 313: second electrode 32: buffer layer 32: first recess 33: Solid phase diffusion bonding layer 331: First bonding layer 332: Second bonding layer 341: First metal layer 342: Second metal layer 343: Third metal layer 344: Fourth metal layer 351: Lower metal layer 352: Upper metal layer 39: Thermistor 41: Input terminal 41A: First input terminal 41B: Second input terminal 411: External connection portion 411A: Connection hole 412: Internal connection portion 413: Intermediate portion 413A: Base portion 413B: Upright portion 42: Output terminal 42A: First terminal portion 42B: Second terminal portion 421: External connection portion 421A: Connection hole 422: Internal connection portion 423: Intermediate portion 423A: Base portion 423B: Upright portion 43: Gate terminal 43A: First gate terminal 43B: Second gate terminal 44: Detection terminal 44A: First detection terminal 44B: Second detection terminal 45: Input current detection terminal 46: Thermistor terminal 51: Conductive member 51A: First conductive member 51B: Second conductive member 511: First joint 512: Second joint 521: First gate wire 522: Second gate wire 531: First detection wire 532: Second detection wire 54: Input current detection wire 55: Thermistor wire 59: Bonding layer 60: Case 611: First side wall 612: Second side wall 62: Mounting base 621: Mounting hole 63: Input terminal block 631: First terminal block 632: Second terminal block 633: Groove 634: Nut 635: Intermediate member64: Output terminal block 641: First terminal block 642: Second terminal block 643: Groove portion 644: Nut 645: Intermediate member 70: Sealing resin T, t1, t2: Thickness z: Thickness direction x: First direction y: Second direction

Claims

1. An insulating layer; a support layer disposed on the insulating layer and containing a metal; a semiconductor element bonded to the support layer; the semiconductor element has an element metal layer facing the support layer; a solid-phase diffusion bonding layer is interposed between the support layer and the element metal layer; The semiconductor device, wherein the insulating layer has a Vickers hardness smaller than a Vickers hardness of the support layer.

2. The semiconductor device according to claim 1 , wherein the insulating layer includes a resin.

3. The semiconductor device according to claim 2 , wherein the metal includes copper.

4. a buffer layer interposed between the support layer and the element metal layer; the solid-state diffusion bonding layer includes a first bonding layer located between the support layer and the buffer layer, and a second bonding layer located between the buffer layer and the element metal layer; The semiconductor device according to claim 1 , wherein the buffer layer has a Vickers hardness lower than a Vickers hardness of the support layer.

5. The semiconductor device according to claim 4 , wherein the buffer layer contains aluminum.

6. a first metal layer interposed between the support layer and the buffer layer; a second metal layer interposed between the buffer layer and the element metal layer; a third metal layer interposed between the support layer and the first metal layer, the first metal layer and the second metal layer are in contact with the buffer layer; the third metal layer is in contact with the support layer; the first bonding layer is located at an interface between the first metal layer and the third metal layer; The semiconductor device of claim 4 , wherein the second bonding layer is located between the second metal layer and the element metal layer.

7. The semiconductor device according to claim 6 , wherein the first metal layer, the second metal layer and the third metal layer each contain silver.

8. a fourth metal layer interposed between the second metal layer and the element metal layer; the fourth metal layer is in contact with the element metal layer; The semiconductor device of claim 6 , wherein the second bonding layer is located at an interface between the second metal layer and the fourth metal layer.

9. The buffer layer has a first recess formed therein, the first recess being recessed toward the support layer, The semiconductor device according to claim 4 , wherein the element metal layer overlaps the first recess when viewed in a thickness direction of the insulating layer.

10. a second recess formed in the insulating layer, the second recess being recessed in the same direction as the first recess; The semiconductor device according to claim 9 , wherein the first recess overlaps the second recess when viewed in the thickness direction.

11. Further comprising a sealing resin for covering the semiconductor element, The semiconductor device according to claim 9 , wherein the sealing resin is in contact with the first recess.

12. The semiconductor device according to claim 1 , wherein the element metal layer contains silver.

13. a lower metal layer interposed between the support layer and the element metal layer; an upper metal layer interposed between the lower metal layer and the element metal layer; the lower metal layer is in contact with the support layer; the top metal layer is in contact with the element metal layer; The semiconductor device of claim 12 , wherein the solid phase diffusion bonding layer is located at an interface between the lower metal layer and the upper metal layer.

14. 14. The semiconductor device according to claim 1, wherein the insulating layer has a thickness equal to or smaller than a thickness of the supporting layer.

15. The semiconductor device according to claim 14 , wherein the thickness of the support layer is 1 to 60 times the thickness of the insulating layer.

16. a heat dissipation layer located on the opposite side of the support layer with the insulating layer interposed therebetween, 14. The semiconductor device according to claim 1, wherein the heat dissipation layer has a thickness greater than a thickness of the insulating layer.

17. 14. The semiconductor device according to claim 1, wherein the element metal layer is electrically connected to the support layer and to a circuit formed in the semiconductor element.