Semiconductor device and method for manufacturing the same

Abstract

Provided is a storage element provided with a new configuration. This storage element has a first electrode, a first insulating layer, a semiconductor layer, a second insulating layer, and a second electrode which are stacked, wherein the first electrode, the first insulating layer, the semiconductor layer, the second insulating layer, and the second electrode each have a region that overlaps each other. An oxide semiconductor that is one type of metal oxide is used as the semiconductor layer. A material having an antiferroelectric property is used as the first insulating layer.

Description

memory element, storage device

[0001] One embodiment of the present invention relates to a memory element or a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Therefore, examples of technical fields related to one embodiment of the present invention include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, testing methods thereof, and methods of using thereof.

[0004] In recent years, development of semiconductor devices such as LSIs, CPUs, and memories (storage devices) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. Furthermore, memories with various storage methods have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage methods include DRAM, SRAM, and flash memory.

[0005] Furthermore, as shown in Non-Patent Document 1, research and development of memories using ferroelectrics is being actively carried out. For next-generation ferroelectric memories, ferroelectric HfO ２ Research on ferroelectric hafnium oxide thin films (Non-Patent Document 3), HfO ２ Research on ferroelectricity of thin films (Non-Patent Document 4), and ferroelectric Hf ０．５ Zr ０．５ O ２ Research related to hafnium oxide is also being actively conducted, including the demonstration of integration of FeRAM (Ferroelectric Random Access Memory) and CMOS using hafnium oxide (Non-Patent Document 5).

[0006] Furthermore, Patent Document 1 discloses a configuration in which, in a MFSFET (Metal Ferroelectric Semiconductor Field Effect Transistor), which is a type of FeFET (Ferroelectric Field Effect Transistor) that uses a ferroelectric material as a gate insulating film, the gate insulating film is provided in contact with an oxide in which a channel is formed.

[0007] Japanese Patent Application Publication No. 7-326683

[0008] T. S. Boescke, et al, “Ferroelectricity in hafnium oxide thin films”, APL99, 2011 Zhen Fan, et al, “Ferroelectricity HfO▲2▼-based materials for next-generation ferroelectric memories”, JOURNAL OF ADVANCED DIELECTRICS, Vol. 6, No. 2, 2016 Jun Okuno, et al., "SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2", VLSI 2020 Akira Toriumi, "Ferroelectricity of HfO2 thin film", The Japan Society of Applied Physics, Vol. 88, No. 9, 2019 T. Francois, et al, “Demonstration of BEOL-compatible ferroelectric Hf▲0.5▼Zr▲0.5▼O▲2▼ scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications”, IEDM 2019

[0009] In recent years, the amount of data handled by electronic devices has tended to increase, and there has been a demand for increased storage capacity. For example, the FeFET shown in Patent Document 1 cannot hold data with three or more values, making it difficult to increase the storage capacity of a storage device using the FeFET.

[0010] An object of one embodiment of the present invention is to provide a memory element or memory device with a large storage capacity. Another object is to provide a memory element or memory device with a small occupation area. Another object is to provide a memory element or memory device with high reliability. Another object is to provide a memory element or memory device with low power consumption. Another object is to provide a novel memory element or memory device. Another object of one embodiment of the present invention is to provide a semiconductor device with a large storage capacity. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device with high reliability. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a novel semiconductor device.

[0011] The problems associated with one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. The problems associated with one embodiment of the present invention do not necessarily solve all of the problems listed above and other problems. One embodiment of the present invention solves at least one of the problems listed above and other problems.

[0012] One embodiment of the present invention is a memory element including: a first electrode having a region overlapping with a semiconductor layer with a first insulating layer interposed therebetween; and a second electrode having a region overlapping with the semiconductor layer with a second insulating layer interposed therebetween; the first electrode and the second electrode have regions overlapping with each other with the first insulating layer, the semiconductor layer, and the second insulating layer interposed therebetween; the semiconductor layer includes an oxide semiconductor; and the first insulating layer has antiferroelectricity.

[0013] Another embodiment of the present invention is a memory element including: a first electrode having a region overlapping with a first region of a semiconductor layer with a first insulating layer interposed therebetween; a second electrode having a region overlapping with the first region with a second insulating layer interposed therebetween; a third electrode electrically connected to the second region of the semiconductor layer; and a fourth electrode electrically connected to the third region of the semiconductor layer, wherein the first electrode and the second electrode have regions overlapping with each other with the first insulating layer, the first region, and the second insulating layer interposed therebetween; the semiconductor layer includes an oxide semiconductor; and the first insulating layer has antiferroelectricity.

[0014] The semiconductor layer preferably contains at least one of indium and zinc. The first insulating layer preferably contains hafnium, and more preferably contains hafnium and zirconium.

[0015] The semiconductor layer preferably contains at least one of hydrogen, nitrogen, phosphorus, fluorine, chlorine, and a noble gas.

[0016] Another embodiment of the present invention is a memory device including a memory array including a plurality of the above memory elements and a driver circuit.

[0017] According to one embodiment of the present invention, a memory element or memory device with a large storage capacity can be provided. Alternatively, a memory element or memory device with a small occupation area can be provided. Alternatively, a memory element or memory device with high reliability can be provided. Alternatively, a memory element or memory device with low power consumption can be provided. Alternatively, a novel memory element or memory device can be provided. Alternatively, a semiconductor device with a large storage capacity can be provided. Alternatively, a semiconductor device with a small occupation area can be provided. Alternatively, a semiconductor device with high reliability can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

[0018] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Therefore, one embodiment of the present invention may not have the effects listed above. The other effects are described below and are not mentioned in this section. Those skilled in the art can derive the other effects from the description in the specification or drawings, etc., and can extract them as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects.

[0019] FIG. 1A is an equivalent circuit diagram of a semiconductor device. FIG. 1B is a cross-sectional schematic diagram showing an example of a transistor configuration. FIG. 1C is a graph showing an example of hysteresis characteristics. FIGS. 2A and 2B are graphs showing an example of hysteresis characteristics. FIG. 3 is a diagram illustrating the crystal structure of hafnium oxide. FIGS. 4A and 4B are diagrams illustrating a model of the orthorhombic crystal structure of HfZrOx. FIG. 5 is a graph showing an example of hysteresis characteristics. FIGS. 6A to 6D are cross-sectional schematic diagrams of a transistor. FIG. 6E is a diagram illustrating the Id-Vg characteristics of a transistor. FIG. 7A is a timing chart for illustrating the operation of the semiconductor device. FIG. 7B is a circuit diagram for illustrating the operation of the semiconductor device. FIG. 8A is a timing chart for illustrating the operation of the semiconductor device. FIG. 8B is a circuit diagram for illustrating the operation of the semiconductor device. FIG. 9A is a timing chart for illustrating the operation of the semiconductor device. FIG. 9B is a circuit diagram for illustrating the operation of the semiconductor device. FIG. 10A is a timing chart for illustrating the operation of the semiconductor device. FIG. 10B is a circuit diagram for explaining the operation of a semiconductor device. FIG. 11A is a block diagram for explaining a configuration example of a semiconductor device. FIG. 11B is a perspective view for explaining a configuration example of a semiconductor device. FIGS. 12A to 12C are views for explaining a configuration example of a transistor. FIGS. 13A and 13B are perspective views showing an example of an electronic component. FIGS. 14A to 14J are views for explaining an example of an electronic device. FIGS. 15A to 15E are views for explaining an example of an electronic device. FIGS. 16A to 16C are views for explaining an example of an electronic device.

[0020] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0021] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0022] In the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size or aspect ratio is not necessarily limited. The drawings are schematic illustrations of ideal examples, and the shapes or values ​​shown in the drawings are not limited.

[0023] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, top views, etc.

[0024] In drawings and the like, arrows indicating the X direction (direction along the X axis), the Y direction (direction along the Y axis), and the Z direction (direction along the Z axis) may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and no distinction is made between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, the Y direction, and the Z direction are directions that intersect with each other. More specifically, the X direction, the Y direction, and the Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, the Y direction, and the Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0025] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment, in the claims, etc. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment, in the claims, etc.

[0026] In this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0027] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0028] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" is not limited to the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed below insulating layer A, the state in which electrode B is formed on the right (or left) side of insulating layer A, the state in which electrode B is formed in front (or rear) of insulating layer A, etc.

[0029] In this specification, the terms "adjacent" and "close to" do not necessarily mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B be in direct contact with each other, and does not exclude the presence of other components (including spaces) between insulating layer A and electrode B.

[0030] In this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" can be replaced with other terms without using them. For example, the term "conductive layer" or "conductive film" can be changed to the term "conductor." Or, the term "conductor" can be changed to the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" can be changed to the term "insulator." Or, the term "insulator" can be changed to the term "insulating layer" or "insulating film."

[0031] Note that voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) of a unit charge in an electrostatic field at a certain point. However, generally, the potential difference between the potential at a certain point and a reference potential (e.g., ground potential) is simply called potential or voltage, and potential and voltage are often used synonymously. For this reason, in this specification and elsewhere, potential may be read as voltage, and voltage may be read as potential, unless otherwise specified.

[0032] In this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0033] In this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Furthermore, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true, and terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Similarly, the reverse is also true, and terms such as "signal" may be changed to the term "potential."

[0034] In this specification and the like, a gate refers to a gate electrode and a part or the whole of a gate wiring. A gate wiring refers to a wiring electrically connected to the gate electrode of at least one transistor.

[0035] The source refers to a part or all of the source region, source electrode, and source wiring. The source region refers to a region of the semiconductor layer whose resistivity is equal to or lower than a certain value. The source electrode refers to a conductive layer including a portion connected to the source region. The source wiring refers to wiring electrically connected to the source electrode of at least one transistor.

[0036] The drain refers to part or all of the drain region, drain electrode, and drain wiring. The drain region refers to a region of the semiconductor layer whose resistivity is below a certain value. The drain electrode refers to a conductive layer that includes a portion connected to the drain region. The drain wiring refers to wiring that is electrically connected to the drain electrode of at least one transistor.

[0037] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0038] In this specification and elsewhere, when referring to counting values ​​and measurement values, terms such as "identical," "same," "equal," or "uniform" (including synonyms thereof) are used, unless otherwise specified, and include an error of plus or minus 20%.

[0039] In this specification and the like, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "A", "b", "_1", "[n]", or "[m, n]" may be added to the reference numeral. For example, the conductive layer 242 may be divided into a conductive layer 242a and a conductive layer 242b.

[0040] Embodiment 1 A semiconductor device 100 according to one embodiment of the present invention will be described. FIG. 1A illustrates an equivalent circuit diagram of the semiconductor device 100. The semiconductor device 100 functions as a memory element (a "memory cell") including a transistor 200. FIG. 1B is a schematic cross-sectional view illustrating a configuration example of the transistor 200.

[0041] The transistor 200 is a field-effect transistor having a back gate. The gate of the transistor 200 is electrically connected to a wiring GL, and the back gate is electrically connected to a wiring BGL (see FIG. 1A). One of the source and the drain of the transistor 200 is electrically connected to a wiring BL, and the other is electrically connected to a wiring SL.

[0042] The transistor 200 includes a conductive layer 201 that functions as a gate, a dielectric layer 202 that functions as a gate insulating layer, a semiconductor layer 203 that functions as a semiconductor layer in which a channel is formed, a dielectric layer 204 that functions as a gate insulating layer on the back gate side, a conductive layer 205 that functions as a back gate, a conductive layer 206 a that functions as one of a source and a drain, and a conductive layer 206 b that functions as the other of the source and the drain (see FIG. 1B ).

[0043] The terms "gate" and "back gate" can be used interchangeably. For example, when one of the conductive layer 201 or the conductive layer 205 is referred to as a "gate" or a "gate electrode," the other may be referred to as a "back gate" or a "back gate electrode." Furthermore, in this specification and the like, one of the conductive layer 201 or the conductive layer 205 may be referred to as a "first electrode," and the other may be referred to as a "second electrode."

[0044] The conductive layer 206a functions as one of a source electrode and a drain electrode. The conductive layer 206b functions as the other of the source electrode and the drain electrode. In this specification and the like, one of the conductive layer 206a and the conductive layer 206b may be referred to as a "third electrode," and the other may be referred to as a "fourth electrode."

[0045] The conductive layer 201 and the semiconductor layer 203 have an overlapping region with the dielectric layer 202 interposed therebetween. The conductive layer 205 and the semiconductor layer 203 have an overlapping region with the dielectric layer 204 interposed therebetween. The region of the semiconductor layer 203 that overlaps with the conductive layer 201 functions as a channel formation region 213. The conductive layer 201 and the conductive layer 205 have an overlapping region with the dielectric layer 202, the semiconductor layer 203, and the dielectric layer 204 interposed therebetween. In other words, the conductive layer 201 and the conductive layer 205 have an overlapping region with the channel formation region 213 interposed therebetween.

[0046] In addition, in the semiconductor layer 203, a region where the semiconductor layer 203 and the conductive layer 206a overlap functions as one of the source region and the drain region. In the semiconductor layer 203, a region where the semiconductor layer 203 and the conductive layer 206b overlap functions as the other of the source region and the drain region of the semiconductor layer 203. In this specification and the like, the channel formation region may be referred to as a "first region," one of the source region and the drain region may be referred to as a "second region," and the other of the source region and the drain region may be referred to as a "third region." Therefore, one of the third electrode and the fourth electrode is electrically connected to the second region, and the other is electrically connected to the third region.

[0047] The dielectric layer 202 of the transistor 200 included in the semiconductor device 100 is an antiferroelectric, which is a type of material that can exhibit ferroelectricity. Antiferroelectrics exhibit hysteresis characteristics when an electric field above or below a certain level is applied. FIG. 1C is a graph showing an example of the hysteresis characteristics of an antiferroelectric. The horizontal axis of FIG. 1C represents the electric field strength applied to the antiferroelectric, and the vertical axis represents polarization. In FIG. 1C, the minimum polarization at an electric field strength of V1 is shown as polarization 63a, and the maximum polarization is shown as polarization 64a. In FIG. 1C, the minimum polarization at an electric field strength of V2 is shown as polarization 63b, and the maximum polarization is shown as polarization 64b. The hysteresis characteristics of a material that can exhibit ferroelectricity can be measured using a capacitor element using a material that can exhibit ferroelectricity as a dielectric layer.

[0048] The transistor 200 according to one embodiment of the present invention functions as an FeFET using an antiferroelectric, which is a type of material that can have ferroelectricity, in the dielectric layer 202 that functions as a gate insulating layer. The threshold voltage of the FeFET is determined according to the polarization generated in the gate insulating layer. The semiconductor device 100 according to one embodiment of the present invention can realize a memory element that can store multi-level data by using the polarizations 63a, 63b, 64a, and 64b generated in the antiferroelectric.

[0049] Here, a material that can have ferroelectricity will be explained. In this specification and the like, a material that can have ferroelectricity refers to a material that can have hysteresis characteristics in the relationship between the strength of an electric field (electric field intensity) applied to the material and the magnitude of polarization, or a material that can spontaneously generate polarization even in the absence of an external electric field (an electric field applied to the material from the outside). Therefore, a material that can have ferroelectricity includes a material that has one or more of ferroelectricity, antiferroelectricity, and ferrielectricity.

[0050] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, and a device having such a ferroelectric layer may be referred to as a ferroelectric device.

[0051] As will be described later, it is presumed that the manifestation of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. The crystal structure may change depending on the film formation conditions of the ferroelectric layer. Therefore, in this specification and the like, a material that can be used to form a ferroelectric layer is called a material that can have ferroelectricity.

[0052] In this specification and the like, a material having ferroelectricity or an insulator containing a material having ferroelectricity may be referred to as a ferroelectric. A material having antiferroelectricity or an insulator containing a material having antiferroelectricity may be referred to as an antiferroelectric. A material having ferrielectricity or an insulator containing a material having ferrielectricity may be referred to as a ferrielectric.

[0053] A ferroelectric is an insulator that is polarized even in the absence of an external electric field. FIG. 2A shows a graph illustrating an example of the hysteresis characteristics of a ferroelectric. In FIG. 2A, the horizontal axis represents the electric field strength applied to the ferroelectric, and the vertical axis represents the polarization of the ferroelectric. Polarization 61 shown in FIG. 2A is the minimum polarization when the electric field strength is 0, and polarization 62 shown in FIG. 2A is the maximum polarization when the electric field strength is 0.

[0054] Antiferroelectrics are insulators that exhibit little or no spontaneous polarization in the absence of an external electric field, but exhibit ferroelectricity when an electric field above or below a certain level is applied. In antiferroelectrics, the polarization directions of adjacent domains are antiparallel, resulting in an overall remanent polarization of nearly zero. Therefore, the remanent polarization after application of an electric field is nearly zero, but when a high electric field is applied, the antiferroelectric exhibits the same properties as a ferroelectric. In other words, when the electric field strength is close to zero, the domains in the antiferroelectric have a predominantly tetragonal crystal structure, whereas when the absolute value of the electric field strength is high, the domains in the antiferroelectric have a predominantly orthorhombic crystal structure.

[0055] FIG. 1C shows a graph illustrating an example of the hysteresis characteristic of an antiferroelectric. In FIG. 1C, the horizontal axis represents the electric field strength applied to the antiferroelectric, and the vertical axis represents the polarization of the antiferroelectric. Polarization 63a shown in FIG. 1C is the minimum polarization when the electric field strength is V1, and polarization 64a shown in FIG. 1C is the maximum polarization when the electric field strength is V1. Polarization 63b shown in FIG. 1C is the minimum polarization when the electric field strength is V2, and polarization 64b shown in FIG. 1C is the maximum polarization when the electric field strength is V2. When the electric field strength is zero, the polarization is zero or close to zero.

[0056] A ferroelectric material is an insulator that exhibits a first ferroelectricity when there is no external electric field or when the absolute value of the electric field strength is small, exhibits a second ferroelectricity different from the first ferroelectricity when an electric field of a certain level or higher is applied, and exhibits a third ferroelectricity different from the first and second ferroelectricities when an electric field of a certain level or lower is applied.

[0057] A graph showing an example of the hysteresis characteristic of a ferrielectric is shown in Fig. 2B. In Fig. 2B, the horizontal axis represents the electric field strength applied to the ferrielectric, and the vertical axis represents the polarization of the ferrielectric. Polarization 65a shown in Fig. 2B is the minimum polarization when the electric field strength is 0, and polarization 66a shown in Fig. 2B is the maximum polarization when the electric field strength is 0. Polarization 65b shown in Fig. 2B is the minimum polarization when the electric field strength is V3, and polarization 66b shown in Fig. 2B is the maximum polarization when the electric field strength is V3. Polarization 65c shown in Fig. 2B is the minimum polarization when the electric field strength is V4, and polarization 66c shown in Fig. 2B is the maximum polarization when the electric field strength is V4.

[0058] Note that a material that can have ferroelectricity may have a higher dielectric constant than a paraelectric material. By using a material that can have ferroelectricity as the gate insulating layer of the transistor 200, the operating voltage of the transistor 200 can be reduced. Therefore, the power consumption of the transistor 200 and a semiconductor device including the transistor 200 can be reduced. Alternatively, the operating speed of the transistor 200 can be increased. Alternatively, the area occupied by the transistor 200 can be reduced.

[0059] Furthermore, by utilizing the remanent polarization of a ferroelectric material, a memory element can be realized, and by utilizing an antiferroelectric material or a ferroelectric material, a memory element capable of storing multi-value data can be realized.

[0060] Materials that can have ferroelectric properties include metal oxides such as hafnium oxide, zirconium oxide, and HfZrOx (x is a real number greater than 0).

[0061] Furthermore, examples of materials that can have ferroelectricity include metal oxides in which element J1 (here, element J1 is one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to hafnium oxide. Here, the atomic ratio of hafnium atoms to element J1 can be set appropriately, and for example, the atomic ratio of hafnium atoms to element J1 may be set to 1:1 or close to 1:1.

[0062] Furthermore, examples of materials that can have ferroelectricity include metal oxides in which element J2 (here, element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to zirconium oxide. The atomic ratio of zirconium atoms to element J2 can be set appropriately, and for example, the atomic ratio of zirconium atoms to element J2 may be set to 1:1 or close to 1:1.

[0063] Furthermore, as a material that can have ferroelectricity, PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0064] Furthermore, as a material that can have ferroelectricity, for example, a mixture or compound made of a plurality of metal oxides selected from the materials listed above can be used.

[0065] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum (Al), gallium (Ga), indium (In), etc. Furthermore, element M2 is one or more elements selected from boron (B), rare earth elements (scandium (Sc), yttrium (Y), and lanthanides (15 elements from lanthanum (La) to lutetium (Lu))), and actinides (15 elements from actinium (Ac) to lawrencium (Lr)). In particular, element M2 is preferably one or more elements selected from boron (B), scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), neodymium (Nd), europium (Eu), etc. It is preferable that the ratio of the sum of the number of atoms of elements M1 and M2 to the number of nitrogen atoms is 1:1 or close to 1:1. Note that "nearby" includes a range of ±30% of the desired atomic ratio. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. For example, the number of atoms of element M1 is preferably larger than the number of atoms of element M2, and more preferably 1.5 times or more the number of atoms of element M2. Note that the ratio of the number of atoms of element M1 to the number of atoms of element M2 is preferably within a range in which the metal nitride can form a solid solution. Note that when two or more elements such as aluminum, gallium, and indium are selected as element M1, a metal nitride having element M1 and nitrogen may exhibit ferroelectricity even without containing element M2.

[0066] Representative examples of metal nitrides containing elements M1, M2, and nitrogen include aluminum scandium nitride (Al １−ａ Sc ａ N ｂ (where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1), Al—Ga—Sc nitride (Al １−ｃ−ｄ Ga ｃ Sc ｄ N ｂ (c and d are each a positive real number, c+d is greater than 0 and less than 0.5, and b is 1 or a value close to 1.)), Ga—Sc nitride (Ga １−ｅ Scｅ N ｂ (e is a real number greater than 0 and less than 1, and b is 1 or a value close to 1.) In other words, materials that can have ferroelectric properties include materials containing aluminum nitride and / or scandium nitride.

[0067] In some cases, Al-Ga-Sc nitride may be preferable to aluminum scandium nitride as a material that can exhibit ferroelectricity. The ionic radius of gallium is larger than that of aluminum and smaller than that of scandium. Therefore, it is speculated that adding gallium to aluminum scandium nitride can adjust the crystal structure and lattice constant of aluminum scandium nitride so that ferroelectricity is more likely to be exhibited. Therefore, Al-Ga-Sc nitride is expected to exhibit ferroelectricity. Furthermore, the band gap of gallium nitride is smaller than that of aluminum nitride and larger than that of scandium nitride. Therefore, adding gallium to aluminum scandium nitride improves the insulating properties of scandium aluminum nitride, making it suitable for use in ferroelectric devices, as described below.

[0068] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides having elements M1, M3, and nitrogen. Here, element M1 is one or more selected from aluminum (Al), gallium (Ga), indium (In), etc. Element M3 is one or more selected from titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), etc. In metal nitrides of titanium, zirconium, hafnium, vanadium, niobium, tantalum, or chromium, the valence of these metal elements is +3. Therefore, even in metal nitrides having elements M1, M3, and nitrogen, the valence of element M3 can be +3. Therefore, when the ratio of the sum of the number of atoms of elements M1 and M3 to the number of nitrogen atoms is 1:1 or close to 1, the electrical neutrality of the metal nitride may be maintained.

[0069] The metal nitride having the element M1, the element M3, and nitrogen may also contain an element M4. Here, the element M4 is an element capable of maintaining the electrical neutrality of the metal nitride. The element M4 is, for example, an element that easily assumes a valence of +1 or an element that easily assumes a valence of +2. Specifically, the element M4 is one or more elements selected from sodium (Na), potassium (K), rubidium (Ru), cesium (Cs), magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), and the like. Titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, and tungsten, which are exemplified as the element M3, can assume a valence of +4 or more. Therefore, it is presumed that the electrical neutrality of the metal nitride is maintained by including the element M4 capable of maintaining the electrical neutrality of the metal nitride. The ratio of the number of atoms of element M3 to element M4 can be appropriately set depending on the type of element selected as element M3 or element M4. For example, when element M4 is an element that easily assumes a +2 valence (e.g., Mg, Ca, Sr, Zn, Cd, etc.) and element M3 is an element that can assume a +4 valence (e.g., Ti, Zr, Hf, etc.), the ratio of the number of atoms of element M4 to the number of atoms of element M3 is preferably 1:1 or close to 1:1. Alternatively, when element M4 is an element that easily assumes a +2 valence and element M3 is an element that can assume a +5 valence (e.g., V, Nb, Ta, etc.), the ratio of the number of atoms of element M4 to the number of atoms of element M3 is preferably 2:1 or close to 2:1. Alternatively, when element M4 is an element (such as Na, K, Ru, or Cs) that easily assumes a valence of +1 and element M3 is an element that can assume a valence of +5, the ratio of the number of atoms of element M4 to the number of atoms of element M3 is preferably 1:1 or close to 1:1. The preferred ratio of the number of atoms of element M3 to the number of atoms of element M4 is not limited to the above. The crystal structure of metal nitrides can change depending on the atomic ratio of metal to nitrogen. Therefore, it is advisable to appropriately set the ratio of the number of atoms of element M3 to element M4 so that ferroelectricity is exhibited. Furthermore, the ratio of the number of atoms of element M1, element M3, and element M4 can be appropriately set. For example, it is preferable that the number of atoms of element M1 is greater than the sum of the numbers of atoms of element M3 and element M4.

[0070] Furthermore, the metal nitride having the element M1, the element M2, and nitrogen may contain the element M3 or the element M4. In this case, the ratio of the number of atoms of the element M3 or the element M4 to the sum of the number of atoms of the element M1 and the element M2 is preferably 0.05 or less, more preferably 0.02 or less. This makes it possible to suppress the amount of defects formed to maintain the electrical neutrality of the metal nitride. By suppressing the amount of defects, the crystallinity of the metal nitride is improved, and ferroelectricity is more likely to be exhibited.

[0071] Furthermore, a metal nitride having element M1, element M3, and nitrogen may contain element M2. In this case, there is no particular limitation on the ratio of the sum of the numbers of atoms of element M1 and element M3 to the number of atoms of element M2. This is because the electrical neutrality of the metal nitride is maintained even if element M2 is contained in the metal nitride.

[0072] Furthermore, a metal nitride having elements M1, M3, M4, and nitrogen may contain element M2. In this case, there is no particular limitation on the ratio of the sum of the numbers of atoms of elements M1, M3, and M4 to the number of atoms of element M2. This is because the electrical neutrality of the metal nitride is maintained even if element M2 is contained in the metal nitride.

[0073] Furthermore, as a material that can have ferroelectricity, for example, a mixture or compound made of a plurality of metal nitrides selected from the materials listed above can be used.

[0074] Among these, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferable as a material that can have ferroelectricity because it can maintain ferroelectricity even when processed into a thin film of several nanometers. By using a ferroelectric layer that can be thinned as a gate insulating layer, etc., a semiconductor device including a semiconductor element such as a miniaturized transistor can be manufactured.

[0075] Here, the crystal structure of hafnium oxide, which is one of the materials that can be used for the gate insulating layer, will be described with reference to FIG. 3. FIG. 3 shows the crystal structure of hafnium oxide (HfO in this embodiment). ２3 is a model diagram illustrating the crystal structure of hafnium oxide. Hafnium oxide is known to have a variety of crystal structures, such as the cubic system (cubic, space group: Fm-3m) shown in FIG. 3 and the tetragonal system (tetragonal, space group: P4 ２ / nmc), orthorhombic, space group: Pbc2 ２ ), and monoclinic, space group: P2 １ / c). Furthermore, as shown in Figure 3, each of the above-mentioned crystal structures can undergo a phase change. For example, by doping hafnium oxide with zirconium to form a composite material, the crystal structure of hafnium oxide, which is mainly monoclinic, can be changed to a crystal structure mainly orthorhombic.

[0076] When the above-mentioned composite material is formed by alternately depositing hafnium oxide and zirconium oxide in a composition ratio of approximately 1:1 using an atomic layer deposition (ALD) method or the like, the composite material has an orthorhombic crystal structure. Alternatively, the composite material has an amorphous structure. The amorphous structure can then be converted into an orthorhombic crystal structure by subjecting the composite material to a heat treatment or the like. Note that the orthorhombic crystal structure may change to a monoclinic crystal structure. When imparting ferroelectricity to the above-mentioned composite material, an orthorhombic crystal structure is preferable to a monoclinic crystal structure.

[0077] Here, a model of the orthorhombic crystal structure of HfZrOx will be described with reference to FIGS. 4A and 4B.

[0078] 4A and 4B show HfZrOx, where Hf ０．５ Zr ０．５ O ２ 4A and 4B are model diagrams of the crystal structure of HfO. In addition, the directions of the a-axis, b-axis, and c-axis are also shown in FIGS. 4A and 4B. ２ orthorhombic structure of Pca2 １ ) is a model in which the atomic arrangement has been optimized using first-principles calculations.

[0079] 4A and 4B, it can be seen that hafnium and zirconium are bonded to each other via oxygen. This can be formed by alternately depositing hafnium and zirconium films by the ALD method.

[0080] In the orthorhombic structure, HfZrOx can have either the atomic arrangement shown in FIG. 4A or the atomic arrangement shown in FIG. 4B. Therefore, an externally applied electric field displaces some of the oxygen atoms in HfZrOx, causing polarization inside the HfZrOx. Here, some of the oxygen atoms are displaced in the c-axis direction, and polarization also occurs in the c-axis direction. Furthermore, by changing the direction or strength of the electric field, some of the oxygen atoms in HfZrOx move, changing the sign of the polarization inside the HfZrOx.

[0081] For example, at minimum polarization (polarization 61 shown in FIG. 2A), the atoms in HfZrOx are arranged as shown in FIG. 4A. At maximum polarization (polarization 62 shown in FIG. 2A), the atoms in HfZrOx are arranged as shown in FIG. 4B.

[0082] The crystalline structure of the gate insulating layer or the like may be at least partially a single crystalline structure. The crystalline structure of the gate insulating layer or the like may be one or more selected from cubic, tetragonal, orthorhombic, and monoclinic. In particular, the gate insulating layer or the like preferably has an orthorhombic crystalline structure because ferroelectricity is exhibited. Alternatively, the gate insulating layer or the like may have an amorphous structure. Alternatively, the gate insulating layer or the like may have a composite structure having an amorphous structure and a crystalline structure.

[0083] Furthermore, for example, by doping hafnium oxide with zirconium to form a composite material, it may be possible to change the monoclinic-based crystalline structure of hafnium oxide to a tetragonal-based crystalline structure. In this case, the composite material may have antiferroelectricity. In other words, when imparting antiferroelectricity to the composite material, a tetragonal crystalline structure is preferable to a monoclinic crystalline structure.

[0084] For example, at the minimum polarization when the electric field strength is V2 (polarization 63b shown in FIG. 1C), the atoms in HfZrOx are arranged as shown in FIG. 4A. At the maximum polarization when the electric field strength is V1 (polarization 64a shown in FIG. 1C), the atoms in HfZrOx are arranged as shown in FIG. 4B. At the polarization when the electric field strength is 0, the minimum polarization when the electric field strength is V1 (polarization 63a shown in FIG. 1C), and the maximum polarization when the electric field strength is V2 (polarization 64b shown in FIG. 1C), the atoms in HfZrOx are arranged in the tetragonal system (space group: P4) shown in FIG. ２ / nmc) is mainly used.

[0085] In the composite material, it is preferable that the zirconium content relative to hafnium is large. For example, the composite material may have a composition of Hf:Zr=1:2 [atomic ratio] or a composition thereof in the vicinity thereof, or a composition of Hf:Zr=1:3 [atomic ratio] or a composition thereof in the vicinity thereof. Note that a composition in the vicinity thereof includes a range of ±30% of the desired atomic ratio. Increasing the zirconium content relative to hafnium makes it easier for the composite material to exhibit antiferroelectricity.

[0086] <<Hysteresis Characteristics of Antiferroelectrics>> Here, the hysteresis characteristics of antiferroelectrics will be described in detail. FIG. 5 is a graph showing an example of hysteresis characteristics. The hysteresis characteristics can be measured using a capacitance element that uses an antiferroelectric as its dielectric layer. In FIG. 5, the horizontal axis represents the voltage (electric field) applied to the antiferroelectric. This voltage is the potential difference between one electrode and the other electrode of a capacitance element that uses an antiferroelectric as its dielectric layer. The electric field strength can be found by dividing this potential difference by the thickness of the dielectric layer.

[0087] In Figure 5, the vertical axis represents the polarization of the dielectric layer. Positive polarization indicates that the positive charges in the dielectric layer are biased toward one electrode of the capacitance element, and negative charges are biased toward the other electrode of the capacitance element. On the other hand, negative polarization indicates that the negative charges in the dielectric layer are biased toward one electrode of the capacitance element, and positive charges are biased toward the other electrode of the capacitance element.

[0088] Furthermore, the polarization shown on the vertical axis of the graph in Figure 5 may be positive when negative charges are biased toward one electrode side of the capacitance element and positive charges are biased toward the other electrode side of the capacitance element, and may be negative when positive charges are biased toward one electrode side of the capacitance element and negative charges are biased toward the other electrode side of the capacitance element.

[0089] An antiferroelectric exhibits hysteresis characteristics when a positive voltage above a certain level or a negative voltage below a certain level is applied. The change in polarization when a positive voltage is applied to an antiferroelectric can be represented by curves 51 and 52. Curves 51 and 52 intersect when the voltage is 0 V and when the voltage is the saturation polarization voltage VSP.

[0090] After applying 0 V or a negative voltage to the antiferroelectric, if the voltage applied to the antiferroelectric is increased in the positive direction, the polarization of the ferroelectric layer increases in the positive direction according to curve 51. After applying a saturation polarization voltage VSP or a voltage higher than this to the ferroelectric layer, if the voltage applied to the ferroelectric layer is decreased toward 0 V, the polarization of the antiferroelectric decreases according to curve 52. When the voltage applied to the ferroelectric layer becomes 0 V, the polarization also becomes 0. When a voltage Vm is applied, the polarization on curve 52 is called "polarization Pr1" and the polarization on curve 51 is called "polarization Pr2."

[0091] Furthermore, the change in polarization when a negative voltage is applied to the antiferroelectric can be represented by curves 53 and 54. Curves 53 and 54 intersect when the voltage is 0 V and when the voltage is the saturated polarization voltage −VSP.

[0092] After applying 0 V or a positive voltage to the antiferroelectric, if the voltage applied to the antiferroelectric is increased in the negative direction, the polarization of the ferroelectric layer increases in the negative direction according to curve 54. After applying a voltage of -VSP or less to the ferroelectric layer, if the voltage applied to the antiferroelectric is decreased toward 0 V, the polarization of the antiferroelectric approaches 0 according to curve 53. When the voltage applied to the ferroelectric layer becomes 0 V, the polarization also becomes 0. When a voltage of -Vm is applied, the polarization on curve 54 is called "polarization Pr3" and the polarization on curve 53 is called "polarization Pr4".

[0093] The saturated polarization voltage VSP may be referred to as the “positive saturated polarization voltage” or the “first saturated polarization voltage,” and the saturated polarization voltage −VSP may be referred to as the “negative saturated polarization voltage” or the “second saturated polarization voltage.” The absolute values ​​of the first saturated polarization voltage and the second saturated polarization voltage may be the same or different.

[0094] <<Operation Example of Memory Cell>> Next, the operation of the semiconductor device 100 will be described. The semiconductor device 100 according to one aspect of the present invention functions as a memory cell capable of holding multi-level data. First, the relationship between the polarization of the antiferroelectric material and the Id-Vg characteristics of the transistor 200 will be described.

[0095] <Relationship Between Polarization of Antiferroelectric Material and Id-Vg Characteristics> The relationship between the polarization of the antiferroelectric material used as the dielectric layer 202 of the transistor 200 and the threshold voltage of the transistor 200 will be described with reference to the drawings.

[0096] 6A to 6D are schematic cross-sectional views of the transistor 200, enlarging the vicinity of the dielectric layer 202 and the channel formation region 213. Also, Fig. 6A to 6D schematically show the polarization of the dielectric layer 202, which is an antiferroelectric, and the carrier concentration in the channel formation region 213.

[0097] 6E is a diagram illustrating the Id-Vg characteristics of the transistor 200 when the voltage between the source and drain (also referred to as "drain voltage" or "Vd") is constant. The horizontal axis of FIG. 6E represents the voltage between the source and gate (also referred to as "gate voltage" or "Vg"), and the vertical axis represents the current flowing between the source and drain (also referred to as "drain current" or "Id").

[0098] 6E, characteristic 290 indicates the Id-Vg characteristic of transistor 200 when no polarization occurs in dielectric layer 202. Transistor 200 is a normally-on transistor in which a large amount of Id flows when Vg is 0 V.

[0099] 6E, a characteristic 291 indicates the Id-Vg characteristic when the polarization of the dielectric layer 202 is Pr1. Also, FIG. 6A is a schematic diagram showing the polarization and carrier concentration when Vg is 0 V in the characteristic 291.

[0100] Because polarization Pr1 is a large positive polarization, the carrier concentration in the channel formation region 213 of the semiconductor layer 203 increases. As a result, the Id-Vg characteristic of characteristic 290 shifts significantly in the negative direction to become characteristic 291. That is, the threshold voltage of the transistor 200 shifts significantly in the negative direction. In FIG. 6E , Id when Vg in characteristic 291 is 0 V is indicated as current Id1.

[0101] 6E, a characteristic 292 indicates the Id-Vg characteristic when the polarization of the dielectric layer 202 is polarization Pr2. Also, FIG. 6B is a schematic diagram showing the polarization and carrier concentration when Vg is 0 V in the characteristic 292.

[0102] Because polarization Pr2 is a positive polarization smaller than polarization Pr1, the increase in carrier concentration in the channel formation region 213 of the semiconductor layer 203 is smaller than in the case of polarization Pr1. Therefore, although the effect is smaller than when the polarization of the dielectric layer 202 is polarization Pr1, the Id-Vg characteristic of characteristic 290 shifts in the negative direction to become characteristic 292. In other words, although the shift amount is smaller than when polarization Pr1 is used, the threshold voltage of the transistor 200 shifts in the negative direction. In Figure 6E, Id when Vg in characteristic 292 is 0 V is shown as current Id2.

[0103] 6E, a characteristic 293 indicates the Id-Vg characteristic when the polarization of the dielectric layer 202 is polarization Pr3. Also, FIG. 6C is a schematic diagram showing the polarization and carrier concentration when Vg is 0 V in the characteristic 293.

[0104] Because polarization Pr3 is negative, the carrier concentration in the channel formation region 213 of the semiconductor layer 203 decreases. As a result, the Id-Vg characteristic of characteristic 290 shifts in the positive direction to characteristic 293. That is, the threshold voltage of the transistor 200 shifts in the positive direction. In FIG. 6E , Id when Vg in characteristic 293 is 0 V is shown as current Id3.

[0105] 6E, a characteristic 294 indicates the Id-Vg characteristic when the polarization of the dielectric layer 202 is Pr4. Also, FIG. 6D is a schematic diagram showing the polarization and carrier concentration when Vg is 0 V in the characteristic 294.

[0106] Because polarization Pr4 is a more negative polarization than polarization Pr3, the carrier concentration in the channel formation region 213 of the semiconductor layer 203 is significantly reduced. As a result, the Id-Vg characteristic of characteristic 290 is significantly shifted in the positive direction to become characteristic 294. That is, the threshold voltage of the transistor 200 is significantly shifted in the positive direction. In FIG. 6E , Id when Vg in characteristic 294 is 0 V is shown as current Id4.

[0107] 6A to 6E, the Id-Vg characteristics of the transistor 200 can be changed depending on the polarization of the dielectric layer 202. In other words, the threshold voltage of the transistor 200 can be controlled by controlling the polarization of the dielectric layer 202. Furthermore, by using an antiferroelectric material for the dielectric layer 202, it is possible to control the realization of four threshold voltages in one transistor 200. Therefore, the semiconductor device 100 including the transistor 200 can function as a memory cell capable of holding four-level data.

[0108] For example, when writing four values ​​of data "0" to "3" into the semiconductor device 100 functioning as a memory cell, the polarization of the dielectric layer 202 can be set to polarization Pr1 when writing data "0", the polarization of the dielectric layer 202 can be set to polarization Pr2 when writing data "1", the polarization of the dielectric layer 202 can be set to polarization Pr3 when writing data "2", and the polarization of the dielectric layer 202 can be set to polarization Pr4 when writing data "3".

[0109] Furthermore, when Vg is 0 V, Id becomes any one of current Id1, current Id2, current Id3, and current Id4 depending on the polarization of the dielectric layer 202. Therefore, by measuring Id when Vg is 0 V, it is possible to read data written in the memory cell.

[0110] In addition to the characteristics 291 to 294, by using the characteristic 290, which is the Id-Vg characteristic when no polarization occurs in the dielectric layer 202, it is also possible to realize a memory cell capable of holding five-level data.

[0111] The transistor 200 needs to allow Id to flow when Vg is 0 V, regardless of whether the polarization of the dielectric layer 202 is one of polarizations Pr1 to Pr4. The transistor 200 is preferably a normally-on transistor in which Id flows when Vg is 0 V, regardless of whether the polarization of the dielectric layer 202 is one of polarizations Pr1 to Pr4.

[0112] <Erase Operation> Before writing data to the semiconductor device 100 functioning as a memory cell, the data must be erased, that is, the polarization of the dielectric layer 202 is set to zero.

[0113] 7A is a timing chart for explaining the erase operation. 7B is a circuit diagram showing the state of the semiconductor device 100 during period T11. In circuit diagrams and the like, in order to clearly show the potential of a wiring or the like, a symbol indicating the potential of the wiring may be written adjacent to the wiring. Furthermore, a symbol indicating the potential may be written in a box around a wiring or the like in which a potential change has occurred.

[0114] In period T11, a common potential COM (0 V) is supplied to the wiring GL and the wiring BGL, so that the gate and back gate of the transistor 200 are at the same potential. It is also preferable that the wiring BL and the wiring SL are also at the common potential COM. As shown in FIG. 5 , the potential difference between the gate and the back gate disappears (the potential difference becomes zero), and thus the polarization of the dielectric layer 202 disappears (the polarization becomes zero). Note that the horizontal axis in FIG. 5 corresponds to the potential difference between the gate and the back gate when the back gate is used as a reference. In other words, it corresponds to the potential difference between the wiring GL and the wiring BGL.

[0115] <Write Operation 1> Next, an operation of writing data "0" to the semiconductor device 100 functioning as a memory cell will be described. Fig. 8A is a timing chart for explaining the write operation. Fig. 8B is a circuit diagram showing the state of the semiconductor device 100 in a period T22.

[0116] After the erase operation, the potential of the wiring BGL is set to potential VbgL during period T21. Note that potential VbgL is lower than the common potential COM. The wiring GL is left at the common potential COM. Then, during period T21, voltage Vm is applied to the dielectric layer 202. Voltage Vm is the potential difference between the common potential COM and potential VbgL when the wiring BGL is used as the reference. Note that voltage Vm can be expressed as voltage Vm = common potential COM - potential VbgL.

[0117] During the period T21, the polarization of the dielectric layer 202 changes along the curve 51 and becomes the polarization Pr2 (see FIG. 5). That is, data "1" is written in the semiconductor device 100.

[0118] Subsequently, in a period T22, the potential of the wiring BGL is kept at the potential VbgL, and the potential of the wiring GL is set to the potential VgH. The potential VgH is set to a potential that satisfies the relationship: potential VgH >= saturated polarization voltage VSP + potential VbgL. That is, the potential VgH is a potential that applies a voltage equal to or higher than the saturated polarization voltage VSP to the dielectric layer 202.

[0119] Next, during period T23, the potential of the wiring GL is set to the common potential COM. During period T23, the polarization of the dielectric layer 202 changes along curve 52 and becomes polarization Pr1. That is, data "0" is written to the semiconductor device 100. Also, during period T23, the potential difference between the wiring GL and the wiring BGL becomes voltage Vm. Therefore, voltage Vm is applied to the dielectric layer 202.

[0120] After the period T23, the polarization Pr1 is maintained by continuing to apply the voltage Vm to the dielectric layer 202. That is, the data "0" is held in the semiconductor device 100. Note that, in the process of writing the data "0", the data "1" is written in the semiconductor device 100 in the period T21. After the period T21, the polarization Pr2 is maintained by continuing to apply the voltage Vm to the dielectric layer 202. That is, the data "1" is held in the semiconductor device 100.

[0121] <Write Operation 2> Next, an operation of writing data "3" to the semiconductor device 100 functioning as a memory cell will be described. Fig. 9A is a timing chart for explaining the write operation. Fig. 9B is a circuit diagram showing the state of the semiconductor device 100 in a period T32.

[0122] After the erase operation, the potential of the wiring BGL is set to potential VbgH in period T31. Note that potential VbgH is higher than the common potential COM. The wiring GL is left at the common potential COM. Then, in period T31, a voltage -Vm is applied to the dielectric layer 202. The voltage -Vm is the potential difference between the common potential COM and the potential VbgL when the wiring BGL is used as the reference. The voltage -Vm can be expressed as voltage -Vm = common potential COM - potential VbgH.

[0123] During the period T31, the polarization of the dielectric layer 202 changes along the curve 54 to become the polarization Pr3 (see FIG. 5). That is, data "2" is written in the semiconductor device 100.

[0124] Subsequently, in a period T32, the potential of the wiring BGL is kept at the potential VbgH, and the potential of the wiring GL is set to the potential VgL. The potential VgL is set to a potential that satisfies the relationship: potential VgL<=saturation polarization voltage−VSP+potential VbgH. That is, the potential VgL is a potential that applies a negative voltage whose absolute value is equal to or greater than the saturated polarization voltage VSP to the dielectric layer 202.

[0125] Next, in period T33, the potential of the wiring GL is set to the common potential COM. In period T33, the polarization of the dielectric layer 202 changes along curve 53 and becomes polarization Pr4. That is, data "3" is written to the semiconductor device 100. Also, in period T33, the potential difference between the wiring GL and the wiring BGL becomes voltage -Vm. Therefore, voltage -Vm is applied to the dielectric layer 202.

[0126] After the period T33, the voltage -Vm is continuously applied to the dielectric layer 202, thereby maintaining the polarization Pr4. That is, the data "3" is held in the semiconductor device 100. In the process of writing the data "3", the data "2" is written in the semiconductor device 100 in the period T31. After the period T31, the voltage -Vm is continuously applied to the dielectric layer 202, thereby maintaining the polarization Pr3. That is, the data "2" is held in the semiconductor device 100.

[0127] In this manner, data can be written to the semiconductor device 100 .

[0128] <Read Operation> Next, a description will be given of a read operation of data held in the semiconductor device 100 functioning as a memory cell. Fig. 10A is a timing chart for explaining the read operation. Fig. 10B is a circuit diagram showing the state of the semiconductor device 100 in a period T41.

[0129] Reading of data held by the semiconductor device 100 can be achieved by generating a potential difference between the wiring SL and the wiring BL while maintaining the potentials of the wiring GL and the wiring BGL, and detecting the current flowing through the wiring BL or the current flowing through the wiring SL.

[0130] Specifically, in the period T41, the wiring SL is supplied with a potential V Ｒ The potential V Ｒ is a potential that makes the potential difference between the wiring SL and the wiring BL equal to or less than the voltage Vm, preferably equal to or less than half the voltage Vm. If the potential difference between the wiring SL and the wiring BL is too large, it may affect the polarization of the dielectric layer 202. Therefore, it is preferable that the potential difference between the wiring SL and the wiring BL is small.

[0131] For example, when a voltage Vm is applied to the line SL, if the value of Id at this time is the same as the current Id1, it can be determined that the semiconductor device 100 holds data "0." Furthermore, if the current value of Id is the same as the current Id4, it can be determined that the semiconductor device 100 holds data "3."

[0132] Furthermore, to achieve a stable read operation, it is preferable that the current difference between current Id1 and current Id2, the current difference between current Id2 and current Id3, and the current difference between current Id3 and current Id4 are equal. That is, it is preferable that the current values ​​of current Id1, current Id2, current Id3, and current Id4 are equally spaced. Therefore, it is preferable that the polarizations Pr1 to Pr4 of the dielectric layer 202 are also equally spaced.

[0133] The values ​​of polarization Pr1 to Pr4 can be controlled by voltage Vm and voltage −Vm. As described above, voltage Vm is the potential difference between wiring GL and wiring BGL. When reading data from the semiconductor device 100, since wiring GL is at the common potential COM (0 V), voltage Vm can be controlled by the value of potential VbgL supplied to wiring BGL. Similarly, voltage −Vm can be controlled by the value of potential VbgH supplied to wiring BGL. By controlling the potential supplied to wiring BGL, polarization Pr1 to Pr4 and the values ​​of currents Id1 to Id4 can be controlled.

[0134] According to one aspect of the present invention, a semiconductor device capable of storing multi-level data and a semiconductor device having a large storage capacity can be realized.

[0135] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0136] Embodiment 2 A configuration example of a memory device 300 including a semiconductor device 100 functioning as a memory cell will be described.

[0137] 11A shows a block diagram illustrating an example configuration of a memory device 300. The memory device 300 has a drive circuit 21 and a memory array 20. The memory array 20 has a plurality of semiconductor devices 100. FIG. 11A shows an example in which the memory array 20 has a plurality of semiconductor devices 100 arranged in a matrix of m rows and n columns (m is an integer of 2 or more, and n is an integer of 2 or more).

[0138] The rows and columns extend in directions perpendicular to each other. In this embodiment, the X direction is referred to as the "rows" and the Y direction is referred to as the "columns," but the X direction may also be referred to as the "columns" and the Y direction may also be referred to as the "rows."

[0139] 11A, the semiconductor device 100 in the first row and first column is indicated as semiconductor device 100[1,1], the semiconductor device 100 in the first row and nth column is indicated as semiconductor device 100[1,n], the semiconductor device 100 in the mth row and first column is indicated as semiconductor device 100[m,1], the semiconductor device 100 in the mth row and nth column is indicated as semiconductor device 100[m,n], and the semiconductor device 100 in the ith row and jth column (i is an integer of 1 to m, and j is an integer of 1 to n) is indicated as semiconductor device 100[i,j].

[0140] The memory array 20 also includes m wirings GL and m wirings BGL extending in the row direction, and n wirings SL and n wirings BL extending in the column direction (not shown). In this embodiment and the like, the wiring GL provided in the i-th line (i-th row) may be referred to as wiring GL[i]. The wiring BGL provided in the i-th line (i-th row) may be referred to as wiring BGL[i]. The wiring SL provided in the j-th line (j-th column) may be referred to as wiring SL[j]. The wiring BL provided in the j-th line (j-th row) may be referred to as wiring BL[j].

[0141] The semiconductor devices 100 provided in the j-th column are electrically connected to the wirings BL[j] and SL[j] (not shown), and the semiconductor devices 100 provided in the i-th row are electrically connected to the wirings GL[i] and BGL[i] (not shown).

[0142] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0143] In the storage device 300, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0144] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 32.

[0145] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0146] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0147] The peripheral circuit 41 is a circuit for writing and reading data to and from the semiconductor device 100. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0148] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring GL specified by the row decoder 42. The column driver 45 has the function of writing data to the semiconductor device 100, the function of reading data from the semiconductor device 100, the function of holding the read data, etc.

[0149] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the semiconductor device 100. The data (Dout) read from the semiconductor device 100 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is a signal RDA.

[0150] The PSW 22 is a V ＤＤ The PSW 23 has a function of controlling the supply of V to the row driver 43. ＨＭ Here, the high power supply potential of the memory device 300 is V ＤＤ and the low power supply voltage is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ 11A, in the peripheral circuit 31, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0151] The drive circuit 21 and the memory array 20 may be provided on the same plane. Alternatively, as shown in FIG. 11B, the drive circuit 21 and the memory array 20 may be provided overlapping each other. By providing the drive circuit 21 and the memory array 20 overlapping each other, the signal propagation distance can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20 are reduced, thereby reducing power consumption and signal delay. Furthermore, the memory device 300 can be made smaller.

[0152] As described above, the semiconductor device 100 according to one embodiment of the present invention functions as a memory cell capable of holding multilevel data. By using the semiconductor device 100 as a memory cell of the memory device 300, a memory device with a large storage capacity can be realized.

[0153] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0154] Embodiment 3 In this embodiment, a structural example of a transistor applicable to the transistor 200 included in the semiconductor device 100 will be described.

[0155] Transistors with various structures can be used as the transistor 200 according to one embodiment of the present invention. For example, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination as the semiconductor layer 203 (see FIG. 1B ) in which a channel of the transistor 200 is formed. Examples of the semiconductor material include silicon and germanium. Alternatively, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor can be used.

[0156] In particular, it is preferable to use a transistor (also referred to as an "OS transistor") that uses an oxide semiconductor, which is a type of metal oxide, for a semiconductor layer in which a channel is formed, as the transistor 200. Since an oxide semiconductor has a band gap of 2 eV or more, the off-state current is significantly small. Therefore, the power consumption of the semiconductor device 100 can be reduced. Therefore, the power consumption of semiconductor devices including the semiconductor device 100 can be reduced.

[0157] Furthermore, for example, a transistor using polycrystalline silicon exhibits variations in threshold voltage due to grain boundaries, whereas an OS transistor is less affected by grain boundaries and exhibits small variations in threshold voltage. Therefore, by using an OS transistor as the transistor 200, malfunction of a memory cell due to variations in threshold voltage can be suppressed.

[0158] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit little fluctuation in their characteristics. For example, the off-state current hardly increases even in high-temperature environments. Specifically, the off-state current hardly increases even in ambient temperatures above room temperature and below 200° C. Furthermore, the on-state current is unlikely to decrease even in high-temperature environments. Therefore, the semiconductor device 100 including an OS transistor operates stably and has high reliability even in high-temperature environments. Furthermore, OS transistors have a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a memory cell, a memory cell that operates stably and has high reliability even in high-temperature environments can be realized. By using an OS transistor as the transistor 200, the reliability of a memory device including the semiconductor device 100 can be improved.

[0159] Furthermore, since silicon is easily oxidized, if silicon is used for the semiconductor layer 203, oxygen contained in the dielectric layer 202, which may have ferroelectricity, reacts with the silicon of the semiconductor layer 203, and defects are likely to occur at or near the interface between the two, which can easily degrade the electrical characteristics and reliability of the transistor 400 used as an FeFET.

[0160] Since an oxide semiconductor is an oxide, by using an oxide semiconductor for the semiconductor layer 203, defects are less likely to occur at or near the interface between the semiconductor layer 203 and the dielectric layer 202. Therefore, the electrical characteristics of the transistor 200 used as an FeFET can be stabilized, and reliability can be improved.

[0161] Note that a memory cell including an OS transistor may be referred to as an "OS memory." A storage device including such a memory cell may also be referred to as an "OS memory."

[0162] <Structure Example of OS Transistor> A structure example of a transistor 400 will be described as an example of an OS transistor that can be used for the transistor 200. FIGS. 12A, 12B, and 12C are top views and cross-sectional views of the transistor 400 and the periphery of the transistor 400. Note that the structure of a transistor that can be used for the transistor 200 is not limited to the structure example of the transistor described in this embodiment.

[0163] FIG. 12A is a top view of the transistor 400. FIGS. 12B and 12C are cross-sectional views of the transistor 400. FIG. 12B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 12A and is also a cross-sectional view of the transistor 400 in the channel length direction. FIG. 12C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 12A and is also a cross-sectional view of the transistor 400 in the channel width direction. Note that some components are omitted from the top view in FIG. 12A for clarity.

[0164] 12 , the transistor 400 includes a metal oxide layer 220a, a metal oxide layer 220b disposed on the metal oxide layer 220a, conductive layers 242a and 242b disposed spaced apart from each other on the metal oxide layer 220b, an insulating layer 254 disposed on the conductive layers 242a and 242b, and an insulating layer 280 disposed on the insulating layer 254. The insulating layer 280 and the insulating layer 254 have openings that overlap the region between the conductive layers 242a and 242b.

[0165] The transistor 400 also has a dielectric layer 250 disposed in the opening. The dielectric layer 250 has regions in contact with parts of the insulating layer 280, the insulating layer 254, the conductive layer 242a, the conductive layer 242b, and the metal oxide layer 220b. The transistor 400 also has a conductive layer 260 disposed in the opening. The conductive layer 260 has a region that overlaps with the metal oxide layer 220b with the dielectric layer 250 interposed therebetween.

[0166] 12B and 12C , it is preferable that the upper surface of conductive layer 260 is substantially flush with the upper surfaces of dielectric layer 250 and insulating layer 280. In this specification and the like, metal oxide layer 220a and metal oxide layer 220b may be collectively referred to as metal oxide layer 220. In this specification and the like, conductive layer 242a and conductive layer 242b may be collectively referred to as conductive layer 242.

[0167] Note that the conductive layer 260 corresponds to the conductive layer 201 of the transistor 200 described in the above embodiment, and the metal oxide layer 220 corresponds to the semiconductor layer 203. The conductive layer 242a corresponds to the conductive layer 206a, and the conductive layer 242b corresponds to the conductive layer 206b.

[0168] 12, the side surfaces of the conductive layers 242a and 242b on the conductive layer 260 side have a substantially vertical shape. Note that the transistor 400 shown in FIG. 12 is not limited thereto, and the angle formed between the side surface and the bottom surface of the conductive layers 242a and 242b may be 10° to 80°, preferably 30° to 60°. The side surfaces of the conductive layers 242a and 242b may have multiple surfaces.

[0169] 12 , it is preferable that an insulating layer 254 be disposed between the insulating layer 224, the metal oxide layer 220a, the metal oxide layer 220b, the conductive layer 242a, and the conductive layer 242b and the insulating layer 280. Furthermore, it is preferable that the insulating layer 254 be in contact with the upper surface and side surfaces of the conductive layer 242a, the upper surface and side surfaces of the conductive layer 242b, the side surfaces of the metal oxide layer 220a, the side surfaces of the metal oxide layer 220b, the side surfaces of the insulating layer 224, and the insulating layer 222, as shown in FIG.

[0170] Note that the transistor 400 has a two-layer structure of the metal oxide layer 220a and the metal oxide layer 220b stacked in the region where a channel is formed (hereinafter also referred to as the channel formation region) and in the vicinity thereof; however, the present invention is not limited to this structure. For example, the metal oxide layer 220b may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the metal oxide layer 220a and the metal oxide layer 220b may have a stacked structure of two or more layers.

[0171] The conductive layer 260 functions as the gate electrode of the transistor 400, and the conductive layers 242a and 242b function as a source electrode and a drain electrode, respectively. The conductive layer 260 is formed so as to be embedded in the opening of the insulating layer 280 and in the region sandwiched between the conductive layers 242a and 242b. The conductive layers 260, 242a, and 242b are arranged in a self-aligned manner with respect to the opening of the insulating layer 280. That is, in the transistor 400, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductive layer 260 can be formed without providing a margin for alignment, which reduces the area occupied by the transistor 400. This allows for an increased integration density of the semiconductor device.

[0172] 12, the conductive layer 260 preferably includes a conductive layer 260a provided inside the dielectric layer 250 and a conductive layer 260b provided so as to be embedded inside the conductive layer 260a. Although the conductive layer 260 has a two-layer stacked structure in this embodiment, the present invention is not limited to this. For example, the conductive layer 260 may have a single-layer structure or a stacked structure of three or more layers.

[0173] The transistor 400 preferably includes an insulating layer 214, an insulating layer 216 disposed over the insulating layer 214, a conductive layer 215 disposed so as to be embedded in the insulating layer 216, an insulating layer 222 disposed over the insulating layer 216 and the conductive layer 215, and an insulating layer 224 disposed over the insulating layer 222. A metal oxide layer 220a is preferably disposed over the insulating layer 224.

[0174] The conductive layer 215 functions as a back gate electrode. The conductive layer 215 corresponds to the conductive layer 205 of the transistor 400 described in the above embodiment. The insulating layer 222 and the insulating layer 224 correspond to the dielectric layer 204. The insulating layer 222 and the insulating layer 224 function as gate insulating films on the back gate electrode side.

[0175] In addition, an insulating layer 274 and an insulating layer 281, which function as interlayer films, are preferably disposed on the transistor 400. Here, the insulating layer 274 is preferably disposed in contact with the upper surfaces of the conductive layer 260, the dielectric layer 250, and the insulating layer 280.

[0176] The insulating layers 214, 222, 254, and 274 preferably have a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). They also preferably have a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulating layers 214, 222, 254, and 274 preferably have lower hydrogen permeability than the insulating layer 224, the dielectric layer 250, and the insulating layer 280. For example, the insulating layers 214 and 274 preferably have lower oxygen permeability than the insulating layer 216, the insulating layer 224, the dielectric layer 250, and the insulating layer 280. In particular, the insulating layers 222 and 254 preferably have a function of suppressing the diffusion of hydrogen and oxygen.

[0177] Here, insulating layer 216, insulating layer 224, metal oxide layer 220, dielectric layer 250, insulating layer 280, etc. are isolated from the outside by insulating layer 214 and insulating layer 274. This prevents impurities such as hydrogen and oxygen from entering insulating layer 216, insulating layer 224, metal oxide layer 220, dielectric layer 250, insulating layer 280, etc. from the outside. This also prevents impurities such as hydrogen contained in insulating layer 216, insulating layer 224, metal oxide layer 220, dielectric layer 250, insulating layer 280, etc. from diffusing to the outside. This prevents fluctuations in the impurity and oxygen concentrations in the layers sandwiched between insulating layer 214 and insulating layer 274.

[0178] A conductive layer 245 (conductive layer 245a and conductive layer 245b) electrically connected to the transistor 400 and functioning as a contact plug is preferably provided. Note that the insulating layer 241 (insulating layer 241a and insulating layer 241b) is provided in contact with the side surface of the conductive layer 245 functioning as a contact plug. That is, the insulating layer 241 is provided in contact with the inner walls of the openings of the insulating layer 254, the insulating layer 280, the insulating layer 274, and the insulating layer 281. Alternatively, a first conductive layer of the conductive layer 245 may be provided in contact with the side surface of the insulating layer 241, and a second conductive layer of the conductive layer 245 may be provided further inside. Here, the height of the top surface of the conductive layer 245 and the height of the top surface of the insulating layer 281 can be made approximately the same. Note that, although the transistor 400 illustrates a structure in which the first conductive layer of the conductive layer 245 and the second conductive layer of the conductive layer 245 are stacked, the present invention is not limited to this. For example, the conductive layer 245 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the layers may be distinguished by adding an ordinal number to the order of formation.

[0179] In the transistor 400, an oxide semiconductor, which is a type of metal oxide, is preferably used for the metal oxide layer 220 (the metal oxide layer 220a and the metal oxide layer 220b) including the channel formation region. For example, the metal oxide layer 220 is preferably made of a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more.

[0180] The metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains indium (In) and zinc (Zn). Furthermore, it is preferable that it contains an element M in addition to these. The element M can be one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), or cobalt (Co). In particular, it is preferable that the element M is one or more of aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Furthermore, it is more preferable that the element M contains either or both of Ga and Sn.

[0181] Furthermore, at least one of hydrogen (H), nitrogen (N), phosphorus (P), fluorine (F), chlorine (Cl), and noble gases may be added to the metal oxide layer 220. This facilitates generation of carriers in the metal oxide layer 220, making it easier to realize a normally-on transistor.

[0182] Furthermore, the thickness of the metal oxide layer 220b in a region that does not overlap with the conductive layer 242 may be thinner than the thickness of the region that overlaps with the conductive layer 242. This occurs because part of the upper surface of the metal oxide layer 220b is removed when the conductive layers 242a and 242b are formed. When a conductive film that will become the conductive layer 242 is formed on the upper surface of the metal oxide layer 220b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region located between the conductive layers 242a and 242b on the upper surface of the metal oxide layer 220b, it is possible to prevent an unintended channel from being formed in that region.

[0183] Next, the configuration of the transistor 400 will be described in more detail.

[0184] The conductive layer 215 is disposed to have a region overlapping with the metal oxide layer 220 and the conductive layer 260. The conductive layer 215 is preferably embedded in the insulating layer 216.

[0185] The conductive layer 215 includes a conductive layer 215a, a conductive layer 215b, and a conductive layer 215c. The conductive layer 215a is provided in contact with the bottom surface and sidewall of an opening provided in the insulating layer 216. The conductive layer 215b is provided so as to be embedded in a recess formed in the conductive layer 215a. Here, the top surface of the conductive layer 215b is lower than the top surface of the conductive layer 215a and the top surface of the insulating layer 216. The conductive layer 215c is provided in contact with the top surface of the conductive layer 215b and the side surface of the conductive layer 215a. Here, the height of the top surface of the conductive layer 215c is approximately the same as the height of the top surface of the conductive layer 215a and the height of the top surface of the insulating layer 216. In other words, the conductive layer 215b is configured to be enclosed by the conductive layer 215a and the conductive layer 215c.

[0186] In this specification, "substantially the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a semiconductor device manufacturing process, a planarization process (typically a CMP process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces treated by the CMP process are configured to be equal in height from the reference surface. Furthermore, "substantially the same height" also includes cases where the heights are equal. However, when there are multiple layers whose surfaces are exposed, the heights of the respective layers may differ depending on the processing equipment, processing method, or material of the treated surfaces during the CMP process. In this specification, this case is also treated as "substantially the same height." For example, when there are two layers (here, a first layer and a second layer) with different heights relative to the reference surface, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "substantially the same height."

[0187] The conductive layer 215a and the conductive layer 215c are formed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0188] By using a conductive material having a function of reducing hydrogen diffusion for the conductive layer 215a and the conductive layer 215c, it is possible to suppress the diffusion of impurities such as hydrogen contained in the conductive layer 215b into the metal oxide layer 220. That is, it is possible to prevent excessive supply of impurities to the metal oxide layer 220. It is also possible to suppress the diffusion of impurities such as hydrogen contained in the metal oxide layer 220 and the insulating layer 224 to the outside via the conductive layer 215. Therefore, it is possible to suppress fluctuations in the concentration of impurities in the metal oxide layer 220.

[0189] Furthermore, by using a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 215a and the conductive layer 215c, it is possible to suppress the phenomenon in which the conductive layer 215b is oxidized and its conductivity is reduced. Examples of conductive materials that have a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductive layer 215a may be formed as a single layer or a stack of the above conductive materials. For example, the conductive layer 215a may be formed as titanium nitride.

[0190] The conductive layer 215b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0191] Note that if the insulating layer 222 has a function of suppressing oxygen diffusion, the phenomenon in which the conductive layer 215b is oxidized and its conductivity is reduced may be suppressed even without providing the conductive layer 215c. Therefore, the conductive layer 215 may have a stacked structure of the conductive layer 215a and the conductive layer 215b. In this case, the height of the upper surface of the conductive layer 215b is approximately the same as the height of the upper surface of the conductive layer 215a and the height of the upper surface of the insulating layer 216.

[0192] Here, the conductive layer 260 may function as a first gate (also referred to as a top gate) electrode, and the conductive layer 215 may function as a second gate (also referred to as a bottom gate) electrode.

[0193] The conductive layer 215 is preferably provided to be larger than the channel formation region in the metal oxide layer 220. In particular, as shown in Fig. 12C, the conductive layer 215 preferably extends also in a region outside the end portion intersecting with the channel width direction of the metal oxide layer 220. In other words, outside the side surface of the metal oxide layer 220 in the channel width direction, the conductive layer 215 and the conductive layer 260 preferably overlap with each other via an insulating layer.

[0194] With the above structure, the channel formation region of the metal oxide layer 220 can be electrically surrounded by the electric field of the conductive layer 260 functioning as a first gate electrode and the electric field of the conductive layer 215 functioning as a second gate electrode.

[0195] 12C, the conductive layer 215 can also function as a wiring. Note that a structure may be adopted in which a conductive layer functioning as a wiring is separately provided and electrically connected to the conductive layer 215.

[0196] The insulating layer 214 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 400 from the substrate side. The insulating layer 214 also preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from diffusing from the transistor 400 side to the outside.

[0197] Therefore, the insulating layer 214 contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (i.e., copper atoms are less likely to penetrate the impurities), or that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., oxygen is less likely to penetrate the insulating material).

[0198] For example, aluminum oxide, silicon nitride, or the like is preferably used for the insulating layer 214. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 214 to the transistor 400 side. Alternatively, it can prevent impurities such as water or hydrogen contained in the transistor 400 side from diffusing beyond the insulating layer 214 to the outside.

[0199] The insulating layer 216, the insulating layer 280, and the insulating layer 281, which function as interlayer films, preferably have a lower dielectric constant than the insulating layer 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the insulating layer 216, the insulating layer 280, and the insulating layer 281 may be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0200] The insulating layer 224 in contact with the metal oxide layer 220 preferably has a property that oxygen is not easily released by heating. In this specification, oxygen released by heating is sometimes referred to as excess oxygen. For example, the insulating layer 224 may be formed using silicon oxide, silicon nitride, or the like as appropriate. When oxygen is supplied to the metal oxide layer 220, oxygen vacancies in the metal oxide layer 220 are reduced, and the transistor 400 is likely to become a normally-off transistor. By providing an insulating layer with little excess oxygen in contact with the metal oxide layer 220, the reduction of oxygen vacancies in the metal oxide layer 220 is suppressed.

[0201] The insulating layer 224 preferably contains an impurity such as hydrogen. For example, when oxygen vacancies in the metal oxide layer 220 are bonded to hydrogen, carriers are easily generated in the metal oxide layer 220, which makes it easier to realize a normally-on transistor.

[0202] On the other hand, when an oxide from which oxygen is partly released by heating is used for the insulating layer 224, the transistor tends to become a normally-off type. The oxide from which oxygen is partly released by heating is an oxide whose amount of released oxygen, converted into oxygen atoms, is 1.0×10 in thermal desorption spectroscopy (TDS) analysis.１８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0203] To make it difficult for the transistor 400 to become normally off, the amount of oxygen released from the insulating layer 224 is set to 1.0×10 １９ atoms / cm ３ Preferably, less than 1.0 x 10 １８ atoms / cm ３ Less than is more preferred.

[0204] Similar to the insulating layer 214 and the like, the insulating layer 222 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 400 from the substrate side. For example, the insulating layer 222 preferably has lower hydrogen permeability than the insulating layer 224. By surrounding the insulating layer 224, the metal oxide layer 220, the dielectric layer 250, and the like with the insulating layer 222, the insulating layer 254, and the insulating layer 274, impurities such as water or hydrogen can be suppressed from entering the transistor 400 from the outside. Furthermore, impurities such as water or hydrogen contained in the insulating layer 224 and the like on the transistor 400 side can be suppressed from diffusing to the outside.

[0205] Furthermore, the insulating layer 222 preferably has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like). When the insulating layer 222 has a function of suppressing diffusion of oxygen and impurities, oxygen diffusion from the outside to the transistor 400 can be reduced, which is preferable.

[0206] The insulating layer 222 may be an insulating layer containing an oxide of one or both of insulating materials, such as aluminum and hafnium. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulating layer containing an oxide of one or both of aluminum and hafnium. When the insulating layer 222 is formed using such a material, the insulating layer 222 functions as a layer that suppresses the release of impurities such as hydrogen from the metal oxide layer 220 and the intrusion of oxygen from the periphery of the transistor 400 into the metal oxide layer 220.

[0207] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulating layers. Alternatively, these insulating layers may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulating layers. For example, the insulating layer 222 may have a three-layer structure in which silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.

[0208] The insulating layer 222 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ An insulating layer containing a so-called high-k material such as BST may be used as a single layer or a laminate. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulating films. By using a high-k material for the insulating layer that functions as a gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0209] The insulating layer 222 and the insulating layer 224 may have a stacked structure of two or more layers. In this case, the insulating layer 222 and the insulating layer 224 are not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials. For example, an insulating layer similar to the insulating layer 224 may be provided below the insulating layer 222.

[0210] The metal oxide layer 220 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. For example, when the metal oxide layer 220 contains at least indium (In) and the element M, it is preferable that the ratio of the number of atoms of the element M contained in the metal oxide layer 220a to the number of atoms of all elements constituting the metal oxide layer 220a is higher than the ratio of the number of atoms of the element M contained in the metal oxide layer 220b to the number of atoms of all elements constituting the metal oxide layer 220b. It is also preferable that the atomic ratio of the element M contained in the metal oxide layer 220a to In is higher than the atomic ratio of the element M contained in the metal oxide layer 220b to In.

[0211] The energy of the conduction band minimum of the metal oxide layer 220a is preferably higher than the energy of the conduction band minimum of the metal oxide layer 220b. In other words, the electron affinity of the metal oxide layer 220a is preferably smaller than the electron affinity of the metal oxide layer 220b.

[0212] Here, the energy level of the conduction band minimum changes gradually at the junction between the metal oxide layer 220 a and the metal oxide layer 220 b. In other words, the energy level of the conduction band minimum at the junction between the metal oxide layer 220 a and the metal oxide layer 220 b changes continuously or can be said to be a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the metal oxide layer 220 a and the metal oxide layer 220 b.

[0213] Specifically, when the metal oxide layer 220a and the metal oxide layer 220b have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the metal oxide layer 220b is an In—Ga—Zn oxide, the metal oxide layer 220a may be made of an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like.

[0214] Specifically, the metal oxide layer 220a may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of 1:1:0.5 or thereabouts, while the metal oxide layer 220b may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or thereabouts, an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of 3:1:2 or thereabouts.

[0215] In this case, the main carrier path is the metal oxide layer 220b. By configuring the metal oxide layer 220a as described above, the defect state density at the interface between the metal oxide layer 220a and the metal oxide layer 220b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 400 can achieve high on-state current and high frequency characteristics.

[0216] Conductive layers 242 (conductive layers 242a and 242b) functioning as a source electrode and a drain electrode are provided over the metal oxide layer 220b. The conductive layer 242 is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain their conductivity even when they absorb oxygen.

[0217] By providing the conductive layer 242 so as to be in contact with the metal oxide layer 220, the oxygen concentration may be reduced in the vicinity of the conductive layer 242 of the metal oxide layer 220. Furthermore, a metal compound layer containing the metal contained in the conductive layer 242 and components of the metal oxide layer 220 may be formed in the vicinity of the conductive layer 242 of the metal oxide layer 220. In such a case, the carrier concentration increases in the region of the metal oxide layer 220 in the vicinity of the conductive layer 242, and this region becomes a low-resistance region.

[0218] Here, the region between the conductive layer 242a and the conductive layer 242b is formed to overlap the opening of the insulating layer 280. This allows the conductive layer 260 to be disposed in a self-aligned manner between the conductive layer 242a and the conductive layer 242b.

[0219] The dielectric layer 250 functions as a gate insulating film. The dielectric layer 250 is preferably disposed in contact with the upper surface of the metal oxide layer 220b. The dielectric layer 250 corresponds to the dielectric layer 202 of the transistor 200. Therefore, the dielectric layer 250 is made of a material capable of exhibiting ferroelectricity as described in the above embodiment. In particular, a material capable of exhibiting antiferroelectricity is used.

[0220] Although the conductive layer 260 is shown as having a two-layer structure in FIG. 12, it may have a single-layer structure or a stacked structure of three or more layers.

[0221] The conductive layer 260a is made of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive layer having a function of suppressing the diffusion of impurities such as copper atoms and the like, or a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0222] The conductive layer 260a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 260b caused by oxygen contained in the dielectric layer 250. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0223] The conductive layer 260b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductive layer 260 also functions as wiring, it is preferable to use a conductive layer with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductive layer 260b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0224] 12A and 12C , in a region of the metal oxide layer 220b that does not overlap with the conductive layer 242, in other words, in the channel formation region of the metal oxide layer 220, the conductive layer 260 is arranged to cover the side surface of the metal oxide layer 220. This makes it easier for the electric field of the conductive layer 260, which functions as the first gate electrode, to act on the side surface of the metal oxide layer 220. This increases the on-state current of the transistor 400 and improves its frequency characteristics.

[0225] The insulating layer 254 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water or hydrogen from the metal oxide layer 220 side to the insulating layer 280 side. For example, the insulating layer 254 preferably has lower hydrogen permeability than the insulating layer 224. Furthermore, as shown in Figures 12B and 12C, the insulating layer 254 preferably contacts the upper and side surfaces of the conductive layer 242a, the upper and side surfaces of the conductive layer 242b, the side surfaces of the metal oxide layer 220a and the metal oxide layer 220b, and the insulating layer 224. With this configuration, it is possible to suppress the diffusion of impurities such as hydrogen contained in the metal oxide layer 220 to the outside.

[0226] Furthermore, the insulating layer 254 preferably has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like). For example, the insulating layer 254 preferably has lower oxygen permeability than the insulating layer 280 or the insulating layer 224.

[0227] For example, an insulating layer containing an oxide of one or both of aluminum and hafnium may be formed as the insulating layer 254. Note that aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like may be used as the insulating layer containing an oxide of one or both of aluminum and hafnium.

[0228] The insulating layer 280 is separated from the insulating layer 224 and the metal oxide layer 220 by the insulating layer 254, which has a barrier property against impurities such as hydrogen and oxygen. This can prevent impurities such as hydrogen and oxygen from penetrating into the metal oxide layer 220 from the insulating layer 280 side. This can prevent excessive supply of impurities such as hydrogen and oxygen to the metal oxide layer 220. Furthermore, the diffusion of impurities such as hydrogen contained in the metal oxide layer 220 to the outside can also be prevented, making it easier to maintain the normally-on characteristics of the transistor 400. This can provide the transistor 400 with good electrical characteristics and reliability.

[0229] The insulating layer 280 is provided over the insulating layer 224, the metal oxide layer 220, and the conductive layer 242 with the insulating layer 254 interposed therebetween. For example, the insulating layer 280 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is released by heating.

[0230] It is preferable that excess oxygen be reduced in the insulating layer 280. The top surface of the insulating layer 280 may be planarized.

[0231] Similar to the insulating layer 214, the insulating layer 274 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the insulating layer 280 from above. As the insulating layer 274, for example, an insulating layer that can be used for the insulating layer 214, the insulating layer 254, or the like may be used.

[0232] An insulating layer 281 functioning as an interlayer film may be provided over the insulating layer 274. Furthermore, conductive layers 245a and 245b are disposed in openings formed in the insulating layer 281, the insulating layer 274, the insulating layer 280, and the insulating layer 254. The conductive layers 245a and 245b are provided opposite each other with the conductive layer 260 interposed therebetween. Note that the height of the top surfaces of the conductive layers 245a and 245b may be flush with the top surface of the insulating layer 281.

[0233] Note that insulating layer 241a is provided in contact with the inner walls of openings provided in parts of insulating layer 281, insulating layer 274, insulating layer 280, and insulating layer 254, and a first conductive layer of conductive layer 245a is formed in contact with the side surfaces of insulating layer 241a. Conductive layer 242a is located in at least a part of the bottom of the openings, and conductive layer 245a is in contact with conductive layer 242a. Similarly, insulating layer 241b is provided in contact with the inner walls of the openings of insulating layer 281, insulating layer 274, insulating layer 280, and insulating layer 254, and a first conductive layer of conductive layer 245b is formed in contact with the side surfaces of insulating layer 241b. Conductive layer 242b is located in at least a part of the bottom of the openings, and conductive layer 245b is in contact with conductive layer 242b.

[0234] The conductive layers 245a and 245b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layers 245a and 245b may have a stacked structure.

[0235] When the conductive layer 245 has a stacked structure, the conductive layers in contact with the conductive layer 242, the insulating layer 254, the insulating layer 280, the insulating layer 274, and the insulating layer 281 preferably use the above-mentioned conductive layers having the function of suppressing the diffusion of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. Furthermore, the conductive material having the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a stacked layer. The use of such a conductive material can suppress impurities such as water or hydrogen from layers above the insulating layer 281 from entering the metal oxide layer 220 through the conductive layer 245a and the conductive layer 245b. Furthermore, the diffusion of impurities such as hydrogen contained in the metal oxide layer 220 to the outside can be suppressed.

[0236] As the insulating layer 241a and the insulating layer 241b, for example, an insulating layer that can be used for the insulating layer 254 or the like may be used. The insulating layer 241a and the insulating layer 241b are provided in contact with the insulating layer 254, and therefore can prevent impurities such as water or hydrogen from the insulating layer 280 or the like from being mixed into the metal oxide layer 220 through the conductive layer 245a and the conductive layer 245b. Furthermore, the impurities such as hydrogen contained in the metal oxide layer 220 can be prevented from diffusing to the outside through the conductive layer 245a and the conductive layer 245b.

[0237] Although not shown, a conductive layer functioning as a wiring may be disposed in contact with the top surface of the conductive layer 245a and the top surface of the conductive layer 245b. The conductive layer functioning as a wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer may have a stacked structure, for example, a stack of titanium or titanium nitride and the above-mentioned conductive material. The conductive layer may be formed so as to be embedded in an opening provided in the insulating layer.

[0238] <Constituent Materials of Transistor> Constituent materials that can be used for the transistor will be described.

[0239] [Substrate] The substrate on which a transistor is formed may be, for example, an insulating layer substrate, a semiconductor substrate, or a conductive layer substrate. Examples of insulating layer substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating layer region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive layer substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include a substrate having a conductive layer or a semiconductor provided on an insulating layer substrate, a substrate having a conductive layer or an insulating layer provided on a semiconductor substrate, and a substrate having a semiconductor or insulating layer provided on a conductive layer substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0240] [Insulating Layer] Examples of insulating layers include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0241] For example, as transistors become more miniaturized and highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulating layer that functions as the gate insulating film makes it possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the function of the insulating layer.

[0242] Examples of insulating layers with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0243] Examples of insulating layers with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0244] The electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding it with an insulating layer (such as the insulating layer 214, the insulating layer 222, the insulating layer 254, and the insulating layer 274) that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulating layer that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, a single insulating layer or a stacked insulating layer containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used. Specifically, as the insulating layer that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride may be used.

[0245] [Conductive Layer] For the conductive layer, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0246] A plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0247] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0248] Embodiment 4 In this embodiment, an oxide semiconductor that can be used for the OS transistor described in the above embodiment will be described.

[0249] The metal oxide used in the OS transistor preferably contains at least indium or zinc, and more preferably contains indium and zinc. For example, the metal oxide preferably contains indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium, and tin, and more preferably gallium.

[0250] The metal oxide can be formed by a sputtering method, a chemical vapor deposition (CVD) method such as a metal organic chemical vapor deposition (MOCVD) method, or an ALD method.

[0251] Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) will be described as an example of a metal oxide. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In—Ga—Zn oxide.

[0252] <Classification of Crystal Structure> Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0253] The crystalline structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incident XRD) measurement. The GIXD method is also called the thin film method or the Seemann-Bohlin method. In the following, the XRD spectrum obtained by GIXD measurement may be simply referred to as the XRD spectrum.

[0254] For example, in the case of a quartz glass substrate, the peak shape of the XRD spectrum is almost symmetrical. On the other hand, in the case of an In-Ga-Zn oxide film having a crystalline structure, the peak shape of the XRD spectrum is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0255] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, confirming that the quartz glass is in an amorphous state. Furthermore, a spot-like pattern is observed in the diffraction pattern of an In—Ga—Zn oxide film formed at room temperature, rather than a halo. For this reason, it is estimated that the In—Ga—Zn oxide formed at room temperature is neither single crystal nor polycrystalline, nor in an amorphous state, but is in an intermediate state, and it cannot be concluded that it is in an amorphous state.

[0256] [Structure of Oxide Semiconductor] Note that oxide semiconductors may be classified differently from the above when focusing on their structure. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0257] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0258] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0259] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of the crystalline region may be several tens of nanometers.

[0260] In an In—Ga—Zn oxide, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as a (Ga, Zn) layer) are stacked. Note that indium and gallium are mutually substituted. Therefore, the (Ga, Zn) layer may contain indium. The In layer may contain gallium. The In layer may contain zinc. The layered structure is observed as a lattice image in a high-resolution transmission electron microscope (TEM) image, for example.

[0261] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type, composition, and the like of the metal elements constituting the CAAC-OS.

[0262] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the observed spots are at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0263] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundary can be identified even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the a-b plane and the change in interatomic bond distance caused by metal atom substitution.

[0264] Note that a crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and are likely to trap carriers, resulting in a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming a CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0265] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities and / or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (oxygen vacancies, etc.). Therefore, an oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0266] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS and an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0267] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0268] [Structure of Oxide Semiconductor] Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0269] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0270] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0271] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In—Ga—Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In—Ga—Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0272] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0273] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0274] Furthermore, CAC-OS in In—Ga—Zn oxide refers to a structure in which a mosaic of regions containing Ga as the main component and regions containing In as the main component are randomly arranged in a material composition containing In, Ga, Zn, and O. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0275] The CAC-OS can be formed by sputtering, for example, without intentionally heating the substrate. When forming the CAC-OS by sputtering, any one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0276] Furthermore, for example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region containing In as a main component (first region) and a region containing Ga as a main component (second region) are unevenly distributed and mixed.

[0277] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving a high field-effect mobility (μ).

[0278] On the other hand, the second region has higher insulating properties than the first region. That is, the second region is distributed in the metal oxide, thereby suppressing leakage current.

[0279] Therefore, when a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (a function of turning on / off). That is, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0280] Furthermore, a transistor using the CAC-OS has high reliability, and therefore, the CAC-OS is ideal for various semiconductor devices such as display devices.

[0281] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0282] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0283] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, when an oxide semiconductor is used for a semiconductor layer of a normally-off transistor, the concentration of silicon or carbon in the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) is set to 2×10 or less. １８ atoms / cm ３ Below 2 × 10, preferably １７ atoms / cm ３ The following would suffice.

[0284] When an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, by using an oxide semiconductor containing an alkali metal or an alkaline earth metal, a normally-on transistor can be easily realized. On the other hand, when an oxide semiconductor is used for a semiconductor layer of a normally-off transistor, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ You can do it as follows.

[0285] When an oxide semiconductor contains nitrogen, electrons serving as carriers are generated, the carrier concentration increases, and the oxide semiconductor is easily made n-type. As a result, by using an oxide semiconductor containing nitrogen as a semiconductor, a normally-on transistor can be easily realized. On the other hand, when an oxide semiconductor is used as a semiconductor layer of a normally-off transistor, the nitrogen concentration in the oxide semiconductor obtained by SIMS is 5×10 １９ atoms / cm ３ Less than 5×10 １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ You can do it as follows.

[0286] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, by using an oxide semiconductor containing hydrogen, a normally-on transistor can be easily realized. On the other hand, when an oxide semiconductor is used for a semiconductor layer of a normally-off transistor, it is preferable that the amount of hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ It should be less than that.

[0287] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0288] Embodiment Mode 5 In this embodiment mode, an example of an electronic component in which the semiconductor device or the like shown in the above embodiment modes is incorporated will be described.

[0289] <Electronic Component> Fig. 13A shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in Fig. 13A has a memory device 300, which is a type of semiconductor device, inside a mold 711. Fig. 13A omits some parts in order to show the interior of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the memory device 300 by wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0290] The storage device 300 includes a drive circuit 21 and a memory array 20. Alternatively, a plurality of memory arrays 20 may be used on the drive circuit 21.

[0291] 13B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 300 provided on the interposer 731.

[0292] The electronic component 730 shows an example in which the storage device 300 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0293] The package substrate 732 may be made of a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. The interposer 731 may be made of a silicon interposer, a resin interposer, etc.

[0294] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0295] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since wiring formation on a silicon interposer can be performed using a semiconductor process, it is easy to form fine wiring that is difficult to form on a resin interposer.

[0296] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0297] Furthermore, in SiP, MCM, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0298] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 300 and the height of the semiconductor device 735.

[0299] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 13B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0300] The electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0301] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0302] Embodiment 6 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0303] A storage device according to one embodiment of the present invention can be used as a storage device for various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, Internet of Things (IoT), healthcare-related devices, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0304] 14A to 14J and 15A to 15E illustrate examples of electronic devices including an electronic component 700 or an electronic component 730 including the memory device according to one embodiment of the present invention.

[0305] 14A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. The display unit 5511 is provided with a touch panel and the housing 5510 is provided with buttons as input interfaces.

[0306] By applying a storage device according to one embodiment of the present invention, the information terminal 5500 can store temporary files (for example, caches when using a web browser) generated when an application is executed.

[0307] 14B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0308] Like the information terminal 5500 described above, the wearable terminal can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0309] 14C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0310] Like the information terminal 5500 described above, the desktop information terminal 5300 can store temporary files generated when an application is executed by applying a storage device according to one embodiment of the present invention.

[0311] 14A to 14C are taken as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0312] 14D also illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, etc. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0313] A storage device according to one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to an information terminal or the like via the Internet. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the semiconductor device.

[0314] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0315] 14E illustrates a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0316] FIG. 14F further illustrates a stationary game console 7500, an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a wired connection. Although not shown in FIG. 14F , the controller 7522 can include a display unit for displaying game images and an input interface other than buttons, such as a touch panel, a stick, a rotary knob, or a sliding knob. The shape of the controller 7522 is not limited to the shape shown in FIG. 14F , and the shape of the controller 7522 may vary depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller with a trigger button and shaped like a gun can be used. For example, in a music game, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures or voice.

[0317] Furthermore, the images of the above-mentioned game machines can be output by display devices such as television devices, personal computer displays, game displays, and head-mounted displays.

[0318] A low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized by applying the storage device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0319] Furthermore, by applying the storage device described in the above embodiment to the portable game console 5200 or the stationary game console 7500, temporary files and the like necessary for calculations that occur during game execution can be stored.

[0320] 14E shows a portable game machine as an example of a game machine. Also, FIG. 14F shows a home-use stationary game machine. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include an arcade game machine installed in an amusement facility (such as an arcade game center or an amusement park) and a pitching machine for batting practice installed in a sports facility.

[0321] [Mobile Body] The storage device described in the above embodiment can be applied to a mobile body such as an automobile and the area around the driver's seat of the automobile.

[0322] FIG. 14G illustrates an automobile 5700 as an example of a moving object.

[0323] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A storage device that displays this information may also be provided around the driver's seat.

[0324] In particular, the display device can enhance safety by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby compensating for a field of view obstructed by a pillar or the like, a blind spot on the driver's seat, etc. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be enhanced.

[0325] The semiconductor device described in the above embodiment can temporarily store information, and therefore, for example, the storage device can be used to store temporary information required in a system that performs automatic driving, road guidance, hazard prediction, or the like of the automobile 5700. The display device may be configured to display temporary information such as road guidance and hazard prediction. Furthermore, the display device may be configured to store video images from a driving recorder installed in the automobile 5700.

[0326] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects may include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0327] [Camera] The storage device described in the above embodiment can be applied to a camera.

[0328] 14H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0329] A low-power digital camera 6240 can be realized by applying the storage device described in the above embodiment to the digital camera 6240. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat generation on the circuit itself, peripheral circuits, and modules.

[0330] [Video Camera] The storage device described in the above embodiment can be applied to a video camera.

[0331] 14I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0332] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the semiconductor device described above, the video camera 6300 can store temporary files generated during encoding.

[0333] [ICD] The storage device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0334] 14J is a cross-sectional schematic diagram showing an example of an ICD. An ICD main body 5400 has at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0335] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0336] The ICD main body 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is administered.

[0337] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 700 heart rate data acquired by the sensor, the number of pacing treatments performed, the duration of the treatment, and the like.

[0338] Furthermore, power can be received by the antenna 5404, and the power is charged in the battery 5401. Furthermore, the ICD main body 5400 has multiple batteries, thereby improving safety. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 also functions as an auxiliary power source.

[0339] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0340] [Expansion Device for PC] The semiconductor device described in the above embodiment can be applied to an expansion device for a computer such as a PC (Personal Computer) or an information terminal.

[0341] Fig. 15A shows an example of such an expansion device: a portable expansion device 6100 equipped with a chip capable of storing information and externally attached to a PC. The expansion device 6100 can store information using the chip by connecting to a PC via, for example, a USB (Universal Serial Bus). While Fig. 15A illustrates a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

[0342] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with a circuit for driving the semiconductor device described in the above embodiment. For example, an electronic component 700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0343] [SD Card] The storage device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0344] FIG. 15B is a schematic diagram of the external appearance of an SD card, and FIG. 15C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. The circuit board 5113 is provided with a memory device and a circuit for driving the memory device. For example, an electronic component 700 and a controller chip 5115 are attached to the circuit board 5113. Note that the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, etc. provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 700.

[0345] The capacity of the SD card 5110 can be increased by providing the electronic component 700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This enables wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 700.

[0346] [SSD] The storage device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.

[0347] FIG. 15D is a schematic diagram of the SSD's exterior, and FIG. 15E is a schematic diagram of the SSD's internal structure. The SSD 5150 includes a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a memory device and a circuit for driving the memory device. For example, the circuit board 5153 is equipped with an electronic component 700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 700 on the back side of the circuit board 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0348] 16A is an example of a large-scale computer. The computer 5600 includes a rack 5610 and a plurality of rack-mounted computers 5620 stored therein.

[0349] The computer 5620 can have the configuration shown in the perspective view of Fig. 16B, for example. In Fig. 16B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0350] A PC card 5621 shown in Figure 16C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 includes a board 5622. The board 5622 also includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 16C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

[0351] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0352] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0353] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0354] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0355] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0356] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for learning and inference in artificial intelligence, for example.

[0357] By using a storage device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller and consume less power. Furthermore, the storage device of one embodiment of the present invention consumes less power, which reduces heat generation from the circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using a storage device of one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

[0358] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0359] 100: semiconductor device, 200: transistor, 201: conductive layer, 202: dielectric layer, 203: semiconductor layer, 204: dielectric layer, 205: conductive layer, 213: channel formation region, 214: insulating layer, 215: conductive layer, 216: insulating layer, 220: metal oxide layer, 222: insulating layer, 224: insulating layer, 241: insulating layer, 242: conductive layer, 245: conductive layer, 250: dielectric layer, 254: insulating layer, 260: conductive layer, 274: insulating layer, 280: insulating layer, 281: insulating layer

Claims

1. a first conductive layer, a first insulating layer, a metal oxide layer, a second conductive layer, a third conductive layer, a second insulating layer, a ferroelectric layer, and a fourth conductive layer; the first conductive layer functions as a first gate electrode of a transistor; the first insulating layer has a region located above the first conductive layer and functions as a first gate insulating layer of the transistor; the metal oxide layer has a region located above the first insulating layer and has a channel formation region of the transistor; the second conductive layer has a region in contact with a top surface of the metal oxide layer and functions as one of a source electrode and a drain electrode of the transistor; the third conductive layer has a region in contact with an upper surface of the metal oxide layer and functions as the other of the source electrode and the drain electrode of the transistor; the second insulating layer has a region located above the second conductive layer, a region located above the second conductive layer, and an opening; the ferroelectric layer has a region located within the opening and serving as a second gate insulating layer of the transistor; the fourth conductive layer is embedded in the opening and functions as a second gate electrode of the transistor, The semiconductor device, wherein the ferroelectric layer comprises hafnium oxide containing zirconium and has an orthorhombic crystal structure.

2. a first conductive layer, a first insulating layer, a metal oxide layer, a second conductive layer, a third conductive layer, a second insulating layer, a ferroelectric layer, and a fourth conductive layer; the first conductive layer functions as a first gate electrode of a transistor; the first insulating layer has a region located above the first conductive layer and functions as a first gate insulating layer of the transistor; the metal oxide layer has a region located above the first insulating layer and has a channel formation region of the transistor; the second conductive layer has a region in contact with a top surface of the metal oxide layer and functions as one of a source electrode and a drain electrode of the transistor; the third conductive layer has a region in contact with an upper surface of the metal oxide layer and functions as the other of the source electrode and the drain electrode of the transistor; the second insulating layer has a region located above the second conductive layer, a region located above the second conductive layer, and an opening; the ferroelectric layer has a region located within the opening and serving as a second gate insulating layer of the transistor; a fourth conductive layer embedded in the opening and functioning as a second gate electrode of the transistor, The method for manufacturing a semiconductor device, wherein the ferroelectric layer contains hafnium oxide containing zirconium, has an orthorhombic crystal structure, and is formed by atomic layer deposition.

3. a first conductive layer, a first insulating layer, a metal oxide layer, a second conductive layer, a third conductive layer, a second insulating layer, an antiferroelectric layer, and a fourth conductive layer; the first conductive layer functions as a first gate electrode of a transistor; the first insulating layer has a region located above the first conductive layer and functions as a first gate insulating layer of the transistor; the metal oxide layer has a region located above the first insulating layer and has a channel formation region of the transistor; the second conductive layer has a region in contact with a top surface of the metal oxide layer and functions as one of a source electrode and a drain electrode of the transistor; the third conductive layer has a region in contact with an upper surface of the metal oxide layer and functions as the other of the source electrode and the drain electrode of the transistor; the second insulating layer has a region located above the second conductive layer, a region located above the second conductive layer, and an opening; the antiferroelectric layer has a region located within the opening and functions as a second gate insulating layer of the transistor; the fourth conductive layer is embedded in the opening and functions as a second gate electrode of the transistor, The antiferroelectric layer comprises hafnium oxide containing zirconium and has a tetragonal crystal structure.