Semiconductor device

Abstract

The present invention provides a semiconductor device which enables miniaturization or high integration. A semiconductor device according to the present invention comprises a first conductor, a second conductor, a first insulating body, a first transistor which is arranged on the first insulating body, and a second insulating body which is arranged on the first transistor. The first transistor comprises: a first metal oxide; a third conductor and a fourth conductor, which are electrically connected to the first metal oxide; a third insulating body which is arranged on the first metal oxide; and a fifth conductor which is arranged on the third insulating body. The upper surface of the fifth conductor has a region that is in contact with the second insulating body. The first conductor has: a portion which is positioned within an opening of the first insulating body; a region which is in contact with the lateral surface of the third conductor; and a portion which is positioned within an opening of the second insulating body. The second conductor has: a region which is in contact with the upper surface of the fourth conductor; and a portion which is positioned within the opening of the second insulating body. The height of the upper surface f the first conductor and the height of the upper surface of the second conductor are equal to or generally equal to each other.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic units, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] In recent years, development of semiconductor devices such as large-scale integration (LSI), central processing unit (CPU), and memory (storage device) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. Furthermore, memories of various storage methods have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage methods include dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory.

[0005] Furthermore, as the amount of data handled increases, semiconductor devices with larger storage capacities are required. Patent Document 1 and Non-Patent Document 1 disclose memory cells formed by stacking transistors.

[0006] International Publication No. 2021 / 053473

[0007] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDMTech. Dig. , 2019, pp. 50-53

[0008] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed.An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with large on-state current.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0009] An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with a small number of steps.

[0010] An object of one embodiment of the present invention is to provide a storage device with a large storage capacity.An object of one embodiment of the present invention is to provide a storage device with a small occupation area.An object of one embodiment of the present invention is to provide a storage device with high reliability.An object of one embodiment of the present invention is to provide a storage device with low power consumption.An object of one embodiment of the present invention is to provide a novel storage device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention is a semiconductor device including a first conductor, a second conductor, a first insulator, a first transistor on the first insulator, and a second insulator on the first transistor. The first transistor includes a first metal oxide, a third conductor and a fourth conductor electrically connected to the first metal oxide, the third insulator on the first metal oxide, and a fifth conductor on the third insulator. An upper surface of the fifth conductor has a region in contact with the second insulator. The first conductor has a portion located inside an opening of the first insulator, a region in contact with a side surface of the third conductor, and a portion located inside the opening of the second insulator. The second conductor has a region located inside the opening of the second insulator, and the height of an upper surface of the first conductor and the height of an upper surface of the second conductor are the same or approximately the same.

[0013] Another embodiment of the present invention provides a semiconductor device including a first conductor, a second conductor, a first insulator, a first transistor and a second transistor on the first insulator, and a second insulator on the first transistor and the second transistor. The first transistor includes a first metal oxide, a third conductor and a fourth conductor electrically connected to the first metal oxide, respectively, a third insulator on the first metal oxide, and a fifth conductor on the third insulator. The second transistor includes a second metal oxide, a sixth conductor and a seventh conductor electrically connected to the second metal oxide, respectively, and a second The semiconductor device has a fourth insulator on a metal oxide and an eighth conductor on the fourth insulator, the top surface of the fifth conductor has a region in contact with the second insulator, the first conductor has a portion located inside an opening of the first insulator, a region in contact with a side surface of the third conductor, and a portion located inside the opening of the second insulator, the second conductor has a region in contact with the top surface of the fourth conductor and a portion located inside the opening of the second insulator, the second conductor and the eighth conductor are electrically connected, and the height of the top surface of the first conductor and the height of the top surface of the second conductor are the same or approximately the same.

[0014] Another embodiment of the present invention provides a semiconductor device including a first conductor, a second conductor, a first insulator, a first transistor, a second transistor, and a third transistor on the first insulator, and a second insulator on the first transistor, the second transistor, and the third transistor. The first transistor includes a first metal oxide, a third conductor and a fourth conductor electrically connected to the first metal oxide, respectively, the third insulator on the first metal oxide, and a fifth conductor on the third insulator. The second transistor includes a second metal oxide, a sixth conductor and a seventh conductor electrically connected to the second metal oxide, respectively, a fourth insulator on the second metal oxide, and an eighth conductor on the fourth insulator. a second metal oxide, a seventh conductor and a ninth conductor electrically connected to the second metal oxide, a fifth insulator on the second metal oxide, and a tenth conductor on the fifth insulator, wherein an upper surface of the fifth conductor and an upper surface of the tenth conductor have regions in contact with the second insulator, the first conductor has a portion located inside an opening of the first insulator, a region in contact with a side surface of the third conductor, and a portion located inside the opening of the second insulator, the second conductor has a region in contact with an upper surface of the fourth conductor and a portion located inside the opening of the second insulator, the second conductor and the eighth conductor are electrically connected, and the height of the upper surface of the first conductor and the height of the upper surface of the second conductor are the same or approximately the same.

[0015] Another embodiment of the present invention provides a transistor including a first conductor, a second conductor, a first insulator, a first transistor, a second transistor, and a third transistor on the first insulator, a second insulator on the first transistor, the second transistor, and the third transistor, and a capacitor. The first transistor includes a first metal oxide, a third conductor and a fourth conductor electrically connected to the first metal oxide, respectively, a third insulator on the first metal oxide, and a fifth conductor on the third insulator. The second transistor includes a second metal oxide, a sixth conductor and a seventh conductor electrically connected to the second metal oxide, respectively, a fourth insulator on the second metal oxide, and an eighth conductor on the fourth insulator. The third transistor includes a second metal oxide, a sixth conductor and a seventh conductor electrically connected to the second metal oxide, respectively. a seventh conductor and a ninth conductor connected to each other, a fifth insulator on the second metal oxide, and a tenth conductor on the fifth insulator; a capacitor having an eleventh conductor, a sixth insulator on the eleventh conductor, and a twelfth conductor on the sixth insulator; an upper surface of the fifth conductor and an upper surface of the tenth conductor have regions in contact with the second insulator; the first conductor has a portion located inside an opening of the first insulator, a region in contact with a side surface of the third conductor, and a portion located inside an opening of the second insulator; the second conductor has a region in contact with an upper surface of the fourth conductor and a portion located inside an opening of the second insulator; the second conductor and the eighth conductor are electrically connected via the eleventh conductor; and the height of the upper surface of the first conductor and the height of the upper surface of the second conductor are the same or approximately the same.

[0016] Another embodiment of the present invention provides a semiconductor device including a first conductor, a second conductor, a first insulator, a first transistor, a second transistor, and a third transistor on the first insulator, a second insulator on the first transistor, the second transistor, and the third transistor, and a capacitor, wherein the first transistor includes a first metal oxide, a third conductor and a fourth conductor electrically connected to the first metal oxide, respectively, and a third conductor on the first metal oxide. the second transistor has a second metal oxide, a sixth conductor and a seventh conductor each electrically connected to the second metal oxide, a fourth insulator on the second metal oxide, and an eighth conductor on the fourth insulator; the third transistor has a second metal oxide, a seventh conductor and a ninth conductor each electrically connected to the second metal oxide, and a fifth insulator on the second metal oxide; , and a tenth conductor on the fifth insulator, the capacitor has an eleventh conductor, a sixth insulator on the eleventh conductor, and a twelfth conductor on the sixth insulator, the thirteenth conductor electrically connected to the first conductor has a portion located inside an opening of the sixth insulator, the first conductor and the thirteenth conductor have overlapping regions, the top surface of the fifth conductor and the top surface of the tenth conductor have regions in contact with the second insulator, and the first conductor is connected to the first the second conductor has a region in contact with the top surface of the fourth conductor and a portion located inside the opening of the second insulator; the second conductor has a region in contact with the top surface of the fourth conductor and a portion located inside the opening of the second insulator; the second conductor and the eighth conductor are electrically connected via the eleventh conductor; and the height of the top surface of the first conductor and the height of the top surface of the second conductor are the same or approximately the same.

[0017] Another embodiment of the present invention provides a semiconductor device including a first conductor, a second conductor, a first insulator, a first transistor, a second transistor, and a third transistor on the first insulator, a second insulator on the first transistor, the second transistor, and the third transistor, and a capacitor, wherein the first transistor includes a first metal oxide, a third conductor and a fourth conductor electrically connected to the first metal oxide, respectively, a third insulator on the first metal oxide, and a third insulator on the third metal oxide. the second transistor has a second metal oxide, a sixth conductor and a seventh conductor each electrically connected to the second metal oxide, a fourth insulator on the second metal oxide, and an eighth conductor on the fourth insulator; the third transistor has a second metal oxide, a seventh conductor and a ninth conductor each electrically connected to the second metal oxide, a fifth insulator on the second metal oxide, and a tenth conductor on the fifth insulator. the capacitor has an eleventh conductor, a sixth insulator on the eleventh conductor, and a twelfth conductor on the sixth insulator; the first conductor and the thirteenth conductor are connected via a fourteenth conductor; the bottom surface of the fourteenth conductor has a region in contact with the top surface of the first conductor; the top surface of the fourteenth conductor has a region in contact with the thirteenth conductor and a region in contact with the sixth insulator; the top surface of the fifth conductor and the top surface of the tenth conductor have regions in contact with the second insulator; The semiconductor device is such that the first conductor has a portion located inside the opening of the first insulator, a region in contact with the side of the third conductor, and a portion located inside the opening of the second insulator, the second conductor has a region in contact with the top surface of the fourth conductor and a portion located inside the opening of the second insulator, the second conductor and the eighth conductor are electrically connected via the eleventh conductor, and the height of the top surface of the first conductor and the height of the top surface of the second conductor are the same or approximately the same.

[0018] In a semiconductor device of one embodiment of the present invention, the width of a region of the first conductor that is in contact with a side surface of the third conductor is preferably smaller than the width of a region of the first conductor that is in contact with a side surface of the second insulator in a cross-sectional view in the channel length direction.

[0019] In the semiconductor device of one embodiment of the present invention, the first metal oxide and the second metal oxide preferably contain indium, zinc, and one or more selected from gallium, aluminum, and tin.

[0020] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in the electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0021] According to one embodiment of the present invention, a method for manufacturing a semiconductor device with a reduced number of steps can be provided.

[0022] According to one embodiment of the present invention, a storage device with a large storage capacity can be provided. According to one embodiment of the present invention, a storage device with a small occupation area can be provided. According to one embodiment of the present invention, a storage device with high reliability can be provided. According to one embodiment of the present invention, a storage device with low power consumption can be provided. According to one embodiment of the present invention, a novel storage device can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0024] FIG. 1 is a cross-sectional view showing a structural example of a semiconductor device. FIG. 2A is a cross-sectional view showing a structural example of a semiconductor device. FIG. 2B is a cross-sectional view showing a structural example of a transistor. FIG. 3 is a cross-sectional view showing a structural example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing a structural example of a semiconductor device. FIG. 5 is a cross-sectional view showing a structural example of a semiconductor device. FIG. 6 is a cross-sectional view showing a structural example of a semiconductor device. FIG. 7 is a cross-sectional view showing a structural example of a semiconductor device. FIGS. 8A and 8B are plan views showing a structural example of a semiconductor device. FIGS. 9A to 9E are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 12A and 12B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 13A and 13B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 14A and 14B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 15A and 15B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 16 is a cross-sectional view illustrating an example of a manufacturing method of a semiconductor device. FIG. 17 is a cross-sectional view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 18A and 18B are diagrams illustrating an example of a memory device. FIGS. 19A and 19B are circuit diagrams illustrating an example of a memory layer. FIG. 20 is a timing chart illustrating an example of operation of a memory cell. FIGS. 21A and 21B are circuit diagrams illustrating an example of operation of a memory cell. FIGS. 22A and 22B are circuit diagrams illustrating an example of operation of a memory cell. FIG. 23 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIGS. 24A and 24B are diagrams illustrating an example of a semiconductor device. FIGS. 25A and 25B are diagrams illustrating an example of an electronic component. FIGS. 26A to 26J are diagrams illustrating an example of electronic equipment. FIGS. 27A to 27E are diagrams illustrating an example of electronic equipment. FIGS. 28A to 28C are diagrams illustrating an example of electronic equipment. FIG. 29 is a diagram illustrating an example of space equipment.

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0027] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0028] In this specification, the ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, an ordinal number assigned to a component in one part of this specification may not match an ordinal number assigned to the same component in another part of this specification or in the claims.

[0029] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0030] In this specification, terms indicating position, such as "above," "below," "upward," or "below" may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in this specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located above a conductor" can be rephrased as "insulator located below a conductor" by rotating the orientation of the drawing 180 degrees.

[0031] In this specification, the term "having the same or approximately the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a semiconductor device manufacturing process, a planarization process (typically a CMP (Chemical Mechanical Polishing) process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces processed by the CMP process have the same height from the reference surface. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "having the same or approximately the same height." For example, in the case of a structure having two layers (here, a first layer and a second layer) with different heights relative to the reference surface, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "having the same or approximately the same height."

[0032] In this specification, "edges that coincide or approximately coincide" means that, when viewed from above, at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "edges that coincide or approximately coincide" is also used.

[0033] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0034] One embodiment of the present invention relates to a semiconductor device including a memory layer over a substrate. The memory layer includes a first transistor, a second transistor, a third transistor, and a capacitor, and these transistors can form a memory cell. The semiconductor device of one embodiment of the present invention has a function of storing data because it includes a memory cell. Therefore, the semiconductor device of one embodiment of the present invention can be referred to as a memory device.

[0035] The first transistor has a first metal oxide, first and second conductors covering a portion of the top surface and side surfaces of the first metal oxide, a first insulator provided between the first and second conductors, and a third conductor on the first insulator. The second transistor has a second metal oxide, a fourth conductor covering a portion of the top surface and side surfaces of the second metal oxide, a fifth conductor covering a portion of the top surface of the second metal oxide, a second insulator provided between the fourth and fifth conductors, and a sixth conductor on the second insulator. The third transistor has a second metal oxide, a fifth conductor, a seventh conductor covering a portion of the top surface and side surfaces of the second metal oxide, a third insulator provided between the fifth and seventh conductors, and an eighth conductor on the third insulator. That is, the second transistor and the third transistor share the second metal oxide and the fifth conductor. Note that it is also referred to as the first metal oxide being electrically connected to the first and second conductors, respectively. It is also referred to as the second metal oxide being electrically connected to the fourth and fifth conductors, respectively. It is also referred to as the second metal oxide being electrically connected to the fifth and seventh conductors, respectively.

[0036] The first metal oxide has a region that functions as a channel formation region of the first transistor. The first conductor has a region that functions as one of the source electrode and the drain electrode of the first transistor. The second conductor has a region that functions as the other of the source electrode and the drain electrode of the first transistor. The third conductor has a region that functions as the gate electrode of the first transistor. The first insulator has a region that functions as a gate insulator of the first transistor.

[0037] The second metal oxide has a region that functions as a channel formation region of the second and third transistors. The fourth conductor has a region that functions as one of a source electrode or a drain electrode of the second transistor. The fifth conductor has a region that functions as the other of a source electrode or a drain electrode of the second transistor and one of a source electrode or a drain electrode of the third transistor. The sixth conductor has a region that functions as a gate electrode of the second transistor. The seventh conductor has a region that functions as the other of a source electrode or a drain electrode of the third transistor. The eighth conductor has a region that functions as a gate electrode of the third transistor. The second insulator has a region that functions as a gate insulator of the second transistor. The third insulator has a region that functions as a gate insulator of the third transistor.

[0038] The second transistor and the third transistor are adjacent to each other and share the second metal oxide and the fifth conductor, respectively, so that the two transistors can be formed in an area smaller than the area of ​​two transistors (for example, the area of ​​1.5 transistors), which allows the transistors to be arranged at high density and realizes high integration in the semiconductor device.

[0039] A semiconductor device according to one embodiment of the present invention includes a transistor having a metal oxide in a channel formation region (OS transistor). Because the off-state current of an OS transistor is low, stored data can be retained for a long time when used in a semiconductor device that can be used as a memory device. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the OS transistor has high frequency characteristics, the semiconductor device can read and write data at high speed.

[0040] In a semiconductor device according to one embodiment of the present invention, a plurality of memory layers having the above structure are stacked. That is, a plurality of memory layers having the above structure are provided, for example, in a direction perpendicular to a substrate surface. This allows the memory capacity of the semiconductor device to be increased without increasing the area occupied by the memory cell compared to a case where a single memory layer is used. Therefore, the area occupied per bit is reduced, and a small-sized semiconductor device with a large memory capacity can be realized.

[0041] When a plurality of memory layers are stacked, the write bit line and the read bit line can be provided, for example, in a direction perpendicular to the substrate surface. For example, when a semiconductor device having n memory layers (n is an integer of 2 or greater) is formed, a connection electrode that vertically connects conductors included in the n memory layers can be formed to form a write bit line and a read bit line extending in the vertical direction. In the semiconductor device of one embodiment of the present invention, a conductor having a region that functions as a write bit line is provided so as to have a region in contact with the top surface and side surface of the first conductor. In addition, in the semiconductor device of one embodiment of the present invention, a conductor having a region that functions as a read bit line is provided so as to have a region in contact with the top surface and side surface of the seventh conductor. This structure eliminates the need to provide a separate connection electrode between the first conductor and the write bit line. Furthermore, it eliminates the need to provide a separate connection electrode between the seventh conductor and the read bit line. As described above, the semiconductor device of one embodiment of the present invention can be a semiconductor device with a high degree of integration of memory cells.

[0042] <Structural Example of Semiconductor Device> A structural example of a semiconductor device of one embodiment of the present invention will be described below.

[0043] 1 is a cross-sectional view illustrating a structural example of a semiconductor device according to one embodiment of the present invention. The semiconductor device illustrated in FIG. 1 includes an insulator 210 over a substrate (not shown), conductors 209a and 209b embedded in the insulator 210, an insulator 212 over the insulator 210, an insulator 214 over the insulator 212, an n-layer memory layer 11 over the insulator 214, connection electrodes connecting the conductors of the n-layer in the Z direction (also referred to as the vertical direction) are formed to extend in the Z direction, thereby forming connection electrodes 240a and 240b electrically connected to the conductor 209, an insulator 181 over the memory layer 11_n, an insulator 183 over the insulator 181, and an insulator 185 over the insulator 183. Note that each of the components included in the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure.

[0044] Hereinafter, when describing matters common to components distinguished by alphabets, the components may be described using symbols without the alphabets. For example, when describing matters common to conductors 209a and 209b, the conductor may be referred to as conductor 209.

[0045] Each of the memory layers 11_1 to 11_n includes a memory cell array having a plurality of memory cells. The memory cell includes a transistor 201, a transistor 202, a transistor 203, and a capacitor 101. The connection electrode 240a has a region that functions as a write bit line, and the connection electrode 240b has a region that functions as a read bit line.

[0046] In this specification and the like, the direction parallel to the channel length direction of the illustrated transistor is referred to as the X direction, and the direction parallel to the channel width direction of the illustrated transistor is referred to as the Y direction. The X direction and the Y direction may be perpendicular to each other. Furthermore, the direction perpendicular to both the X direction and the Y direction, i.e., the direction perpendicular to the XY plane, is referred to as the Z direction. The X direction and the Y direction may be parallel to the substrate surface, for example, and the Z direction may be perpendicular to the substrate surface.

[0047] The conductors 209a and 209b function as parts, wirings, electrodes, or terminals of circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes.

[0048] FIG. 1 shows, of the n memory layers, a memory layer 11_1 which is the bottom layer, a memory layer 11_2 on the memory layer 11_1, and a memory layer 11_n which is the top layer.

[0049] The conductors 209a and 209b are electrically connected to a drive circuit for driving the memory cells provided in the memory layer 11. The drive circuit is provided below the conductors 209a and 209b. By increasing the number of stacked layers (the number n) in the memory layer 11, the memory capacity of the memory device can be increased without increasing the area occupied by the memory cells. This reduces the area occupied per bit, making it possible to realize a small-sized semiconductor device with a large memory capacity.

[0050] The transistors 201, 202, and 203 are provided over an insulator 214. The transistors 202 and 203 share some layers. A capacitor 101 is provided above the transistors 201 to 203.

[0051] 2A is a cross-sectional view illustrating a configuration example of the conductor 209a, the conductor 209b, the insulator 210, the insulator 212, the insulator 214, and the memory layer 11. As shown in FIG. 2A, an insulator 282 is provided over the transistors 201 to 203, and a capacitor 101 is provided over the insulator 282.

[0052] Transistor 201, transistor 202, and transistor 203 each have a conductor 205a1 on insulator 214, an insulator 222 on conductor 205a1, an insulator 224 on insulator 222, a metal oxide 230 (metal oxide 230a and metal oxide 230b) on insulator 224, a conductor 242 covering part of the side of insulator 224 and part of the top surface and part of the side of metal oxide 230, an insulator 253 on metal oxide 230, an insulator 254 on insulator 253, and a conductor 260 on insulator 254. Here, the transistor 201 has a conductor 242a and a conductor 242b as the conductor 242, the transistor 202 has a conductor 242c and a conductor 242d as the conductor 242, and the transistor 203 has a conductor 242d and a conductor 242e as the conductor 242. The transistors 202 and 203 share the metal oxide 230 and the conductor 242d, respectively.

[0053] An insulator 216a having an opening is provided over the insulator 214, and a conductor 205a1 is embedded in the opening. An insulator 222 is provided over the conductor 205a1 and the insulator 216a. An insulator 275 is provided over the conductors 242a to 242e, and an insulator 280 is provided over the insulator 275. The insulators 253, 254, and conductor 260 are embedded in the openings provided in the insulator 280 and the insulator 275. An insulator 282 is provided over the insulator 280 and the conductor 260, and an insulator 285 is provided over the insulator 282. The conductor 205a1 can have a region in contact with a side surface of the insulator 216a. Furthermore, the insulator 253 may have an area that contacts at least a portion of the side of the conductor 242 , the side of the insulator 275 , and the side of the insulator 280 .

[0054] The metal oxide 230 has a region that functions as a channel formation region of the transistor 201, the transistor 202, or the transistor 203. Note that instead of the metal oxide 230, the transistor 201, the transistor 202, or the transistor 203 may be formed using a semiconductor such as single crystal silicon, polycrystalline silicon, or amorphous silicon, such as low temperature polysilicon (LTPS).

[0055] The conductor 242a has a region functioning as one of the source electrode and the drain electrode of the transistor 201. The conductor 242b has a region functioning as the other of the source electrode and the drain electrode of the transistor 201. The conductor 242c has a region functioning as one of the source electrode and the drain electrode of the transistor 202. The conductor 242d has a region functioning as the other of the source electrode and the drain electrode of the transistor 202 and one of the source electrode and the drain electrode of the transistor 203. The conductor 242e has a region functioning as the other of the source electrode and the drain electrode of the transistor 203.

[0056] The conductor 260 has a region that functions as a first gate electrode of the transistor 201, the transistor 202, or the transistor 203. The insulator 253 and the insulator 254 have a region that functions as a first gate insulator of the transistor 201, the transistor 202, or the transistor 203, respectively.

[0057] The conductor 205a1 has a region functioning as the second gate electrode of the transistor 201, the transistor 202, or the transistor 203. The insulator 222 has a region functioning as the second gate insulator of the transistor 201, a region functioning as the second gate insulator of the transistor 202, and a region functioning as the second gate insulator of the transistor 203. The insulator 224 has a region functioning as the second gate insulator of the transistor 201, the transistor 202, or the transistor 203.

[0058] In this specification and the like, the first gate electrode can be referred to as a front gate electrode or simply as a gate electrode, and the second gate electrode can be referred to as a back gate electrode. Note that the first gate electrode may be referred to as a back gate electrode, and the second gate electrode may be referred to as a front gate electrode or simply as a gate electrode.

[0059] The transistors 202 and 203 are adjacent to each other and share the metal oxide 230 and the conductor 242d as described above. This allows the two transistors (the transistors 202 and 203) to be formed in an area smaller than the area of ​​two transistors (for example, the area of ​​1.5 transistors). Therefore, the transistors can be arranged more densely than when the transistors 202 and 203 do not share the metal oxide 230 and the conductor 242d, thereby achieving high integration in the semiconductor device.

[0060] Furthermore, the conductor 242d is disposed in a region between the conductor 260 of the transistor 202 and the conductor 260 of the transistor 203. Therefore, an n-type region (low resistance region) can be formed in a region of the metal oxide 230 that overlaps with the conductor 242d. In particular, an n-type region can be formed in a region of the metal oxide 230b that overlaps with the conductor 242d. Furthermore, a current can flow between the transistor 202 and the transistor 203 through the conductor 242d. Therefore, the resistance component between the transistor 202 and the transistor 203 can be significantly reduced compared to a configuration in which two transistors using silicon (also referred to as Si transistors) in a semiconductor layer in which a channel is formed are connected in series.

[0061] The capacitor 101 includes a conductor 160c on an insulator 285, an insulator 215 on the conductor 160c, and a conductor 205b on the insulator 215.

[0062] An insulator 287 is provided on the insulator 285. Openings are provided in the insulator 287, and conductors 160a, 160b, and 160c (sometimes collectively referred to as conductors 160) are embedded inside the openings. An insulator 215 is provided on the conductor 160 and on the insulator 287. An insulator 216b having openings is provided on the insulator 215, and conductors 205a2 and 205b are embedded inside the openings. The conductor 160 can have a region in contact with part of the side surface of the insulator 287. The conductors 205a2 and 205b can also have a region in contact with the side surface of the insulator 216b.

[0063] Hereinafter, when describing matters common to the conductor 205a1 and the conductor 205a2, they may be referred to as the conductor 205a. Furthermore, when describing matters common to the conductor 205a and the conductor 205b, they may be referred to as the conductor 205.

[0064] The conductor 160c has a region that functions as one electrode (also referred to as a lower electrode) of the capacitor 101. The insulator 215 has a region that functions as a dielectric of the capacitor 101. The conductor 205b has a region that functions as the other electrode (also referred to as an upper electrode) of the capacitor 101. The capacitor 101 forms a metal-insulator-metal (MIM) capacitor.

[0065] The insulators 275, 280, 282, and 285 have openings that reach the conductor 242b, and the conductor 231 is embedded in the openings. The insulators 282 and 285 have openings that reach the conductor 260 of the transistor 202, and the conductor 232 is embedded in the openings. The conductor 242b and the conductor 160c are electrically connected by the conductor 231. The conductor 260 of the transistor 202 is electrically connected to the conductor 160c by the conductor 232. As described above, the conductor 242b, which has a region that functions as the other of the source electrode and drain electrode of the transistor 201, is electrically connected to the conductor 260, which has a region that functions as the gate electrode of the transistor 202, through the conductor 231, the conductor 160c, and the conductor 232. The conductor 160c has an area in contact with the upper surface of the conductor 231 and the upper surface of the conductor 232.

[0066] Openings reaching the conductor 209a are provided in the insulators 212, 214, 216a, 222, 275, 280, 282, and 285, and the conductor 233a1 is embedded in the openings. Openings reaching the conductor 160a are provided in the insulators 215 and 216b, and the conductor 233a2 is embedded in the openings. Therefore, it can be said that the conductor 233a1 has a region in contact with one or more side surfaces of the insulators 212, 214, 216a, 222, 275, 280, 282, and 285. It can also be said that the conductor 233a2 has a region in contact with one or both side surfaces of the insulators 215 and 216b.

[0067] In other words, the conductor 233a1 can be said to have a portion located inside one or more of the openings of the insulator 212, the openings of the insulator 214, the openings of the insulator 216a, the openings of the insulator 222, the openings of the insulator 275, the openings of the insulator 280, the openings of the insulator 282, and the openings of the insulator 285. The conductor 233a2 can be said to have a portion located inside one or both of the openings of the insulator 215 and the openings of the insulator 216b.

[0068] Furthermore, openings reaching conductor 209b are provided in insulators 212, 214, 216a, 222, 275, 280, 282, and 285, and conductor 233b1 is embedded in the openings. Openings reaching conductor 160b are provided in insulators 215 and 216b, and conductor 233b2 is embedded in the openings. Therefore, it can be said that conductor 233b1 has a region in contact with one or more side surfaces of insulators 212, 214, 216a, 222, 275, 280, 282, and 285. It can also be said that conductor 233b2 has a region in contact with one or both side surfaces of insulators 215 and 216b. In addition, when describing matters common to the conductor 233a1, the conductor 233a2, the conductor 233b1, and the conductor 233b2, they may be referred to as conductor 233.

[0069] In other words, the conductor 233b1 has a portion located inside one or more of the openings of the insulator 212, the openings of the insulator 214, the openings of the insulator 216a, the openings of the insulator 222, the openings of the insulator 275, the openings of the insulator 280, the openings of the insulator 282, and the openings of the insulator 285. The conductor 233b2 has a portion located inside one or both of the openings of the insulator 215 and the openings of the insulator 216b.

[0070] The upper surface of conductor 209a has a region in contact with conductor 233a1. The upper surface of conductor 233a1 has a region in contact with conductor 160a. The upper surface of conductor 160a has a region in contact with conductor 233a2. In this manner, connection electrode 240a has conductor 233a1 and conductor 160a. Note that, in the range shown in FIG. 2A , connection electrode 240a can be said to have conductor 233a1, conductor 160a, and conductor 233a2.

[0071] Furthermore, the upper surface of conductor 209b has a region in contact with conductor 233b1. The upper surface of conductor 233b1 has a region in contact with conductor 160b. The upper surface of conductor 160b has a region in contact with conductor 233b2. In this manner, connection electrode 240b has conductor 233b1 and conductor 160b. Note that, in the range shown in FIG. 2A , connection electrode 240b can be said to have conductor 233b1, conductor 160b, and conductor 233b2.

[0072] As described above and shown in FIG. 2A, the height of the top surface of the conductor 231, the height of the top surface of the conductor 232, the height of the top surface of the conductor 233a1, and the height of the top surface of the conductor 233b1 are the same or approximately the same.

[0073] The conductors 242a, 242b, 242c, and 242e extend beyond the metal oxide 230, which functions as a semiconductor layer, and cover part of the upper surface and side surface of the metal oxide 230. Therefore, the conductors 242a, 242b, 242c, and 242e also function as wirings. For example, a connection electrode 240a having a region that functions as a write bit line is provided so as to have a region that contacts the upper surface and part of the side surface of the conductor 242a. Furthermore, a connection electrode 240b having a region that functions as a read bit line is provided so as to have a region that contacts the upper surface and part of the side surface of the conductor 242e. Note that the conductor 242d can also function as a wiring. In addition, other wirings may also function as wirings.

[0074] Since the connection electrode 240a has an area in contact with the upper surface and a portion of the side surface of the conductor 242a, and the connection electrode 240b has an area in contact with the upper surface and a portion of the side surface of the conductor 242e, there is no need to provide a separate connection electrode, thereby reducing the area occupied by the memory cell array. This also improves the integration density of memory cells, thereby increasing memory capacity. Furthermore, since the connection electrode 240a contacts multiple surfaces of the conductor 242a, the contact resistance between the connection electrode 240a and the conductor 242a can be reduced, and since the connection electrode 240b contacts multiple surfaces of the conductor 242e, the contact resistance between the connection electrode 240b and the conductor 242e can be reduced.

[0075] FIG. 2B is a cross-sectional view showing an example of the configuration of the transistor shown in FIG. 2A in the channel width direction, that is, in the Y direction.

[0076] 2B , an insulator 212 is provided on an insulator 210, an insulator 214 is provided on an insulator 212, an insulator 216a is provided on an insulator 214, and a conductor 205a1 is provided inside an opening provided in the insulator 216a. Furthermore, an insulator 222 is provided on the conductor 205a1 and on the insulator 216a, an insulator 224 and an insulator 275 are provided on the insulator 222, and a metal oxide 230 is provided on the insulator 224. The side surface of the insulator 224 and the top and side surfaces of the metal oxide 230 are covered with an insulator 253, an insulator 254, and a conductor 260. The insulators 253, 254, and conductor 260 are provided inside an opening 258 of an insulator 280 provided on the insulator 275. An insulator 282 is provided over the insulators 253 , 254 , conductors 260 , and insulator 280 , and an insulator 285 is provided over the insulator 282 .

[0077] Here, it can be said that not only the top surface but also the side surfaces of the metal oxide 230 are covered with the conductor 260 having a region that functions as the first gate electrode.

[0078] In this specification, etc., a transistor structure in which a channel formation region is electrically surrounded by the electric field of at least a first gate electrode is called a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification, etc., is different from a Fin structure and a planar structure. On the other hand, the S-channel structure disclosed in this specification, etc., can also be regarded as a type of Fin structure. In this specification, etc., a Fin structure refers to a structure in which a gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides). By employing the Fin structure and the S-channel structure, resistance to the short channel effect can be increased, in other words, a transistor in which the short channel effect is less likely to occur can be obtained.

[0079] By forming the transistor included in the semiconductor device of this embodiment into the S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore, can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming the transistor into the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide and the gate insulator can be the entire bulk of the oxide. Therefore, the current density flowing through the transistor can be improved, which is expected to improve the on-state current of the transistor or the field-effect mobility of the transistor.

[0080] 2B is an example of a transistor having an S-channel structure, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistor structure that can be used in one embodiment of the present invention may be one or more selected from a planar structure, a Fin structure, and a GAA structure.

[0081] The cross-sectional shape of the metal oxide 230 is not limited to the configuration shown in Fig. 2B. For example, the metal oxide 230 may have a curved surface between the side surface and the top surface. This can improve the coverage of the film formed on the metal oxide 230.

[0082] Figure 3 is a modified example of the configuration shown in Figure 2A, in which the conductor 233a1 of the connection electrode 240a has an area that contacts the upper surface, side surface, and part of the lower surface of the conductor 242a, and the conductor 233b1 of the connection electrode 240b has an area that contacts the upper surface, side surface, and part of the lower surface of the conductor 242e.

[0083] As shown in FIG. 3 , the connection electrode 240a has a region in contact with the upper surface, side surface, and part of the lower surface of the conductor 242a, and the connection electrode 240b has a region in contact with the upper surface, side surface, and part of the lower surface of the conductor 242e. This eliminates the need for separate connection electrodes, thereby reducing the area occupied by the memory cell array. Furthermore, the integration density of memory cells is improved, resulting in increased storage capacity. The connection electrode 240a has a region in contact with two or more of the upper surface, side surface, and lower surface of the conductor 242a, while the connection electrode 240b has a region in contact with two or more of the upper surface, side surface, and lower surface of the conductor 242e. The connection electrode 240a contacting multiple surfaces of the conductor 242a reduces the contact resistance between the connection electrode 240a and the conductor 242a. The connection electrode 240b contacting multiple surfaces of the conductor 242e reduces the contact resistance between the connection electrode 240b and the conductor 242e.

[0084] 4A is an enlarged view of a portion of connection electrode 240a in FIG. 2A and its surrounding area. In FIG. 4A, the width of a region of conductor 233a1 of connection electrode 240a that contacts the side surface of insulator 216a is defined as width W1, the width of a region of conductor 242 that contacts the side surface of insulator 242 is defined as width W2, the width of a region of insulator 280 that contacts the side surface of insulator 285 is defined as width W3, and the width of a region of conductor 233a2 of connection electrode 240a that contacts the side surface of insulator 216b is defined as width W5.

[0085] 4A , in a cross-sectional view, it is preferable that at least a portion of widths W1, W3, W4, and W5 is larger than width W2. In this configuration, conductor 233a1 contacts at least a portion of the top surface and side surface of conductor 242. Therefore, the area of ​​the region where conductor 233a1 and conductor 242 contact can be increased. Note that in this specification and the like, the contact between conductor 233a1 and conductor 242 is sometimes referred to as a top-side contact.

[0086] Fig. 4B is an enlarged view of a portion of connection electrode 240a and its surrounding area in Fig. 3. In Fig. 4B, the width of a region of conductor 233a1 of connection electrode 240a that contacts the side surface of insulator 216a is width W1, the width of a region of conductor 242 that contacts the side surface of insulator 242 is width W2, the width of a region of insulator 280 that contacts the side surface of insulator 280 is width W3, and the width of a region of insulator 285 that contacts the side surface of insulator 216b is width W4. Furthermore, the width of a region of conductor 233a1 of connection electrode 240a that contacts the side surface of insulator 216b is width W5.

[0087] As shown in FIG. 4B , in a cross-sectional view, it is preferable that at least a portion of widths W1, W3, W4, and W5 is larger than width W2. In this configuration, conductor 233a1 contacts at least a portion of the upper surface and side surface of conductor 242. Therefore, the area of ​​the region where conductor 233a1 and conductor 242 contact can be increased. Note that in this specification, the contact between conductor 233a1 and conductor 242 is sometimes referred to as a top-side contact. Furthermore, as shown in FIG. 4B , conductor 233a1 may contact a portion of the lower surface of conductor 242. With this configuration, the area of ​​the region where conductor 233a1 and conductor 242 contact can be further increased.

[0088] FIG. 5 shows a modified example of the configuration shown in FIG. 2A, in which the connection electrode 240a does not have the conductor 160a, and the connection electrode 240b does not have the conductor 160b.

[0089] 5, openings reaching the conductor 233a1 are provided in the insulators 287, 215, and 216b, and the conductor 233a2 is embedded in the openings. Also, openings reaching the conductor 233b1 are provided in the insulators 287, 215, and 216b, and the conductor 233b2 is embedded in the openings.

[0090] Next, a transistor included in the semiconductor device of this embodiment mode will be described in detail.

[0091] The metal oxide 230 preferably has a metal oxide 230a on the insulator 224 and a metal oxide 230b on the metal oxide 230a. By having the metal oxide 230a below the metal oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the metal oxide 230a to the metal oxide 230b.

[0092] In this embodiment, the metal oxide 230 has a two-layer structure of the metal oxide 230 a and the metal oxide 230 b, but is not limited thereto. The metal oxide 230 may have, for example, a single-layer structure of the metal oxide 230 b, or a stacked structure of three or more layers.

[0093] The metal oxide 230b includes a channel formation region of the transistor, and a source region and a drain region provided to sandwich the channel formation region. At least a part of the channel formation region overlaps with the conductor 260. The source region overlaps with one of the pair of conductors 242, and the drain region overlaps with the other of the pair of conductors 242.

[0094] The channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0095] The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, the source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0096] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0097] Note that when the carrier concentration of the metal oxide 230b is reduced, the impurity concentration in the metal oxide 230b is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0098] In order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide 230b. Furthermore, in order to reduce the impurity concentration in the metal oxide 230b, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the metal oxide 230b refer to, for example, elements other than the main component constituting the metal oxide 230b. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0099] Note that the channel formation region, the source region, and the drain region may each be formed not only with the metal oxide 230b but also with the metal oxide 230a.

[0100] Furthermore, it may be difficult to clearly detect the boundaries between regions in the metal oxide 230. The concentrations of the metal element and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, the concentrations of the metal element and impurity elements such as hydrogen and nitrogen may decrease in regions closer to the channel formation region.

[0101] The metal oxide 230 is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0102] The band gap of the metal oxide functioning as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. Use of a metal oxide with a wide band gap can reduce the off-state current of a transistor.

[0103] The metal oxide 230 preferably includes metal oxides such as indium oxide, gallium oxide, and zinc oxide. The metal oxide 230 preferably includes two or three elements selected from the group consisting of indium, element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. The element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin. A metal oxide including indium, element M, and zinc may be referred to as an In-M-Zn oxide.

[0104] The metal oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for the metal oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the metal oxide 230b. Furthermore, in the metal oxide used for the metal oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the metal oxide 230b. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the metal oxide 230a into the metal oxide 230b.

[0105] In the metal oxide used for the metal oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the metal oxide 230a. With this structure, the transistor can have large on-state current and high frequency characteristics.

[0106] Furthermore, since the metal oxide 230a and the metal oxide 230b contain a common element other than oxygen as a main component, the density of defect states at the interface between the metal oxide 230a and the metal oxide 230b can be reduced. This reduces the effect of interface scattering on carrier conduction, and the transistor can achieve a large on-state current and high frequency characteristics.

[0107] Specifically, the metal oxide 230a may be a metal oxide having an atomic ratio of In:M:Zn = 1:3:4 or a similar composition, or an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition. The metal oxide 230b may be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M. Furthermore, when a single layer of metal oxide 230b is provided as the metal oxide 230, the metal oxide 230b may be the same as that used for the metal oxide 230a. The compositions of the metal oxides that can be used for the metal oxide 230a and the metal oxide 230b are not limited to those described above. For example, the composition of the metal oxide that can be used for the metal oxide 230a may be used for the metal oxide 230b. Similarly, the composition of the metal oxide that can be used for the metal oxide 230b may be used for the metal oxide 230a.

[0108] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0109] The metal oxide 230b preferably has crystallinity. In particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the metal oxide 230b.

[0110] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not polycrystallize after formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0111] Furthermore, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0112] Furthermore, by using a crystalline oxide such as CAAC-OS as the metal oxide 230b, extraction of oxygen from the metal oxide 230b by the source electrode or the drain electrode can be suppressed, and thus even when heat treatment is performed, extraction of oxygen from the metal oxide 230b can be reduced, making the transistor stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0113] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in a region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V ＯIt is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration in a region where a channel is formed in the oxide semiconductor be reduced and that the region be i-type (intrinsic) or substantially i-type.

[0114] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor may decrease. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of a semiconductor device including the transistor may vary. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, and the conductivity may be impaired, which may adversely affect the electrical characteristics and reliability of the transistor.

[0115] Therefore, in an oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242, and the like. Note that hydrogen in the oxide semiconductor is converted into V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0116] Therefore, in this embodiment, the semiconductor device is configured to reduce the hydrogen concentration in the channel formation region, suppress oxidation of the conductor 242 and the conductor 260, and further suppress reduction in the hydrogen concentration in the source and drain regions.

[0117] The insulator 253 in contact with the channel formation region of the metal oxide 230b preferably has a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the metal oxide 230b. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0118] Examples of insulators that have the function of capturing and fixing hydrogen include metal oxides with an amorphous structure. For example, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium as the insulator 253. In such metal oxides with an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides with an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0119] It is also preferable to use a high-dielectric constant (high-k) material for the insulator 253. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulator 253 makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0120] For the above reasons, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 253, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use hafnium oxide having an amorphous structure. In this embodiment, hafnium oxide is used as the insulator 253. In this case, the insulator 253 is an insulator containing at least oxygen and hafnium. Furthermore, the hafnium oxide has an amorphous structure. In this case, the insulator 253 has an amorphous structure.

[0121] Alternatively, an insulator having a thermally stable structure, such as silicon oxide or silicon oxynitride, may be used for the insulator 253. For example, a stacked layer structure including aluminum oxide and silicon oxide or silicon oxynitride on the aluminum oxide may be used for the insulator 253. Alternatively, for example, a stacked layer structure including aluminum oxide, silicon oxide or silicon oxynitride on the aluminum oxide, and hafnium oxide on the silicon oxide or silicon oxynitride may be used for the insulator 253.

[0122] In order to suppress oxidation of the conductor 242 and the conductor 260, it is preferable to provide a barrier insulator against oxygen near each of the conductor 242 and the conductor 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulator 253, the insulator 254, and the insulator 275.

[0123] In this specification and the like, a barrier insulator refers to an insulator having barrier properties. In this specification and the like, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0124] Examples of oxygen barrier insulators include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulators 253, 254, and 275 each preferably have a single-layer structure or a stacked-layer structure of the above oxygen barrier insulators.

[0125] The insulator 253 preferably has a barrier property against oxygen. The insulator 253 is preferably at least less permeable to oxygen than the insulator 280. The insulator 253 has a region that contacts the side surface of the conductor 242. The insulator 253 has a barrier property against oxygen, which can prevent the side surface of the conductor 242 from being oxidized and an oxide film from being formed on the side surface. This can prevent a decrease in the on-state current or a decrease in the field-effect mobility of the transistor.

[0126] The insulator 253 is provided in contact with the top surface and side surface of the metal oxide 230b, the side surface of the metal oxide 230a, the side surface of the insulator 224, and the top surface of the insulator 222. The insulator 253 has a barrier property against oxygen, which can prevent oxygen from being released from the channel formation region of the metal oxide 230b, for example, during heat treatment. Therefore, the formation of oxygen vacancies in the metal oxide 230a and the metal oxide 230b can be reduced.

[0127] Conversely, even if the insulator 280 contains an excessive amount of oxygen, the oxygen can be prevented from being excessively supplied to the metal oxide 230 a and the metal oxide 230 b, thereby preventing the source and drain regions from being excessively oxidized, thereby preventing a decrease in the on-state current or the field-effect mobility of the transistor.

[0128] An oxide containing one or both of aluminum and hafnium has a barrier property against oxygen and can therefore be suitably used as the insulator 253 .

[0129] The insulator 254 preferably has a barrier property against oxygen. The insulator 254 is provided between the channel formation region of the metal oxide 230 and the conductor 260, and between the insulator 280 and the conductor 260. This structure can prevent oxygen contained in the channel formation region of the metal oxide 230 from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the metal oxide 230. Furthermore, it can prevent oxygen contained in the metal oxide 230 and oxygen contained in the insulator 280 from diffusing to the conductor 260 and oxidizing the conductor 260. The insulator 254 is preferably at least less permeable to oxygen than the insulator 280. For example, silicon nitride is preferably used as the insulator 254. In this case, the insulator 254 is an insulator containing at least nitrogen and silicon.

[0130] The insulator 254 preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the metal oxide 230b.

[0131] The insulator 275 preferably has a barrier property against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242. This configuration can prevent oxygen contained in the insulator 280 from diffusing into the conductor 242. Therefore, it is possible to prevent the conductor 242 from being oxidized by the oxygen contained in the insulator 280, which would increase its resistivity and reduce its on-current. The insulator 275 is preferably at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0132] To suppress a decrease in the hydrogen concentration in the source and drain regions in the metal oxide 230, it is preferable to provide a barrier insulator against hydrogen near each of the source and drain regions. In the semiconductor device described in this embodiment, the barrier insulator against hydrogen is, for example, the insulator 275.

[0133] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 preferably has a single-layer structure or a stacked structure of the above-mentioned barrier insulator against hydrogen.

[0134] The insulator 275 preferably has a barrier property against hydrogen. The insulator 275 having a barrier property against hydrogen can prevent the insulator 253 from capturing and fixing hydrogen in the source and drain regions. Therefore, the source and drain regions can be made n-type.

[0135] By adopting the above structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, thereby providing a semiconductor device with good electrical characteristics. Furthermore, by adopting the above structure, the semiconductor device can have good electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0136] The insulators 253 and 254 each function as part of a gate insulator. The insulators 253 and 254, together with the conductor 260, are provided in openings formed in the insulator 280 or the like. To miniaturize the transistor, the thicknesses of the insulators 253 and 254 are preferably small. The thickness of the insulator 253 is preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. The thickness of the insulator 254 is preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 3.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that the insulators 253 and 254 each may have a region with the above thickness at least in part.

[0137] To thin the insulator 253 as described above, it is preferable to form the film using atomic layer deposition (ALD). The ALD method includes thermal ALD, in which a precursor and a reactant react using only thermal energy, and plasma enhanced ALD, in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, which allows film formation at a lower temperature.

[0138] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling the formation of extremely thin films, the formation of films on structures with high aspect ratios, the formation of films with few defects such as pinholes, the formation of films with excellent coverage, and the formation of films at low temperatures, etc. Therefore, the insulator 253 can be formed with good coverage on the side surfaces of the openings formed in the insulator 280, etc., and on the side ends of the conductor 242, etc., with the thin film thickness as described above.

[0139] Note that some precursors used in the ALD method contain, for example, carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0140] For example, the insulator 254 can be made of silicon nitride formed by the PEALD method.

[0141] Note that by using an insulator such as hafnium oxide that has a function of suppressing permeation of impurities such as hydrogen and oxygen as the insulator 253, the insulator 253 can also have the function of the insulator 254. In such a case, by not providing the insulator 254, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0142] In addition to the above structure, the semiconductor device in this embodiment preferably has a structure that prevents hydrogen from entering the transistor. For example, an insulator that has a function of preventing hydrogen diffusion is preferably provided so as to cover one or both of the top and bottom of the transistor. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 212.

[0143] An insulator having a function of suppressing diffusion of hydrogen is preferably used as the insulator 212. This can suppress diffusion of hydrogen from below the insulator 212 to the transistor. The insulator 212 can be any of the insulators that can be used for the insulator 275.

[0144] It is preferable that one or more of the insulators 212, 214, and 282 function as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor into the transistor. Therefore, one or more of the insulators 212, 214, and 282 may contain hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0145] The insulators 212, 214, and 282 each preferably have an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, or the like can be used. For example, silicon nitride, which has a higher hydrogen barrier property, is preferably used as the insulator 212. The insulators 282 and the like may have a single-layer structure or a stacked-layer structure. As an example of a stacked-layer structure, an insulator in which aluminum oxide and silicon nitride are stacked in this order, or an insulator in which hafnium oxide and silicon nitride are stacked in this order can be used. For example, the insulators 212, 214, and 282 each preferably have aluminum oxide, magnesium oxide, or the like that have the function of capturing and fixing hydrogen. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor side through the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like disposed outside the insulator 282 to the transistor side. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 280 or the like to an area above the transistor via the insulator 282 or the like. In this way, it is preferable to have a structure in which the transistor is surrounded from above and below by insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0146] The conductor 205a is disposed so as to overlap with the metal oxide 230 and the conductor 260. Here, the conductor 205a is preferably provided by being embedded in an opening formed in the insulator 216a. In addition, a part of the conductor 205a may be embedded in the insulator 214.

[0147] The conductor 205a may have a single-layer structure or a laminated structure. For example, FIG. 2A shows an example in which the conductor 205a has a two-layer laminated structure of a first conductor and a second conductor. The first conductor of the conductor 205a is provided in contact with the bottom surface and sidewall of an opening provided in the insulator 216a. The second conductor of the conductor 205a is provided so as to be embedded in a recess formed in the first conductor of the conductor 205a. Here, the height of the top surface of the second conductor of the conductor 205a is approximately the same as the height of the top surface of the first conductor of the conductor 205a and the height of the top surface of the insulator 216a.

[0148] Here, the first conductor of the conductor 205a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N ２ O, NO, or NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc., or oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0149] By using a conductive material that has the function of reducing hydrogen diffusion for the first conductor of the conductor 205a, impurities such as hydrogen contained in the second conductor of the conductor 205a can be prevented from diffusing into the metal oxide 230 via the insulators 216a and 224. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the first conductor of the conductor 205a, it is possible to suppress oxidation of the second conductor of the conductor 205a and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The first conductor of the conductor 205a can have a single-layer structure or a multilayer structure of the above conductive materials. For example, the first conductor of the conductor 205a preferably contains titanium nitride.

[0150] The second conductor of the conductor 205a is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the second conductor of the conductor 205a preferably contains tungsten.

[0151] The conductor 205a can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor can be controlled by changing the potential applied to the conductor 205a independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205a can increase the Vth of the transistor and reduce its off-state current. Therefore, applying a negative potential to the conductor 205a can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when a negative potential is not applied.

[0152] Furthermore, the electrical resistivity of the conductor 205a is designed taking into consideration the potential applied to the conductor 205a, and the film thickness of the conductor 205a is set to match this electrical resistivity. Furthermore, the film thickness of the insulator 216a is approximately the same as the film thickness of the conductor 205a. Here, it is preferable to thin the film thicknesses of the conductor 205a and the insulator 216a within the range permitted by the design of the conductor 205a. By thinning the film thickness of the insulator 216a, the absolute amount of impurities such as hydrogen contained in the insulator 216a can be reduced, thereby reducing the diffusion of the impurities into the metal oxide 230.

[0153] The insulators 222 and 224 function as gate insulators.

[0154] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0155] The insulator 222 preferably includes an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. Alternatively, an oxide containing hafnium and zirconium, such as hafnium zirconium oxide, is preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the metal oxide 230 to the substrate and diffusion of impurities such as hydrogen from the periphery of the transistor to the metal oxide 230. Therefore, the insulator 222 can suppress diffusion of impurities such as hydrogen into the inside of the transistor and suppress generation of oxygen vacancies in the metal oxide 230. Furthermore, reaction of the first conductor of the conductor 205a with oxygen contained in the insulator 224 and the metal oxide 230 can be suppressed.

[0156] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on the insulator.

[0157] The insulator 222 may have a single-layer structure or a multi-layer structure of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. The insulator 222 may also be made of lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３ In some cases, a material with a high dielectric constant such as (BST) can be used.

[0158] The insulator 224 in contact with the metal oxide 230 preferably comprises, for example, silicon oxide or silicon oxynitride.

[0159] Each of the insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the stacked structures are not limited to those made of the same material, and may be stacked structures made of different materials.

[0160] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen as the conductor 242 and the conductor 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductor 242 and the conductor 260. When a conductive material containing metal and nitrogen is used as the conductor 242 and the conductor 260, the conductor 242 and the conductor 260 become conductors that contain at least metal and nitrogen.

[0161] The conductor 242 may have a single layer structure or a multilayer structure, and the conductor 260 may have a single layer structure or a multilayer structure.

[0162] 2A, for example, the conductor 242 is shown as having a two-layer structure consisting of a first conductor and a second conductor on the first conductor. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the first conductor of the conductor 242 that contacts the metal oxide 230b. This can prevent the conductivity of the conductor 242 from decreasing. Furthermore, it is preferable to use a material that easily absorbs (extracts) hydrogen as the first conductor of the conductor 242, because this can reduce the hydrogen concentration in the metal oxide 230.

[0163] Furthermore, it is preferable that the second conductor of the conductor 242 has higher conductivity than the first conductor of the conductor 242. For example, it is preferable that the film thickness of the second conductor of the conductor 242 is larger than the film thickness of the first conductor of the conductor 242.

[0164] For example, the first conductor of the conductor 242 may be tantalum nitride or titanium nitride, and the second conductor of the conductor 242 may be tungsten.

[0165] To prevent a decrease in the conductivity of the conductor 242, it is preferable to use a crystalline oxide such as CAAC-OS as the metal oxide 230b. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. The use of CAAC-OS can prevent the conductor 242 from extracting oxygen from the metal oxide 230b. Furthermore, a decrease in the conductivity of the conductor 242 can be prevented.

[0166] As the conductor 242, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0167] For example, hydrogen contained in the metal oxide 230b may diffuse into the conductor 242. In particular, when a nitride containing tantalum is used for the conductor 242, hydrogen contained in the metal oxide 230b may easily diffuse into the conductor 242, and the diffused hydrogen may bond with nitrogen contained in the conductor 242. In other words, hydrogen contained in the metal oxide 230b or the like may be absorbed by the conductor 242.

[0168] The conductor 260 is arranged so that its upper surface is approximately flush with the height of the top of the insulator 254 , the top of the insulator 253 , and the top surface of the insulator 280 .

[0169] The conductor 260 functions as a first gate electrode of the transistor. The conductor 260 preferably includes a first conductor and a second conductor on the first conductor. For example, the first conductor of the conductor 260 is preferably disposed so as to surround the bottom and side surfaces of the second conductor of the conductor 260.

[0170] 2A shows a two-layer structure of the conductor 260. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the first conductor of the conductor 260.

[0171] The first conductor of the conductor 260 is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, or copper atoms, or is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0172] Furthermore, since the first conductor of the conductor 260 has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the second conductor of the conductor 260 by oxygen contained in the insulator 280, for example. As the conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0173] Furthermore, it is preferable to use a conductor with high conductivity for the conductor 260. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used for the second conductor of the conductor 260. Furthermore, the second conductor of the conductor 260 may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0174] Furthermore, in the transistor, the conductor 260 is formed in a self-aligned manner so as to fill, for example, an opening formed in the insulator 280. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the pair of conductors 242 without alignment.

[0175] It is preferable that the insulators 216a, 280, 285, 287, 216b, 181, and 185 each have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced.

[0176] For example, it is preferable that insulator 216a, insulator 280, insulator 285, insulator 287, insulator 216b, insulator 181, and insulator 185 each have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0177] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0178] Furthermore, the top surfaces of the insulators 216a, 280, 285, 287, 216b, 181, and 185 may each be flattened.

[0179] The concentration of impurities such as water and hydrogen is preferably reduced in the insulator 280. For example, the insulator 280 preferably includes an oxide containing silicon such as silicon oxide or silicon oxynitride.

[0180] At the opening of the insulator 280, the sidewall of the insulator 280 may be approximately perpendicular to the upper surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, for example, the coverage of the insulator 253 provided at the opening of the insulator 280 can be improved, and defects such as voids can be reduced.

[0181] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of the structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side surface of the structure and the substrate surface do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0182] The conductor 160c and the conductor 205b included in the capacitor 101 can be formed using the same material as the conductor 205a, the conductor 242, or the conductor 260. The conductor 160c and the conductor 205b are preferably formed using a film formation method with good coverage, such as an ALD method or a CVD method.

[0183] The conductor 160 has a first conductor and a second conductor on the first conductor. For example, titanium nitride formed by ALD can be used as the first conductor of the conductor 160, and tungsten formed by CVD can be used as the second conductor of the conductor 160. Note that if the adhesion of tungsten to the insulator 282 is sufficiently high, the conductor 160 may have a single-layer structure of tungsten formed by CVD.

[0184] A high-dielectric-constant (high-k) material (a material with a high relative dielectric constant) is preferably used for the insulator 215 of the capacitor 101. The insulator 215 is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.

[0185] Examples of high-dielectric-constant (high-k) insulators include oxides, oxynitrides, oxynitrides, and nitrides containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. Silicon may also be contained in the oxides, oxynitrides, oxynitrides, or nitrides. Insulators made of the above materials may also be stacked.

[0186] Examples of insulators made of high dielectric constant (high-k) materials include aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, oxides containing silicon and zirconium, oxynitrides containing silicon and zirconium, oxides containing hafnium and zirconium, and oxynitrides containing hafnium and zirconium. By using such high-k materials, the insulator 215 can be made thick enough to suppress leakage current and the capacitance of the capacitor 101 can be sufficiently ensured.

[0187] Insulators made of the above materials are preferably stacked, and a stacked structure of a high-dielectric-constant (high-k) material and a material having a higher dielectric strength than the high-dielectric-constant (high-k) material is preferably used. For example, the insulator 215 can be an insulator stacked in the order of zirconium oxide, aluminum oxide, and zirconium oxide. Alternatively, an insulator stacked in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. Alternatively, an insulating film stacked in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By stacking insulators with relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved and electrostatic breakdown of the capacitor 101 can be suppressed. When stacking insulators, it is preferable to form each layer (also referred to as successive film formation) without exposing them to the atmosphere. For example, successive film formation can be performed using an ALD method.

[0188] The conductor 233 preferably has a layered structure of a first conductor and a second conductor. For example, as shown in FIG. 2A , the conductor 233 may have a structure in which a first conductor is provided in contact with the inner wall of the opening, and a second conductor is provided further inside. The first conductor of the conductor 233 has an area that contacts at least a portion of the top surface of the conductor 209, the side surface of the insulator 212, the side surface of the insulator 216a, the top surface and side surface of the conductor 242, the side surface of the insulator 280, and the side surface of the insulator 285.

[0189] A conductive material having a function of suppressing the permeation of impurities such as water and hydrogen is preferably used as the first conductor of the conductor 233. The first conductor of the conductor 233 can have a single-layer structure or a stacked-layer structure using, for example, one or more of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. This can suppress impurities such as water and hydrogen from being mixed into the metal oxide 230 through the conductor 233.

[0190] In addition, since the conductor 233 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used for the second conductor of the conductor 233.

[0191] For example, it is preferable to use titanium nitride as the first conductor of the conductor 233 and tungsten as the second conductor of the conductor 233. In this case, the first conductor of the conductor 233 is a conductor containing titanium and nitrogen, and the second conductor of the conductor 233 is a conductor containing tungsten.

[0192] 6 is a cross-sectional view illustrating a structural example of a semiconductor device of one embodiment of the present invention. The semiconductor device illustrated in FIG. 6 illustrates an example in which a layer including, for example, a transistor 300 is provided below the structure illustrated in FIG. 1. The transistor 300 can be provided in a driver circuit of a memory cell formed above the insulator 210, for example. Note that the structure of the layer above the insulator 210 in FIG. 6 is the same as that in FIG. 1, and therefore detailed description thereof will be omitted.

[0193] 6 illustrates a transistor 300. The transistor 300 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single-crystal silicon substrate.

[0194] Here, in the transistor 300 shown in FIG. 6 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI (silicon-on-insulator) substrate.

[0195] Note that the transistor 300 illustrated in FIG. 6 is an example, and the structure is not limited to this example. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0196] A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. A plurality of wiring layers may be provided depending on the design. In this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0197] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and the like are embedded in the insulators 320 and 322. Conductors 330 and the like are embedded in the insulators 324 and 326. The conductors 328 and 330 function as contact plugs or wirings.

[0198] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using, for example, chemical mechanical polishing (CMP) to enhance flatness.

[0199] 7 is a cross-sectional view showing an example of two memory cells arranged in the X direction, in which a memory cell including transistors 201a, 202a, and 203a as transistors 201, 202, and 203, respectively, and a memory cell including transistors 201b, 202b, and 203b as transistors 201, 202, and 203b, respectively, are shown.

[0200] 7, the connection electrode 240b can be electrically connected to the conductor 242e of the transistor 203a and the conductor 242e of the transistor 203b. Therefore, the connection electrode 240b can be shared by, for example, two memory cells adjacent in the X direction. Furthermore, the connection electrode 240a can be electrically connected to, for example, two conductors 242a adjacent in the X direction. Therefore, the connection electrode 240a can also be shared by, for example, two memory cells adjacent in the X direction.

[0201] 8A and 8B are plan views showing an example of a semiconductor device having the configuration shown in FIG. 2A etc., and show an example of the configuration in the XY plane.

[0202] 8A shows a transistor 201, a transistor 202, a transistor 203, a connection electrode 240a, and a connection electrode 240b. FIG. 8B shows a configuration in which a capacitor 101 is added to FIG. 8A. In FIG. 8B, the memory cell 10 is configured with the transistor 201, the transistor 202, the transistor 203, and the capacitor 101. Note that components other than conductors are omitted in FIGS. 8A and 8B.

[0203] 8B, the conductor 160 having a region that functions as one electrode of the capacitor 101 and the conductor 205b having a region that functions as the other electrode of the capacitor 101 are rectangular. For example, when the various conductors shown in FIG. 8B are formed in a line and space pattern, the design is such that the line / space is 20 nm / 20 nm, the margin where the two patterns overlap is 10 nm, and the connection electrodes 240a and 240b are designed to be 25 nm × 25 nm, with a margin of 5 nm added for misalignment, the area of ​​the memory cell 10 is 80 nm × 245 nm = 0.0196 μm ２ For example, the cell density of each of the memory layers 11_1 to 11_n shown in FIG. ２ This becomes:

[0204] <Example of Manufacturing Method of Semiconductor Device> An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below. Here, the case of manufacturing the semiconductor device illustrated in FIG. 1 will be described as an example.

[0205] In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed as a film by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0206] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, or carbides using reactive sputtering.

[0207] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0208] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, and elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0209] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0210] The CVD and ALD methods differ from sputtering methods in that particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0211] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0212] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0213] First, a substrate (not shown) is prepared, and then a conductor 209a, a conductor 209b, and an insulator 210 are formed on the substrate. Next, an insulator 212 is formed on the conductor 209a, the conductor 209b, and the insulator 210, and an insulator 214 is formed on the insulator 212 ( FIG. 9A ).

[0214] The insulators 212 and 214 are preferably formed by an ALD method. Note that the insulators 212 and 214 may also be formed by a sputtering method, a CVD method, an MBE method, or a PLD method.

[0215] In this embodiment, a silicon nitride film is formed by a PEALD method as the insulator 212. A hafnium oxide film is formed by an ALD method as the insulator 214.

[0216] By using, as the insulators 212 and 214, insulators that are impermeable to impurities such as water and hydrogen, such as silicon nitride and hafnium oxide, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below the insulator 212. Furthermore, by using, as the insulators 212 and 214, insulators that are impermeable to copper, such as silicon nitride and hafnium oxide, it is possible to suppress the upward diffusion of metals such as copper, even if such metals as copper are easily diffused in conductors below the insulator 212, such as the conductors 209a and 209b.

[0217] Subsequently, an insulator 216a is formed on the insulator 214 (FIG. 9B).

[0218] In this embodiment, a silicon oxide film is formed as the insulator 216a by pulsed DC sputtering using a silicon target in an atmosphere containing oxygen gas. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0219] Next, an opening 207a reaching the insulator 214 is formed in the insulator 216a (FIG. 9C). The opening 207a may be formed by wet etching, but dry etching is preferable for fine processing. Note that the formation of the opening 207a may result in the removal of a portion of the insulator 214. This may result in the formation of a recess in the insulator 214 in the area overlapping the opening 207a.

[0220] In this specification and the like, the term "opening" also includes grooves, slits, etc. Furthermore, a region in which an opening is formed may be referred to as an opening portion.

[0221] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

[0222] Next, a conductive film to be the conductor 205a1 is formed. The conductive film preferably has a stacked structure of a conductive film having a function of suppressing oxygen permeation and a conductive film having a lower electrical resistivity than the conductive film. The conductive film having a function of suppressing oxygen permeation preferably includes one or more of tantalum nitride, tungsten nitride, and titanium nitride. Alternatively, the conductive film may have a stacked structure of a conductive film having a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. Furthermore, the conductive film having a low electrical resistivity preferably includes one or more of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy. These conductive films can be formed by, for example, a sputtering method, a plating method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0223] In this embodiment, a titanium nitride film is formed as a lower layer and a tungsten film is formed as an upper layer of the conductive film that becomes the conductor 205a1. By using a metal nitride as the lower layer of the conductor 205a1, it is possible to prevent the conductor 205a1 from being oxidized by the insulator 216a, for example. Furthermore, even if a metal that easily diffuses is used as the upper layer of the conductor 205a1, it is possible to prevent the metal from diffusing out of the conductor 205a1.

[0224] Next, a CMP process is performed to remove a portion of the conductive film that will become the conductor 205a1, thereby exposing the insulator 216a. As a result, the conductor 205a1 is formed so as to fill the opening of the insulator 216a (FIG. 9D). Note that the CMP process may remove a portion of the insulator 216a. This allows the insulator 216a to be planarized.

[0225] Next, an insulator 222 is formed on the insulator 216a and the conductor 205a1 (FIG. 9E).

[0226] The insulator 222 may be formed as an insulator containing one or both of an oxide of aluminum and hafnium. As the insulator containing one or both of an oxide of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. Alternatively, the insulator 222 may have a stacked structure of an insulating film containing one or both of an oxide of aluminum and hafnium and silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide.

[0227] The insulator 222 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, hafnium oxide is formed as the insulator 222 by an ALD method. Alternatively, the insulator 222 may have a stacked structure of silicon nitride formed by a PEALD method and hafnium oxide formed by an ALD method.

[0228] Subsequently, heat treatment is preferably performed. The temperature of the heat treatment is preferably 250°C or higher and 650°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0229] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, for example, moisture can be prevented from being absorbed into the insulator 222 as much as possible.

[0230] In this embodiment, after the insulator 222 is formed, heat treatment is performed at a temperature of 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4:1. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment may crystallize part of the insulator 222. The heat treatment can also be performed, for example, after the insulating film 224f is formed.

[0231] Next, an insulating film 224f is formed on the insulator 222 (FIG. 9E).

[0232] The insulating film 224f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon oxide is formed as the insulating film 224f by a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulating film 224f can be reduced. Because the insulating film 224f will come into contact with a metal oxide in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0233] Next, a metal oxide film 230af is formed on the insulating film 224f, and a metal oxide film 230bf is formed on the metal oxide film 230af (FIG. 9E). It is preferable to form the metal oxide films 230af and 230bf consecutively without exposing them to the air. By forming the films without exposing them to the air, it is possible to prevent impurities or moisture from the air from adhering to the metal oxide films 230af and 230bf, and to keep the vicinity of the interface between the metal oxide films 230af and 230bf clean.

[0234] The metal oxide film 230af and the metal oxide film 230bf can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, the metal oxide film 230af and the metal oxide film 230bf are formed by a sputtering method.

[0235] For example, when the metal oxide film 230af and the metal oxide film 230bf are formed by sputtering, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the metal oxide film 230af and the metal oxide film 230bf are formed by sputtering, for example, an In-M-Zn oxide target can be used.

[0236] In particular, during the formation of the metal oxide film 230af, part of the oxygen contained in the sputtering gas may be supplied to the insulating film 224f. Therefore, the proportion of oxygen contained in the sputtering gas is preferably 70% or more, more preferably 80% or more, and even more preferably 100%.

[0237] When the metal oxide film 230bf is formed by a sputtering method, an oxygen-excess oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the metal oxide film 230bf is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.

[0238] In this embodiment, the metal oxide film 230af is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4. The metal oxide film 230bf is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1, an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1, an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2, or an oxide target with an atomic ratio of In:Ga:Zn = 1:1:2. The oxide films can be formed according to the desired characteristics of the metal oxides 230a and 230b by appropriately selecting the film formation conditions and atomic ratios.

[0239] Note that the insulating film 224f, the metal oxide film 230af, and the metal oxide film 230bf are preferably formed by sputtering without exposure to the atmosphere. For example, a multi-chamber film formation apparatus is preferably used. This can reduce the incorporation of hydrogen into the insulating film 224f, the metal oxide film 230af, and the metal oxide film 230bf between film formation steps.

[0240] The metal oxide films 230af and 230bf may be formed by ALD. By using the ALD method to form the metal oxide films 230af and 230bf, films with a uniform thickness can be formed even in trenches or openings with a large aspect ratio. Furthermore, by using the PEALD method, the metal oxide films 230af and 230bf can be formed at a lower temperature than by thermal ALD.

[0241] Next, heat treatment is preferably performed within a temperature range in which the metal oxide film 230af and the metal oxide film 230bf are not polycrystallized. The heat treatment temperature is preferably 250° C. to 650° C., more preferably 400° C. to 600° C.

[0242] Note that the atmosphere for the heat treatment may be the same as the atmosphere that can be applied to the heat treatment performed after the formation of the insulator 222.

[0243] It is preferable that the gas used in the heat treatment be highly purified, similar to the heat treatment performed after the formation of the insulator 222. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented as much as possible from being absorbed into the metal oxide film 230af, the metal oxide film 230bf, and the like.

[0244] In this embodiment, the heat treatment is performed at 400° C. for 1 hour with a nitrogen gas / oxygen gas flow ratio of 4:1. This heat treatment using oxygen gas can reduce impurities such as carbon, water, and hydrogen in the metal oxide film 230af and the metal oxide film 230bf. Reducing the impurities in the film in this manner improves the crystallinity of the metal oxide film 230bf, resulting in a denser, more compact structure. This increases the crystalline regions in the metal oxide film 230af and the metal oxide film 230bf, reducing the in-plane variation of the crystalline regions in the metal oxide film 230af and the metal oxide film 230bf. This reduces the in-plane variation of the electrical characteristics of the transistor.

[0245] Furthermore, by performing the heat treatment, hydrogen in the insulator 216a, the insulating film 224f, the metal oxide film 230af, and the metal oxide film 230bf moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the insulator 216a, the insulating film 224f, the metal oxide film 230af, and the metal oxide film 230bf diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216a, the insulating film 224f, the metal oxide film 230af, and the metal oxide film 230bf decrease.

[0246] In particular, the insulating film 224f (later the insulator 224) functions as a gate insulator of the transistor 201, the transistor 202, and the transistor 203, and the metal oxide film 230af and the metal oxide film 230bf (later the metal oxide 230a and the metal oxide 230b) function as channel formation regions of the transistor 201, the transistor 202, and the transistor 203. The transistor 201, the transistor 202, and the transistor 203 formed using the insulating film 224f, the metal oxide film 230af, and the metal oxide film 230bf in which the hydrogen concentrations are reduced are preferable because they have good reliability.

[0247] Next, the insulating film 224f, the metal oxide film 230af, and the metal oxide film 230bf are processed into island shapes by, for example, lithography and etching to form the insulator 224, the metal oxide 230a, and the metal oxide 230b ( FIG. 10A ). The insulator 224, the metal oxide 230a, and the metal oxide 230b are formed so that at least a portion of each overlaps with the conductor 205a1. As described above, the metal oxide 230a of the transistor 202 and the metal oxide 230a of the transistor 203 are a common layer, and the metal oxide 230b of the transistor 202 and the metal oxide 230b of the transistor 203 are a common layer.

[0248] 10A , the side surfaces of the insulator 224, the metal oxide 230a, and the metal oxide 230b may be tapered. The taper angle of the side surfaces of the insulator 224, the metal oxide 230a, and the metal oxide 230b may be, for example, 60° or more and less than 90°. By tapering the side surfaces in this manner, the coverage of the insulator 275, for example, can be improved in subsequent processes, and defects such as voids can be reduced.

[0249] However, the present invention is not limited to the above, and the side surfaces of the insulator 224, the metal oxide 230a, and the metal oxide 230b may be substantially perpendicular to the top surface of the insulator 222. With such a structure, it is possible to reduce the area and increase the density when providing multiple transistors.

[0250] The above processing can be performed using a dry etching method or a wet etching method. Processing using a dry etching method is suitable for fine processing. Furthermore, the insulating film 224f, the metal oxide film 230af, and the metal oxide film 230bf may be processed under different conditions.

[0251] In lithography, a resist is first exposed through a mask. Next, the exposed region is removed or left using a developer to form a resist mask. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, a liquid immersion technique can be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching. After forming a resist mask using lithography, a conductive film, a semiconductor film, an insulating film, or the like can be processed into a desired shape by etching through the resist mask. Thus, lithography and etching can be used to form a conductor, a semiconductor, an insulator, or the like. An electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required.

[0252] Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as the hard mask material is formed on the metal oxide film 230bf, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of the desired shape. For example, etching of the metal oxide film 230bf may be performed after removing the resist mask, or may be performed while leaving the resist mask in place. In the latter case, the resist mask may be lost during etching. For example, after etching the metal oxide film 230bf, the hard mask may be removed by etching. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0253] Next, a conductive film is formed over the metal oxide 230b and the insulator 222. The conductive film can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Note that heat treatment may be performed before the formation of the conductive film. The heat treatment may be performed under reduced pressure, and the conductive film may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the metal oxide 230b can be removed and the moisture and hydrogen concentrations in the metal oxide 230a and the metal oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 200° C.

[0254] Next, the conductive film is processed by lithography and etching to form conductive layers 242A and 242B that cover the top surface and side surfaces of the metal oxide 230b, the side surfaces of the metal oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222 ( FIG. 10B ). Here, the conductive layer 242A is formed so as to cover the top surface and side surfaces of the metal oxide 230b, the side surfaces of the metal oxide 230a, and the side surfaces of the insulator 224, which will later become part of the transistor 201. The conductive layer 242B is formed so as to cover the top surface and side surfaces of the metal oxide 230b, the side surfaces of the metal oxide 230a, and the side surfaces of the insulator 224, which will later become part of the transistors 202 and 203.

[0255] In this embodiment, the conductive films to be the conductive layers 242A and 242B have a stacked structure of tantalum nitride and tungsten, which are formed by a sputtering method. Here, the film containing tungsten and the film containing tantalum nitride may be processed under the same conditions or different conditions.

[0256] Next, an insulator 275 is formed on the conductive layer 242A, the conductive layer 242B, and the insulator 222, and an insulator 280 is formed on the insulator 275 ( FIG. 10C ). The insulator 280 is preferably formed by forming an insulating film that will become the insulator 280 and then performing CMP on the insulating film to form an insulator with a flat upper surface. Alternatively, a silicon nitride film may be formed on the insulator 280 by, for example, sputtering, and then CMP may be performed on the silicon nitride film until it reaches the insulator 280.

[0257] The insulators 275 and 280 can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0258] It is preferable to use an insulator having a function of suppressing oxygen permeation for the insulator 275. For example, it is preferable to form a silicon nitride film for the insulator 275 by an ALD method, specifically, a PEALD method. Alternatively, it is preferable to form an aluminum oxide film for the insulator 275 by a sputtering method and then form a silicon nitride film thereon by a PEALD method. By forming the insulator 275 with such a layered structure, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0259] In this way, the insulator 224, the metal oxide 230a, the metal oxide 230b, the conductive layer 242A, and the conductive layer 242B can be covered with the insulator 275, which has a function of suppressing oxygen diffusion. This makes it possible to reduce the direct diffusion of oxygen from the insulator 280 and the like to the insulator 224, the metal oxide 230a, the metal oxide 230b, the conductive layer 242A, and the conductive layer 242B in a later process.

[0260] The insulator 280 is preferably silicon oxide formed by, for example, a sputtering method. The insulator 280 containing excess oxygen can be formed by depositing the insulator 280 by a sputtering method in an atmosphere containing oxygen. The hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. The hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. ２０ atoms / cm３ Preferably, it is lower than 1×10 １９ atoms / cm ３ It is more preferable that the value is lower than 1×10 １８ atoms / cm ３ It is more preferable that the temperature is lower than 1000°C. Note that heat treatment may be performed before the formation of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 can be removed, and the moisture and hydrogen concentrations in the metal oxide 230a, the metal oxide 230b, and the insulator 224 can be reduced. The heat treatment conditions described above can be used for the heat treatment.

[0261] Then, the conductive layer 242A, the insulator 275, and the insulator 280 are processed using lithography and etching to form an opening 258a that reaches the metal oxide 230b. The conductive layer 242B, the insulator 275, and the insulator 280 are also processed to form openings 258b and 258c that reach the metal oxide 230b. By forming the opening 258a, the conductors 242a and 242b are formed. By forming the openings 258b and 258c, the conductors 242c, 242d, and 242e are formed ( FIG. 11A ). The openings 258a, 258b, and 258c have regions that overlap with the conductive layer 205a1. Note that the processing of the conductive layer 242A and the conductive layer 242B, the processing of the insulator 275, and the processing of the insulator 280 may be performed under different conditions. Alternatively, the insulators 275 and 280 may be processed under the same conditions, and the conductive layers 242A and 242B may be processed under different conditions.

[0262] The etching process may result in impurities adhering to or diffusing into the side surfaces of the metal oxide 230a, the top surface and side surfaces of the metal oxide 230b, the side surfaces of the conductors 242a to 242e, the side surfaces of the insulator 275, and the side surfaces of the insulator 280. A process for removing such impurities may be performed. Furthermore, particularly when dry etching is used to form the openings 258a, 258b, and 258c, damaged regions may be formed on the surface of the metal oxide 230b. Such damaged regions may be removed. Examples of such impurities include those derived from components contained in the insulators 280, 275, and the conductors 242a to 242e, components contained in the components of the apparatus used to form the openings 258a to 258c, and components contained in the gas or liquid used in etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0263] In particular, impurities such as aluminum and silicon may reduce the crystallinity of the metal oxide 230b. Therefore, it is preferable to remove impurities such as aluminum and silicon from the surface of the metal oxide 230b and its vicinity. It is also preferable to reduce the concentration of these impurities. For example, the concentration of aluminum atoms on the surface of the metal oxide 230b and its vicinity is preferably 5.0 atomic % or less, more preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0264] In addition, in the region where the crystallinity of the metal oxide 230b is low due to impurities such as aluminum and silicon, the density of the crystal structure is reduced. Ｏ A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the region of low crystallinity in the metal oxide 230b be reduced or removed.

[0265] In contrast, the metal oxide 230b preferably has a layered CAAC structure. In particular, it is preferable that the metal oxide 230b has the CAAC structure up to the bottom end of the drain. Here, in the transistors 201 to 203, the conductors 242a to 242e and at least a part thereof function as the drain. Therefore, it is preferable that the metal oxide 230b near the bottom ends of the conductors 242a to 242e have the CAAC structure. Thus, even at the drain end, which significantly affects the drain breakdown voltage, the low-crystalline region of the metal oxide 230b is removed. By having the CAAC structure, fluctuations in the electrical characteristics of the transistors 201 to 203 can be further suppressed. Furthermore, the reliability of the transistors 201 to 203 can be improved.

[0266] For example, a cleaning process is performed to remove impurities that have adhered to the surface of the metal oxide 230b during the etching process. Examples of cleaning methods include wet cleaning using a cleaning solution (also known as wet etching), plasma processing using plasma, and cleaning by heat treatment. These cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0267] Wet cleaning may be performed using an aqueous solution of one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid diluted with carbonated water or pure water, pure water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0268] In this specification, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration and temperature of the aqueous solution are adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0269] For ultrasonic cleaning, a frequency of 200 kHz or higher is preferably used, and a frequency of 900 kHz or higher is more preferably used. By using such a frequency, damage to the metal oxide 230b can be reduced, for example.

[0270] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0271] In this embodiment, the cleaning treatment is performed by wet cleaning using diluted ammonia water. By performing this cleaning treatment, impurities attached to the surfaces of the metal oxide 230a, the metal oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of the metal oxide 230b can be improved.

[0272] Heat treatment may be performed after the etching or cleaning. The temperature of the heat treatment is preferably 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the metal oxide 230a and the metal oxide 230b, thereby reducing oxygen vacancies. Furthermore, such heat treatment can improve the crystallinity of the metal oxide 230b. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, a subsequent heat treatment in a nitrogen atmosphere may be performed without exposure to the air.

[0273] Next, an insulating film that becomes the insulator 253 is formed so as to fill the openings 258a, 258b, and 258c. The insulating film can be formed using, for example, ALD, sputtering, CVD, MBE, or PLD, but is preferably formed using ALD. The insulator 253 is preferably formed to a thin film thickness, and it is preferable to minimize film thickness variation. The ALD method is a film formation method that alternately introduces a precursor and a reactant (e.g., an oxidizer). The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Furthermore, as shown in FIG. 11B, the insulator 253 is preferably formed with good coverage on the bottom and side surfaces of the openings 258a, 258b, and 258c. By using the ALD method, atomic layers can be deposited one by one on the bottom and side surfaces of the openings 258 a, 258 b, and 258 c, so that the insulator 253 can be formed with good coverage over the openings 258 a, 258 b, and 258 c.

[0274] When the insulating film that becomes the insulator 253 is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), or water (H ２ O) and the like can be used. ３ ), or oxygen (O ２) as an oxidizing agent, hydrogen diffusing into the metal oxide 230b can be reduced.

[0275] In this embodiment, hafnium oxide is deposited by a thermal ALD method as the insulating film to be the insulator 253. Alternatively, aluminum oxide and hafnium oxide can be deposited in this order as the insulating film to be the insulator 253.

[0276] Next, it is preferable to perform microwave treatment in an oxygen-containing atmosphere. Here, microwave treatment refers to treatment using, for example, a device having a power source that generates high-density plasma using microwaves. In addition, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0277] In the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. The use of high-density plasma can generate high-density oxygen radicals. Furthermore, the power of the power supply that applies microwaves to the microwave treatment device is preferably 1000 W to 10,000 W, and preferably 2000 W to 5,000 W. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently introduced into the metal oxide 230b.

[0278] The microwave treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or higher and 1000 Pa or lower, and more preferably being 300 Pa or higher and 700 Pa or lower. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C or higher and 750°C or lower, and more preferably 300°C or higher and 500°C or lower.

[0279] Furthermore, for example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%. ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ +Ar)) is set to 10% or more and 30% or less. By performing microwave treatment in an atmosphere containing oxygen in this way, the carrier concentration in the metal oxide 230b can be reduced. Furthermore, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, an excessive reduction in the carrier concentration in the metal oxide 230b can be prevented.

[0280] By performing microwave treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region of the metal oxide 230b between the conductors 242a and 242b, the region between the conductors 242c and 242d, and the region between the conductors 242d and 242e. The action of the plasma, microwaves, etc., can reduce V in these regions. Ｏ This breaks down H and removes hydrogen from the region. Ｏ Therefore, oxygen vacancies in the channel formation region and V Ｏ By supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be lowered.

[0281] On the other hand, the metal oxide 230b has a region overlapping with any of the conductors 242a to 242e. This region can function as a source region or a drain region. Here, the conductors 242a to 242e preferably function as a shielding film against the action of microwaves, high frequency waves such as RF, or oxygen plasma when performing microwave treatment in an oxygen-containing atmosphere. Therefore, the conductors 242a to 242e preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0282] The conductors 242a to 242e shield the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc., so that these effects do not reach the regions of the metal oxide 230b that overlap with any of the conductors 242a to 242e. As a result, V Ｏ Since the amount of H is reduced and an excessive amount of oxygen is not supplied, a decrease in the carrier concentration can be prevented.

[0283] Furthermore, an insulator 253 having a barrier property against oxygen is provided in contact with the side surfaces of the conductors 242a to 242e, which can prevent an oxide film from being formed on the side surfaces of the conductors 242a to 242e by microwave treatment.

[0284] Furthermore, the film quality of the insulator 253 can be improved, thereby improving the reliability of the transistor.

[0285] In this way, oxygen vacancies and V are selectively formed in the channel formation region of the metal oxide. Ｏ By removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions that function as source and drain regions can be suppressed, thereby maintaining conductivity. This suppresses fluctuations in the electrical characteristics of the transistor, and suppresses variations in the electrical characteristics of the transistor within the substrate surface.

[0286] In microwave treatment, thermal energy may be transferred directly to the metal oxide 230b due to electromagnetic interaction between the microwaves and molecules in the metal oxide 230b. This thermal energy may heat the metal oxide 230b. This type of heat treatment is sometimes called microwave annealing. Performing microwave treatment in an oxygen-containing atmosphere may produce an effect equivalent to that of oxygen annealing. Furthermore, if the metal oxide 230b contains hydrogen, it is thought that this thermal energy is transferred to the hydrogen in the metal oxide 230b, thereby activating and releasing the hydrogen from the metal oxide 230b.

[0287] Note that the microwave treatment may be performed before the formation of the insulating film that becomes the insulator 253, rather than after the formation of the insulating film.

[0288] Furthermore, after the microwave treatment after the formation of the insulating film to be the insulator 253, heat treatment may be performed while the reduced pressure state is maintained. By performing such treatment, hydrogen can be efficiently removed from the insulating film, the metal oxide 230b, and the metal oxide 230a. Some of the hydrogen may be gettered to the conductor 242 (the conductors 242a to 242e). Alternatively, the step of performing heat treatment while the reduced pressure state is maintained after the microwave treatment may be repeated multiple times. Repeated heat treatment can more efficiently remove hydrogen from the insulating film, the metal oxide 230b, and the metal oxide 230a. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. The microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the metal oxide 230b is sufficiently heated by microwave annealing, for example, the heat treatment is not necessary.

[0289] Furthermore, the diffusion of hydrogen, water, impurities, and the like can be suppressed by performing microwave treatment to modify the film quality of the insulating film that becomes the insulator 253. Therefore, a post-process such as film formation of a conductive film that becomes the conductor 260 or a post-treatment such as heat treatment can suppress the diffusion of hydrogen, water, impurities, and the like into the metal oxide 230b and the metal oxide 230a through the insulator 253.

[0290] Next, an insulating film to be the insulator 254 is formed on the insulating film to be the insulator 253. The insulating film can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Like the insulating film to be the insulator 253, the insulating film is preferably formed by an ALD method. By using the ALD method, the insulating film to be the insulator 254 can be formed to a thin film thickness with good coverage. In this embodiment, silicon nitride is formed as the insulating film by a PEALD method.

[0291] Subsequently, a conductive film to be the conductor 260 is deposited over the insulating film to be the insulator 254. The conductive film may be a single layer or a stacked structure of two or more layers. The conductive film to be the conductor 260 can be deposited by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, the conductive film to be the conductor 260 has a stacked structure of titanium nitride deposited by an ALD method and tungsten deposited by a CVD method.

[0292] Next, the insulating film to be the insulator 253, the insulating film to be the insulator 254, and the conductive film to be the conductor 260 are polished by CMP treatment until the insulator 280 is exposed. That is, the portions of the insulating film to be the insulator 253, the insulating film to be the insulator 254, and the conductive film to be the conductor 260 exposed from the openings 258a, 258b, and 258c are removed. As a result, the insulator 253, the insulator 254, and the conductor 260 are formed inside the openings 258a, 258b, and 258c ( FIG. 11B ).

[0293] As a result, the insulator 253 is provided in contact with the bottom and side surfaces of the openings 258a, 258b, and 258c. The conductor 260 is formed to fill the openings 258a, 258b, and 258c with the insulators 253 and 254 interposed therebetween. As a result, the transistors 201, 202, and 203 are formed. As described above, the transistors 201, 202, and 203 can be manufactured in parallel using the same process.

[0294] Subsequently, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulator 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0295] Next, the insulator 282 is deposited over the insulator 253, the insulator 254, the conductor 260, and the insulator 280 ( FIG. 12A ). The insulator 282 can be deposited by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably deposited by a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0296] In this embodiment, an aluminum oxide film is formed as the insulator 282 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. In addition, the RF power applied to the substrate is 1.86 W / cm. ２ Preferably, 0 W / cm ２ 0.62W / cm or more ２ By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed. Alternatively, the insulator 282 may be formed in a two-layer laminate structure. In this case, for example, the lower layer of the insulator 282 may be formed by applying an RF power of 0 W / cm to the substrate. ２ The upper layer of the insulator 282 was formed as follows: the RF power applied to the substrate was 0.62 W / cm ２ The film is formed as follows.

[0297] Furthermore, by depositing the insulator 282 in an oxygen-containing atmosphere by using a sputtering method, oxygen can be added to the insulator 280 during deposition. This allows the insulator 280 to contain excess oxygen. In this case, it is preferable to deposit the insulator 282 while heating the substrate.

[0298] Subsequently, an insulator 285 is formed on the insulator 282 (FIG. 12B).

[0299] In this embodiment, as the insulator 285, a silicon oxide film is formed by pulse DC sputtering using a silicon target in an atmosphere containing oxygen gas.

[0300] Next, an opening reaching the conductor 242b is formed in the insulators 285, 282, 280, and 275. An opening reaching the conductor 260 of the transistor 202 is formed in the insulators 285 and 282. An opening reaching the conductor 209a is formed in the insulators 285, 282, 280, 275, 222, 216a, 214, and 212. An opening reaching the conductor 209b is formed in the insulators 285, 282, 280, 275, 222, 216a, 214, and 212 ( FIG. 13A ). These openings may be formed by wet etching, but dry etching is preferable for fine processing.

[0301] Next, conductive films that become the conductors 231, 232, 233a1, and 233b1 are formed. The conductive films preferably have a stacked structure of a conductive film that has a function of suppressing oxygen permeation and a conductive film that has lower electrical resistivity than the conductive film. For example, the same material that can be used for the conductor 205a1 can be used for the conductive films that become the conductors 231, 232, 233a1, and 233b1.

[0302] Subsequently, CMP treatment is performed to remove portions of the conductive film that will become the conductors 231, 232, 233a1, and 233b1, thereby exposing the insulator 285. As a result, the conductor 231 is formed to fill the opening that reaches the conductor 242b. The conductor 232 is formed to fill the opening that reaches the conductor 260 of the transistor 202. The conductor 233a1 is formed to fill the opening that reaches the conductor 209a. The conductor 233b1 is formed to fill the opening that reaches the conductor 209b ( FIG. 13B ). Note that the CMP treatment may remove a portion of the insulator 285. This allows the insulator 285 to be planarized. In this way, the heights of the top surfaces of the conductors 231, 232, 233a1, and 233b1 are the same or approximately the same.

[0303] Next, an insulator 287 is deposited over the insulator 285. The insulator 287 can be deposited using a method similar to that used to deposit the insulator 216a or the insulator 280. The insulator 287 can be formed using a material similar to that used to deposit the insulator 216a or the insulator 280.

[0304] Next, the insulator 287 is processed using lithography and etching to form openings that reach the conductors 231, 232, 233a1, and 233b1. One of the openings is preferably formed larger than the top surfaces of the conductors 231 and 232. One of the openings is also preferably formed larger than the top surface of the conductor 233a1. One of the openings is also preferably formed larger than the top surface of the conductor 233b1.

[0305] Next, conductive films to become the conductors 160a, 160b, and 160c are formed so as to fill the openings. The conductive films can be formed by the same method as that used to form the films to become the conductors 242a to 242e. The conductive films can be formed using the same materials as those used to form the films to become the conductors 242a to 242e.

[0306] Subsequently, CMP treatment is performed to remove portions of the conductive film that will become the conductors 160a, 160b, and 160c, thereby exposing the insulator 287. As a result, the conductors 160a, 160b, and 160c are formed so as to fill the openings (FIG. 14A). Note that the CMP treatment may remove a portion of the insulator 287. This allows the insulator 287 to be planarized.

[0307] Here, if the etching selectivity between insulator 287 and insulator 285 is low, insulator 285 may not function as an etching stop film when forming the above-mentioned opening in insulator 287, and an opening may be formed in insulator 285 as well.

[0308] The conductor 160c is formed to be electrically connected to the conductor 231 and the conductor 232, and is formed to have, for example, a region in contact with the conductor 231 and the conductor 232. As described above, the conductor 160c is electrically connected to the conductor 242b through the conductor 231 and is electrically connected to the conductor 260 of the transistor 202 through the conductor 232.

[0309] Next, an insulator 215 is formed over the conductor 160a, the conductor 160b, the conductor 160c, and the insulator 287 ( FIG. 14B ). The insulator 215 functions as a dielectric of the capacitor 101. The insulator 215 also has a function of preventing oxidation of the conductor 160a, the conductor 160b, and the conductor 160c.

[0310] The insulator 215 is preferably formed using a film formation method with good coverage. Furthermore, it is preferable to use a high-k material as the insulator 215, and it is more preferable to use a stacked structure of a high-k material and a material having a higher dielectric strength than the high-k material. In this embodiment, zirconium oxide, aluminum oxide, and zirconium oxide are sequentially deposited as the insulator 215 by the ALD method. Alternatively, zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide may be sequentially deposited as the insulator 215 by the ALD method.

[0311] Next, the insulator 216b is formed ( FIG. 15A ). The insulator 216b can be formed by a method similar to that used to form the insulator 287, the insulator 285, the insulator 280, the insulator 216a, or the insulator 212. Furthermore, the insulator 216b can be formed using the same materials as those used to form the insulator 287, the insulator 285, the insulator 280, the insulator 216a, or the insulator 212. Next, an opening 207b reaching the insulator 215 is formed in the insulator 216b ( FIG. 15B ). The opening 207b may be formed using wet etching, but dry etching is preferable for microfabrication. Note that the formation of the opening 207b may remove a portion of the insulator 215. This may result in the formation of a recess in the insulator 215 in the area overlapping the opening 207b.

[0312] Next, conductor 205a2 and conductor 205b are formed inside opening 207b (FIG. 16). Conductor 205a2 and conductor 205b can be formed using a method similar to that used to form conductor 205a1. Furthermore, conductor 205a2 and conductor 205b can be formed using the same materials as those used to form conductor 205a1. Here, conductor 205b is formed so as to have a region that overlaps with conductor 160c. As described above, capacitor 101 is formed, which includes conductor 160c, insulator 215, and conductor 205b.

[0313] In this manner, the memory layer 11_1 can be formed. After that, the manufacturing process of the transistor 201, the transistor 202, the transistor 203, and the capacitor 101 is repeated n-1 times to form the memory layers 11_2 to 11_n (FIG. 17). Note that the conductor 205a is not formed on the insulator 215 of the memory layer 11_n because the transistor that constitutes the memory layer 11 is not formed thereon.

[0314] 17, the memory layers 11_1 to 11_n have a connection electrode 240a and a connection electrode 240b. The connection electrode 240a has conductors 233a1 to 233an (not shown), which are electrically connected to each other. The connection electrode 240b has conductors 233b1 to 233bn (not shown), which are electrically connected to each other.

[0315] Next, the insulator 181 is formed over the conductor 205b and the insulator 216b of the memory layer 11_n. The insulator 181 can be formed by a method similar to that which can be used to form the insulator 216b, the insulator 287, the insulator 285, the insulator 280, the insulator 216a, or the insulator 212. Furthermore, the insulator 181 can be formed using a material similar to that which can be used to form the insulator 216b, the insulator 287, the insulator 285, the insulator 280, the insulator 216a, or the insulator 212.

[0316] Next, an insulator 183 is formed over the insulator 181, and an insulator 185 is formed over the insulator 183. The insulators 183 and 185 can be formed by an ALD method, a sputtering method, a CVD method, an MBE method, or a PLD method. In this manner, the semiconductor device shown in FIG. 1 can be manufactured.

[0317] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0318] Embodiment 2 In this embodiment, a memory device of one embodiment of the present invention will be described with reference to drawings.

[0319] 18A and 18B are schematic perspective and block diagrams of a storage device according to one embodiment of the present invention.

[0320] 18A and 18B includes a drive circuit layer 50 and n memory layers 11. Each memory layer 11 includes a memory cell array 15. The memory cell array 15 includes a plurality of memory cells 10.

[0321] The n-layer memory layer 11 is provided on the drive circuit layer 50. By providing the n-layer memory layer 11 on the drive circuit layer 50, the area occupied by the memory device 100 can be reduced. In addition, the memory capacity per unit area can be increased.

[0322] In this embodiment, the first memory layer 11 is referred to as memory layer 11_1, the second memory layer 11 is referred to as memory layer 11_2, and the third memory layer 11 is referred to as memory layer 11_3. Furthermore, the kth memory layer 11 (k is an integer of 1 to n) is referred to as memory layer 11_k, and the nth memory layer 11 is referred to as memory layer 11_n. Note that in this embodiment and the like, when describing matters relating to all n memory layers 11 or when indicating matters common to each of the n memory layers 11, the term "memory layer 11" may be used.

[0323] <Configuration Example of Drive Circuit Layer 50> The drive circuit layer 50 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0324] In the storage device 100, the circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside.

[0325] The signal CLK is a clock signal. The signals BW, CE, and GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are power gating control signals. The signals PON1 and PON2 may be generated by the control circuit 32.

[0326] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 100. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 100. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0327] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0328] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0329] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting a wiring WWL (write word line) or a wiring RWL (read word line) specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 10, the function of reading data from the memory cell 10, and the function of retaining the read data. The column driver 45 has the function of selecting a wiring WBL (write bit line) or a wiring RBL (read bit line) specified by the column decoder 44.

[0330] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device 100. The data output from the output circuit 48 is a signal RDA.

[0331] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply voltage of the memory device 100 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of PSW22 is controlled by signal PON1, and the on / off of PSW23 is controlled by signal PON2. In FIG. 18B, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0332] <Configuration Example of Memory Layer 11> A configuration example of n memory layers 11 will be described. Each of the n memory layers 11 has a memory cell array 15. Furthermore, the memory cell array 15 has a plurality of memory cells 10. Figures 18A and 18B show an example in which the memory cell array 15 has a plurality of memory cells 10 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more).

[0333] The rows and columns extend in directions perpendicular to each other. In this embodiment, the X direction is referred to as the "rows" and the Y direction is referred to as the "columns," but the X direction may also be referred to as the "columns" and the Y direction may also be referred to as the "rows."

[0334] 18B, the memory cell 10 located in the first row and first column is indicated as memory cell 10[1,1], the memory cell 10 located in the pth row and qth column is indicated as memory cell 10[p,q], and the memory cell 10 located in the ith row and jth column (i is an integer from 1 to p, and j is an integer from 1 to q) is indicated as memory cell 10[i,j].

[0335] 19A and 19B show examples of the circuit configuration of a memory cell 10. For an example of a cross-sectional configuration of a memory cell 10 corresponding to the circuit configuration, reference can be made to Embodiment 1.

[0336] The memory cell 10 includes a transistor M1, a transistor M2, a transistor M3, and a capacitor C. A memory cell including three transistors and one capacitor is also called a 3Tr1C memory cell. Therefore, the memory cell 10 described in this embodiment is a 3Tr1C memory cell.

[0337] The transistor M1 corresponds to the transistor 201 or 201b described in Embodiment 1. The transistor M2 corresponds to the transistor 202 or 202b described in Embodiment 1. The transistor M3 corresponds to the transistor 203 or 203b described in Embodiment 1. The capacitor C corresponds to the capacitor 101 described in Embodiment 1. The wiring WBL corresponds to the connection electrode 240a described in Embodiment 1. The wiring RBL corresponds to the connection electrode 240b described in Embodiment 1.

[0338] In the memory cell 10[i,j], the gate of the transistor M1 is electrically connected to the wiring WWL[j], and one of the source and drain is electrically connected to the wiring WBL[i,s]. Note that FIG. 19A shows a configuration example in which a part of the wiring WWL[j] functions as the gate of the transistor M1. One electrode of the capacitor C is electrically connected to the wiring PL[i,s], and the other electrode is electrically connected to the other of the source and drain of the transistor M1. Note that, for example, FIG. 19A shows a configuration example in which a part of the wiring PL[i,s] functions as one electrode of the capacitor C. Furthermore, the gate of the transistor M2 is electrically connected to the other electrode of the capacitor C, and one of the source and drain is electrically connected to one of the source and drain of the transistor M3, and the other of the source and drain is electrically connected to the wiring PL[i,s]. Furthermore, the gate of the transistor M3 is electrically connected to the wiring RWL[j], and the other of the source and drain is electrically connected to the wiring RBL[i,s].

[0339] In the memory cell 10[i,j], the other electrode of the capacitor C, the other of the source or drain of the transistor M1, and the gate of the transistor M2 are electrically connected, and a region that is always at the same potential is called a node ND.

[0340] In the memory cell 10[i,j+1], the gate of the transistor M1 is electrically connected to the wiring WWL[j+1], and one of the source and drain is electrically connected to the wiring WBL[i,s+1]. Note that FIG. 19A shows a configuration example in which a part of the wiring WWL[j+1] functions as the gate of the transistor M1. One electrode of the capacitor C is electrically connected to the wiring PL[i,s+1], and the other electrode is electrically connected to the other of the source and drain of the transistor M1. Note that, for example, FIG. 19A shows a configuration example in which a part of the wiring PL[i,s+1] functions as one electrode of the capacitor C. Furthermore, the gate of the transistor M2 is electrically connected to the other electrode of the capacitor C, and one of the source and drain is electrically connected to one of the source and drain of the transistor M3, and the other of the source and drain is electrically connected to the wiring PL[i,s+1]. The gate of the transistor M3 is electrically connected to the wiring RWL[j+1], and the other of the source and the drain is electrically connected to the wiring RBL[i,s].

[0341] As described above, the wiring RBL[i,s] is electrically connected to the other of the source and drain of the transistor M3 in the memory cell 10[i,j] and the other of the source and drain of the transistor M3 in the memory cell 10[i,j+1]. Therefore, the wiring RBL[i,s] is shared by the memory cell 10[i,j] and the memory cell 10[i,j+1]. Although not shown, the wiring WBL[i,s] is shared by the memory cell 10[i,j-1] and the memory cell 10[i,j], and the wiring WBL[i,s+1] is shared by the memory cell 10[i,j+1] and the memory cell 10[i,j+2].

[0342] In the memory cell 10[i, j+1], the other electrode of the capacitor C, the other of the source or drain of the transistor M1, and the gate of the transistor M2 are electrically connected, and a region that is always at the same potential is called a node ND.

[0343] 19A, a transistor having a back gate may be used as each of the transistors M1, M2, and M3. The gate and the back gate are arranged to sandwich a semiconductor channel formation region between them. The gate and the back gate are formed of a conductor. The back gate can function in the same manner as the gate. The threshold voltage of the transistor can be changed by changing the potential of the back gate. The potential of the back gate may be the same as the gate, or may be ground potential or any other potential.

[0344] Note that the transistors M1, M2, and M3 do not necessarily have back gates. For example, as shown in FIG. 19B , the transistor M1 may have a back gate, and the transistors M2 and M3 may not have back gates.

[0345] Furthermore, since the gate and back gate are made of conductors, they also have the function of preventing an electric field generated outside the transistor from acting on the semiconductor in which the channel is formed (particularly, an electrostatic shielding function against static electricity). That is, it is possible to suppress fluctuations in the electrical characteristics of the transistor due to the influence of an external electric field such as static electricity. Furthermore, by providing a back gate, it is possible to reduce the amount of change in the threshold voltage of the transistor before and after the BT test.

[0346] For example, by using a transistor having a back gate as the transistor M1, the influence of an external electric field can be reduced and the transistor M1 can be stably maintained in an off state. Therefore, data written to the node ND can be stably held. By providing a back gate, the operation of the memory cell 10 can be stabilized, and the reliability of the storage device including the memory cell 10 can be improved.

[0347] Similarly, by using a transistor having a back gate as the transistor M3, the influence of an external electric field is reduced and the transistor M3 can be stably maintained in an off state, thereby reducing leakage current between the wiring RBL and the wiring PL and reducing power consumption of the memory device including the memory cell 10.

[0348] For the semiconductor layers in which the channels of the transistors M1, M2, and M3 are formed, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. Examples of the semiconductor material include silicon and germanium. Alternatively, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor can be used.

[0349] Note that the transistors M1, M2, and M3 preferably use transistors (also referred to as "OS transistors") that use an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. The oxide semiconductor has a band gap of 2 eV or more, and therefore has a significantly low off-state current. Therefore, the power consumption of the memory cell 10 can be reduced. Therefore, the power consumption of the memory device 100 including the memory cell 10 can be reduced.

[0350] A memory cell including an OS transistor can be called an "OS memory." The memory device 100 including the memory cell can also be called an "OS memory."

[0351] Furthermore, the OS transistor operates stably even in a high-temperature environment, and its characteristics fluctuate little. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range of room temperature to 200° C. Furthermore, the on-state current hardly decreases even in a high-temperature environment. Therefore, the OS memory operates stably even in a high-temperature environment, and high reliability is achieved.

[0352] <Example of Operation of Memory Cell 10> A description will be given of an example of a data write operation and a data read operation of the memory cell 10. In this embodiment, normally-off n-channel transistors are used as the transistors M1, M2, and M3.

[0353] Fig. 20 is a timing chart for explaining an example of operation of the memory cell 10. Fig. 21A, Fig. 21B, Fig. 22A, and Fig. 22B are circuit diagrams for explaining an example of operation of the memory cell 10.

[0354] In addition, in drawings and the like, to indicate the potential of a wiring or an electrode, "H" indicating a potential H or "L" indicating a potential L may be added next to the wiring or electrode. Furthermore, "H" or "L" may be enclosed in a box next to a wiring or electrode in which a potential change has occurred. Furthermore, when a transistor is in an off state, an "x" symbol may be added over the transistor.

[0355] Furthermore, when a potential H is supplied to the gate of an n-channel transistor, the transistor is turned on. When a potential L is supplied to the gate of an n-channel transistor, the transistor is turned off. Therefore, the potential H is higher than the potential L. The potential H may be the same potential as the high power supply potential VDD. The potential L is lower than the potential H. The potential L may be the same potential as the ground potential GND. In this embodiment, the potential L is the same potential as the ground potential GND.

[0356] First, in the period T0, the potentials of the wirings WWL, RWL, WBL, RBL, and PL and the node ND are set to the potential L (FIG. 20). Also, the ground potential GND is supplied to the back gates of the transistors M1, M2, and M3.

[0357] [Data Write Operation] In the period T1, a potential H is supplied to the wiring WWL and the wiring WBL (FIGS. 20 and 21A). Then, the transistor M1 is turned on, and the potential H is written to the node ND as data indicating "1".

[0358] When the potential of the node ND becomes the potential H, the transistor M2 is turned on. The potential of the wiring RWL is the potential L, so the transistor M3 is turned off. By keeping the transistor M3 in the off state, a short circuit between the wiring RBL and the wiring PL can be prevented.

[0359] [Retention Operation] In the period T2, a potential L is supplied to the wiring WWL. Then, the transistor M1 is turned off, and the node ND is brought into a floating state. Therefore, the data (potential H) written to the node ND is retained (FIGS. 20 and 21B). Note that after the end of the period T2, the potential of the wiring WBL becomes the potential L.

[0360] As described above, an OS transistor has an extremely low off-state current. By using an OS transistor as the transistor M1, data written to the node ND can be held for a long period of time. Therefore, the node ND does not need to be refreshed, and the power consumption of the memory cell 10 can be reduced. Therefore, the power consumption of the memory device 100 can be reduced.

[0361] Furthermore, by using an OS transistor as one or both of the transistors M2 and M3, leakage current flowing between the wiring RBL and the wiring PL can be significantly reduced during writing and holding operations.

[0362] In addition, an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon in a semiconductor layer in which a channel is formed (also referred to as a Si transistor). By using an OS transistor as the transistor M1, a higher potential can be supplied to the node ND. Therefore, the potential range held in the node ND can be increased. By increasing the potential range held in the node ND, multi-level data or analog data can be easily held.

[0363] [Read Operation] In the period T3, the wiring RBL is precharged to a potential H. That is, the potential of the wiring RBL is set to the potential H, and then the wiring RBL is set to a floating state (FIGS. 20 and 22A).

[0364] Next, in a period T4, a potential H is supplied to the wiring RWL to turn on the transistor M3 (FIGS. 20 and 22B). At this time, when the potential of the node ND is the potential H, the transistor M2 is on, and therefore the wiring RBL and the wiring PL are brought into electrical continuity through the transistors M2 and M3. When the wiring RBL and the wiring PL are brought into electrical continuity, the potential of the floating wiring RBL changes from the potential H to the potential L.

[0365] Note that when the potential L is written to the node ND as data indicating "0," the transistor M2 is in an off state. Therefore, even if the transistor M3 is turned on, the wiring RBL and the wiring PL are not brought into electrical continuity, and the potential of the wiring RBL remains at the potential H.

[0366] In this manner, by detecting a change in the potential of the wiring RBL when the potential H is supplied to the wiring RWL, data written in the memory cell 10 can be read.

[0367] In the memory cell 10 using an OS transistor, charge is written to the node ND via the OS transistor, so the high voltage required in conventional flash memories is not necessary and high-speed write operations can be achieved. Furthermore, unlike flash memories, charge is not injected into or extracted from the floating gate or the charge trapping layer, so the memory cell 10 using an OS transistor can write and read data a virtually unlimited number of times. Unlike flash memories, the memory cell 10 using an OS transistor does not experience instability due to an increase in electron trap centers even during repeated rewrite operations. The memory cell 10 using an OS transistor exhibits less degradation and higher reliability than conventional flash memories.

[0368] The memory cell 10 using an OS transistor does not involve a structural change at the atomic level, unlike a magnetic memory or a resistance change memory, etc. Therefore, the memory cell 10 using an OS transistor has higher rewrite endurance than a magnetic memory or a resistance change memory.

[0369] <Configuration Example of Sense Amplifier 46> Next, a configuration example of the sense amplifier 46 will be described. Specifically, a configuration example of a write / read circuit that includes the sense amplifier 46 and writes or reads a data signal will be described.

[0370] 23 is a circuit diagram showing a configuration example of a circuit 600 that writes and reads data signals and includes a sense amplifier 46. The circuit 600 is provided for each wiring WBL and each wiring RBL.

[0371] The circuit 600 includes transistors 661 to 666 , a sense amplifier 46 , an AND circuit 652 , an analog switch 653 , and an analog switch 654 .

[0372] The circuit 600 operates in accordance with the signals SEN, SEP, BPR, RSEL, WSEL, GRSEL, and GWSEL.

[0373] Data DIN input to the circuit 600 is written to the memory cell 10 via a wiring WBL electrically connected to the node NS. Data DOUT written to the memory cell 10 is transmitted to a wiring RBL electrically connected to the node NSB, and is output from the circuit 600 as data DOUT.

[0374] The data DIN and data DOUT are internal signals and correspond to the signals WDA and RDA, respectively.

[0375] The transistor 661 constitutes a precharge circuit. The transistor 661 precharges the wiring RBL to a precharge potential Vpre. Note that in this embodiment, a case will be described in which a potential Vdd (high level) is used as the precharge potential Vpre (denoted as Vdd (Vpre) in FIG. 23 ). A signal BPR is a precharge signal, and the conduction state of the transistor 661 is controlled by the signal BPR.

[0376] During a read operation, the sense amplifier 46 determines whether the data input to the wiring RBL is high or low. During a write operation, the sense amplifier 46 functions as a latch circuit that temporarily holds the data DIN input to the circuit 600.

[0377] 23 is a latch-type sense amplifier. The sense amplifier 46 has two inverter circuits, with the input node of one inverter circuit connected to the output node of the other inverter circuit. If the input node of one inverter circuit is node NS and the output node is node NSB, complementary data is held at nodes NS and NSB.

[0378] The signals SEN and SEP are sense amplifier enable signals for activating the sense amplifier 46, and the reference potential Vref is a read determination potential. The sense amplifier 46 determines whether the potential of the node NSB at the time of activation is high or low based on the reference potential Vref.

[0379] The AND circuit 652 controls the conduction state between the node NS and the wiring WBL. The analog switch 653 controls the conduction state between the node NSB and the wiring RBL, and the analog switch 654 controls the conduction state between the node NS and the wiring that supplies the reference potential Vref.

[0380] When reading data, the potential of the line RBL is transmitted to the node NSB by the analog switch 653. When the potential of the line RBL becomes lower than the reference potential Vref, the sense amplifier 46 determines that the line RBL is at a low level. When the potential of the line RBL does not become lower than the reference potential Vref, the sense amplifier 46 determines that the line RBL is at a high level.

[0381] The signal WSEL is a write selection signal that controls the AND circuit 652. The signal RSEL is a read selection signal that controls the analog switches 653 and 654.

[0382] The transistors 662 and 663 constitute an output multiplexer circuit. The signal GRSEL is a global read selection signal that controls the output MUX circuit. The output MUX circuit has a function of selecting the wiring RBL from which data is read.

[0383] The output MUX circuit has a function of outputting data DOUT read from the sense amplifier 46 .

[0384] The transistors 664 to 666 constitute a write driver circuit. The signal GWSEL is a global write select signal that controls the write driver circuit. The write driver circuit has the function of writing data DIN to the sense amplifier 46.

[0385] The write driver circuit has a function of selecting a column to write data DIN into. The write driver circuit writes data in units of bytes, half words, or words in accordance with the signal GWSEL.

[0386] A gain cell type memory cell requires at least two transistors per memory cell, making it difficult to increase the number of memory cells that can be arranged per unit area. However, by using OS transistors as the transistors that constitute the memory cell 10, multiple memory cell arrays 15 can be stacked. That is, the amount of data that can be stored per unit area can be increased. Even if the gain cell type memory cell has a small charge storage capacity, it can operate as a memory by amplifying the stored charge using the nearest transistor. Furthermore, by using OS transistors with very low off-state current as the transistors that constitute the memory cell 10, the capacitance of the capacitor can be reduced. Alternatively, the gate capacitance of the transistor and / or the parasitic capacitance of the wiring can be used as the capacitor, thereby eliminating the need for a capacitor. That is, the area of ​​the memory cell 10 can be reduced.

[0387] This embodiment mode can be combined with other embodiment modes as appropriate.

[0388] Embodiment 3 In this embodiment, an example of a chip on which a memory device of one embodiment of the present invention is mounted will be described with reference to drawings.

[0389] 24A and 24B, multiple circuits (systems) are implemented on a chip 1200. The technology for integrating multiple circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0390] As shown in FIG. 24A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0391] Chip 1200 is provided with bumps (not shown), which are connected to a first surface of package substrate 1201 as shown in Fig. 24B. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of package substrate 1201, which are connected to motherboard 1203.

[0392] The motherboard 1203 may be provided with storage devices such as a dynamic random access memory (DRAM) 1221 and a flash memory 1222. For example, the non-single-chip random access memory (NSRAM) described in the above embodiment can be used as the DRAM 1221. This allows the DRAM 1221 to have low power consumption, high speed, and large capacity.

[0393] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the NOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing or multiply-and-accumulate operations. Providing an image processing circuit or a multiply-and-accumulate operation circuit using OS transistors in the GPU 1212 enables image processing or multiply-and-accumulate operations to be performed with low power consumption.

[0394] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0395] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0396] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0397] The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. Controllers include a mouse, a keyboard, a game controller, etc. As such an interface, a Universal Serial Bus (USB) or a High-Definition Multimedia Interface (HDMI (registered trademark)) can be used.

[0398] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0399] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0400] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided, can be called a GPU module 1204.

[0401] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a smaller size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, the product-sum operation circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0402] This embodiment mode can be combined with other embodiment modes as appropriate.

[0403] Embodiment 4 In this embodiment, an example of an electronic component in which a memory device of one embodiment of the present invention is incorporated will be described.

[0404] [Electronic Component] FIG. 25A shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in FIG. 25A includes a memory device 100, which is a memory device of one embodiment of the present invention, in a mold 711. FIG. 25A omits some parts of the electronic component 700 in order to show the interior of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the memory device 100 via wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0405] As described in the above embodiment, the memory device 100 includes the drive circuit layer 50 and the memory layer 11 (including the memory cell array 15).

[0406] 25B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 100 provided on the interposer 731.

[0407] The electronic component 730 shows an example in which the memory device 100 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0408] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0409] The interposer 731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or in multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as the through electrodes.

[0410] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require the provision of an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0411] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0412] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0413] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 100 and the height of the semiconductor device 735.

[0414] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 25B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0415] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0416] This embodiment mode can be combined with other embodiment modes as appropriate.

[0417] Embodiment 5 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0418] The storage device of one embodiment of the present invention can be applied to storage devices of various electronic devices (for example, information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, and game consoles). The storage device can also be used in image sensors, Internet of Things (IoT), healthcare-related devices, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0419] 26A to 26J and 27A to 27E illustrate examples of electronic devices including the memory device of one embodiment of the present invention, each of which includes an electronic component 700 or an electronic component 730 including the memory device described in the above embodiment.

[0420] 26A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. The display unit 5511 is provided with a touch panel and the housing 5510 is provided with buttons as input interfaces.

[0421] By applying the storage device of one embodiment of the present invention, the information terminal 5500 can hold temporary files (for example, caches when using a web browser) generated when an application is executed.

[0422] 26B shows an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0423] Like the information terminal 5500 described above, the wearable terminal can store temporary files generated when an application is executed by applying the storage device of one embodiment of the present invention.

[0424] 26C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0425] The desktop information terminal 5300, like the information terminal 5500 described above, can hold temporary files generated when an application is executed by applying the storage device of one embodiment of the present invention.

[0426] In Figures 26A to 26C, smartphones, wearable terminals, and desktop information terminals have been described as electronic devices, but other information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0427] 26D shows an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, and a freezer compartment door 5803. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0428] The storage device of one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information about food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to and from an information terminal via the Internet, for example. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the storage device of one embodiment of the present invention.

[0429] In Figure 26D, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0430] 26E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0431] FIG. 26F also shows a home-use game console 7500, which is an example of a game console. The home-use game console 7500 can be particularly referred to as a home-use game console. The home-use game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 26F , the controller 7522 can include a display unit that displays game images and an input interface other than buttons, such as a touch panel, a stick, a rotary knob, or a sliding knob. The shape of the controller 7522 is not limited to the shape shown in FIG. 26F , and the shape of the controller 7522 may be modified in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with one or more of a camera, a depth sensor, and a microphone, and may be operated by the game player's gestures or voice.

[0432] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0433] Power consumption can be reduced by applying the storage device of one embodiment of the present invention to the portable game console 5200 or the stationary game console 7500. Furthermore, the reduced power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0434] Furthermore, by applying a storage device of one embodiment of the present invention to the portable game console 5200 or the stationary game console 7500, temporary files and the like necessary for calculations that occur during game execution can be stored.

[0435] In Figures 26E and 26F, portable game machines and home-use stationary game machines are described as examples of game machines, but other game machines include, for example, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0436] [Mobile Body] A storage device according to one embodiment of the present invention can be applied to a mobile body such as an automobile and the area around the driver's seat of the automobile.

[0437] FIG. 26G illustrates an automobile 5700 as an example of a moving object.

[0438] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A storage device that displays such information may also be provided around the driver's seat.

[0439] In particular, the display device can compensate for, for example, a view blocked by a pillar or a blind spot of the driver's seat, thereby improving safety, by displaying an image from an imaging device (not shown) provided on the automobile 5700. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be improved.

[0440] Since the storage device of one embodiment of the present invention can temporarily store information, the storage device can be used to temporarily store information required in a system that performs automatic driving, road guidance, or hazard prediction of the automobile 5700. The storage device of one embodiment of the present invention may also be configured to store video images from a driving recorder installed in the automobile 5700.

[0441] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects may include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0442] [Camera] The storage device according to one embodiment of the present invention can be applied to a camera.

[0443] 26H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0444] Power consumption can be reduced by applying the storage device of one embodiment of the present invention to the digital camera 6240. Furthermore, the reduced power consumption can reduce heat generation from a circuit, and the influence of heat on the circuit itself, peripheral circuits, and modules can be reduced.

[0445] [Video Camera] The storage device of one embodiment of the present invention can be applied to a video camera.

[0446] 26I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, and a connection unit 6306. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0447] When recording video captured by the video camera 6300, the video needs to be encoded according to the data recording format. By using the storage device of one embodiment of the present invention, the video camera 6300 can store temporary files generated during encoding.

[0448] [ICD] The storage device according to one aspect of the present invention can be applied to an implantable cardioverter defibrillator (ICD).

[0449] 26J is a cross-sectional schematic diagram showing an example of an ICD. An ICD main body 5400 has at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0450] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0451] The ICD main body 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is administered.

[0452] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store, in the electronic component 700, data on the heart rate acquired by the sensor, the number of times pacing therapy has been performed, or the duration of the therapy, for example.

[0453] Furthermore, power can be received by the antenna 5404, and the power is charged in the battery 5401. Furthermore, the ICD main body 5400 has multiple batteries, thereby improving safety. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 also functions as an auxiliary power source.

[0454] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0455] [Expansion Device for PC] A storage device according to one aspect of the present invention can be applied to an expansion device for a computer such as a PC (Personal Computer) and an information terminal.

[0456] Figure 27A shows an example of such an expansion device: a portable expansion device 6100 equipped with a chip capable of storing information and externally attached to a PC. The expansion device 6100 can store information using the chip by connecting to a PC via, for example, a USB (Universal Serial Bus). While Figure 27A illustrates a portable expansion device 6100, the expansion device of one aspect of the present invention is not limited to this, and may also be, for example, a relatively large expansion device equipped with a cooling fan.

[0457] The expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with, for example, a circuit that drives the storage device of one embodiment of the present invention. For example, an electronic component 700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0458] [SD Card] A storage device according to one embodiment of the present invention can be applied to an SD card that can be attached to an electronic device such as an information terminal or a digital camera.

[0459] FIG. 27B is a schematic diagram of the external appearance of an SD card, and FIG. 27C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. A memory device and a circuit for driving the memory device are provided on the circuit board 5113. For example, an electronic component 700 and a controller chip 5115 are attached to the circuit board 5113. Note that the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, a write circuit, a row driver, a read circuit, etc. provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 700.

[0460] The capacity of the SD card 5110 can be increased by providing the electronic component 700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This enables wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 700.

[0461] [SSD] A storage device according to one embodiment of the present invention can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.

[0462] FIG. 27D is a schematic diagram of the external appearance of an SSD, and FIG. 27E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a board 5153. The connector 5152 functions as an interface for connecting to an external device. The board 5153 is housed in the housing 5151. The board 5153 is provided with a memory device and a circuit for driving the memory device. For example, the board 5153 is equipped with an electronic component 700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 700 on the back side of the board 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC (Error-Correcting Code) circuit, and the like. The circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0463] 28A is an example of a large-scale computer. The computer 5600 has a rack 5610 and multiple rack-mounted computers 5620 stored in it.

[0464] The computer 5620 can have the configuration shown in the perspective view of Fig. 28B, for example. In Fig. 28B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0465] A PC card 5621 shown in Figure 28C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 28C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

[0466] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0467] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621 or inputting signals. They can also be, for example, interfaces for outputting signals calculated by the PC card 5621. The connection terminals 5623, 5624, and 5625 can comply with standards such as USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When video signals are output from the connection terminals 5623, 5624, and 5625, the standard for each can be, for example, HDMI (registered trademark).

[0468] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0469] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0470] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. An example of the semiconductor device 5628 is a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0471] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0472] By using a storage device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller and consume less power. Furthermore, the storage device of one embodiment of the present invention consumes less power, which can reduce heat generation from a circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using a storage device of one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

[0473] This embodiment mode can be combined with other embodiment modes as appropriate.

[0474] Embodiment 6 In this embodiment, a specific example in which a semiconductor device of one embodiment of the present invention is applied to space equipment will be described with reference to FIGS.

[0475] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0476] Fig. 29 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 29, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include one or more of the thermosphere, mesosphere, and stratosphere.

[0477] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0478] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0479] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0480] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0481] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0482] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, and a space probe.

[0483] 10: memory cell, 11: memory layer, 15: memory cell array, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage generation circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: column driver, 46: sense amplifier, 47: input circuit, 48: output circuit, 50: drive circuit layer, 100: memory device, 101: capacitance, 160: conductor, 181: insulator, 183: insulator, 185: insulator, 201a: transistor, 201b: transistor, 201: transistor, 202a: transistor, 202 b: transistor, 202: transistor, 203a: transistor, 203b: transistor, 203: transistor, 205a: conductor, 205b: conductor, 205: conductor, 207a: opening, 207b: opening, 209a: conductor, 209b: conductor, 209: conductor, 210: insulator, 212: insulator, 214: insulator, 215: insulator, 216a: insulator, 216b: insulator, 222: insulator, 224f: insulating film, 224: insulator, 230a: metal oxide, 230af: metal oxide film, 230b: metal oxide, 230bf: metal oxide film, 230: metal Oxide, 231: conductor, 232: conductor, 233: conductor, 233a: conductor, 233b: conductor, 240a: connection electrode, 240b: connection electrode, 240: connection electrode, 242a: conductor, 242A: conductive layer, 242b: conductor, 242B: conductive layer, 242c: conductor, 242d: conductor, 242e: conductor, 242: conductor, 253: insulator, 254: insulator, 258a: opening, 258b: opening, 258c: opening, 258: opening, 260: conductor, 275: insulator, 280: insulator, 282: insulator, 285: insulator, 287: insulator, 300: transistor 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 600: circuit, 652: AND circuit, 653: analog switch, 654: analog switch, 661: transistor, 662: transistor, 663: transistor, 664: transistor, 666: transistor, 700: electronic component, 702: printed circuit board, 704: mounting board, 711: mold, 712: land,713: electrode pad, 714: wire, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 1200: chip, 1201: package substrate, 1202: bump, 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: analog calculation unit, 1214: memory controller, 1215: interface, 1216: network circuit, 1221: DRAM, 1222: flash memory, 5110: SD card, 5111: housing, 5112: connector, 5113: board, 5115: controller chip, 5150: SSD, 5151: housing, 5152: connector, 5153: board, 5155: memory chip, 5156: controller chip, 5200: portable game console, 5201: housing, 5202: display unit, 5203: button, 5300: desktop information terminal, 5301: main body, 5302: display unit, 5303: keyboard, 5400: ICD main body, 5401: battery, 5402: wire, 5403: wire, 5404: antenna, 5405: subclavian vein, 5406: superior vena cava, 5500: Information terminal, 5510: housing, 5511: display unit, 5600: computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 5700: automobile, 5800: electric refrigerator-freezer, 5801: housing, 5802: refrigerator compartment door, 5803: freezer compartment door, 5900: information terminal, 5901: housing, 5902: display unit, 5903: Operation switch, 5904: operation switch, 5905: band, 6100: expansion device, 6101: housing, 6102: cap, 6103: USB connector, 6104: board, 6106: controller chip, 6240: digital camera, 6241: housing, 6242: display unit, 6243: operation switch, 6244: shutter button, 6246: lens, 6300: video camera, 6301: first housing, 6302: second housing, 6303: display unit, 6304: operation switch, 6305: lens, 6306: connection unit, 6800: satellite, 6801: aircraft,6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device, 7500: Stationary game console, 7520: Main body, 7522: Controller,

Claims

1. a first conductor, a second conductor, a first insulator, a first transistor, a second transistor, and a third transistor on the first insulator, and a second insulator on the first transistor, the second transistor, and the third transistor; the first transistor includes a first metal oxide, a third conductor and a fourth conductor electrically connected to the first metal oxide, a third insulator on the first metal oxide, and a fifth conductor on the third insulator; the second transistor includes a second metal oxide, a sixth conductor and a seventh conductor electrically connected to the second metal oxide, a fourth insulator on the second metal oxide, and an eighth conductor on the fourth insulator; the third transistor includes the second metal oxide, the seventh conductor and the ninth conductor electrically connected to the second metal oxide, a fifth insulator on the second metal oxide, and a tenth conductor on the fifth insulator; an upper surface of the fifth conductor and an upper surface of the tenth conductor have a region in contact with the second insulator; the first conductor has a portion located inside the opening of the first insulator, a region in contact with a side surface of the third conductor, and a portion located inside the opening of the second insulator, the second conductor has a region in contact with an upper surface of the fourth conductor and a portion located inside an opening of the second insulator, the second conductor and the eighth conductor are electrically connected; A semiconductor device in which the height of an upper surface of the first conductor and the height of an upper surface of the second conductor are the same or approximately the same.

2. a first conductor, a second conductor, a first insulator, a first transistor, a second transistor, and a third transistor on the first insulator, a second insulator on the first transistor, the second transistor, and the third transistor, and a capacitor; the first transistor includes a first metal oxide, a third conductor and a fourth conductor electrically connected to the first metal oxide, a third insulator on the first metal oxide, and a fifth conductor on the third insulator; the second transistor includes a second metal oxide, a sixth conductor and a seventh conductor electrically connected to the second metal oxide, a fourth insulator on the second metal oxide, and an eighth conductor on the fourth insulator; the third transistor includes the second metal oxide, the seventh conductor and the ninth conductor electrically connected to the second metal oxide, a fifth insulator on the second metal oxide, and a tenth conductor on the fifth insulator; the capacitor has an eleventh conductor, a sixth insulator on the eleventh conductor, and a twelfth conductor on the sixth insulator; an upper surface of the fifth conductor and an upper surface of the tenth conductor have a region in contact with the second insulator; the first conductor has a portion located inside the opening of the first insulator, a region in contact with a side surface of the third conductor, and a portion located inside the opening of the second insulator, the second conductor has a region in contact with an upper surface of the fourth conductor and a portion located inside an opening of the second insulator, the second conductor and the eighth conductor are electrically connected via the eleventh conductor; A semiconductor device in which the height of an upper surface of the first conductor and the height of an upper surface of the second conductor are the same or approximately the same.

3. a first conductor, a second conductor, a first insulator, a first transistor, a second transistor, and a third transistor on the first insulator, a second insulator on the first transistor, the second transistor, and the third transistor, and a capacitor; the first transistor includes a first metal oxide, a third conductor and a fourth conductor electrically connected to the first metal oxide, a third insulator on the first metal oxide, and a fifth conductor on the third insulator; the second transistor includes a second metal oxide, a sixth conductor and a seventh conductor electrically connected to the second metal oxide, a fourth insulator on the second metal oxide, and an eighth conductor on the fourth insulator; the third transistor includes the second metal oxide, the seventh conductor and the ninth conductor electrically connected to the second metal oxide, a fifth insulator on the second metal oxide, and a tenth conductor on the fifth insulator; the capacitor has an eleventh conductor, a sixth insulator on the eleventh conductor, and a twelfth conductor on the sixth insulator; a thirteenth conductor electrically connected to the first conductor has a portion located inside the opening of the sixth insulator, the first conductor and the thirteenth conductor have an overlapping region; an upper surface of the fifth conductor and an upper surface of the tenth conductor have a region in contact with the second insulator; the first conductor has a portion located inside the opening of the first insulator, a region in contact with a side surface of the third conductor, and a portion located inside the opening of the second insulator, the second conductor has a region in contact with an upper surface of the fourth conductor and a portion located inside an opening of the second insulator, the second conductor and the eighth conductor are electrically connected via the eleventh conductor; A semiconductor device in which the height of an upper surface of the first conductor and the height of an upper surface of the second conductor are the same or approximately the same.

4. a first conductor, a second conductor, a first insulator, a first transistor, a second transistor, and a third transistor on the first insulator, a second insulator on the first transistor, the second transistor, and the third transistor, and a capacitor; the first transistor includes a first metal oxide, a third conductor and a fourth conductor electrically connected to the first metal oxide, a third insulator on the first metal oxide, and a fifth conductor on the third insulator; the second transistor includes a second metal oxide, a sixth conductor and a seventh conductor electrically connected to the second metal oxide, a fourth insulator on the second metal oxide, and an eighth conductor on the fourth insulator; the third transistor includes the second metal oxide, the seventh conductor and the ninth conductor electrically connected to the second metal oxide, a fifth insulator on the second metal oxide, and a tenth conductor on the fifth insulator; the capacitor has an eleventh conductor, a sixth insulator on the eleventh conductor, and a twelfth conductor on the sixth insulator; the first conductor and the thirteenth conductor are connected via a fourteenth conductor; a lower surface of the fourteenth conductor has a region in contact with an upper surface of the first conductor; an upper surface of the fourteenth conductor has a region in contact with the thirteenth conductor and a region in contact with the sixth insulator; an upper surface of the fifth conductor and an upper surface of the tenth conductor have a region in contact with the second insulator; the first conductor has a portion located inside the opening of the first insulator, a region in contact with a side surface of the third conductor, and a portion located inside the opening of the second insulator, the second conductor has a region in contact with an upper surface of the fourth conductor and a portion located inside an opening of the second insulator, the second conductor and the eighth conductor are electrically connected via the eleventh conductor; A semiconductor device in which the height of an upper surface of the first conductor and the height of an upper surface of the second conductor are the same or approximately the same.

5. In any one of claims 1 to 4, a width of a region of the first conductor that contacts a side surface of the third conductor is smaller than a width of a region of the first conductor that contacts a side surface of the second insulator in a cross-sectional view in a channel length direction;

6. In any one of claims 1 to 4, The semiconductor device, wherein the first metal oxide and the second metal oxide each contain indium, zinc, and one or more selected from the group consisting of gallium, aluminum, and tin.