Semiconductor device and method for producing semiconductor device

Abstract

The present invention provides a semiconductor device which has a high degree of integration. A semiconductor device according to the present invention comprises first and second transistors and an insulating layer. The first transistor comprises: a source electrode; a drain electrode which is arranged on an insulating layer on the source electrode; a first semiconductor layer which is in contact with the upper surface of the source electrode, the inner wall of an opening that is provided in the insulating layer, and the upper surface of the drain electrode; a first gate insulating layer which is in contact with the upper surface and the lateral surface of the first semiconductor layer; and a first gate electrode which is arranged on the first gate insulating layer and has a region that overlaps with the inner wall of the opening. The second transistor comprises: a second semiconductor layer which is arranged on an insulating layer; a source electrode which is in contact with one of the upper surface and the lateral surface of the second semiconductor layer; a drain electrode which is in contact with the other one of the upper surface and the lateral surface of the second semiconductor layer; a second gate insulating layer which is in contact with the upper surface of the second semiconductor layer, the upper surface and the lateral surface of the source electrode, and the upper surface and the lateral surface of the drain electrode; and a second gate electrode which is arranged on the second gate insulating layer. The first semiconductor layer and the second gate electrode are in contact with each other.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a display device, a display module, and an electronic device. 1. Field of the Invention One embodiment of the present invention relates to a method for manufacturing a semiconductor device and a method for manufacturing a display device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), an electronic device equipped with any of the above devices, a driving method thereof, or a manufacturing method thereof.

[0003] Semiconductor devices having transistors are widely used in display devices and electronic devices, and there is a demand for higher integration and higher speed of the semiconductor devices. For example, when a semiconductor device is applied to a high-resolution display device, a highly integrated semiconductor device is required. As one means for increasing the integration degree of transistors, the development of fine-sized transistors is underway.

[0004] In recent years, there has been a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). Display devices for XR are desired to have high resolution and high color reproducibility in order to enhance the sense of realism and immersion. Examples of display devices applicable to such devices include liquid crystal display devices, organic electroluminescence (EL) elements, and light-emitting devices including light-emitting devices (also referred to as light-emitting elements) such as light-emitting diodes (LEDs).

[0005] Patent Document 1 discloses a display device for VR that uses an organic EL device (also called an organic EL element).

[0006] International Publication No. 2018 / 087625

[0007] An object of one embodiment of the present invention is to provide a semiconductor device including transistors with a small size and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device in which transistors are arranged at high density and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a highly integrated semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a manufacturing method of a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a novel semiconductor device and a manufacturing method thereof.

[0008] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily need to solve all of these problems. Note that problems other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc.

[0009] One embodiment of the present invention includes a first transistor, a second transistor, and an insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a first semiconductor layer, a first gate insulating layer, and a first gate electrode. The second transistor includes a third conductive layer, a fourth conductive layer, a second semiconductor layer, a second gate insulating layer, and a second conductive layer. The insulating layer is in contact with a top surface of the first conductive layer, a side surface of the first semiconductor layer, and a bottom surface of the second semiconductor layer and has an opening reaching the first conductive layer. The first conductive layer serves as one of a source electrode and a drain electrode of the first transistor. The second conductive layer serves as the other of the source electrode and the drain electrode of the first transistor and a second gate electrode of the second transistor. the third conductive layer functions as one of a source electrode and a drain electrode of the second transistor, the fourth conductive layer functions as the other of the source electrode and the drain electrode of the second transistor, the first semiconductor layer is in contact with an upper surface of the first conductive layer, an inner wall of the opening, and a side surface and an upper surface of the second conductive layer, the first gate electrode is provided on the first semiconductor layer via a first gate insulating layer to have a region overlapping with the inner wall of the opening, the second conductive layer is provided on the second semiconductor layer via a second gate insulating layer and is in contact with a lower surface of the first semiconductor layer, the third conductive layer is in contact with a side surface and an upper surface of one of the side ends of the second semiconductor layer, and the fourth conductive layer is in contact with a side surface and an upper surface of the other of the side ends of the second semiconductor layer.

[0010] In the above, the first semiconductor layer and the second semiconductor layer preferably each contain an oxide semiconductor.

[0011] Another embodiment of the present invention includes a first transistor, a second transistor, and an insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a first semiconductor layer, a gate insulating layer, and a first gate electrode. The second transistor includes a second conductive layer, a third conductive layer, the second semiconductor layer, a gate insulating layer, and a second gate electrode. The insulating layer is in contact with a top surface of the first conductive layer, a side surface of the first semiconductor layer, and a bottom surface of the second semiconductor layer and has an opening reaching the first conductive layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, an inner wall of the opening, and one side surface and a top surface of a source electrode or a drain electrode of the second transistor. a first conductive layer having a function as one of a drain electrode and a second conductive layer having a function as the other of a source electrode or a drain electrode of the first transistor and a function as one of a source electrode or a drain electrode of the second transistor; a third conductive layer having a function as the other of a source electrode or a drain electrode of the second transistor; a first gate electrode provided on the first semiconductor layer with a gate insulating layer interposed therebetween so as to have a region overlapping with an inner wall of an opening; a second conductive layer in contact with a side surface and an upper surface of one of the side ends of the second semiconductor layer; a third conductive layer in contact with a side surface and an upper surface of the other of the side ends of the second semiconductor layer; and a second gate electrode provided on the second semiconductor layer with a gate insulating layer interposed therebetween.

[0012] In the above, the first semiconductor layer and the second semiconductor layer preferably each contain an oxide semiconductor.

[0013] Another embodiment of the present invention includes forming a first conductive film, processing the first conductive film to form a first conductive layer, forming a first insulating layer over the first conductive layer, forming a first metal oxide film over the first insulating layer, processing the first metal oxide film to form a first semiconductor layer, forming a second conductive film over the first semiconductor layer, and processing the second conductive film to form a second conductive layer and a third conductive layer that cover a part of a top surface and a side surface of the first semiconductor layer, respectively, forming a second insulating layer over the first semiconductor layer, the second conductive layer, the third conductive layer, and the first insulating layer, forming a third conductive film over the second insulating layer, and forming a third conductive film over the third conductive layer, the second insulating layer, and the first insulating layer. a third insulating layer on the second semiconductor layer, the fourth conductive layer, and the second insulating layer; a fourth conductive layer on the third insulating layer; a fourth conductive layer on the third insulating layer; a fourth conductive layer on the third insulating layer; a fourth conductive layer on the third insulating layer; a fifth conductive layer on the fourth insulating layer; a second metal oxide film on the first conductive layer;

[0014] In the above method, after the first insulating layer is formed, treatment for supplying oxygen to the first insulating layer is preferably performed.

[0015] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device in which transistors are arranged at high density and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a highly integrated semiconductor device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a manufacturing method of a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a novel semiconductor device and a manufacturing method thereof can be provided.

[0016] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc.

[0017] FIG. 1A is a plan view showing an example of a semiconductor device. FIG. 1B is a cross-sectional view showing an example of a semiconductor device. FIG. 2A is a plan view showing an example of a semiconductor device. FIG. 2B is a cross-sectional view showing an example of a semiconductor device. FIG. 3A is a plan view showing an example of a semiconductor device. FIG. 3B is a cross-sectional view showing an example of a semiconductor device. FIG. 4A is a plan view showing an example of a semiconductor device. FIG. 4B is a cross-sectional view showing an example of a semiconductor device. FIG. 5A is a plan view showing an example of a semiconductor device. FIG. 5B is a cross-sectional view showing an example of a semiconductor device. FIG. 6A is a plan view showing an example of a semiconductor device. FIG. 6B is a cross-sectional view showing an example of a semiconductor device. FIGS. 7A to 7C are cross-sectional views showing an example of a semiconductor device. FIGS. 8A to 8C are cross-sectional views showing an example of a semiconductor device. FIGS. 9A to 9C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 10A to 10C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 11A to 11C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 12A to 12C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 13A to 13C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 14A to 14D are circuit diagrams of pixel circuits. FIGS. 15A to 15D are circuit diagrams of pixel circuits. FIG. 16 is a perspective view showing an example of a display device. FIG. 17 is a cross-sectional view showing an example of a display device. FIG. 18 is a cross-sectional view showing an example of a display device. FIG. 19 is a cross-sectional view showing an example of a display device. FIG. 20 is a cross-sectional view showing an example of a display device. FIG. 21 is a cross-sectional view showing an example of a display device. FIG. 22 is a cross-sectional view showing an example of a display device. FIGS. 23A to 23H are views showing an example of a pixel. FIGS. 24A to 24K are views showing an example of a pixel. FIGS. 25A to 25F are views showing an example of a configuration of a light-emitting device. FIGS. 26A to 26C are views showing an example of a configuration of a light-emitting device. FIGS. 27A and 27B are views showing an example of a light-receiving device. FIGS. 27C to 27E are views showing an example of a display device. FIGS. 28A to 28D are views showing examples of electronic devices. 29A to 29F are diagrams showing an example of an electronic device, and Fig. 30A to Fig. 30G are diagrams showing an example of an electronic device.Fig. 31 is a cross-sectional view showing an example of a semiconductor device, Fig. 32 is a cross-sectional STEM image of the semiconductor device, and Fig. 33A and Fig. 33B are diagrams showing the Id-Vg characteristics of a transistor.

[0018] The following description of the preferred embodiments will be given in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the preferred embodiments shown below.

[0019] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0020] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0021] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0022] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0023] In this specification and the like, a structure in which at least light-emitting layers are separately fabricated for light-emitting devices with different emission wavelengths may be referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting device, increasing the degree of freedom in the selection of materials and configurations, and facilitating improvements in brightness and reliability.

[0024] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other depending on their cross-sectional shapes or characteristics. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0025] In this specification and the like, a light-emitting device has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer).

[0026] In this specification and the like, a light-receiving device (also referred to as a light-receiving element) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes.

[0027] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0028] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface on which the structure is to be formed. For example, it refers to a shape having a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface on which the structure is to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, or the surface on which the structure is to be formed does not necessarily have to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0029] In this specification and the like, a mask layer (also referred to as a sacrificial layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that constitute the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0030] In this specification and the like, the term "step discontinuity" refers to a phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0031] In this specification, the phrase "planar shapes that are approximately the same" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where only a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, the phrase "planar shapes that are approximately the same" is also used.

[0032] Embodiment 1 One embodiment of the present invention is a semiconductor device that includes one lateral channel transistor (described later) and one vertical channel transistor (described later), in which any one of a source electrode, a drain electrode, and a gate electrode of the lateral channel transistor is electrically connected to any one of a source electrode, a drain electrode, and a gate electrode of the vertical channel transistor. The semiconductor device can occupy a smaller area in a substrate than a semiconductor device that includes two lateral channel transistors. In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS. 1A to 15D .

[0033] <Configuration Example> A semiconductor device 10 of one embodiment of the present invention will be described. FIG. 1A shows a plan view (also referred to as a top view) of the semiconductor device 10. FIG. 1B shows a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 1A. Note that some of the components of the semiconductor device 10 are omitted in FIG. 1A. As with FIG. 1A, some of the components are omitted in the plan views of the semiconductor device in the following drawings.

[0034] The semiconductor device 10 includes a transistor M1 and a transistor M2 on a substrate 102 .

[0035] The transistor M1 includes a semiconductor layer 109 provided on a conductive layer 112a and an insulating layer 110 stacked on a substrate 102, a conductive layer 116a in contact with the side surface and top surface of one of the side ends of the semiconductor layer 109 and one top surface of the insulating layer 110, a conductive layer 116b in contact with the side surface and top surface of the other side end of the semiconductor layer 109 and the other top surface of the insulating layer 110, an insulating layer 107 having an area in contact with the top surface of the semiconductor layer 109, the top surface and side surface of the conductive layer 116a, the top surface and side surface of the conductive layer 116b, and part of the top surface of the insulating layer 110, and a conductive layer 112b on the insulating layer 107.

[0036] In the transistor M1, the semiconductor layer 109 functions as a semiconductor layer in which a channel is formed. The conductive layer 116a functions as one of a source electrode and a drain electrode, and the conductive layer 116b functions as the other of the source electrode and the drain electrode. The insulating layer 107 functions as a gate insulating layer. The conductive layer 112b functions as a gate electrode.

[0037] The transistor M2 includes a conductive layer 112a on the substrate 102, an insulating layer 110 stacked on the conductive layer 112a and a conductive layer 112b provided on the insulating layer 107, a semiconductor layer 108 in contact with the inner wall of an opening 141 provided in the insulating layer 110, etc. (a part of the upper surface of the conductive layer 112a, a side surface of the insulating layer 110, a side surface of the insulating layer 107, and a side surface of the conductive layer 112b) and a part of the upper surface of the conductive layer 112b, an insulating layer 106 having a region in contact with the upper surface and side surface of the semiconductor layer 108 and the upper surface of the conductive layer 112b, and a conductive layer 104 provided on the insulating layer 106 so as to have a region overlapping with the inner wall of the opening 141.

[0038] In the transistor M2, the conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other of the source electrode and the drain electrode. The semiconductor layer 108 functions as a semiconductor layer in which a channel is formed. The insulating layer 106 functions as a gate insulating layer. The conductive layer 104 functions as a gate electrode.

[0039] In the transistor M2, a region of the semiconductor layer 108 located at a height between the top surface of the conductive layer 112a and the bottom surface of the conductive layer 112b in a cross-sectional view (see FIG. 1B ) and overlapping with the conductive layer 104 via the insulating layer 106 functions as a channel formation region. That is, the length of this region is the channel length of the transistor M2. Therefore, in the transistor M2, the channel length can be determined by adjusting the thicknesses of the insulating layers (insulating layer 110 and insulating layer 107) provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor with a short channel length can be manufactured with high accuracy. Furthermore, when multiple transistors M2 are manufactured, the variation in characteristics between the transistors M2 can be reduced.

[0040] Furthermore, since the transistor M2 is provided in a region where the semiconductor layer 108 overlaps with the opening 141 in a plan view (see FIG. 1A ), the perimeter of the opening 141, or more precisely, the perimeter of the channel formation region of the transistor M2 in the opening 141, is the channel width of the transistor M2. Note that in FIG. 1B , the width of the opening 141 in the X direction is narrower toward the conductive layer 112a and wider toward the conductive layer 112b. In this configuration, the perimeter of the channel formation region at the narrowest portion of the opening 141 in the X direction may be defined as the channel width of the transistor M2, or conversely, the perimeter of the channel formation region at the widest portion of the opening 141 in the X direction may be defined as the channel width of the transistor M2. Alternatively, the intermediate value between the two may be defined as the channel width of the transistor M2.

[0041] As described above, the conductive layer 112b functions as the gate electrode of the transistor M1 and the other of the source electrode and the drain electrode of the transistor M2. That is, the gate electrode of the transistor M1 and the other of the source electrode and the drain electrode of the transistor M2 are electrically connected. Therefore, the semiconductor device 10 of one embodiment of the present invention can be said to include two electrically connected transistors (the transistor M1 and the transistor M2).

[0042] Here, in transistor M1, the drain current flows through a region between conductive layer 116a and conductive layer 116b in semiconductor layer 109, whereas in transistor M2, the drain current flows through a region between conductive layer 112a and conductive layer 112b in semiconductor layer 108. That is, in transistor M1, the direction of the drain current flow is substantially parallel to the substrate surface, whereas in transistor M2, the direction of the drain current flow is substantially perpendicular to the substrate surface.

[0043] A transistor such as transistor M1, in which the source electrode and the drain electrode are arranged in the horizontal direction (the X direction or the Y direction shown in FIGS. 1A and 1B ) and the drain current flows in the horizontal direction, is also called a "horizontal channel transistor." On the other hand, a transistor such as transistor M2, in which the source electrode and the drain electrode are arranged in the vertical direction (the Z direction shown in FIGS. 1A and 1B ) and the drain current flows in the vertical direction, is also called a "vertical channel transistor."

[0044] In a vertical channel transistor, both the source electrode and the drain electrode are arranged in the Z direction, thereby significantly reducing the area occupied by the transistor in the substrate plane compared to a horizontal channel transistor. In the semiconductor device 10 of one embodiment of the present invention, one of the two transistors (transistor M2) included in the semiconductor device is a vertical channel transistor. Therefore, the semiconductor device 10 of one embodiment of the present invention can reduce the area occupied by the semiconductor device in the substrate plane compared to a semiconductor device in which two horizontal channel transistors are arranged laterally. Furthermore, in the semiconductor device 10 of one embodiment of the present invention, one of the two transistors (transistor M1) included in the semiconductor device is a horizontal channel transistor. Therefore, some transistor components, such as the source electrode and the drain electrode, can be fabricated simultaneously on the same plane. Therefore, the number of manufacturing steps can be reduced compared to a vertical channel transistor. As described above, one embodiment of the present invention can realize a semiconductor device in which transistors are arranged at high density. Furthermore, a highly integrated semiconductor device can be realized. For example, when the semiconductor device 10 of one embodiment of the present invention is used in a pixel circuit (described later) of a display device, the display device can have high resolution.

[0045] Materials that can be used for the semiconductor device 10 of one embodiment of the present invention will be described below.

[0046] [Substrate 102] There are no significant limitations on the material used for the substrate 102. The material may be determined depending on the purpose, taking into consideration the presence or absence of light-transmitting properties and heat resistance sufficient to withstand heat treatment. For example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a semiconductor substrate, a flexible substrate, a laminated film, a base film, or the like may be used.

[0047] Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. The semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0048] When the semiconductor device 10 of one embodiment of the present invention is used in a display device, a large-area glass substrate such as a sixth-generation (1500 mm × 1850 mm), seventh-generation (1870 mm × 2200 mm), eighth-generation (2200 mm × 2400 mm), ninth-generation (2400 mm × 2800 mm), or tenth-generation (2950 mm × 3400 mm) substrate can be used as the substrate 102. This enables a large display device to be manufactured. Furthermore, by increasing the size of the substrate, more display devices can be produced from one substrate, leading to reduced production costs.

[0049] In order to increase the flexibility of the semiconductor device, a flexible substrate, a lamination film, a base film, or the like may be used as the substrate 102 .

[0050] Examples of materials that can be used for flexible substrates, laminated films, base films, etc. include polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, and cellulose nanofiber.

[0051] A lightweight semiconductor device can be provided by using the above-mentioned material for the substrate 102. Furthermore, a semiconductor device that is resistant to shock can be provided by using the above-mentioned material for the substrate 102. Furthermore, a semiconductor device that is resistant to breakage can be provided by using the above-mentioned material for the substrate 102.

[0052] When a flexible substrate is used for the substrate 102, the lower the linear expansion coefficient of the flexible substrate, the more preferable it is, since deformation due to the environment is suppressed. For example, the linear expansion coefficient of the flexible substrate used for the substrate 102 is 1×10 −３ / K or less, 5×10 −５ / K or less, or 1 × 10 −５ In particular, aramid has a low coefficient of linear expansion and is therefore suitable as a flexible substrate for use in the substrate 102.

[0053] [Conductive layer 104, conductive layer 112a, conductive layer 112b, conductive layer 116a, conductive layer 116b] Examples of conductive materials that can be used for the conductive layers (conductive layer 116a and conductive layer 116b) that function as the source electrode and drain electrode of the transistor M1, the conductive layer (conductive layer 112b) that function as the gate electrode of the transistor M1, the conductive layers (conductive layer 112a and conductive layer 112b) that function as the source electrode and drain electrode of the transistor M2, and the conductive layer (conductive layer 104) that function as the gate electrode of the transistor M2 include various wirings and electrodes that constitute the semiconductor device 10 of one embodiment of the present invention. Examples of conductive materials that can be used for the conductive layers include metal elements selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), alloys containing any of the above metal elements, and alloys combining any of the above metal elements can be used. Alternatively, a semiconductor such as polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used. The method for forming the conductive material is not particularly limited, and various methods such as evaporation, chemical vapor deposition (CVD), sputtering, and spin coating may be used.

[0054] Alternatively, a Cu-X alloy (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used as the conductive material. A layer formed of a Cu-X alloy can be processed by a wet etching process, thereby reducing manufacturing costs. Alternatively, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used as the conductive material.

[0055] In addition, conductive materials that can be used for the conductive layer include conductive materials containing oxygen, such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon oxide has been added. Also, conductive materials containing nitrogen, such as titanium nitride, tantalum nitride, and tungsten nitride, can be used. The conductive layer can also have a stacked structure in which a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the above-mentioned metal element are appropriately combined.

[0056] For example, the conductive layer may have a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is stacked on an aluminum layer, a two-layer structure in which a titanium layer is stacked on a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked on a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked on a tantalum nitride layer, or a three-layer structure in which a titanium layer, an aluminum layer is stacked on the titanium layer, and a titanium layer is further stacked on the aluminum layer.

[0057] Furthermore, a plurality of conductive layers formed from the above-described conductive materials may be stacked. For example, the conductive layer may have a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined. Alternatively, the conductive layer may have a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined. Alternatively, the conductive layer may have a stacked structure in which the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

[0058] For example, the conductive layer may have a three-layer structure in which a conductive layer containing at least one of indium or zinc and oxygen is stacked on a conductive layer containing copper, and a conductive layer containing at least one of indium or zinc and oxygen is further stacked on top of that. In this case, it is preferable that the side surface of the conductive layer containing copper is also covered with a conductive layer containing at least one of indium or zinc and oxygen. Furthermore, for example, a plurality of conductive layers containing at least one of indium or zinc and oxygen may be stacked as the conductive layer.

[0059] For example, when an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 109, the conductive layers 112a and 112b in contact with the semiconductor layer 108 and the conductive layers 116a and 116b in contact with the semiconductor layer 109 are preferably made of a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Alternatively, another conductive material may be provided over the conductive material containing nitrogen.

[0060] [Insulating Layer 106, Insulating Layer 107, and Insulating Layer 110] In addition to the insulating layer (insulating layer 107) that functions as a gate insulating layer of the transistor M1, the insulating layer (insulating layer 106) that functions as a gate insulating layer of the transistor M2, and the insulating layer 110 that functions as an interlayer film, various insulating layers included in the semiconductor device 10 of one embodiment of the present invention are formed using a single layer or a stacked layer of a material selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, or the like. Alternatively, a mixture of two or more materials selected from oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.

[0061] In this specification and elsewhere, an oxynitride refers to a material containing more oxygen than nitrogen. A nitride oxide refers to a material containing more nitrogen than oxygen. The content of each element can be measured, for example, by Rutherford Backscattering Spectrometry (RBS).

[0062] For example, when an oxide semiconductor is used for the semiconductor layer 108 and the semiconductor layer 109, it is preferable to use an insulating material containing oxygen and having reduced hydrogen for the insulating layer 106, the insulating layer 107, and the insulating layer 110. For example, it is preferable to use silicon oxide for each of the insulating layer 106, the insulating layer 107, and the insulating layer 110. By using silicon oxide for each of the insulating layer 106, the insulating layer 107, and the insulating layer 110, it is difficult for the semiconductor layer 108 and the semiconductor layer 109, which have regions in contact with these insulating layers, to become n-type. Furthermore, oxygen can be efficiently supplied from these insulating layers to the semiconductor layer 108 and the semiconductor layer 109. As a result, oxygen deficiency (V Ｏ : Oxygen Vacancy) is reduced, and it is possible to simultaneously improve the electrical characteristics and reliability of the transistors M1 and M2.

[0063] On the other hand, for example, insulating layers (not shown) located above or below the transistor M1 and the transistor M2 are preferably made of an insulating material that is impermeable to impurities. For example, an insulating material containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Examples of insulating materials that are impermeable to impurities include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and silicon nitride.

[0064] By using an insulating material that is difficult for impurities to penetrate in an insulating layer located above or below transistor M1 and transistor M2, it is possible to prevent impurities from diffusing from above and below transistor M1 and transistor M2 toward transistor M1 and transistor M2, thereby improving the reliability of semiconductor device 10.

[0065] Furthermore, an insulating layer that can function as a planarization layer may be used as an insulating layer located above or below the transistor M1 and the transistor M2. Heat-resistant organic materials such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin can be used as the insulating layer that can function as a planarization layer. In addition to the above organic materials, low-dielectric-constant materials (low-k materials), siloxane resin, PSG (phosphor glass), BPSG (borophosphor glass), and the like can also be used. Note that multiple insulating layers made of these materials may be stacked.

[0066] The siloxane resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane resin may use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. The organic group may also have a fluoro group.

[0067] The insulating layer that can function as a planarizing layer may be subjected to a chemical mechanical polishing (CMP) process on the surface, which reduces the unevenness of the sample surface and improves the coverage of the insulating layer and conductive layer that will be formed later.

[0068] [Semiconductor Layer 108, Semiconductor Layer 109] The semiconductor layer 109, which functions as a semiconductor layer in which a channel of the transistor M1 is formed, and the semiconductor layer 108, which functions as a semiconductor layer in which a channel of the transistor M2 is formed, can be made of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like, either singly or in combination. Examples of semiconductor materials include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors can also be used. Examples of compound semiconductors include organic materials having semiconductor properties and metal oxides (also referred to as oxide semiconductors) having semiconductor properties. These semiconductor materials may contain impurities as dopants.

[0069] In particular, since an oxide semiconductor has a band gap of 2 eV or more, a transistor using an oxide semiconductor, which is a type of metal oxide, for a semiconductor layer in which a channel is formed (also referred to as an "OS transistor") has significantly smaller off-state current than transistors using other materials. Therefore, the power consumption of the semiconductor device 10 can be reduced. Furthermore, an OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in characteristics. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range from room temperature to 200° C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. Therefore, a semiconductor device using an OS transistor operates stably even in a high-temperature environment and has high reliability.

[0070] Examples of silicon that can be used for the semiconductor layer in which the channel is formed include single crystal silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon, etc. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0071] A transistor using amorphous silicon for the semiconductor layer where a channel is formed can be formed on a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer where a channel is formed has high field-effect mobility and can operate at high speed. Furthermore, a transistor using microcrystalline silicon for the semiconductor layer where a channel is formed has higher field-effect mobility than a transistor using amorphous silicon and can operate at high speed.

[0072] In this embodiment, OS transistors are used for both the transistor M1 and the transistor M2. That is, oxide semiconductors are used for both the semiconductor layer 108 and the semiconductor layer 109. Since an OS transistor has a high withstand voltage between the source and drain, the channel length can be shortened. Therefore, the on-state current of the transistor can be increased.

[0073] Examples of metal oxides that can be used for the semiconductor layer in which the channel of an OS transistor is formed include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0074] For example, indium oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide), indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO), etc. Alternatively, indium tin oxide containing silicon can be used.

[0075] The element M is preferably one or more elements selected from the group consisting of gallium, aluminum, yttrium, and tin, and is particularly preferably gallium.

[0076] Here, the composition of a metal oxide used for a semiconductor layer in which a channel is formed greatly affects the electrical characteristics and reliability of an OS transistor.

[0077] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized.

[0078] When an In-Zn oxide is used for a semiconductor layer in which a channel of an OS transistor is formed, a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc is preferably used. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or any of these values, or a metal oxide in a range of these values, can be used.

[0079] When an In—Sn oxide is used for a semiconductor layer in which a channel of an OS transistor is formed, a metal oxide in which the atomic ratio of indium is equal to or greater than that of tin is preferably used. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a metal oxide in a range of these values, can be used.

[0080] When an In-Sn-Zn oxide is used for a semiconductor layer in which a channel of an OS transistor is formed, a metal oxide in which the atomic ratio of indium is higher than that of tin can be used. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than that of tin can be used. For example, the atomic ratios of metal elements are In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn=6:1:6, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:8, In:Sn:Zn=6:1:6, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn=6:1:6, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:8, In:Sn:Zn=5:1:8, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7 ... In:Sn:Zn = 10:1:3, In:Sn:Zn = 10:1:6, In:Sn:Zn = 10:1:7, In:Sn:Zn = 10:1:8, In:Sn:Zn = 5:2:5, In:Sn:Zn = 10:1:10, In:Sn:Zn = 20:1:10, In:Sn:Zn = 40:1:10, or metal oxides thereof having a similar ratio can be used.

[0081] When an In-Al-Zn oxide is used for a semiconductor layer in which a channel of an OS transistor is formed, a metal oxide in which the atomic ratio of indium is higher than that of aluminum can be used. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than that of aluminum can be used. For example, the atomic ratios of metal elements may be In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=6:1:6, or In:Al:Zn=5:1:3. It is possible to use metal oxides such as In:Al:Zn = 10:1:3, In:Al:Zn = 10:1:6, In:Al:Zn = 10:1:7, In:Al:Zn = 10:1:8, In:Al:Zn = 5:2:5, In:Al:Zn = 10:1:10, In:Al:Zn = 20:1:10, In:Al:Zn = 40:1:10, or metal oxides in the vicinity of these.

[0082] When an In—Ga—Zn oxide is used for a semiconductor layer in which a channel of an OS transistor is formed, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of gallium can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc to the number of atoms of gallium is higher. For example, the semiconductor layer may have atomic ratios of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, or In:Ga:Zn=6:1: In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides thereof can be used.

[0083] When an In-M-Zn oxide is used for a semiconductor layer in which a channel of an OS transistor is formed, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc to the number of atoms of the element M is higher than the atomic ratio of the element M. For example, the semiconductor layer may have atomic ratios of metal elements of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, or In:M:Zn=6:1:6. , In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides in the vicinity of these can be used.

[0084] When a plurality of metal elements are contained as the element M, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned ranges.

[0085] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the number of atoms of metal elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In-Ga-Zn oxide is used for the semiconductor layer, it is preferable that the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is in the above-mentioned range.

[0086] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0087] By increasing the indium content of the metal oxide, a transistor with a large on-state current can be obtained. By using the transistor, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. For example, when the transistor is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0088] The composition of the metal oxide can be analyzed by, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0089] In this specification, a "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio is described as In:M:Zn = 4:2:3 or a composition near there, this includes a case where, when the atomic ratio of indium is 4, the atomic ratio of M is 1 to 3 and the atomic ratio of zinc is 2 to 4. Furthermore, when an atomic ratio is described as In:M:Zn = 5:1:6 or a composition near there, this includes a case where, when the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 5 and less than 7. Furthermore, when an atomic ratio is described as In:M:Zn = 1:1:1 or a composition near there, this includes a case where, when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 0.1 and less than 2.

[0090] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target.

[0091] Here, the reliability of a transistor will be described. One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which the transistor is held in a state in which an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate with respect to the source potential and the drain potential and the transistor is held at a high temperature is called a Positive Bias Temperature (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate and the transistor is held at a high temperature is called a Negative Bias Temperature (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and an NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0092] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows). Therefore, the amount of variation in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0093] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer where the channel of the transistor is formed, the transistor can be made highly reliable against positive bias application. That is, the transistor can be made to have a small amount of fluctuation in threshold voltage in a PBTS test. Furthermore, when using a metal oxide that contains gallium, it is preferable to make the gallium content lower than the indium content. This makes it possible to realize a highly reliable transistor.

[0094] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer where the transistor channel is formed and the gate insulating layer. The higher the defect level density, the more significant the degradation in the PBTS test. The generation of the defect levels can be suppressed by reducing the gallium content in the region of the semiconductor layer where the transistor channel is formed that contacts the gate insulating layer.

[0095] The following is a possible reason why using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer where the transistor channel is formed can suppress fluctuations in the threshold voltage in the PBTS test. Gallium contained in the metal oxide has a property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer where the transistor channel is formed and the gate insulating layer, which is thought to cause fluctuations in the threshold voltage.

[0096] More specifically, when an In—Ga—Zn oxide is used for a semiconductor layer in which a transistor channel is formed, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than that of gallium. It is also more preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for a semiconductor layer in which a transistor channel is formed.

[0097] For example, when a semiconductor layer in which a channel of an OS transistor is formed has metal elements with atomic ratios of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=5:1:9, In:Ga:Zn=5:1:10, In:Ga:Zn=5:1:11, In:Ga:Zn=5:1:12, In:Ga:Zn=5:1:13, In:Ga:Zn=5:1:14, In:Ga:Zn=5:1:15, In:Ga:Zn=5:1:16, In:Ga:Zn=5:1:17, In:Ga:Zn=5:1:18, In:Ga:Zn=5:1:19 ... In:Ga:Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides thereof having a similar ratio can be used.

[0098] The semiconductor layer in which the channel of an OS transistor is formed preferably uses a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is greater than 0 atomic % and less than 50 atomic %, preferably 0.1 atomic % to 40 atomic %, more preferably 0.1 atomic % to 35 atomic %, more preferably 0.1 atomic % to 30 atomic %, more preferably 0.1 atomic % to 25 atomic %, more preferably 0.1 atomic % to 20 atomic %, more preferably 0.1 atomic % to 15 atomic %, and more preferably 0.1 atomic % to 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to a PBTS test can be obtained. Including gallium in the metal oxide can prevent oxygen deficiency (V Ｏ ) is less likely to occur.

[0099] A metal oxide containing no gallium may be used for the semiconductor layer in which the channel of an OS transistor is formed. For example, In—Zn oxide may be used for the semiconductor layer. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide can result in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability. Furthermore, a metal oxide containing no gallium or zinc, such as indium oxide, may be used for the semiconductor layer. The use of a metal oxide containing no gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0100] For example, a semiconductor layer in which a channel of an OS transistor is formed can be formed using an oxide containing indium and zinc, in which the atomic ratio of metal elements is, for example, In:Zn=2:3, In:Zn=4:1, or a metal oxide having a ratio close to these values.

[0101] Although gallium has been used as a representative example, the present invention can also be applied to a case where the element M is used instead of gallium. For a semiconductor layer in which a channel of an OS transistor is formed, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of the element M is preferably used. Also, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M is preferably used.

[0102] By using a metal oxide having a low content of element M in a semiconductor layer in which a channel of an OS transistor is formed, a transistor with high reliability against application of a positive bias can be realized. By using the transistor as a transistor that is required to have high reliability against application of a positive bias, a highly reliable semiconductor device can be realized.

[0103] Next, the reliability of the transistor against light will be described.

[0104] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0105] By increasing the content of element M in the metal oxide used in the semiconductor layer in which the channel of the transistor is formed, a transistor with high reliability against light can be realized. That is, a transistor with a small variation in threshold voltage in the NBTIS test can be realized. Specifically, a metal oxide in which the atomic ratio of element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in the NBTIS test. The band gap of the metal oxide in the semiconductor layer in which the channel of the transistor is formed is preferably 2.0 eV or more, more preferably 2.5 eV or more, even more preferably 3.0 eV or more, still more preferably 3.2 eV or more, even more preferably 3.3 eV or more, still more preferably 3.4 eV or more, and even more preferably 3.5 eV or more.

[0106] For example, a semiconductor layer in which a channel of a transistor is formed can be made of a metal oxide having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a ratio close to these.

[0107] In particular, as the semiconductor layer in which the channel of a transistor is formed, a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0108] When an In—Ga—Zn oxide is used for a semiconductor layer in which a transistor channel is formed, a metal oxide having an atomic ratio of indium to gallium equal to or less than that of gallium can be used. For example, metal oxides having atomic ratios of metal elements of In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or similar can be used.

[0109] As the semiconductor layer in which the channel of the transistor is formed, a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is 20 atomic % or more and 60 atomic % or less, preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0110] A transistor with high reliability against light can be realized by using a metal oxide with a high content of element M in a semiconductor layer in which a channel of the transistor is formed. By applying the transistor to a transistor that is required to have high reliability against light, a highly reliable semiconductor device can be realized.

[0111] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide applied to the semiconductor layer in which the channel of the transistor is formed. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a display device that has both excellent electrical characteristics and high reliability can be realized.

[0112] The semiconductor layer in which the channel of the transistor is formed may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0113] The two or more metal oxide layers included in the semiconductor layer in which the channel of the transistor is formed may have different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a composition similar thereto and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition similar thereto provided on the first metal oxide layer can be preferably used. Furthermore, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0114] A crystalline metal oxide layer is preferably used as the semiconductor layer in which the channel of the transistor is formed. For example, a metal oxide layer having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer, the density of defect states in the semiconductor layer can be reduced, and a highly reliable display device can be realized.

[0115] The higher the crystallinity of a metal oxide layer used in a semiconductor layer in which a channel of a transistor is formed, the more the density of defect states in the semiconductor layer can be reduced.On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0116] When a metal oxide layer is formed by a sputtering method, the higher the substrate temperature (stage temperature) during formation, the higher the crystallinity of the formed metal oxide layer.Furthermore, the higher the ratio of the flow rate of oxygen gas to the total deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide layer.

[0117] The semiconductor layer in which the channel of the OS transistor is formed may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, the semiconductor layer may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided over the first metal oxide layer, where the second metal oxide layer has a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition. The stacked structure of metal oxide layers with the same composition can be formed using the same sputtering target, for example, thereby reducing manufacturing costs. For example, a stacked structure of two or more metal oxide layers with different crystallinity can be formed by using the same sputtering target and varying the oxygen flow rate. Note that the two or more metal oxide layers included in the semiconductor layer may have different compositions.

[0118] The following describes modifications of the above configuration example. Note that for parts that overlap with the above, please refer to the above and the description may be omitted.

[0119] <Modification 1> A semiconductor device 10A shown in FIGS. 2A and 2B differs from the semiconductor device 10 shown in FIGS. 1A and 1B in that a transistor M2 is provided so as to overlap a transistor M1.

[0120] As shown in FIG. 2B, the semiconductor device 10A has a structure in which the upper surface of the conductive layer 112a, which functions as the gate electrode of the transistor M1, is in contact with the lower surface of the semiconductor layer 108, which functions as the semiconductor layer in which the channel of the transistor M2 is formed.

[0121] In the semiconductor device 10A, the conductive layer 112a functions as the gate electrode of the transistor M1 and also functions as one of the source electrode and drain electrode of the transistor M2. That is, in the semiconductor device 10A, the gate electrode of the transistor M1 and one of the source electrode and drain electrode of the transistor M2 are electrically connected to each other.

[0122] As shown in FIG. 2A, the semiconductor device 10A has a configuration in which a semiconductor layer 109 that functions as a semiconductor layer in which a channel of the transistor M1 is formed and a semiconductor layer 108 that functions as a semiconductor layer in which a channel of the transistor M2 is formed are overlapped with each other.

[0123] This configuration makes it possible to realize a semiconductor device in which transistors are arranged at high density. Furthermore, the area occupied by the semiconductor device 10A on the substrate surface can be made smaller than the area occupied by the semiconductor device 10 shown in Figures 1A and 1B. Therefore, a semiconductor device with a high degree of integration can be realized.

[0124] <Variation 2> A semiconductor device 10B shown in FIGS. 3A and 3B is different from the semiconductor device 10 shown in FIGS. 1A and 1B in the configuration of the gate electrode of the transistor M1, the configuration of one of the source electrode or the drain electrode of the transistor M1, and the configuration of the gate electrode of the transistor M2.

[0125] 3B , in the semiconductor device 10B, one end of the conductive layer 104 functioning as the gate electrode of the transistor M2 extends toward the transistor M1 and covers one side end of the semiconductor layer 109 functioning as the semiconductor layer in which the channel of the transistor M1 is formed. Also, the insulating layer 106 functioning as the gate insulating layer of the transistor M2 extends toward the transistor M1 and is located under the semiconductor layer 109 functioning as the semiconductor layer in which the channel of the transistor M1 is formed and the conductive layer 116b functioning as the other of the gate electrode or drain electrode of the transistor M1.

[0126] In the semiconductor device 10B, the conductive layer 103 functions as the gate electrode of the transistor M1. The conductive layer 104 also functions as one of the source electrode or drain electrode of the transistor M1 and as the gate electrode of the transistor M2. That is, in the semiconductor device 10B, one of the source electrode or drain electrode of the transistor M1 is electrically connected to the gate electrode of the transistor M2. It can be said that the transistor M1 in the semiconductor device 10B corresponds to the transistor M2 in the semiconductor device 10, and the transistor M2 in the semiconductor device 10B corresponds to the transistor M1 in the semiconductor device 10. With this configuration, it is possible to obtain the same effects as those obtained by the semiconductor device 10.

[0127] <Variation 3> A semiconductor device 10C shown in FIGS. 4A and 4B is different from the semiconductor device 10 shown in FIGS. 1A and 1B in the configuration of the gate electrode of the transistor M1, the configuration of one of the source electrode or the drain electrode of the transistor M1, the configuration of the other of the source electrode or the drain electrode of the transistor M2, and the configuration of the gate insulating layer of the transistor M2.

[0128] 4B , in the semiconductor device 10C, the conductive layer 112b functioning as one of the source electrode or drain electrode of the transistor M1 extends toward the transistor M2 and is in contact with the bottom surface of the semiconductor layer 108 functioning as the semiconductor layer in which the channel of the transistor M2 is formed. The insulating layer 106 functioning as the gate insulating layer of the transistor M2 extends toward the transistor M1 and covers the conductive layer 112b, the semiconductor layer 109 functioning as the semiconductor layer in which the channel of the transistor M1 is formed, and the conductive layer 112c functioning as the other of the source electrode or drain electrode of the transistor M1.

[0129] In the semiconductor device 10C, the conductive layer 103 functions as the gate electrode of the transistor M1. The conductive layer 112b functions as one of the source and drain electrodes of the transistor M1 and the other of the source and drain electrodes of the transistor M2. That is, in the semiconductor device 10C, one of the source and drain electrodes of the transistor M1 and the other of the source and drain electrodes of the transistor M2 are electrically connected. The conductive layer 112c functions as the other of the source and drain electrodes of the transistor M1. The insulating layer 106 functions as the gate insulating layer of the transistor M1 and also as the gate insulating layer of the transistor M2. This configuration can achieve the same effects as those achieved by the semiconductor device 10. Furthermore, the number of processes can be reduced because the semiconductor device 10 does not have the insulating layer 107.

[0130] <Variation 4> A semiconductor device 10D shown in FIGS. 5A and 5B is different from the semiconductor device 10 shown in FIGS. 1A and 1B in the configuration of the gate electrode of the transistor M1, the configuration of one of the source electrode or the drain electrode of the transistor M1, and the configuration of the other of the source electrode or the drain electrode of the transistor M2.

[0131] In the semiconductor device 10D, the conductive layer 103 functions as the gate electrode of the transistor M1. The conductive layer 112a functions as one of the source electrode or drain electrode of the transistor M1 and also functions as one of the source electrode or drain electrode of the transistor M2. The conductive layer 112d functions as the other of the source electrode or drain electrode of the transistor M1. The conductive layer 112b functions as the other of the source electrode or drain electrode of the transistor M2. The conductive layer 112b extends over the transistor M1 with the insulating layer 110 interposed therebetween. That is, in the semiconductor device 10D, one of the source electrode or drain electrode of the transistor M1 and one of the source electrode or drain electrode of the transistor M2 are electrically connected. With this configuration, the same effects as those obtained in the semiconductor device 10 can be obtained.

[0132] <Variation 5> A semiconductor device 10E shown in FIGS. 6A and 6B is different from the semiconductor device 10 shown in FIGS. 1A and 1B in the configuration of the gate electrode of the transistor M1, the configuration of the gate insulating layer of the transistor M1, the configuration of one of the source electrode or drain electrode of the transistor M1, the configuration of one of the source electrode or drain electrode of the transistor M2, and the configuration of the other of the source electrode or drain electrode of the transistor M2.

[0133] In the semiconductor device 10E, the conductive layer 112e functions as the gate electrode of the transistor M1. The insulating layer 107 and the insulating layer 110 function as the gate insulating layer of the transistor M1. The conductive layer 112a functions as one of the source electrode or drain electrode of the transistor M1 and also as one of the source electrode or drain electrode of the transistor M2. The conductive layer 112d functions as the other of the source electrode or drain electrode of the transistor M1. The conductive layer 112b functions as the other of the source electrode or drain electrode of the transistor M2. That is, in the semiconductor device 10E, the thickness of the gate insulating layer of the transistor M1 is thicker than the thickness of the gate insulating layer of the transistor M1 included in the semiconductor device 10. Furthermore, one of the source electrode or drain electrode of the transistor M1 and one of the source electrode or drain electrode of the transistor M2 are electrically connected. With this configuration, the same effects as those obtained by the semiconductor device 10 can be obtained.

[0134] 7A is different from the semiconductor device 10 shown in FIGS. 1A and 1B in that the other of the source electrode and the drain electrode of the transistor M2 (conductive layer 112b) is in contact with the top surface of the semiconductor layer (semiconductor layer 108) in which the channel of the transistor M2 is formed, and that the bottom surface of the semiconductor layer is in contact with the top surface of the gate insulating layer (insulating layer 107) of the transistor M1. The other configurations are the same as those of the semiconductor device 10. This configuration allows for the same effects as those of the semiconductor device 10.

[0135] 7B is different from the semiconductor device 10A shown in FIGS. 2A and 2B in that the other of the source electrode and the drain electrode of the transistor M2 (conductive layer 112b) is in contact with the top surface of the semiconductor layer (semiconductor layer 108) in which the channel of the transistor M2 is formed. The other configuration is the same as that of the semiconductor device 10A. This configuration allows for the same effects as those obtained by the semiconductor device 10A to be obtained.

[0136] 7C is different from the semiconductor device 10B shown in FIGS. 3A and 3B in that the other of the source electrode and the drain electrode of the transistor M2 (conductive layer 112b) is in contact with the top surface of the semiconductor layer (semiconductor layer 108) in which the channel of the transistor M2 is formed. The other configuration is the same as that of the semiconductor device 10B. This configuration allows for the same effects as those obtained by the semiconductor device 10B to be obtained.

[0137] 8A is different from the semiconductor device 10C shown in FIGS. 4A and 4B in that the other of the source electrode and the drain electrode of the transistor M2 (conductive layer 112b) is in contact with the top surface of the semiconductor layer (semiconductor layer 108) in which the channel of the transistor M2 is formed. The other configuration is the same as that of the semiconductor device 10C. This configuration allows for the same effects as those obtained by the semiconductor device 10C to be obtained.

[0138] 8B is different from the semiconductor device 10D shown in FIGS. 5A and 5B in that the other of the source electrode and the drain electrode of the transistor M2 (conductive layer 112b) is in contact with the top surface of the semiconductor layer (semiconductor layer 108) in which the channel of the transistor M2 is formed. The other configuration is the same as that of the semiconductor device 10D. This configuration allows for the same effects as those obtained by the semiconductor device 10D to be obtained.

[0139] 8C is different from the semiconductor device 10E shown in FIGS. 6A and 6B in that the other of the source electrode and the drain electrode of the transistor M2 (conductive layer 112b) is in contact with the top surface of the semiconductor layer (semiconductor layer 108) in which the channel of the transistor M2 is formed. The other configuration is the same as that of the semiconductor device 10E. This configuration allows for the same effects as those obtained by the semiconductor device 10E to be obtained.

[0140] <Manufacturing Method Example> Next, a description will be given of an example of a manufacturing method of the semiconductor device 10. First, constituent materials of each layer and a method for forming each layer will be described.

[0141] [Method of Forming Each Layer] Insulating layers, semiconductor layers, conductive layers for forming electrodes or wirings, etc. can be formed using a sputtering method, a CVD method, a vacuum deposition method, a pulsed laser deposition (PLD) method, an ALD method, etc. CVD methods may include plasma enhanced chemical vapor deposition (PECVD) methods or thermal CVD methods. An example of a thermal CVD method is metal organic chemical vapor deposition (MOCVD) methods.

[0142] Furthermore, the insulating layer, semiconductor layer, conductive layer, and the like that constitute the semiconductor device may be formed by a method such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, slit coating, roll coating, curtain coating, or knife coating.

[0143] The PECVD method can produce high-quality films at relatively low temperatures. When a film formation method that does not use plasma during film formation, such as MOCVD, ALD, or thermal CVD, is used, damage to the surface on which the film is formed is less likely to occur. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, when a film formation method that does not use plasma is used, such plasma damage does not occur, and therefore the yield of semiconductor devices can be increased. Furthermore, since plasma damage does not occur during film formation, films with fewer defects can be obtained.

[0144] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0145] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film whose composition changes continuously by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for transportation and pressure adjustment is eliminated compared to when forming a film using multiple film formation chambers, and the time required for the entire film formation process can be shortened. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0146] When processing a layer (thin film) constituting a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, an island-shaped layer may be formed by a film formation method using a masking mask. Alternatively, the layer may be processed by a nanoimprint method, a sandblasting method, a lift-off method or the like. Photolithography methods include a method in which a resist mask is formed on the layer (thin film) to be processed, and a method in which a resist mask is used as a mask to selectively remove a portion of the layer (thin film), and then the resist mask is removed, and a method in which a photosensitive layer is formed, and then the layer is processed into a desired shape by exposure and development.

[0147] When light is used in photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0148] The layer (thin film) can be removed (etched) by dry etching, wet etching, sandblasting, etc. These etching methods may also be used in combination.

[0149] An example of a method for manufacturing the semiconductor device 10 will be described below.

[0150] First, a conductive layer 112a is formed over a substrate 102, and an insulating layer 110 is formed over the conductive layer 112a (see FIG. 9A).

[0151] For example, an insulating substrate having an insulating surface is used as the substrate 102. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate.

[0152] Furthermore, a semiconductor substrate or a conductor substrate may be used as the substrate 102, if necessary. Examples of the semiconductor substrate include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, examples of the semiconductor substrate include semiconductor substrates having an insulator region therein, such as an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Other examples include substrates in which a conductor or semiconductor is provided on an insulator substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductor substrate. Alternatively, these substrates may have elements provided thereon. Examples of elements provided on the substrate include capacitors, resistors, switch elements, light-emitting elements, and memory elements.

[0153] The conductive film that will become the conductive layer 112a can be formed by, for example, a sputtering method using the above-described material. After a resist mask (not shown) is formed on the conductive film by a photolithography process, the conductive film is processed to form the conductive layer 112a that will later become one of the source and drain electrodes of the transistor M2. The conductive film can be processed by wet etching or dry etching, or both.

[0154] Note that when the conductive layer 112a, which functions as one of the source electrode and the drain electrode of the transistor M2, also functions as a wiring, the wiring is preferably formed of a material with low electrical resistance. Therefore, the conductive layer 112a is preferably formed of a material with low electrical resistance. Alternatively, a conductive layer formed of a material with lower electrical resistance than the conductive layer 112a is preferably stacked above or below the conductive layer 112a.

[0155] For example, it is preferable to use a conductive oxide material for the conductive layer 112a and to use a metal, an alloy, or a nitride thereof that can be used for the conductive layer 104 or the like for a conductive layer stacked with the conductive layer 112a. By providing a conductive layer having lower electrical resistance than the conductive layer 112a in contact with the conductive layer 112a, when the conductive layer 112a is used as a wiring, the wiring resistance can be reduced.

[0156] The insulating layer 110 can be formed by, for example, the PECVD method using the above-mentioned materials. The insulating layer 110 may have a stacked structure of two or more layers. In this case, it is preferable to form each layer successively in a vacuum without exposing the surface of each layer to the atmosphere. This makes it possible to prevent impurities from the atmosphere from adhering to the surface of each layer. Examples of such impurities include water and organic substances.

[0157] The substrate temperature during the formation of the insulating layer 110 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, even more preferably 250° C. or higher and 450° C. or lower, even more preferably 300° C. or higher and 450° C. or lower, even more preferably 300° C. or higher and 400° C. or lower, and even more preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating layer 110 within the above-mentioned range, it is possible to reduce the release of impurities (e.g., water and hydrogen) from the insulating layer 110 itself, and to suppress the diffusion of the impurities into the semiconductor layer 109 to be formed later. This makes it possible to realize a semiconductor device that exhibits good electrical characteristics and is highly reliable.

[0158] Since the insulating layer 110 is formed before the semiconductor layer 109, there is no need to worry about oxygen being released from the semiconductor layer 109 due to heat applied during the formation of the insulating layer 110.

[0159] Heat treatment may be performed after the insulating layer 110 is formed. By performing the heat treatment, water and hydrogen can be released from the surface of the insulating layer 110 and from the film.

[0160] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a rare gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) may be used. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. By using an atmosphere containing as little hydrogen, water, or the like as possible, it is possible to prevent hydrogen, water, or the like from being taken into the insulating layer 110 as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) device, etc. By using an RTA device, the heat treatment time can be shortened.

[0161] Next, a process for supplying oxygen 160 to the insulating layer 110 is performed (see FIG. 9B ). Examples of the oxygen 160 include oxygen radicals, oxygen atoms, oxygen atomic ions, and oxygen molecular ions. The oxygen 160 can be supplied by, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment.

[0162] For the plasma treatment, an apparatus that converts oxygen gas into plasma by high-frequency power (also called a plasma etching apparatus or a plasma ashing apparatus) can be suitably used. For example, plasma treatment may be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ Oxygen may be supplied to the insulating layer 110 by plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide gas. When plasma treatment containing nitrous oxide gas is performed, oxygen can be supplied while organic substances on the surface of the insulating layer 110 are suitably removed.

[0163] Next, a metal oxide film 109f, which will later become the semiconductor layer 109, is formed over the insulating layer 110 (see FIG. 9C). The metal oxide film 109f is preferably formed by a sputtering method using a metal oxide target.

[0164] The metal oxide film 109f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 109f is preferably a high-purity film in which impurities including hydrogen are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 109f.

[0165] When the metal oxide film 109f is formed, oxygen gas is preferably used. By using oxygen gas when the metal oxide film 109f is formed, oxygen can be suitably supplied into the insulating layer 110.

[0166] By supplying oxygen to the insulating layer 110, oxygen is supplied to the semiconductor layer 109 in a later process, and oxygen vacancies (V Ｏ ), and defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V Ｏ This can reduce the amount of heat generated by the heat sink.

[0167] When forming the metal oxide film 109f, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). The higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film 109f (oxygen flow ratio), the higher the crystallinity of the metal oxide film 109f, thereby achieving a highly reliable transistor M1. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film 109f, thereby achieving a transistor M1 with a large on-state current.

[0168] The higher the substrate temperature when the metal oxide film 109f is formed, the higher the crystallinity and density of the metal oxide film 109f can be.On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film 109f can be.

[0169] The substrate temperature during the formation of the metal oxide film 109f may be set to a range from room temperature to 250° C., preferably from room temperature to 200° C., and more preferably from room temperature to 140° C. For example, setting the substrate temperature to a range from room temperature to 140° C. is preferable because productivity is increased. Furthermore, by setting the substrate temperature to room temperature or by forming the metal oxide film 109f without heating the substrate, the crystallinity can be reduced.

[0170] When the semiconductor layer 109 has a stacked structure, it is preferable that after a metal oxide film is formed first, a next metal oxide film is formed successively without exposing the surface of the first metal oxide film to the air.

[0171] After the metal oxide film 109f is formed, heat treatment may be performed. By performing the heat treatment, water and hydrogen can be desorbed from the surface and the inside of the metal oxide film 109f. Furthermore, by the heat treatment, oxygen can be supplied from the insulating layer 110 to the metal oxide film 109f. Furthermore, by the heat treatment, the film quality of the metal oxide film 109f may be improved (for example, by reducing defects or improving crystallinity). Note that the conditions for the heat treatment can be the same as those for the heat treatment that can be performed after the formation of the insulating layer 110.

[0172] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, there are cases where a high-temperature treatment in a later step (e.g., a film formation step) can also serve as the heat treatment.

[0173] Next, the metal oxide film 109f is processed into an island shape to form the semiconductor layer 109 (see FIG. 10A).

[0174] The semiconductor layer 109 can be formed by one or both of a wet etching method and a dry etching method. For example, a wet etching method can be suitably used for forming the semiconductor layer 109. At this time, a part of the insulating layer 110 in a region that does not overlap with the semiconductor layer 109 may be etched, resulting in a thin film thickness. Note that in etching the metal oxide film 109f, by using a material with a high etching selectivity for the insulating layer 110, the thin film thickness of the insulating layer 110 can be prevented from being thinned.

[0175] Next, a conductive film 116f, which will later become the conductive layers 116a and 116b (see FIG. 10B ), is formed over the semiconductor layer 109 and the insulating layer 110. The conductive film 116f can be formed by a sputtering method using any of the above-described materials, for example.

[0176] Next, a resist mask (not shown) is formed over the conductive film 116f by a photolithography process, and then the conductive film is processed to form conductive layers 116a and 116b that cover part of the top surface and side surfaces of the semiconductor layer 109 (see FIG. 10C ). The conductive layers 116a and 116b will later become the source and drain electrodes of the transistor M1. The conductive layers 116a and 116b can be formed by either or both of a wet etching method and a dry etching method. For example, the wet etching method can be suitably used to form the conductive layers 116a and 116b.

[0177] Note that when the conductive layers 116a and 116b are formed, the thickness of the semiconductor layer 109 in a region not overlapping with the conductive layers 116a and 116b may be thinner than the thickness of the semiconductor layer 109 in a region overlapping with the conductive layers 116a and 116b. Furthermore, the thickness of the insulating layer 110 in a region not overlapping with the conductive layers 116a and 116b may be thinner than the thickness of the insulating layer 110 in a region overlapping with the conductive layers 116a and 116b.

[0178] After the conductive layers 116a and 116b are formed, cleaning treatment may be performed. As the cleaning treatment, wet cleaning using a cleaning solution or cleaning by plasma treatment using plasma can be used. The above cleaning treatments may be combined as appropriate.

[0179] When the conductive layers 116a and 116b are formed, the surface of the semiconductor layer 109 may be damaged. Ｏ is formed, and V Ｏ In some cases, H may be formed. By performing cleaning treatment after the formation of the conductive layers 116a and 116b, the damaged layers can be removed. Furthermore, by performing cleaning treatment, impurities (e.g., metals and organic substances) attached to the surface of the semiconductor layer 109 during the formation of the conductive layers 116a and 116b can be removed.

[0180] For example, a cleaning solution containing one or more of phosphoric acid, oxalic acid, and hydrochloric acid can be used for wet cleaning. A cleaning solution containing phosphoric acid can be suitably used for wet cleaning. The concentration of the cleaning solution is preferably determined in consideration of the etching rate for the semiconductor layer 109. For example, when a cleaning solution containing phosphoric acid is used, the phosphoric acid concentration is preferably 0.01 weight% to 5 weight%, more preferably 0.02 weight% to 4 weight%, even more preferably 0.05 weight% to 3 weight%, still more preferably 0.1 weight% to 2 weight%, and even more preferably 0.15 weight% to 1 weight%. By setting the concentration within the above-mentioned range, it is possible to prevent the semiconductor layer 109 from disappearing, and it is possible to efficiently remove damaged layers of the semiconductor layer 109 and impurities (e.g., metals and organic substances) attached to the semiconductor layer 109.

[0181] The plasma treatment may involve the use of, for example, oxygen, ozone, nitrogen, or nitrous oxide (N ２ For the plasma treatment, it is preferable to use a gas containing oxygen. In particular, nitrous oxide (N ２ By using a gas containing O, it is possible to suitably remove organic substances from the surface of the semiconductor layer 109. The plasma treatment can be performed using, for example, a PECVD apparatus or an etching apparatus.

[0182] Next, the insulating layer 107, which will later become a gate insulating layer of the transistor M1, is formed over the semiconductor layer 109, the conductive layer 116a, the conductive layer 116b, and the insulating layer 110 (see FIG. 11A). The insulating layer 107 can be formed by, for example, a PECVD method using the above-described material.

[0183] When an oxide semiconductor is used for the semiconductor layer 109, it is preferable to use an insulating material containing oxygen and having reduced hydrogen for the insulating layer 107. This makes it difficult for the semiconductor layer 109 having a region in contact with the insulating layer 107 to become n-type. In addition, oxygen can be efficiently supplied from the insulating layer 107 to the semiconductor layer 109, so that oxygen vacancies (VＯ ) can be reduced. The semiconductor layer 109 functions as a semiconductor layer in which a channel of the transistor M1 will be formed later. Therefore, by using the above-described material for the insulating layer 107, the transistor M1 can exhibit good electrical characteristics and be highly reliable.

[0184] By increasing the temperature during the formation of the insulating layer 107 that functions as a gate insulating layer of the transistor M1, the insulating layer can have fewer defects. However, if the temperature during the formation of the insulating layer 107 is high, oxygen is released from the semiconductor layer 109, and oxygen vacancies (V Ｏ ) and V Ｏ H may increase. The substrate temperature during the formation of the insulating layer 107 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating layer 107 within the above range, defects in the insulating layer 107 can be reduced and oxygen can be prevented from being released from the semiconductor layer 109. Therefore, a highly reliable transistor M1 can be realized, which exhibits favorable electrical characteristics.

[0185] Before forming the insulating layer 107, plasma treatment may be performed on the surface of the semiconductor layer 109. The plasma treatment can reduce impurities such as water adsorbed to the surface of the semiconductor layer 109. Therefore, impurities at the interface between the semiconductor layer 109 and the insulating layer 107 can be reduced, and a highly reliable transistor M1 can be realized. This is particularly suitable when the surface of the semiconductor layer 109 is exposed to the air between the formation of the semiconductor layer 109 and the formation of the insulating layer 107. The plasma treatment can be performed in an atmosphere containing, for example, oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. Furthermore, the plasma treatment and the formation of the insulating layer 107 are preferably performed successively without exposure to the air.

[0186] Next, a conductive film 112f, which will later become the conductive layer 112b (see FIG. 11B), is formed over the insulating layer 107. The conductive film 112f can be formed by a sputtering method using the above-described material, for example.

[0187] Next, a resist mask (not shown) is formed by a photolithography process over the conductive film 112f that does not overlap with a position where the transistor M2 will be formed later, and then the conductive film 112f, the insulating layer 107, and the insulating layer 110 are processed to form an opening 141 (see FIG. 11C ). The opening 141 can be formed by one or both of a wet etching method and a dry etching method. For example, a dry etching method can be suitably used to form the opening 141.

[0188] Next, a resist mask (not shown) is formed by a photolithography process over the conductive film 112f that overlaps with a portion that will later become the gate electrode of the transistor M1, and then the conductive film is processed to form the conductive layer 112b (see FIG. 12A ). The conductive layer 112b can be formed by one or both of a wet etching method and a dry etching method. For example, the wet etching method can be preferably used to form the conductive layer 112b.

[0189] In this way, the transistor M1 is formed.

[0190] Next, a metal oxide film 108f, which will later become the semiconductor layer 108, is formed so as to cover the inner wall of the opening 141 (part of the top surface of the conductive layer 112a, the side surfaces of the insulating layer 110, the side surfaces of the insulating layer 107, and the side surfaces of the conductive layer 112b), the top surface of the conductive layer 112b, and part of the top surface of the insulating layer 107 (see FIG. 12B ). The metal oxide film 108f is preferably formed by sputtering using a metal oxide target.

[0191] Note that the conditions for forming the metal oxide film 108f and the conditions for the heat treatment performed after the formation of the metal oxide film 108f can refer to the conditions for forming the metal oxide film 109f described above and the conditions for the heat treatment performed after the formation of the metal oxide film 109f.

[0192] Next, the metal oxide film 108f is processed into an island shape so as to have a region overlapping the inner wall of the opening 141, thereby forming the semiconductor layer 108 (see FIG. 12C).

[0193] One or both of a wet etching method and a dry etching method can be used to form the semiconductor layer 108. For example, a wet etching method can be suitably used to form the semiconductor layer 108.

[0194] Next, the insulating layer 106, which will later become the gate insulating layer of the transistor M2 (see FIG. 13A ), is formed over the semiconductor layer 108, the conductive layer 112b, and the insulating layer 107. The insulating layer 106 can be formed by, for example, a PECVD method using the above-described material.

[0195] For the conditions for forming the insulating layer 106 and the conditions for the plasma treatment on the semiconductor layer 108 before the insulating layer 106 is formed, the above-mentioned conditions for forming the insulating layer 107 and the conditions for the plasma treatment on the semiconductor layer 109 before the insulating layer 107 can be referred to.

[0196] Next, a conductive film 104f, which will later become the conductive layer 104, is formed over the insulating layer 106 (see FIG. 13B). The conductive film 104f can be formed by, for example, a sputtering method using the above-described material.

[0197] Next, a resist mask (not shown) is formed over the conductive film 104f by a photolithography process so as to have a region overlapping with the opening 141, and then the conductive film is processed to form the conductive layer 104 (see FIG. 13C ). The conductive layer 104 can be formed by one or both of a wet etching method and a dry etching method. For example, the wet etching method can be suitably used to form the conductive layer 104.

[0198] In this way, the transistor M2 is formed.

[0199] Through the above steps, the semiconductor device 10 (FIGS. 1A and 1B) which is one embodiment of the present invention and includes the transistor M1 and the transistor M2 can be manufactured.

[0200] As described above, the semiconductor device of one embodiment of the present invention can be applied to, for example, a pixel circuit of a display device. Below, a structural example of a pixel circuit to which the semiconductor device of one embodiment of the present invention can be applied is described.

[0201] 14A to 14D and 15A to 15D show structural examples of a pixel 230 of a display device to which the semiconductor device of one embodiment of the present invention can be applied. The pixel 230 includes a pixel circuit 51 (a pixel circuit 51A, a pixel circuit 51B, a pixel circuit 51C, or a pixel circuit 51D) and a light-emitting device 61.

[0202] The "light-emitting device" described in the present embodiment and the like refers to a self-luminous display device (also referred to as a display element) such as an organic EL element (also referred to as an OLED (Organic LED)). Note that the light-emitting element electrically connected to the pixel circuit can be a self-luminous light-emitting element such as an LED, a micro LED, a QLED (Quantum-dot LED), or a semiconductor laser.

[0203] A pixel circuit 51A shown in FIG. 14A is a 2Tr1C type pixel circuit having a transistor 52A, a transistor 52B, and a capacitor 53.

[0204] One of the source and drain of the transistor 52A is electrically connected to the wiring SL, and the gate of the transistor 52A is electrically connected to the wiring GL. The other of the source and drain of the transistor 52A is electrically connected to the gate of the transistor 52B. One of the source and drain of the transistor 52B and one terminal of the capacitor 53 are electrically connected to the wiring ANO. The other terminal of the capacitor 53 is electrically connected to the gate of the transistor 52B. The other of the source and drain of the transistor 52B is electrically connected to the anode of the light-emitting device 61. The cathode of the light-emitting device 61 is electrically connected to the wiring VCOM.

[0205] The wiring GL corresponds to the conductive layer 104 of the semiconductor device 10, and the wiring SL corresponds to the conductive layer 112a of the semiconductor device 10. The wiring VCOM is a wiring that applies a potential for supplying a current to the light-emitting device 61. The transistor 52A has a function of controlling the conductive state or non-conductive state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0206] The transistor 52B has a function of controlling the amount of current flowing through the light-emitting device 61. The capacitor 53 has a function of maintaining the gate potential of the transistor 52B. The intensity of light emitted by the light-emitting device 61 is controlled in accordance with an image signal supplied to the gate of the transistor 52B.

[0207] 14A, an n-channel transistor is used as the transistor 52A, and a p-channel transistor is used as the transistor 52B. However, as in the pixel circuit 51A shown in FIG. 14B, an n-channel transistor may be used as the transistor 52B. When an n-channel transistor is used as the transistor 52B, one terminal of the capacitor 53 is electrically connected to the other of the source and drain of the transistor 52B.

[0208] 14B can be used for a pixel circuit 51A. For example, the transistor M2 included in each of the semiconductor devices shown in FIGS. 1A to 2B and 7A and 7B can be used for a transistor 52A included in the pixel circuit 51A, and the transistor M1 included in each of the semiconductor devices shown in FIGS. 1A to 2B and 7A and 7B can be used for a transistor 52B included in the pixel circuit 51A.

[0209] Furthermore, for example, the transistor M1 included in each semiconductor device shown in Figures 3A, 3B, and 7C can be used as the transistor 52A included in the pixel circuit 51A, and the transistor M2 included in each semiconductor device shown in Figures 3A, 3B, and 7C can be used as the transistor 52B included in the pixel circuit 51A.

[0210] When a p-channel transistor is used for the transistor 52B, the circuit configuration of the pixel circuit 51B shown in Fig. 14C may be that of a 3Tr1C pixel circuit having a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. The pixel circuit 51B shown in Fig. 14C has a configuration in which a transistor 52C is added to the pixel circuit 51A shown in Fig. 14A.

[0211] Similarly, when an n-channel transistor is used as the transistor 52B, the circuit configuration of the pixel circuit 51B shown in Fig. 14D may be used. The pixel circuit 51B shown in Fig. 14D has a configuration in which a transistor 52C is added to the pixel circuit 51A shown in Fig. 14B.

[0212] 14C and 14D, one of the source and the drain of a transistor 52C is electrically connected to the other of the source and the drain of the transistor 52B. The other of the source and the drain of the transistor 52C is electrically connected to a wiring V0. For example, a reference potential is supplied to the wiring V0.

[0213] The transistor 52C has a function of controlling conduction or non-conduction between the other of the source and the drain of the transistor 52B and the wiring V0 based on the potential of the wiring GL. The wiring V0 is a wiring for applying a reference potential. When an n-channel transistor is used as the transistor 52B, the reference potential of the wiring V0 applied via the transistor 52C can suppress variations in the gate-source voltage of the transistor 52B.

[0214] Furthermore, the wiring V0 can be used to acquire a current value that can be used to set pixel parameters. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting device 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the outside.

[0215] 14D can be used for a pixel circuit 51B. For example, the transistor M2 included in each of the semiconductor devices shown in FIGS. 1A to 2B and 7A and 7B can be used for a transistor 52A included in the pixel circuit 51B, and the transistor M1 included in each of the semiconductor devices shown in FIGS. 1A to 2B and 7A and 7B can be used for a transistor 52B included in the pixel circuit 51B.

[0216] Furthermore, for example, the transistor M1 included in each semiconductor device shown in Figures 3A, 3B, and 7C can be used as the transistor 52A included in the pixel circuit 51B, and the transistor M2 included in each semiconductor device shown in Figures 3A, 3B, and 7C can be used as the transistor 52B included in the pixel circuit 51B.

[0217] Furthermore, for example, the transistor 52B of the pixel circuit 51B can be the transistor M1 (transistor M2) of each semiconductor device shown in Figures 4A to 6B and Figures 8A to 8C, and the transistor 52C of the pixel circuit 51B can be the transistor M2 (transistor M1) of each semiconductor device shown in Figures 4A to 6B and Figures 8A to 8C.

[0218] 15A has a configuration in which a transistor 52D is added to the pixel circuit 51B shown in Fig. 14C. The pixel circuit 51C shown in Fig. 15A is a 4Tr1C type pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, a transistor 52D, and a capacitor 53.

[0219] One of the source and the drain of the transistor 52D is electrically connected to the wiring ANO, and the other is electrically connected to the other of the source and the drain of the transistor 52A, the other terminal of the capacitor 53, and the gate of the transistor 52B.

[0220] The pixel circuit 51C is electrically connected to a wiring GL1, a wiring GL2, and a wiring GL3. Note that in this embodiment and the like, the wirings GL1, GL2, and GL3 may be collectively referred to as wirings GL. Therefore, the number of wirings GL is not limited to one, and there may be multiple wirings GL.

[0221] The wiring GL1 is electrically connected to the gate of the transistor 52A, the wiring GL2 is electrically connected to the gate of the transistor 52C, and the wiring GL3 is electrically connected to the gate of the transistor 52D.

[0222] By turning on the transistor 52D, the source and gate of the transistor 52B have the same potential, and the transistor 52B can be turned off. This forcibly cuts off the current flowing through the light-emitting device 61. This pixel circuit is suitable for use in a display method in which a display period and an extinction period are alternately provided. The transistor 52C may be turned on at the same time that the transistor 52D is turned on.

[0223] 15A can be used for a pixel circuit 51C. For example, the transistor M1 (or M2) included in each of the semiconductor devices shown in FIGS. 4A to 6B and 8A to 8C can be used for a transistor 52A included in the pixel circuit 51C, and the transistor M2 (or M1) included in each of the semiconductor devices shown in FIGS. 4A to 6B and 8A to 8C can be used for a transistor 52D included in the pixel circuit 51C.

[0224] 15A, n-channel transistors are used as the transistors 52A, 52C, and 52D, and a p-channel transistor is used as the transistor 52B. However, as in the pixel circuit 51C shown in FIG. 15B, an n-channel transistor may be used as the transistor 52B. When an n-channel transistor is used as the transistor 52B, one terminal of the capacitor 53 is electrically connected to the other of the source and drain of the transistor 52B. In addition, one of the source and drain of the transistor 52D is electrically connected to the wiring V0.

[0225] 15B can be used for a pixel circuit 51C. For example, the transistor M1 (or M2) included in each of the semiconductor devices shown in FIGS. 4A to 6B and 8A to 8C can be used for a transistor 52A included in the pixel circuit 51C, and the transistor M2 (or M1) included in each of the semiconductor devices shown in FIGS. 4A to 6B and 8A to 8C can be used for a transistor 52D included in the pixel circuit 51C.

[0226] Furthermore, for example, the transistor 52B of the pixel circuit 51C can be the transistor M1 (transistor M2) of each semiconductor device shown in Figures 4A to 6B and Figures 8A to 8C, and the transistor 52C of the pixel circuit 51C can be the transistor M2 (transistor M1) of each semiconductor device shown in Figures 4A to 6B and Figures 8A to 8C.

[0227] Furthermore, for example, the transistor M2 included in each semiconductor device shown in Figures 1A to 2B and Figures 7A and 7B can be used as the transistor 52A included in the pixel circuit 51C, and the transistor M1 included in each semiconductor device shown in Figures 1A to 2B and Figures 7A and 7B can be used as the transistor 52B included in the pixel circuit 51C.

[0228] Furthermore, for example, the transistor 52A of the pixel circuit 51C can be the transistor M1 of each semiconductor device shown in Figures 3A, 3B, and 7C, and the transistor 52B of the pixel circuit 51C can be the transistor M2 of each semiconductor device shown in Figures 3A, 3B, and 7C.

[0229] Furthermore, for example, the transistor M2 included in each semiconductor device shown in Figures 1A to 2B and Figures 7A and 7B can be used as the transistor 52D included in the pixel circuit 51C, and the transistor M1 included in each semiconductor device shown in Figures 1A to 2B and Figures 7A and 7B can be used as the transistor 52B included in the pixel circuit 51C.

[0230] Furthermore, for example, the transistor 52D of the pixel circuit 51C can be the transistor M1 of each semiconductor device shown in Figures 3A and 3B and Figure 7C, and the transistor 52B of the pixel circuit 51C can be the transistor M2 of each semiconductor device shown in Figures 3A and 3B and Figure 7C.

[0231] A pixel circuit 51D shown in Fig. 15C has a configuration in which a capacitor 53A is added to the pixel circuit 51C shown in Fig. 15A. In the pixel circuit 51D shown in Fig. 15C, one terminal of the capacitor 53A is electrically connected to the other of the source and drain terminals of the transistor 52B, and the other terminal is electrically connected to the gate of the transistor 52B.

[0232] 15C can be used for a pixel circuit 51D. For example, the transistor M1 (or M2) included in each of the semiconductor devices shown in FIGS. 4A to 6B and 8A to 8C can be used for the transistor 52A included in the pixel circuit 51D, and the transistor M2 (or M1) included in each of the semiconductor devices shown in FIGS. 4A to 6B and 8A to 8C can be used for the transistor 52D included in the pixel circuit 51D.

[0233] The pixel circuit 51D shown in Fig. 15D has a configuration in which a capacitor 53A is added to the pixel circuit 51C shown in Fig. 15B. In the pixel circuit 51D shown in Fig. 15D, one terminal of the capacitor 53A is electrically connected to the wiring ANO, and the other terminal is electrically connected to the gate of the transistor 52B. The capacitor 53A and the capacitor 53A each function as a storage capacitor. The pixel circuit 51D shown in Figs. 15C and 15D is a 4Tr2C type pixel circuit.

[0234] 15D can be a pixel circuit 51D including a semiconductor device of one embodiment of the present invention. For example, the transistor M1 (or the transistor M2) included in each of the semiconductor devices shown in FIGS. 4A to 6B and 8A to 8C can be used as the transistor 52A included in the pixel circuit 51D, and the transistor M2 (or the transistor M1) included in each of the semiconductor devices shown in FIGS. 4A to 6B and 8A to 8C can be used as the transistor 52D included in the pixel circuit 51D.

[0235] Furthermore, for example, the transistor 52B of the pixel circuit 51D can be the transistor M1 (transistor M2) of each semiconductor device shown in Figures 4A to 6B and Figures 8A to 8C, and the transistor 52C of the pixel circuit 51D can be the transistor M2 (transistor M1) of each semiconductor device shown in Figures 4A to 6B and Figures 8A to 8C.

[0236] Furthermore, for example, the transistor 52A in the pixel circuit 51D can be the transistor M2 in each semiconductor device shown in Figures 1A to 2B and Figures 7A and 7B, and the transistor 52B in the pixel circuit 51D can be the transistor M1 in each semiconductor device shown in Figures 1A to 2B and Figures 7A and 7B.

[0237] Furthermore, for example, the transistor 52A in the pixel circuit 51D can be the transistor M1 in each semiconductor device shown in Figures 3A, 3B, and 7C, and the transistor 52B in the pixel circuit 51D can be the transistor M2 in each semiconductor device shown in Figures 3A, 3B, and 7C.

[0238] Furthermore, for example, the transistor M2 included in each semiconductor device shown in Figures 1A to 2B and Figures 7A and 7B can be used as the transistor 52D included in the pixel circuit 51D, and the transistor M1 included in each semiconductor device shown in Figures 1A to 2B and Figures 7A and 7B can be used as the transistor 52B included in the pixel circuit 51D.

[0239] Furthermore, for example, the transistor 52D of the pixel circuit 51D can be the transistor M1 of each semiconductor device shown in Figures 3A, 3B, and 7C, and the transistor 52B of the pixel circuit 51D can be the transistor M2 of each semiconductor device shown in Figures 3A, 3B, and 7C.

[0240] It is preferable that each of the transistors 52A, 52B, 52C, and 52D has a back gate electrode (second gate electrode). In this case, the back gate electrode can be configured to receive the same signal as the gate electrode, or a signal different from the gate electrode can be received by the back gate electrode.

[0241] Not only the transistor 52B, but also the transistors 52A, 52C, and 52D may be p-channel transistors.

[0242] As described above, the semiconductor device of one embodiment of the present invention can be applied to a pixel circuit of a display device. Since the semiconductor device of one embodiment of the present invention has transistors arranged at high density and can be highly integrated, a display device in which the semiconductor device is used as a pixel circuit can achieve high definition.

[0243] This embodiment mode can be combined with other embodiment modes or examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0244] Embodiment 2 In this embodiment, a display device to which a semiconductor device of one embodiment of the present invention is applied will be described.

[0245] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type device for AR.

[0246] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used in electronic devices having relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0247] <Display Device 200A> FIG. 16 shows a perspective view of the display device 200A.

[0248] The display device 200A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 16, the substrate 152 is clearly indicated by a dashed line.

[0249] The display device 200A includes a display unit 162, a connection unit 140, a circuit 164, wiring 165, etc. Fig. 16 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 200A. Therefore, the configuration shown in Fig. 16 can also be said to be a display module including the display device 200A, an IC (integrated circuit), and an FPC.

[0250] The display unit 162 has a plurality of pixels arranged in a matrix, each of which has a plurality of sub-pixels.

[0251] Each subpixel has a display device. Examples of the display device include a liquid crystal device (also referred to as a liquid crystal element) and a light-emitting device. It is preferable to use, for example, an OLED or a QLED as the light-emitting device. Examples of the light-emitting material included in the light-emitting device include a fluorescent material (fluorescent material), a phosphorescent material (phosphorescent material), a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material), and an inorganic compound (such as a quantum dot material). Furthermore, an LED such as a micro LED can also be used as the light-emitting device.

[0252] The light emitting device can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light emitting device with a microcavity structure.

[0253] In the following, a configuration in which a light-emitting device is used as a display device will be described as an example.

[0254] A display device according to one embodiment of the present invention includes light-emitting devices each manufactured for a different light-emitting color and is capable of full-color display.

[0255] The display device of one embodiment of the present invention may be any of a top emission type that emits light in a direction opposite to a substrate on which a light-emitting device is formed, a bottom emission type that emits light toward a substrate on which a light-emitting device is formed, and a dual emission type that emits light from both sides.

[0256] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided, for example, along one or more sides of the display portion 162. The planar shape of the connection portion 140 is not particularly limited, and can be strip-shaped, L-shaped, U-shaped, frame-shaped, or the like. The connection portion 140 may be singular or plural. FIG. 16 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 electrically connects the common electrode of the light-emitting device and the conductive layer, and can supply a potential to the common electrode. The connection portion 140 can also be called a cathode contact portion.

[0257] The circuit 164 can be, for example, a scanning line driver circuit.

[0258] The wiring 165 has a function of supplying signals and power to the display portion 162 and the circuit 164. The signals and power are input to the wiring 165 from the outside via the FPC 172 or input to the wiring 165 from the IC 173.

[0259] 16 shows an example in which an IC 173 is provided on a substrate 151 by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like. For example, an IC having a scanning line driver circuit or a signal line driver circuit can be used as the IC 173. The display device 200A and the display module may not necessarily include an IC. Alternatively, the IC may be mounted on an FPC by a COF method or the like.

[0260] Figure 17 shows an example of a cross section of the display device 200A, obtained by cutting a portion of the area including the FPC 172, a portion of the circuit 164, a portion of the display unit 162, a portion of the connection unit 140, and a portion of the area including the end portion.

[0261] The display device 200A shown in Figure 17 has, between the substrate 151 and the substrate 152, a transistor 201, a transistor 205R (not shown), a transistor 205G, a transistor 205B, a transistor 206R (not shown), a transistor 206G, a transistor 206B (not shown), a light-emitting device 130R (not shown), a light-emitting device 130G, and a light-emitting device 130B, etc.

[0262] The transistor 201, the transistor 205R, the transistor 205G, the transistor 205B, the transistor 206R, the transistor 206G, and the transistor 206B are provided over the substrate 151. An insulating layer 218 and an insulating layer 235 on the insulating layer 218 are provided to cover the transistor 201, the transistor 205R, the transistor 205G, the transistor 205B, the transistor 206R, the transistor 206G, and the transistor 206B. The light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B are provided over the insulating layer 235.

[0263] When describing matters common to light-emitting device 130R, light-emitting device 130G, and light-emitting device 130B, the letters that distinguish them may be omitted and they may be referred to as light-emitting device 130. Similarly, when describing matters common to components that are distinguished by letters, such as transistor 205R, transistor 205G, and transistor 205B, they may be described using symbols without the letters.

[0264] The transistor 201, the transistor 205R, the transistor 205G, the transistor 205B, the transistor 206R, the transistor 206G, and the transistor 206B are all formed over a substrate 151. The transistor 201, the transistor 205R, the transistor 205G, and the transistor 205B can be manufactured using the same material and the same process. The transistor 206R, the transistor 206G, and the transistor 206B can be manufactured using the same material and the same process. Note that although FIG. 17 shows an example in which the transistor 201 has the same structure as the transistor 205 (the transistor 205R, the transistor 205G, and the transistor 205B), this is not limiting. The transistor 201 may have the same structure as the transistor 206 (the transistor 206R, the transistor 206G, and the transistor 206B).

[0265] The transistors described in Embodiment 1 can be suitably used for the transistor 201, the transistor 205R, the transistor 205G, the transistor 205B, the transistor 206R, the transistor 206G, and the transistor 206B. In FIG. 17, the transistor M2 in the semiconductor device 10 shown in FIGS. 1A and 1B is used for the transistor 201, the transistor 205R, the transistor 205G, and the transistor 205B. In addition, the transistor M1 in the semiconductor device 10 shown in FIGS. 1A and 1B is used for the transistor 206R, the transistor 206G, and the transistor 206B.

[0266] That is, it can be said that the transistors 205R and 206R constitute a semiconductor device in a subpixel that emits red (R) light, the transistors 205G and 206G constitute a semiconductor device in a subpixel that emits green (G) light, and the transistors 205B and 206B constitute a semiconductor device in a subpixel that emits blue (B) light. Note that FIG. 17 illustrates an example in which the insulating layer 110 has a three-layer structure including an insulating layer 110c, an insulating layer 110a, and an insulating layer 110b. By using the transistor described in Embodiment 1 for the display portion 162, a high-resolution display device can be obtained. Furthermore, by using the transistor described in Embodiment 1 for the circuit 164, a display device with a narrow frame can be obtained.

[0267] All the transistors included in the display portion 162 may be OS transistors, all the transistors included in the display portion 162 may be Si transistors, or some of the transistors included in the display portion 162 may be OS transistors and the rest may be Si transistors. Transistors using LTPS (hereinafter referred to as LTPS transistors) may be used as Si transistors.

[0268] For example, by using both an LTPS transistor and an OS transistor in the display portion 162, a display device with low power consumption and high driving capability can be realized. A structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. For example, it is preferable to use an OS transistor as a transistor that functions as a switch for controlling conduction / non-conduction between wirings and an LTPS transistor as a transistor for controlling current.

[0269] For example, one of the transistors (transistor 206) included in the display portion 162 functions as a transistor for controlling a current flowing through a light-emitting device and can also be called a driving transistor. One of the source and drain of the driving transistor is electrically connected to a pixel electrode of the light-emitting device. An LTPS transistor is preferably used as the driving transistor. This allows a large current to flow through the light-emitting device in the pixel circuit. Meanwhile, the other transistor (transistor 205) included in the display portion 162 functions as a switch for controlling pixel selection and non-selection and can also be called a selection transistor. The gate of the selection transistor is electrically connected to a gate line, and one of the source and drain is electrically connected to a source line (signal line). An OS transistor is preferably used as the selection transistor. This allows the grayscale of a pixel to be maintained even when the frame frequency is significantly reduced (for example, 1 fps or less). Therefore, power consumption can be reduced by stopping the driver when displaying a still image.

[0270] Each of the light-emitting devices 130R, 130G, and 130B has a pair of electrodes and a layer sandwiched between the pair of electrodes. The layer has at least a light-emitting layer. Of the pair of electrodes that each light-emitting device has, one electrode functions as an anode and the other electrode functions as a cathode. In the following, an example in which the pixel electrode functions as the anode and the common electrode functions as the cathode may be described.

[0271] The light-emitting device 130R has a pixel electrode 111R on an insulating layer 235, an island-shaped layer 113R (not shown) on the pixel electrode 111R, and a common electrode 115 on the island-shaped layer 113R.

[0272] The light-emitting device 130G has a pixel electrode 111G on an insulating layer 235, an island-shaped layer 113G on the pixel electrode 111G, and a common electrode 115 on the island-shaped layer 113G.

[0273] The light-emitting device 130B has a pixel electrode 111B on an insulating layer 235, an island-shaped layer 113B on the pixel electrode 111B, and a common electrode 115 on the island-shaped layer 113B.

[0274] Each of the layers 113R, 113G, and 113B includes at least a light-emitting layer. For example, the light-emitting device 130R may emit red (R) light, the light-emitting device 130G may emit green (G) light, and the light-emitting device 130B may emit blue (B) light. The layer 113R includes a light-emitting layer that emits red light, the layer 113G includes a light-emitting layer that emits green light, and the layer 113B includes a light-emitting layer that emits blue light. In other words, the layer 113R includes a light-emitting material that emits red light, the layer 113G includes a light-emitting material that emits green light, and the layer 113B includes a light-emitting material that emits blue light. The layer 113R, 113G, and 113B may each include one or more functional layers. Examples of the functional layers include a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer).

[0275] 17, layers 113R, 113G, and 113B are all shown with the same thickness, but the present invention is not limited to this. The thicknesses of layers 113R, 113G, and 113B may be different. For example, it is preferable to set the thicknesses of layers 113R, 113G, and 113B in accordance with the optical path length that enhances the light emitted by each of layers 113R, 113G, and 113B. This allows for a microcavity structure to be realized, and the color purity of the light emitted from each light-emitting device 130 to be improved.

[0276] The layers 113R, 113G, and 113B can each be formed by, for example, a vacuum deposition method using a fine metal mask. When using a vacuum deposition method using a fine metal mask, the layers 113R, 113G, and 113B can be formed over an area wider than the openings in the fine metal mask. The edges of the layers 113R, 113G, and 113B each have a tapered shape. The layers 113R, 113G, and 113B may also be formed by a sputtering method using a fine metal mask or an inkjet method.

[0277] The light-emitting device of the present embodiment may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer.

[0278] When a light-emitting device with a tandem structure is used, it is preferable that the layer 113R has a structure having a plurality of light-emitting units that emit red light, the layer 113G has a structure having a plurality of light-emitting units that emit green light, and the layer 113B has a structure having a plurality of light-emitting units that emit blue light. It is preferable to provide a charge generation layer (also called an intermediate layer) between each light-emitting unit.

[0279] The common electrode 115 is shared by the light-emitting devices 130R, 130G, and 130B. The common electrode 115 is electrically connected to a conductive layer 123 provided in the connection portion 140. The conductive layer 123 is preferably formed of the same material and in the same process as the pixel electrodes 111R, 111G, and 111B. It is preferable that the layers 113R, 113G, and 113B are not formed on the conductive layer 123.

[0280] In the connection portion 140, a common electrode 115 is provided on the conductive layer 123. The common electrode 115 can be formed by, for example, sputtering or vacuum evaporation. Alternatively, a film formed by evaporation and a film formed by sputtering may be stacked. When forming the common electrode 115, a mask (also called an area mask or a rough metal mask, to distinguish it from a fine metal mask) may be used to define the region where the common electrode 115 is to be formed.

[0281] The insulating layer 218 provided over the transistor 205R, the transistor 205G, the transistor 205B, the transistor 206R, the transistor 206G, and the transistor 206B functions as a protective layer for the transistor 205R, the transistor 205G, the transistor 205B, the transistor 206R, the transistor 206G, and the transistor 206B. The insulating layer 218 is preferably formed using a material through which impurities are less likely to diffuse. The insulating layer 218 functions as a blocking film that prevents impurities from diffusing from the outside into the transistor. Examples of impurities include water and hydrogen. Providing the insulating layer 218 can improve the reliability of the display device.

[0282] The insulating layer 218 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. An inorganic material can be suitably used for the insulating layer 218. Examples of inorganic materials include one or more of oxide, oxynitride, nitride oxide, and nitride. More specifically, examples of materials that can be used include one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate. For example, silicon nitride oxide is suitable for use as the insulating layer 218 because it releases little impurities (e.g., water and hydrogen) from itself and can function as a blocking film that suppresses impurity diffusion from above the transistor to the transistor. Examples of organic materials that can be used include one or more of acrylic resin and polyimide resin. A photosensitive material may also be used as the organic material. Two or more of the above insulating films may be stacked. The insulating layer 218 may have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0283] By increasing the temperature during the formation of the insulating film that becomes the insulating layer 218, the blocking property of impurities (for example, water and hydrogen) can be improved. However, when an oxide semiconductor is used for the semiconductor layers 108 and 109 that function as semiconductor layers in which the channels of the transistors 205 and 206 are formed, if the temperature during the formation of the insulating film is high, oxygen is released from the semiconductor layers 108 and 109, resulting in oxygen vacancies (V Ｏ ) and V ＯH may increase. The substrate temperature during the formation of the insulating film is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating film within the above range, the impurity blocking ability of the insulating layer 218 can be improved and oxygen can be prevented from being released from the semiconductor layers 108 and 109. Therefore, the transistors 205 and 206 exhibiting favorable electrical characteristics and high reliability can be realized.

[0284] The insulating layer 235 has a function of reducing unevenness caused by the transistor 205R, the transistor 205G, the transistor 205B, the transistor 206R, the transistor 206G, and the transistor 206B and making the surface on which the light-emitting device 130 is formed more flat. Note that in this specification and the like, the insulating layer 235 may be referred to as a planarizing layer.

[0285] An organic material can be suitably used for the insulating layer 235. As the organic material, it is preferable to use a photosensitive organic resin, for example, a photosensitive resin composition containing an acrylic resin. Note that in this specification and the like, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0286] The insulating layer 235 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, or precursors of these resins. Alternatively, the insulating layer 235 may be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. Alternatively, a photoresist may be used as the photosensitive resin. Either a positive-type material or a negative-type material may be used as the photosensitive organic resin.

[0287] The insulating layer 235 may have a laminated structure of an organic insulating layer and an inorganic insulating layer. For example, the insulating layer 235 may have a laminated structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer. By providing an inorganic insulating layer on the outermost surface of the insulating layer 235, it can function as an etching protection layer. This makes it possible to prevent a portion of the insulating layer 235 from being etched when forming the pixel electrode 111, thereby preventing the insulating layer 235 from becoming less flat.

[0288] If the top surface of the insulating layer 235, on which the light-emitting device 130 is formed, is not flat, problems such as poor connection due to step disconnection of the common electrode 115 or an increase in electrical resistance due to a localized thinning of the film thickness of the common electrode 115 may occur. Furthermore, if the top surface of the insulating layer 235 is not flat, the processing accuracy of layers formed on the insulating layer 235 may be reduced. By flattening the top surface of the insulating layer 235, the processing accuracy of the light-emitting device 130 and the like provided on the insulating layer 235 can be improved, resulting in a display device with high resolution. Furthermore, it is possible to prevent poor connection due to step disconnection of the common electrode 115 and an increase in electrical resistance due to a localized thinning of the film thickness of the common electrode 115, thereby resulting in a display device with high display quality.

[0289] When forming the pixel electrodes 111R, 111G, and 111B, a part of the insulating layer 235 may be removed. The insulating layer 235 may have a recess in a region that does not overlap with any of the pixel electrodes 111R, 111G, and 111B.

[0290] Note that the structure of a pixel electrode that can be applied to the display device that is one embodiment of the present invention is not limited to the structure of the pixel electrode 111 shown in FIG. 17 and the like.

[0291] The insulating layer 237 covers the upper end portions of the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B. The insulating layer 237 functions as a partition wall (also referred to as a bank or spacer). The insulating layer 237 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. The insulating layer 237 can be made of a material that can be used for the insulating layer 218 or the insulating layer 235. The insulating layer 237 may have a stacked structure of an inorganic insulating layer and an organic insulating layer.

[0292] By providing the insulating layer 237, it is possible to prevent the pixel electrode 111 and the common electrode 115 from coming into contact with each other, thereby preventing the light-emitting device 130 from shorting out. The end of the insulating layer 237 is preferably tapered. By tapering the end of the insulating layer 237, it is possible to improve the coverage of a film to be formed later. In particular, it is preferable to use a photosensitive material as an organic insulating layer for the insulating layer 237, because this makes it easy to control the shape of the end by adjusting the exposure and development conditions. Note that an inorganic insulating layer may be used for the insulating layer 237. By using an inorganic insulating layer for the insulating layer 237, a high-definition display device can be achieved.

[0293] When a photosensitive organic material is used for the film that becomes the insulating layer 237, the insulating layer 237 can be formed by applying a composition containing the organic material by spin coating, followed by selective exposure and development. When a photosensitive organic material is used for the film that becomes the insulating layer 237, a positive-type photosensitive resin or a negative-type photosensitive resin may be used. The light used for exposure preferably includes i-line. The light used for exposure may also include at least one of g-line and h-line. The width of the opening can be controlled by adjusting the exposure dose. Other formation methods that may be used include one or more of sputtering, vapor deposition, droplet discharge (inkjet), screen printing, and offset printing.

[0294] Recesses are formed in the pixel electrodes 111R, 111G, and 111B so as to cover the openings of the insulating layers 107, 106, 218, and 235. An insulating layer 237 is embedded in the recesses. For example, after forming the insulating layer 237 that covers the upper surface end of the pixel electrode 111 and the openings, the island-shaped layers 113R, 113G, and 113B can be formed using a fine metal mask.

[0295] The layer 113R, the layer 113G, and the layer 113B may be provided over the insulating layer 237. Note that although FIG. 17 illustrates a structure in which adjacent layers 113 are not in contact with each other, one embodiment of the present invention is not limited to this. The adjacent layers 113 may be in contact with each other over the insulating layer 237. The adjacent layers 113 may overlap with each other over the insulating layer 237. For example, the layer 113R and the layer 113G may be in contact with each other or may overlap with each other over the insulating layer 237.

[0296] The insulating layer 237 can also be applied to other configuration examples.

[0297] A protective layer 131 is provided on the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light-emitting devices. In FIG. 17 , the space between the substrate 152 and the substrate 151 is filled with the adhesive layer 142, thereby applying a solid sealing structure. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), thereby applying a hollow sealing structure. In this case, the adhesive layer 142 may be provided so as not to overlap with the light-emitting device. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 142.

[0298] It is preferable to provide a protective layer 131 on the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B. By providing the protective layer 131, it is possible to prevent the common electrode 115 from being oxidized and to prevent impurities (such as water and oxygen) from entering the light-emitting device. This prevents deterioration of the light-emitting device and improves the reliability of the display device. The protective layer 131 may have a single-layer structure or a laminated structure of two or more layers. The conductivity of the protective layer 131 is not important. The protective layer 131 can be at least one of an insulating layer, a semiconductor layer, and a conductive layer.

[0299] The protective layer 131 can be made of an inorganic material. For example, the protective layer 131 can be made of one or more of an oxide, an oxynitride, a nitride oxide, or a nitride. Specific examples include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, and hafnium oxide. In particular, the protective layer 131 preferably contains a nitride or a nitride oxide, and more preferably contains a nitride.

[0300] The protective layer 131 may be a layer containing In—Sn oxide (ITO), In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, or In—Ga—Zn oxide (IGZO). The layer preferably has high resistance, specifically, a higher resistance than the common electrode 115. The layer may further contain nitrogen.

[0301] When light emitted from the light-emitting device is extracted through the protective layer 131, it is preferable that the protective layer 131 have high transparency to visible light. For example, In—Sn oxide, In—Ga—Zn oxide, and aluminum oxide are preferable because they each have high transparency to visible light.

[0302] Furthermore, the protective layer 131 may include an organic film. For example, the protective layer 131 may include both an organic film and an inorganic film.

[0303] Examples of a method for forming the protective layer 131 include a vacuum deposition method, a sputtering method, a CVD method, and an ALD method. The protective layer 131 may have a laminated structure formed using different film formation methods.

[0304] The protective layer 131 is provided at least on the display unit 162, and is preferably provided so as to cover the entire display unit 162. The protective layer 131 is preferably provided so as to cover not only the display unit 162 but also the connection unit 140 and the circuit 164. Furthermore, the protective layer 131 is preferably provided up to the edge of the display device 200A.

[0305] A connection portion 204 is provided in a region of the substrate 151 that does not overlap with the substrate 152. In the connection portion 204, the wiring 165 is electrically connected to the FPC 172 via a conductive layer 166 and a connection layer 242. The conductive layer 166 can be formed in the same process as the pixel electrodes 111R, 111G, and 111B. The conductive layer 166 is exposed on the top surface of the connection portion 204. This allows the connection portion 204 and the FPC 172 to be electrically connected via the connection layer 242.

[0306] The connection layer 242 may be formed using, for example, an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP).

[0307] Note that the connecting portion 204 has a portion where the protective layer 131 is not provided in order to electrically connect the FPC 172 and the conductive layer 166. For example, after the protective layer 131 is formed on the entire surface of the display device 200A, a mask is used to remove a region of the protective layer 131 that overlaps with the conductive layer 166, thereby exposing the conductive layer 166.

[0308] A laminated structure of at least one organic layer and a conductive layer may be provided on the conductive layer 166, and the protective layer 131 may be provided on the laminated structure. A peeling starting point (a portion that triggers peeling) may then be formed on the laminated structure using a laser or a sharp blade (e.g., a needle or cutter), selectively removing the laminated structure and the protective layer 131 thereon to expose the conductive layer 166. For example, the protective layer 131 can be selectively removed by pressing an adhesive roller against the substrate 151 and moving the roller relative to the substrate while rotating. Alternatively, adhesive tape may be attached to the substrate 151 and peeled off. Because of poor adhesion between the organic layer and the conductive layer, or between the organic layers themselves, separation occurs at the interface between the organic layer and the conductive layer or within the organic layer. This allows selective removal of the region of the protective layer 131 that overlaps with the conductive layer 166. If an organic layer or the like remains on the conductive layer 166, it can be removed using an organic solvent or the like.

[0309] The organic layer can be, for example, at least one organic layer (a layer functioning as a light-emitting layer, a carrier blocking layer, a carrier transport layer, or a carrier injection layer) used in any of the layers 113B, 113G, and 113R. The organic layer can be formed when any of the layers 113B, 113G, and 113R is formed, or can be provided separately. The conductive layer can be formed in the same process and with the same material as the common electrode 115. For example, it is preferable to form an ITO film as the common electrode 115 and the conductive layer. Note that when a stacked structure is used for the common electrode 115, at least one of the layers constituting the common electrode 115 is provided as the conductive layer.

[0310] The top surface of the conductive layer 166 may be covered with a mask so that the protective layer 131 is not formed on the conductive layer 166. The mask may be, for example, a metal mask (area metal mask), or a tape or film having adhesive or adsorption properties. The protective layer 131 is formed with the mask in place, and then the mask is removed, so that the conductive layer 166 can remain exposed even after the protective layer 131 is formed.

[0311] Using this method, an area in the connection portion 204 where the protective layer 131 is not provided can be formed, and in this area, the conductive layer 166 and the FPC 172 can be electrically connected via the connection layer 242.

[0312] In the connection portion 140, the conductive layer 123 is provided on the insulating layer 235. The end portion of the conductive layer 123 is covered with an insulating layer 237. In addition, the common electrode 115 is provided on the conductive layer 123.

[0313] The display device 200A shown in Fig. 17 is a top-emission type. Light emitted by the light-emitting devices is emitted toward the substrate 152. The substrate 152 is preferably made of a material that is highly transparent to visible light. The pixel electrode 111 includes a material that reflects visible light, and the common electrode 115 includes a material that transmits visible light. In Fig. 17, light G and light B emitted toward the substrate 152 from the light-emitting device 130G and the light-emitting device 130B are respectively indicated by dashed arrows.

[0314] A light-shielding layer 117 is preferably provided on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting devices, in the connection portion 140, and in the circuit 164. By providing the light-shielding layer 117, light emitted from adjacent subpixels can be blocked, thereby preventing color mixing. Furthermore, external light can be prevented from reaching the transistor 201, the transistor 205R, the transistor 205G, the transistor 205B, the transistor 206R, the transistor 206G, and the transistor 206B, thereby preventing deterioration of the transistor 201, the transistor 205R, the transistor 205G, the transistor 205B, the transistor 206R, the transistor 206G, and the transistor 206B due to the external light. Note that a configuration without providing the light-shielding layer 117 is also possible.

[0315] Various optical members can be disposed on the outside of the substrate 152. Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (e.g., a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be disposed on the outside of the substrate 152. For example, the surface protection layer may be a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ ), polyester-based materials, or polycarbonate-based materials may also be used. Note that it is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0316] The substrate 151 and the substrate 152 can be made of the same material as that used for the substrate 102 shown in FIG. 1B etc. The substrate on the side from which light from the light-emitting device is extracted is made of a material that transmits the light. A polarizing plate may also be used as the substrate on the side from which light from the light-emitting device is extracted.

[0317] The flexibility of the display device can be increased by using a flexible material for the substrates 151 and 152. For the substrates 151 and 152, for example, polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, or cellulose nanofiber can be used. For the substrates 151 and 152, glass having a thickness sufficient to provide flexibility can also be used.

[0318] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has small birefringence (or a small amount of birefringence).

[0319] The absolute value of the retardation (phase difference) of a substrate having high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0320] Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0321] When a film is used as a substrate, the film may absorb water, which may cause changes in shape, such as wrinkles, in the display device. Therefore, it is preferable to use a film with low water absorption as the substrate. For example, it is preferable to use a film with a water absorption rate of 1% or less, more preferably 0.1% or less, and even more preferably 0.01% or less.

[0322] The adhesive layer 142 may be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Materials with low moisture permeability, such as epoxy resin, are particularly preferred. Two-component resins may also be used. Adhesive sheets or the like may also be used.

[0323] The following describes examples of configurations different from the display device described above. Note that descriptions of parts that overlap with the display device described above may be omitted. Also, in the drawings shown below, parts that have the same functions as the display device described above may be marked with the same hatching pattern and may not be assigned reference numerals.

[0324] Display Device 200B A display device 200B shown in FIG. 18 differs from the display device 200A shown in FIG. 17 mainly in that the configurations of the light-emitting devices 130R (not shown), 130G, and 130B are different.

[0325] The light-emitting device 130R has a layer 113W instead of the layer 113R. The light-emitting device 130G has a layer 113W instead of the layer 113G. The light-emitting device 130B has a layer 113W instead of the layer 113B. The layer 113W can be configured to emit, for example, white light. The layer 113W can be formed by, for example, vacuum deposition or sputtering. The layer 113W can be shared by the light-emitting devices 130R, 130G, and 130B. By sharing the layer 113W among multiple light-emitting devices 130, the layer 113W can be formed without using a fine metal mask. The layer 113W is provided in the display unit 162. The layer 113W can be formed by, for example, an area mask.

[0326] An optical adjustment layer (not shown) may be provided between the pixel electrode 111 and the layer 113. A conductive layer that is transparent to visible light may be used as the optical adjustment layer. The thickness of the optical adjustment layer may be different for each of the light-emitting devices 130R, 130G, and 130B. By adjusting the thickness of the optical adjustment layer to obtain an optimal optical path length, it is possible to obtain light with a desired wavelength that is intensified from the light-emitting device 130, even when the layer 113W that emits white light is used.

[0327] A coloring layer 132R (not shown) that transmits red light, a coloring layer 132G that transmits green light, and a coloring layer 132B that transmits blue light may be provided on the surface of the substrate 152 facing the adhesive layer 142. The coloring layer 132R is provided in a region overlapping the light-emitting device 130R. The coloring layer 132G is provided in a region overlapping the light-emitting device 130G. The coloring layer 132B is provided in a region overlapping the light-emitting device 130B. For example, the coloring layer 132R can block light of unnecessary wavelengths emitted from the red light-emitting device 130R. This configuration can improve the color purity of the light emitted from each light-emitting device. Note that the combination of the light-emitting device 130G and the coloring layer 132G and the combination of the light-emitting device 130B and the coloring layer 132B each provide similar effects.

[0328] The colored layer 132R, the colored layer 132G, and the colored layer 132B can also be applied to other configuration examples.

[0329] <Display device 200C> The display device 200C shown in FIG. 19 differs from the display device 200A shown in FIG. 17 mainly in that the pixel electrode 111R (not shown), the pixel electrode 111G, the pixel electrode 111B, the conductive layer 123, and the conductive layer 166 have different configurations, that the display device 200C does not have the insulating layer 237, that the layer 113 covers the top and side surfaces of the pixel electrode 111, and that the display device 200C has the common layer 114, the insulating layer 125, and the insulating layer 127.

[0330] Light-emitting device 130R (not shown) has pixel electrode 111R on insulating layer 235, island-shaped layer 113R on pixel electrode 111R, common layer 114 on island-shaped layer 113R, and common electrode 115 on common layer 114. In light-emitting device 130R, layer 113R and common layer 114 can be collectively referred to as an EL layer.

[0331] The light-emitting device 130G has a pixel electrode 111G on an insulating layer 235, an island-shaped layer 113G on the pixel electrode 111G, a common layer 114 on the island-shaped layer 113G, and a common electrode 115 on the common layer 114. In the light-emitting device 130G, the layer 113G and the common layer 114 can be collectively referred to as an EL layer.

[0332] Light-emitting device 130B has pixel electrode 111B on insulating layer 235, island layer 113B on pixel electrode 111B, common layer 114 on island layer 113B, and common electrode 115 on common layer 114. In light-emitting device 130B, layer 113B and common layer 114 can be collectively referred to as an EL layer.

[0333] In this specification and the like, among the EL layers included in the light-emitting devices, layers provided in an island shape for each light-emitting device are referred to as layer 113R, layer 113G, or layer 113B, and a layer shared by a plurality of light-emitting devices is referred to as common layer 114. Note that in this specification and the like, the layer 113R, layer 113G, and layer 113B may be referred to as an island-shaped EL layer, an EL layer formed in an island shape, or the like, without including the common layer 114.

[0334] For example, each of the layers 113R, 113G, and 113B may have a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer in this order. Alternatively, an electron blocking layer may be provided between the hole transport layer and the light-emitting layer. Alternatively, a hole blocking layer may be provided between the electron transport layer and the light-emitting layer. Alternatively, an electron injection layer may be provided on the electron transport layer.

[0335] For example, each of the layers 113R, 113G, and 113B may have an electron injection layer, an electron transport layer, an emitting layer, and a hole transport layer in this order. Alternatively, a hole blocking layer may be provided between the electron transport layer and the emitting layer. Alternatively, an electron blocking layer may be provided between the hole transport layer and the emitting layer. Alternatively, a hole injection layer may be provided on the hole transport layer.

[0336] As described above, the layers 113R, 113G, and 113B each preferably have a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Alternatively, the layers 113R, 113G, and 113B each preferably have a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer. Alternatively, the layers 113R, 113G, and 113B each preferably have a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer.

[0337] A tandem structure may be applied to light-emitting device 130R, light-emitting device 130G, and light-emitting device 130G. When a tandem structure is applied, layer 113R preferably has a structure including multiple light-emitting units that emit red light, layer 113G preferably has a structure including multiple light-emitting units that emit green light, and layer 113B preferably has a structure including multiple light-emitting units that emit blue light. A charge generation layer is preferably provided between each of the light-emitting units. Layer 113R, layer 113G, and layer 113B may each include, for example, a first light-emitting unit, a charge generation layer on the first light-emitting unit, and a second light-emitting unit on the charge generation layer.

[0338] The second light-emitting unit preferably has an emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the emitting layer. Alternatively, the second light-emitting unit preferably has an emitting layer and a carrier block layer (hole block layer or electron block layer) on the emitting layer. Alternatively, the second light-emitting unit preferably has an emitting layer, a carrier block layer on the emitting layer, and a carrier transport layer on the carrier block layer. Since the surface of the second light-emitting unit is exposed during the manufacturing process of the display device, providing one or both of a carrier transport layer and a carrier block layer on the emitting layer can prevent the emitting layer from being exposed to the outermost surface and reduce damage to the emitting layer. This can improve the reliability of the light-emitting device. Note that when three or more emitting units are included, the uppermost emitting unit preferably has an emitting layer and one or both of a carrier transport layer and a carrier block layer on the emitting layer.

[0339] The common layer 114 includes, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The common layer 114 is shared by the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B. The common layer 114 can be formed by, for example, a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0340] The common layer 114 does not have to be provided in the connection portion 140. Fig. 19 shows a configuration in which the common electrode 115 is provided directly on the conductive layer 123. Note that the common layer 114 may be provided on the conductive layer 123, and the conductive layer 123 and the common electrode 115 may be electrically connected via the common layer 114. For example, by using an area mask, the regions where the common layer 114 and the common electrode 115 are formed can be different.

[0341] As shown in FIG. 19, a pixel electrode 111G of a light-emitting device 130G has a laminated structure of a conductive layer 124G, a conductive layer 126G on the conductive layer 124G, and a conductive layer 129G on the conductive layer 126G.

[0342] The conductive layer 124G is electrically connected to the conductive layer 116b included in the transistor 206G through openings provided in the insulating layer 107, the insulating layer 106, the insulating layer 218, and the insulating layer 235.

[0343] The end of conductive layer 124G is located outside the end of conductive layer 126G. The end of conductive layer 126G is located inside the end of conductive layer 129G. The end of conductive layer 124G is located outside the end of conductive layer 129G. In other words, the end of conductive layer 126G is located on conductive layer 124G. Also, the end of conductive layer 129G is located on conductive layer 124G. The top and side surfaces of conductive layer 126G are covered with conductive layer 129G.

[0344] The transmittance and reflectance of the conductive layer 124G to visible light are not particularly limited. A conductive layer that is transmissive to visible light or a conductive layer that is reflective to visible light can be used for the conductive layer 124G. As a conductive layer that is transmissive to visible light, for example, a conductive layer containing an oxide conductor (also referred to as an oxide conductive layer) can be used. Specifically, In—Si—Sn oxide (also referred to as ITSO) can be suitably used for the conductive layer 124G. As a conductive layer that is reflective to visible light, for example, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, silver, tin, zinc, silver, platinum, gold, molybdenum, tantalum, or tungsten, or an alloy containing any of these as a main component (for example, an alloy of silver, palladium, and copper (APC: Ag-Pd-Cu)) can be used. The conductive layer 124G may have a stacked structure of a conductive layer that is transmissive to visible light and a conductive layer that is reflective over the conductive layer. The conductive layer 124G is preferably made of a material that has high adhesion to the surface on which the conductive layer 124G is formed (here, the insulating layer 235), thereby preventing the conductive layer 124G from peeling off.

[0345] The conductive layer 126G can be a conductive layer that is reflective to visible light. The conductive layer 126G may have a stacked structure of a conductive layer that is transparent to visible light and a conductive layer that is reflective on the conductive layer. The same material as the conductive layer 124G can be used for the conductive layer 126G. Specifically, a stacked structure of In—Si—Sn oxide (ITSO) and an alloy of silver, palladium, and copper (APC) on the In—Si—Sn oxide (ITSO) can be suitably used for the conductive layer 126G.

[0346] The conductive layer 129G can be made of the same material as the conductive layer 124G. For example, a conductive layer that is transparent to visible light can be used for the conductive layer 129G. Specifically, In—Si—Sn oxide (ITSO) can be used for the conductive layer 129G.

[0347] When a material that is easily oxidized is used for the conductive layer 126G, applying a material that is less likely to be oxidized to the conductive layer 129G and covering the conductive layer 126G with the conductive layer 129G can prevent the conductive layer 126G from being oxidized. Furthermore, deposition of metal components contained in the conductive layer 126G can be prevented. For example, when a material containing silver is used for the conductive layer 126G, In—Si—Sn oxide (ITSO) can be suitably used for the conductive layer 129G. This can prevent the conductive layer 126G from being oxidized and suppress deposition of silver.

[0348] Conductive layer 124R (not shown), conductive layer 126R (not shown), and conductive layer 129R (not shown) in light-emitting device 130R, and conductive layer 124B, conductive layer 126B, and conductive layer 129B in light-emitting device 130B are similar to conductive layer 124G, conductive layer 126G, and conductive layer 129G in light-emitting device 130G, respectively, and therefore will not be described in detail.

[0349] The pixel electrodes 111R, 111G, 111B, conductive layer 123, and conductive layer 166 shown in FIG. 19 and other figures can also be applied to other configuration examples.

[0350] Recesses are formed in the conductive layers 124R, 124G, and 124B so as to cover the openings provided in the insulating layers 107, 106, 218, and 235. A layer 128 is buried in the recesses.

[0351] Layer 128 has the function of flattening the recesses of conductive layer 124R, conductive layer 124G, and conductive layer 124B. Conductive layers 126R, 126G, and 126B, which are electrically connected to conductive layer 124R, conductive layer 124G, and conductive layer 124B, respectively, are provided on conductive layer 124R, conductive layer 124G, and conductive layer 124B, and layer 128. Therefore, in light-emitting device 130, regions overlapping with the recesses of conductive layer 124R, conductive layer 124G, and conductive layer 124B also function as light-emitting regions, thereby increasing the aperture ratio of the pixel.

[0352] The layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 128. The layer 128 is preferably formed using an organic material. It is particularly preferable to use a photosensitive organic resin as the organic material. For example, a photosensitive resin composition containing an acrylic resin can be suitably used for the layer 128.

[0353] When the layer 128 is a conductive layer, the layer 128 can function as a part of a pixel electrode. The layer 128 can be made of, for example, an organic resin in which metal particles are dispersed.

[0354] The layer 128 shown in FIG. 19 and other figures can also be applied to other configuration examples.

[0355] FIG. 19 shows an example in which the edge of the layer 113G is located outside the edge of the pixel electrode 111G. The layer 113G is formed to cover the edge of the pixel electrode 111G. This configuration allows the entire upper surface of the pixel electrode to be used as a light-emitting region, thereby increasing the aperture ratio compared to a configuration in which the edge of the island-shaped EL layer is located inside the edge of the pixel electrode. Furthermore, covering the side surface of the pixel electrode 111 with the EL layer prevents the pixel electrode 111 from contacting the common electrode 115, thereby preventing short circuits in the light-emitting device 130. Note that while the pixel electrode 111G and the layer 113G are used as examples for explanation, the same applies to the pixel electrode 111R and the layer 113R, and the pixel electrode 111B and the layer 113B.

[0356] Between the pixel electrode 111G and the layer 113G, there is no insulating layer (see insulating layer 237 in FIG. 17 ) covering the upper end of the pixel electrode 111G. Furthermore, between the pixel electrode 111B and the layer 113B, there is no insulating layer covering the upper end of the pixel electrode 111B. This allows the distance between adjacent light-emitting devices to be reduced. This allows for a high-definition or high-resolution display device to be realized. Furthermore, a mask for forming the insulating layer is no longer required, thereby reducing the manufacturing costs of the display device.

[0357] The EL layer can be formed, for example, using a photolithography method. Specifically, a pixel electrode is formed for each subpixel, and then a film serving as an emissive layer is formed across the multiple pixel electrodes. The film is then processed using a photolithography method to form an island-shaped emissive layer for each pixel electrode. This divides the emissive layer into subpixels, allowing for the formation of an island-shaped emissive layer for each subpixel. Using a photolithography method, a fine-sized EL layer can be formed. By providing an island-shaped EL layer for each light-emitting device, leakage current between adjacent light-emitting devices can be suppressed. This prevents crosstalk due to unintended light emission, enabling a display device with extremely high contrast. In particular, a display device with high current efficiency at low brightness can be realized.

[0358] The heat resistance temperature of the compounds contained in the layers 113R, 113G, and 113B is preferably 100° C. or higher and 180° C. or lower, more preferably 120° C. or higher and 180° C. or lower, and more preferably 140° C. or higher and 180° C. or lower. For example, the glass transition point (Tg) of these compounds is preferably 100° C. or higher and 180° C. or lower, more preferably 120° C. or higher and 180° C. or lower, and more preferably 140° C. or higher and 180° C. or lower. This prevents the layers 113R, 113G, and 113B from being damaged by heat applied during the process, thereby reducing the luminous efficiency and shortening the lifetime.

[0359] An insulating layer 125 and an insulating layer 127 on the insulating layer 125 are provided in the region between adjacent light-emitting devices 130. Although multiple cross sections of the insulating layer 125 and the insulating layer 127 are shown in Figure 19, when the display device 200C is viewed from above, the insulating layer 125 and the insulating layer 127 are each connected to one another. In other words, the display device 200C can be configured to have, for example, one insulating layer 125 and one insulating layer 127. Note that the display device 200C may have multiple insulating layers 125 that are separated from one another, or may have multiple insulating layers 127 that are separated from one another.

[0360] The insulating layer 125 is preferably in contact with the side surfaces of the layers 113R, 113G, and 113B. The insulating layer 125 being in contact with the layers 113R, 113G, and 113B can prevent the layers 113R, 113G, and 113B from peeling off. The insulating layer 125 being in close contact with the layers 113R, 113G, or 113B can fix or bond the adjacent layers 113 and the like by the insulating layer 125. This can improve the reliability of the light-emitting device. Furthermore, the manufacturing yield of the light-emitting device can be increased.

[0361] The insulating layer 125 can be formed using an inorganic material. For example, the insulating layer 125 can include one or more of an oxide, an oxynitride, a nitride oxide, and a nitride. The insulating layer 125 can have a single-layer structure or a stacked-layer structure. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, indium gallium zinc oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride and aluminum oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide. In particular, aluminum oxide is preferable because it has a high etching selectivity with respect to the EL layer and has a function of protecting the EL layer.

[0362] The insulating layer 125 preferably functions as a barrier insulating layer against at least one of water and oxygen. The insulating layer 125 preferably has a function of suppressing diffusion of at least one of water and oxygen. The insulating layer 125 preferably has a function of capturing or fixing (also referred to as gettering) at least one of water and oxygen. Note that in this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. In this specification and the like, barrier properties refer to a function of suppressing diffusion of a corresponding substance (also referred to as low permeability).

[0363] The insulating layer 125 has a function as a barrier insulating layer or a gettering function, which can suppress the intrusion of impurities (typically, at least one of water and oxygen) that can diffuse into each light-emitting device from the outside. With this configuration, a highly reliable light-emitting device and further a highly reliable display device can be provided.

[0364] The insulating layer 127 is provided on the insulating layer 125 so as to fill recesses formed in the insulating layer 125. The insulating layer 127 can be configured to overlap with part of the top surface and side surfaces of the layers 113R, 113G, and 113B via the insulating layer 125. The insulating layer 127 preferably covers at least part of the side surfaces of the insulating layer 125. By providing the insulating layer 125 and the insulating layer 127, the gaps between adjacent island-shaped layers can be filled, thereby reducing unevenness on the formation surfaces of layers (e.g., carrier injection layers, common electrodes, etc.) provided on the island-shaped layers and improving the coverage of the layers. The top surface of the insulating layer 127 preferably has a highly flat shape, but may also have a convex portion, a convex curved surface, a concave curved surface, or a concave portion.

[0365] An insulating layer containing an organic material can be suitably used as the insulating layer 127. As the organic material, a photosensitive organic resin is preferably used, and for example, a photosensitive resin composition containing an acrylic resin is preferably used.

[0366] The insulating layer 127 may be made of an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimideamide resin, a silicone resin, a siloxane resin, a benzocyclobutene-based resin, a phenolic resin, or a precursor of any of these resins. Alternatively, the insulating layer 127 may be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or an alcohol-soluble polyamide resin. Alternatively, a photoresist may be used as the photosensitive resin. Either a positive-type material or a negative-type material may be used as the photosensitive organic resin.

[0367] The insulating layer 127 may be made of a material that absorbs visible light. By having the insulating layer 127 absorb light emitted from the light-emitting device, it is possible to suppress leakage of light from the light-emitting device to an adjacent light-emitting device through the insulating layer 127 (stray light). This can improve the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, it is possible to reduce the weight and thickness of the display device.

[0368] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used for color filters (color filter materials). In particular, using a resin material in which two or more color filter materials are laminated or mixed is preferable because it can enhance the visible light blocking effect. In particular, mixing three or more color filter materials makes it possible to form a black or nearly black resin layer.

[0369] Mask layers 118R and 119R are located on layer 113R of light-emitting device 130R, mask layers 118G and 119G are located on layer 113G of light-emitting device 130G, and mask layers 118B and 119B are located on layer 113B of light-emitting device 130B. Mask layers 118 and 119 are provided to surround the light-emitting region. In other words, mask layers 118 and 119 have openings in areas that overlap with the light-emitting region. Mask layers 118R and 119R are remaining portions of the mask layer that was provided on layer 113R when layer 113R was formed. Similarly, the mask layers 118G and 119G are mask layers that are formed when the layer 113G is formed, and the mask layers 118B and 119B are mask layers that are formed when the layer 113B is formed, and the mask layers are mask layers that are formed when the layer 113G is formed. In this manner, in the display device of one embodiment of the present invention, the mask layers that are used to protect the EL layer during the manufacturing process may be partially left.

[0370] The common layer 114 and the common electrode 115 are provided over the layer 113R, the layer 113G, the layer 113B, the mask layer 118, the mask layer 119, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, a step is generated between a region where the pixel electrode and the island-shaped EL layer are provided and a region where the pixel electrode and the island-shaped EL layer are not provided (a region between light-emitting devices). By including the insulating layer 125 and the insulating layer 127, the display device of one embodiment of the present invention can reduce the step and improve the coverage of the common layer 114 and the common electrode 115. Therefore, poor connection due to a step between the common layer 114 and the common electrode 115 can be suppressed. Furthermore, the step can locally reduce the thickness of the common electrode 115, thereby suppressing an increase in the electrical resistance of the common electrode 115.

[0371] In addition, the insulating layer 127 may cover at least a portion of the side surfaces of the insulating layer 125, the mask layer 118R, the mask layer 119R, the mask layer 118G, the mask layer 119G, the mask layer 118B, and the mask layer 119B. In addition, the insulating layer 127 may have regions in contact with the layer 113R, the layer 113G, and the layer 113B.

[0372] <Display Device 200D> The display device 200D shown in FIG. 20 differs from the display device 200C shown in FIG. 19 mainly in that it has an insulating layer 239.

[0373] The insulating layer 239 is provided over the insulating layer 235 and has an opening in a region overlapping with the opening of the insulating layer 235. The pixel electrode 111 is provided to cover the openings provided in the insulating layer 239, the insulating layer 235, the insulating layer 218, the insulating layer 106, and the insulating layer 107.

[0374] The insulating layer 239 can function as an etching protective film when the layer 113, the mask layer 118, and the mask layer 119 are formed. By providing the insulating layer 239, it is possible to prevent part of the insulating layer 235 from being etched when the layer 113, the mask layer 118, and the mask layer 119 are formed, thereby preventing unevenness from being generated in the insulating layer 235. That is, the step on the surface where the insulating layer 125 is to be formed is reduced, and the coverage of the insulating layer 125 can be improved. Therefore, the side surface of the layer 113 is covered with the insulating layer 125, and peeling of the layer 113 can be prevented.

[0375] The insulating layer 239 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulating layer 239. The insulating layer 239 may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. For example, a silicon oxide film or a silicon oxynitride film can be suitably used for the insulating layer 239.

[0376] For the insulating layer 239, a material having a high etching rate (also referred to as a high selectivity) relative to the layer 113, the mask layer 118, and the film to be the mask layer 119 is preferably selected when the film is etched.

[0377] Here, if the flatness of the surface on which the light-emitting device 130 is formed is low, problems such as poor connection due to a step in the common electrode 115, or an increase in electrical resistance due to a localized thinning of the film thickness of the common electrode 115 may occur. Also, the processing accuracy of the layer formed on the surface may be reduced.

[0378] In the display device according to one embodiment of the present invention, the insulating layer 239 can make the surface on which the light-emitting device 130 is formed more flat. Therefore, the processing accuracy of the light-emitting device 130 and the like provided over the insulating layer 239 can be improved, and a display device with high definition can be provided. Furthermore, poor connection due to a step in the common electrode 115 and an increase in electrical resistance due to a local thinning of the thickness of the common electrode 115 can be prevented, and a display device with high display quality can be provided.

[0379] 20 shows the insulating layer 239 having a single-layer structure; however, one embodiment of the present invention is not limited to this. The insulating layer 239 may have a stacked-layer structure.

[0380] A part of the insulating layer 239 may be removed in a region that does not overlap with any of the layers 113R, 113G, and 113B. The thickness of the insulating layer 239 in a region that does not overlap with any of the layers 113R, 113G, and 113B may be thinner than the thickness of the insulating layer 239 in a region that overlaps with the layer 113R, 113G, or 113B.

[0381] The insulating layer 239 can also be applied to other configuration examples.

[0382] 21 differs from the display devices shown in FIGS. 17 to 20 in the relative positions of the transistor 205 and the transistor 206. The display device 200E also differs from the display device 200D shown in FIG. 20 mainly in that it is a bottom-emission display device.

[0383] 17 to 20, the transistors 205 and 206 are adjacent to each other, and the overall positional relationship corresponds to that of the semiconductor device 10 shown in FIGS. 1A and 1B. On the other hand, in the display device 200E, the transistor 205 is disposed so as to overlap the transistor 206, and the overall positional relationship corresponds to that of the semiconductor device 10A shown in FIGS. 2A and 2B. In the case of a bottom-emission display device, light emitted by the light-emitting device is emitted toward the substrate 151. Therefore, by configuring the relative positional relationship between the transistors 205 and 206 to that of the semiconductor device 10A, the aperture ratio of the display device can be significantly increased compared to the configuration of the semiconductor device 10.

[0384] As described above, light emitted from the light-emitting device is emitted toward the substrate 151. Therefore, it is preferable to use a material that is highly transparent to visible light for the substrate 151. On the other hand, the light-transmitting property of the material used for the substrate 152 does not matter.

[0385] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistor 201, and between the substrate 151 and the transistor 205 and between the substrate 151 and the transistor 206. Figure 21 shows an example in which the light-shielding layer 117 is provided over the substrate 151, the insulating layer 153 is provided over the light-shielding layer 117, and the transistor 201, the transistor 205R, the transistor 206R, the transistor 205G, and the transistor 206G are provided over the insulating layer 153.

[0386] The pixel electrodes 111R (not shown), 111G, and 111B are made of a material that is highly transparent to visible light, and the common electrode 115 is preferably made of a material that reflects visible light.

[0387] <Display Device 200F> A display device 200F shown in FIG. 22 differs from the display device 200D shown in FIG. 20 mainly in that it includes a light receiving device 150.

[0388] For example, a pn-type or pin-type photodiode can be used as the light-receiving device 150. The light-receiving device 150 functions as a photoelectric conversion device (also called a photoelectric conversion element) that detects light incident on the light-receiving device and generates electric charges. The amount of electric charges generated by the light-receiving device 150 is determined based on the amount of light incident on the light-receiving device 150.

[0389] The light receiving device 150 can detect either or both of visible light and infrared light. When detecting visible light, it can detect one or more of light such as blue, purple, blue-purple, green, yellow-green, yellow, orange, and red. When detecting infrared light, it is possible to detect an object even in a dark place, which is preferable.

[0390] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light-receiving device 150. Organic photodiodes can be easily made thin, lightweight, and large in area, and have a high degree of freedom in shape and design, making them applicable to a variety of display devices.

[0391] In one embodiment of the present invention, an organic EL device is used as the light-emitting device 130, and an organic photodiode is used as the light-receiving device 150. The organic EL device and the organic photodiode can be formed on the same substrate. Therefore, the organic photodiode can be built into a display device using the organic EL device.

[0392] The light receiving device 150 is driven by applying a reverse bias between the pixel electrode 111S and the common electrode 115, so that it can detect light incident on the light receiving device, generate electric charges, and extract them as a current.

[0393] In FIG. 22, light G emitted from the light emitting device 130G toward the substrate 152 side, and light Lin incident on the light receiving device 150 from the substrate 152 side are indicated by dashed arrows.

[0394] The light-receiving device 150 can be fabricated using the same method as the light-emitting device 130. The island-shaped active layer (also referred to as a photoelectric conversion layer) of the light-receiving device can be formed using, for example, a fine metal mask. Alternatively, the active layer can be formed using a photolithography method instead of using a fine metal mask. When using a photolithography method, the active layer is formed by depositing a film that will become the active layer on the entire surface and then processing it, so that the island-shaped active layer can be formed with a uniform thickness. Furthermore, by providing a mask layer on the active layer, damage to the active layer during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-receiving device. Here, a configuration in which the active layer is formed using a photolithography method will be described as an example.

[0395] The light-receiving device 150 includes a pixel electrode 111S, a layer 113S, a common layer 114, and a common electrode 115. The layer 113S includes at least an active layer. The pixel electrode 111S has a layered structure including a conductive layer 124S, a conductive layer 126S on the conductive layer 124S, and a conductive layer 129S on the conductive layer 126S. The pixel electrode 111S can be formed in the same process as the pixel electrodes 111R (not shown), 111G, and 111B (not shown).

[0396] The pixel electrode 111S is electrically connected to the conductive layer 116b of the transistor 206S. The transistor 205S can be formed using the same process as the transistors 205R, 205G, and 205B. The transistor 206S can be formed using the same process as the transistors 206R, 206G, and 206B. The insulating layers 235, 218, 106, and 107 each have an opening in a region overlapping with the conductive layer 116b of the transistor 206S. The pixel electrode 111S of the light-receiving device 150 is provided to cover the opening. The conductive layer 116b of the transistor 206S is electrically connected to the pixel electrode 111S through the opening. The layer 113S is provided on the pixel electrode 111S. A common layer 114 is provided on the layer 113S, and a common electrode 115 is provided on the common layer 114. The common layer 114 is a continuous layer that is provided in common to the light-receiving device 150 and the light-emitting device 130 .

[0397] The layer 113S includes at least an active layer and preferably has multiple functional layers. Examples of functional layers include a carrier transport layer (hole transport layer and electron transport layer) and a carrier block layer (hole block layer and electron block layer). It is also preferable to have one or more layers on the active layer. Having another layer between the active layer and the mask layer can prevent the active layer from being exposed to the outermost surface during the manufacturing process of the display device, thereby reducing damage to the active layer. This can improve the reliability of the light-receiving device 150. Therefore, the layer 113S preferably has an active layer and a carrier block layer (hole block layer or electron block layer) or a carrier transport layer (electron transport layer or hole transport layer) on the active layer.

[0398] The layer 113S is a layer that is provided in the light-receiving device 150 but not in the light-emitting device 130. However, functional layers other than the active layer included in the layer 113S may have the same material as functional layers other than the light-emitting layers included in the layers 113R, 113G, and 113B. On the other hand, the common layer 114 is a continuous layer shared by the light-emitting device 130 and the light-receiving device 150.

[0399] Here, a layer shared by a light-receiving device and a light-emitting device may have different functions in the light-emitting device and in the light-receiving device. In this specification, components may be referred to based on their functions in the light-emitting device. For example, a hole injection layer functions as a hole injection layer in the light-emitting device and as a hole transport layer in the light-receiving device. Similarly, an electron injection layer functions as an electron injection layer in the light-emitting device and as an electron transport layer in the light-receiving device. Furthermore, a layer shared by a light-receiving device and a light-emitting device may have the same function in the light-emitting device and in the light-receiving device. For example, a hole transport layer functions as a hole transport layer in both the light-emitting device and the light-receiving device, and an electron transport layer functions as an electron transport layer in both the light-emitting device and the light-receiving device.

[0400] In the region between the adjacent light-emitting device 130 and light-receiving device 150, an insulating layer 125 and an insulating layer 127 on the insulating layer 125 are provided.

[0401] Mask layers 118R and 119R are located between layer 113R and insulating layer 125, and mask layers 118S and 119S are located between layer 113S and insulating layer 125. Mask layers 118R and 119R are formed by remaining portions of a mask layer formed on layer 113R when processing layer 113R. Mask layers 118S and 119S are formed by remaining portions of a mask layer formed in contact with the top surface of layer 113S, which includes an active layer, when processing layer 113S. Mask layers 118R and 118S may be made of the same material or different materials. Mask layers 119R and 119S may be made of the same material or different materials.

[0402] This embodiment mode can be combined with other embodiment modes or examples as appropriate.

[0403] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS. 23A to 24K.

[0404] The pixel layout will now be described. There are no particular limitations on the arrangement of sub-pixels, and various methods can be applied. Examples of the arrangement of sub-pixels include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0405] Examples of the planar shape of the subpixel include a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, shapes with rounded corners of these polygons, an ellipse, and a circle. The planar shape of the subpixel corresponds to the planar shape of the light-emitting region of the light-emitting device or the light-receiving region of the light-receiving device.

[0406] A stripe arrangement is applied to the pixel 210 shown in FIG. 23A . The pixel 210 is composed of three types of subpixels: subpixel 11a, subpixel 11b, and subpixel 11c. The subpixels 11a, subpixel 11b, and subpixel 11c each emit light of a different color. Examples of the subpixels 11a, subpixel 11b, and subpixel 11c include subpixels of three colors: red (R), green (G), and blue (B), and subpixels of three colors: yellow (Y), cyan (C), and magenta (M). The number of colors of the subpixels is not limited to three and may be four or more. Examples of four-color subpixels include subpixels of R, G, B, and white (W), subpixels of R, G, B, and Y, and subpixels of R, G, B, and infrared (IR).

[0407] Each subpixel has a pixel circuit that controls a light-emitting device. The pixel circuit is not limited to the area of ​​the subpixel shown in Fig. 23A and may be located outside of it. For example, the transistor included in the pixel circuit of subpixel 11a may be located within the area of ​​subpixel 11a shown in Fig. 23A, or part or all of the transistor may be located outside the area of ​​subpixel 11a.

[0408] 23A shows the subpixels 11a, 11b, and 11c as having the same or approximately the same aperture ratio (which can also be referred to as the size or the size of the light-emitting region), but this is not a limitation of one embodiment of the present invention. The aperture ratios of the subpixels 11a, 11b, and 11c can be determined as appropriate. The aperture ratios of the subpixels 11a, 11b, and 11c may be different from one another, or two or more of them may be the same or approximately the same.

[0409] An S-stripe arrangement is applied to the pixel 210 shown in Fig. 23B. The pixel 210 shown in Fig. 23B is composed of three types of subpixels: subpixel 11a, subpixel 11b, and subpixel 11c, with two subpixels (subpixel 11a and subpixel 11b) in the left column (first column) and one subpixel (subpixel 11c) in the right column (second column).

[0410] 23C includes a subpixel 11a having a substantially trapezoidal planar shape with rounded corners, a subpixel 11b having a substantially triangular planar shape with rounded corners, and a subpixel 11c having a substantially rectangular or hexagonal planar shape with rounded corners. Furthermore, the light-emitting area of ​​the subpixel 11a is smaller than that of the subpixel 11b. In this manner, the shape and size of each subpixel can be determined independently. For example, the more reliable the light-emitting device of a subpixel, the smaller its size can be.

[0411] The Pentile arrangement is applied to the pixels 210a and 210b shown in Fig. 23D. Fig. 23D shows an example in which a pixel 210a having sub-pixels 11a and 11b and a pixel 210b having sub-pixels 11b and 11c are arranged alternately.

[0412] 23E to 23G, a delta arrangement is applied to pixels 210a and 210b. Pixel 210a has two subpixels (subpixel 11a and subpixel 11b) in the top row (first row) and one subpixel (subpixel 11c) in the bottom row (second row). Pixel 210b has one subpixel (subpixel 11c) in the top row (first row) and two subpixels (subpixel 11a and subpixel 11b) in the bottom row (second row).

[0413] Figure 23E is an example in which each sub-pixel has a roughly rectangular planar shape with rounded corners, Figure 23F is an example in which each sub-pixel has a circular planar shape, and Figure 23G is an example in which each sub-pixel has a roughly hexagonal planar shape with rounded corners.

[0414] In Figure 23G, each subpixel is arranged inside a closely packed hexagonal region. Each subpixel is arranged so that it is surrounded by six other subpixels when focusing on one subpixel. Furthermore, subpixels that emit light of the same color are arranged so that they are not adjacent to each other. For example, when focusing on subpixel 11a, three subpixels 11b and three subpixels 11c are arranged alternately so as to surround it.

[0415] 23H shows an example in which subpixels of each color are arranged in a zigzag pattern. Specifically, the positions of the upper sides of two subpixels aligned in the column direction (for example, subpixels 11a and 11b, or subpixels 11b and 11c) are misaligned in a plan view.

[0416] 23A to 23H, it is preferable that, for example, subpixel 11a be subpixel R that emits red light, subpixel 11b be subpixel G that emits green light, and subpixel 11c be subpixel B that emits blue light. Note that the configuration of the subpixels is not limited to this, and the colors that the subpixels emit and their order of arrangement can be determined appropriately. For example, subpixel 11b may be subpixel R that emits red light, and subpixel 11a may be subpixel G that emits green light.

[0417] In photolithography, the finer the pattern to be processed, the more significant the effect of light diffraction becomes. This reduces the fidelity of the photomask pattern when it is transferred by exposure, making it difficult to process the resist mask into the desired shape. Therefore, even if the photomask pattern is rectangular, a pattern with rounded corners is likely to be formed. As a result, the planar shape of the subpixel may become a polygon with rounded corners, an ellipse, a circle, or the like.

[0418] In order to make the planar shape of the sub-pixel a desired shape, a technique for correcting the mask pattern in advance (OPC (Optical Proximity Correction) technique) may be used so that the design pattern and the transfer pattern coincide with each other. Specifically, the OPC technique adds a correction pattern to the corners of the figures on the mask pattern.

[0419] As shown in Figures 24A to 24I, a pixel can be configured to have four types of sub-pixels.

[0420] A stripe arrangement is applied to the pixel 210 shown in FIGS. 24A to 24C.

[0421] Figure 24A is an example in which each subpixel has a rectangular planar shape, Figure 24B is an example in which each subpixel has a planar shape that combines two semicircles and a rectangle, and Figure 24C is an example in which each subpixel has an elliptical planar shape.

[0422] A matrix arrangement is applied to the pixels 210 shown in FIGS. 24D to 24F.

[0423] Figure 24D is an example in which each sub-pixel has a square planar shape, Figure 24E is an example in which each sub-pixel has an approximately square planar shape with rounded corners, and Figure 24F is an example in which each sub-pixel has a circular planar shape.

[0424] 24G and 24H show an example in which one pixel 210 is configured in two rows and three columns.

[0425] 24G has three subpixels (subpixels 11a, 11b, and 11c) in the top row (first row) and one subpixel (subpixel 11d) in the bottom row (second row). In other words, pixel 210 has subpixel 11a in the left column (first column), subpixel 11b in the center column (second column), subpixel 11c in the right column (third column), and subpixel 11d across these three columns.

[0426] The pixel 210 shown in FIG. 24H has three subpixels (subpixels 11a, 11b, and 11c) in the top row (first row) and three subpixels 11d in the bottom row (second row). In other words, the pixel 210 has subpixels 11a and 11d in the left column (first column), subpixels 11b and 11d in the center column (second column), and subpixels 11c and 11d in the right column (third column). By aligning the subpixels in the top and bottom rows as shown in FIG. 24H , it is possible to efficiently remove dust and other impurities that may occur during the manufacturing process. Therefore, a display device with high display quality can be provided.

[0427] FIG. 24I shows an example in which one pixel 210 is configured in three rows and two columns.

[0428] 24I has subpixel 11a in the top row (first row), subpixel 11b in the center row (second row), subpixel 11c across the first and second rows, and one subpixel (subpixel 11d) in the bottom row (third row). In other words, pixel 210 has subpixels 11a and 11b in the left column (first column), subpixel 11c in the right column (second column), and subpixel 11d across these two columns.

[0429] A pixel 210 shown in FIGS. 24A to 24I is composed of four subpixels: subpixel 11a, subpixel 11b, subpixel 11c, and subpixel 11d.

[0430] The sub-pixels 11a, 11b, 11c, and 11d may each have a light-emitting device that emits light of a different color, such as sub-pixels of four colors R, G, B, and white (W), sub-pixels of four colors R, G, B, and Y, or sub-pixels of four colors R, G, B, and infrared (IR).

[0431] In each pixel 210 shown in Figures 24A to 24I, it is preferable that, for example, subpixel 11a is a subpixel R that emits red light, subpixel 11b is a subpixel G that emits green light, subpixel 11c is a subpixel B that emits blue light, and subpixel 11d is any one of subpixels W that emit white light, Y that emit yellow light, and IR that emit near-infrared light. With such a configuration, in the pixel 210 shown in Figures 24G and 24H, the layout of R, G, and B is a stripe arrangement, thereby improving display quality. Furthermore, in the pixel 210 shown in Figure 24I, the layout of R, G, and B is a so-called S-stripe arrangement, thereby improving display quality.

[0432] The pixel 210 may have sub-pixels that include light-receiving devices.

[0433] In each pixel 210 shown in FIGS. 24A to 24I, any one of the subpixels 11a to 11d may be a subpixel having a light receiving device.

[0434] 24A to 24I , it is preferable that, for example, subpixel 11a is a subpixel R that emits red light, subpixel 11b is a subpixel G that emits green light, subpixel 11c is a subpixel B that emits blue light, and subpixel 11d is a subpixel S that has a light-receiving device. With this configuration, the pixel 210 shown in FIGS. 24G and 24H has a stripe layout of R, G, and B, which can improve display quality. Furthermore, the pixel 210 shown in FIG. 24I has a so-called S-stripe layout of R, G, and B, which can improve display quality.

[0435] The wavelength of light detected by the subpixel S having the light receiving device is not particularly limited, and the subpixel S can be configured to detect either or both of visible light and infrared light.

[0436] As shown in Figures 24J and 24K, a pixel can be configured to have five types of sub-pixels.

[0437] FIG. 24J shows an example in which one pixel 210 is configured in two rows and three columns.

[0438] 24J has three subpixels (subpixel 11a, subpixel 11b, and subpixel 11c) in the top row (first row) and two subpixels (subpixel 11d and subpixel 11e) in the bottom row (second row). In other words, pixel 210 has subpixel 11a and subpixel 11d in the left column (first column), subpixel 11b in the center column (second column), subpixel 11c in the right column (third column), and subpixel 11e from the second column to the third column.

[0439] FIG. 24K shows an example in which one pixel 210 is configured in three rows and two columns.

[0440] 24K has subpixel 11a in the top row (first row), subpixel 11b in the middle row (second row), subpixel 11c from the first row to the second row, and two subpixels (subpixel 11d and subpixel 11e) in the bottom row (third row). In other words, pixel 210 has subpixels 11a, subpixel 11b, and subpixel 11d in the left column (first column), and subpixels 11c and subpixel 11e in the right column (second column).

[0441] 24J and 24K, it is preferable that, for example, subpixel 11a is a subpixel R that emits red light, subpixel 11b is a subpixel G that emits green light, and subpixel 11c is a subpixel B that emits blue light. In this configuration, the pixel 210 shown in FIG. 24J has a stripe layout of R, G, and B, which can improve display quality. Furthermore, the pixel 210 shown in FIG. 24K has a so-called S-stripe layout of R, G, and B, which can improve display quality.

[0442] 24J and 24K, it is preferable to use a subpixel S having a light-receiving device in at least one of the subpixels 11d and 11e. When light-receiving devices are used in both the subpixels 11d and 11e, the configurations of the light-receiving devices may be different from each other. For example, the wavelength ranges of light detected by the subpixels 11d and 11e may be at least partially different from each other. Specifically, one of the subpixels 11d and 11e may have a light-receiving device that mainly detects visible light, and the other may have a light-receiving device that mainly detects infrared light.

[0443] 24J and 24K, it is preferable that one of the subpixels 11d and 11e is a subpixel S having a light-receiving device, and the other is a subpixel having a light-emitting device that can be used as a light source. For example, it is preferable that one of the subpixels 11d and 11e is a subpixel IR that emits infrared light, and the other is a subpixel S having a light-receiving device that detects infrared light.

[0444] In a pixel having subpixels R, G, B, IR, and S, an image can be displayed using subpixels R, G, and B, while subpixel IR is used as a light source to detect reflected infrared light emitted by subpixel IR at subpixel S.

[0445] As described above, the display device of one embodiment of the present invention can employ various layouts for a pixel having a subpixel including a light-emitting device. Furthermore, the display device of one embodiment of the present invention can employ a pixel having both a light-emitting device and a light-receiving device. In this case, various layouts can also be employed.

[0446] This embodiment mode can be combined with other embodiment modes or examples as appropriate.

[0447] Embodiment 4 In this embodiment, a light-emitting device that can be used for a display device of one embodiment of the present invention will be described.

[0448] 25A, the light-emitting device has an EL layer 763 between a pair of electrodes (a lower electrode 761 and an upper electrode 762). The EL layer 763 can be composed of multiple layers, such as a layer 780, a light-emitting layer 771, and a layer 790.

[0449] The light-emitting layer 771 contains at least a light-emitting substance (also referred to as a light-emitting material).

[0450] When the lower electrode 761 is an anode and the upper electrode 762 is a cathode, the layer 780 includes one or more of a layer containing a material with high hole injection properties (hole injection layer), a layer containing a material with high hole transport properties (hole transport layer), and a layer containing a material with high electron blocking properties (electron blocking layer). The layer 790 also includes one or more of a layer containing a material with high electron injection properties (electron injection layer), a layer containing a material with high electron transport properties (electron transport layer), and a layer containing a material with high hole blocking properties (hole blocking layer). When the lower electrode 761 is a cathode and the upper electrode 762 is an anode, the layers 780 and 790 have the opposite configurations to those described above.

[0451] A structure including the layer 780, the light-emitting layer 771, and the layer 790 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 25A is referred to as a single structure in this specification.

[0452] Fig. 25B shows a modified example of the EL layer 763 included in the light-emitting device shown in Fig. 25A. Specifically, the light-emitting device shown in Fig. 25B has a layer 781 on a lower electrode 761, a layer 782 on the layer 781, a light-emitting layer 771 on the layer 782, a layer 791 on the light-emitting layer 771, a layer 792 on the layer 791, and an upper electrode 762 on the layer 792.

[0453] When the lower electrode 761 is an anode and the upper electrode 762 is a cathode, for example, the layer 781 can be a hole injection layer, the layer 782 can be a hole transport layer, the layer 791 can be an electron transport layer, and the layer 792 can be an electron injection layer. When the lower electrode 761 is a cathode and the upper electrode 762 is an anode, the layer 781 can be an electron injection layer, the layer 782 can be an electron transport layer, the layer 791 can be a hole transport layer, and the layer 792 can be a hole injection layer. Such a layer structure allows carriers to be efficiently injected into the light-emitting layer 771, and the efficiency of carrier recombination in the light-emitting layer 771 can be increased.

[0454] 25C and 25D , a variation of the single structure is a configuration in which multiple light-emitting layers (light-emitting layer 771, light-emitting layer 772, and light-emitting layer 773) are provided between layer 780 and layer 790. While FIGS. 25C and 25D show an example having three light-emitting layers, the light-emitting layer in a single-structure light-emitting device may have two layers or four or more layers. Furthermore, a light-emitting device with a single structure may have a buffer layer between the two light-emitting layers. For example, a carrier transport layer (hole transport layer or electron transport layer) can be used as the buffer layer.

[0455] As shown in Figures 25E and 25F, a configuration in which multiple light-emitting units (light-emitting unit 763a and light-emitting unit 763b) are connected in series via a charge generation layer 785 is referred to as a tandem structure in this specification. The tandem structure may also be referred to as a stack structure. The tandem structure can provide a light-emitting device capable of emitting high-luminance light. Furthermore, the tandem structure can reduce the current required to obtain the same luminance compared to a single structure, thereby improving reliability.

[0456] 25D and 25F are examples of display devices having a layer 764 overlapping with the light-emitting device. Fig. 25D is an example in which the layer 764 overlaps with the light-emitting device shown in Fig. 25C, and Fig. 25F is an example in which the layer 764 overlaps with the light-emitting device shown in Fig. 25E. In Fig. 25D and 25F, a conductive film that transmits visible light is used for the upper electrode 762 in order to extract light to the upper electrode 762 side.

[0457] As the layer 764, one or both of a color conversion layer and a color filter (coloring layer) can be used.

[0458] 25C and 25D , the light-emitting layers 771, 772, and 773 may be made of light-emitting materials that emit light of the same color, or even the same light-emitting material. For example, the light-emitting layers 771, 772, and 773 may be made of a light-emitting material that emits blue light. In the subpixel that emits blue light, blue light emitted by the light-emitting device can be extracted. In the subpixels that emit red light and the subpixels that emit green light, a color conversion layer can be provided as the layer 764 shown in FIG. 25D to convert blue light emitted by the light-emitting device into light with a longer wavelength, thereby extracting red or green light. It is also preferable to use both a color conversion layer and a colored layer as the layer 764. A portion of the light emitted by the light-emitting device may be transmitted directly without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer through the colored layer, light other than the desired color can be absorbed by the colored layer, thereby improving the color purity of the light emitted by the subpixel.

[0459] 25C and 25D , light-emitting layers 771, 772, and 773 may each contain a light-emitting substance that emits light of a different color. When the light emitted by light-emitting layers 771, 772, and 773 is complementary in color, the light is mixed to produce white light overall. For example, a single-structure light-emitting device preferably has a light-emitting layer containing a light-emitting substance that emits blue light and a light-emitting layer containing a light-emitting substance that emits visible light with a wavelength longer than blue.

[0460] 25D, a color filter may be provided as layer 764. When white light passes through the color filter, light of a desired color can be obtained.

[0461] For example, when a light-emitting device with a single structure has three light-emitting layers, it preferably has a light-emitting layer containing a light-emitting material that emits red (R) light, a light-emitting layer containing a light-emitting material that emits green (G) light, and a light-emitting layer containing a light-emitting material that emits blue (B) light. The stacking order of the light-emitting layers can be R, G, B from the anode side, or R, B, G from the anode side, etc. In this case, a buffer layer may be provided between R and G or B.

[0462] For example, when a light-emitting device with a single structure has two light-emitting layers, a structure having one light-emitting layer containing a light-emitting substance that emits blue (B) light and another light-emitting layer containing a light-emitting substance that emits yellow (Y) light is preferred. This structure is sometimes called a BY single structure.

[0463] A light-emitting device that emits white light preferably contains two or more types of light-emitting materials. To obtain white light emission, light-emitting materials may be selected such that the respective emissions of the two or more light-emitting materials have a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a light-emitting device that emits white light as a whole can be obtained. The same applies to a light-emitting device having three or more light-emitting layers.

[0464] 25C and 25D, the layer 780 and the layer 790 may each independently have a laminated structure made up of two or more layers, as shown in FIG. 25B.

[0465] 25E and 25F , the light-emitting layer 771 and the light-emitting layer 772 may be made of a light-emitting material that emits light of the same color, or even the same light-emitting material. For example, in a light-emitting device having subpixels that emit light of different colors, the light-emitting layer 771 and the light-emitting layer 772 may each be made of a light-emitting material that emits blue light. In the subpixel that emits blue light, the blue light emitted by the light-emitting device can be extracted. In the subpixel that emits red light and the subpixel that emits green light, a color conversion layer can be provided as the layer 764 shown in FIG. 25F to convert the blue light emitted by the light-emitting device into light with a longer wavelength, thereby allowing red or green light to be extracted. Furthermore, it is preferable to use both a color conversion layer and a colored layer as the layer 764.

[0466] When the light-emitting devices having the configurations shown in FIG. 25E or 25F are used for the subpixels emitting light of each color, different light-emitting materials may be used for each subpixel. Specifically, in a light-emitting device included in a subpixel emitting red light, light-emitting materials that emit red light may be used for the light-emitting layers 771 and 772. Similarly, in a light-emitting device included in a subpixel emitting green light, light-emitting materials that emit green light may be used for the light-emitting layers 771 and 772. In a light-emitting device included in a subpixel emitting blue light, light-emitting materials that emit blue light may be used for the light-emitting layers 771 and 772. A display device having such a configuration can be said to employ a tandem-structure light-emitting device and also have an SBS structure. Therefore, it can have the advantages of both the tandem structure and the SBS structure. This allows for a highly reliable light-emitting device capable of emitting high-brightness light.

[0467] 25E and 25F, the light-emitting layer 771 and the light-emitting layer 772 may be made of light-emitting materials that emit light of different colors. When the light emitted by the light-emitting layer 771 and the light emitted by the light-emitting layer 772 are complementary colors, the respective lights are mixed together to produce white light overall. A color filter may be provided as the layer 764 shown in FIG. 25F. When white light passes through the color filter, light of a desired color can be obtained.

[0468] 25E and 25F show an example in which the light-emitting unit 763a has one light-emitting layer 771 and the light-emitting unit 763b has one light-emitting layer 772, but this is not limiting. Each of the light-emitting unit 763a and the light-emitting unit 763b may have two or more light-emitting layers.

[0469] 25E and 25F illustrate light-emitting devices having two light-emitting units, but the present invention is not limited to this. The light-emitting device may have three or more light-emitting units. Note that a configuration having two light-emitting units may be referred to as a two-tiered tandem structure, and a configuration having three light-emitting units may be referred to as a three-tiered tandem structure.

[0470] 25E and 25F, light-emitting unit 763a includes layer 780a, light-emitting layer 771, and layer 790a, and light-emitting unit 763b includes layer 780b, light-emitting layer 772, and layer 790b.

[0471] When the lower electrode 761 is an anode and the upper electrode 762 is a cathode, the layers 780a and 780b each have one or more of a hole injection layer, a hole transport layer, and an electron blocking layer. The layers 790a and 790b each have one or more of an electron injection layer, an electron transport layer, and a hole blocking layer. When the lower electrode 761 is a cathode and the upper electrode 762 is an anode, the layers 780a and 790a have the opposite structures to those described above, and the layers 780b and 790b also have the opposite structures to those described above.

[0472] When the lower electrode 761 is an anode and the upper electrode 762 is a cathode, for example, the layer 780a may have a hole injection layer, a hole transport layer on the hole injection layer, and an electron blocking layer on the hole transport layer. The layer 790a may have an electron transport layer and a hole blocking layer between the light-emitting layer 771 and the electron transport layer. The layer 780b may have a hole transport layer and an electron blocking layer on the hole transport layer. The layer 790b may have an electron transport layer, an electron injection layer on the electron transport layer, and a hole blocking layer between the light-emitting layer 772 and the electron transport layer. When the lower electrode 761 is a cathode and the upper electrode 762 is an anode, for example, the layer 780a may have an electron injection layer, an electron transport layer on the electron injection layer, and an electron blocking layer on the electron transport layer. Layer 790a may have a hole transport layer and may further have an electron blocking layer between light-emitting layer 771 and the hole transport layer. Layer 780b may have an electron transport layer and may further have a hole blocking layer on the electron transport layer. Layer 790b may have a hole transport layer and a hole injection layer on the hole transport layer and may further have an electron blocking layer between light-emitting layer 772 and the hole transport layer.

[0473] When a light-emitting device with a tandem structure is fabricated, two light-emitting units are stacked via a charge generation layer 785. The charge generation layer 785 has at least a charge generation region. The charge generation layer 785 has a function of injecting electrons into one of the two light-emitting units and injecting holes into the other when a voltage is applied between a pair of electrodes.

[0474] An example of a light emitting device with a tandem structure is shown in FIGS. 26A to 26C.

[0475] 26A shows a configuration having three light-emitting units. In FIG. 26A , a plurality of light-emitting units (light-emitting unit 763a, light-emitting unit 763b, and light-emitting unit 763c) are connected in series via charge generation layers 785. Furthermore, light-emitting unit 763a includes layer 780a, light-emitting layer 771, and layer 790a. Light-emitting unit 763b includes layer 780b, light-emitting layer 772, and layer 790b. Light-emitting unit 763c includes layer 780c, light-emitting layer 773, and layer 790c. Note that layer 780c can have a structure applicable to layers 780a and 780b, and layer 790c can have a structure applicable to layers 790a and 790b.

[0476] 26A , the light-emitting layers 771, 772, and 773 preferably contain light-emitting materials that emit light of the same color. Specifically, the light-emitting layers 771, 772, and 773 may each contain a red (R) light-emitting material (a so-called R\R\R three-stage tandem structure), the light-emitting layers 771, 772, and 773 may each contain a green (G) light-emitting material (a so-called G\G\G three-stage tandem structure), or the light-emitting layers 771, 772, and 773 may each contain a blue (B) light-emitting material (a so-called B\B\B three-stage tandem structure). Note that "a\b" means that a light-emitting unit containing a light-emitting material that emits light of b is provided on a light-emitting unit containing a light-emitting material that emits light of a, via a charge-generating layer, and a and b represent colors.

[0477] 26A , light-emitting materials that emit light of different colors may be used for some or all of the light-emitting layers 771, 772, and 773. Examples of combinations of the light-emitting colors of the light-emitting layers 771, 772, and 773 include a configuration in which two of them are blue (B) and the remaining one is yellow (Y), and a configuration in which one of them is red (R), the other one is green (G), and the remaining one is blue (B).

[0478] Note that the light-emitting materials that emit light of the same color are not limited to the above configuration. For example, as shown in FIG. 26B , a tandem light-emitting device may be used in which light-emitting units having multiple light-emitting layers are stacked. In FIG. 26B , two light-emitting units (light-emitting unit 763a and light-emitting unit 763b) are connected in series via a charge generation layer 785. Furthermore, light-emitting unit 763a includes layer 780a, light-emitting layer 771a, light-emitting layer 771b, light-emitting layer 771c, and layer 790a. Light-emitting unit 763b includes layer 780b, light-emitting layer 772a, light-emitting layer 772b, light-emitting layer 772c, and layer 790b.

[0479] In FIG. 26B , light-emitting materials having complementary colors are selected for the light-emitting layers 771a, 771b, and 771c, and the light-emitting unit 763a is configured to emit white light (W). Light-emitting materials having complementary colors are also selected for the light-emitting layers 772a, 772b, and 772c, and the light-emitting unit 763b is configured to emit white light (W). That is, the structure shown in FIG. 26B is a two-tiered W / W tandem structure. The stacking order of the light-emitting materials having complementary colors is not particularly limited. The implementer can select the optimal stacking order as appropriate. Although not shown, a three-tiered W / W / W tandem structure or a four-tiered or more tandem structure may also be used.

[0480] When a light-emitting device with a tandem structure is used, there are used a two-stage tandem structure of B\Y or Y\B having a light-emitting unit that emits yellow (Y) light and a light-emitting unit that emits blue (B) light, a two-stage tandem structure of R·G\B or B\R·G having a light-emitting unit that emits red (R) and green (G) light and a light-emitting unit that emits blue (B) light, a light-emitting unit that emits yellow (Y) light and a light-emitting unit that emits blue (B) light, and a light-emitting unit that emits blue (B) light. Examples of such a tandem structure include a B\Y\B three-stage tandem structure having, in this order, a light-emitting unit that emits blue (B) light, a light-emitting unit that emits yellow-green (YG) light, and a light-emitting unit that emits blue (B) light, and a B\G\B three-stage tandem structure having, in this order, a light-emitting unit that emits blue (B) light, a light-emitting unit that emits green (G) light, and a light-emitting unit that emits blue (B) light. Note that "a·b" means that one light-emitting unit has a light-emitting material that emits light of a and a light-emitting material that emits light of b.

[0481] As shown in FIG. 26C, a light-emitting unit having one light-emitting layer and a light-emitting unit having multiple light-emitting layers may be combined.

[0482] 26C , a plurality of light-emitting units (light-emitting unit 763a, light-emitting unit 763b, and light-emitting unit 763c) are connected in series via charge generation layers 785. Light-emitting unit 763a includes a layer 780a, a light-emitting layer 771, and a layer 790a. Light-emitting unit 763b includes a layer 780b, a light-emitting layer 772a, a light-emitting layer 772b, a light-emitting layer 772c, and a layer 790b. Light-emitting unit 763c includes a layer 780c, a light-emitting layer 773, and a layer 790c.

[0483] For example, in the configuration shown in Figure 26C, a three-stage tandem structure of B\R·G·YG\B can be applied, in which light-emitting unit 763a is a light-emitting unit that emits blue (B) light, light-emitting unit 763b is a light-emitting unit that emits red (R), green (G), and yellow-green (YG) light, and light-emitting unit 763c is a light-emitting unit that emits blue (B) light.

[0484] For example, the number of stacked light-emitting units and the order of colors can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, and the number of stacked light-emitting layers in light-emitting unit X and the order of colors can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. Furthermore, another layer can be provided between the two light-emitting layers.

[0485] Next, materials that can be used in light-emitting devices will be described.

[0486] Of the lower electrode 761 and the upper electrode 762, a conductive film that transmits visible light is used for the electrode from which light is extracted. A conductive film that reflects visible light is preferably used for the electrode from which light is not extracted. When the display device has a light-emitting device that emits infrared light, a conductive film that transmits visible light and infrared light is preferably used for the electrode from which light is extracted, and a conductive film that reflects visible light and infrared light is preferably used for the electrode from which light is not extracted.

[0487] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, the electrode is preferably disposed between the reflective layer and the EL layer 763. That is, light emitted from the EL layer 763 may be reflected by the reflective layer and extracted from the display device.

[0488] Materials for forming the pair of electrodes of a light-emitting device can include metals, alloys, electrically conductive compounds, and mixtures thereof. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these metals in combination. Other examples of such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Other examples of such materials include aluminum-containing alloys (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and silver-containing alloys, such as an alloy of silver and magnesium and an alloy of silver, palladium, and copper (APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not exemplified above, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these elements, and graphene.

[0489] The light-emitting device preferably has a micro-optical resonator (microcavity) structure. Therefore, one of a pair of electrodes of the light-emitting device preferably has a transmissive and reflective electrode for visible light, and the other preferably has a reflective electrode for visible light. By having the light-emitting device have a microcavity structure, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby intensifying the light emitted from the light-emitting device.

[0490] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of a light-emitting device. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes is 1×10 −２ Preferably, it is Ωcm or less.

[0491] The light-emitting device has at least a light-emitting layer. The light-emitting device may further include a layer other than the light-emitting layer, such as a layer containing a material with high hole injection properties, a material with high hole transport properties, a hole blocking material, a material with high electron transport properties, an electron blocking material, a material with high electron injection properties, or a bipolar material (a material with high electron transport properties and high hole transport properties). For example, the light-emitting device may have, in addition to the light-emitting layer, one or more layers selected from a hole injection layer, a hole transport layer, a hole blocking layer, a charge generation layer, an electron blocking layer, an electron transport layer, and an electron injection layer.

[0492] The light-emitting device may contain either a low-molecular-weight compound or a high-molecular-weight compound, and may also contain an inorganic compound. The layers constituting the light-emitting device may be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, ink-jet printing, or coating.

[0493] The light-emitting layer contains one or more light-emitting materials. As the light-emitting material, a material that emits light of blue, purple, blue-purple, green, yellow-green, yellow, orange, red, or the like is appropriately used. Further, as the light-emitting material, a material that emits near-infrared light can also be used.

[0494] The light-emitting material may include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

[0495] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0496] Examples of phosphorescent materials include organometallic complexes (particularly iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; organometallic complexes (particularly iridium complexes) having a phenylpyridine derivative having an electron-withdrawing group as a ligand; platinum complexes; and rare earth metal complexes.

[0497] The light-emitting layer may contain one or more organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). As the one or more organic compounds, one or both of a material with high hole transporting properties (hole transporting material) and a material with high electron transporting properties (electron transporting material) can be used. As the hole transporting material, a material with high hole transporting properties that can be used in a hole transport layer, which will be described later, can be used. As the electron transporting material, a material with high electron transporting properties that can be used in an electron transporting layer, which will be described later, can be used. Furthermore, as the one or more organic compounds, a bipolar material or a TADF material may be used.

[0498] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This configuration allows for efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, the energy transfer becomes smooth, allowing for efficient emission. This configuration allows for high efficiency, low-voltage operation, and long life of the light-emitting device to be achieved simultaneously.

[0499] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound and a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0500] As the hole transporting material, a material having high hole transporting properties that can be used for the hole transport layer, which will be described later, can be used.

[0501] As the acceptor material, for example, an oxide of a metal belonging to Groups 4 to 8 of the periodic table can be used. Specific examples include molybdenum oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, tungsten oxide, manganese oxide, and rhenium oxide. Among them, molybdenum oxide is particularly preferable because it is stable in the air, has low hygroscopicity, and is easy to handle. Alternatively, an organic acceptor material containing fluorine can be used. Alternatively, an organic acceptor material such as a quinodimethane derivative, a chloranil derivative, or a hexaazatriphenylene derivative can be used.

[0502] For example, as a material with high hole injection properties, a material containing a hole transporting material and an oxide of a metal belonging to Groups 4 to 8 in the periodic table (typically, molybdenum oxide) may be used.

[0503] The hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light emitting layer. The hole transport layer is a layer that contains a hole transport material. The hole transport material is 1×10 −６ cm ２ A substance having a hole mobility of 1 / Vs or more is preferred. Note that other materials can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.), an aromatic amine (a compound having an aromatic amine skeleton), or the like, is preferred.

[0504] The electron blocking layer is provided in contact with the light-emitting layer. The electron blocking layer is a layer containing a material that has hole transport properties and can block electrons. The electron blocking layer can be made of a material that has electron blocking properties among the hole transport materials described above.

[0505] The electron blocking layer has hole transport properties and can therefore also be called a hole transport layer. Furthermore, a layer of the hole transport layer that has electron blocking properties can also be called an electron blocking layer.

[0506] The electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light emitting layer. The electron transport layer is a layer that contains an electron transporting material. −６ cm ２ / Vs or more is preferred. Note that other materials can also be used as long as they have a higher electron transporting property than holes. As the electron-transporting material, materials with a high electron transporting property such as metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, and metal complexes having a thiazole skeleton can be used. Examples of the electron-transporting material include oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and other π-electron-deficient heteroaromatic compounds including nitrogen-containing heteroaromatic compounds.

[0507] The hole-blocking layer is provided in contact with the light-emitting layer. The hole-blocking layer is a layer containing a material that has electron transport properties and can block holes. The hole-blocking layer can be made of a material that has hole-blocking properties and is selected from the above electron-transporting materials.

[0508] The hole blocking layer has electron transport properties and can therefore also be called an electron transport layer. Furthermore, a layer of the electron transport layer that has hole blocking properties can also be called a hole blocking layer.

[0509] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer and contains a material with high electron injection properties. Examples of the material with high electron injection properties include alkali metals, alkaline earth metals, and compounds thereof. Examples of the material with high electron injection properties include a composite material containing an electron transport material and a donor material (electron donor material).

[0510] It is preferable that the lowest unoccupied molecular orbital (LUMO) level of a material with high electron injection properties has a small difference (specifically, 0.5 eV or less) from the work function value of the material used for the cathode.

[0511] The electron injection layer may contain, for example, lithium, cesium, ytterbium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF ｘ , where X is an arbitrary number), 8-(quinolinolato)lithium (abbreviation: Liq), 2-(2-pyridyl)phenolatolithium (abbreviation: LiPP), 2-(2-pyridyl)-3-pyridinolatolithium (abbreviation: LiPPy), 4-phenyl-2-(2-pyridyl)phenolatolithium (abbreviation: LiPPP), lithium oxide (LiO ｘ ), alkali metals such as cesium carbonate, alkaline earth metals, or compounds thereof can be used. The electron injection layer may have a stacked structure of two or more layers. For example, the stacked structure may include a structure in which lithium fluoride is used as a first layer and ytterbium is provided as a second layer.

[0512] The electron injection layer may include an electron transporting material. For example, a compound having an unshared electron pair and an electron-deficient heteroaromatic ring can be used as the electron transporting material. Specifically, a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), and a triazine ring can be used.

[0513] The LUMO level of an organic compound having an unshared electron pair is preferably −3.6 eV or more and −2.3 eV or less. Generally, the highest occupied molecular orbital (HOMO) level and the LUMO level of an organic compound can be estimated by CV (cyclic voltammetry), photoelectron spectroscopy, optical absorption spectroscopy, inverse photoelectron spectroscopy, or the like.

[0514] For example, 4,7-diphenyl-1,10-phenanthroline (abbreviation: BPhen), 2,9-di(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen), 2,2′-(1,3-phenylene)bis(9-phenyl-1,10-phenanthroline) (abbreviation: mPPhen2P), diquinoxalino[2,3-a:2′,3′-c]phenazine (abbreviation: HATNA), 2,4,6-tris[3′-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviation: TmPPPyTz), etc. can be used as the organic compound having an unshared electron pair. Note that NBPhen has a higher glass transition point (Tg) and is superior in heat resistance compared to BPhen.

[0515] As described above, the charge generation layer has at least a charge generation region. The charge generation region preferably contains an acceptor material, for example, a hole transport material and an acceptor material applicable to the hole injection layer.

[0516] The charge generation layer preferably has a layer containing a material with high electron injection properties. This layer may also be called an electron injection buffer layer. The electron injection buffer layer is preferably provided between the charge generation region and the electron transport layer. By providing the electron injection buffer layer, the injection barrier between the charge generation region and the electron transport layer can be alleviated, so that electrons generated in the charge generation region can be easily injected into the electron transport layer.

[0517] The electron injection buffer layer preferably contains an alkali metal or an alkaline earth metal, and may contain, for example, an alkali metal compound or an alkaline earth metal compound. Specifically, the electron injection buffer layer preferably contains an inorganic compound containing an alkali metal and oxygen, or an inorganic compound containing an alkaline earth metal and oxygen, and may contain an inorganic compound containing lithium and oxygen (lithium oxide (Li ２ In addition, the electron injection buffer layer can be suitably made of the materials applicable to the electron injection layer described above.

[0518] The charge generation layer preferably has a layer containing a material with high electron transport properties. This layer can also be called an electron relay layer. The electron relay layer is preferably provided between the charge generation region and the electron injection buffer layer. When the charge generation layer does not have an electron injection buffer layer, the electron relay layer is preferably provided between the charge generation region and the electron transport layer. The electron relay layer has the function of preventing interaction between the charge generation region and the electron injection buffer layer (or the electron transport layer) and smoothly transferring electrons.

[0519] The electron relay layer is preferably made of a phthalocyanine material such as copper (II) phthalocyanine (abbreviated as CuPc) or a metal complex having a metal-oxygen bond and an aromatic ligand.

[0520] It should be noted that the charge generation region, electron injection buffer layer, and electron relay layer may not be clearly distinguishable from one another due to their cross-sectional shapes or characteristics.

[0521] The charge generation layer may have a donor material instead of an acceptor material. For example, the charge generation layer may have a layer containing an electron transport material and a donor material that can be used for the electron injection layer.

[0522] When light-emitting units are stacked, an increase in driving voltage can be suppressed by providing a charge generating layer between two light-emitting units.

[0523] This embodiment mode can be combined with other embodiment modes or examples as appropriate.

[0524] Embodiment 5 In this embodiment, a light-receiving device that can be used for a display device of one embodiment of the present invention and a display device having a light detection function will be described.

[0525] 27A, the light-receiving device has a layer 765 between a pair of electrodes (a lower electrode 761 and an upper electrode 762). The layer 765 has at least one active layer and may further have other layers.

[0526] Fig. 27B shows a modification of the layer 765 included in the light-receiving device shown in Fig. 27A. Specifically, the light-receiving device shown in Fig. 27B includes a layer 766 on a lower electrode 761, an active layer 767 on the layer 766, a layer 768 on the active layer 767, and an upper electrode 762 on the layer 768.

[0527] The active layer 767 functions as a photoelectric conversion layer.

[0528] When the lower electrode 761 is an anode and the upper electrode 762 is a cathode, the layer 766 includes a hole transport layer and / or an electron blocking layer. The layer 768 includes an electron transport layer and / or a hole blocking layer. When the lower electrode 761 is a cathode and the upper electrode 762 is an anode, the layers 766 and 768 have the opposite structures.

[0529] Next, materials that can be used for the light-receiving device will be described.

[0530] The light-receiving device may be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-receiving device may be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, inkjet printing, or coating.

[0531] The active layer of the light-receiving device includes a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors containing organic compounds. In this embodiment, an example in which an organic semiconductor is used as the semiconductor of the active layer is shown. Using an organic semiconductor is preferable because the light-emitting layer and the active layer can be formed by the same method (e.g., vacuum deposition), allowing the use of a common manufacturing device.

[0532] As the n-type semiconductor material of the active layer, fullerene (e.g., C ６０ , C ７０ Examples of the fullerene derivative include [6,6]-Phenyl-C71-butylic acid methyl ester (abbreviation: PC70BM), [6,6]-Phenyl-C61-butylic acid methyl ester (abbreviation: PC60BM), and 1',1",4',4"-Tetrahydro-di[1,4]methanenaphthaleno[1,2:2',3',56,60:2"3"][5,6]fullerene-C60 (abbreviation: ICBA).

[0533] Examples of n-type semiconductor materials include perylene tetracarboxylic acid derivatives such as N,N′-dimethyl-3,4,9,10-perylenetetracarboxylic acid diimide (abbreviation: Me-PTCDI) and 2,2′-(5,5′-(thieno[3,2-b]thiophene-2,5-diyl)bis(thiophene-5,2-diyl))bis(methane-1-yl-1-ylidene)dimalononitrile (abbreviation: FT2TDMN).

[0534] Examples of n-type semiconductor materials include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, naphthalene derivatives, anthracene derivatives, coumarin derivatives, rhodamine derivatives, triazine derivatives, and quinone derivatives.

[0535] Examples of p-type semiconductor materials contained in the active layer include electron-donating organic semiconductor materials such as copper(II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), zinc phthalocyanine (ZnPc), tin phthalocyanine (SnPc), quinacridone, and rubrene.

[0536] Examples of p-type semiconductor materials include carbazole derivatives, thiophene derivatives, furan derivatives, compounds having an aromatic amine skeleton, etc. Further examples of p-type semiconductor materials include naphthalene derivatives, anthracene derivatives, pyrene derivatives, triphenylene derivatives, fluorene derivatives, pyrrole derivatives, benzofuran derivatives, benzothiophene derivatives, indole derivatives, dibenzofuran derivatives, dibenzothiophene derivatives, indolocarbazole derivatives, porphyrin derivatives, phthalocyanine derivatives, naphthalocyanine derivatives, quinacridone derivatives, rubrene derivatives, tetracene derivatives, polyphenylenevinylene derivatives, polyparaphenylene derivatives, polyfluorene derivatives, polyvinylcarbazole derivatives, and polythiophene derivatives.

[0537] The HOMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the HOMO level of the electron-accepting organic semiconductor material, and the LUMO level of the electron-donating organic semiconductor material is preferably shallower (higher) than the LUMO level of the electron-accepting organic semiconductor material.

[0538] It is preferable to use a spherical fullerene as the electron-accepting organic semiconductor material and a planar organic semiconductor material as the electron-donating organic semiconductor material. Molecules with similar shapes tend to aggregate together, and when molecules of the same type aggregate, the energy levels of their molecular orbitals become close, which can improve carrier transport properties.

[0539] The active layer can be formed using a polymer compound such as Poly[[4,8-bis[5-(2-ethylhexyl)-2-thienyl]benzo[1,2-b:4,5-b']dithiophene-2,6-diyl]-2,5-thiophenediyl[5,7-bis(2-ethylhexyl)-4,8-dioxo-4H,8H-benzo[1,2-c:4,5-c']dithiophene-1,3-diyl]] polymer (abbreviated as PBDB-T) or a PBDB-T derivative, which functions as a donor. For example, a method of dispersing an acceptor material in PBDB-T or a PBDB-T derivative can be used.

[0540] For example, the active layer is preferably formed by co-evaporating an n-type semiconductor and a p-type semiconductor, or may be formed by laminating an n-type semiconductor and a p-type semiconductor.

[0541] The active layer may contain three or more materials. For example, in order to broaden the absorption wavelength range, a third material may be mixed in addition to an n-type semiconductor material and a p-type semiconductor material. In this case, the third material may be a low-molecular-weight compound or a high-molecular-weight compound.

[0542] The light-receiving device may further include a layer other than the active layer that contains a material with high hole transport properties, a material with high electron transport properties, or a bipolar material (a material with high electron transport properties and hole transport properties). Furthermore, without being limited to the above, the light-receiving device may further include a layer that contains a material with high hole injection properties, a hole blocking material, a material with high electron injection properties, or an electron blocking material. For the layers other than the active layer of the light-receiving device, for example, materials that can be used in the above-mentioned light-emitting devices can be used.

[0543] For example, the hole transport material or electron blocking material may be a polymer compound such as poly(3,4-ethylenedioxythiophene) / poly(styrenesulfonic acid) (PEDOT / PSS), or an inorganic compound such as molybdenum oxide or copper iodide (CuI). The electron transport material or hole blocking material may be an inorganic compound such as zinc oxide (ZnO), or an organic compound such as polyethyleneimine ethoxylate (PEIE). The light-receiving device may have a mixed film of PEIE and ZnO, for example.

[0544] [Display Device Having Light Detection Function] In a display device according to one embodiment of the present invention, light-emitting devices are arranged in a matrix in a display portion, and an image can be displayed on the display portion. Furthermore, light-receiving devices are arranged in a matrix in the display portion, and the display portion has one or both of an imaging function and a sensing function in addition to an image display function. The display portion can be used as an image sensor or a touch sensor. That is, by detecting light in the display portion, an image can be captured or the proximity or contact of an object (such as a finger, a hand, or a pen) can be detected.

[0545] Furthermore, in the display device of one embodiment of the present invention, the light-emitting device can be used as a light source for a sensor. In the display device of one embodiment of the present invention, when light emitted from the light-emitting device included in the display portion is reflected (or scattered) by an object, the light-receiving device can detect the reflected light (or scattered light), thereby enabling imaging or touch detection even in a dark place.

[0546] Therefore, a light receiving unit and a light source are not required to be provided separately from the display device, and the number of components in the electronic device can be reduced. For example, a biometric authentication device or a capacitive touch panel for scrolling or the like is not required to be provided separately in the electronic device. Therefore, by using the display device of one embodiment of the present invention, an electronic device with reduced manufacturing costs can be provided.

[0547] Specifically, a display device according to one embodiment of the present invention has a light-emitting device and a light-receiving device in each pixel. In the display device according to one embodiment of the present invention, an organic EL device is used as the light-emitting device, and an organic photodiode is used as the light-receiving device. The organic EL device and the organic photodiode can be formed on the same substrate. Therefore, the organic photodiode can be built into a display device using an organic EL device.

[0548] In a display device having a light-emitting device and a light-receiving device in each pixel, the pixel has a light-receiving function, and therefore it is possible to detect contact or proximity of an object while displaying an image. For example, instead of displaying an image using all of the sub-pixels of the display device, some of the sub-pixels can emit light as a light source, while other sub-pixels can detect light, and the remaining sub-pixels can display the image.

[0549] When the light receiving device is used as an image sensor, the display device can capture an image using the light receiving device. For example, the display device of the present embodiment can be used as a scanner.

[0550] For example, an image sensor can be used to capture images for personal authentication using fingerprints, palm prints, irises, pulse patterns (including vein patterns and arterial patterns), faces, or the like.

[0551] For example, an image sensor can be used to capture images of the area around the eye, the surface of the eye, or the inside of the eye (such as the fundus) of a user of the wearable device. Therefore, the wearable device can have a function to detect one or more of the user's blinking, movement of the pupil, and movement of the eyelid.

[0552] The light receiving device can be used as a touch sensor (also called a direct touch sensor) or a near-touch sensor (also called a hover sensor, hover touch sensor, non-contact sensor, or touchless sensor).

[0553] Here, the touch sensor or near-touch sensor can detect the proximity or contact of an object (such as a finger, a hand, or a pen).

[0554] A touch sensor can detect an object when the display device and the object are in direct contact with each other. A near-touch sensor can detect an object even when the object does not touch the display device. For example, a configuration in which the display device can detect an object when the distance between the display device and the object is between 0.1 mm and 300 mm, preferably between 3 mm and 50 mm, is preferred. This configuration allows the display device to be operated without the object directly touching it; in other words, it allows the display device to be operated in a non-contact (touchless) manner. This configuration reduces the risk of the display device becoming dirty or scratched, or allows the object to operate the display device without directly touching dirt (e.g., dust, viruses, etc.) attached to the display device.

[0555] The display device of one embodiment of the present invention can have a variable refresh rate. For example, the refresh rate can be adjusted (for example, within a range of 1 Hz to 240 Hz) depending on content displayed on the display device, thereby reducing power consumption. Furthermore, the drive frequency of the touch sensor or near-touch sensor may be changed depending on the refresh rate. For example, when the refresh rate of the display device is 120 Hz, the drive frequency of the touch sensor or near-touch sensor can be configured to be higher than 120 Hz (typically, 240 Hz). This configuration enables low power consumption and an increased response speed of the touch sensor or near-touch sensor.

[0556] The display device 200 shown in FIGS. 27C to 27E includes a layer 353 having a light-receiving device, a functional layer 355, and a layer 357 having a light-emitting device between a substrate 351 and a substrate 359.

[0557] The functional layer 355 includes a circuit for driving a light-receiving device and a circuit for driving a light-emitting device. The functional layer 355 can be provided with one or more of a switch, a transistor, a capacitor, a resistor, a wiring, a terminal, and the like. Note that when the light-emitting device and the light-receiving device are driven by a passive matrix method, a structure without a switch or a transistor may be used. The transistors provided in the functional layer 355 can preferably be the transistors described in Embodiment 1.

[0558] 27C , light emitted by a light-emitting device in layer 357 having a light-emitting device is reflected by finger 352 that touches display device 200, and the reflected light is detected by a light-receiving device in layer 353 having a light-receiving device. This makes it possible to detect that finger 352 has touched display device 200.

[0559] As shown in Figures 27D and 27E, the display device may have a function of detecting or capturing an image of an object that is close to (not in contact with) the display device. Figure 27D shows an example of detecting a person's finger, and Figure 27E shows an example of detecting information about the periphery, surface, or interior of a person's eye (such as the number of blinks, eyeball movement, eyelid movement, etc.).

[0560] This embodiment mode can be combined with other embodiment modes or examples as appropriate.

[0561] Embodiment 6 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS. 28A to 30G.

[0562] The electronic devices of this embodiment include the display device of one embodiment of the present invention in their display portions. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device of one embodiment of the present invention can be used in the display portions of various electronic devices.

[0563] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0564] In particular, the display device of one embodiment of the present invention can be suitably used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.

[0565] The display device of one embodiment of the present invention preferably has an extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display device having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. Furthermore, the screen ratio (aspect ratio) of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0566] The electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0567] The electronic device of the present embodiment can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out programs or data recorded on a recording medium, etc.

[0568] 28A to 28D , examples of wearable devices that can be worn on the head are described. These wearable devices have at least one of the following functions: a function for displaying AR content, a function for displaying VR content, a function for displaying SR content, and a function for displaying MR content. By having an electronic device with the function for displaying at least one of AR, VR, SR, and MR content, it is possible to enhance the sense of immersion felt by the user.

[0569] The electronic device 700A shown in FIG. 28A and the electronic device 700B shown in FIG. 28B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0570] The display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can provide an extremely high-definition display.

[0571] The electronic device 700A and the electronic device 700B can each project an image displayed on the display panel 751 onto a display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.

[0572] Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image in front of them as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

[0573] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0574] The electronic device 700A and the electronic device 700B are provided with batteries, which can be charged wirelessly and / or by wire.

[0575] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. The touch sensor module can detect a tap operation, a slide operation, or the like by the user and perform various processes. For example, a tap operation can perform processes such as pausing or resuming a video, and a slide operation can perform processes such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can expand the range of operations.

[0576] The touch sensor module can employ various touch sensors, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, an optical type, etc. In particular, it is preferable to employ a capacitance type or an optical type sensor in the touch sensor module.

[0577] When an optical touch sensor is used, a photoelectric conversion device (also called a photoelectric conversion element) can be used as the light receiving device. The active layer of the photoelectric conversion device can be made of either or both of an inorganic semiconductor and an organic semiconductor.

[0578] The electronic device 800A shown in Figure 28C and the electronic device 800B shown in Figure 28D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0579] The display device of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high definition can be provided, which allows a user to feel a high sense of immersion.

[0580] The display unit 820 is provided inside the housing 821 at a position where it can be viewed through the lens 832. Also, by displaying different images on the pair of display units 820, it is possible to perform three-dimensional display using parallax.

[0581] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view an image displayed on the display unit 820 through the lens 832.

[0582] It is preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the left and right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.

[0583] The mounting unit 823 allows the user to mount the electronic device 800A or the electronic device 800B on the head. Note that, in Fig. 28C and other figures, the mounting unit 823 is shaped like the temples of glasses (also called joints or temples), but is not limited to this. The mounting unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0584] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.

[0585] Although an example including the imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. For example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) may be used as the detection unit. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0586] The electronic device 800A may have a vibration mechanism to function as bone conduction earphones. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This allows a user to enjoy video and audio simply by wearing the electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0587] The electronic device 800A and the electronic device 800B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device.

[0588] The electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 750. The earphone 750 includes a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, an electronic device 700A shown in FIG. 28A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, an electronic device 800A shown in FIG. 28C has a function of transmitting information to the earphone 750 through the wireless communication function.

[0589] The electronic device may have an earphone unit. Electronic device 700B shown in Fig. 28B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.

[0590] Similarly, electronic device 800B shown in Fig. 28D has earphone unit 827. For example, earphone unit 827 and control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or wearing unit 823. Furthermore, earphone unit 827 and wearing unit 823 may have magnets. This allows earphone unit 827 to be fixed to wearing unit 823 by magnetic force, which is preferable as it makes storage easier.

[0591] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. The audio input mechanism may use, for example, a sound collection device such as a microphone. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0592] As described above, the electronic devices of one embodiment of the present invention can be suitably applied to both glasses-type electronic devices (such as the electronic devices 700A and 700B) and goggle-type electronic devices (such as the electronic devices 800A and 800B).

[0593] An electronic device according to one embodiment of the present invention can transmit information to an earphone via a wired or wireless connection.

[0594] The electronic device 6500 shown in FIG. 29A is a portable information terminal that can be used as a smartphone.

[0595] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

[0596] The display device of one embodiment of the present invention can be applied to the display portion 6502 .

[0597] FIG. 29B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0598] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0599] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0600] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0601] The flexible display device of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, the thickness of the electronic device can be reduced and a large-capacity battery 6518 can be mounted thereon. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the display portion 6502, an electronic device with a narrow frame can be realized.

[0602] 29C shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0603] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0604] 29C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0605] The television device 7100 is configured to include a receiver, a modem, and the like. Ordinary television broadcasts can be received using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0606] 29D shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214. The housing 7211 includes a display portion 7000.

[0607] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0608] 29E and 29F show an example of digital signage.

[0609] 29E includes a housing 7301, a display portion 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0610] 29F shows a digital signage 7400 attached to a cylindr...

Claims

1. It comprises a first transistor, a second transistor, and an insulating layer. The first transistor described above includes a first conductive layer, a second conductive layer, a first semiconductor layer, a first gate insulating layer, and a first gate electrode. The second transistor comprises a third conductive layer, a fourth conductive layer, a second semiconductor layer, a second gate insulating layer, and the second conductive layer. The insulating layer is in contact with the upper surface of the first conductive layer and the lower surface of the second semiconductor layer, and has an opening that reaches the first conductive layer. The first conductive layer functions as either the source electrode or the drain electrode of the first transistor. The second conductive layer has the function of being the other of the source electrode or drain electrode of the first transistor, and the function of being the second gate electrode of the second transistor. The third conductive layer functions as either the source electrode or the drain electrode of the second transistor. The fourth conductive layer functions as the other of the source electrode or drain electrode of the second transistor. The first semiconductor layer is in contact with the upper surface of the first conductive layer, the inner wall of the opening, and the side and upper surfaces of the second conductive layer. The first gate electrode is provided such that it has a region that overlaps with the first semiconductor layer via the first gate insulating layer. The second conductive layer is provided such that it has a region that overlaps with the second semiconductor layer via the second gate insulating layer. The third conductive layer is in contact with one side and top surface of the side edge of the second semiconductor layer. The fourth conductive layer is in contact with the other side and top surface of the side edge of the second semiconductor layer. Semiconductor equipment.

2. In claim 1, The first semiconductor layer and the second semiconductor layer each have an oxide semiconductor. Semiconductor equipment.

3. It comprises a first transistor, a second transistor, and an insulating layer. The first transistor described above includes a first conductive layer, a second conductive layer, a first semiconductor layer, a gate insulating layer, and a first gate electrode. The second transistor comprises the second conductive layer, the third conductive layer, the second semiconductor layer, the gate insulating layer, and the second gate electrode. The insulating layer is in contact with the upper surface of the first conductive layer and the lower surface of the second semiconductor layer, and has an opening that reaches the first conductive layer. The first semiconductor layer is in contact with the upper surface of the first conductive layer, the inner wall of the opening, and one side and upper surface of the source electrode or drain electrode of the second transistor. The first conductive layer functions as either the source electrode or the drain electrode of the first transistor. The second conductive layer has the function of being the other of the source electrode or drain electrode of the first transistor, and the function of being the source electrode or drain electrode of the second transistor. The third conductive layer functions as the other of the source electrode or drain electrode of the second transistor. The first gate electrode is provided such that it has a region that overlaps with the first semiconductor layer via the gate insulating layer. The second conductive layer is in contact with one side and top surface of the side edge of the second semiconductor layer. The third conductive layer is in contact with the other side and top surface of the side edge of the second semiconductor layer. The second gate electrode is provided such that it has a region that overlaps with the second semiconductor layer via the gate insulating layer. Semiconductor equipment.

4. In claim 3, The first semiconductor layer and the second semiconductor layer each have an oxide semiconductor. Semiconductor equipment.

5. A first conductive film is formed, The first conductive film is processed to form a first conductive layer. A first insulating layer is formed on the first conductive layer. A first metal oxide film is formed on the first insulating layer. The first metal oxide film is processed to form a first semiconductor layer. A second conductive film is formed on the first semiconductor layer. The second conductive film is processed to form a second conductive layer and a third conductive layer, respectively, which cover a part of the upper surface and the side surface of the first semiconductor layer. A second insulating layer is formed on the first semiconductor layer, the second conductive layer, the third conductive layer, and the first insulating layer. A third conductive film is formed on the second insulating layer. The third conductive film, the second insulating layer, and the first insulating layer are processed to form openings in the third conductive film, the second insulating layer, and the first insulating layer. The third conductive film is processed to form a fourth conductive layer. A second metal oxide film is formed so as to cover the upper surface of the first conductive layer, the inner wall of the opening, the upper surface of the fourth conductive layer, and a portion of the upper surface of the second insulating layer. The second metal oxide film is processed to have a region that overlaps with the inner wall of the opening, thereby forming a second semiconductor layer. A third insulating layer is formed on the second semiconductor layer, the fourth conductive layer, and the second insulating layer. A fourth conductive film is formed on the third insulating layer. The fourth conductive film is processed to have a region that overlaps with the opening to form a fifth conductive layer. Method for manufacturing semiconductor devices.

6. In claim 5, After forming the first insulating layer, a process is performed to supply oxygen to the first insulating layer. Method for manufacturing semiconductor devices.