Gate drive device and power conversion device

Abstract

A gate drive device 20H comprises: a gate drive unit 21H that outputs power for switching the on / off of a semiconductor switching element 30H; a speed control unit 22H that controls at least one of the turn-on speed and the turn-off speed of the semiconductor switching element 30H; and a speed switching unit 23H that switches at least one of the turn-on speed and the turn-off speed in accordance with an instruction from the speed control unit 22H. The speed switching unit 23H includes a plurality of impedance elements (for example, gate resistances RG1 to RG3) and switch units SW1 to SW3 that controls power which is output from the gate drive unit 21H and passes through each of the plurality of impedance elements. The speed control unit 22H controls the switch units SW1 to SW3 on the basis of the output current IL flowing through the semiconductor switching element 30H.

Description

Gate drivers, power converters

[0001] The present disclosure relates to a gate driver and a power conversion device using the same.

[0002] 2. Description of the Related Art A power conversion device such as an inverter is equipped with a gate driver as a means for driving semiconductor switching elements.

[0003] An example of the related prior art is disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0004] JP 2011-166920 A

[0005] However, conventional gate drive devices have room for improvement in switching loss.

[0006] For example, a gate drive device disclosed in this specification includes a gate drive unit configured to output power for switching a semiconductor switching element on and off, a speed control unit configured to control at least one of a turn-on speed and a turn-off speed of the semiconductor switching element, and a speed switching unit configured to switch at least one of the turn-on speed and the turn-off speed in response to an instruction from the speed control unit, wherein the speed switching unit includes a plurality of impedance elements and a switch unit configured to control the power output from the gate drive unit and passing through each of the plurality of impedance elements, and the speed control unit controls the switch unit based on the output current flowing through the semiconductor switching element.

[0007] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto.

[0008] According to the present disclosure, it is possible to provide a gate driver with small switching loss and a power conversion device using the same.

[0009] FIG. 1 is a diagram illustrating a comparative example of a power conversion device. FIG. 2 is a diagram illustrating a first embodiment of a power conversion device. FIG. 3 is a diagram illustrating a second embodiment of a power conversion device. FIG. 4 is a diagram illustrating a third embodiment of a power conversion device. FIG. 5 is a diagram illustrating an example of a configuration of a speed control unit. FIG. 6 is a diagram illustrating an example of speed switching control in the third embodiment. FIG. 7 is a diagram illustrating a fourth embodiment of a power conversion device. FIG. 8 is a diagram illustrating a first example of speed switching control in the fourth embodiment. FIG. 9 is a diagram illustrating a second example of speed switching control in the fourth embodiment. FIG. 10 is a diagram illustrating a fifth embodiment of a power conversion device. FIG. 11 is a diagram illustrating an example of speed switching control in the fifth embodiment. FIG. 12 is a diagram illustrating a sixth embodiment of a power conversion device. FIG. 13 is a diagram illustrating an example of speed switching control in the sixth embodiment. FIG. 14 is a diagram illustrating a seventh embodiment of a power conversion device. FIG. 15 is a diagram illustrating an example of speed switching control in the seventh embodiment. FIG. 16 is a diagram illustrating an eighth embodiment of a power conversion device. FIG. 17 is a diagram illustrating an example of speed switching control in the eighth embodiment. FIG. 18 is a diagram illustrating a ninth embodiment of a power conversion device. Fig. 19 is a diagram illustrating a tenth embodiment of a power conversion device. Fig. 20 is a diagram illustrating an eleventh embodiment of a power conversion device. Fig. 21 is a diagram illustrating an example of speed switching control in the eleventh embodiment. Fig. 22 is a diagram illustrating a twelfth embodiment of a power conversion device. Fig. 23 is a diagram illustrating an example of speed switching control in the twelfth embodiment. Fig. 24 is a diagram illustrating a thirteenth embodiment of a power conversion device. Fig. 25 is a diagram illustrating an example of speed switching control in the thirteenth embodiment. Fig. 26 is a diagram illustrating a fourteenth embodiment of a power conversion device. Fig. 27 is a diagram illustrating an example of speed switching control in the fourteenth embodiment. Fig. 28 is a diagram illustrating an example of a configuration of a reset circuit.

[0010] 1 is a diagram showing a comparative example (= a general circuit configuration to be compared with the embodiments described later) of a power conversion device 1. The power conversion device 1 of this comparative example generates a desired output voltage VOUT from a DC voltage VDC and supplies the output voltage VOUT to a load.

[0011] Referring to the figure, the power conversion device 1 includes a control device 10, a gate drive device 20, and semiconductor switching elements 30H and 30L. The power conversion device 1 may be, for example, an AC / DC converter or a DC / DC converter.

[0012] The control device 10 generates control signals GSH and GSL based on the DC voltage VDC and the output current IL to control the gate driver 20. Although not explicitly shown in the figure, the control device 10 also includes an output feedback loop that controls the control signals GSH and GSL so that the output voltage VOUT matches a target value.

[0013] The gate driver 20 receives control signals GSH and GSL output from the control device 10, and generates gate signals GH and GL for turning on / off the semiconductor switching elements 30H and 30L, respectively.

[0014] Referring to this figure, the gate drive device 20 includes an upper gate drive section 21H that drives the semiconductor switching element 30H, and a lower gate drive section 21L that drives the semiconductor switching element 30L.

[0015] The gate drivers 21H and 21L generate gate signals GH and GL by outputting power for switching the semiconductor switching elements 30H and 30L on / off in accordance with control signals GSH and GSL, respectively, and drive the semiconductor switching elements 30H and 30L.

[0016] Gate resistors RGH and RGL are connected between the output terminals of the gate drivers 21H and 21L and the gates of the semiconductor switching elements 30H and 30L (=application terminals to which the gate signals GH and GL are applied).

[0017] The semiconductor switching elements 30H and 30L are connected in series between an application terminal of a DC voltage VDC and an application terminal of a ground voltage GND to form a half-bridge output stage, and output an output current IL from a connection node between them.

[0018] The semiconductor switching elements 30H and 30L are turned on / off in response to gate signals GH and GL, respectively. For example, if the semiconductor switching elements 30H and 30L are both N-channel metal oxide semiconductor field effect transistors (MOSFETs), the semiconductor switching elements 30H and 30L are turned on when the gate signals GH and GL are at high levels, and turned off when the gate signals GH and GL are at low levels.

[0019] Furthermore, when the semiconductor switching elements 30H and 30L are each an N-channel MOSFET, the semiconductor switching elements 30H and 30L are each accompanied by a body diode with the drain of the semiconductor switching elements 30H and 30L as the cathode and the source of the semiconductor switching elements 30H and 30L as the anode.

[0020] <Considerations Regarding Switching Loss> In a power conversion device 1 such as an inverter, the resistance values ​​of the gate resistors RGH and RGL used to drive the semiconductor switching elements 30H and 30L, respectively, are determined taking into consideration the surge voltage that occurs when the device is stopped due to overcurrent or overvoltage protection.

[0021] However, in a normal state where overcurrent and overvoltage protection are not activated, the output current IL is smaller than in an abnormal state where overcurrent and overvoltage protection are activated. Therefore, the resistance values ​​of the gate resistors RGH and RGL, which are set with safety in mind in an abnormal state, are not necessarily appropriate in a normal state, and there is a risk that switching loss will increase and efficiency will deteriorate. In particular, in the light load region where the output current IL is small, the proportion of switching loss is high, and the deterioration in efficiency can be significant.

[0022] In the following, in view of the above considerations, a novel embodiment capable of reducing switching loss will be proposed.

[0023] <First Embodiment> Figure 2 is a diagram showing a first embodiment of a power conversion device 1. The power conversion device 1 of this embodiment is based on the comparative example (Figure 1) described above, but instead of the gate drive device 20, it includes a gate drive device 20H that drives an upper semiconductor switching element 30H and a gate drive device 20L that drives a lower semiconductor switching element 30L. Note that the circuit configurations of the gate drive devices 20H and 20L may be basically the same. Therefore, the following will describe the gate drive device 20H in detail, and a description of the gate drive device 20L will be omitted.

[0024] The gate driving device 20H includes a gate driving unit 21, a speed control unit 22, and a speed switching unit 23.

[0025] The gate driver 21 is a circuit portion corresponding to the gate driver 21H in FIG. 1, and outputs power for switching on / off the semiconductor switching element 30H in response to a control signal GSH output from the control device 10.

[0026] Specifically, when the semiconductor switching element 30H is turned on, the gate signal GH rises from low level to high level, and a charging current is generated from the gate driver 21 to the input capacitance Ciss (not shown) of the semiconductor switching element 30H.

[0027] On the other hand, when the semiconductor switching element 30H is turned off, the gate signal GH falls from high level to low level, and a discharge current is generated from the input capacitance Ciss (not shown) of the semiconductor switching element 30H to the gate driver 21.

[0028] The speed control unit 22 generates a flag signal FLAG for controlling at least one of the turn-on speed and the turn-off speed of the semiconductor switching element 30H based on information about the output current IL flowing through the semiconductor switching element 30H or 30L.

[0029] The speed switching unit 23 switches at least one of the turn-on speed and the turn-off speed in response to an instruction (=flag signal FLAG) from the speed control unit 22. For example, the speed switching unit 23 includes gate resistors RG1 to RG3 (=corresponding to a plurality of impedance elements) and switch units SW1 to SW3 configured to control the power output from the gate driving unit 21 and passing through the gate resistors RG1 to RG3, respectively.

[0030] Specifically, referring to this diagram, gate resistors RG1 to RG3 are connected in parallel between the gate driver 21 and the gate of the semiconductor switching element 30H (= the terminal to which the gate signal GH is applied). Furthermore, switch units SW1 to SW3 are connected in series to the gate resistors RG1 to RG3, respectively. Therefore, the combined resistance value (= gate resistance value) of the gate resistors RG1 to RG3 is switched depending on the on / off state of the switch units SW1 to SW3.

[0031] For example, when switch SW1 is on and switch SW2 and SW3 are off, the gate resistance value is RG1. Also, when switch SW1 and SW2 are on and switch SW3 is off, the gate resistance value is the combined resistance value of the parallel-connected gate resistors RG1 and RG2. Furthermore, when switch SW1 to SW3 are all on, the gate resistance value is the combined resistance value of the parallel-connected gate resistors RG1 to RG3.

[0032] The higher the gate resistance value, the slower the rise and fall of the gate signal GH, which reduces the turn-on and turn-off speeds of the semiconductor switching element 30H and increases switching loss. Conversely, the lower the gate resistance value, the steeper the rise and fall of the gate signal GH, which increases the turn-on and turn-off speeds of the semiconductor switching element 30H and reduces switching loss.

[0033] The speed control unit 22 may perform on / off control of each of the switches SW1 to SW3 based on information about the output current IL. For example, in a light load region where the output current IL is small, the gate resistance value may be reduced to increase the turn-on and turn-off speeds of the semiconductor switching element 30H.

[0034] Such speed control makes it possible to improve the efficiency of the power conversion device 1 in a light load region where the ratio of switching loss is high.

[0035] <Second embodiment> Fig. 3 is a diagram showing a second embodiment of the power conversion device 1. The power conversion device 1 of this embodiment is based on the first embodiment (Fig. 2) described above, but is provided with separate control systems for the turn-on speed and the turn-off speed.

[0036] Referring to the figure, the gate driver 21 includes transistors 21a and 21b (for example, N-channel MOSFETs) and a controller 21c.

[0037] The drain of the transistor 21a is connected to a terminal to which a first drive voltage VG1 is applied. The source of the transistor 21a is connected to the speed switching unit 23 (particularly the speed switching unit 23a described below) as a first output terminal of the gate driver 21. The transistor 21a is turned on during a high-level period of the gate signal GH (= an on-period of the semiconductor switching element 30H), and is turned off during a low-level period of the gate signal GH (= an off-period of the semiconductor switching element 30H).

[0038] The source of the transistor 21b is connected to a terminal to which a second drive voltage VG2 is applied. The drain of the transistor 21b is connected to the speed switching unit 23 (particularly the speed switching unit 23b described below) as a second output terminal of the gate driver 21. The transistor 21b is turned on during a low-level period of the gate signal GH (= an off-period of the semiconductor switching element 30H), and is turned off during a high-level period of the gate signal GH (= an on-period of the semiconductor switching element 30H).

[0039] The controller 21 c turns on / off the transistors 21 a and 21 b in a complementary manner in response to a control signal GSH output from the control device 10 .

[0040] The speed control unit 22 includes speed control units 22a and 22b. The speed control unit 22a generates a flag signal FLAGa for controlling the turn-on speed of the semiconductor switching element 30H based on information about the output current IL. On the other hand, the speed control unit 22b generates a flag signal FLAGb for controlling the turn-off speed of the semiconductor switching element 30H based on information about the output current IL.

[0041] The speed switching unit 23 includes speed switching units 23a and 23b. The speed switching unit 23a is connected between the source of the transistor 21a and the terminal to which the gate signal GH is applied, and switches the turn-on speed of the semiconductor switching element 30H in response to the flag signal FLAGa. On the other hand, the speed switching unit 23b is connected between the drain of the transistor 21b and the terminal to which the gate signal GH is applied, and switches the turn-off speed of the semiconductor switching element 30H in response to the flag signal FLAGb.

[0042] According to this embodiment, it is possible to individually control the turn-on speed and the turn-off speed of the semiconductor switching element 30H. For example, it is desirable to employ this embodiment when the threshold value for switching the turn-on speed and the threshold value for switching the turn-off speed, which are compared with the output current IL, are different.

[0043] <Third embodiment> Fig. 4 is a diagram showing a third embodiment of the power conversion device 1. The power conversion device 1 of this embodiment is based on the second embodiment (Fig. 3) described above, but the speed control units 22a and 22b are shared as a single speed control unit 22 without distinguishing between turn-on and turn-off. In other words, the speed control unit 22 has the same configuration as that of the first embodiment (Fig. 2) described above.

[0044] According to this embodiment, it is possible to reduce the circuit size by sharing the speed control unit 22. For example, it is desirable to employ this embodiment when the threshold value for switching the turn-on speed and the threshold value for switching the turn-off speed, which are compared with the output current IL, are the same.

[0045] 5 is a diagram showing an example of the configuration of the speed control unit 22. The speed control unit 22 of this example configuration includes a comparator CMP1.

[0046] The comparator CMP1 generates a flag signal FLAG by comparing the output current IL (or a signal containing information about it) input to the non-inverting input terminal (+) with the reference current Iref (or a signal containing information about it) input to the inverting input terminal (-). For example, the flag signal FLAG goes low when the output current IL is smaller than the reference current Iref, and goes high when the output current IL is larger than the reference current Iref.

[0047] FIG. 6 is a diagram showing an example of speed switching control in the third embodiment, depicting, from top to bottom, a control signal GSH, an output current IL, and a flag signal FLAG.

[0048] As described above, when the output current IL is smaller than the reference current Iref, the flag signal FLAG goes low. At this time, the speed switching units 23a and 23b may, for example, reduce the gate resistance values ​​of the semiconductor switching elements 30H and 30L, thereby increasing the turn-on and turn-off speeds of the semiconductor switching element 30H.

[0049] On the other hand, when the output current IL is greater than the reference current Iref, the flag signal FLAG goes high. At this time, the speed switching units 23a and 23b may increase the gate resistance values ​​of the semiconductor switching elements 30H and 30L, respectively, to decrease the turn-on and turn-off speeds of the semiconductor switching element 30H.

[0050] <Fourth embodiment> Fig. 7 is a diagram showing a fourth embodiment of the power conversion device 1. The power conversion device 1 of this embodiment is based on the first embodiment (Fig. 2) described above, and specifically illustrates the internal configuration of the speed control unit 22.

[0051] Referring to this figure, the speed control unit 22 includes an inverter INV1, a sample-and-hold circuit SH1, and a comparator CMP2.

[0052] The inverter INV1 inverts the logic level of the control signal GSH to generate the inverted control signal GSHB. Therefore, the inverted control signal GSHB is at a low level when the control signal GSH is at a high level, and is at a high level when the control signal GSH is at a low level.

[0053] The sample-and-hold circuit SH1 holds the detected value of the output current IL for a certain period in synchronization with the inverted control signal GSHB, and outputs the held output current IL' (or a signal containing information about it).

[0054] The comparator CMP2 generates a flag signal FLAG by comparing the held output current IL' (or a signal containing information thereof) input to the non-inverting input terminal (+) with the reference current Iref (or a signal containing information thereof) input to the inverting input terminal (-). For example, the flag signal FLAG goes low when the held output current IL' is smaller than the reference current Iref, and goes high when the held output current IL' is larger than the reference current Iref.

[0055] In this embodiment, chattering can be prevented by holding the detected value of the output current IL (=updating the held output current IL') at the timing when the on / off state of the semiconductor switching element 30H is switched.

[0056] The speed control section 22 may be divided into two speed control sections 22a and 22b, as in the second embodiment (FIG. 3). Also, the sample-and-hold circuit SH1 may be provided with a turn-on control section and a turn-off control section.

[0057] FIG. 8 is a diagram showing a first example of speed switching control in the fourth embodiment, and depicts, from top to bottom, a control signal GSH, an output current IL, a held output current IL', and a flag signal FLAG.

[0058] As shown in this figure, the sample-and-hold circuit SH1 may hold the detected value of the output current IL at the timing when the control signal GSH falls from high level to low level, i.e., at the timing when the semiconductor switching element 30H switches from an on state to an off state.

[0059] FIG. 9 is a diagram showing a second example of speed switching control in the fourth embodiment, and like FIG. 8, from top to bottom, it depicts the control signal GSH, the output current IL, the held output current IL′, and the flag signal FLAG.

[0060] As shown in this figure, the sample-and-hold circuit SH1 may hold the detected value of the output current IL at the timing when the control signal GSH rises from low level to high level, i.e., at the timing when the semiconductor switching element 30H switches from an off state to an on state.

[0061] <Fifth embodiment> Fig. 10 is a diagram showing a fifth embodiment of the power conversion device 1. The power conversion device 1 of this embodiment is based on the fourth embodiment (Fig. 7) described above, but has a modified internal configuration of the speed control unit 22.

[0062] Referring to this figure, the speed control unit 22 includes a sample-and-hold circuit SH2, a current estimation unit IE1, and a comparator CMP3.

[0063] The sample-and-hold circuit SH2 holds the drain-source voltage Vds for a certain period in synchronization with the control signal GSH during the on-period of the semiconductor switching element 30H, and outputs the held drain-source voltage Vds'.

[0064] In addition, if there are few switching stages for the turn-on speed and the turn-off speed, a desaturation detection signal (so-called DESAT signal) of the semiconductor switching element 30H may be input to the sample-and-hold circuit SH2 instead of the drain-source voltage Vds of the semiconductor switching element 30H.

[0065] The current estimation unit IE1 derives an estimated value IL" of the output current IL from the held drain-source voltage Vds'. Note that the current estimation unit IE1 may be provided with, for example, an approximate formula IL = k1 × Vds + k2 (where k1 and k2 are constants) that indicates the current-voltage characteristics of the semiconductor switching element 30H.

[0066] The comparator CMP3 generates a flag signal FLAG by comparing the estimated value IL" of the output current IL (or a signal containing that information) input from the current estimation unit IE1 to the non-inverting input terminal (+) with the reference current Iref (or a signal containing that information) input to the inverting input terminal (-). For example, the flag signal FLAG becomes low level when the estimated value IL" of the output current IL is smaller than the reference current Iref, and becomes high level when the estimated value IL" of the output current IL is larger than the reference current Iref.

[0067] FIG. 11 is a diagram showing an example of speed switching control in the fifth embodiment, and depicts, from top to bottom, a control signal GSH, an output current IL, a held drain-source voltage Vds′, an estimated value IL″ of the output current IL, and a flag signal FLAG.

[0068] As shown in this figure, the sample-and-hold circuit SH2 may be configured to hold the drain-source voltage Vds of the semiconductor switching element 30H (=update the held drain-source voltage Vds') at the timing when the control signal GSH rises from low level to high level, i.e., at the timing when the semiconductor switching element 30H switches from the off state to the on state.

[0069] 12 is a diagram showing a sixth embodiment of the power conversion device 1. The power conversion device 1 of this embodiment is based on the fourth embodiment (FIG. 7) described above, and includes a sense transistor 31 as means for detecting the output current IL.

[0070] The gate and drain of the sense transistor 31 are connected to the gate and drain of the semiconductor switching element 30H, respectively. A sense current Isns corresponding to the output current IL flows through the sense transistor 31 connected in this manner. The sense transistor 31 may be modularized together with the semiconductor switching element 30H.

[0071] Furthermore, with the introduction of the sense transistor 31, a change has also been made to the internal configuration of the speed control unit 22. Referring to this figure, the speed control unit 22 includes a current estimation unit IE2, a sample-and-hold circuit SH3, and a comparator CMP4.

[0072] The current estimation unit IE2 derives an estimated value IL" of the output current IL from the sense current Isns flowing through the sense transistor 31. The current estimation unit IE2 may, for example, have an approximate formula IL = k3 × Isns (where k3 is a constant) that indicates the ratio between the output current IL and the sense current Isns.

[0073] The sample-and-hold circuit SH3 synchronizes with the control signal GSH and holds the estimated value IL″ of the output current IL during the on-period of the semiconductor switching element 30H for a certain period of time, thereby outputting the held output current IL′ (or a signal containing that information).

[0074] The comparator CMP4 generates a flag signal FLAG by comparing the held output current IL' (or a signal containing information thereof) input to the non-inverting input terminal (+) with the reference current Iref (or a signal containing information thereof) input to the inverting input terminal (-). For example, the flag signal FLAG goes low when the held output current IL' is smaller than the reference current Iref, and goes high when the held output current IL' is larger than the reference current Iref.

[0075] FIG. 13 is a diagram showing an example of speed switching control in the sixth embodiment, depicting, from top to bottom, a control signal GSH, an output current IL, a sense current Isns, a held output current IL′, and a flag signal FLAG.

[0076] As shown in this figure, the sample-and-hold circuit SH3 may hold the sense current Isns (and thus the estimated value IL″ of the output current IL) at the timing when the control signal GSH rises from a low level to a high level, that is, at the timing when the semiconductor switching element 30H switches from an off state to an on state.

[0077] <Seventh embodiment> Fig. 14 is a diagram showing a seventh embodiment of the power conversion device 1. The power conversion device 1 of this embodiment is based on the fourth embodiment (Fig. 7) described above, but has a modified internal configuration of the speed control unit 22.

[0078] Referring to this figure, the speed control unit 22 includes a comparator CMP5, and receives a current command value ILref generated by the control device 10 to control the speed switching unit 23 (more specifically, the switch unit included in the speed switching unit 23).

[0079] The comparator CMP5 generates a flag signal FLAG by comparing the current command value ILref input to the non-inverting input terminal (+) with the reference current Iref (or a signal containing information thereof) input to the inverting input terminal (-). For example, the flag signal FLAG goes low when the current command value ILref is smaller than the reference current Iref, and goes high when the current command value ILref is larger than the reference current Iref.

[0080] The current command value ILref is a type of internal signal generated by the control device 10 for each switching period of the semiconductor switching element 30H, and is originally used for internal processing of the control device 10 (such as current mode control).

[0081] In this embodiment, unlike the fourth to sixth embodiments (FIGS. 7, 10, and 12), the sample-and-hold circuits SH1 to SH3 are not required.

[0082] FIG. 15 is a diagram showing an example of speed switching control in the seventh embodiment, and depicts, from top to bottom, a control signal GSH, an output current IL, a current command value ILref, and a flag signal FLAG.

[0083] As shown in this figure, the control device 10 may update the current command value ILref at the timing when the control signal GSH rises from low level to high level, that is, at the timing when the semiconductor switching element 30H switches from the off state to the on state.

[0084] Eighth Embodiment Fig. 16 is a diagram showing an eighth embodiment of the power conversion device 1. The power conversion device 1 of this embodiment combines the fifth embodiment (Fig. 10) and the seventh embodiment (Fig. 14) described above, with a modification made to the internal configuration of the speed control unit 22.

[0085] Referring to this figure, the speed control unit 22 includes a comparator CMP6 and a logic LGC1 in addition to the comparator CMP5, sample-and-hold circuit SH2, and current estimation unit IE1 mentioned above.

[0086] The comparator CMP6 generates a maximum flag signal FLAG_max by comparing the estimated value IL" of the output current IL (or a signal containing that information) input to the inverting input terminal (-) from the current estimation unit IE1 with the maximum reference current Iref_max (or a signal containing that information) input to the non-inverting input terminal (+). For example, the maximum flag signal FLAG_max goes high when the estimated value IL" of the output current IL is smaller than the maximum reference current Iref_max, and goes low when the estimated value IL" of the output current IL is larger than the maximum reference current Iref_max.

[0087] The logic LGC1 receives both the flag signal FLAG and the maximum flag signal FLAG_max and outputs the output flag signal FLAG'. For example, when the maximum flag signal FLAG_max is at a low level, that is, when the output current IL is greater than a predetermined threshold, the logic LGC1 may generate the output flag signal FLAG' so as to reduce at least one of the turn-on speed and the turn-off speed to a minimum value, regardless of the flag signal FLAG corresponding to the current command value ILref.

[0088] FIG. 17 is a diagram showing an example of speed switching control in the eighth embodiment, depicting, from top to bottom, the control signal GSH, the output current IL, the current command value ILref, the flag signal FLAG, the maximum flag signal FLAG_max, and the output flag signal FLAG′.

[0089] As shown in the figure, when the maximum flag signal FLAG_max is at a high level, the flag signal FLAG corresponding to the current command value ILref takes priority. As a result, when the flag signal FLAG is at a low level, at least one of the turn-on speed and the turn-off speed becomes high (HIGH), and conversely, when the flag signal FLAG is at a high level, at least one of the turn-on speed and the turn-off speed becomes low (LOW).

[0090] On the other hand, when the maximum flag signal FLAG_max is at a low level, as mentioned above, at least one of the turn-on speed and the turn-off speed is reduced to the minimum value (MIN) regardless of the flag signal FLAG corresponding to the current command value ILref.

[0091] For example, if a deviation occurs between the actual output current IL and the current command value ILref generated by the control device 10 due to a sudden load change, etc., and the output current IL flowing through the semiconductor switching element 30H becomes large, it is possible to reduce the turn-on speed and turn-off speed to their minimum values.

[0092] <Ninth embodiment> Fig. 18 is a diagram showing a ninth embodiment of the power conversion device 1. The power conversion device 1 of this embodiment is a combination of the sixth embodiment (Fig. 12) and the seventh embodiment (Fig. 14) described above, with a modification made to the internal configuration of the speed control unit 22.

[0093] Referring to this figure, the speed control unit 22 includes a comparator CMP7 and a logic LGC2 in addition to the comparator CMP5, sample-and-hold circuit SH3, and current estimation unit IE2 mentioned above.

[0094] The comparator CMP7 generates a maximum flag signal FLAG_max by comparing the held output current IL' or a signal containing information thereof input from the sample-and-hold circuit SH3 to its inverting input terminal (-) with the maximum reference current Iref_max (or a signal containing information thereof) input to its non-inverting input terminal (+). For example, the maximum flag signal FLAG_max goes high when the held output current IL' is smaller than the maximum reference current Iref_max, and goes low when the held output current IL' is larger than the maximum reference current Iref_max.

[0095] The logic LGC2 receives both the flag signal FLAG and the maximum flag signal FLAG_max and outputs the output flag signal FLAG'. For example, when the maximum flag signal FLAG_max is at a low level, that is, when the output current IL is greater than a predetermined threshold, the logic LGC2 may generate the output flag signal FLAG' so as to reduce at least one of the turn-on speed and the turn-off speed to a minimum value, regardless of the flag signal FLAG corresponding to the current command value ILref.

[0096] In this embodiment, similar to the eighth embodiment (FIG. 16) described above, appropriate speed switching control can be performed even when a deviation occurs between the output current IL and the current command value ILref.

[0097] <Tenth embodiment> Figure 19 is a diagram showing a tenth embodiment of the power conversion device 1. The power conversion device 1 of this embodiment is based on the second embodiment (Figure 3) or the third embodiment (Figure 4) described above, and further includes new diodes 24a and 24b as components of a gate driver 20H. In addition, with the introduction of the diodes 24a and 24b, changes have also been made to the internal configuration of the gate driver 21 and the connection relationship between the speed switching units 23a and 23b.

[0098] Referring to this figure, in the gate driver 21, the source of the transistor 21a and the drain of the transistor 21b are connected to each other, and the connection node is connected to the input terminals of the speed switching units 23a and 23b.

[0099] The anode of the diode 24a is connected to the output terminal of the speed switching unit 23a. The cathode of the diode 24b is connected to the output terminal of the speed switching unit 23b. The cathode of the diode 24a and the anode of the diode 24b are both connected to the application terminal of the gate signal GH (= the gate of the semiconductor switching element 30H).

[0100] According to this embodiment, similarly to the second embodiment (FIG. 3) and the third embodiment (FIG. 4) described above, it is possible to individually control the turn-on speed and the turn-off speed of the semiconductor switching element 30H.

[0101] 20 is a diagram illustrating an eleventh embodiment of the power conversion device 1. In the power conversion device 1 of the present embodiment, the internal configurations of the speed control unit 22 and the speed switching units 23 a and 23 b are specifically illustrated.

[0102] Referring to this figure, the speed control unit 22 includes comparators CMP8 and CMP9, an inverter INV2, AND gates AND11 and AND12, and AND gates AND21 and AND22.

[0103] The comparator CMP8 generates a flag signal FLAG1 by comparing the output current IL (or a signal containing information about it) input to the inverting input terminal (-) with the reference current Iref1 (or a signal containing information about it) input to the non-inverting input terminal (+). For example, the flag signal FLAG1 goes high when the output current IL is smaller than the reference current Iref1, and goes low when the output current IL is larger than the reference current Iref1.

[0104] The comparator CMP9 generates a flag signal FLAG2 by comparing the output current IL (or a signal containing information about it) input to the inverting input terminal (-) with the reference current Iref2 (or a signal containing information about it) input to the non-inverting input terminal (+). For example, the flag signal FLAG2 goes high when the output current IL is smaller than the reference current Iref2, and goes low when the output current IL is larger than the reference current Iref2.

[0105] The reference currents Iref1 and Iref2 may be set to Iref1<Iref2.

[0106] Further, as the means for detecting the output current IL in the speed control section 22, any of the fourth to seventh embodiments (FIGS. 7, 10, 12 and 14) may be applied.

[0107] The AND gate AND11 performs a logical AND operation on the control signal GSH and the flag signal FLAG1 to generate the switching signal S11. Therefore, the switching signal S11 is at a low level when at least one of the control signal GSH and the flag signal FLAG1 is at a low level, and is at a high level when both the control signal GSH and the flag signal FLAG1 are at a high level.

[0108] The AND gate AND12 performs a logical AND operation on the control signal GSH and the flag signal FLAG2 to generate the switching signal S12. Therefore, the switching signal S12 is at a low level when at least one of the control signal GSH and the flag signal FLAG2 is at a low level, and is at a high level when both the control signal GSH and the flag signal FLAG2 are at a high level.

[0109] The inverter INV2 inverts the logic level of the control signal GSH to generate the inverted control signal GSHB. Therefore, the inverted control signal GSHB is at a low level when the control signal GSH is at a high level, and is at a high level when the control signal GSH is at a low level.

[0110] The AND gate AND21 performs a logical AND operation on the inverted control signal GSHB and the flag signal FLAG1 to generate the switching signal S21. Therefore, the switching signal S21 goes low when at least one of the inverted control signal GSHB and the flag signal FLAG1 is low, and goes high when both the inverted control signal GSHB and the flag signal FLAG1 are high.

[0111] The AND gate AND22 performs a logical AND operation on the inverted control signal GSHB and the flag signal FLAG2 to generate the switching signal S22. Therefore, the switching signal S22 is at a low level when at least one of the inverted control signal GSHB and the flag signal FLAG2 is at a low level, and is at a high level when both the inverted control signal GSHB and the flag signal FLAG2 are at a high level.

[0112] The speed switching unit 23a includes gate resistors RG11 to RG13 (corresponding to a plurality of impedance elements) and switch units SW11 and SW12. For example, the resistance values ​​of the gate resistors RG11 to RG13 may be, for example, RG11≦RG12≦RG13.

[0113] A first terminal of each of the switches SW11 and SW12 and a first terminal of the gate resistor R13 are all connected to a first output terminal of the gate driver 21 (= the source of the transistor 21a in FIG. 3 ). A second terminal of the switch SW11 is connected to a first terminal of the gate resistor RG11. A second terminal of the switch SW12 is connected to a first terminal of the gate resistor RG12. A second terminal of each of the gate resistors RG11 to RG13 is all connected to an application terminal of the gate signal GH (= the gate of the semiconductor switching element 30H).

[0114] The switch SW11 is turned on / off in response to the switching signal S11. For example, if an N-channel MOSFET is used as the switch SW11, the switch SW11 is turned on when the switching signal S11 is at a high level, and turned off when the switching signal S11 is at a low level.

[0115] The switch SW12 is turned on / off in response to the switching signal S12. For example, if an N-channel MOSFET is used as the switch SW12, the switch SW12 is turned on when the switching signal S12 is at a high level, and turned off when the switching signal S12 is at a low level.

[0116] The speed switching unit 23a in this configuration example controls the switch units SW11 and SW12 to switch the number of parallel gate resistors RG11 to RG13, thereby switching the gate resistance value (= combined resistance value of gate resistors RG11 to RG13) that contributes to the turn-on speed of the semiconductor switching element 30H.

[0117] The speed switching unit 23b includes gate resistors RG21 to RG23 (corresponding to a plurality of impedance elements) and switch units SW21 and SW22. For example, the resistance values ​​of the gate resistors RG21 to RG23 may be, for example, RG21≦RG22≦RG23.

[0118] The first terminals of the switches SW21 and SW22 and the first terminal of the gate resistor RG23 are all connected to the second output terminal of the gate driver 21 (=the drain of the transistor 21b in FIG. 3). The second terminal of the switch SW21 is connected to the first terminal of the gate resistor RG21. The second terminal of the switch SW22 is connected to the first terminal of the gate resistor RG22. The second terminals of the gate resistors RG21 to RG23 are all connected to the application terminal of the gate signal GH (=the gate of the semiconductor switching element 30H).

[0119] The switch SW21 is turned on / off in response to the switching signal S21. For example, if an N-channel MOSFET is used as the switch SW21, the switch SW21 is turned on when the switching signal S21 is at a high level, and turned off when the switching signal S21 is at a low level.

[0120] The switch SW22 is turned on / off in response to the switching signal S22. For example, if an N-channel MOSFET is used as the switch SW22, the switch SW22 is turned on when the switching signal S22 is at a high level, and turned off when the switching signal S22 is at a low level.

[0121] The speed switching unit 23b in this configuration example controls the switch units SW21 and SW22 to switch the number of parallel gate resistors RG21 to RG23, thereby switching the gate resistance value (= combined resistance value of gate resistors RG21 to RG23) that contributes to the turn-off speed of the semiconductor switching element 30H.

[0122] FIG. 21 is a diagram showing an example of speed switching control in the eleventh embodiment, depicting, from top to bottom, the control signal GSH, the output current IL, the flag signals FLAG1 and FLAG2, the switching signals S11 and S12, and the switching signals S21 and S22.

[0123] First, the case where IL<Iref1 is described. In this case, both the flag signals FLAG1 and FLAG2 are at high level.

[0124] Therefore, during the high-level period of the control signal GSH (corresponding to the on-period of the semiconductor switching element 30H), both the switching signals S11 and S12 are at a high level. As a result, both the switches SW11 and SW12 are in an on state, and the gate resistance value (= combined resistance value) of the speed switching unit 23a becomes the combined resistance value of the parallel-connected gate resistors RG11 to RG13. This state corresponds to the state in which the gate resistance value of the speed switching unit 23a is at its lowest, in other words, the state in which the turn-on speed of the semiconductor switching element 30H is at its highest. Note that during the high-level period of the control signal GSH, both the switching signals S21 and S22 are at a low level, and therefore both the switches SW21 and SW22 are in an off state.

[0125] Furthermore, during the low-level period of the control signal GSH (corresponding to the off-period of the semiconductor switching element 30H), both the switching signals S21 and S22 are at a high level. As a result, both the switches SW21 and SW22 are in an on state, and the gate resistance value (= combined resistance value) of the speed switching unit 23b becomes the combined resistance value of the parallel-connected gate resistors RG21 to RG23. This state corresponds to the state in which the gate resistance value of the speed switching unit 23b is at its lowest, in other words, the state in which the turn-off speed of the semiconductor switching element 30H is at its highest. Note that during the low-level period of the control signal GSH, both the switching signals S11 and S12 are at a low level, and therefore both the switches SW11 and SW12 are in an off state.

[0126] Next, a case where Iref1<IL<Iref2 will be described. In this case, the flag signal FLAG1 goes low and the flag signal FLAG2 goes high.

[0127] Therefore, during the high-level period of the control signal GSH (corresponding to the on-period of the semiconductor switching element 30H), the switching signal S11 is at a low level and the switching signal S12 is at a high level. As a result, the switch unit SW11 is in an off state and the switch unit SW12 is in an on state, so that the gate resistance value (= combined resistance value) of the speed switching unit 23a becomes the combined resistance value of the parallel-connected gate resistors RG12 and RG13. This state corresponds to a state in which the gate resistance value of the speed switching unit 23a is increased by one step, in other words, a state in which the turn-on speed of the semiconductor switching element 30H is decreased by one step. Note that, as mentioned above, during the high-level period of the control signal GSH, both the switching signals S21 and S22 are at a low level, so that both the switch units SW21 and SW22 are in an off state.

[0128] Furthermore, during the low-level period of the control signal GSH (corresponding to the off-period of the semiconductor switching element 30H), the switching signal S21 is at a low level and the switching signal S22 is at a high level. As a result, the switch unit SW21 is in an off state and the switch unit SW22 is in an on state, so that the gate resistance value (= combined resistance value) of the speed switching unit 23b becomes the combined resistance value of the parallel-connected gate resistors RG22 and RG23. This state corresponds to a state in which the gate resistance value of the speed switching unit 23b is increased by one step, in other words, a state in which the turn-off speed of the semiconductor switching element 30H is decreased by one step. Note that, as mentioned above, during the low-level period of the control signal GSH, both the switching signals S11 and S12 are at a low level, so that both the switch units SW11 and SW12 are in an off state.

[0129] Next, a case where Iref2<IL will be described. In this case, both the flag signals FLAG1 and FLAG2 are at low level.

[0130] Therefore, during the high-level period of the control signal GSH (corresponding to the on-period of the semiconductor switching element 30H), both the switching signals S11 and S12 are at a low level. As a result, both the switches SW11 and SW12 are in an off state, and the gate resistance value (= combined resistance value) of the speed switching unit 23a becomes RG13. This state corresponds to the state in which the gate resistance value of the speed switching unit 23a is the highest, in other words, the state in which the turn-on speed of the semiconductor switching element 30H is the slowest. Note that, as mentioned above, during the high-level period of the control signal GSH, both the switching signals S21 and S22 are at a low level, and therefore both the switches SW21 and SW22 are in an off state.

[0131] Furthermore, during the low-level period of the control signal GSH (corresponding to the off-period of the semiconductor switching element 30H), both the switching signals S21 and S22 are at a low level. As a result, both the switches SW21 and SW22 are in an off state, and the gate resistance value (= combined resistance value) of the speed switching unit 23b becomes RG23. This state corresponds to the state in which the gate resistance value of the speed switching unit 23b is the highest, in other words, the state in which the turn-off speed of the semiconductor switching element 30H is the slowest. Note that, as mentioned above, during the low-level period of the control signal GSH, both the switching signals S11 and S12 are at a low level, and therefore both the switches SW11 and SW12 are in an off state.

[0132] <Twelfth Embodiment> Fig. 22 is a diagram showing a twelfth embodiment of the power conversion device 1. The power conversion device 1 of this embodiment is based on the previously described eleventh embodiment (Fig. 20), but has a modified internal configuration of the speed switching unit 23a. Note that although the speed switching unit 23b is not explicitly shown in this figure, its circuit configuration may basically be the same as that of the speed switching unit 23a. Therefore, the following will describe the speed switching unit 23a in detail, and a description of the speed switching unit 23b will be omitted.

[0133] The speed switching unit 23a includes gate resistors RG31 to RG33 (corresponding to a plurality of impedance elements) and switch units SW31 and SW32. For example, the resistance values ​​of the gate resistors RG31 to RG33 may be RG31≦RG32≦RG33.

[0134] A first terminal of the gate resistor RG31 is connected to a first output terminal of the gate driver 21 (= the source of the transistor 21a in FIG. 3 ). A second terminal of the gate resistor RG31 is connected to a first terminal of the gate resistor RG32 and the switch unit SW31. A second terminal of the gate resistor RG32 and the switch unit SW31 is connected to a first terminal of the gate resistor RG33 and the switch unit SW32. A second terminal of the gate resistor RG33 and the switch unit SW32 is connected to an application terminal of the gate signal GH (= the gate of the semiconductor switching element 30H).

[0135] The switch SW31 is turned on / off in response to the switching signal S11. For example, if an N-channel MOSFET is used as the switch SW31, the switch SW31 is turned on when the switching signal S11 is at a high level, and turned off when the switching signal S11 is at a low level.

[0136] The switch SW32 is turned on / off in response to the switching signal S12. For example, if an N-channel MOSFET is used as the switch SW32, the switch SW32 is turned on when the switching signal S12 is at a high level, and turned off when the switching signal S12 is at a low level.

[0137] The speed switching unit 23a in this configuration example controls the switch units SW31 and SW32 to switch the number of gate resistors RG31 to RG33 connected in series, thereby switching the gate resistance value (= combined resistance value of gate resistors RG31 to RG33) that contributes to the turn-on speed of the semiconductor switching element 30H.

[0138] FIG. 23 is a diagram showing an example of speed switching control in the twelfth embodiment, depicting, from top to bottom, the control signal GSH, the output current IL, the flag signals FLAG1 and FLAG2, and the switching signals S11 and S12.

[0139] First, the case where IL<Iref1 is described. In this case, both the flag signals FLAG1 and FLAG2 are at high level.

[0140] Therefore, during the high-level period of the control signal GSH (corresponding to the on-period of the semiconductor switching element 30H), both the switching signals S11 and S12 are at a high level. As a result, both the switches SW31 and SW32 are in the on state, and the gate resistance value (= combined resistance value) of the speed switching unit 23a becomes RG31. This state corresponds to the state in which the gate resistance value of the speed switching unit 23a is at its lowest, in other words, the state in which the turn-on speed of the semiconductor switching element 30H is at its highest.

[0141] Next, a case where Iref1<IL<Iref2 will be described. In this case, the flag signal FLAG1 goes low and the flag signal FLAG2 goes high.

[0142] Therefore, during the high-level period of the control signal GSH (corresponding to the on-period of the semiconductor switching element 30H), the switching signal S11 is at a low level and the switching signal S12 is at a high level. As a result, the switch unit SW31 is in an off state and the switch unit SW32 is in an on state, so that the gate resistance value (= combined resistance value) of the speed switching unit 23a becomes RG31+RG32. This state corresponds to a state in which the gate resistance value of the speed switching unit 23a has been increased by one step, in other words, a state in which the turn-on speed of the semiconductor switching element 30H has been decreased by one step.

[0143] Next, a case where Iref2<IL will be described. In this case, both the flag signals FLAG1 and FLAG2 are at low level.

[0144] Therefore, during the high-level period of the control signal GSH (corresponding to the on-period of the semiconductor switching element 30H), both the switching signals S11 and S12 are at a low level. As a result, both the switches SW31 and SW32 are in an off state, and the gate resistance value (= combined resistance value) of the speed switching unit 23a becomes RG31 + RG32 + RG33. This state corresponds to the state in which the gate resistance value of the speed switching unit 23a is the highest, in other words, the state in which the turn-on speed of the semiconductor switching element 30H is the slowest.

[0145] 24 is a diagram showing a thirteenth embodiment of the power conversion device 1. In the power conversion device 1 of this embodiment, the internal configurations of the speed control unit 22 and the speed switching unit 23 are specifically illustrated.

[0146] The speed control unit 22 includes comparators CMP10 and CMP11.

[0147] The comparator CMP10 generates a flag signal FLAG3 by comparing the output current IL (or a signal containing information about it) input to the non-inverting input terminal (+) with the reference current Iref1 (or a signal containing information about it) input to the inverting input terminal (-). For example, the flag signal FLAG3 goes low when the output current IL is smaller than the reference current Iref1, and goes high when the output current IL is larger than the reference current Iref1.

[0148] The comparator CMP11 generates a flag signal FLAG4 by comparing the output current IL (or a signal containing information about it) input to the non-inverting input terminal (+) with the reference current Iref2 (or a signal containing information about it) input to the inverting input terminal (-). For example, the flag signal FLAG4 goes low when the output current IL is smaller than the reference current Iref2, and goes high when the output current IL is larger than the reference current Iref2.

[0149] The reference currents Iref1 and Iref2 may be set to Iref1<Iref2.

[0150] Further, as the means for detecting the output current IL in the speed control section 22, any of the fourth to seventh embodiments (FIGS. 7, 10, 12 and 14) may be applied.

[0151] The speed switching unit 23 includes a gate resistor RG, gate capacitances CG1 and CG2 (corresponding to a plurality of impedance elements), and switch units SW41 and SW42. For example, the capacitance values ​​of the gate capacitances CG1 and CG2 may be such that CG1≦CG2.

[0152] A first terminal of the gate resistor RG is connected to a first output terminal of the gate driver 21 (= the source of the transistor 21a in FIG. 3 ). A second terminal of the gate resistor RG and first terminals of the gate capacitors CG1 and CG2 are all connected to an application terminal of the gate signal GH (= the gate of the semiconductor switching element 30H). A second terminal of the gate capacitor CG1 is connected to a first terminal of the switch unit SW41. A second terminal of the gate capacitor CG2 is connected to a first terminal of the switch unit SW42. A second terminal of the switch units SW41 and SW42 is all connected to a common node (= the source of the semiconductor switching element 30H).

[0153] The switch SW41 is turned on / off in response to the flag signal FLAG3. For example, if an N-channel MOSFET is used as the switch SW41, the switch SW41 is turned on when the flag signal FLAG3 is at a high level, and turned off when the flag signal FLAG3 is at a low level.

[0154] The switch SW42 is turned on / off in response to the flag signal FLAG4. For example, if an N-channel MOSFET is used as the switch SW42, the switch SW42 is turned on when the flag signal FLAG4 is at a high level, and turned off when the flag signal FLAG4 is at a low level.

[0155] The speed switching unit 23 in this configuration example controls the switch units SW41 and SW42 to switch the number of parallel gate capacitances CG1 to CG2, thereby switching the gate capacitance values ​​(= combined capacitance values ​​of gate capacitances CG1 and CG2) that contribute to the turn-on speed and turn-off speed of the semiconductor switching element 30H.

[0156] FIG. 25 is a diagram showing an example of speed switching control in the thirteenth embodiment, depicting, from top to bottom, the control signal GSH, the output current IL, and the flag signals FLAG3 and FLAG4.

[0157] First, the case where IL<Iref1 is described. In this case, both flag signals FLAG3 and FLAG4 are at low level.

[0158] As a result, both switches SW41 and SW42 are turned off, and the gate capacitance value (=composite capacitance value) of the speed switching unit 23 becomes Ciss. This state corresponds to a state in which the gate capacitance value of the speed switching unit 23 is smallest, in other words, a state in which the time constant τ (=RG×Ciss) when charging the input capacitance Ciss is smallest and the turn-on speed and turn-off speed of the semiconductor switching element 30H are highest.

[0159] Next, a case where Iref1<IL<Iref2 will be described. In this case, the flag signal FLAG3 goes high and the flag signal FLAG4 goes low.

[0160] As a result, switch SW41 is turned on and switch SW42 is turned off, so that the gate capacitance value (=composite capacitance value) of speed switching unit 23 becomes Ciss+CG1. This state corresponds to a state in which the gate capacitance value of speed switching unit 23 is increased by one step, in other words, a state in which the time constant τ (=RG×(Ciss+CG1)) when charging input capacitance Ciss is increased by one step and the turn-on speed and turn-off speed of semiconductor switching element 30H are decreased by one step.

[0161] Next, a case where Iref2<IL will be described. In this case, both flag signals FLAG3 and FLAG4 are at high level.

[0162] As a result, both switches SW41 and SW42 are turned on, and the gate capacitance value (=composite capacitance value) of speed switching unit 23 becomes Ciss+CG1+CG2. This state corresponds to the state in which the gate capacitance value of speed switching unit 23 is greatest, i.e., the state in which the time constant τ (=RG×(Ciss+CG1+CG2)) when charging input capacitance Ciss is greatest, and the turn-on speed and turn-off speed of semiconductor switching element 30H are lowest.

[0163] <Fourteenth embodiment> Fig. 26 is a diagram showing a fourteenth embodiment of the power conversion device 1. The power conversion device 1 of this embodiment is based on the previously described thirteenth embodiment (Fig. 24), but the speed switching unit 23 used as means for switching both the turn-on speed and the turn-off speed is changed to a speed switching unit 23a used as means for switching the turn-on speed.

[0164] In addition, in accordance with the above changes, changes have also been made to the internal configurations of the speed control unit 22 and the speed switching unit 23a. Although the speed switching unit 23b is not explicitly shown in this figure, its circuit configuration may basically be the same as that of the speed switching unit 23a. Therefore, the following will describe the speed switching unit 23a in detail, and will omit a description of the speed switching unit 23b.

[0165] The speed control unit 22 includes logical AND gates AND31 and AND32 in addition to the comparators CMP10 and CMP11 described above.

[0166] The AND gate AND31 performs a logical AND operation on the control signal GSH and the flag signal FLAG3 to generate the switching signal S31. Therefore, the switching signal S31 is at a low level when at least one of the control signal GSH and the flag signal FLAG3 is at a low level, and is at a high level when both the control signal GSH and the flag signal FLAG3 are at a high level. The switching signal S31 is output to the control terminal (gate) of the switch unit SW41 in place of the previously mentioned flag signal FLAG3.

[0167] The AND gate AND32 performs a logical AND operation on the control signal GSH and the flag signal FLAG4 to generate the switching signal S32. Therefore, the switching signal S32 is at a low level when at least one of the control signal GSH and the flag signal FLAG4 is at a low level, and is at a high level when both the control signal GSH and the flag signal FLAG4 are at a high level. The switching signal S32 is output to the control terminal (gate) of the switch unit SW42 in place of the previously mentioned flag signal FLAG4.

[0168] The speed switching unit 23a includes inverters INV3 and INV4 and reset circuits RST1 and RST2 in addition to the gate resistor RG, gate capacitors CG1 and CG2, and switch units SW41 and SW42.

[0169] The switch SW41 is turned on / off in response to the switching signal S31. For example, if an N-channel MOSFET is used as the switch SW41, the switch SW41 is turned on when the switching signal S31 is at a high level, and turned off when the switching signal S31 is at a low level.

[0170] The switch SW42 is turned on / off in response to the switching signal S32. For example, if an N-channel MOSFET is used as the switch SW42, the switch SW42 is turned on when the switching signal S32 is at a high level, and turned off when the switching signal S32 is at a low level.

[0171] The inverter INV3 inverts the logic level of the switching signal S31 to generate the inverted switching signal S31 B. Therefore, the inverted switching signal S31 B is at a low level when the switching signal S31 is at a high level, and is at a high level when the switching signal S31 is at a low level.

[0172] The inverter INV4 inverts the logic level of the switching signal S32 to generate the inverted switching signal S32 B. Therefore, the inverted switching signal S32 B is at a low level when the switching signal S32 is at a high level, and is at a high level when the switching signal S32 is at a low level.

[0173] The reset circuit RST1 is connected in parallel to the gate capacitor CG1 and resets (discharges) the charge stored in the gate capacitor CG1 in response to the inverted switching signal S31B. Referring to the figure, the reset circuit RST1 resets (discharges) the charge stored in the gate capacitor CG1 when the inverted switching signal S31B is at a high level.

[0174] The reset circuit RST2 is connected in parallel to the gate capacitance CG2, and resets (discharges) the charge stored in the gate capacitance CG2 in response to the inverted switching signal S32B. Referring to this diagram, the reset circuit RST2 resets (discharges) the charge stored in the gate capacitance CG2 when the inverted switching signal S32B is at a high level.

[0175] The speed switching unit 23a in this configuration example controls the switch units SW41 and SW42 to switch the number of parallel gate capacitances CG1 to CG2, thereby switching the gate capacitance value (= the combined capacitance value of gate capacitances CG1 and CG2) that contributes to the turn-on speed of the semiconductor switching element 30H.

[0176] FIG. 27 is a diagram showing an example of speed switching control in the fourteenth embodiment, depicting, from top to bottom, the control signal GSH, the output current IL, the flag signals FLAG3 and FLAG4, and the switching signals S31 and S32.

[0177] First, the case where IL<Iref1 is described. In this case, both flag signals FLAG3 and FLAG4 are at low level.

[0178] Therefore, during the high-level period of the control signal GSH (corresponding to the on-period of the semiconductor switching element 30H), both the switching signals S31 and S32 are at a low level. As a result, both the switches SW41 and SW42 are in an off state, and the gate capacitance value (=composite capacitance value) of the speed switching unit 23a is Ciss. This state corresponds to the state in which the gate capacitance value of the speed switching unit 23a is at its smallest, in other words, the state in which the time constant τ (=RG×Ciss) when charging the input capacitance Ciss is smallest and the turn-on speed of the semiconductor switching element 30H is highest.

[0179] Next, a case where Iref1<IL<Iref2 will be described. In this case, the flag signal FLAG3 goes high and the flag signal FLAG4 goes low.

[0180] Therefore, during the high-level period of the control signal GSH (corresponding to the on-period of the semiconductor switching element 30H), the switching signal S31 is at a high level and the switching signal S32 is at a low level. As a result, the switch unit SW41 is in an on state and the switch unit SW42 is in an off state, so that the gate capacitance value (=composite capacitance value) of the speed switching unit 23a becomes Ciss+CG1. This state corresponds to a state in which the gate capacitance value of the speed switching unit 23a has been increased by one step; in other words, a state in which the time constant τ (=RG×(Ciss+CG1)) when charging the input capacitance Ciss has been increased by one step and the turn-on speed of the semiconductor switching element 30H has been decreased by one step.

[0181] Next, a case where Iref2<IL will be described. In this case, both flag signals FLAG3 and FLAG4 are at high level.

[0182] Therefore, during the high-level period of the control signal GSH (corresponding to the on-period of the semiconductor switching element 30H), both the switching signals S31 and S32 are at a high level. As a result, both the switches SW41 and SW42 are in the on state, and the gate capacitance value (=composite capacitance value) of the speed switching unit 23a is Ciss + CG1 + CG2. This state corresponds to the state in which the gate capacitance value of the speed switching unit 23a is greatest; in other words, the state in which the time constant τ (= RG × (Ciss + CG1 + CG2)) when charging the input capacitance Ciss is greatest and the turn-on speed of the semiconductor switching element 30H is slowest.

[0183] During the low-level period of the control signal GSH (corresponding to the off-period of the semiconductor switching element 30H), both the switching signals S31 and S32 are at low level. At this time, both the inverted switching signals S31B and S32B are at high level, so the charges stored in the gate capacitances CG1 and CG2 are reset (discharged). Therefore, during the on-period of the semiconductor switching element 30H in the next cycle, the gate capacitances CG1 and CG2 can start to be charged anew, and there is no disruption to the switching control of the turn-on speed.

[0184] This embodiment is effective when it is desired to separately provide a speed switching unit 23a that controls the switching of the turn-on speed and a speed switching unit 23b that controls the switching of the turn-off speed, or when it is desired to control the switching of only one of the turn-on speed and the turn-off speed.

[0185] 28 is a diagram showing an example of the configuration of the reset circuit RST1. The circuit configuration of the reset circuit RST2 may basically be the same as that of the reset circuit RST1. Therefore, the reset circuit RST1 will be described in detail, and a description of the reset circuit RST2 will be omitted.

[0186] The reset circuit RST1 of this configuration example includes a resistor R1 and a transistor M1 (e.g., an NMOSFET). A first terminal of the resistor R1 is connected to a first terminal of a gate capacitor CG1 (see FIG. 26). A second terminal of the resistor R1 is connected to the drain of the transistor M1. The second terminal of the resistor R1 is connected to the second terminal of the gate capacitor CG1. The gate of the transistor M1 is connected to the output terminal of the inverter INV3 (= the application terminal of the inverted switching signal S31B).

[0187] The transistor M1 is turned on when the inverted switching signal S31B is at a high level, and turned off when the inverted switching signal S31B is at a low level. When the transistor M1 is turned on, both ends of the gate capacitance CG1 are shorted via the resistor R1 and the transistor M1. As a result, the charge stored in the gate capacitance CG1 is reset (discharged).

[0188] <Summary> The various embodiments described above will be summarized below.

[0189] For example, a gate drive device disclosed in this specification includes a gate drive unit configured to output power for switching a semiconductor switching element on and off, a speed control unit configured to control at least one of a turn-on speed and a turn-off speed of the semiconductor switching element, and a speed switching unit configured to switch at least one of the turn-on speed and the turn-off speed in response to an instruction from the speed control unit, wherein the speed switching unit includes a plurality of impedance elements and a switch unit configured to control the power output from the gate drive unit and passing through each of the plurality of impedance elements, and the speed control unit is configured to control the switch unit based on an output current flowing through the semiconductor switching element (first configuration).

[0190] In the gate driver according to the first configuration, the speed switching section may be configured (second configuration) to include at least one of a gate resistor and a gate capacitor as the plurality of impedance elements.

[0191] Furthermore, in the gate drive device according to the first or second configuration, the speed switching unit may be configured (third configuration) to include a first speed switching unit configured to switch the turn-on speed and a second speed switching unit configured to switch the turn-off speed.

[0192] Furthermore, in the gate drive device according to any one of the first to third configurations, the speed control unit may be configured (fourth configuration) to include a sample-and-hold circuit configured to hold the detected value of the output current or the voltage across the semiconductor switching element for a certain period of time.

[0193] Furthermore, in the gate drive device according to any one of the first to fourth configurations, the speed control unit may be configured (fifth configuration) to include a current estimation unit configured to estimate the output current from the voltage across the semiconductor switching element or from a sense current corresponding to the output current.

[0194] Furthermore, in the gate drive device according to any one of the first to third configurations, the speed control unit may be configured (sixth configuration) to receive a current command value generated by a control device and control the switch unit.

[0195] In addition, in the gate driver according to the sixth configuration, the speed control unit may be configured (seventh configuration) to reduce at least one of the turn-on speed and the turn-off speed to a minimum value when the output current is greater than a threshold value.

[0196] Furthermore, the gate driver according to the third configuration may be configured (eighth configuration) further including a first diode having an anode connected to the output terminal of the first speed switching unit and a cathode connected to the gate of the semiconductor switching element, and a second diode having a cathode connected to the output terminal of the second speed switching unit and an anode connected to the gate of the semiconductor switching element.

[0197] In the gate driving device according to any one of the first to eighth configurations, the speed switching section may be configured to switch the gate resistance value or the gate capacitance value of the semiconductor switching element (ninth configuration).

[0198] Furthermore, for example, the power conversion device disclosed in this specification has a configuration (tenth configuration) that includes a gate drive device having any of the first to ninth configurations described above, a control device configured to control the gate drive device, and a semiconductor switch element configured to be turned on / off by the gate drive device.

[0199] <Other Modifications> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0200] 1 Power conversion device 10 Control device 20, 20H, 20L Gate drive device 21, 21H, 21L Gate drive unit 21a, 21b Transistor (NMOSFET) 21c Controller 22, 22a, 22b Speed ​​control unit 23, 23a, 23b Speed ​​switching unit 24a, 24b Diode 30H, 30L Semiconductor switching element 31 Sense transistor AND11, AND12, AND21, AND22, AND31, AND32 Logical product gate CG1, CG2 Gate capacitance (impedance element) Ciss Input capacitance CMP1 to CMP11 Comparator IE1, IE2 Current estimation unit INV1 to INV4 Inverter LGC1, LGC2 Logic M1 Transistor (NMOSFET) R1 Resistor RST1, RST2 Reset circuit SH1 to SH3 Sample and hold circuit SW1, SW2, SW3, SW11, SW12, SW21, SW22, SW31, SW32, SW41, SW42 Switch section RG, RG1 to RG3, RG11 to RG13, RG21 to RG23, RG31 to RG33 Gate resistor (impedance element) RGH, RGL Gate resistor

Claims

1. A gate driver configured to output power for switching on / off the semiconductor switching element; a speed control unit configured to control at least one of a turn-on speed and a turn-off speed of the semiconductor switching element; a speed switching unit configured to switch at least one of the turn-on speed and the turn-off speed in response to an instruction from the speed control unit; Equipped with The speed switching unit is A plurality of impedance elements; a switch unit configured to control power output from the gate driver and passing through each of the impedance elements; Including, The speed control unit controls the switch unit based on an output current flowing through the semiconductor switching element.

2. The gate driver according to claim 1 , wherein the speed switching section includes at least one of a gate resistor and a gate capacitor as the plurality of impedance elements.

3. The speed switching unit is A first speed switching unit configured to switch the turn-on speed; A second speed switching unit configured to switch the turn-off speed; 2. The gate drive of claim 1 , comprising:

4. 2. The gate driver according to claim 1, wherein the speed control section includes a sample-and-hold circuit configured to hold a detected value of the output current or a voltage across the semiconductor switching element for a certain period of time.

5. 2. The gate driver according to claim 1, wherein the speed control unit includes a current estimating unit configured to estimate the output current from a voltage across the semiconductor switching element or from a sense current corresponding to the output current.

6. The gate drive device according to claim 1 , wherein the speed control unit receives a current command value generated by a control device and controls the switch unit.

7. The gate driver of claim 6 , wherein the speed controller reduces at least one of the turn-on speed and the turn-off speed to a minimum value when the output current is greater than a threshold value.

8. a first diode having an anode connected to an output terminal of the first speed switching unit and a cathode connected to a gate of the semiconductor switching element; a second diode having a cathode connected to the output terminal of the second speed switching unit and an anode connected to the gate of the semiconductor switching element; The gate drive of claim 3 further comprising:

9. The gate driver according to claim 1 , wherein the speed switching section switches a gate resistance value or a gate capacitance value of the semiconductor switching element.

10. A gate drive device according to any one of claims 1 to 9; a controller configured to control the gate drivers; A semiconductor switch element configured to be turned on / off by the gate driver; A power conversion device comprising: