Semiconductor device and module

Abstract

In the present invention, a semiconductor device comprises, for example, a current detection circuit that generates a current detection signal that corresponds to a monitored current, an error amplifier that generates an error signal that correponds to error between the current detection signal and a prescribed reference signal, a comparator that compares the error signal and the current detection signal and generates a set signal, and a controller that accepts the set signal as an input and controls the monitored current. The current detection circuit includes a current-output-type differential amplifier, a first input resistor connected between the first input end of the differential amplifier and a first current sense terminal, a second input resistor connected between the second input end of the differential amplifier and a second current sense terminal, an output resistor connected to the output end of the differential amplifier, a first feedback current path through which a first feedback current flows between the first input end and the output end of the differential amplifier, and a second feedback current path through which a second feedback current flows between the second input end and the output end of the differential amplifier.

Description

Semiconductor device, module

[0001] The invention disclosed in this specification relates to a semiconductor device and a module.

[0002] 2. Description of the Related Art Conventionally, semiconductor devices equipped with current detection circuits have been used in a variety of applications.

[0003] An example of the related prior art is disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0004] International Publication No. 2017 / 022633

[0005] However, conventional semiconductor devices have room for improvement in current detection accuracy.

[0006] In view of the above-mentioned problems found by the inventors of the present application, the invention disclosed in this specification has an object to provide a semiconductor device and a module with high current detection accuracy.

[0007] For example, a semiconductor device disclosed in this specification includes: a current detection circuit configured to generate a current detection signal corresponding to a current to be monitored; an error amplifier configured to generate an error signal corresponding to an error between the current detection signal and a predetermined reference signal; a comparator configured to compare the error signal with the current detection signal to generate a set signal; and a controller configured to receive an input of the set signal and control the current to be monitored, wherein the current detection circuit includes a current output type differential amplifier; a first input resistor configured to be connected between a first input terminal and a first current sense terminal of the differential amplifier; a second input resistor configured to be connected between a second input terminal and a second current sense terminal of the differential amplifier; an output resistor configured to be connected to an output terminal of the differential amplifier; a first feedback current path configured to flow a first feedback current between the first input terminal and the output terminal of the differential amplifier; and a second feedback current path configured to flow a second feedback current between the second input terminal and the output terminal of the differential amplifier.

[0008] a first reference current path configured to pass a first reference current between the first current sense terminal and a first output terminal of the VI converter; and a second reference current path configured to pass a second reference current between the second current sense terminal and a second output terminal of the VI converter.

[0009] According to the invention disclosed in this specification, it is possible to provide a semiconductor device and a module with high current detection accuracy.

[0010] FIG. 1 is a diagram illustrating a first embodiment of an LED lamp module. FIG. 2 is a diagram illustrating output feedback control using a bottom detection on-time fixed method. FIG. 3 is a diagram illustrating a second embodiment of an LED lamp module. FIG. 4 is a diagram illustrating the response performance required of an LED driver IC. FIG. 5 is a diagram illustrating the path of a surge current that flows during a load open / shortcut test. FIG. 6 is a diagram illustrating the waveform of a surge current that flows during a load open / shortcut test. FIG. 7 is a diagram illustrating a third embodiment of an LED lamp module. FIG. 8 is a diagram illustrating the occurrence of a gain error in a current sense amplifier. FIG. 9 is a diagram illustrating a fourth embodiment of an LED lamp module. FIG. 10 is a diagram illustrating the temperature characteristics of a current detection signal. FIG. 11 is a diagram illustrating a fifth embodiment of an LED lamp module. FIG. 12 is a diagram illustrating the elimination of a gain error in a current sense amplifier. FIG. 13 is a diagram illustrating a sixth embodiment of an LED lamp module. FIG. 14 is a diagram equivalently illustrating the current detection circuit of the sixth embodiment. FIG. 15 is a diagram illustrating a seventh embodiment of an LED lamp module. FIG. 16 is a diagram illustrating an eighth embodiment of an LED lamp module. FIG. 17 is a diagram illustrating a ninth embodiment of an LED lamp module. Fig. 18 is a diagram showing a tenth embodiment of the LED lamp module. Fig. 19 is a diagram showing an example of signal transmission in the eighth embodiment. Fig. 20 is a diagram showing an eleventh embodiment of the LED lamp module. Fig. 21 is a diagram showing an example of signal transmission in the tenth embodiment.

[0011] 1 is a diagram showing a first embodiment (basic configuration) of an LED lamp module. The LED lamp module Z of the first embodiment includes an LED driver IC1, an LED string 2 (a plurality of light-emitting diode elements connected in series), and various discrete components (capacitors Cb, Cc, and Co, an inductor L1, a resistor Rt, and a sense resistor Rs).

[0012] The LED driver IC1 is a semiconductor device that steps down the power input voltage Vi and supplies power to the LED string 2. The LED driver IC1 has a plurality of external terminals (such as a PIN pin, a SW pin, a BOOT pin, a PGND pin, a SNSP pin, a SNSN pin, a TON pin, and a COMP pin) as means for establishing electrical connection with the outside of the IC.

[0013] The PIN pin is a power supply terminal. The SW pin is a switch output terminal. The BOOT pin is a bootstrap capacitor connection terminal for driving the upper gate. The PGND pin is a power ground terminal. The SNSP pin is a first current sense terminal (+). The SNSN pin is a second current sense terminal (-). The TON pin is a resistor connection terminal for setting the on time. The COMP pin is a capacitor connection terminal for phase compensation.

[0014] The PIN pin is connected to the power supply terminal of the power system (the terminal to which the input voltage Vi is applied). The SW pin is connected to the first terminal of the inductor L1. The second terminal of the inductor L1 is connected to the first terminal of the sense resistor Rs. The second terminal of the sense resistor Rs is connected to the anode of the LED string 2. The cathode of the LED string 2 is connected to the ground terminal. A capacitor Cb (bootstrap capacitor) is connected between the BOOT pin and the SW pin. A capacitor Co (output capacitor) is connected between the anode of the LED string 2 and the ground terminal. A first terminal (high potential terminal) of the sense resistor Rs is connected to the SNSP pin. A second terminal (low potential terminal) of the sense resistor Rs is connected to the SNSN pin. The PGND pin is connected to the ground terminal of the power system. A resistor Rt (on-time setting resistor) is connected between the TON pin and the ground terminal. A capacitor Cc (phase compensation capacitor) is connected between the COMP pin and the ground terminal.

[0015] <LED Driver IC> Continuing with reference to Fig. 1, the circuit configuration of the LED driver IC1 will be described. The LED driver IC1 of this configuration example is configured by integrating an upper switch 11H, a lower switch 11L, an upper driver 12H, a lower driver 12L, a controller 13, an on-time setting unit 14, a slope signal generating unit 15, a current sense amplifier 16, an error amplifier 17, a comparator 18, a DAC 19, and a bootstrap diode D1 as means for driving the LED string 2. Of course, the LED driver IC1 may also integrate other components (such as a temperature detection circuit and various protection circuits) besides those described above.

[0016] The upper switch 11H is connected between the PIN pin and the SW pin and is turned on / off in response to the upper gate signal GH. An NMOSFET (N-channel type metal oxide semiconductor field effect transistor) or the like can be suitably used as the upper switch 11H. In this case, the upper switch 11H is turned on when GH=H (=BOOT) and turned off when GH=L (=SW). It is also possible to use a PMOSFET (P-channel type MOSFET) instead of an NMOSFET as the upper switch 11H. In this case, the bootstrap diode D1, capacitor Cb, and BOOT pin are unnecessary.

[0017] The lower switch 11L is connected between the SW pin and the PGND pin, and is turned on / off in response to a lower gate signal GL. An NMOSFET or the like can be suitably used as the lower switch 11L. In this case, the lower switch 11L is turned on when GL=H (=5VEXT) and turned off when GL=L (=PGND).

[0018] The upper switch 11H and the lower switch 11L connected in this manner form a half-bridge output stage that outputs a rectangular wave switch voltage Vsw from the SW pin. In other words, the upper switch 11H corresponds to the output element, and the lower switch 11L corresponds to the synchronous rectification element. The aforementioned inductor L1, sense resistor Rs, and LED string 2 are connected in series to the upper switch 11H. While this diagram illustrates a synchronous rectification type half-bridge output stage, if a diode rectification type is used, a diode can be used as the lower switch 11L.

[0019] The high-side driver 12H generates the high-side gate signal GH based on the high-side control signal SH input from the controller 13. The high level of the high-side gate signal GH corresponds to the boost voltage Vbst (≈Vsw+5VEXT) appearing at the BOOT pin, while the low level of the high-side gate signal GH corresponds to the switch voltage Vsw appearing at the SW pin.

[0020] The low-side driver 12L generates a low-side gate signal GL based on a low-side control signal SL input from the controller 13. The high level of the low-side gate signal GL is a constant voltage 5VEXT (internal power supply voltage or a separate external input voltage), while the low level of the low-side gate signal GL is the terminal voltage of the PGND pin (power ground voltage).

[0021] The controller 13 includes, for example, an RS flip-flop that receives inputs of a set signal SET and a reset signal RST, and generates an upper control signal SH and a lower control signal SL to complementarily turn on / off the upper switch 11H and the lower switch 11L.

[0022] More specifically, the controller 13 generates the upper control signal SH and the lower control signal SL so as to turn on the upper switch 11H and turn off the lower switch 11L at the rising timing of the set signal SET, and turn off the upper switch 11H and turn on the lower switch 11L at the rising timing of the reset signal RST.

[0023] However, the term "complementary" in this specification should be understood in a broad sense to include not only the case where the on / off states of the upper switch 11H and the lower switch 11L are completely reversed, but also the case where a simultaneous off period (so-called dead time) is provided to prevent through current.

[0024] The on-time setting unit 14 raises the reset signal RST to high level when a predetermined on-time Ton has elapsed since the rising edge of the set signal SET (and thus the on-time of the upper switch 11H). The on-time setting unit 14 has a function of arbitrarily setting the on-time Ton according to the resistance value of the resistor Rt connected to the TON pin. The on-time setting unit 14 also has a function of varying the on-time Ton so as to suppress fluctuations in the switching frequency Fsw based on the terminal voltages of the PIN pin and the SNSN pin.

[0025] The slope signal generator 15 detects the voltage between the SNSP pin and the SNSN pin (= the sense voltage Vsns generated across the sense resistor Rs) and generates a slope signal Vslp containing information (AC component) of the inductor current IL. The slope signal Vslp increases as the inductor current IL increases, and decreases as the inductor current IL decreases.

[0026] The current sense amplifier 16 (corresponding to a current detection circuit) amplifies the sense voltage Vsns to generate a current detection signal VISET. The current detection signal VISET increases as the output current ILED (=average inductor current IL_ave) flowing through the sense resistor Rs increases, and decreases as the output current ILED decreases. An arbitrary offset voltage Vofs (several hundred mV) may be applied to the current detection signal VISET.

[0027] The error amplifier 17 outputs a current corresponding to the difference between the analog dimming signal Vdcdim (corresponding to a predetermined reference signal) input to the non-inverting input terminal (+) and the current detection signal VISET input to the inverting input terminal (-), and generates an error signal Vc by charging and discharging a capacitor Cc. The error signal Vc rises when VISET<Vdcdim and falls when VISET>Vdcdim.

[0028] The comparator 18 generates a set signal SET by comparing the slope signal Vslp input to its inverting input terminal (-) with the error signal Vc input to its non-inverting input terminal (+). The set signal SET goes low when Vc<Vslp and goes high when Vc>Vslp. Therefore, the lower the error signal Vc, the later the rise timing of the set signal SET (and therefore the turn-on timing of the upper switch 11H). Conversely, the higher the error signal Vc, the earlier the rise timing of the set signal SET.

[0029] The DAC 19 converts an m-bit (for example, m=10) digital dimming signal ISET externally input to the LED driver IC1 into an analog dimming signal Vdcdim.

[0030] Among the above components, the upper driver 12H, the lower driver 12L, the controller 13, the on-time setting unit 14, the slope signal generating unit 15, the current sense amplifier 16, the error amplifier 17, the comparator 18, and the DAC 19 function as a bottom-detection fixed-on-time output feedback control unit, and the upper switch 11H and the lower switch 11L are complementarily driven so that the output current ILED supplied from the switch output terminal SW to the LED string 2 matches a predetermined target value.

[0031] <Output Feedback Control> FIG. 2 is a diagram showing output feedback control of the bottom detection fixed on-time type, and depicts, from top to bottom, the inductor current IL and the switch voltage Vsw.

[0032] While the upper switch 11H is off and the lower switch 11L is on, the switch voltage Vsw is at a low level (= the negative voltage −VDSW generated between the drain and source of the lower switch 11L). At this time, the inductor current IL flowing from the PGND pin to the SW pin via the lower switch 11L decreases as the energy of the inductor L1 is released.

[0033] When the inductor current IL decreases to a bottom value IL_btm corresponding to the error signal Vc, Vc > Vslp, and the set signal SET rises to a high level. As a result, the upper switch 11H turns on and the lower switch 11L turns off. At this time, the switch voltage Vsw becomes a high level (≒ Vi), and the inductor current IL flowing from the PIN pin to the SW pin via the upper switch 11H increases.

[0034] After that, when a predetermined on-time Ton has elapsed, the reset signal RST rises to a high level, the upper switch 11H is turned off, and the lower switch 11L is turned on, so that the inductor current IL again changes from increasing to decreasing, resulting in a ripple waveform in which the inductor current IL repeatedly increases and decreases between a peak value IL_pk and a bottom value IL_btm.

[0035] Here, the bottom value IL_btm of the inductor current IL varies depending on the difference between the current detection signal VISET (corresponding to the average inductor current IL_ave) and the analog dimming signal Vdcdim (corresponding to the target value of the average inductor current IL_ave). Also, the ripple amplitude ΔIL (=IL_pk-IL_btm) of the inductor current IL is determined depending on the on-time Ton.

[0036] Therefore, by repeating the above series of operations, the LED driver IC1 performs output feedback control using a bottom detection fixed on-time method so that the average inductor current IL_ave (and therefore the output current ILED) matches a predetermined target value.

[0037] The output feedback control method of the LED driver IC1 is not necessarily limited to the above. For example, instead of the bottom detection fixed on-time method, a peak detection fixed off-time method or a hysteresis window method may be used. Furthermore, in applications that do not require high-speed response, a linear control method such as PWM (pulse width modulation) control may also be used.

[0038] <LED Lamp Module (Second Embodiment)> Figure 3 is a diagram showing a second embodiment of an LED lamp module. The LED lamp module Z of the second embodiment is based on the first embodiment (Figure 1) and further includes a matrix manager 3. This figure also clearly shows a capacitor Ci (=input capacitor) connected between the PIN pin of the LED driver IC1 and the ground terminal.

[0039] The matrix manager 3 includes a plurality of switch elements connected in parallel to each of the plurality of light-emitting diode elements that form the LED string 2, and can arbitrarily switch the number of series stages (number of lights-on) of the light-emitting diode elements by turning on / off each switch element.

[0040] FIG. 4 is a diagram showing the response performance required of the LED driver IC 1 in the LED lamp module Z of the second embodiment, and depicts, from top to bottom, the voltage VLED across the LED string 2 (= the sum of the forward voltage drops of the light-emitting diode elements in the lit state) and the output current ILED.

[0041] In the LED lamp module Z of the second embodiment, the matrix manager 3 is introduced, so the number of lit light-emitting diode elements (and thus the voltage VLED across the LED string 2) can fluctuate sharply while the LED string 2 is lit.

[0042] Therefore, in order to light each light-emitting diode element at a constant brightness, it is necessary to increase the response speed of the LED driver IC1 and continue to stably supply a constant output current ILED even if the number of light-emitting diode elements that are turned on varies.

[0043] Therefore, it is desirable to adopt a nonlinear control method (such as a bottom detection fixed on-time method) that has excellent high-speed response as the output feedback control method for the LED driver IC 1. When a nonlinear control method is adopted, it is necessary to detect the average inductor current IL_ave, so a common configuration is to insert a sense resistor Rs after the inductor L1 and detect the sense voltage Vsns generated across the resistor by the LED driver IC 1.

[0044] <Load Open / Shortcut Test> FIGS. 5 and 6 are diagrams showing the paths and waveforms of surge currents ID1 and ID2 that flow during a load open / shortcut test, respectively.

[0045] First, let us consider an open load test. If an open circuit occurs in an LED element while LED string 2 is lit, the current path toward LED string 2 is interrupted. This causes the back electromotive force of inductor L1 to charge capacitor Co, resulting in an output overshoot. As a result, a surge current ID1 flows back to the power supply terminal via the electrostatic protection diode Desd (particularly the upper electrostatic protection diode connected between the SNSN pin and the power supply terminal) built into LED driver IC1.

[0046] If the LED driver IC1 uses a nonlinear control method (e.g., a bottom-detection fixed on-time method), the inductance value of the inductor L1 is set to a relatively large value (tens to hundreds of μH) relative to the capacitance value of the capacitor Co (several μF). Therefore, a large amount of energy is stored in the inductor L1, and a surge current ID1 of several amperes flows back for a relatively long time. As a result, the upper electrostatic protection diode Desd, which only has a current capacity of several tens of mA, may be destroyed.

[0047] Next, we will consider the load shortcut test. For example, if the LED lamp module Z is for automotive use, the LED driver IC 1 and the LED string 2 are mounted on separate boards. The boards are connected by a wire harness of approximately 1 m to 1.5 m. Therefore, the wire harness has non-negligible parasitic inductance components Lx and Ly (approximately 1 μH).

[0048] Therefore, when a shortcut occurs to the light-emitting diode elements (including the control of switching the number of lit-up diodes by the matrix manager 3), energy is charged from the capacitor Co to the parasitic inductance components Lx and Ly, and a surge current ID2 of several tens of amperes instantaneously flows from the ground terminal via the electrostatic protection diode Desd (particularly the lower electrostatic protection diode connected between the SNSN pin and the ground terminal) built into the LED driver IC1. As a result, the lower electrostatic protection diode Desd, which only has a current capacity of several tens of milliamperes, may be destroyed.

[0049] 7 is a diagram showing a third embodiment of an LED lamp module. In the LED lamp module Z of the third embodiment, surge protection diodes DH and DL are externally attached to the LED driver IC1 as a means for protecting the electrostatic protection diode Desd (see FIG. 5) from surge currents.

[0050] The surge protection diode DH is connected between the anode of the LED string 2 and the application terminal of the input voltage Vi. The surge protection diode DL is connected between the anode of the LED string 2 and the ground terminal.

[0051] With this circuit configuration, even if an open / short circuit occurs in a light-emitting diode element, the anode potential of the LED string 2 can be clamped within a predetermined range, making it possible to protect the electrostatic protection diode Desd of the LED driver IC1.

[0052] However, since two relatively expensive surge protection diodes DH and DL are required for each channel, this may increase the cost (including the cost of procuring and transporting parts) of the LED lamp module Z. In addition, the area required for mounting parts on the board also increases.

[0053] On the other hand, instead of attaching external surge protection diodes DH and DL, it is also possible to attach cheaper and smaller current limiting resistors RpP and RpN (approximately 1 kΩ) externally to the SNSP pin and SNSN pin of the LED driver IC1, respectively, thereby suppressing the surge current flowing through the electrostatic protection diode Desd and dissipating the surge current to the power supply terminal and ground terminal via the electrostatic protection diode Desd.

[0054] The current limiting resistor RpP is preferably connected between the SNSP pin and the first end (high potential end) of the sense resistor Rs, and the current limiting resistor RpN is preferably connected between the SNSN pin and the second end (low potential end) of the sense resistor Rs.

[0055] However, simply providing external current limiting resistors RpP and RpN reduces the accuracy of detecting the output current ILED in the LED driver IC 1. This point will be considered in detail below.

[0056] FIG. 8 is a diagram showing how a gain error occurs in the current sense amplifier 16 due to the external attachment of current limiting resistors RpP and RpN.

[0057] As shown in this diagram, the current sense amplifier 16 includes a current output type differential amplifier AMP1, input resistors R1P and R1N, and an output resistor R2. The non-inverting input terminal (+) of the differential amplifier AMP1 is connected to a first terminal of the input resistor R1P (e.g., 10 kΩ). The second terminal of the input resistor R1P is connected to the SNSP pin. The inverting input terminal (-) of the differential amplifier AMP1 is connected to a first terminal of the input resistor R1N (e.g., 10 kΩ). The second terminal of the input resistor R1N is connected to the SNSN pin. The output terminal of the differential amplifier AMP1 is connected to a first terminal of the output resistor R2 (e.g., 120 kΩ) and also to the non-inverting input terminal (+) of the differential amplifier AMP1. The second terminal of the output resistor R2 is connected to ground.

[0058] The slope signal generating unit 15 also includes a current-output differential amplifier AMP2, input resistors R3P and R3N, and an output resistor R4. The non-inverting input terminal (+) of the differential amplifier AMP2 is connected to a first terminal of the input resistor R3P (e.g., 10 kΩ). The second terminal of the input resistor R3P is connected to the SNSP pin. The inverting input terminal (-) of the differential amplifier AMP2 is connected to a first terminal of the input resistor R3N (e.g., 10 kΩ). The second terminal of the input resistor R3N is connected to the SNSN pin. The output terminal of the differential amplifier AMP2 is connected to a first terminal of the output resistor R4 (e.g., 10 kΩ) and also to the non-inverting input terminal (+) of the differential amplifier AMP2. The second terminal of the output resistor R4 is connected to ground.

[0059] A feedback current I1 flows between the non-inverting input terminal (+) and output terminal of the differential amplifier AMP1. This feedback current I1 is essential for highly accurate current feedback control. A feedback current I2 flows between the non-inverting input terminal (+) and output terminal of the differential amplifier AMP2.

[0060] Thus, a typical current sense amplifier 16 for nonlinear control of the average inductor current IL_ave includes a differential amplifier AMP1 having a floating input stage that can amplify the sense voltage Vsns rail-to-rail (between the power supply potential and the ground potential). Here, "floating" means floating from the ground potential (potentially separated).

[0061] If the current limiting resistors RpP and RpN are not externally attached to the SNSP pin and the SNSN pin, respectively, the gain G of the current sense amplifier 16 is uniquely determined according to the ratio of the input resistance R1 to the output resistance R2 (G = R2 / R1, for example, G = 12).

[0062] On the other hand, when the current limiting resistors RpP and RpN are externally connected, the terminal current (I1 + I2) flowing through the SNSP pin causes the differential input current difference ΔIBIAS of the differential amplifier AMP1 (= the difference between the input currents flowing through the non-inverting input terminal (+) and the inverting input terminal (-) of the differential amplifier AMP1) to fluctuate.

[0063] As a result, the gain G of the current sense amplifier 16 is no longer uniquely determined according to the ratio of the input resistance R1 and the output resistance R2, and the current detection signal VISET (=Vsns.R2.R3 / (R1.R3+R3.Rp+Rp.R1)) significantly deviates from its original value (=Vsns.R2 / R1). In particular, the larger the feedback currents I1 and I2, the greater the fluctuations in the current detection signal VISET.

[0064] Furthermore, the input resistor R1 and output resistor R2 built into the LED driver IC1 are paired with each other and work to cancel out their respective temperature characteristics, but the external current limiting resistors RpP and RpN have temperature coefficients that are completely different from those of the input resistor R1 and output resistor R2, and there are also manufacturing variations in each of them, which results in large variations in the temperature characteristics of the final current detection signal VISET.

[0065] It is possible to trim the input resistor R1 so that the combined resistance of the input resistor R1 and the current limiting resistor RpP is always constant, but this would make the chip size of the LED driver IC1 very large, so this is not a very realistic solution.

[0066] 9 is a diagram showing a fourth embodiment of an LED lamp module. In the LED lamp module Z of the fourth embodiment, the aforementioned components (LED driver IC1, LED string 2, inductor L1, capacitor Co, sense resistor Rs, and current limiting resistors RpP and RpN) are provided for two channels (indicated in the figure by adding A and B to the end of the reference numerals of the respective components), and an MCU 4 is configured to control both channels in an integrated manner.

[0067] The LED driver ICs 1A and 1B each include a buck converter that supplies power to the LED strings 2A and 2B, a temperature detection unit that detects the internal junction temperature Tj, and a communication unit that communicates with the MCU 4 via SPI (serial peripheral interface).

[0068] Here, the problem caused by externally attaching the current limiting resistors RpPA and RpNA, and the current limiting resistors RpPB and RpNB is a decrease in the current detection accuracy (particularly temperature drift) in the LED driver ICs 1A and 1B.

[0069] One possible solution to this problem is to use the MCU 4 to monitor the internal junction temperatures Tj of the LED driver ICs 1A and 1B, and dynamically correct the detection results of the sense voltages VsnsA and VsnsB on an ongoing basis based on the monitoring results.

[0070] FIG. 10 shows the temperature characteristics of the sense voltage Vsns (corresponding to the aforementioned current detection signal VISET). The thick solid line VsnsA indicates the detection result of the sense voltage VsnsA in the LED driver IC 1A. The thick solid line VsnsB indicates the detection result of the sense voltage VsnsB in the LED driver IC 1B. Meanwhile, the thin solid line Vsns (@RpP = RpN = 0Ω) indicates the detection result of the sense voltage Vsns when neither the current limiting resistors RpP nor RpN are externally connected. The thick dashed line Vsns (typical) indicates the temperature characteristics that serve as the correction reference for the MCU 4.

[0071] As shown in the figure, the detection results of the sense voltages VsnsA and VsnsB have different temperature characteristics. For example, at Tj = +25°C, the detection results of the sense voltages VsnsA and VsnsB are shifted by +a% and +b% (where a≠b) relative to the detection results when there are no external resistors.

[0072] Therefore, even if the temperature characteristic of +c% (where c≠a, b) is used as the correction standard and the detection results of the sense voltages VsnsA and VsnsB are dynamically corrected using the MCU 4, it is difficult to fully cancel out the temperature characteristics of each. Referring to this figure, over the entire temperature range (-40°C to +150°C), a temperature drift of up to ±(d+e)% remains between the LED driver ICs 1A and 1B.

[0073] Furthermore, in order to constantly dynamically correct the detection results of the sense voltages VsnsA and VsnsB using the MCU 4, it is necessary to constantly execute read / write command sequences, which increases the load on the MCU 4.

[0074] 11 is a diagram showing a fifth embodiment of an LED lamp module. In the LED lamp module Z of the fifth embodiment, the LED driver IC1 has a functional unit (ΔIBIASctl) for reducing the differential input current difference ΔIBIAS of the differential amplifier AMP1 (see FIG. 8) that forms the current sense amplifier 16, and is designed to reduce the gain error of the current sense amplifier 16 even when current limiting resistors RpP and RpN are externally connected.

[0075] 12 is a diagram showing elimination of the gain error in the current sense amplifier 16. As shown in the diagram, in the LED driver IC1 of the fifth embodiment, the current sense amplifier 16 not only has a first feedback current path configured to pass a feedback current I1 between the non-inverting input terminal (+) and the output terminal of the differential amplifier AMP1, but also has a new second feedback current path configured to pass a feedback current I1′ between the SNSN pin and the output terminal of the differential amplifier AMP1.

[0076] The feedback current I1' is a copy (mirror current) of the feedback current I1, and the respective current values ​​should be set to the same value (maximum of approximately 20 μA). In this way, by flowing a feedback current I1' of the same value as the feedback current I1 also on the reference side of the differential amplifier AMP1, the differential input current difference ΔIBIAS can be made close to zero.

[0077] However, it is not necessary that the feedback current I1 and the feedback current I1' have exactly the same value, and for example, an arbitrary offset may be added between the two.

[0078] Furthermore, the slope signal generating unit 15 includes a gm amplifier AMP2g, instead of the differential amplifier AMP2 described above, that detects the sense voltage Vsns that appears between the SNSP pin and the SNSN pin without drawing current from both terminals. In this way, in the slope signal generating unit 15, which does not require particularly high current detection accuracy, the use of the gm amplifier AMP2g, which does not require feedback current control, makes it possible to reduce the feedback current I2 described above to zero.

[0079] With this configuration, even if current limiting resistors RpP and RpN are externally attached to the SNSP pin and the SNSN pin, respectively, the gain G of the current sense amplifier 16 is uniquely determined according to the ratio of the input resistance R1 and the output resistance R2, making it possible to eliminate deterioration in current detection accuracy (especially temperature drift) in the LED driver IC1.

[0080] Furthermore, by attaching external current limiting resistors RpP and RpN, the electrostatic protection diode Desd (see FIG. 5) of the LED driver IC1 can be protected from surge currents ID1 and ID2. This eliminates the need for external surge protection diodes DH and DL, which were previously required for each channel. As a result, it is possible to reduce the cost of the LED lamp module Z and the component mounting area on the board.

[0081] In the on-time setting unit 14 (see FIG. 1), a simple resistive voltage divider circuit is often used as a means for detecting the terminal voltage (=VLED) appearing at the SNSN pin. However, in consideration of improving the accuracy of current detection, it is desirable to use a source follower in the on-time setting unit 14, instead of the resistive voltage divider circuit, which detects the terminal voltage appearing at the SNSN pin without drawing current from the SNSP and SNSN pins.

[0082] <LED Lamp Module (Sixth Embodiment)> Figure 13 is a diagram showing a sixth embodiment of an LED lamp module. In the LED lamp module Z of the sixth embodiment, the LED driver IC1 includes a valley current control unit 20, a current sense amplifier 21, a VI converter 22, and a DAC 23, instead of the components 15 to 19 in Figure 1. The LED driver IC1 also integrates input resistors R5P and R5N (e.g., both 10 kΩ) and feedback resistors R6P and R6N (e.g., both 140 kΩ). These components 20 to 23 can all be understood as components of a current detection circuit.

[0083] The valley current control unit 20 generates the aforementioned set signal SET by detecting the bottom (valley detection) of the inductor current IL based on the sense voltage Vsns generated across the sense resistor Rs and the current detection signal CS generated by the current sense amplifier 21.

[0084] The current sense amplifier 21 is a current output type differential amplifier equipped with a floating input stage capable of amplifying an input signal rail-to-rail. The inverting input terminal (-) of the current sense amplifier 21 is connected to a first terminal of an input resistor R5P. The second terminal of the input resistor R5P is connected to the SNSP pin. The non-inverting input terminal (+) of the current sense amplifier 21 is connected to a first terminal of an input resistor R5N. The second terminal of the input resistor R5N is connected to the SNSN pin. The output terminal of the current sense amplifier 21 is connected to a phase compensation capacitor Cc via the COMP pin.

[0085] The VI converter 22 is a functional block that converts a voltage signal (=current adjustment voltage VIadj) into a current signal (=reference currents I11 and I11'), and includes an operational amplifier 22a and NMOSFETs 22b and 22c.

[0086] The operational amplifier 22a controls the gates of the NMOSFETs 22b and 22c so that the current adjustment voltage VIadj input to its non-inverting input terminal (+) matches the terminal voltage (=I11×R6P) of the feedback resistor R6P input to its inverting input terminal (-). Therefore, the reference current I11 flowing through the NMOSFET 22b and the reference current I11' flowing through the NMOSFET 22c each have a current value (=VIadj / R6P) that corresponds to the voltage value of the current adjustment voltage VIadj and the resistance value of the feedback resistor R6P. In other words, the gain of the VI converter 22 is determined by the feedback resistor R6P.

[0087] The drain of the NMOSFET 22b is connected to the inverting input terminal (-) of the current sense amplifier 21 and the first terminal of the input resistor R5P. The source of the NMOSFET 22b is connected to the first terminal of the feedback resistor R6P and the inverting input terminal (-) of the operational amplifier 22a. The second terminal of the feedback resistor R6P is connected to ground. The gate of the NMOSFET 22b is connected to the output terminal of the operational amplifier 22a.

[0088] Meanwhile, the drain of the NMOSFET 22c is connected to the second terminal of the input resistor R5N and the SNSN pin. The source of the NMOSFET 22c is connected to the first terminal of the feedback resistor R6N. The second terminal of the feedback resistor R6N is connected to the ground terminal. The gate of the NMOSFET 22c is connected to the output terminal of the operational amplifier 22a.

[0089] The DAC 23 converts a digital signal (for example, 10 bits) not shown into an analog current adjustment voltage VIadj.

[0090] In the current detection circuit of this embodiment, the current sense amplifier 21 generates a current detection signal CS by amplifying the difference between the scaled current adjustment voltage (= VIadj × R5P / R6P) and the sense voltage Vsns input between the SNSP pin and the SNSN pin. This current detection signal CS controls the bottom detection value (valley detection value) of the inductor current IL. As a result, the output current ILED is adjusted to VIadj × R5P / (R6P × Rs).

[0091] 14 is a diagram equivalent to the current detection circuit of the sixth embodiment. The feedback resistor R6 in this diagram can be understood as the feedback resistor R6P (or feedback resistor R6N) in FIG.

[0092] As shown in the figure, in the current detection circuit of this embodiment, in order to generate the reference voltage (=scaled current adjustment voltage VIadj×R5P / R6) for the current sense amplifier 21, it is necessary to flow a reference current I11 through the VI converter 22. For this reason, the current detection circuit of this embodiment includes a first reference current path configured to flow the reference current I11 between the SNSP pin and the first output terminal (=drain of NMOSFET 22b) of the VI converter 22.

[0093] However, in a configuration in which the reference current I11 flows only through the current limiting resistor RpP externally attached to the SNSP pin, the reference voltage of the current sense amplifier 21 will deviate by the voltage across the current limiting resistor RpP. Therefore, the current detection circuit of this embodiment includes a second reference current path configured to pass a reference current I11' between the SNSN pin and the second output terminal (=the drain of the NMOSFET 22c) of the VI converter 22. Note that the reference currents I11 and I11' may have the same value, or an arbitrary offset may be added between them.

[0094] In this way, with the configuration in which the reference current I11 required to generate the reference voltage of the current sense amplifier 21 is corrected by the reference current I11′, even if current limiting resistors RpP and RpN are externally attached to the SNSP pin and the SNSN pin, respectively, the gain of the VI converter 22 (and therefore the reference voltage of the current sense amplifier 21) is uniquely determined according to the ratio between the input resistor R5P and the feedback resistor R6, making it possible to eliminate degradation in current detection accuracy (particularly temperature drift) in the LED driver IC1.

[0095] In the current detection circuit of this embodiment, the current sense amplifier 21 functions as a gm amplifier that generates the current detection signal CS by amplifying the difference between the scaled current adjustment voltage (= VIadj × R5P / R6P) and the sense voltage Vsns without drawing the feedback current I2 from the SNSP pin and the SNSN pin.

[0096] 15 is a diagram showing a seventh embodiment of an LED lamp module (corresponding to a first comparative example to be compared with the eighth and ninth embodiments described later). In the LED lamp module Z of this embodiment, the LED driver IC1 is based on the first embodiment (FIG. 1) described above, but includes a current sense amplifier 31, an error amplifier 32, and a VI converter 33 instead of the components 15 to 17 and 19.

[0097] The current sense amplifier 31 is a functional block that generates a slope signal Vslp containing current information regarding the inductor current IL in response to the sense voltage Vsns_IC applied between the SNSP pin and the SNSN pin and outputs the signal to the comparator 18 (not shown), and includes a gm amplifier AMP31, input resistors R7P and R7N, and an output resistor R8.

[0098] The non-inverting input terminal (+) of the gm amplifier AMP31 is connected to a first terminal of the input resistor R7P. ​​The second terminal of the input resistor R7P is connected to the SNSP pin. The inverting input terminal (-) of the gm amplifier AMP31 is connected to a first terminal of the input resistor R7N. The second terminal of the input resistor R7N is connected to the SNSN pin. The output terminal of the gm amplifier AMP31 is connected to a first terminal of the output resistor R8. The second terminal of the output resistor R8 is connected to the ground terminal.

[0099] The gm amplifier AMP31 also includes a first feedback current path configured to pass a first feedback current i11 between its output terminal and a non-inverting input terminal (+), and a second feedback current path configured to pass a second feedback current i11' between its output terminal and an inverting input terminal (-). Note that the second feedback current i11' may be a copy (mirror current) of the first feedback current i11, or may be a copy of the first feedback current i11 with an offset.

[0100] The error amplifier 32 is a functional block that generates an error signal Vc in response to a sense voltage Vsns_IC applied between the SNSP pin and the SNSN pin, and includes a gm amplifier AMP32, input resistors R9P and R9N, and a capacitor Cc.

[0101] The non-inverting input terminal (+) of the gm amplifier AMP32 is connected to a first terminal of the input resistor R9P. The second terminal of the input resistor R9P is connected to the power supply terminal of the gm amplifier AMP32 and the SNSP pin. The inverting input terminal (-) of the gm amplifier AMP32 is connected to a first terminal of the input resistor R9N. The second terminal of the input resistor R9N is connected to the SNSN pin. The output terminal of the gm amplifier AMP32 is connected to a first terminal of the capacitor Cc. The second terminal of the capacitor Cc is connected to the ground terminal.

[0102] The VI converter 33 is a functional block that converts the current adjustment voltage VIadj into a reference current i12, and includes a gm amplifier AMP33 and a feedback resistor R10. The gm amplifier AMP33 controls the reference current i12 that flows through the input resistor R9P so that the current adjustment voltage VIadj input to the non-inverting input terminal (+) matches the terminal voltage of the feedback resistor R10 (= i12 × R10) input to the inverting input terminal (-).

[0103] As described above, in the LED driver IC1 of this embodiment, the current sense amplifier 31 for detecting the current ripple component ΔIL and the error amplifier 32 for detecting the average inductor current IL_ave are connected in parallel to the SNSP pin and the SNSN pin.

[0104] When a sense voltage Vsns_IC is generated between the SNSP pin and the SNSN pin, an input potential difference ΔV occurs in the current sense amplifier 31, causing a detection current I31 to flow through the SNSP pin. As a result, a current difference occurs between the SNSP pin and the SNSN pin, which leads to a decrease in the current detection accuracy of the LED driver IC1 (and ultimately a deviation from the target value of the output current ILED). To eliminate this current difference, the input potential difference ΔV of the current sense amplifier 31 must be set to zero.

[0105] On the other hand, in the error amplifier 32, the difference between the sense voltage Vsns_IC and the reference voltage (=input potential difference Vin) becomes zero due to output feedback control.

[0106] In view of the above considerations, the inventors of the present application have found that if the feedback control point (Vin=0) of the error amplifier 32 is set as the input of the current sense amplifier 31, the input potential difference ΔV of the current sense amplifier 31 becomes 0. A new embodiment based on this finding will be proposed below.

[0107] 16 is a diagram showing an eighth embodiment of an LED lamp module. In the LED lamp module Z of this embodiment, the LED driver IC1 is based on the first embodiment (FIG. 1) described above, but includes a current sense amplifier 41, an error amplifier 42, and a VI converter 43 instead of the components 15 to 17 and 19.

[0108] The current sense amplifier 41 is a functional block that generates a current detection signal Vcso including current information on the inductor current IL in response to the sense voltage Vsns_IC applied between the SNSP pin and the SNSN pin and outputs the signal to the comparator 18 (not shown), and includes a gm amplifier AMP41, input resistors R11P and R11N, and an output resistor R12.

[0109] The non-inverting input terminal (+) of the gm amplifier AMP41 is connected to a first terminal of the input resistor R11P. The second terminal of the input resistor R11P is connected to the SNSP pin. The inverting input terminal (-) of the gm amplifier AMP41 is connected to a first terminal of the input resistor R11N. The second terminal of the input resistor R11N is connected to the SNSN pin. The output terminal of the gm amplifier AMP41 is connected to a first terminal of the output resistor R12. The second terminal of the output resistor R12 is connected to an application terminal of the reference signal Vref.

[0110] The gm amplifier AMP41 also includes a first feedback current path configured to pass a first feedback current i21 between its output terminal and a non-inverting input terminal (+), and a second feedback current path configured to pass a second feedback current i21' between its output terminal and an inverting input terminal (-). Note that the second feedback current i21' may be a copy (mirror current) of the first feedback current i21, or may be a copy of the first feedback current i21 with an offset.

[0111] The error amplifier 42 is a functional block that generates an error signal Vc according to the error between the current detection signal Vcso and a predetermined reference signal Vref, and includes a gm amplifier AMP42 and a capacitor Cc.

[0112] The non-inverting input terminal (+) of the gm amplifier AMP42 is connected to the application terminal of the reference signal Vref. The inverting input terminal (-) of the gm amplifier AMP42 is connected to the application terminal of the current detection signal Vcso. The output terminal of the gm amplifier AMP42 is connected to the first terminal of the capacitor Cc. The second terminal of the capacitor Cc is connected to the ground terminal.

[0113] The VI converter 43 is a functional block that converts the current adjustment voltage VIadj into a reference current i22, and includes a gm amplifier AMP43 and a feedback resistor R13. The gm amplifier AMP43 controls the reference current i22 that flows through the input resistor R11P so that the current adjustment voltage VIadj input to the non-inverting input terminal (+) matches the terminal voltage of the feedback resistor R13 (= i22 × R13) input to the inverting input terminal (-).

[0114] In this way, in the LED driver IC1 of this embodiment, the current sense amplifier 41 and the error amplifier 42 share a common input system. In other words, the current sense amplifier 41 and the error amplifier 42 are connected in tandem to the SNSP pin and the SNSN pin.

[0115] Therefore, the feedback control point (Vin=0) of the error amplifier 32 becomes the input of the current sense amplifier 31, and the input potential difference ΔV of the current sense amplifier 31 becomes 0. As a result, even if a sense voltage Vsns_IC is generated between the SNSP pin and the SNSN pin, no current difference occurs between the SNSP pin and the SNSN pin, and therefore, the current detection accuracy of the LED driver IC1 is less likely to decrease (and thus the output current ILED does not deviate from the target value).

[0116] <LED Lamp Module (Ninth Embodiment)> Fig. 17 is a diagram showing a ninth embodiment of an LED lamp module. In the LED lamp module Z of this embodiment, the LED driver IC1 is based on the eighth embodiment (Fig. 16) and further improved to make the current difference between the SNSP pin and the SNSN pin close to zero.

[0117] More specifically, the VI converter 43 causes the reference current i22 to flow through the input resistor R11P, and also draws a correction current i22' equal to the reference current i22 directly from the SNSN pin, as shown in FIG.

[0118] Furthermore, a sink current i23 flows from the SNSP pin to the ground terminal in a resistive voltage divider circuit (resistors R14 and R15) for transmitting the terminal voltage (=VLED+Vsns_R+VRpP) appearing at the SNSP pin to the on-time setting unit 14. Therefore, a resistive circuit (resistors R16 and R17) is provided between the SNSN pin and the ground terminal for passing a correction current i23' equal to the sink current i23.

[0119] In the LED driver IC1 of this embodiment, i21 = i21', i22 = i22', and i23 = i23' hold true. Therefore, the combined current flowing through the SNSP pin (= i21 + i22 + i23) is equal to the combined current flowing through the SNSN pin (= i21' + i22' + i23'). In other words, the current difference between the SNSP pin and the SNSN pin is always zero.

[0120] With this configuration, even if current limiting resistors RpP and RpN are externally attached to the SNSP pin and the SNSN pin, respectively, it is possible to eliminate the degradation of current detection accuracy in the LED driver IC1 (particularly temperature drift).

[0121] Furthermore, by attaching external current limiting resistors RpP and RpN, the electrostatic protection diode Desd (see FIG. 5) of the LED driver IC1 can be protected from surge currents ID1 and ID2. This eliminates the need for external surge protection diodes DH and DL, which were previously required for each channel. As a result, it is possible to reduce the cost of the LED lamp module Z and the component mounting area on the board.

[0122] <LED Lamp Module (Tenth Embodiment)> Fig. 18 is a diagram showing a tenth embodiment of the LED lamp module (corresponding to a second comparative example to be compared with the eleventh embodiment described below). This diagram depicts an example of a more specific circuit configuration based on the first embodiment (Fig. 1). Therefore, components already described are assigned the same reference numerals as in Fig. 1, and redundant explanations will be omitted. The following description will focus on new components and changes.

[0123] The LED driver IC1 of this embodiment integrates resistors R21, R22, and Ro in addition to the previously mentioned slope signal generating unit 15, current sense amplifier 16, error amplifier 17, comparator 18, input resistors R1P and R1N, and capacitor Cc.

[0124] In addition, in the LED driver IC1 of this embodiment, current limiting resistors RpP and RpN are connected between the first end (high potential end) of the sense resistor Rs and the SNSP pin, and between the second end (low potential end) of the sense resistor Rs and the SNSN pin, respectively.

[0125] The error amplifier 17 outputs a current corresponding to the difference between the analog dimming signal Vdcdim (corresponding to a predetermined current setting signal) input to its non-inverting input terminal (+) and the current detection signal VISET input to its inverting input terminal (-), and generates an error signal Vc by charging and discharging a capacitor Cc. Therefore, the error signal Vc rises when VISET<Vdcdim and falls when VISET>Vdcdim. A resistor ro is connected in parallel with the capacitor Cc between the output terminal and ground terminal of the error amplifier 17. The capacitor Cc is used for phase compensation. The resistor ro is the output impedance of the error amplifier 17 and does not exist as an actual element.

[0126] The slope signal generating unit 15 is a gm amplifier that receives a current supply from the PIN pin and can detect the sense voltage Vsns that appears between the SNSP and SNSN pins without drawing current from them. A resistor R22 is connected between the output terminal of the slope signal generating unit 15 and the ground terminal.

[0127] The current sense amplifier 16 receives power from the PIN pin and amplifies the sense voltage Vsns to generate the current detection signal VISET. The non-inverting input terminal (+) of the current sense amplifier 16 is connected to the SNSP pin via an input resistor R1P. The inverting input terminal (-) of the current sense amplifier 16 is connected to the SNSN pin via an input resistor R1N. The output terminal of the current sense amplifier 16 (= the terminal to which the current detection signal VISET is applied) is connected to the first terminal of a resistor R21 and also to the inverting input terminal (-) of the error amplifier 17. The second terminal of the resistor R21 is connected to ground.

[0128] The current sense amplifier 16 also includes a first feedback current path configured to pass a first feedback current i31 between its output terminal and its non-inverting input terminal (+), and a second feedback current path configured to pass a second feedback current i31' between its output terminal and the SNSN pin. The second feedback current i31' may be a copy (mirror current) of the first feedback current i31, or may be a copy of the first feedback current i31 with an offset.

[0129] With this configuration, even if current limiting resistors RpP and RpN are externally attached to the SNSP pin and the SNSN pin, respectively, it is possible to reduce the differential input current difference of the current sense amplifier 16 (and thus the gain error of the current sense amplifier 16), thereby eliminating the degradation of current detection accuracy (particularly temperature drift) in the LED driver IC1.

[0130] Furthermore, by attaching external current limiting resistors RpP and RpN, the electrostatic protection diodes Desd (FIG. 5) built into the SNSP pin and the SNSN pin, respectively, can be protected from surge currents. This eliminates the need for external surge protection diodes DH and DL (FIG. 7), thereby reducing the cost of the LED lamp module Z and the component mounting area on the board.

[0131] However, the LED driver IC1 of this embodiment requires two floating amplifiers (a slope signal generator 15 and a current sense amplifier 16) that can amplify the sense voltage Vsns rail-to-rail (between the power supply potential and the ground potential). Therefore, it should be noted that the circuit area becomes large. Note that "floating" in this specification means floating from the ground potential (potentially separated).

[0132] FIG. 19 is a diagram showing an example of signal transmission in the LED driver IC1 of the tenth embodiment (= a block diagram rewritten from FIG. 16 ). The symbol Gcs denotes the gain of the slope signal generating unit 15. The symbol Gsns denotes the gain of the current sense amplifier 16. The symbol gm denotes the transconductance of the error amplifier 17 (= the value converted from the amplifier input voltage to the amplifier output current). The symbol ΔVsns denotes the sense voltage Vsns. The symbol X denotes the current setting value (target value) of the output current ILED. The symbol ΔVc denotes the error signal Vc. The symbol ΔD denotes the off-duty of the lower switch 11L (control of the bottom value of the inductor current IL → control of the off-period). The symbol ro denotes the resistance value of the resistor ro (= the output impedance of the error amplifier 17). The symbol Cc denotes the capacitance value of the capacitor Cc. The symbol s denotes the complex number s (= jω).

[0133] As can be seen from this figure, the signal transmission system in the LED driver IC1 of the tenth embodiment has first-order characteristics with the inductor current IL (=average inductor current IL_ave+current ripple component ΔIL) as the control point.

[0134] <LED Lamp Module (Eleventh Embodiment)> Figure 20 is a diagram showing an eleventh embodiment of an LED lamp module. In addition to the current sense amplifier 16, error amplifier 17, comparator 18, input resistors R1P and R1N, and capacitor Cc shown in Figure 18, the LED driver IC1 of this embodiment also integrates a bias amplifier 1A, a VI converter 1B, transistors P1a and P1b (e.g., PMOSFETs [P-channel type MOSFETs]), and resistors R31a, R31b, R32a, R32b, R33, R34a, R34b, and Ro. However, the LED driver IC1 of this embodiment does not include the slope signal generator 15.

[0135] In addition, in the LED driver IC1 of this embodiment, current limiting resistors RpP and RpN are connected between the first end (high potential end) of the sense resistor Rs and the SNSP pin, and between the second end (low potential end) of the sense resistor Rs and the SNSN pin, respectively, as in the case of FIG.

[0136] The VI converter 1B is a functional block that converts a voltage signal (=analog dimming signal Vdcdim) into a current signal (=first reference current i41 and second reference current i41').

[0137] As shown in the figure, in the LED driver IC1 of this embodiment, a first reference current i41 needs to flow through the VI converter 1B to generate the reference voltage (=scaled analog dimming signal Vdcdim×R1P / R33) for the current sense amplifier 16. Therefore, the LED driver IC1 of this embodiment includes a first reference current path configured to flow the first reference current i41 between the SNSP pin and the first output terminal of the VI converter 1B.

[0138] However, in a configuration in which the first reference current i41 flows only through the current-limiting resistor RpP externally attached to the SNSP pin, the reference voltage of the current sense amplifier 16 will deviate by the voltage across the current-limiting resistor RpP. Therefore, the LED driver IC1 of this embodiment includes a second reference current path configured to pass a second reference current i41' between the SNSN pin and the second output terminal of the VI converter 1B. The first reference current i41 and the second reference current i41' may have the same value, or an arbitrary offset may be applied between them.

[0139] In this manner, with the configuration in which the first reference current i41 required to generate the reference voltage of the current sense amplifier 16 is corrected by the second reference current i41′, even if current limiting resistors RpP and RpN are externally attached to the SNSP pin and the SNSN pin, respectively, the gain of the VI converter 1B (and therefore the reference voltage of the current sense amplifier 16) is uniquely determined according to the ratio between the input resistor R1P and the resistor R33, making it possible to eliminate degradation in current detection accuracy (particularly temperature drift) in the LED driver IC1.

[0140] The current sense amplifier 16 amplifies the sense voltage Vsns to generate a differential current detection signal ΔVcso (=VcsoP-VcsoN). The non-inverting input terminal (+) of the current sense amplifier 16 is connected to the SNSP pin via an input resistor R1P. The inverting input terminal (-) of the current sense amplifier 16 is connected to the SNSN pin via an input resistor R1N. The first differential output terminal of the current sense amplifier 16 is connected to the first terminal of a resistor R31a and also to the inverting input terminal (-) of an error amplifier 17. The second differential output terminal of the current sense amplifier 16 is connected to the first terminal of a resistor R31b and also to the non-inverting input terminal (+) of the error amplifier 17. The second terminals of the resistors R31a and R31b are both connected to ground. Resistors R32a and R32b are connected in series between the non-inverting input terminal (+) and the inverting input terminal (-) of the current sense amplifier 16, and the drive voltage of the current sense amplifier 16 is supplied from the connection node between them.

[0141] The error amplifier 17 outputs a current corresponding to a current detection signal ΔVcso differentially input between the non-inverting input terminal (+) and the inverting input terminal (−), and generates an error signal Vc by charging and discharging a capacitor Cc. Note that a resistor Ro is connected in parallel with the capacitor Cc between the output terminal of the error amplifier 17 and the ground terminal.

[0142] The gate of the transistor P1a is connected to the first differential output terminal of the current sense amplifier 16. The drain of the transistor P1a is connected to the ground terminal. The source of the transistor P1a is connected to the first terminal of the resistor R34a. The second terminal of the resistor R34a is connected to the inverting input terminal (-) of the comparator 18. The transistor P1a connected in this manner functions as a first voltage follower (first source follower) connected between the first differential output terminal of the current sense amplifier 16 and the inverting input terminal (-) of the comparator 18.

[0143] The gate of the transistor P1b is connected to the second differential output terminal of the current sense amplifier 16. The drain of the transistor P1b is connected to the ground terminal. The source of the transistor P1b is connected to the first terminal of the resistor R34b. The second terminal of the resistor R34b is connected to the non-inverting input terminal (+) of the comparator 18. The transistor P1b connected in this manner functions as a second voltage follower (second source follower) connected between the second differential output terminal of the current sense amplifier 16 and the non-inverting input terminal (+) of the comparator 18.

[0144] The bias amplifier 1A determines the operating points of the first voltage follower and the second voltage follower by outputting differential currents to the resistors R34a and R34b, respectively, according to the difference between the error signal Vc input to the non-inverting input terminal (+) and the bias voltage Vbias input to the inverting input terminal (-).

[0145] Referring to this figure, the inverting input terminal (-) of the comparator 18 receives a subtraction signal (=VcsoP+Vgs(P1a)-(Vc-Vbias)) obtained by subtracting the error signal Vc from the output signal (=VcsoP+Vgs(P1a)) of the first voltage follower.

[0146] On the other hand, the non-inverting input terminal (+) of the comparator 18 receives an addition signal (=VcsoN+Vgs(P1b)+(Vc-Vbias)) obtained by adding the error signal Vc to the output signal (=VcsoN+Vgs(P1b)) of the second voltage follower.

[0147] Therefore, in the comparator 18, when (VcsoP-Vc)-(VcsoN+Vc)>0, that is, when ΔVcso-2Vc>0, the logical level of the set signal SET is switched. To further explain, the bottom value of the inductor current IL is detected at the point where the current information ΔVcso reaches the control voltage Vc.

[0148] If the difference between the inductor current IL and its target value is sensed, the differential input difference of the current sense amplifier 16 becomes zero (the DC error is zero), and no current difference occurs between the SNSP pin and the SNSN pin. As a result, there is no need to supply power to the current sense amplifier 16 from the PIN pin, and a Δ zero bias current can be achieved. Furthermore, the slope signal generator 15 can be integrated into the current sense amplifier 16, allowing for a smaller circuit size.

[0149] FIG. 21 is a diagram showing an example of signal transmission in the LED driver IC1 of the eleventh embodiment (= a block diagram redrawn from the aforementioned FIG. 20). The symbol Gsns denotes the gain of the current sense amplifier 16. The symbol gm denotes the transconductance of the error amplifier 17 (= the value converted from the amplifier input voltage to the amplifier output current). The symbol ΔVsns denotes the sense voltage Vsns. The symbol X denotes the current setting value (target value) of the output current ILED. The symbol ΔVc denotes the error signal Vc. The symbol ΔD denotes the off-duty of the lower switch 11L (control of the bottom value of the inductor current IL → control of the off-interval). The symbol ro denotes the resistance value of the resistor ro (= the output impedance of the error amplifier 17). The symbol Cc denotes the capacitance value of the capacitor Cc. The symbol s denotes the complex number s (= jω).

[0150] As can be seen from this diagram, the signal transmission system in the LED driver IC1 of the eleventh embodiment is a system in which only the current ripple component ΔIL of the inductor current IL is a control point. Furthermore, in this signal transmission system, a high-speed path can be generated for the current error component (= the difference between the output current ILED and the current setting value).

[0151] <Generalization> The following provides a general description of the various embodiments disclosed in this specification.

[0152] a first input resistor connected between a first input terminal and a first current sense terminal of the differential amplifier; a second input resistor connected between a second input terminal and a second current sense terminal of the differential amplifier; an output resistor connected to an output terminal of the differential amplifier; a first feedback current path configured to cause a first feedback current to flow between the first input terminal and the output terminal of the differential amplifier; and a second feedback current path configured to cause a second feedback current to flow between the second input terminal and the output terminal of the differential amplifier (first configuration).

[0153] In the semiconductor device according to the first configuration, the first feedback current and the second feedback current may have the same value (second configuration).

[0154] Furthermore, the semiconductor device according to the first configuration may be configured (third configuration) in which an offset is applied to the first feedback current and the second feedback current.

[0155] a first reference current path configured to pass a first reference current between the first current sense terminal and a first output terminal of the VI converter; and a second reference current path configured to pass a second reference current between the second current sense terminal and a second output terminal of the VI converter.

[0156] In addition, a semiconductor device according to any of the first to fourth configurations may further include an on-time setting unit configured to generate a pulse in the reset signal when a predetermined on-time has elapsed from the timing of generating the pulse in the set signal, and the controller may be configured (fifth configuration) to control the monitored current so that it matches a predetermined target value using a bottom detection on-time fixed method in accordance with the set signal and the reset signal.

[0157] Furthermore, in the semiconductor device according to the fifth configuration, the on-time setting unit may be configured (sixth configuration) to include a source follower configured to detect the terminal voltage appearing at the second current sense terminal without drawing current from the first current sense terminal and the second current sense terminal.

[0158] Furthermore, the module disclosed in this specification is configured (seventh configuration) to include a semiconductor device having any one of the first to sixth configurations described above, an inductor, a sense resistor, and a load connected in series to an output element, a first current limiting resistor connected between the first current sense terminal and the sense resistor, and a second current limiting resistor connected between the second current sense terminal and the sense resistor.

[0159] In the module according to the seventh configuration, the load may include a light-emitting diode element (eighth configuration).

[0160] The module according to the eighth configuration may be configured (ninth configuration) further including a matrix manager configured to arbitrarily switch the number of series stages of the light-emitting diode elements.

[0161] <Other Modifications> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0162] DESCRIPTION OF SYMBOLS 1, 1A, 1B LED driver IC (semiconductor device) 2, 2A, 2B LED string 3 Matrix manager 4 MCU 11H Upper switch (NMOSFET) 11L Lower switch (NMOSFET) 12H Upper driver 12L Lower driver 13 Controller (RS flip-flop) 14 On-time setting unit 15 Slope signal generation unit 16 Current sense amplifier (current detection circuit) 17 Error amplifier 18 Comparator 19 DAC 1A Bias amplifier 1B V-I converter 20 Valley current control unit 21 Current sense amplifier 22 V-I converter 22a Operational amplifier 22b, 22c NMOSFET 23 DAC 31, 41 Current sense amplifier (current detection circuit) 32, 42 Error amplifier 33, 43 V-I converter AMP1, AMP2 Differential amplifier AMP2g gm amplifier AMP31, AMP32, AMP33 gm amplifier AMP41, AMP42, AMP43 gm amplifier Cb, Cc, Ci, Co, CoA, CoB Capacitor D1 Diode Desd Electrostatic protection diode DH, DL Surge protection diode L1, L1A, L1B Inductor Lx, Ly Parasitic inductance component R1P, R1N, R3P, R3N, R5P, R5N, R7P, R7N, R9P, R9N, R11P, R11N Input resistance R2, R4, R8, R12 Output resistance R6, R6P, R6N, R10, R13 Feedback resistance R14 to R17, R21, R22, R31a, R31b, R32a, R32b, R33, R34a, R34b Resistors RpP, RpN, RpPA, RpNA, RpPB, RpNB Current limiting resistors Rs, RsA, RsB Sense resistors Rt, ro Resistor Z LED lamp module

Claims

1. a current sense circuit configured to generate a current sense signal responsive to a monitored current; an error amplifier configured to generate an error signal corresponding to an error between the current detection signal and a predetermined reference signal; a comparator configured to compare the error signal with the current sense signal to generate a set signal; a controller configured to receive the set signal and control the monitored current; Equipped with The current detection circuit includes: A current output type differential amplifier; a first input resistor configured to be connected between the first input of the differential amplifier and a first current sense terminal; a second input resistor configured to be connected between the second input of the differential amplifier and a second current sense terminal; an output resistor configured to be connected to an output end of the differential amplifier; a first feedback current path configured to pass a first feedback current between the first input terminal and the output terminal of the differential amplifier; a second feedback current path configured to pass a second feedback current between the second input terminal and the output terminal of the differential amplifier; 13. A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein said first feedback current and said second feedback current have the same value.

3. 2. The semiconductor device according to claim 1, wherein an offset is applied to said first feedback current and said second feedback current.

4. a current sense circuit configured to generate a current sense signal responsive to a monitored current; an error amplifier configured to generate an error signal corresponding to an error between the current detection signal and a predetermined reference signal; a comparator configured to compare the error signal with the current sense signal to generate a set signal; a controller configured to receive the set signal and control the monitored current; Equipped with The current detection circuit includes: A current output type differential amplifier; a first input resistor configured to be connected between the first input of the differential amplifier and a first current sense terminal; a second input resistor configured to be connected between the second input of the differential amplifier and a second current sense terminal; a VI converter for converting a voltage signal into a current signal; a feedback resistor configured to determine the gain of the VI converter; a first reference current path configured to pass a first reference current between the first current sense terminal and a first output of the VI converter; a second reference current path configured to pass a second reference current between the second current sense terminal and a second output of the VI converter; 13. A semiconductor device comprising:

5. an on-time setting unit configured to generate a pulse in the reset signal when a predetermined on-time has elapsed from a pulse generation timing of the set signal, 5. The semiconductor device according to claim 1, wherein the controller controls the monitored current to coincide with a predetermined target value using a bottom detection on-time fixed method in response to the set signal and the reset signal.

6. 6. The semiconductor device according to claim 5, wherein the on-time setting unit includes a source follower configured to detect a terminal voltage appearing at the second current sense terminal without drawing current from the first current sense terminal and the second current sense terminal.

7. A semiconductor device according to any one of claims 1 to 4, an inductor, a sense resistor, and a load connected in series to an output element; a first current limiting resistor connected between the first current sense terminal and the sense resistor; a second current limiting resistor connected between the second current sense terminal and the sense resistor; A module comprising:

8. The module of claim 7 , wherein the load comprises a light emitting diode device.

9. The module according to claim 8 , further comprising a matrix manager configured to arbitrarily switch the number of series stages of the light-emitting diode elements.