Semiconductor device

Abstract

The semiconductor device includes: a chip having a major surface; a trench resistive structure formed on the major surface; a gate pad having a lower resistance value than the trench resistive structure and disposed over the trench resistive structure so as to be electrically connected to the trench resistive structure; and gate wiring having a lower resistance value than the trench resistive structure and disposed over the trench resistive structure so as to be electrically connected to the gate pad via the trench resistive structure.

Description

Semiconductor Devices

[0001] This application claims priority from Japanese Patent Application No. 2022-061315 filed on March 31, 2022, the entire content of which is incorporated herein by reference. The present invention relates to a semiconductor device.

[0002] Japanese Patent Application Laid-Open No. 2006-124499 discloses a semiconductor device including a semiconductor substrate, a plurality of trench structures, and a gate pad portion. The plurality of trench structures are formed on the surface of the semiconductor substrate. The gate pad portion is disposed on the semiconductor substrate so as to cover the plurality of trench structures.

[0003] US Patent Application Publication No. 2017 / 0040423

[0004] One embodiment provides a semiconductor device having a novel layout.

[0005] One embodiment provides a semiconductor device including a chip having a main surface, a trench resistance structure formed on the main surface, a gate pad having a lower resistance value than the trench resistance structure and arranged on the trench resistance structure so as to be electrically connected to the trench resistance structure, and a gate wiring having a lower resistance value than the trench resistance structure and arranged on the trench resistance structure so as to be electrically connected to the gate pad via the trench resistance structure.

[0006] The above and other objects, features, and advantages will become apparent from the following description of the embodiments with reference to the accompanying drawings.

[0007] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing a layout of gate electrodes and source electrodes. FIG. 4 is a plan view showing a layout of a first main surface. FIG. 5 is an enlarged plan view showing the vicinity of a resistor region. FIG. 6 is an enlarged plan view showing the layout of the vicinity of the resistor region. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 6 . FIG. 8 is an enlarged plan view showing the layout of a resistor region and an active region. FIG. 9 is an enlarged plan view showing the layout of an active region and a peripheral region. FIG. 10 is a cross-sectional view taken along line XX in FIG. 8 . FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 8 . FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 8 . FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 8 . FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 9 . FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 9 . FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 9 . FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 9 . FIG. 18 is an enlarged plan view showing the layout of the resistor region, active region, and dummy region. FIG. 19 is an enlarged plan view showing the layout of the active region, peripheral region, and dummy region. FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 18 . FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 18 . FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 18 . FIG. 23 is an enlarged plan view showing the layout of the termination region. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 23 . FIG. 25 is a cross-sectional view showing the structure of the peripheral region. FIG. 26 is an electrical circuit diagram showing the connection configuration of the gate electrode and the gate resistor. FIG. 27 is a cross-sectional view showing a trench resistor structure according to a first modified example. FIG. 28 is a cross-sectional view showing a trench resistor structure according to a second modified example. Fig. 29 is a cross-sectional view showing a trench resistor structure according to a third modified example. Fig. 30 is a cross-sectional view showing a trench resistor structure according to a fourth modified example. Fig. 31 is a cross-sectional view showing a chip according to a first modified example. Fig. 32 is a cross-sectional view showing a chip according to a second modified example.

[0008] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0009] When the phrase "substantially equal" is used in a description in which a comparison target is present, this phrase includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not attached with the intent of limiting the names of each structure.

[0010] FIG. 1 is a plan view showing a semiconductor device 1 according to one embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing the layout of a gate electrode 85 and a source electrode 95. FIG. 4 is a plan view showing the layout of a first main surface 3. The semiconductor device 1 is a semiconductor switching device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

[0011] 1 to 4, in this embodiment, a semiconductor device 1 includes a chip 2 that includes a single crystal of a wide bandgap semiconductor and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In other words, the semiconductor device 1 is a "wide bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip" or a "wide bandgap semiconductor chip." A wide bandgap semiconductor is a semiconductor that has a bandgap that exceeds the bandgap of Si (silicon). GaN (gallium nitride), SiC (silicon carbide), and C (diamond) are examples of wide bandgap semiconductors.

[0012] In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device." The semiconductor device 1 may also be referred to as a "SiC-MISFET." The hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may include other polytypes.

[0013] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2. The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of a SiC single crystal.

[0014] In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be more than 0° and not more than 10°. The off angle is preferably not more than 5°.

[0015] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0016] The chip 2 may have a thickness of 5 μm or more and 200 μm or less. The thickness of the chip 2 may be set to a value belonging to any one of the following ranges: 5 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, and 175 μm or more and 200 μm or less. The thickness of the chip 2 is preferably 100 μm or less.

[0017] The first to fourth side surfaces 5A to 5D may have lengths of 0.5 mm or more and 20 mm or less in plan view. The lengths of the first to fourth side surfaces 5A to 5D may be set to a value belonging to any one of the ranges of 0.5 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The lengths of the first to fourth side surfaces 5A to 5D are preferably 5 mm or more.

[0018] The semiconductor device 1 includes an n-type first semiconductor region 6 formed in a region (surface layer) on the first main surface 3 side of the chip 2. The first semiconductor region 6 is formed in a layer extending along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer). The first semiconductor region 6 may have a thickness of 1 μm or more and 50 μm or less. The thickness of the first semiconductor region 6 is preferably 3 μm or more and 30 μm or less. The thickness of the first semiconductor region 6 is particularly preferably 5 μm or more and 25 μm or less.

[0019] The semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side of the chip 2. The second semiconductor region 7 is formed in a layer extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6 and is electrically connected to the first semiconductor region 6. In this embodiment, the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC semiconductor substrate). In other words, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer.

[0020] The second semiconductor region 7 may have a thickness of 1 μm or more and 200 μm or less. The thickness of the second semiconductor region 7 may be 150 μm or less, 100 μm or less, 50 μm or less, or 40 μm or less. The thickness of the second semiconductor region 7 may be 5 μm or more. The thickness of the second semiconductor region 7 is preferably 10 μm or more. In this embodiment, the second semiconductor region 7 has a thickness greater than that of the first semiconductor region 6.

[0021] The semiconductor device 1 includes an active surface 8, an outer surface 9, and first to fourth connecting surfaces 10A-10D formed on a first main surface 3. The active surface 8, the outer surface 9, and the first to fourth connecting surfaces 10A-10D define an active plateau 11 on the first main surface 3. The active surface 8 may be referred to as a "first surface portion," the outer surface 9 may be referred to as a "second surface portion," and the first to fourth connecting surfaces 10A-10D may be referred to as a "connecting surface portion." The active surface 8, the outer surface 9, and the first to fourth connecting surfaces 10A-10D (i.e., the active plateau 11) may be considered to be components of the chip 2 (first main surface 3).

[0022] The active surface 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 8 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 8 is formed by the c-plane (Si-plane). In this embodiment, the active surface 8 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0023] The outer peripheral surface 9 is located outside the active surface 8 and is recessed from the active surface 8 in the thickness direction of the chip 2 (toward the second main surface 4). Specifically, the outer peripheral surface 9 is recessed to a depth less than the thickness of the first semiconductor region 6 so as to expose the first semiconductor region 6. The outer peripheral surface 9 extends in a band shape along the active surface 8 in a plan view and is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8.

[0024] The outer peripheral surface 9 has a flat surface extending in the first direction X and the second direction Y, and is formed substantially parallel to the active surface 8. In this embodiment, the outer peripheral surface 9 is formed by the c-plane (Si-plane). The outer peripheral surface 9 is continuous with the first to fourth side surfaces 5A to 5D. The outer peripheral surface 9 has a circumferential depth DO. The circumferential depth DO may be 0.1 μm or more and 5 μm or less. The circumferential depth DO is preferably 2.5 μm or less.

[0025] The first to fourth connection surfaces 10A to 10D extend in the normal direction Z and connect the active surface 8 and the outer peripheral surface 9. The first connection surface 10A is located on the first side surface 5A side, the second connection surface 10B is located on the second side surface 5B side, the third connection surface 10C is located on the third side surface 5C side, and the fourth connection surface 10D is located on the fourth side surface 5D side. The first connection surface 10A and the second connection surface 10B extend in the first direction X and face the second direction Y. The third connection surface 10C and the fourth connection surface 10D extend in the second direction Y and face the first direction X.

[0026] The first to fourth connection surfaces 10A to 10D may extend substantially perpendicularly between the active surface 8 and the outer peripheral surface 9 so as to define a quadrangular pillar-shaped active plateau 11. The first to fourth connection surfaces 10A to 10D may be inclined obliquely downward from the active surface 8 toward the outer peripheral surface 9 so as to define a quadrangular pyramid-shaped active plateau 11. In this manner, the semiconductor device 1 includes an active plateau 11 defined in a protruding shape in the first semiconductor region 6 on the first main surface 3. The active plateau 11 is formed only in the first semiconductor region 6, and is not formed in the second semiconductor region 7.

[0027] 4, semiconductor device 1 includes resistor region 12, active region 13, peripheral region 14, dummy region 15, termination region 16, and outer periphery region 17. Resistor region 12 is provided in active surface 8. Specifically, resistor region 12 is provided in an inner portion of active surface 8 at a distance from the peripheral edge (first to fourth connecting surfaces 10A to 10D) of active surface 8. In this embodiment, resistor region 12 is provided in a region along the center of first connecting surface 10A in plan view. Resistor region 12 is provided in a quadrangle shape having four sides parallel to first to fourth side surfaces 5A to 5D in plan view.

[0028] The active region 13 is a region that generates a drain current IDS by controlling the channel. The active region 13 is provided around the resistance region 12 in the active surface 8. Specifically, the active region 13 is provided in the inner part of the active surface 8 in a region outside the resistance region 12 and spaced apart from the periphery of the active surface 8. The active region 13 includes a first active region 13A, a second active region 13B, and a third active region 13C.

[0029] The first active region 13A is provided on the second connection surface 10B side (the inner side of the active surface 8) of the resistor region 12, and faces the resistor region 12 in the second direction Y. The first active region 13A is provided in a quadrangle shape having four sides parallel to the periphery of the active surface 8 in a plan view. The first active region 13A is provided to be wider in the first direction X than the resistor region 12.

[0030] The second active region 13B is provided in a region between the resistance region 12 and the third connecting surface 10C, and faces the resistance region 12 in the first direction X. The third active region 13C is provided in a region between the resistance region 12 and the fourth connecting surface 10D, and faces the second active region 13B in the first direction X, with the resistance region 12 sandwiched therebetween.

[0031] The peripheral regions 14 are provided on the active surface 8 so as to sandwich the active region 13 from both sides in the first direction X. The peripheral regions 14 include a first peripheral region 14A and a second peripheral region 14B. The first peripheral region 14A is provided in the region between the active region 13 and the third connecting surface 10C and extends in a strip-like shape in the second direction Y so as to face the first active region 13A and the second active region 13B in the first direction X. The second peripheral region 14B is provided in the region between the active region 13 and the fourth connecting surface 10D and extends in a strip-like shape in the second direction Y so as to face the first active region 13A and the third active region 13C in the first direction X.

[0032] The dummy regions 15 are provided on the active surface 8 so as to sandwich the active region 13 from both sides in the second direction Y. The dummy regions 15 include a first dummy region 15A, a second dummy region 15B, and a third dummy region 15C. The first dummy region 15A is provided in a region between the resistance region 12 and the third connecting surface 10C. The first dummy region 15A extends in a strip shape in the first direction X so as to face the resistance region 12 in the first direction X and to face the second active region 13B and the first peripheral region 14A in the second direction Y.

[0033] The second dummy region 15B is provided in a region between the resistance region 12 and the fourth connecting surface 10D. The second dummy region 15B extends in a strip shape in the first direction X so as to face the resistance region 12 in the first direction X and face the third active region 13C and the second peripheral region 14B in the second direction Y. The third dummy region 15C is provided in a region between the first active region 13A and the second connecting surface 10B. The third dummy region 15C extends in a strip shape in the first direction X so as to face the first active region 13A, the first peripheral region 14A, and the second peripheral region 14B in the second direction Y.

[0034] The plane area of ​​the first dummy region 15A is preferably smaller than the plane area of ​​the second active region 13B. In other words, the opposing area of ​​the first dummy region 15A to the resistor region 12 is preferably smaller than the opposing area of ​​the second active region 13B to the resistor region 12. The plane area of ​​the second dummy region 15B is preferably smaller than the plane area of ​​the third active region 13C. In other words, the opposing area of ​​the second dummy region 15B to the resistor region 12 is preferably smaller than the opposing area of ​​the third active region 13C to the resistor region 12.

[0035] The termination region 16 is provided on the active surface 8 so as to sandwich the dummy region 15 from both sides in the second direction Y. The termination region 16 includes a first termination region 16A and a second termination region 16B. The first termination region 16A is provided in the region between the resistor region 12 and the first connection surface 10A.

[0036] The first termination region 16A extends in a strip shape in the first direction X so as to face the resistor region 12, the first dummy region 15A, and the second dummy region 15B in the second direction Y. The second termination region 16B is provided in a region between the third dummy region 15C and the second connecting surface 10B. The second termination region 16B extends in a strip shape in the first direction X so as to face the third dummy region 15C in the second direction Y.

[0037] The outer peripheral region 17 is provided on the outer peripheral surface 9. In this embodiment, the outer peripheral region 17 is provided in a ring shape (specifically, a quadrangular ring shape) surrounding the active surface 8 (active plateau 11) in a plan view. In other words, the outer peripheral region 17 collectively surrounds the resistance region 12, the active region 13, the peripheral region 14, the dummy region 15, and the termination region 16.

[0038] The semiconductor device 1 includes a main surface insulating film 18 that covers the first main surface 3. The main surface insulating film 18 selectively covers the active surface 8, the outer peripheral surface 9, and the first to fourth connecting surfaces 10A to 10D. The main surface insulating film 18 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0039] In this embodiment, the main surface insulating film 18 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 18 includes a silicon oxide film made of an oxide of the chip 2. In this embodiment, the main surface insulating film 18 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the wall portion of the main surface insulating film 18 may be formed at a distance inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9.

[0040] Fig. 5 is an enlarged plan view showing the vicinity of the resistor region 12. Fig. 6 is an enlarged plan view showing the layout of the vicinity of the resistor region 12. Fig. 7 is a cross-sectional view taken along line VII-VII shown in Fig. 6. Fig. 8 is an enlarged plan view showing the layout of the resistor region 12 and the active region 13. Fig. 9 is an enlarged plan view showing the layout of the active region 13 and the peripheral region 14.

[0041] Fig. 10 is a cross-sectional view taken along line XX in Fig. 8. Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 8. Fig. 12 is a cross-sectional view taken along line XII-XII in Fig. 8. Fig. 13 is a cross-sectional view taken along line XIII-XIII in Fig. 8. Fig. 14 is a cross-sectional view taken along line XIV-XIV in Fig. 9. Fig. 15 is a cross-sectional view taken along line XV-XV in Fig. 9. Fig. 16 is a cross-sectional view taken along line XVI-XVI in Fig. 9. Fig. 17 is a cross-sectional view taken along line XVII-XVII in Fig. 9.

[0042] 5 to 17 , semiconductor device 1 includes p-type (second conductivity type) body region 19 formed in a surface layer portion of first main surface 3 (active surface 8). Body region 19 is formed at an interval from the bottom of first semiconductor region 6 toward active surface 8. Body region 19 is formed in a layer shape extending along active surface 8. Body region 19 may be formed over the entire active surface 8 and exposed from first to fourth connecting surfaces 10A to 10D.

[0043] The semiconductor device 1 includes a trench resistor structure 20 formed in the first main surface 3 (active surface 8) in the resistor region 12. In this embodiment, a single trench resistor structure 20 is formed in the first main surface 3 (active surface 8). The trench resistor structure 20 is incorporated into the chip 2 as a gate resistor R electrically connected to the gate of the MISFET. A gate potential VG is applied to the trench resistor structure 20, but the trench resistor structure 20 does not contribute to channel control.

[0044] The trench resistance structure 20 is arranged in a region on the first connection surface 10A side of the active region 13, and faces the active region 13 in the second direction Y. The trench resistance structure 20 is arranged at a distance from the peripheral region 14 in the first direction X so as not to face the peripheral region 14 in the second direction Y. In this embodiment, the trench resistance structure 20 is arranged between the center of the first connection surface 10A and the active region 13.

[0045] The trench resistance structure 20 penetrates the body region 19 to reach the first semiconductor region 6, and is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8. In this embodiment, the trench resistance structure 20 is formed in a quadrangle shape having four sides parallel to the periphery of the active surface 8 in a plan view. The trench resistance structure 20 has first to fourth sidewalls 21A to 21D and a bottom wall 22.

[0046] The first side wall 21A is located on the first connecting surface 10A side, the second side wall 21B is located on the second connecting surface 10B side, the third side wall 21C is located on the third connecting surface 10C side, and the fourth side wall 21D is located on the fourth connecting surface 10D side. The first connecting surface 10A and the second connecting surface 10B extend in the first direction X and face the second direction Y. The third connecting surface 10C and the fourth connecting surface 10D extend in the second direction Y and face the first direction X. The bottom wall 22 connects the first to fourth side walls 21A to 21D and extends approximately parallel to the active surface 8.

[0047] The trench resistor structure 20 preferably has a planar area of ​​1% to 25% of the planar area of ​​the first main surface 3. The planar area of ​​the trench resistor structure 20 is preferably 5% to 20% of the planar area of ​​the first main surface 3. The trench resistor structure 20 has a resistor depth DR in the normal direction Z. The resistor depth DR is preferably equal to or less than the aforementioned peripheral depth DO. In this embodiment, the resistor depth DR is approximately equal to the peripheral depth DO. The resistor depth DR may be equal to or greater than 0.1 μm and equal to 5 μm. The resistor depth DR is preferably equal to or less than 2.5 μm.

[0048] The trench resistor structure 20 includes a resistor trench 23, a resistor insulating film 24, a buried resistor 25, and a buried insulator 26. The resistor trench 23 is formed in the active surface 8 and defines the wall surfaces (first to fourth side walls 21A to 21D and a bottom wall 22) of the trench resistor structure 20.

[0049] The resistive insulating film 24 covers the wall surface of the resistive trench 23 and is connected to the main surface insulating film 18 on the active surface 8. The resistive insulating film 24 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the resistive insulating film 24 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the resistive insulating film 24 include a silicon oxide film made of an oxide of the chip 2.

[0050] The buried resistor 25 is disposed in the resistor trench 23 with the resistor insulating film 24 sandwiched therebetween. The buried resistor 25 includes at least one of a conductive polysilicon film and an alloy crystal film. The alloy crystal film includes alloy crystals composed of a metal element and a non-metal element. The alloy crystal film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film. In this embodiment, the buried resistor 25 includes conductive polysilicon.

[0051] The buried resistor 25 is disposed inside the resistor trench 23 at a distance from the periphery (first to fourth side walls 21A to 21D) of the resistor trench 23. That is, the buried resistor 25 is formed as a resistive film extending in a film-like shape inside the resistor trench 23. The buried resistor 25 defines an insulating region 27 between itself and the periphery of the resistor trench 23, exposing a part of the resistive insulating film 24. In this embodiment, the buried resistor 25 is formed at a distance inward from the entire periphery of the resistor trench 23. That is, the insulating region 27 is defined in a ring shape extending along the first to fourth side walls 21A to 21D in a plan view.

[0052] The buried resistor 25 may be unevenly located toward the periphery of the trench resistor structure 20 relative to the center of the resistive trench 23. That is, the buried resistor 25 may be shifted from the center of the trench resistor structure 20 toward at least one of the first to fourth side walls 21A to 21D. In this embodiment, the buried resistor 25 is unevenly located toward the first side wall 21A relative to the second side wall 21B. That is, the distance between the first side wall 21A and the buried resistor 25 is smaller than the distance between the second side wall 21B and the buried resistor 25.

[0053] The buried resistor 25 has a resistor thickness TR that is smaller than the resistor depth DR of the resistor trench 23. The resistor trench 23 has a resistor end surface 25a that is formed at a distance from the height position of the active surface 8 toward the bottom wall 22 of the resistor trench 23. The resistor end surface 25a extends approximately parallel to the bottom wall 22. In this embodiment, the buried resistor 25 is formed in a tapered shape in cross section, with its width narrowing toward the resistor end surface 25a.

[0054] The resistor end surface 25a may be located closer to the bottom wall 22 of the resistor trench 23 than the intermediate portion of the resistor trench 23 in the depth direction. Of course, the resistor end surface 25a may be located closer to the active surface 8 than the intermediate portion of the resistor trench 23 in the depth direction. The resistor thickness TR is preferably ¾ or less of the resistor depth DR. The resistor thickness TR may be ½ or less of the resistor depth DR. The resistor thickness TR may be ¼ or less of the resistor depth DR. Of course, the resistor thickness TR may be greater than ½ of the resistor depth DR. The resistor thickness TR may be 0.05 μm or more and 2.5 μm or less.

[0055] The resistor thickness TR may be set to a value belonging to any one of the ranges of 0.05 μm to 0.1 μm, 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, and 2 μm to 2.5 μm. When the buried resistor 25 is made of an alloy crystal film, the resistor thickness TR may be 0.1 nm to 100 nm.

[0056] The planar shape and area of ​​the buried resistor 25 are arbitrary and are adjusted appropriately depending on the resistance value to be achieved. In this embodiment, the buried resistor 25 is formed in a quadrangular shape having four sides parallel to the first to fourth side walls 21A to 21D in a planar view. In other words, the insulating region 27 is defined in a quadrangular ring shape extending along the first to fourth side walls 21A to 21D in a planar view. Of course, the buried resistor 25 may be formed in a polygonal or circular shape in a planar view.

[0057] The buried resistor 25 preferably has a planar area of ​​0.05 to 0.5 times the planar area of ​​the resistive trench 23. The planar area of ​​the buried resistor 25 is particularly preferably 0.1 to 0.25 times the planar area of ​​the resistive trench 23. The planar area of ​​the insulating region 27 is preferably larger than the planar area of ​​the buried resistor 25. Of course, the planar area of ​​the insulating region 27 may be set to be equal to or smaller than the planar area of ​​the buried resistor 25.

[0058] The buried insulator 26 covers the buried resistor 25 in the resistive trench 23. The buried insulator 26 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the buried insulator 26 includes a silicon oxide film. The buried insulator 26 covers the entire buried resistor 25 and the entire insulating region 27 in the resistive trench 23, and is connected to the resistive insulating film 24 at the periphery (first to fourth side walls 21A to 21D) of the resistive trench 23.

[0059] In this embodiment, the buried insulator 26 has an insulating thickness TI that is equal to or less than the resistive depth DR of the resistive trench 23. The insulating thickness TI is the thickness of the buried insulator 26 relative to the resistive insulating film 24. In this embodiment, the insulating thickness TI is less than the resistive depth DR. The buried insulator 26 has an insulating end surface 26a that is formed at a distance from the height position of the active surface 8 toward the bottom wall 22 of the resistive trench 23. The insulating end surface 26a extends approximately parallel to the resistive insulating film 24 and the buried resistor 25.

[0060] The insulation thickness TI may be ¾ or less of the resistor depth DR. The insulation thickness TI may be ½ or less of the resistor depth DR. The insulation thickness TI may be ¼ or less of the resistor depth DR. It is preferable that the insulation thickness TI is equal to or greater than the resistor thickness TR of the embedded resistor 25. Of course, the insulation thickness TI may be equal to or less than the resistor thickness TR. The insulation thickness TI may be 0.1 μm or more and 2.5 μm or less. It is preferable that the insulation thickness TI is 0.5 μm or more and 1.5 μm or less.

[0061] The semiconductor device 1 includes a p-type first well region 28 formed in a region of the resistor region 12 along the trench resistor structure 20. In this embodiment, the first well region 28 has a higher p-type impurity concentration than the body region 19. Of course, the p-type impurity concentration of the first well region 28 may be lower than that of the body region 19.

[0062] The first well region 28 covers the wall surfaces (first to fourth side walls 21A to 21D and bottom wall 22) of the trench resistor structure 20 and is electrically connected to the body region 19 in the surface layer portion of the active surface 8. The first well region 28 faces the buried resistor 25 and the buried insulator 26 (insulating region 27) with the resistive insulating film 24 interposed therebetween. The first well region 28 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8, and faces the second semiconductor region 7 with a part of the first semiconductor region 6 interposed therebetween. The first well region 28 forms a pn junction with the first semiconductor region 6.

[0063] The semiconductor device 1 includes an n-type source region 29 formed in a surface layer portion of the first main surface 3 (active surface 8) in the active region 13. Specifically, the source region 29 is formed in the surface layer portion of the body region 19 at a distance from the bottom of the body region 19 toward the active surface 8. The source region 29 is not formed in the resistor region 12, the peripheral region 14, the dummy region 15, or the termination region 16. In other words, the source region 29 is not formed in a region along the trench resistor structure 20.

[0064] Of course, the source region 29 may be formed in the resistance region 12, the peripheral region 14, the dummy region 15, and the termination region 16 to the extent that it does not affect channel control. The source region 29 has a higher n-type impurity concentration than the first semiconductor region 6. The source region 29, together with the first semiconductor region 6, forms the channel of the MISFET in the body region 19.

[0065] The semiconductor device 1 includes a plurality of trench gate structures 30 formed in the first main surface 3 (active surface 8) in the active region 13 (first to third active regions 13A to 13C). A gate potential VG is applied to the plurality of trench gate structures 30. The plurality of trench gate structures 30 control inversion and non-inversion of the channel in the body region 19.

[0066] In this embodiment, the plurality of trench gate structures 30 are arranged inward of the active surface 8 at intervals from the periphery of the active surface 8. Specifically, the plurality of trench gate structures 30 are arranged at intervals from the first to fourth connecting surfaces 10A to 10D in the first direction X and the second direction Y, and define an active region 13 in the inner portion of the active surface 8 and a peripheral region 14 in the periphery of the active surface 8. The plurality of trench gate structures 30 penetrate the body region 19 and the source region 29 to reach the first semiconductor region 6, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0067] The multiple trench gate structures 30 on the first active region 13A side are each formed in a strip shape extending in the first direction X in a region between the second connection surface 10B and the trench resistance structure 20, and are arranged at intervals in the second direction Y. The multiple trench gate structures 30 on the first active region 13A side are formed at intervals from the trench resistance structure 20 in the second direction Y, and face the trench resistance structure 20 in the second direction Y. The multiple trench gate structures 30 are formed wider in the first active region 13A in the first direction X than the trench resistance structure 20.

[0068] The plurality of trench gate structures 30 on the second active region 13B side are each formed in a strip shape extending in the first direction X in a region between the third connection surface 10C and the trench resistance structure 20, and are arranged at intervals in the second direction Y. The plurality of trench gate structures 30 on the second active region 13B side are formed at intervals from the trench resistance structure 20 in the first direction X, and face the trench resistance structure 20 in the first direction X. The plurality of trench gate structures 30 on the second active region 13B side are formed wider in the first direction X than the trench resistance structure 20. Of course, the plurality of trench gate structures 30 on the second active region 13B side may be formed narrower than the trench resistance structure 20.

[0069] The trench resistance structures 20 on the third active region 13C side are each formed in a strip shape extending in the first direction X in a region between the fourth connection surface 10D and the trench resistance structures 20, and are arranged at intervals in the second direction Y. The plurality of trench gate structures 30 on the third active region 13C side are formed at intervals from the trench resistance structure 20 in the first direction X, and face the trench resistance structure 20 in the first direction X.

[0070] The plurality of trench gate structures 30 on the third active region 13C side may face the plurality of trench gate structures 30 on the second active region 13B side in a one-to-one correspondence, with the trench resistance structure 20 sandwiched therebetween. The plurality of trench gate structures 30 on the third active region 13C side are formed wider in the first direction X than the trench resistance structure 20. Of course, the plurality of trench gate structures 30 on the third active region 13C side may also be formed narrower than the trench resistance structure 20.

[0071] One trench gate structure 30 will be described below. The trench gate structure 30 has a first width W1 in the second direction Y and a first depth D1 in the normal direction Z. The first width W1 is less than the width of the trench resistor structure 20. The first width W1 may be 1 / 1000 or more and 1 / 10 or less of the width of the trench resistor structure 20. Preferably, the first width W1 is 1 / 100 or more of the width of the trench resistor structure 20.

[0072] The first width W1 may be 0.1 μm or more and 3 μm or less. The first width W1 is preferably 0.5 μm or more and 2 μm or less. The first depth D1 is less than the resistor depth DR (periphery depth DO) described above. The first depth D1 may be 1 / 3 or more and 2 / 3 or less of the resistor depth DR. The first depth D1 may be 0.1 μm or more and 3 μm or less. The first depth D1 is preferably 0.5 μm or more and 1.5 μm or less.

[0073] In the second and third active regions 13B and 13C, the trench gate structures 30 are formed at a first interval I1 from the trench resistor structure 20 in the first direction X. The first interval I1 is preferably less than the distance between two adjacent trench gate structures 30 in the second direction Y. The first interval I1 may be equal to or greater than the first width W1, or may be less than the first width W1. The first interval I1 is preferably 0.5 to 2 times the first width W1. The first interval I1 may be 0.1 μm to 2.5 μm. The first interval I1 is preferably 0.5 μm to 1.5 μm.

[0074] The trench gate structure 30 includes a gate trench 31, a gate insulating film 32, and a buried gate electrode 33. The gate trench 31 is formed in the active surface 8 and defines the wall surface of the trench gate structure 30. The gate insulating film 32 covers the wall surface of the gate trench 31 and is connected to the main surface insulating film 18 at the active surface 8. The gate insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 32 include a silicon oxide film made of an oxide of the chip 2.

[0075] The buried gate electrode 33 is disposed in the gate trench 31 with the gate insulating film 32 interposed therebetween and faces the channel with the gate insulating film 32 interposed therebetween. The buried gate electrode 33 may include conductive polysilicon. In this embodiment, the buried gate electrode 33 has an end face located on the active surface 8 side with respect to the height position of the resistor end face 25a of the buried resistor 25. The end face of the buried gate electrode 33 may be located on the active surface 8 side with respect to the height position of the insulating end face 26a of the buried insulator 26.

[0076] The semiconductor device 1 includes a plurality of first trench source structures 35 formed in the first main surface 3 (active surface 8) in the active region 13 (first to third active regions 13A to 13C). A source potential VS is applied to the plurality of first trench source structures 35. The source potential VS may be a reference potential (e.g., ground potential) that serves as an operational reference. The plurality of first trench source structures 35 penetrate the body region 19 and the source region 29 to reach the first semiconductor region 6, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0077] The multiple first trench source structures 35 on the first active region 13A side are each arranged in a region between two trench gate structures 30 adjacent in the second direction Y in a region between the second connection surface 10B and the trench resistance structure 20. The multiple first trench source structures 35 on the first active region 13A side are arranged alternately with the multiple trench gate structures 30 in the second direction Y in a plan view, and are each formed in a strip shape extending in the first direction X. In this embodiment, the multiple first trench source structures 35 on the first active region 13A side include a first trench source structure 35 arranged in a region between the trench resistance structure 20 and the trench gate structure 30.

[0078] The plurality of first trench source structures 35 on the first active region 13A side are drawn to at least one of the first peripheral region 14A and the second peripheral region 14B so as to be exposed from at least one of the third connection surface 10C and the fourth connection surface 10D. In this embodiment, the plurality of first trench source structures 35 on the first active region 13A side are exposed from both the third connection surface 10C and the fourth connection surface 10D. The plurality of first trench source structures 35 on the first active region 13A side face the trench gate structure 30 in the second direction Y, but do not face the trench gate structure 30 in the second direction Y in the peripheral region 14.

[0079] The multiple first trench source structures 35 on the second active region 13B side are each arranged in a region between two trench gate structures 30 adjacent to each other in the second direction Y, in a region between the third connection surface 10C and the trench resistance structure 20. The multiple first trench source structures 35 on the second active region 13B side are arranged alternately with the multiple trench gate structures 30 in the second direction Y in a plan view, and are each formed in a strip shape extending in the first direction X.

[0080] The plurality of first trench source structures 35 on the second active region 13B side are formed at intervals from the trench resistance structure 20 in the first direction X and face the trench resistance structure 20 in the first direction X. The plurality of first trench source structures 35 on the second active region 13B side are formed wider in the first direction X than the trench resistance structure 20. Of course, the plurality of first trench source structures 35 on the second active region 13B side may be formed narrower in the first direction X than the trench resistance structure 20.

[0081] The plurality of first trench source structures 35 on the second active region 13B side are drawn to the first peripheral region 14A and exposed from the third connection surface 10C. The plurality of first trench source structures 35 on the second active region 13B side face the trench gate structure 30 in the second direction Y, but do not face the trench gate structure 30 in the second direction Y in the first peripheral region 14A.

[0082] The plurality of first trench source structures 35 on the third active region 13C side are each arranged in a region between two trench gate structures 30 adjacent to each other in the second direction Y, in a region between the fourth connection surface 10D and the trench resistance structure 20. The plurality of first trench source structures 35 on the third active region 13C side are arranged alternately with the plurality of trench gate structures 30 in the second direction Y in a plan view, and are each formed in a strip shape extending in the first direction X.

[0083] The plurality of first trench source structures 35 on the third active region 13C side are formed at intervals from the trench resistance structure 20 in the first direction X, and face the trench resistance structure 20 in the first direction X. The plurality of first trench source structures 35 on the third active region 13C side may face the plurality of first trench source structures 35 on the second active region 13B side in a one-to-one correspondence, with the trench resistance structure 20 sandwiched therebetween.

[0084] The plurality of first trench source structures 35 on the third active region 13C side are formed wider in the first direction X than the trench resistance structure 20. Of course, the plurality of first trench source structures 35 on the third active region 13C side may be formed narrower in the first direction X than the trench resistance structure 20.

[0085] The plurality of first trench source structures 35 on the third active region 13C side are drawn to the second peripheral region 14B and exposed from the fourth connection surface 10D. The plurality of first trench source structures 35 on the third active region 13C side face the trench gate structure 30 in the second direction Y, but do not face the trench gate structure 30 in the second direction Y in the second peripheral region 14B.

[0086] One first trench source structure 35 will be described below. The first trench source structure 35 has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z. The second width W2 is less than the width of the trench resistor structure 20. The second width W2 may be 1 / 1000 to 1 / 10 of the width of the trench resistor structure 20. Preferably, the second width W2 is 1 / 100 or more of the width of the trench resistor structure 20. Preferably, the second width W2 is approximately equal to the first width W1 described above. The second width W2 may be 0.1 μm to 3 μm. Preferably, the second width W2 is 0.5 μm to 2 μm.

[0087] The second depth D2 is equal to or greater than the first depth D1. In this embodiment, the second depth D2 is greater than the first depth D1. The second depth D2 is preferably 1.5 to 3 times the first depth D1. It is particularly preferable that the second depth D2 be approximately equal to the resistor depth DR (periphery depth DO) described above. The second depth D2 may be 0.1 μm to 5 μm. It is particularly preferable that the second depth D2 be 2.5 μm or less.

[0088] The first trench source structure 35 is disposed in the second direction Y at a second distance I2 from the trench resistor structure 20 and the trench gate structure 30. The second distance I2 is preferably 0.5 to 2 times the second width W2. It is particularly preferable that the second distance I2 be less than the second width W2. The second distance I2 may be 0.1 μm to 2.5 μm. The second distance I2 is preferably 0.5 μm to 1.5 μm.

[0089] In the second and third active regions 13B and 13C, the first trench source structures 35 are arranged at a third distance I3 from the trench resistor structure 20 in the first direction X. The third distance I3 is preferably less than the distance between two adjacent first trench source structures 35 (trench gate structures 30) in the second direction Y.

[0090] The third interval I3 may be equal to or greater than the second width W2, or may be less than the second width W2. The third interval I3 is preferably 0.5 to 2 times the second width W2. The third interval I3 is preferably approximately equal to the first interval I1. The third interval I3 may be 0.1 μm to 2.5 μm. The third interval I3 is preferably 0.5 μm to 1.5 μm.

[0091] The first trench source structure 35 includes a first source trench 36, a first source insulating film 37, and a first source buried electrode 38. The first source trench 36 is formed in the active surface 8 and defines the wall surface of the first trench source structure 35. The sidewall of the first source trench 36 is exposed from either or both of the third connection surface 10C and the fourth connection surface 10D. The bottom wall of the first source trench 36 communicates with the outer peripheral surface 9.

[0092] The first source insulating film 37 covers the wall surface of the first source trench 36 and is connected to the main surface insulating film 18 at the active surface 8. The first source insulating film 37 is connected to the main surface insulating film 18 at the communicating portion of the third connection surface 10C (the communicating portion of the fourth connection surface 10D) and the communicating portion of the outer peripheral surface 9. The first source insulating film 37 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first source insulating film 37 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first source insulating film 37 include a silicon oxide film made of an oxide of the chip 2.

[0093] The first source buried electrode 38 is disposed in the first source trench 36 with the first source insulating film 37 sandwiched therebetween. The first source buried electrode 38 may include conductive polysilicon. In this embodiment, the first source buried electrode 38 has an end face located on the active surface 8 side relative to the height position of the resistor end face 25a of the buried resistor 25. The end face of the first source buried electrode 38 may be located on the active surface 8 side relative to the height position of the insulating end face 26a of the buried insulator 26.

[0094] The semiconductor device 1 includes a plurality of second trench source structures 40 formed in the first main surface 3 (active surface 8) in the peripheral region 14 (first and second peripheral regions 14A and 14B). A source potential VS is applied to the plurality of second trench source structures 40. The plurality of second trench source structures 40 penetrate the body region 19 to reach the first semiconductor region 6, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0095] The second trench source structures 40 on the first peripheral region 14A side are arranged in a region between two first trench source structures 35 adjacent in the second direction Y in a region between the third connection surface 10C and the trench gate structures 30, and face the trench gate structures 30 in a one-to-one correspondence in the first direction X. The second trench source structures 40 on the first peripheral region 14A side are each formed in a strip shape extending in the first direction X in a plan view. The second trench source structures 40 on the first peripheral region 14A side are exposed from the third connection surface 10C.

[0096] The second trench source structures 40 on the second peripheral region 14B side are arranged in a region between two first trench source structures 35 adjacent in the second direction Y in a region between the fourth connection surface 10D and the trench gate structures 30, and face the trench gate structures 30 in a one-to-one correspondence in the first direction X. The second trench source structures 40 on the second peripheral region 14B side are each formed in a strip shape extending in the first direction X in a plan view. The second trench source structures 40 on the second peripheral region 14B side are exposed from the fourth connection surface 10D.

[0097] One second trench source structure 40 will be described below. The second trench source structure 40 has a third width W3 in the second direction Y and a third depth D3 in the normal direction Z. The third width W3 is preferably approximately equal to the second width W2 (first width W1) described above. The third width W3 may be 0.1 μm or more and 3 μm or less. The third width W3 is preferably 0.5 μm or more and 2 μm or less.

[0098] The third depth D3 is equal to or greater than the first depth D1. In this embodiment, the third depth D3 is greater than the first depth D1. The third depth D3 is preferably 1.5 to 3 times the first depth D1. It is particularly preferable that the third depth D3 be approximately equal to the second depth D2 (resistance depth DR) described above. The third depth D3 may be 0.1 μm to 5 μm. It is particularly preferable that the second depth D2 be 2.5 μm or less.

[0099] The second trench source structure 40 is disposed in the second direction Y at a fourth distance I4 from the first trench source structure 35. The fourth distance I4 is preferably 0.5 to 2 times the third width W3 (second width W2). It is particularly preferable that the fourth distance I4 be less than the third width W3 (second width W2). The fourth distance I4 is preferably approximately equal to the second distance I2. The fourth distance I4 may be 0.1 μm to 2.5 μm. The fourth distance I4 is preferably 0.5 μm to 1.5 μm.

[0100] The second trench source structure 40 is disposed in the first direction X at a fifth distance I5 from the trench gate structure 30. The fifth distance I5 is preferably 0.5 to 2 times the third width W3 (second width W2). The fifth distance I5 is preferably 0.5 to 2 times the fourth distance I4. The fifth distance I5 is particularly preferably 1.5 times or less the fourth distance I4. The fifth distance I5 is preferably approximately equal to the first distance I1 (third distance I3) described above. The fifth distance I5 may be approximately equal to the fourth distance I4. The fifth distance I5 may be 0.1 μm to 2.5 μm. The fifth distance I5 is preferably 0.5 μm to 1.5 μm.

[0101] The second trench source structure 40 includes a second source trench 41, a second source insulating film 42, and a second buried source electrode 43. The second source trench 41 is formed in the active surface 8 and defines the wall surface of the second trench source structure 40. A sidewall of the second source trench 41 communicates with the third connection surface 10C (fourth connection surface 10D). A bottom wall of the second source trench 41 communicates with the outer peripheral surface 9.

[0102] The second source insulating film 42 covers the wall surface of the second source trench 41 and is connected to the main surface insulating film 18 at the active surface 8. The second source insulating film 42 is connected to the main surface insulating film 18 at the communicating portion of the third connection surface 10C (the communicating portion of the fourth connection surface 10D) and the communicating portion of the outer peripheral surface 9. The second source insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second source insulating film 42 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second source insulating film 42 include a silicon oxide film made of an oxide of the chip 2.

[0103] The second source buried electrode 43 is disposed in the second source trench 41 with the second source insulating film 42 sandwiched therebetween. The second source buried electrode 43 may include conductive polysilicon. In this embodiment, the second source buried electrode 43 has an end face located on the active surface 8 side relative to the height position of the resistor end face 25a of the buried resistor 25. The end face of the second source buried electrode 43 may be located on the active surface 8 side relative to the height position of the insulating end face 26a of the buried insulator 26.

[0104] The semiconductor device 1 includes a plurality of p-type second well regions 45 formed in the active region 13 in regions along the plurality of trench gate structures 30. In this embodiment, the second well regions 45 have a higher p-type impurity concentration than the body region 19. Of course, the p-type impurity concentration of the second well regions 45 may be lower than that of the body region 19. It is preferable that the p-type impurity concentration of the second well regions 45 is approximately equal to the p-type impurity concentration of the first well region 28.

[0105] The plurality of second well regions 45 cover the wall surfaces of the corresponding trench gate structures 30 at intervals from the adjacent first trench source structures 35, and are electrically connected to the body region 19 in the surface layer portion of the active surface 8. The plurality of second well regions 45 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 with a part of the first semiconductor region 6 in between. The bottoms of the plurality of second well regions 45 are located on the active surface 8 side with respect to the depth position of the bottom of the first well region 28. The plurality of second well regions 45 form pn junctions with the first semiconductor region 6.

[0106] The semiconductor device 1 includes a plurality of p-type third well regions 46 formed in the active region 13 and the peripheral region 14 in regions along the plurality of first trench source structures 35. In this embodiment, the third well regions 46 have a higher p-type impurity concentration than the body region 19. Of course, the p-type impurity concentration of the third well regions 46 may be lower than that of the body region 19. It is preferable that the p-type impurity concentration of the third well regions 46 be approximately equal to the p-type impurity concentration of the first well region 28 (second well region 45).

[0107] The plurality of third well regions 46 cover the wall surfaces of the corresponding first trench source structures 35 at intervals from the adjacent trench gate structures 30, and are electrically connected to the body region 19 in the surface portion of the active surface 8. The plurality of third well regions 46 cover the wall surfaces of the corresponding first trench source structures 35 in the active region 13 and the peripheral region 14, and are exposed from the third connection surface 10C and the fourth connection surface 10D.

[0108] The plurality of third well regions 46 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the plurality of third well regions 46 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the plurality of second well regions 45. The bottoms of the plurality of third well regions 46 are formed at approximately the same depth as the bottom of the first well region 28. The plurality of third well regions 46 form pn junctions with the first semiconductor region 6.

[0109] The semiconductor device 1 includes a plurality of p-type fourth well regions 47 formed in the peripheral region 14 in regions along the plurality of second trench source structures 40. In this embodiment, the fourth well regions 47 have a higher p-type impurity concentration than the body region 19. Of course, the p-type impurity concentration of the fourth well regions 47 may be lower than that of the body region 19. It is preferable that the p-type impurity concentration of the fourth well regions 47 be approximately equal to the p-type impurity concentration of the first well region 28 (third well region 46).

[0110] The plurality of fourth well regions 47 cover the wall surfaces of the corresponding second trench source structures 40 at intervals from the adjacent trench gate structures 30 and first trench source structures 35, and are electrically connected to the body region 19 in the surface portion of the active surface 8. Of course, the fourth well regions 47 may be integrated with the second well region 45 in the region between the trench gate structures 30 and the second trench source structures 40. The plurality of fourth well regions 47 are exposed from the third connection surface 10C or the fourth connection surface 10D.

[0111] The plurality of fourth well regions 47 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The bottoms of the plurality of fourth well regions 47 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the plurality of second well regions 45. The bottoms of the plurality of fourth well regions 47 are formed at approximately the same depth as the bottom of the first well region 28 (third well region 46). The plurality of fourth well regions 47 form pn junctions with the first semiconductor region 6.

[0112] The semiconductor device 1 includes a plurality of p-type first contact regions 48 formed in the active region 13 in regions along the plurality of first trench source structures 35. The first contact regions 48 have a higher p-type impurity concentration than the body region 19. In this embodiment, the p-type impurity concentration of the first contact regions 48 is higher than that of the third well region 46.

[0113] The plurality of first contact regions 48 cover the wall surfaces of the corresponding first trench source structures 35 in the corresponding third well regions 46. The plurality of first contact regions 48 are formed in a one-to-many correspondence with each of the first trench source structures 35. The plurality of first contact regions 48 are formed at intervals along the corresponding first trench source structures 35.

[0114] The plurality of first contact regions 48 are extended from within the corresponding third well region 46 to the surface portion of the body region 19 along the wall surfaces of the corresponding first trench source structures 35 and are exposed from the active surface 8. The plurality of first contact regions 48 are formed in the active region 13 and are not formed in the peripheral region 14. In other words, the plurality of first contact regions 48 face the trench gate structure 30 in the second direction Y, but do not face the second trench source structure 40 in the second direction Y. The first contact regions 48 are not formed in the fourth well region 47.

[0115] In this embodiment, the multiple first contact regions 48 are each formed in a strip shape extending in the first direction X in a plan view. The length of the multiple first contact regions 48 in the first direction X is preferably equal to or greater than the second width W2 of the first trench source structure 35. The length of the multiple first contact regions 48 is preferably greater than the distance between two adjacent first contact regions 48 in the first direction X.

[0116] The plurality of first contact regions 48 along one first trench source structure 35 face the plurality of first contact regions 48 along another first trench source structure 35 in the second direction Y. That is, in this embodiment, the plurality of first contact regions 48 are arranged in a matrix form at intervals in the first direction X and the second direction Y as a whole in a plan view.

[0117] The first contact regions 48 along one first trench source structure 35 may be arranged offset in the first direction X so as to face the second direction Y in a region between the first contact regions 48 along another first trench source structure 35. In other words, the first contact regions 48 may be arranged in a staggered pattern as a whole with intervals in the first direction X and the second direction Y in a plan view.

[0118] 7 , 9 and 14 , the semiconductor device 1 includes a plurality of gate connection electrode films 49 covering end portions and intermediate portions of the plurality of trench gate structures 30 on the first main surface 3 (active surface 8) in the active region 13. Specifically, the plurality of gate connection electrode films 49 are disposed on the main surface insulating film 18. The plurality of gate connection electrode films 49 cover end portions and intermediate portions of the corresponding trench gate structures 30 at intervals from the plurality of first trench source structures 35 and the plurality of second trench source structures 40.

[0119] The multiple gate connection electrode films 49 are arranged alternately with the multiple first trench source structures 35 in the second direction Y in plan view. In this embodiment, the multiple gate connection electrode films 49 are each formed in a strip shape extending in the first direction X. The multiple gate connection electrode films 49 do not face the multiple second trench source structures 40 in the second direction Y in plan view. Below, one gate connection electrode film 49 will be described.

[0120] The gate connection electrode film 49 is connected to the corresponding gate buried electrode 33 in a portion covering the corresponding trench gate structure 30. In this embodiment, the gate connection electrode film 49 is formed integrally with the corresponding gate buried electrode 33. That is, the gate connection electrode film 49 is formed by a portion of the gate buried electrode 33 being extended in a film form onto the active surface 8 (main surface insulating film 18). Of course, the gate connection electrode film 49 may be formed separately from the gate buried electrode 33.

[0121] The gate connection electrode film 49 has an electrode surface 49a extending along the active surface 8. The electrode surface 49a is located higher than the resistor end surface 25a of the buried resistor 25. The electrode surface 49a is located higher than the insulating end surface 26a of the buried insulator 26. In this embodiment, the gate connection electrode film 49 is formed in a tapered shape in cross section, with its width narrowing toward the electrode surface 49a.

[0122] The electrode surface 49 a is preferably formed to be wider than the trench gate structure 30 in the second direction Y. The electrode surface 49 a preferably has a portion facing the trench gate structure 30 in the normal direction Z and a portion facing a region outside the trench gate structure 30 (i.e., the main surface insulating film 18) in the normal direction Z.

[0123] In this embodiment, the gate connection electrode film 49 includes conductive polysilicon. The gate connection electrode film 49 has an electrode thickness TE. The electrode thickness TE is preferably 0.5 times or more the first width W1 described above. The electrode thickness TE is preferably equal to or less than the resistor depth DR (second depth D2) described above. It is particularly preferable that the electrode thickness TE be less than the resistor depth DR (second depth D2).

[0124] The electrode thickness TE is preferably equal to or less than the first depth D1 described above. It is particularly preferable that the electrode thickness TE is less than the first depth D1. The electrode thickness TE may be approximately equal to the resistor thickness TR. The electrode thickness TE may be equal to or greater than the resistor thickness TR. The electrode thickness TE may be less than the resistor thickness TR. The electrode thickness TE may be 0.05 μm or more and 2.5 μm or less. The electrode thickness TE is preferably 0.5 μm or more and 1.5 μm or less. Of course, the electrode thickness TE may be greater than the first depth D1. Furthermore, the electrode thickness TE may be greater than the resistor depth DR (second depth D2).

[0125] 18 is an enlarged plan view showing the layout of the resistance region 12, the active region 13, and the dummy region 15. FIG. 19 is an enlarged plan view showing the layout of the active region 13, the peripheral region 14, and the dummy region 15. FIG. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 18. FIG. 21 is a cross-sectional view taken along line XXI-XXI shown in FIG. 18. FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 18.

[0126] 18 to 22, semiconductor device 1 includes a plurality of dummy trench structures 50 formed in first main surface 3 (active surface 8) in dummy regions 15 (first to third dummy regions 15A to 15C). A potential different from that of trench resistance structure 20 is applied to the plurality of dummy trench structures 50. A source potential VS is applied to the plurality of dummy trench structures 50. The plurality of dummy trench structures 50 penetrate body region 19 to reach first semiconductor region 6, and are formed at intervals from the bottom of first semiconductor region 6 toward active surface 8.

[0127] The multiple dummy trench structures 50 are incorporated into the active surface 8 for one purpose of alleviating local electric field concentration near the active region 13 and near the trench resistor structure 20 and improving the breakdown voltage (e.g., breakdown voltage). The multiple dummy trench structures 50 (dummy regions 15) may or may not be provided, and a configuration not including the multiple dummy trench structures 50 (dummy regions 15) may also be employed.

[0128] The multiple dummy trench structures 50 on the first dummy region 15A side are each formed in a strip shape extending in the first direction X in the region between the third connection surface 10C and the trench resistance structure 20, and are arranged at intervals in the second direction Y. The multiple dummy trench structures 50 on the first dummy region 15A side are formed at intervals from the trench resistance structure 20 in the first direction X, and face the trench resistance structure 20 in the first direction X.

[0129] The multiple dummy trench structures 50 on the first dummy region 15A side face the multiple trench gate structures 30 and the multiple first trench source structures 35 in the second direction Y. The multiple dummy trench structures 50 on the first dummy region 15A side penetrate the third connection surface 10C and are exposed from the third connection surface 10C. In other words, the multiple dummy trench structures 50 on the first dummy region 15A side face the multiple second trench source structures 40 in the second direction Y.

[0130] The multiple dummy trench structures 50 on the second dummy region 15B side are each formed in a strip shape extending in the first direction X in a region between the fourth connection surface 10D and the trench resistance structure 20, and are arranged at intervals in the second direction Y. The multiple dummy trench structures 50 on the second dummy region 15B side are formed at intervals from the trench resistance structure 20 in the first direction X, and face the trench resistance structure 20 in the first direction X. The multiple dummy trench structures 50 on the second dummy region 15B side may face the multiple dummy trench structures 50 on the first dummy region 15A side in a one-to-one correspondence, with the trench resistance structure 20 sandwiched between them.

[0131] The multiple dummy trench structures 50 on the second dummy region 15B side face the multiple trench gate structures 30 and the multiple first trench source structures 35 in the second direction Y. The multiple dummy trench structures 50 on the second dummy region 15B side penetrate the fourth connection surface 10D and are exposed from the fourth connection surface 10D. In other words, the multiple dummy trench structures 50 on the second dummy region 15B side face the multiple second trench source structures 40 in the second direction Y.

[0132] The plurality of dummy trench structures 50 on the third dummy region 15C side are each formed in a strip shape extending in the first direction X in the region between the second connection surface 10B and the first active region 13A, and are arranged at intervals in the second direction Y. The plurality of dummy trench structures 50 on the third dummy region 15C side penetrates at least one of the third connection surface 10C and the fourth connection surface 10D, and is exposed from at least one of the third connection surface 10C and the fourth connection surface 10D.

[0133] In this embodiment, the plurality of dummy trench structures 50 on the third dummy region 15C side are exposed from both the third connection surface 10C and the fourth connection surface 10D. The plurality of dummy trench structures 50 on the third dummy region 15C side face the plurality of trench gate structures 30, the plurality of first trench source structures 35, and the plurality of second trench source structures 40 in the second direction Y.

[0134] In this embodiment, the multiple dummy trench structures 50 include multiple first dummy trench structures 51 and multiple second dummy trench structures 52 that are deeper than the multiple first dummy trench structures 51. The multiple first dummy trench structures 51 are each formed in a strip shape extending in the first direction X and are arranged at intervals in the second direction Y. The multiple first dummy trench structures 51 are exposed from either or both of the third connecting surface 10C and the fourth connecting surface 10D in the first to third dummy regions 15A to 15C.

[0135] The plurality of first dummy trench structures 51 face the trench resistance structure 20 in the first direction X in the first and second dummy regions 15A and 15B, and face the plurality of trench gate structures 30, the plurality of first trench source structures 35, and the plurality of second trench source structures 40 in the second direction Y. The plurality of first dummy trench structures 51 penetrate the body region 19 to reach the first semiconductor region 6. The plurality of first dummy trench structures 51 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0136] One first dummy trench structure 51 will be described below. The first dummy trench structure 51 has a fourth width W4 in the second direction Y and a fourth depth D4 in the normal direction Z. The fourth width W4 is preferably approximately equal to the first width W1 described above. The fourth width W4 may be 0.1 μm or more and 3 μm or less. The fourth width W4 is preferably 0.5 μm or more and 2 μm or less.

[0137] The fourth depth D4 is less than the resistor depth DR (second depth D2) described above. The fourth depth D4 may be ⅓ or more and ⅔ or less of the resistor depth DR (second depth D2). The fourth depth D4 is preferably approximately equal to the first depth D1 described above. The fourth depth D4 may be 0.1 μm or more and 3 μm or less. The fourth depth D4 is preferably 0.5 μm or more and 1.5 μm or less.

[0138] The first dummy trench structure 51 is arranged at a sixth distance I6 from the trench resistor structure 20 in the first direction X. The sixth distance I6 is preferably 0.5 to 2 times the fourth width W4. The sixth distance I6 may be approximately equal to the first distance I1. The sixth distance I6 may be 0.1 μm to 2.5 μm. The sixth distance I6 is preferably 0.5 μm to 1.5 μm. In this embodiment, the outermost first dummy trench structure 51 on the active region 13 side is arranged at the second distance I2 from the outermost first trench source structure 35 so as to be adjacent to the outermost first trench source structure 35 in the second direction Y.

[0139] The first dummy trench structure 51 includes a first dummy trench 53, a first dummy insulating film 54, and a first dummy buried electrode 55. The first dummy trench 53 is formed in the active surface 8 and defines the wall surface of the first dummy trench structure 51. The sidewall and bottom wall of the first dummy trench 53 communicate with the third connecting surface 10C (fourth connecting surface 10D).

[0140] The first dummy insulating film 54 covers the wall surfaces of the first dummy trenches 53 and is connected to the main surface insulating film 18 at the active surface 8. The first dummy insulating film 54 is connected to the main surface insulating film 18 at the communicating portion of the third connection surface 10C (the communicating portion of the fourth connection surface 10D). The first dummy insulating film 54 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first dummy insulating film 54 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first dummy insulating film 54 include a silicon oxide film made of an oxide of the chip 2.

[0141] The first dummy buried electrode 55 is disposed in the first dummy trench 53 with the first dummy insulating film 54 sandwiched therebetween. The first dummy buried electrode 55 may include conductive polysilicon. The first dummy buried electrode 55 has an end face located on the active surface 8 side relative to the height position of the resistor end face 25a of the buried resistor 25. The end face of the first dummy buried electrode 55 may be located on the active surface 8 side relative to the height position of the insulating end face 26a of the buried insulator 26.

[0142] The second dummy trench structures 52 are arranged in a region between two adjacent first dummy trench structures 51 in the second direction Y. The second dummy trench structures 52 are arranged alternately with the first dummy trench structures 51 in the second direction Y, and are each formed in a strip shape extending in the first direction X. The second dummy trench structures 52 are exposed from either or both of the third connecting surface 10C and the fourth connecting surface 10D in the first to third dummy regions 15A to 15C.

[0143] The second dummy trench structures 52 face the trench resistance structure 20 in the first direction X in the first and second dummy regions 15A and 15B, and face the trench gate structures 30, the first trench source structures 35, the second trench source structures 40, and the first dummy trench structures 51 in the second direction Y. The second dummy trench structures 52 penetrate the body region 19 to reach the first semiconductor region 6. The second dummy trench structures 52 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0144] One second dummy trench structure 52 will be described below. The second dummy trench structure 52 has a fifth width W5 in the second direction Y and a fifth depth D5 in the normal direction Z. The fifth width W5 is preferably approximately equal to the second width W2 (first width W1) described above. The fifth width W5 may be 0.1 μm or more and 3 μm or less. The fifth width W5 is preferably 0.5 μm or more and 2 μm or less.

[0145] The fifth depth D5 is equal to or greater than the fourth depth D4 (first depth D1). In this embodiment, the fifth depth D5 is greater than the fourth depth D4 (first depth D1). The fifth depth D5 is preferably 1.5 to 3 times the fourth depth D4 (first depth D1). It is particularly preferable that the fifth depth D5 be approximately equal to the resistor depth DR (periphery depth DO) described above. The fifth depth D5 may be 0.1 μm to 5 μm. It is particularly preferable that the fifth depth D5 be 2.5 μm or less.

[0146] The second dummy trench structure 52 is disposed in the second direction Y at a seventh interval I7 from the first dummy trench structure 51. The seventh interval I7 is preferably 0.5 to 2 times the fifth width W5. It is particularly preferable that the seventh interval I7 be less than the fifth width W5. The seventh interval I7 is preferably approximately equal to the second interval I2 described above. The seventh interval I7 may be 0.1 μm to 2.5 μm. It is preferable that the seventh interval I7 be 0.5 μm to 1.5 μm.

[0147] The second dummy trench structure 52 is disposed in the first direction X at an eighth distance I8 from the trench resistor structure 20. The eighth distance I8 is preferably 0.5 to 2 times the fifth width W5. The eighth distance I8 may be approximately equal to the first distance I1. The eighth distance I8 may be 0.1 μm to 2.5 μm. The eighth distance I8 is preferably 0.5 μm to 1.5 μm.

[0148] The second dummy trench structure 52 includes a second dummy trench 56, a second dummy insulating film 57, and a second dummy buried electrode 58. The second dummy trench 56 is formed in the active surface 8 and defines the wall surface of the second dummy trench structure 52. The sidewall of the second dummy trench 56 communicates with the third connection surface 10C (fourth connection surface 10D). The bottom wall of the second dummy trench 56 communicates with the outer peripheral surface 9.

[0149] The second dummy insulating film 57 covers the wall surfaces of the second dummy trenches 56 and is connected to the main surface insulating film 18 at the active surface 8. The second dummy insulating film 57 is connected to the main surface insulating film 18 at the communicating portion of the third connection surface 10C (the communicating portion of the fourth connection surface 10D) and the communicating portion of the outer peripheral surface 9. The second dummy insulating film 57 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second dummy insulating film 57 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second dummy insulating film 57 include a silicon oxide film made of an oxide of the chip 2.

[0150] The second dummy buried electrode 58 is disposed in the second dummy trench 56 with the second dummy insulating film 57 sandwiched therebetween. The second dummy buried electrode 58 may include conductive polysilicon. The second dummy buried electrode 58 has an end face located on the active surface 8 side relative to the height position of the resistor end face 25a of the buried resistor 25. The end face of the second dummy buried electrode 58 may be located on the active surface 8 side relative to the height position of the insulating end face 26a of the buried insulator 26.

[0151] The semiconductor device 1 includes a plurality of p-type fifth well regions 67 formed in the dummy region 15 in regions along the plurality of first dummy trench structures 51. In this embodiment, the fifth well regions 67 have a higher p-type impurity concentration than the body region 19. Of course, the p-type impurity concentration of the fifth well regions 67 may be lower than that of the body region 19. It is preferable that the p-type impurity concentration of the fifth well regions 67 is approximately equal to the p-type impurity concentration of the first well region 28.

[0152] The plurality of fifth well regions 67 cover the wall surfaces of the corresponding first dummy trench structures 51 at intervals from the adjacent second dummy trench structures 52, and are electrically connected to the body region 19 in the surface layer portion of the active surface 8. The plurality of fifth well regions 67 are exposed from the third connection surface 10C or the fourth connection surface 10D.

[0153] The plurality of fifth well regions 67 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the plurality of fifth well regions 67 are located on the active surface 8 side relative to the depth position of the bottom of the first well region 28. The bottoms of the plurality of fifth well regions 67 are formed at approximately the same depth as the bottom of the second well region 45. The plurality of fifth well regions 67 form pn junctions with the first semiconductor region 6.

[0154] The semiconductor device 1 includes a plurality of p-type sixth well regions 68 formed in the dummy region 15 in regions along the plurality of second dummy trench structures 52. In this embodiment, the sixth well regions 68 have a higher p-type impurity concentration than the body region 19. Of course, the p-type impurity concentration of the sixth well regions 68 may be lower than that of the body region 19. It is preferable that the p-type impurity concentration of the sixth well regions 68 be approximately equal to the p-type impurity concentration of the first well region 28 (fifth well region 67).

[0155] The plurality of sixth well regions 68 cover the wall surfaces of the corresponding second dummy trench structures 52 at intervals from the adjacent first dummy trench structures 51, and are electrically connected to the body region 19 in the surface portion of the active surface 8. The plurality of sixth well regions 68 are exposed from the third connection surface 10C or the fourth connection surface 10D. The plurality of sixth well regions 68 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 with a part of the first semiconductor region 6 in between.

[0156] The bottoms of the plurality of sixth well regions 68 are located closer to the bottom of the first semiconductor region 6 than the depth position of the bottoms of the plurality of fifth well regions 67 (second well region 45). The bottoms of the plurality of sixth well regions 68 are formed at approximately the same depth as the bottom of the first well region 28 (third well region 46). The plurality of sixth well regions 68 form pn junctions with the first semiconductor region 6.

[0157] The semiconductor device 1 includes a plurality of p-type second contact regions 69 formed in the dummy region 15 in regions along the plurality of second dummy trench structures 52. The second contact regions 69 have a higher p-type impurity concentration than the body region 19. The p-type impurity concentration of the second contact regions 69 is higher than the sixth well region 68. It is preferable that the p-type impurity concentration of the second contact regions 69 be approximately equal to the p-type impurity concentration of the first contact region 48.

[0158] The second contact regions 69 cover the wall surfaces of the corresponding second dummy trench structures 52 in the corresponding sixth well regions 68. The second contact regions 69 are formed in a one-to-many correspondence with the second dummy trench structures 52. The second contact regions 69 are formed at intervals along the corresponding second dummy trench structures 52. The second contact regions 69 are extended from the corresponding sixth well regions 68 along the wall surfaces of the corresponding second dummy trench structures 52 to the surface layer of the body region 19 and are exposed from the active surface 8.

[0159] In this embodiment, the multiple second contact regions 69 are each formed in a strip shape extending in the first direction X in a plan view. The length of the multiple second contact regions 69 in the first direction X is preferably equal to or greater than the fifth width W5 of the second dummy trench structure 52. The length of the multiple second contact regions 69 is preferably greater than the distance between two second contact regions 69 adjacent to each other in the first direction X. The length of the multiple second contact regions 69 is preferably approximately equal to the length of the multiple first contact regions 48.

[0160] The multiple second contact regions 69 along one second dummy trench structure 52 face the multiple second contact regions 69 along other second dummy trench structures 52 in the second direction Y. That is, in this embodiment, the multiple second contact regions 69 are arranged in a matrix with gaps in between in the first direction X and the second direction Y as a whole in a plan view. In this case, the multiple second contact regions 69 may be arranged in a matrix together with the multiple first contact regions 48. The multiple second contact regions 69 may also be arranged in a matrix together with the multiple first contact regions 48.

[0161] The multiple second contact regions 69 along one second dummy trench structure 52 may be arranged offset in the first direction X so as to face in the second direction Y in regions between the multiple second contact regions 69 along other second dummy trench structures 52. In other words, the multiple second contact regions 69 may be arranged in a staggered pattern overall in a plan view with intervals in the first direction X and the second direction Y. In this case, the multiple second contact regions 69 may be arranged in a staggered pattern together with the multiple first contact regions 48. The multiple second contact regions 69 may also be arranged in a staggered pattern together with the multiple first contact regions 48.

[0162] FIG. 23 is an enlarged plan view showing the layout of termination region 16. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 23. Referring to FIGS. 23 and 24, semiconductor device 1 includes a plurality of trench termination structures 70 formed in termination region 16 on first main surface 3 (active surface 8). A potential different from that applied to trench resistor structure 20 is applied to the plurality of trench termination structures 70. A source potential VS is applied to the plurality of trench termination structures 70. The plurality of trench termination structures 70 penetrate body region 19 to reach first semiconductor region 6 and are formed at intervals from the bottom of first semiconductor region 6 toward active surface 8.

[0163] The plurality of trench termination structures 70 are incorporated into the active surface 8 for one purpose: to alleviate local electric field concentrations around the periphery of the active surface 8 and in the vicinity of the trench resistor structure 20, thereby improving the breakdown voltage (e.g., breakdown voltage). The presence or absence of the plurality of trench termination structures 70 (termination region 16) is optional, and a configuration not including the plurality of trench termination structures 70 (termination region 16) may also be employed.

[0164] The plurality of trench termination structures 70 on the first termination region 16A side are each formed in a strip shape extending in the first direction X in the region between the first connection surface 10A and the trench resistance structure 20, and are arranged at intervals in the second direction Y. The plurality of trench termination structures 70 on the first termination region 16A side are formed at intervals in the second direction Y from the trench resistance structure 20, and face the trench resistance structure 20 in the second direction Y. The plurality of trench termination structures 70 on the first termination region 16A side are further formed at intervals in the second direction Y from the outermost dummy trench structure 50 (first dummy trench structure 51 in this embodiment), and face the outermost dummy trench structure 50 in the second direction Y.

[0165] The plurality of trench termination structures 70 on the first termination region 16A side penetrate at least one of the third connection surface 10C and the fourth connection surface 10D and are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D. In this embodiment, the plurality of trench termination structures 70 on the first termination region 16A side are exposed from both the third connection surface 10C and the fourth connection surface 10D.

[0166] The plurality of trench termination structures 70 on the second termination region 16B side are each formed in a strip shape extending in the first direction X in the region between the second connection surface 10B and the third dummy region 15C, and are arranged at intervals in the second direction Y. The plurality of trench termination structures 70 on the second termination region 16B side are formed at intervals in the second direction Y from the outermost dummy trench structure 50 (first dummy trench structure 51 in this embodiment), and face the outermost dummy trench structure 50 in the second direction Y.

[0167] The plurality of trench termination structures 70 on the second termination region 16B side penetrate at least one of the third connection surface 10C and the fourth connection surface 10D and are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D. In this embodiment, the plurality of trench termination structures 70 on the second termination region 16B side are exposed from both the third connection surface 10C and the fourth connection surface 10D.

[0168] One trench termination structure 70 will be described below. Trench termination structure 70 has a sixth width W6 in second direction Y and a sixth depth D6 in normal direction Z. The sixth width W6 is preferably approximately equal to the first width W1 (second width W2) described above. The sixth width W6 may be 0.1 μm or more and 3 μm or less. The sixth width W6 is preferably 0.5 μm or more and 2 μm or less.

[0169] The sixth depth D6 is equal to or greater than the first depth D1. In this embodiment, the sixth depth D6 is greater than the first depth D1. The sixth depth D6 is preferably 1.5 to 3 times the first depth D1. It is particularly preferable that the sixth depth D6 be approximately equal to the resistor depth DR (periphery depth DO) described above. The sixth depth D6 may be 0.1 μm to 5 μm. It is particularly preferable that the second depth D2 be 2.5 μm or less.

[0170] The multiple trench termination structures 70 are arranged at a ninth interval I9 in the second direction Y. In addition, the outermost trench termination structure 70 on the trench resistance structure 20 side is arranged at a ninth interval I9 in the second direction Y from the trench resistance structure 20 and the outermost dummy trench structure 50 (first dummy trench structure 51 in this embodiment).

[0171] The ninth interval I9 is ​​preferably 0.5 to 2 times the sixth width W6. It is particularly preferable that the ninth interval I9 be less than the sixth width W6. It is preferable that the ninth interval I9 be approximately equal to the second interval I2 described above. The ninth interval I9 may be 0.1 μm to 2.5 μm. It is preferable that the ninth interval I9 be 0.5 μm to 1.5 μm.

[0172] Trench termination structure 70 includes a termination trench 71, a termination insulating film 72, and a termination buried electrode 73. Termination trench 71 is formed in active surface 8 and defines the wall surface of trench termination structure 70. The sidewall of termination trench 71 communicates with third connection surface 10C and fourth connection surface 10D. The bottom wall of termination trench 71 communicates with outer peripheral surface 9.

[0173] The termination insulating film 72 covers the wall surface of the termination trench 71 and is connected to the main surface insulating film 18 at the active surface 8. The termination insulating film 72 is connected to the main surface insulating film 18 at the communicating portion of the third connecting surface 10C, the communicating portion of the fourth connecting surface 10D, and the communicating portion of the outer peripheral surface 9. The termination insulating film 72 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the termination insulating film 72 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the termination insulating film 72 include a silicon oxide film made of an oxide of the chip 2.

[0174] The buried termination electrode 73 is disposed in the termination trench 71 with the termination insulating film 72 sandwiched therebetween. The buried termination electrode 73 may include conductive polysilicon. The buried termination electrode 73 has an end face located on the active surface 8 side relative to the height position of the resistor end face 25a of the buried resistor 25. The end face of the buried termination electrode 73 may be located on the active surface 8 side relative to the height position of the insulating end face 26a of the buried insulator 26.

[0175] The semiconductor device 1 includes a plurality of p-type seventh well regions 74 formed in the termination region 16 in regions along the plurality of trench termination structures 70. In this embodiment, the seventh well regions 74 have a higher p-type impurity concentration than the body region 19. Of course, the p-type impurity concentration of the seventh well regions 74 may be lower than that of the body region 19. It is preferable that the p-type impurity concentration of the seventh well regions 74 be approximately equal to the p-type impurity concentration of the first well region 28.

[0176] The seventh well regions 74 cover the wall surfaces of the corresponding trench termination structures 70 at intervals from adjacent trench termination structures 70, and are electrically connected to body region 19 in the surface portion of active surface 8. The seventh well regions 74 extend in a strip shape along the corresponding trench termination structures 70 in a plan view, and are exposed from third connection surface 10C and fourth connection surface 10D.

[0177] The multiple seventh well regions 74 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the multiple seventh well regions 74 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the multiple second well regions 45. The bottoms of the multiple seventh well regions 74 are formed at approximately the same depth as the bottom of the first well region 28 (third well region 46). The multiple seventh well regions 74 form pn junctions with the first semiconductor region 6.

[0178] Next, the structure of the peripheral region 17 will be described with reference to the cross-sectional view of Figure 25. Referring to Figure 25, the semiconductor device 1 includes a p-type outer well region 75 formed in a surface layer portion of the peripheral surface 9. The outer well region 75 has a p-type impurity concentration lower than that of the first contact region 48. In this embodiment, the p-type impurity concentration of the outer well region 75 is higher than that of the body region 19. Of course, the p-type impurity concentration of the outer well region 75 may be lower than that of the body region 19. It is preferable that the outer well region 75 has a p-type impurity concentration approximately equal to that of the first well region 28.

[0179] The outer well region 75 is formed in a plan view at a distance from the periphery of the outer peripheral surface 9 (first to fourth side surfaces 5A to 5D) toward the active surface 8, and extends in a band shape along the active surface 8. In this embodiment, the outer well region 75 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8 in a plan view. The outer well region 75 extends from the surface layer portion of the outer peripheral surface 9 toward the surface layer portions of the first to fourth connection surfaces 10A to 10D.

[0180] The outer well region 75 is electrically connected to the body region 19 in a surface layer portion of the active surface 8. The outer well region 75 is connected to the third well region 46 at the connection portion between the third connection surface 10C (fourth connection surface 10D) and the first trench source structure 35. The outer well region 75 is connected to the fourth well region 47 at the connection portion between the third connection surface 10C (fourth connection surface 10D) and the second trench source structure 40.

[0181] The outer well region 75 is connected to the fifth well region 67 at the communication portion between the third connection surface 10C (fourth connection surface 10D) and the first dummy trench structure 51. The outer well region 75 is connected to the sixth well region 68 at the communication portion between the third connection surface 10C (fourth connection surface 10D) and the second dummy trench structure 52. The outer well region 75 is connected to the seventh well region 74 at the communication portion between the third connection surface 10C (fourth connection surface 10D) and the trench termination structure 70.

[0182] The outer well region 75 is formed at a distance from the bottom of the first semiconductor region 6 toward the outer circumferential surface 9, and faces the second semiconductor region 7 across a part of the first semiconductor region 6. The outer well region 75 is located closer to the bottom of the first semiconductor region 6 than the bottom wall 22 of the trench resistance structure 20. The outer well region 75 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first trench source structure 35.

[0183] The bottom of the outer well region 75 is located closer to the bottom of the first semiconductor region 6 than the bottom of the first contact region 48. The bottom of the outer well region 75 is preferably formed at a depth substantially equal to the bottom of the first well region 28 (third well region 46). The outer well region 75 forms a pn junction with the first semiconductor region 6.

[0184] The semiconductor device 1 includes a p-type outer contact region 76 formed in a surface layer portion of the outer well region 75. The outer contact region 76 has a higher p-type impurity concentration than the body region 19. The p-type impurity concentration of the outer contact region 76 is higher than that of the outer well region 75. It is preferable that the p-type impurity concentration of the outer contact region 76 is approximately equal to the p-type impurity concentration of the first contact region 48.

[0185] The outer contact region 76 is formed in the surface layer portion of the outer well region 75 at a distance from the periphery of the active surface 8 (first to fourth connection surfaces 10A to 10D) and the periphery of the outer peripheral surface 9 (first to fourth side surfaces 5A to 5D) in plan view, and is formed in a band shape extending along the active surface 8. In this embodiment, the outer contact region 76 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in plan view.

[0186] The outer contact region 76 is formed at a distance from the bottom of the outer well region 75 toward the outer peripheral surface 9, and faces the first semiconductor region 6 across a part of the outer well region 75. The outer contact region 76 is located closer to the bottom of the first semiconductor region 6 than the bottom wall 22 of the trench resistor structure 20. The outer contact region 76 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first trench source structure 35. The bottom of the outer contact region 76 is preferably formed at a depth position substantially equal to the bottom of the first contact region 48.

[0187] Semiconductor device 1 includes at least one (preferably two to twenty) p-type field region 77 formed in a surface layer portion of outer peripheral surface 9 in a region between the periphery of outer peripheral surface 9 and outer well region 75. In this embodiment, semiconductor device 1 includes four field regions 77. The multiple field regions 77 are formed in an electrically floating state and relieve the electric field within chip 2 at outer peripheral surface 9.

[0188] The number, width, depth, p-type impurity concentration, etc. of the field regions 77 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The field regions 77 may have a lower p-type impurity concentration than the outer contact regions 76. The field regions 77 may have a higher p-type impurity concentration than the outer well region 75. The field regions 77 may have a lower p-type impurity concentration than the outer well region 75.

[0189] The multiple field regions 77 are arranged at intervals from the outer well region 75 side to the peripheral edge side of the outer peripheral surface 9. The multiple field regions 77 are formed in a band shape extending along the active surface 8 in a plan view. In this embodiment, the multiple field regions 77 are formed in a ring shape (specifically, a square ring) surrounding the active surface 8 in a plan view.

[0190] The plurality of field regions 77 are formed at intervals from the bottom of the first semiconductor region 6 toward the outer peripheral surface 9, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The plurality of field regions 77 are located closer to the bottom of the first semiconductor region 6 than the bottom wall 22 of the trench resistance structure 20.

[0191] The plurality of field regions 77 are located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first trench source structure 35. The bottoms of the plurality of field regions 77 are located closer to the bottom of the first semiconductor region 6 than the bottoms of the first contact regions 48. The bottoms of the plurality of field regions 77 may be formed at a depth position substantially equal to the bottom of the third well region 46.

[0192] The semiconductor device 1 includes a sidewall wiring 78 formed on the outer peripheral surface 9 so as to cover at least one of the first to fourth connecting surfaces 10A to 10D. Specifically, the sidewall wiring 78 is disposed on the main surface insulating film 18. The sidewall wiring 78 also functions as a sidewall structure that reduces a step formed between the active surface 8 and the outer peripheral surface 9.

[0193] The sidewall wiring 78 is preferably formed in a strip shape extending along at least one of the third connecting surface 10C and the fourth connecting surface 10D. In this embodiment, the sidewall wiring 78 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connecting surfaces 10A to 10D so as to surround the active surface 8 in a plan view. The portions of the sidewall wiring 78 that cover the four corners of the active surface 8 are formed in a curved shape toward the outer peripheral surface 9.

[0194] The sidewall wiring 78 includes a portion extending in a film-like manner along the outer circumferential surface 9 and a portion extending in a film-like manner along the first to fourth connecting surfaces 10A to 10D. The portion of the sidewall wiring 78 located on the outer circumferential surface 9 may cover the outer circumferential surface 9 in a film-like manner in a region on the outer circumferential surface 9 side of the active surface 8. The portion of the sidewall wiring 78 located on the outer circumferential surface 9 may have a thickness less than the thickness of the active plateau 11 (peripheral depth DO).

[0195] The sidewall wiring 78 faces the outer well region 75 on the outer peripheral surface 9, with the main surface insulating film 18 therebetween. The sidewall wiring 78 may also face the outer contact region 76, with the main surface insulating film 18 therebetween. In this embodiment, the sidewall wiring 78 is formed at an interval from the field region 77 toward the active surface 8 in plan view.

[0196] The sidewall wiring 78 faces the third well region 46, the fourth well region 47, the fifth well region 67, the sixth well region 68, the seventh well region 74, and the outer well region 75 on the first to fourth connecting surfaces 10A to 10D, with the main surface insulating film 18 sandwiched therebetween. In this embodiment, the sidewall wiring 78 also faces the body region 19, with the main surface insulating film 18 sandwiched therebetween.

[0197] The sidewall wiring 78 covers the exposed portions of the first trench source structure 35, the second trench source structure 40, the first dummy trench structure 51, the second dummy trench structure 52, and the trench termination structure 70 at the first to fourth connection surfaces 10A to 10D.

[0198] As a result, the sidewall wiring 78 is electrically connected to the first trench source structure 35, the second trench source structure 40, the first dummy trench structure 51, the second dummy trench structure 52, and the trench termination structure 70. In other words, the sidewall wiring 78 applies the source potential VS to the connection target from the outer circumferential surface 9 side.

[0199] The sidewall wiring 78 has an overlapping portion 79 that extends from at least one of the first to fourth connecting surfaces 10A to 10D onto the edge of the active surface 8. The overlapping portion 79 covers the active surface 8 in a film-like manner in plan view and is formed in a band shape that extends along the edge of the active surface 8. In this form, the overlapping portion 79 is formed in a ring shape (specifically, a quadrangular ring) that surrounds the inner portion of the active surface 8 in plan view.

[0200] The overlap portion 79 is formed on the active surface 8 at a distance from the trench resistor structure 20 toward the peripheral edge of the active surface 8. The overlap portion 79 is electrically connected to the first trench source structure 35, the second trench source structure 40, the first dummy trench structure 51, the second dummy trench structure 52, and the trench termination structure 70.

[0201] In this embodiment, the sidewall wiring 78 includes conductive polysilicon and is formed integrally with the first buried source electrode 38, the second buried source electrode 43, the first dummy buried electrode 55, the second dummy buried electrode 58, and the terminal buried electrode 73. Of course, the sidewall wiring 78 may be formed separately from the first buried source electrode 38, the second buried source electrode 43, the first dummy buried electrode 55, the second dummy buried electrode 58, and the terminal buried electrode 73.

[0202] The semiconductor device 1 includes an interlayer insulating film 80 that covers the main surface insulating film 18. The interlayer insulating film 80 covers the active surface 8, the outer peripheral surface 9, and the first to fourth connecting surfaces 10A to 10D with the main surface insulating film 18 sandwiched therebetween. The interlayer insulating film 80 covers the trench resistance structure 20, the trench gate structure 30, the first trench source structure 35, the second trench source structure 40, the first dummy trench structure 51, the second dummy trench structure 52, and the trench termination structure 70 on the active surface 8.

[0203] The interlayer insulating film 80 extends from above the main surface insulating film 18 into the resistor trench 23 in the resistor region 12. The interlayer insulating film 80 extends into the resistor trench 23 from the entire periphery (first to fourth side walls 21A to 21D) of the resistor trench 23. The interlayer insulating film 80 covers the resistor insulating film 24 on the periphery (first to fourth side walls 21A to 21D) of the resistor trench 23 and is connected to the buried insulator 26.

[0204] The interlayer insulating film 80 is preferably connected to the resistive insulating film 24 at a distance from the periphery of the embedded resistor 25 in plan view. In this embodiment, the interlayer insulating film 80 forms a single insulating film together with the embedded insulator 26. That is, in this embodiment, the embedded insulator 26 is formed by utilizing a part of the interlayer insulating film 80. Of course, the interlayer insulating film 80 may be formed separately from the embedded insulator 26.

[0205] The interlayer insulating film 80 covers the outer well region 75, the outer contact region 76, and the plurality of field regions 77 with the main surface insulating film 18 sandwiched therebetween in the peripheral region 17. The interlayer insulating film 80 covers the sidewall wirings 78 on the first to fourth connecting surfaces 10A to 10D.

[0206] In this embodiment, the interlayer insulating film 80 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the wall portions of the interlayer insulating film 80 may be formed at intervals inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9. The interlayer insulating film 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer insulating film 80 includes a silicon oxide film.

[0207] 1 to 17 (particularly FIGS. 5 and 6 ), semiconductor device 1 includes a gate electrode 85 disposed on trench resistance structure 20. Gate electrode 85 has a resistance value lower than that of trench resistance structure 20. Specifically, gate electrode 85 has a resistance value lower than that of buried resistor 25.

[0208] The gate electrode 85 is preferably thicker than the buried resistor 25. It is particularly preferable that the gate electrode 85 is thicker than the buried insulator 26. The gate electrode 85 is preferably thicker than the interlayer insulating film 80. The gate electrode 85 preferably has a thickness greater than the first depth D1 described above. The gate electrode 85 preferably has a thickness greater than the resistor depth DR (peripheral depth DO, second depth D2) described above. The gate electrode 85 may have a thickness of 0.5 μm or more and 10 μm or less. The thickness of the gate electrode 85 is preferably 1 μm or more and 5 μm or less.

[0209] The gate electrode 85 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. The gate electrode 85 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the gate electrode 85 has a layered structure including a Ti film and an Al alloy film (an AlSiCu alloy film in this embodiment) stacked in this order from the chip 2 side. The gate electrode 85 may also be referred to as a "gate metal."

[0210] In this embodiment, the gate electrode 85 includes a gate pad 86, a gate wiring 87, and a gate subpad 88. A gate potential VG is applied to the gate pad 86 from the outside. The gate pad 86 is disposed directly above the trench resistor structure 20 in the resistor region 12. In this embodiment, the gate pad 86 is disposed on an inner portion of the active surface 8 at a distance from the periphery of the active surface 8, and is not disposed on the outer circumferential surface 9.

[0211] In this embodiment, the gate pad 86 has a planar area smaller than that of the trench resistor structure 20 (resistance trench 23), and is arranged only within the region surrounded by the periphery of the trench resistor structure 20, with a space inward from the periphery of the trench resistor structure 20. In other words, the gate pad 86 is arranged directly above the trench resistor structure 20, with a space from the active region 13 (first to third active regions 13A to 13C), dummy region 15, and termination region 16, and does not face the active region 13, dummy region 15, or termination region 16 in the normal direction Z.

[0212] The gate pad 86 preferably has a planar area of ​​1% to 25% of the planar area of ​​the first main surface 3. The planar area of ​​the gate pad 86 is preferably 5% to 20% of the planar area of ​​the first main surface 3. Of course, the gate pad 86 may have a planar area larger than the planar area of ​​the trench resistor structure 20. In this case, the gate pad 86 may face at least one of the active region 13, the dummy region 15, and the termination region 16 in the normal direction Z.

[0213] Specifically, the gate pad 86 is disposed on the buried insulator 26 so as to face the buried resistor 25. The gate pad 86 has a planar area equal to or larger than the planar area of ​​the buried resistor 25. The planar area of ​​the gate pad 86 is preferably larger than the planar area of ​​the buried resistor 25. Of course, the planar area of ​​the gate pad 86 may be set to be smaller than the planar area of ​​the buried resistor 25.

[0214] The gate pad 86 is disposed inside the resistor trench 23 at a distance from the periphery (first to fourth side walls 21A to 21D) of the resistor trench 23. In other words, the gate pad 86 is disposed so as to avoid a step formed between the active surface 8 and the resistor trench 23.

[0215] In this embodiment, the gate pad 86 is formed at a distance inward from the entire periphery of the first to fourth side walls 21A to 21D. In other words, the gate pad 86 is disposed only on the buried insulator 26, and is not disposed on the interlayer insulating film 80. In this embodiment, the gate pad 86 is formed in a quadrangular shape having four sides parallel to the periphery of the resistive trench 23 in a plan view. Of course, the gate pad 86 may be formed in a polygonal or circular shape in a plan view.

[0216] The gate pad 86 has a first covering portion 86a that covers the embedded resistor 25 with the embedded insulator 26 in between, and a second covering portion 86b that covers the insulating region 27 with the embedded insulator 26 in between. The facing area of ​​the second covering portion 86b to the insulating region 27 is preferably larger than the facing area of ​​the first covering portion 86a to the embedded resistor 25. This structure is particularly preferable when the plane area of ​​the insulating region 27 is larger than the plane area of ​​the embedded resistor 25. Of course, the facing area of ​​the second covering portion 86b to the insulating region 27 may be smaller than the facing area of ​​the first covering portion 86a to the embedded resistor 25.

[0217] In this embodiment, the gate pad 86 has a portion located on the bottom wall 22 side of the resistor trench 23 relative to the height position of the active surface 8, and a portion that protrudes upward relative to the height position of the active surface 8. The portion of the gate pad 86 located on the bottom wall 22 side of the resistor trench 23 penetrates the buried insulator 26 and is electrically connected to the buried resistor 25. Specifically, the gate pad 86 is connected to the buried resistor 25 via a first resistor opening 89 formed in the buried resistor 25.

[0218] The first resistor openings 89 are formed in a strip shape extending in the first direction X in a plan view. The planar shape and number of the first resistor openings 89 are arbitrary. For example, a plurality of first resistor openings 89 each having a rectangular shape in a plan view may be formed at intervals in either or both of the first direction X and the second direction Y.

[0219] The plane area of ​​the connection portion of the gate pad 86 to the buried resistor 25 is preferably smaller than the plane area of ​​the non-connection portion of the gate pad 86 to the buried resistor 25. Of course, the plane area of ​​the connection portion of the gate pad 86 to the buried resistor 25 may be larger than the plane area of ​​the non-connection portion of the gate pad 86 to the buried resistor 25.

[0220] The gate wiring 87 is electrically connected to the gate pad 86 via the trench resistor structure 20 in the resistor region 12, and is electrically connected to the plurality of trench gate structures 30 in the active region 13. The gate wiring 87 transmits the gate potential VG applied to the gate pad 86 to the plurality of trench gate structures 30.

[0221] The gate wiring 87 is arranged directly above the trench resistor structure 20 at a distance from the gate pad 86 in the resistor region 12, and is selectively routed from the resistor region 12 to the active region 13. In this embodiment, the gate wiring 87 is arranged on the inner part of the active surface 8 at a distance from the periphery of the active surface 8, and is not arranged on the outer circumferential surface 9.

[0222] In this embodiment, the gate wiring 87 includes a resistance wiring 87 a, a first gate wiring 87 b, a second gate wiring 87 c, and a third gate wiring 87 d. The resistance wiring 87 a is located directly above the trench resistance structure 20 and is connected to the trench resistance structure 20. In this embodiment, the resistance wiring 87 a is formed in a strip shape extending in the first direction X so as to intersect (specifically, perpendicular to) the trench resistance structure 20 in a plan view, and is arranged in a region between the first sidewall 21A of the trench resistance structure 20 and the gate pad 86.

[0223] Specifically, the resistance wiring 87a is formed in a strip shape narrower than the trench resistance structure 20 in the second direction Y, and is disposed in a region between the first sidewall 21A and the gate pad 86 at a distance from the first sidewall 21A and the gate pad 86. In other words, the resistance wiring 87a has two sides that cross the inner part of the trench resistance structure 20 in a plan view.

[0224] In this embodiment, two sides of the resistive wiring 87a intersect (specifically, are perpendicular to) the third sidewall 21C and the fourth sidewall 21D of the trench resistor structure 20. Of course, the resistive wiring 87a may have one side that intersects the inside of the trench resistor structure 20 and one side that is located outside the trench resistor structure 20.

[0225] Specifically, the resistive wiring 87a is disposed on the buried insulator 26 so as to face the buried resistor 25 at a position different from the gate pad 86. The resistive wiring 87a may have a planar area equal to or larger than the planar area of ​​the buried resistor 25. The resistive wiring 87a is disposed in a region between the first sidewall 21A and the gate pad 86 at a distance from the first sidewall 21A and the gate pad 86 in a plan view.

[0226] The resistive wiring 87a has two sides that cross the inner part of the buried resistor 25 in plan view. Of course, the resistive wiring 87a may have one side that crosses the inner part of the buried resistor 25 and one side that is located outside the buried resistor 25. The buried resistor 25 has a portion that faces the buried resistor 25 across the buried insulator 26, and a portion that faces the insulating region 27 across the buried insulator 26. The two sides of the buried resistor 25 cross (specifically, are perpendicular to) the third sidewall 21C and the fourth sidewall 21D of the resistive trench 23 and are led out from above the buried insulator 26 onto the interlayer insulating film 80.

[0227] In this embodiment, the resistive wiring 87a has a portion located on the bottom wall 22 side of the resistive trench 23 relative to the height position of the active surface 8, and a portion protruding upward relative to the height position of the active surface 8. The resistive wiring 87a penetrates the buried insulator 26 at the portion located on the bottom wall 22 side of the resistive trench 23 and is electrically connected to the buried resistor 25. Specifically, the resistive wiring 87a is connected to the buried resistor 25 via a second resistor opening 90 formed in the buried insulator 26 at a distance from the first resistor opening 89 toward the first sidewall 21A.

[0228] In this embodiment, the second resistor opening 90 is formed in a strip shape extending in the first direction X in a plan view. That is, the second resistor opening 90 extends substantially parallel to the first resistor opening 89. The planar shape and number of the second resistor openings 90 are arbitrary. For example, multiple second resistor openings 90 each having a rectangular shape in a plan view may be formed at intervals in either or both of the first direction X and the second direction Y.

[0229] The plane area of ​​the connection portion of the resistive wiring 87a to the buried resistor 25 is preferably smaller than the plane area of ​​the non-connection portion of the resistive wiring 87a to the buried resistor 25. Of course, the plane area of ​​the connection portion of the resistive wiring 87a to the buried resistor 25 may be larger than the plane area of ​​the non-connection portion of the resistive wiring 87a to the buried resistor 25.

[0230] The opposing area of ​​the resistive wiring 87a (gate wiring 87) to the buried resistor 25 may be larger than the opposing area of ​​the gate pad 86 to the buried resistor 25. Of course, the opposing area of ​​the resistive wiring 87a (gate wiring 87) to the buried resistor 25 may be smaller than the opposing area of ​​the gate pad 86 to the buried resistor 25.

[0231] The first gate wiring 87b is disposed on the interlayer insulating film 80. The first gate wiring 87b is drawn out from the resistance wiring 87a to a region on the third connecting surface 10C side and extends in a line along the first connecting surface 10A and the third connecting surface 10C. The first gate wiring 87b is electrically connected to the trench resistance structure 20 via the resistance wiring 87a in the resistance region 12, and is electrically connected to the plurality of trench gate structures 30 in the active region 13.

[0232] Specifically, the first gate wiring 87b is drawn out in a line shape extending in the first direction X from the resistance wiring 87a (resistance region 12) toward the first dummy region 15A, and covers the plurality of dummy trench structures 50 in the first dummy region 15A with the interlayer insulating film 80 sandwiched therebetween. In this embodiment, the first gate wiring 87b covers the plurality of first dummy trench structures 51 and the plurality of second dummy trench structures 52 with the interlayer insulating film 80 sandwiched therebetween.

[0233] The first gate wiring 87b is routed in a line extending in the second direction Y from the first dummy region 15A toward the active region 13, and intersects (specifically, is perpendicular to) the plurality of trench gate structures 30 in the first active region 13A and the second active region 13B. The first gate wiring 87b is electrically connected to the plurality of gate connection electrode films 49 via the plurality of gate openings 91 formed in the interlayer insulating film 80 in the active region 13. As a result, the first gate wiring 87b is electrically connected to the plurality of trench gate structures 30 via the plurality of gate connection electrode films 49.

[0234] The second gate wiring 87c is disposed on the interlayer insulating film 80. The second gate wiring 87c is drawn from the resistance wiring 87a to a region on the fourth connecting surface 10D side and extends in a line along the first connecting surface 10A and the fourth connecting surface 10D. The second gate wiring 87c is electrically connected to the trench resistance structure 20 via the resistance wiring 87a in the resistance region 12, and is electrically connected to the plurality of trench gate structures 30 in the active region 13.

[0235] The second gate wiring 87c is drawn out in a line shape extending in the first direction X from the resistance wiring 87a (resistance region 12) toward the second dummy region 15B, and covers the plurality of dummy trench structures 50 in the second dummy region 15B with the interlayer insulating film 80 sandwiched therebetween. In this embodiment, the second gate wiring 87c covers the plurality of first dummy trench structures 51 and the plurality of second dummy trench structures 52 with the interlayer insulating film 80 sandwiched therebetween.

[0236] The second gate wiring 87c is routed in a line extending in the second direction Y from the second dummy region 15B toward the active region 13, and intersects (specifically, is perpendicular to) the trench gate structures 30 in the first active region 13A and the third active region 13C. The second gate wiring 87c is electrically connected to the gate connection electrode films 49 via gate openings 91 formed in the interlayer insulating film 80 in the active region 13.

[0237] The second gate wiring 87c is electrically connected to the plurality of trench gate structures 30 via the plurality of gate connection electrode films 49. In this embodiment, the second gate wiring 87c is electrically connected to the plurality of trench gate structures 30 that are electrically connected to the first gate wiring 87b.

[0238] The third gate wiring 87d is disposed on the buried insulator 26 and the interlayer insulating film 80. The third gate wiring 87d is drawn out from the resistance wiring 87a to a region on the second connecting surface 10B side of the gate pad 86, and extends in a line shape in the second direction Y through the region between the resistance wiring 87a and the second connecting surface 10B. The third gate wiring 87d is electrically connected to the trench resistance structure 20 via the resistance wiring 87a in the resistance region 12, and is electrically connected to the plurality of trench gate structures 30 in the active region 13 (first active region 13A).

[0239] Specifically, the third gate wiring 87d includes a line portion 92, a first branch portion 93, and a second branch portion 94. The line portion 92 extends linearly in the second direction Y in the region between the gate pad 86 and the second connecting surface 10B on the interlayer insulating film 80. The line portion 92 has a first end portion on the second connecting surface 10B side and a second end portion on the gate pad 86 side. The first end portion is disposed on the interlayer insulating film 80 at a distance from the second connecting surface 10B toward the gate pad 86.

[0240] The second end is disposed directly above the trench resistor structure 20 and spaced from the gate pad 86 toward the second connection surface 10B. Specifically, the second end is disposed on the buried insulator 26. More specifically, the second end is disposed on the buried insulator 26 and spaced from the buried resistor 25 in a plan view.

[0241] That is, the line portion 92 faces the insulating region 27 across the buried insulator 26, but does not face the buried resistor 25 across the buried insulator 26. In this embodiment, the line portion 92 (second end portion) has a portion located on the bottom wall 22 side of the resistor trench 23 relative to the height position of the active surface 8, and a portion that protrudes upward relative to the height position of the active surface 8.

[0242] The line portion 92 is electrically connected to the plurality of gate connection electrode films 49 through the plurality of gate openings 91 formed in the interlayer insulating film 80 in the active region 13 (first active region 13A). As a result, the line portion 92 is electrically connected to the plurality of trench gate structures 30 through the plurality of gate connection electrode films 49. In this embodiment, the line portion 92 is electrically connected to the plurality of trench gate structures 30 connected to the first gate wiring 87b and the second gate wiring 87c.

[0243] The first branch portion 93 connects the resistance wiring 87a and the line portion 92. Specifically, the first branch portion 93 is drawn out from the second end of the line portion 92 to one side (the third connection surface 10C side) and extends in a strip shape along the gate pad 86. In this embodiment, the first branch portion 93 is formed directly above the trench resistance structure 20.

[0244] Specifically, the first branch portion 93 is disposed only within the region surrounded by the periphery of the resistor trench 23, at a distance inward from the periphery (first to fourth sidewalls 21A to 21D) of the resistor trench 23. In other words, the first branch portion 93 is disposed directly above the trench resistor structure 20, at a distance from the active region 13, the dummy region 15, and the termination region 16, and does not face the active region 13, the dummy region 15, and the termination region 16 in the normal direction Z.

[0245] In this embodiment, the first branch portion 93 is disposed on the buried insulator 26 at a distance from the periphery of the resistive trench 23, and extends in a strip shape along the second sidewall 21B and the third sidewall 21C of the resistive trench 23. The first branch portion 93 is disposed on the buried insulator 26 at a distance from the buried resistor 25 in a plan view. The first branch portion 93 faces the insulating region 27 across the buried insulator 26, but does not face the buried resistor 25 across the buried insulator 26.

[0246] The first branch portion 93 is connected to the resistive wiring 87a in a region on the first sidewall 21A side of the resistive trench 23. That is, the first branch portion 93 is connected to the resistive wiring 87a directly above the insulating region 27. In this embodiment, the first branch portion 93 has a portion located on the bottom wall 22 side of the resistive trench 23 relative to the height position of the active surface 8, and a portion that protrudes upward relative to the height position of the active surface 8.

[0247] Of course, the first branch portion 93 may have a portion extending from above the buried insulator 26 onto the interlayer insulating film 80, and facing a region outside the trench resistor structure 20 in the normal direction Z. In this case, the first branch portion 93 may face at least one of the active region 13, the dummy region 15, and the termination region 16 in the normal direction Z. The first branch portion 93 may also be connected to the first gate wiring 87b, and electrically connected to the resistor wiring 87a via the first gate wiring 87b.

[0248] The second branch portion 94 connects the resistance wiring 87a and the line portion 92. The second branch portion 94 is drawn out from the first end of the line portion 92 to the other side (the fourth connection surface 10D side) and extends in a strip shape along the gate pad 86. In this embodiment, the second branch portion 94 is formed directly above the trench resistance structure 20.

[0249] Specifically, the second branch portion 94 is disposed only within the region surrounded by the periphery of the trench resistance structure 20, at a distance inward from the periphery (first to fourth side walls 21A to 21D) of the trench resistance structure 20. In other words, the second branch portion 94 is disposed directly above the trench resistance structure 20, at a distance from the active region 13, the dummy region 15, and the termination region 16, and does not face the active region 13, the dummy region 15, and the termination region 16 in the normal direction Z.

[0250] In this embodiment, the second branch portion 94 is disposed on the buried insulator 26 at a distance from the periphery of the resistive trench 23, and extends in a strip shape along the second sidewall 21B and the fourth sidewall 21D of the resistive trench 23. The second branch portion 94 is disposed on the buried insulator 26 at a distance from the buried resistor 25 in a plan view. In other words, the second branch portion 94 faces the insulating region 27 across the buried insulator 26, but does not face the buried resistor 25 across the buried insulator 26.

[0251] The second branch portion 94 is connected to the resistive wiring 87a in a region on the first sidewall 21A side of the resistive trench 23. The second branch portion 94 is connected to the resistive wiring 87a directly above the insulating region 27. The second branch portion 94, together with the resistive wiring 87a and the first branch portion 93, surrounds the gate pad 86. In this embodiment, the second branch portion 94 has a portion located on the bottom wall 22 side of the resistive trench 23 relative to the height position of the active surface 8, and a portion that protrudes upward relative to the height position of the active surface 8.

[0252] Of course, the second branch portion 94 may have a portion extending from above the buried insulator 26 onto the interlayer insulating film 80, and facing an area outside the trench resistor structure 20 in the normal direction Z. In this case, the second branch portion 94 may face at least one of the active region 13, the dummy region 15, and the termination region 16 in the normal direction Z. The second branch portion 94 may also be connected to the second gate wiring 87c, and electrically connected to the resistor wiring 87a via the second gate wiring 87c.

[0253] A gate potential VG is applied from the outside to the gate subpad 88. The gate subpad 88 is formed narrower than the gate pad 86 and wider than the gate wiring 87. A part or all of the gate subpad 88 is disposed in a region outside the trench resistance structure 20 in a plan view.

[0254] The gate subpad 88 is disposed on the interlayer insulating film 80 so as to be electrically connected to the gate pad 86 via the trench resistor structure 20. In this embodiment, the gate subpad 88 is disposed at a distance from the gate pad 86 on the third connection surface 10C side, and faces the gate pad 86 in the first direction X.

[0255] The gate subpad 88 is disposed on a portion of the interlayer insulating film 80 that covers the active region 13, spaced apart from the dummy region 15 (first dummy region 15A) in plan view. The gate subpad 88 faces the plurality of trench gate structures 30 and the plurality of first trench source structures 35 across the interlayer insulating film 80. The gate subpad 88 faces the dummy region 15 (first dummy region 15A) in the second direction Y in plan view.

[0256] In this embodiment, the gate subpad 88 is electrically connected to the gate wiring 87. Specifically, the gate subpad 88 is drawn out from the third gate wiring 87d (first branch portion 93) to a region outside the trench resistance structure 20, and has a portion facing the trench resistance structure 20 with the buried resistor 25 interposed therebetween.

[0257] Gate subpad 88 may be located anywhere as long as it is connected to at least one of first to third gate wirings 87b to 87d. Of course, gate subpad 88 may be connected to resistance wiring 87a. Gate subpad 88 may also be located in a region facing at least one of first dummy region 15A, second dummy region 15B, and first termination region 16A.

[0258] The connection between the gate electrode 85 and the trench resistance structure 20 will be described below with reference to Fig. 26. Fig. 26 is an electrical circuit diagram showing the connection between the gate electrode 85 and the trench resistance structure 20. In Fig. 26, the trench gate structure 30 is represented by a circuit symbol indicating a MISFET.

[0259] 26, the gate wiring 87 is electrically connected to the gate pad 86 via a gate resistance R. The gate resistance R is formed by a portion of the trench resistance structure 20 located between the connection portion of the gate pad 86 and the connection portion of the first gate wiring 87b (i.e., a part of the buried resistor 25). The resistance value of the gate resistance R is adjusted by increasing or decreasing the distance between the connection portion of the gate pad 86 and the connection portion of the first gate wiring 87b.

[0260] The gate resistor R (trench resistor structure 20) slows down the switching speed during switching operation to suppress surge currents. In other words, the gate resistor R suppresses noise caused by surge currents. Because the gate resistor R is formed on the first main surface 3 (active surface 8), it is not externally connected to the semiconductor device 1. Therefore, by incorporating the gate resistor R on the first main surface 3, the number of components mounted on the circuit board is reduced.

[0261] Because the gate resistor R includes a trench resistor structure 20 embedded in the thickness direction of the chip 2, the area occupied by the gate resistor R with respect to the first main surface 3 is limited. This prevents a reduction in the area of ​​the active region 13 due to the introduction of the gate resistor R. It also prevents an increase in thickness (size) of the semiconductor device 1 along the thickness direction of the chip 2. The gate wiring 87 does not need to include all of the first to third gate wirings 87b to 87d at the same time, and it is sufficient if it includes at least one of the first to third gate wirings 87b to 87d.

[0262] 1 to 25 again, the semiconductor device 1 includes a source electrode 95 disposed on the interlayer insulating film 80 at a distance from the gate electrode 85. The source electrode 95 is disposed on the interlayer insulating film 80 at a distance from the trench resistor structure 20 in a plan view. The source electrode 95 does not cover the buried insulator 26.

[0263] The source electrode 95 has a resistance value lower than that of the trench resistor structure 20. Specifically, the source electrode 95 has a resistance value lower than that of the buried resistor 25. The source electrode 95 is preferably thicker than the buried resistor 25. It is particularly preferable that the source electrode 95 is thicker than the buried insulator 26. The source electrode 95 is preferably thicker than the interlayer insulating film 80.

[0264] The source electrode 95 preferably has a thickness greater than the first depth D1 described above. The source electrode 95 preferably has a thickness greater than the resistance depth DR (peripheral depth DO, second depth D2) described above. The source electrode 95 may have a thickness of 0.5 μm or more and 10 μm or less. The thickness of the source electrode 95 is preferably 1 μm or more and 5 μm or less. The thickness of the source electrode 95 is preferably approximately equal to the thickness of the gate electrode 85.

[0265] The source electrode 95 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. The source electrode 95 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the source electrode 95 has a layered structure including a Ti film and an Al alloy film (an AlSiCu alloy film in this embodiment) stacked in this order from the chip 2 side. The source electrode 95 may also be referred to as a "source metal."

[0266] In this embodiment, the source electrode 95 includes a first source pad 96, a second source pad 97, a first source sub-pad 98, a second source sub-pad 99, and a source wiring 100. A source potential VS for the main source is applied from the outside to the first source pad 96. The first source pad 96 is disposed in a region between the first gate wiring 87b and the third gate wiring 87d on a portion of the interlayer insulating film 80 that covers the first active region 13A.

[0267] The first source pad 96 faces the plurality of trench gate structures 30 with the interlayer insulating film 80 interposed therebetween. The first source pad 96 is electrically connected to the plurality of first trench source structures 35, the source regions 29, and the plurality of first contact regions 48 via a plurality of source openings 101 formed in the interlayer insulating film 80. The first source pad 96 preferably has a planar area larger than that of the gate pad 86.

[0268] A source potential VS for the main source is externally applied to the second source pad 97. The second source pad 97 is disposed in a region between the second gate wiring 87c and the third gate wiring 87d on a portion of the interlayer insulating film 80 that covers the first active region 13A. The second source pad 97 faces the plurality of trench gate structures 30 with the interlayer insulating film 80 interposed therebetween.

[0269] The second source pad 97 is electrically connected to the plurality of first trench source structures 35, the source region 29, and the plurality of first contact regions 48 via a plurality of source openings 101 formed in the interlayer insulating film 80. The second source pad 97 preferably has a planar area larger than the planar area of ​​the gate pad 86. When the third gate wiring 87d is not formed, the second source pad 97 may be formed integrally with the first source pad 96.

[0270] A source potential VS for source sensing is externally applied to the first source subpad 98. In this embodiment, the first source subpad 98 is disposed in a region between the gate pad 86 and the first gate wiring 87b (third connection surface 10C) on a portion of the interlayer insulating film 80 that covers the second active region 13B. Specifically, the first source subpad 98 is disposed in a region between the first gate wiring 87b and the first branch portion 93 of the third gate wiring 87d.

[0271] The first source subpad 98 has a planar area smaller than that of the first source pad 96 and is formed integrally with the first source pad 96. The planar area of ​​the first source subpad 98 is preferably larger than that of the gate subpad 88. It is particularly preferable that the planar area of ​​the first source subpad 98 be larger than that of the gate pad 86.

[0272] The first source subpad 98 faces the plurality of trench gate structures 30 across the interlayer insulating film 80. The first source subpad 98 is electrically connected to the plurality of first trench source structures 35, the source regions 29, and the plurality of first contact regions 48 via a plurality of source openings 101 formed in the interlayer insulating film 80.

[0273] A source potential VS for source sensing is applied from the outside to the second source subpad 99. In this embodiment, the second source subpad 99 is disposed in a region between the gate pad 86 and the second gate wiring 87c (fourth connecting surface 10D) on a portion of the interlayer insulating film 80 that covers the third active region 13C. Specifically, the second source subpad 99 is disposed in a region between the second gate wiring 87c and the second branch portion 94 of the third gate wiring 87d.

[0274] In this embodiment, the second source subpad 99 has a planar area smaller than that of the second source pad 97 and is formed integrally with the second source pad 97. The planar area of ​​the second source subpad 99 is preferably larger than that of the gate subpad 88. It is particularly preferable that the planar area of ​​the second source subpad 99 be larger than that of the gate pad 86.

[0275] The second source subpad 99 faces the plurality of trench gate structures 30 across the interlayer insulating film 80. The second source subpad 99 is electrically connected to the plurality of first trench source structures 35, the source regions 29, and the plurality of first contact regions 48 via a plurality of source openings 101 formed in the interlayer insulating film 80.

[0276] The total plane area of ​​the first source pad 96, the second source pad 97, the first source sub-pad 98, and the second source sub-pad 99 is preferably 50% or more and 90% or less of the plane area of ​​the first main surface 3. It is particularly preferable that the total plane area be 75% or more of the plane area of ​​the first main surface 3.

[0277] The source wiring 100 transmits the source potential VS applied to the first source pad 96 and the second source pad 97 to other regions. In this embodiment, the source wiring 100 is drawn out from the first source pad 96 and the second source pad 97 so as to be located closer to the outer periphery region 17 than the gate wiring 87.

[0278] The source wiring 100 is drawn out from the active surface 8 side to the outer peripheral surface 9 side, passing through the first to fourth connecting surfaces 10A to 10D. The source wiring 100 is formed in a strip shape extending along the first to fourth connecting surfaces 10A to 10D. In other words, the source wiring 100 faces the sidewall wiring 78 with the interlayer insulating film 80 sandwiched therebetween. In this embodiment, the source wiring 100 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connecting surfaces 10A to 10D, and surrounds the gate wiring 87.

[0279] The source wiring 100 is electrically connected to the sidewall wiring 78 and the outer contact region 76 via an outer opening 102 formed in the interlayer insulating film 80. The outer opening 102 is formed in a strip or ring shape extending along the sidewall wiring 78 and the outer contact region 76. The source potential VS applied to the source wiring 100 is transmitted via the sidewall wiring 78 to the first trench source structure 35, the second trench source structure 40, the first dummy trench structure 51, the second dummy trench structure 52, and the trench termination structure 70.

[0280] The semiconductor device 1 includes an upper insulating film 110 that selectively covers the gate electrode 85, the source electrode 95, and the interlayer insulating film 80 on the first main surface 3. The upper insulating film 110 includes a gate pad opening 111 that exposes an inner portion of the gate pad 86 and a gate subpad opening 112 that exposes an inner portion of the gate subpad 88.

[0281] The upper insulating film 110 covers the periphery of the gate pad 86, the periphery of the gate subpad 88, and the entire gate wiring 87. That is, the upper insulating film 110 covers the buried insulator 26, the periphery of the gate pad 86, the resistive wiring 87a, the first branch portion 93, and the second branch portion 94 within the resistive trench 23.

[0282] The gate pad opening 111 is formed in a rectangular shape in a plan view. The gate subpad opening 112 is also formed in a rectangular shape in a plan view. The gate subpad opening 112 has a plane area smaller than the plane area of ​​the gate pad opening 111.

[0283] The upper insulating film 110 includes a first source pad opening 113 exposing an inner portion of the first source pad 96, a second source pad opening 114 exposing an inner portion of the second source pad 97, a first source subpad opening 115 exposing an inner portion of the first source subpad 98, and a second source subpad opening 116 exposing an inner portion of the second source subpad 99. The upper insulating film 110 covers the peripheral portion of the first source pad 96, the peripheral portion of the second source pad 97, the peripheral portion of the first source subpad 98, the peripheral portion of the second source subpad 99, and the entire area of ​​the source wiring 100.

[0284] The first source pad opening 113 is formed in a rectangular shape in a plan view. The first source pad opening 113 has a planar area larger than the planar area of ​​the gate subpad opening 112. The planar area of ​​the first source pad opening 113 is preferably larger than the planar area of ​​the gate pad opening 111.

[0285] The second source pad opening 114 is formed in a rectangular shape in a plan view. The second source pad opening 114 has a plan area larger than the plan area of ​​the gate subpad opening 112. The plan area of ​​the second source pad opening 114 is preferably larger than the plan area of ​​the gate pad opening 111. The plan area of ​​the second source pad opening 114 is preferably approximately equal to the plan area of ​​the first source pad opening 113.

[0286] The first source subpad opening 115 is formed in a rectangular shape in a plan view. The first source subpad opening 115 has a planar area smaller than that of the first source pad opening 113. The planar area of ​​the first source subpad opening 115 is preferably larger than that of the gate subpad opening 112. In this embodiment, the planar area of ​​the first source subpad opening 115 is larger than that of the gate pad opening 111. Of course, the planar area of ​​the first source subpad opening 115 may be smaller than that of the gate pad opening 111.

[0287] The second source subpad opening 116 is formed in a rectangular shape in a plan view. The second source subpad opening 116 has a planar area smaller than that of the second source pad opening 114. The planar area of ​​the second source subpad opening 116 is preferably larger than that of the gate subpad opening 112. In this embodiment, the planar area of ​​the second source subpad opening 116 is larger than that of the gate pad opening 111. Of course, the planar area of ​​the second source subpad opening 116 may be smaller than that of the gate pad opening 111. The planar area of ​​the second source subpad opening 116 is preferably approximately equal to that of the first source subpad opening 115.

[0288] If source sensing using the first source subpad 98 is not required, a first source pad opening 113 may be formed to expose both the first source pad 96 and the first source subpad 98. If source sensing using the second source subpad 99 is not required, a second source pad opening 114 may be formed to expose both the second source pad 97 and the second source subpad 99.

[0289] The upper insulating film 110 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2, and defines a dicing street 117 between itself and the periphery of the chip 2. The dicing street 117 is formed in a band shape extending along the periphery of the chip 2 in a plan view. In this embodiment, the dicing street 117 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8 in a plan view. In this embodiment, the dicing street 117 exposes the interlayer insulating film 80.

[0290] Of course, when the main surface insulating film 18 and the interlayer insulating film 80 expose the outer peripheral surface 9, the dicing street 117 may also expose the outer peripheral surface 9. The dicing street 117 may have a width of 1 μm or more and 200 μm or less. The width of the dicing street 117 is the width in a direction perpendicular to the extension direction of the dicing street 117. The width of the dicing street 117 is preferably 5 μm or more and 50 μm or less.

[0291] The upper insulating film 110 preferably has a thickness greater than the thickness of the gate electrode 85 and the thickness of the source electrode 95. The thickness of the upper insulating film 110 is preferably less than the thickness of the chip 2. The thickness of the upper insulating film 110 may be 3 μm or more and 35 μm or less. The thickness of the upper insulating film 110 is preferably 25 μm or less.

[0292] In this embodiment, the upper insulating film 110 has a laminated structure including an inorganic insulating film 120 and an organic insulating film 121 laminated in this order from the chip 2 side. The upper insulating film 110 only needs to include at least one of the inorganic insulating film 120 and the organic insulating film 121, and does not necessarily need to include both the inorganic insulating film 120 and the organic insulating film 121 at the same time.

[0293] The inorganic insulating film 120 selectively covers the gate electrode 85, the source electrode 95, and the interlayer insulating film 80, and defines a portion of the gate pad opening 111, a portion of the gate subpad opening 112, a portion of the first source pad opening 113, a portion of the second source pad opening 114, a portion of the first source subpad opening 115, a portion of the second source subpad opening 116, and a portion of the dicing street 117.

[0294] The inorganic insulating film 120 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film 120 preferably includes an insulating material different from that of the interlayer insulating film 80. The inorganic insulating film 120 preferably includes a silicon nitride film. The inorganic insulating film 120 preferably has a thickness less than that of the interlayer insulating film 80. The thickness of the inorganic insulating film 120 may be 0.1 μm or more and 5 μm or less.

[0295] The organic insulating film 121 selectively covers the inorganic insulating film 120 and defines a portion of the gate pad opening 111, a portion of the gate subpad opening 112, a portion of the first source pad opening 113, a portion of the second source pad opening 114, a portion of the first source subpad opening 115, a portion of the second source subpad opening 116, and a portion of the dicing street 117.

[0296] The organic insulating film 121 may expose the inorganic insulating film 120 at the wall surface of the gate pad opening 111. The organic insulating film 121 may expose the inorganic insulating film 120 at the wall surface of the gate subpad opening 112. The organic insulating film 121 may expose the inorganic insulating film 120 at the wall surface of the first source pad opening 113. The organic insulating film 121 may expose the inorganic insulating film 120 at the wall surface of the second source pad opening 114.

[0297] The organic insulating film 121 may expose the inorganic insulating film 120 at the wall surface of the first source subpad opening 115. The organic insulating film 121 may expose the inorganic insulating film 120 at the wall surface of the second source subpad opening 116. The organic insulating film 121 may expose the inorganic insulating film 120 at the wall surface of the dicing street 117. Of course, the organic insulating film 121 may cover the entire inorganic insulating film 120 so that the inorganic insulating film 120 is not exposed.

[0298] The organic insulating film 121 is preferably made of a resin film other than a thermosetting resin. The organic insulating film 121 may be made of a light-transmitting resin or a transparent resin. The organic insulating film 121 may be made of a negative-type or positive-type photosensitive resin film. The organic insulating film 121 is preferably made of a polyimide film, a polyamide film, or a polybenzoxazole film. In this embodiment, the organic insulating film 121 includes a polybenzoxazole film.

[0299] The organic insulating film 121 preferably has a thickness greater than that of the inorganic insulating film 120. The thickness of the organic insulating film 121 preferably exceeds that of the interlayer insulating film 80. The thickness of the organic insulating film 121 particularly preferably exceeds that of the gate electrode 85 and that of the source electrode 95. The thickness of the organic insulating film 121 may be 3 μm or more and 30 μm or less. The thickness of the organic insulating film 121 is preferably 20 μm or less.

[0300] The semiconductor device 1 includes a drain electrode 130 covering the second main surface 4. The drain electrode 130 forms ohmic contact with the second semiconductor region 7 exposed from the second main surface 4. The drain electrode 130 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. A breakdown voltage that can be applied between the source electrode 95 and the drain electrode 130 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.

[0301] As described above, the semiconductor device 1 includes the chip 2, the trench resistance structure 20, the gate pad 86, and the gate wiring 87. The chip 2 has a first main surface 3. The trench resistance structure 20 is formed on the first main surface 3. The gate pad 86 has a lower resistance value than the trench resistance structure 20, and is arranged on the trench resistance structure 20 so as to be electrically connected to the trench resistance structure 20. The gate wiring 87 has a lower resistance value than the trench resistance structure 20, and is arranged on the trench resistance structure 20 so as to be electrically connected to the gate pad 86 via the trench resistance structure 20.

[0302] According to this structure, the trench resistance structure 20 that serves as the gate resistance R is incorporated within the chip 2, which makes it possible to suppress an increase in size (thickness) of the device along the normal direction Z of the first main surface 3. Furthermore, since the gate pad 86 and the gate wiring 87 are disposed on the trench resistance structure 20, the area occupied by the trench resistance structure 20, the gate pad 86, and the gate wiring 87 relative to the first main surface 3 in plan view can be reduced. Therefore, in a configuration including the gate resistance R, it is possible to provide a semiconductor device 1 that has a novel layout that contributes to miniaturization.

[0303] The gate pad 86 preferably has a planar area smaller than the planar area of ​​the trench resistance structure 20. With this structure, the gate pad 86 can be arranged in a region surrounded by the wall surfaces of the trench resistance structure 20 at a distance from the wall surfaces of the trench resistance structure 20 in a plan view. Furthermore, since the size of the gate pad 86 can be prevented from increasing and the location of the gate pad 86 can be limited to directly above the trench resistance structure 20, restrictions on the design rules resulting from the layout of the gate pad 86 (for example, restrictions on the layout of structures formed on the chip 2 side) can be alleviated.

[0304] The gate wiring 87 preferably extends in a strip shape narrower than the trench resistance structure 20 in a plan view. The gate wiring 87 preferably has two sides that cross the inner part of the trench resistance structure 20 in a plan view. These structures can prevent the gate wiring 87 from becoming large, and therefore can alleviate design rule restrictions resulting from the layout of the gate wiring 87 (for example, restrictions on the layout of structures formed on the chip 2 side).

[0305] The trench resistor structure 20 preferably includes a resistor trench 23 formed in the first main surface 3, a resistor insulating film 24 covering the wall surfaces of the resistor trench 23, and a buried resistor 25 disposed in the resistor trench 23 across the resistor insulating film 24. In this case, the gate pad 86 preferably has a lower resistance value than the buried resistor 25 and is electrically connected to the buried resistor 25. Furthermore, the gate wiring 87 preferably has a lower resistance value than the buried resistor 25 and is electrically connected to the buried resistor 25.

[0306] The buried resistor 25 is preferably disposed within the inner portion of the resistor trench 23 at a distance from the periphery of the resistor trench 23. With this structure, an insulating region 27 where the resistor insulating film 24 is exposed can be defined between the buried resistor 25 and the periphery of the resistor trench 23. With this structure, the buried resistor 25 (trench resistor structure 20) can be appropriately electrically isolated from the chip 2 and other structures.

[0307] This reduces the electrical influence of the gate resistor R on other structures, and reduces the electrical influence of other structures on the gate resistor R. For example, it is possible to suppress malfunction of the channel caused by the buried resistor 25. Therefore, the gate resistor R can be appropriately incorporated into the chip 2.

[0308] It is particularly preferable that the buried resistor 25 be disposed within the inner portion of the resistor trench 23 at a distance from the entire periphery of the resistor trench 23. This structure allows the insulating region 27 to be defined so as to surround the buried resistor 25 in a ring shape in a plan view. The planar area of ​​the insulating region 27 is preferably equal to or larger than the planar area of ​​the buried resistor 25.

[0309] The buried resistor 25 may be unevenly located on the peripheral edge side of the resistor trench 23 with respect to the center of the resistor trench 23. With this structure, the connection position of the gate pad 86 to the buried resistor 25 and the connection position of the gate wiring 87 to the buried resistor 25 can be appropriately adjusted. In other words, the restrictions on the design rules imposed on the buried resistor 25, the gate pad 86, and the gate wiring 87 can be relaxed.

[0310] The gate pad 86 preferably has a planar area equal to or larger than the planar area of ​​the buried resistor 25. With this structure, the gate potential VG can be appropriately applied to the gate pad 86 from the outside. The gate wiring 87 is preferably formed in a strip shape narrower than the buried resistor 25 in a planar view. The gate wiring 87 preferably has two sides that cross the inner part of the buried resistor 25 in a planar view. With these structures, it is possible to appropriately prevent the gate wiring 87 from becoming large.

[0311] The buried resistor 25 preferably has a thickness smaller than the depth of the resistor trench 23, and is disposed in the resistor trench 23 at a distance from the height position of the first main surface 3 toward the bottom wall 22 of the resistor trench 23. With this structure, the buried resistor 25 can be accommodated in the resistor trench 23, thereby preventing the buried resistor 25 from becoming large due to its thickness.

[0312] In such a structure, the gate pad 86 is preferably connected to the embedded resistor 25 in a region on the bottom wall 22 side of the resistor trench 23 relative to the height position of the first main surface 3. In this case, the gate pad 86 preferably has a portion that protrudes above the first main surface 3. With this structure, the gate potential VG can be appropriately applied to the gate pad 86 from outside.

[0313] Furthermore, the gate wiring 87 is preferably connected to the buried resistor 25 in a region on the bottom wall 22 side of the resistive trench 23 with respect to the height position of the first main surface 3. In this case, the gate wiring 87 may have a portion that protrudes above the first main surface 3.

[0314] The trench resistor structure 20 preferably includes a buried insulator 26 that covers the buried resistor 25 in the resistor trench 23. With this structure, the buried insulator 26 can appropriately insulate and protect the buried resistor 25 from other structures. In this case, the gate pad 86 is preferably disposed on the buried insulator 26 so as to penetrate the buried insulator 26 and be electrically connected to the buried resistor 25. Furthermore, the gate wiring 87 is preferably disposed on the buried insulator 26 so as to penetrate the buried insulator 26 and be electrically connected to the buried resistor 25.

[0315] The semiconductor device 1 preferably includes an interlayer insulating film 80 covering the first main surface 3 so as to be connected to the buried insulator 26. In this case, the interlayer insulating film 80 is preferably connected to the buried insulator 26. According to this structure, the buried insulator 26 and the interlayer insulating film 80 can protect the resistive trench 23 and the buried resistor 25.

[0316] The semiconductor device 1 preferably includes a dummy trench structure 50 formed on the first main surface 3 adjacent to the trench resistance structure 20 and spaced apart from the trench resistance structure 20. With this structure, the dummy trench structure 50 can be used to alleviate the electric field in the vicinity of the trench resistance structure 20. A potential different from that of the trench resistance structure 20 is preferably applied to the dummy trench structure 50. In other words, it is preferable that the dummy trench structure 50 does not contribute to channel control. In this case, a source potential VS is preferably applied to the dummy trench structure 50.

[0317] In this case, the gate wiring 87 may overlap the dummy trench structure 50 in plan view. With this structure, the arrangement location of the gate wiring 87 can be limited to directly above the dummy trench structure 50, thereby alleviating design rule restrictions (e.g., restrictions on the layout of structures formed on the chip 2 side) resulting from the layout of the gate wiring 87. It is preferable that a plurality of dummy trench structures 50 are formed on the first main surface 3. With this structure, the plurality of dummy trench structures 50 can be used to alleviate the noise in the vicinity of the trench resistance structure 20.

[0318] The semiconductor device 1 preferably includes a trench gate structure 30 formed on the first main surface 3 adjacent to the trench resistance structure 20 at a distance from the trench resistance structure 20. In this case, the gate wiring 87 is preferably electrically connected to the trench gate structure 30. This structure allows the trench resistance structure 20 (gate resistance R) to be electrically interposed between the gate pad 86 and the trench gate structure 30.

[0319] The semiconductor device 1 preferably includes a first trench source structure 35 formed on the first main surface 3 adjacent to the trench resistor structure 20 and the trench gate structure 30. The trench resistor structure 20 may be formed shallower than the trench resistor structure 20. The first trench source structure 35 may be formed deeper than the trench gate structure 30. The first trench source structure 35 may be formed to a depth approximately equal to that of the trench resistor structure 20.

[0320] Such a structure is effective in suppressing electric field concentration in the trench resistance structure 20 and improving the breakdown voltage (breakdown voltage). In such a structure, the multiple dummy trench structures 50 preferably include a first dummy trench structure 51 formed relatively shallowly in correspondence with the trench gate structure 30, and a second dummy trench structure 52 formed relatively deep in correspondence with the trench resistance structure 20.

[0321] The semiconductor device 1 preferably includes an n-type first semiconductor region 6 formed in a surface layer portion of the first main surface 3. In this case, the trench resistance structure 20 is formed on the first main surface 3 so as to be located within the first semiconductor region 6. In such a structure, the semiconductor device 1 preferably includes a p-type first well region 28 formed in a region along the trench resistance structure 20 within the first semiconductor region 6 so as to form a p-n junction with the first semiconductor region 6. With this structure, the withstand voltage (e.g., breakdown voltage) can be improved by a depletion layer that spreads from the first well region 28.

[0322] The semiconductor device 1 may include an active surface 8 formed in an inner portion of the first main surface 3, an outer peripheral surface 9 formed on the periphery of the first main surface 3 so as to be recessed from the active surface 8 in the thickness direction of the chip 2, and an active plateau 11 defined on the first main surface 3 by first to fourth connection surfaces 10A to 10D connecting the active surface 8 and the outer peripheral surface 9. In this case, the trench resistor structure 20 is preferably formed on the active surface 8.

[0323] The semiconductor device 1 may include a sidewall structure disposed on the outer peripheral surface 9 so as to cover at least one of the first to fourth connection surfaces 10A to 10D. The first trench source structure 35 may be exposed from at least one of the first to fourth connection surfaces 10A to 10D. In this case, the sidewall structure may be made of a sidewall wiring 78 electrically connected to the first trench source structure 35.

[0324] According to this structure, the sidewall wiring 78 can apply a potential different from the potential for the trench resistance structure 20 to the first trench source structure 35 from the outer peripheral surface 9 side. Of course, the dummy trench structure 50 may be exposed from at least one of the first to fourth connecting surfaces 10A to 10D, and the sidewall wiring 78 may be electrically connected to the dummy trench structure 50.

[0325] The semiconductor device 1 may include a gate subpad 88 arranged on the first main surface 3 so as to have a lower resistance value than the trench resistor structure 20 and to be electrically connected to the gate pad 86 via the trench resistor structure 20. With this structure, the resistance value between the gate pad 86 and the gate wiring 87 can be indirectly measured by measuring the resistance value between the gate pad 86 and the gate subpad 88.

[0326] The gate subpad 88 is preferably disposed in a region outside the trench resistor structure 20 in a plan view. The gate subpad 88 is preferably formed to be narrower than the gate pad 86 and wider than the gate wiring 87. The gate subpad 88 may be connected to the gate wiring 87.

[0327] Semiconductor device 1 may include a p-type outer well region 75 formed in a surface layer portion of first main surface 3 in peripheral region 17. With this structure, outer well region 75 can alleviate the electric field in peripheral region 17. Semiconductor device 1 may include at least one p-type field region 77 formed in a surface layer portion of first main surface 3 in peripheral region 17. With this structure, field region 77 can alleviate the electric field in peripheral region 17.

[0328] The chip 2 preferably includes a single crystal of a wide bandgap semiconductor. The single crystal of a wide bandgap semiconductor is effective in improving electrical characteristics. Furthermore, the single crystal of a wide bandgap semiconductor has a relatively high hardness, which suppresses deformation of the chip 2, while enabling the chip 2 to be thinned and have an increased planar area.

[0329] Thinning the chip 2 and increasing its planar area are also effective in improving electrical characteristics. For example, the chip 2 may have a first main surface 3 having an area of ​​1 mm square or more in a plan view. For example, the chip 2 may have a thickness of 200 μm or less. It is preferable that the chip 2 have a thickness of 100 μm or less in a cross-sectional view.

[0330] Various modified examples applicable to the embodiment will be described below with reference to FIGS. 27 to 32. FIG. 27 is a cross-sectional view showing a trench resistance structure 20 according to a first modified example. The trench resistance structure 20 according to the above-described embodiment includes an insulating region 27. In contrast, the trench resistance structure 20 according to the first modified example does not include an insulating region 27. In other words, the buried resistor 25 covers the entire bottom wall 22 of the resistor trench 23 so as to be connected to the resistor insulating film 24 at the periphery of the resistor trench 23.

[0331] 28 is a cross-sectional view showing a trench resistor structure 20 according to a second modification. The trench resistor structure 20 according to the second modification has a configuration in which the buried resistor 25 in the trench resistor structure 20 according to the first modification is thickened. In this configuration, the buried resistor 25 has a resistor end face 25a located closer to the active surface 8 than the intermediate portion in the depth direction of the resistor trench 23. In this case, the end face of the gate buried electrode 33 may be formed at a height position substantially equal to the resistor end face 25a of the buried resistor 25. Furthermore, the end face of the first source buried electrode 38 may be formed at a height position substantially equal to the resistor end face 25a of the buried resistor 25.

[0332] 29 is a cross-sectional view showing a trench resistor structure 20 according to a third modification. The trench resistor structure 20 according to the above-described embodiment has a depth approximately equal to the circumferential depth DO of the circumferential surface 9. In contrast, the trench resistor structure 20 according to the third modification has a resistor depth DR that is less than the circumferential depth DO. In this case, the resistor depth DR may be 0.1 μm or more and 3 μm or less. Preferably, the resistor depth DR is 0.5 μm or more and 1.5 μm or less.

[0333] In this case, the trench gate structure 30 may have a first depth D1 that is approximately equal to the resistance depth DR. Also, the first trench source structure 35 may have a second depth D2 that is greater than the resistance depth DR. In this embodiment, the bottom of the second well region 45 is formed at a depth that is approximately equal to the bottom of the first well region 28. In this embodiment, the bottom of the third well region 46 is formed closer to the bottom of the first semiconductor region 6 than the bottom of the first well region 28.

[0334] 30 is a cross-sectional view showing a trench resistor structure according to a fourth modification. The trench resistor structure 20 according to the fourth modification has a configuration in which the insulating region 27 in the third modification is eliminated. That is, the buried resistor 25 covers the entire bottom wall 22 of the resistor trench 23 so as to be connected to the resistor insulating film 24 at the periphery of the resistor trench 23.

[0335] In this case, the buried resistor 25 may have a resistor end face 25a located closer to the active surface 8 than the intermediate portion in the depth direction of the resistor trench 23. The end face of the gate buried electrode 33 may be formed at a height position substantially equal to that of the resistor end face 25a of the buried resistor 25. Furthermore, the end face of the first source buried electrode 38 may be formed at a height position substantially equal to that of the resistor end face 25a of the buried resistor 25.

[0336] 31 is a cross-sectional view showing a chip 2 according to a first modification. Referring to Fig. 31, the semiconductor device 1 may include a second semiconductor region 7 inside the chip 2, the second semiconductor region 7 having a thickness smaller than that of the first semiconductor region 6. In other words, the chip 2 may include an epitaxial layer that is thicker than the semiconductor substrate.

[0337] 32 is a cross-sectional view showing a chip 2 according to a second modification. Referring to FIG. 32, the semiconductor device 1 may include only the first semiconductor region 6 without the second semiconductor region 7 inside the chip 2. In this case, the first semiconductor region 6 is exposed from the first main surface 3, the second main surface 4, and the first to fourth side surfaces 5A to 5D of the chip 2. That is, in this embodiment, the chip 2 does not have a semiconductor substrate and has a single-layer structure made of an epitaxial layer.

[0338] The above-described embodiments may be implemented in other forms. In the above-described embodiments, the "first conductivity type" is "n-type" and the "second conductivity type" is "p-type." However, in the above-described embodiments, the "first conductivity type" may be "p-type" and the "second conductivity type" may be "n-type." A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and the accompanying drawings.

[0339] In the above-described embodiment, the n-type second semiconductor region 7 has been described. However, a p-type second semiconductor region 7 may also be employed. In this case, an IGBT (Insulated Gate Bipolar Transistor) is formed instead of the MISFET. In this case, in the above description, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT. The p-type second semiconductor region 7 may be an impurity region containing p-type impurities introduced into a surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0340] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following clauses may be replaced with "wide bandgap semiconductor device," "SiC semiconductor device," "semiconductor switching device," "SiC-MISFET," etc., as necessary.

[0341] [A1] A semiconductor device (1) including: a chip (2) having a main surface (3); a trench resistance structure (20) formed on the main surface (3); a gate pad (86) having a lower resistance value than the trench resistance structure (20) and arranged on the trench resistance structure (20) so as to be electrically connected to the trench resistance structure (20); and gate wiring (87, 87a-87d) having a lower resistance value than the trench resistance structure (20) and arranged on the trench resistance structure (20) so as to be electrically connected to the gate pad (86) via the trench resistance structure (20).

[0342] [A2] The semiconductor device (1) according to A1, wherein the gate pad (86) has a planar area less than the planar area of ​​the trench resistor structure (20).

[0343] [A3] The semiconductor device (1) described in A1 or A2, wherein the gate pad (86) is arranged within a region surrounded by the wall surfaces of the trench resistance structure (20) at a distance from the wall surfaces of the trench resistance structure (20) in a planar view.

[0344] [A4] The semiconductor device (1) according to any one of A1 to A3, wherein the gate wiring (87, 87a to 87d) is formed in a strip shape narrower than the trench resistance structure (20) in a plan view.

[0345] [A5] The semiconductor device (1) according to A4, wherein the gate wiring (87, 87a to 87d) has two sides that cross the inner part of the trench resistance structure (20) in a plan view.

[0346] [A6] The semiconductor device (1) described in any one of A1 to A5, wherein the trench resistor structure (20) includes a trench (23) formed in the main surface (3), an insulating film (24) covering the wall surface of the trench (23), and a buried resistor (25) arranged in the trench (23) across the insulating film (24), the gate pad (86) has a resistance value lower than the buried resistor (25) and is electrically connected to the buried resistor (25), and the gate wiring (87, 87a to 87d) has a resistance value lower than the buried resistor (25) and is electrically connected to the buried resistor (25).

[0347] [A7] The semiconductor device (1) described in A6, wherein the buried resistor (25) is disposed within the inner portion of the trench (23) at a distance from the periphery (21A to 21D) of the trench (23), and defines an insulating region (27) exposing the insulating film (24) between the buried resistor (25) and the periphery (21A to 21D) of the trench (23).

[0348] [A8] The semiconductor device (1) according to A7, wherein the gate pad (86) has a planar area equal to or greater than the planar area of ​​the buried resistor (25).

[0349] [A9] The semiconductor device (1) according to A7 or A8, wherein the gate wiring (87, 87a to 87d) is formed in a strip shape narrower than the embedded resistor (25) in plan view.

[0350] [A10] The semiconductor device (1) according to any one of A7 to A9, wherein the gate wiring (87, 87a to 87d) has two sides that cross the buried resistor (25) within the trench (23) in a plan view.

[0351] [A11] The semiconductor device (1) described in any one of A6 to A10, wherein the buried resistor (25) has a thickness smaller than the depth of the trench (23) and is arranged in the trench (23) at a distance from a height position of the main surface (3) toward the bottom wall (22) of the trench (23), the gate pad (86) is connected to the buried resistor (25) in a region on the bottom wall (22) side of the trench (23) relative to a height position of the main surface (3), and the gate wiring (87, 87a to 87d) is connected to the buried resistor (25) in a region on the bottom wall (22) side of the trench (23) relative to a height position of the main surface (3).

[0352] [A12] The semiconductor device (1) according to A11, wherein the gate pad (86) has a portion that protrudes above the main surface (3).

[0353] [A13] The semiconductor device (1) according to A11 or A12, wherein the trench resistor structure (20) includes a buried insulator (26) covering the buried resistor (25) within the trench (23), the gate pad (86) is disposed on the buried insulator (26) so as to penetrate the buried insulator (26) and be electrically connected to the buried resistor (25), and the gate wiring (87, 87a to 87d) is disposed on the buried insulator (26) so as to penetrate the buried insulator (26) and be electrically connected to the buried resistor (25).

[0354] [A14] The semiconductor device (1) according to A13, further comprising an interlayer insulating film (80) covering the main surface (3) so as to be connected to the buried insulator (26).

[0355] [A15] The semiconductor device (1) according to any one of A1 to A14, further comprising a dummy trench structure (50-52) formed on the main surface (3) at a distance from the trench resistance structure (20) so as to be adjacent to the trench resistance structure (20), and to which a potential different from that of the trench resistance structure (20) is applied.

[0356] [A16] The semiconductor device (1) according to any one of A1 to A15, further comprising a trench gate structure (30) formed on the main surface (3) adjacent to the trench resistance structure (20) and spaced apart from the trench resistance structure (20), and the gate wiring (87, 87a to 87d) is electrically connected to the trench gate structure (30).

[0357] [A17] The semiconductor device (1) according to A16, further comprising a trench source structure (35) formed on the main surface (3) adjacent to the trench resistor structure (20) and the trench gate structure (30).

[0358] [A18] The semiconductor device (1) according to any one of A1 to A17, further comprising: a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); the trench resistance structure (20) formed on the main surface (3) so as to be located within the semiconductor region (6); and a well region (28) of a second conductivity type (p-type) formed in the semiconductor region (6) in a region along the trench resistance structure (20) so as to form a pn junction with the semiconductor region (6).

[0359] [A19] A semiconductor device (1) according to any one of A1 to A18, further comprising a first surface portion (8) formed in the inner portion of the main surface (3), a second surface portion (9) formed on the periphery of the main surface (3) so as to be recessed from the first surface portion (8) in the thickness direction of the chip (2), and a plateau (11) defined on the main surface (3) by connection surface portions (10A to 10D) connecting the first surface portion (8) and the second surface portion (9), and the trench resistance structure (20) is formed on the first surface portion (8).

[0360] [A20] A semiconductor device (1) according to any one of A1 to A19, further comprising a gate subpad (88) having a resistance value lower than that of the trench resistor structure (20) and arranged on the main surface (3) so as to be electrically connected to the gate pad (86) via the trench resistor structure (20).

[0361] Although the embodiments have been described in detail above, these are merely specific examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiments.

[0362] REFERENCE SIGNS LIST 1 semiconductor device 2 chip 3 first main surface 6 first semiconductor region 8 active surface (first surface portion) 9 outer peripheral surface (second surface portion) 10A first connection surface (connection surface portion) 10B second connection surface (connection surface portion) 10C third connection surface (connection surface portion) 10D fourth connection surface (connection surface portion) 11 active plateau 20 trench resistor structure 21A first side wall (periphery) of trench resistor structure 21B second side wall (periphery) of trench resistor structure 21C third side wall (periphery) of trench resistor structure 21D fourth side wall (periphery) of trench resistor structure 22 bottom wall of trench resistor structure 23 resistor trench 24 resistor insulating film 25 buried resistor 26 buried insulator 27 insulating region 28 first well region 30 trench gate structure 35 first trench source structure 50 Dummy trench structure 51 First dummy trench structure 52 Second dummy trench structure 80 Interlayer insulating film 86 Gate pad 87 Gate wiring 87a Resistance wiring (gate wiring) 87b First gate wiring (gate wiring) 87c Second gate wiring (gate wiring) 87d Third gate dashed line (gate wiring) 88 Gate subpad

Claims

1. a chip having a major surface; a trench resistor structure formed on the principal surface; a gate pad having a lower resistance value than the trench resistor structure and disposed on the trench resistor structure so as to be electrically connected to the trench resistor structure; a gate wiring having a resistance value lower than that of the trench resistance structure and arranged on the trench resistance structure so as to be electrically connected to the gate pad via the trench resistance structure.

2. The semiconductor device as described in claim 1, wherein the gate wiring has two sides that cross the inner part of the trench resistor structure in a planar view.

3. The trench resistor structure includes a trench formed in the main surface, an insulating film covering a wall surface of the trench, and a buried resistor disposed in the trench with the insulating film therebetween; the gate pad has a resistance value lower than that of the buried resistor and is electrically connected to the buried resistor; 2. The semiconductor device according to claim 1, wherein said gate wiring has a resistance value lower than that of said buried resistor and is electrically connected to said buried resistor.

4. A semiconductor device as described in claim 3, wherein the buried resistor is positioned within an inner portion of the trench at a distance from the periphery of the trench, and defines an insulating region between the buried resistor and the periphery of the trench, exposing the insulating film.

5. A semiconductor device as described in claim 4, wherein the gate pad has a planar area greater than or equal to the planar area of ​​the buried resistor.

6. The semiconductor device described in claim 4, wherein the gate wiring is formed in a band shape narrower than the buried resistor when viewed in a plan view.

7. The semiconductor device described in Claim 4, wherein the gate wiring has two sides that cross the buried resistor within the trench in a plan view.

8. The buried resistor has a thickness smaller than the depth of the trench and is disposed in the trench at a distance from the height position of the main surface to a bottom wall side of the trench; the gate pad is connected to the buried resistor in a region on a bottom wall side of the trench with respect to a height position of the main surface; 4. The semiconductor device according to claim 3, wherein said gate wiring is connected to said buried resistor in a region on a bottom wall side of said trench with respect to a height position of said main surface.

9. The semiconductor device described in Claim 8, wherein the gate pad has a portion that protrudes upward from the main surface.

10. The trench resistor structure, comprising: a buried insulator covering the buried resistor within the trench; the gate pad is disposed on the buried insulator so as to penetrate the buried insulator and be electrically connected to the buried resistor; 9. The semiconductor device according to claim 8, wherein said gate wiring is disposed on said buried insulator so as to penetrate said buried insulator and be electrically connected to said buried resistor.

11. The semiconductor device described in claim 10, further comprising an interlayer insulating film covering the main surface so as to be connected to the buried insulator.

12. A semiconductor device as described in claim 1, further comprising a gate subpad having a lower resistance value than the trench resistor structure and arranged on the main surface so as to be electrically connected to the gate pad via the trench resistor structure.

13. 13. The semiconductor device according to claim 1, wherein the gate pad has a planar area smaller than a planar area of ​​the trench resistor structure.

14. 13. The semiconductor device according to claim 1, wherein the gate pad is arranged in a region surrounded by the wall surfaces of the trench resistance structure and spaced apart from the wall surfaces of the trench resistance structure in a plan view.

15. 13. The semiconductor device according to claim 1, wherein the gate wiring is formed in a strip shape narrower than the trench resistor structure in a plan view.

16. The semiconductor device according to any one of claims 1 to 12, further comprising a dummy trench structure formed on the main surface at a distance from the trench resistance structure so as to be adjacent to the trench resistance structure, and to which a potential different from that of the trench resistance structure is applied.

17. a trench gate structure formed on the main surface adjacent to the trench resistance structure and spaced apart from the trench resistance structure; 13. The semiconductor device according to claim 1, wherein the gate wiring is electrically connected to the trench gate structure.

18. The semiconductor device according to claim 17 , further comprising a trench source structure formed in said main surface adjacent to said trench resistor structure and said trench gate structure.

19. a first conductivity type semiconductor region formed in a surface layer portion of the main surface; the trench resistor structure formed on the main surface so as to be located within the semiconductor region; The semiconductor device according to any one of claims 1 to 12, further comprising: a well region of a second conductivity type formed in the semiconductor region in a region along the trench resistor structure so as to form a pn junction with the semiconductor region.

20. a first surface portion formed on an inner portion of the main surface, a second surface portion formed on a peripheral portion of the main surface so as to be recessed from the first surface portion in a thickness direction of the chip, and a plateau defined on the main surface by a connection surface portion connecting the first surface portion and the second surface portion, 13. The semiconductor device according to claim 1, wherein the trench resistor structure is formed in the first surface portion.