Semiconductor device

Abstract

A semiconductor device including: a chip having a major surface; a gate resistor including a trench resistive structure formed on the major surface; a gate pad having a lower resistance value than the trench resistive structure and disposed over the trench resistive structure so as to be electrically connected to the trench resistive structure; and gate wiring having a lower resistance value than the trench resistive structure and disposed over the major surface so as to be electrically connected to the gate pad via the trench resistive structure.

Description

Semiconductor Devices

[0001] This application claims priority based on Japanese Patent Application No. 2022-061314 filed on March 31, 2022, and Japanese Patent Application No. 2022-061316 filed on March 31, 2022, the entire contents of which are incorporated herein by reference. The present invention relates to a semiconductor device.

[0002] Japanese Patent Application Laid-Open No. 2006-124499 discloses a semiconductor device including a semiconductor substrate, a plurality of trench structures, and a gate pad portion. The plurality of trench structures are formed on the surface of the semiconductor substrate. The gate pad portion is disposed on the semiconductor substrate so as to cover the plurality of trench structures.

[0003] US Patent Application Publication No. 2017 / 0040423

[0004] One embodiment provides a semiconductor device having a novel layout.

[0005] One embodiment provides a semiconductor device including: a chip having a main surface; a gate resistor including a trench resistance structure formed on the main surface; a gate pad having a resistance value lower than that of the trench resistance structure and arranged on the main surface to be electrically connected to the trench resistance structure; and a gate wiring having a resistance value lower than that of the trench resistance structure and arranged on the main surface to be electrically connected to the gate pad via the trench resistance structure.

[0006] One embodiment provides a semiconductor device including: a chip having a main surface; a first groove structure formed on the main surface; a second groove structure formed on the main surface adjacent to the first groove structure in a first direction; a third groove structure formed on the main surface adjacent to the first groove structure in a second direction perpendicular to the first direction; a fourth groove structure formed on the main surface adjacent to the third groove structure in the first direction; a first mesa portion defined in a region between the first groove structure and the second groove structure; and a second mesa portion defined in a region between the third groove structure and the fourth groove structure and shifted in the first direction with respect to the first mesa portion.

[0007] The above and other objects, features, and advantages will become apparent from the following description of the embodiments with reference to the accompanying drawings.

[0008] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing a layout of gate electrodes and source electrodes. FIG. 4 is a plan view showing a layout of a first main surface. FIG. 5 is an enlarged plan view showing a layout of an active region. FIG. 6 is an enlarged plan view showing a layout of a peripheral region. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5 . FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 6 . FIG. 10 is a cross-sectional view taken along line XX in FIG. 6 . FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 6 . FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 6 . FIG. 13 is an enlarged plan view showing a layout of a termination region. FIG. 14 is an enlarged plan view showing a layout of a gate resistor. FIG. 15 is an enlarged plan view showing an inner portion of a gate resistor. FIG. 16 is an enlarged plan view showing a peripheral portion of a gate resistor. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 15 . FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 15 . FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 16 . FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 16 . FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 16 . FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 16 . FIG. 23 is an enlarged plan view showing a main portion of a gate resistor. FIG. 24 is an enlarged plan view showing the layout of a termination dummy structure. FIG. 25 is a further enlarged plan view showing the layout of a termination dummy structure. FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 25 . FIG. 27 is an electrical circuit diagram showing the connection configuration of a gate electrode and a gate resistor. FIG. 28 is a cross-sectional view showing the structure of the peripheral region. FIG. 29 is a cross-sectional view showing a trench resistor structure according to a first modification. Fig. 30 is a cross-sectional view showing a trench resistor structure according to a second modified example. Fig. 31 is an enlarged plan view showing a trench resistor structure according to a third modified example. Fig. 32 is an enlarged plan view showing a gate pad according to the modified examples. Fig. 33 is a cross-sectional view showing a chip according to a first modified example. Fig. 34 is a cross-sectional view showing a chip according to a second modified example.

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When the phrase "substantially equal" is used in a description in which a comparison target is present, this phrase includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not attached with the intent of limiting the names of each structure.

[0011] FIG. 1 is a plan view showing a semiconductor device 1 according to one embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing a layout of a gate electrode 100 and a source electrode 120. FIG. 4 is a plan view showing a layout of a first main surface 3. Referring to FIGS. 1 to 4, the semiconductor device 1 is a semiconductor switching device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

[0012] In this embodiment, the semiconductor device 1 includes a chip 2 that includes a single crystal of a wide bandgap semiconductor and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). That is, the semiconductor device 1 is a "wide bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip" or a "wide bandgap semiconductor chip." A wide bandgap semiconductor is a semiconductor that has a bandgap that exceeds the bandgap of Si (silicon). GaN (gallium nitride), SiC (silicon carbide), and C (diamond) are examples of wide bandgap semiconductors.

[0013] In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device." The semiconductor device 1 may also be referred to as a "SiC-MISFET." The hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may include other polytypes.

[0014] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2. The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of a SiC single crystal.

[0015] In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be more than 0° and not more than 10°. The off angle is preferably not more than 5°.

[0016] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0017] The chip 2 may have a thickness of 5 μm or more and 200 μm or less. The thickness of the chip 2 may be set to a value belonging to any one of the following ranges: 5 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, and 175 μm or more and 200 μm or less. The thickness of the chip 2 is preferably 100 μm or less.

[0018] The first to fourth side surfaces 5A to 5D may have lengths of 0.5 mm or more and 20 mm or less in plan view. The lengths of the first to fourth side surfaces 5A to 5D may be set to a value belonging to any one of the ranges of 0.5 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The lengths of the first to fourth side surfaces 5A to 5D are preferably 5 mm or more.

[0019] The semiconductor device 1 includes an n-type first semiconductor region 6 formed in a region (surface layer) on the first main surface 3 side of the chip 2. The first semiconductor region 6 is formed in a layer extending along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer). The first semiconductor region 6 may have a thickness of 1 μm or more and 50 μm or less. The thickness of the first semiconductor region 6 is preferably 3 μm or more and 30 μm or less. The thickness of the first semiconductor region 6 is particularly preferably 5 μm or more and 25 μm or less.

[0020] The semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side of the chip 2. The second semiconductor region 7 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6 and is electrically connected to the first semiconductor region 6.

[0021] In this embodiment, the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC semiconductor substrate). That is, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer. The second semiconductor region 7 may have a thickness of 1 μm or more and 200 μm or less. The thickness of the second semiconductor region 7 may be 150 μm or less, 100 μm or less, 50 μm or less, or 40 μm or less. The thickness of the second semiconductor region 7 may be 5 μm or more. The thickness of the second semiconductor region 7 is preferably 10 μm or more. In this embodiment, the second semiconductor region 7 has a thickness greater than that of the first semiconductor region 6.

[0022] The semiconductor device 1 includes an active surface 8, an outer surface 9, and first to fourth connecting surfaces 10A-10D formed on a first main surface 3. The active surface 8, the outer surface 9, and the first to fourth connecting surfaces 10A-10D define an active plateau 11 on the first main surface 3. The active surface 8 may be referred to as a "first surface portion," the outer surface 9 may be referred to as a "second surface portion," and the first to fourth connecting surfaces 10A-10D may be referred to as a "connecting surface portion." The active surface 8, the outer surface 9, and the first to fourth connecting surfaces 10A-10D (i.e., the active plateau 11) may be considered to be components of the chip 2 (first main surface 3).

[0023] The active surface 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 8 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 8 is formed by the c-plane (Si-plane). In this embodiment, the active surface 8 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0024] The outer peripheral surface 9 is located outside the active surface 8 and is recessed from the active surface 8 in the thickness direction of the chip 2 (toward the second main surface 4). Specifically, the outer peripheral surface 9 is recessed to a depth less than the thickness of the first semiconductor region 6 so as to expose the first semiconductor region 6. The outer peripheral surface 9 extends in a band shape along the active surface 8 in a plan view and is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8.

[0025] The outer peripheral surface 9 has a flat surface extending in the first direction X and the second direction Y, and is formed substantially parallel to the active surface 8. In this embodiment, the outer peripheral surface 9 is formed by the c-plane (Si-plane). The outer peripheral surface 9 is continuous with the first to fourth side surfaces 5A to 5D. The outer peripheral surface 9 has a circumferential depth DO. The circumferential depth DO may be 0.1 μm or more and 5 μm or less. The circumferential depth DO is preferably 2.5 μm or less.

[0026] The first to fourth connection surfaces 10A to 10D extend in the normal direction Z and connect the active surface 8 and the outer peripheral surface 9. The first connection surface 10A is located on the first side surface 5A side, the second connection surface 10B is located on the second side surface 5B side, the third connection surface 10C is located on the third side surface 5C side, and the fourth connection surface 10D is located on the fourth side surface 5D side. The first connection surface 10A and the second connection surface 10B extend in the first direction X and face the second direction Y. The third connection surface 10C and the fourth connection surface 10D extend in the second direction Y and face the first direction X.

[0027] The first to fourth connection surfaces 10A to 10D may extend substantially perpendicularly between the active surface 8 and the outer peripheral surface 9 so as to define a quadrangular pillar-shaped active plateau 11. The first to fourth connection surfaces 10A to 10D may be inclined obliquely downward from the active surface 8 toward the outer peripheral surface 9 so as to define a quadrangular pyramid-shaped active plateau 11. In this manner, the semiconductor device 1 includes an active plateau 11 defined in a protruding shape in the first semiconductor region 6 on the first main surface 3. The active plateau 11 is formed only in the first semiconductor region 6, and is not formed in the second semiconductor region 7.

[0028] 4, the semiconductor device 1 includes an active region 12, an outer periphery region 13, a peripheral region 14, and a termination region 15. The active region 12 is provided on the active surface 8. Specifically, the active region 12 is provided in an inner portion of the active surface 8 at a distance from the periphery (first to fourth connection surfaces 10A to 10D) of the active surface 8. In this embodiment, the active region 12 is provided in a quadrangular shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view. The outer periphery region 13 is provided on the outer periphery surface 9. In this embodiment, the outer periphery region 13 is provided in a ring shape (specifically, a quadrangular ring shape) surrounding the active surface 8 (active plateau 11) in a plan view.

[0029] The peripheral region 14 is provided on the active surface 8 in a region between the active region 12 and the outer peripheral region 13. The peripheral regions 14 are provided on both sides of the active region 12 in the first direction X, and extend in a strip shape in the second direction Y. The peripheral region 14 includes a first peripheral region 14A and a second peripheral region 14B. The first peripheral region 14A is provided on the third side surface 5C side (the third connecting surface 10C side) of the active region 12, and the second peripheral region 14B is provided on the fourth side surface 5D side (the fourth connecting surface 10D side) of the active region 12.

[0030] Termination region 15 is provided on active surface 8 in a region between active region 12 and peripheral region 13. Termination region 15 is provided to sandwich active region 12 from both sides in second direction Y and extends in a strip shape in first direction X. Termination region 15 includes a first termination region 15A and a second termination region 15B. First termination region 15A is provided on the first side surface 5A side (first connection surface 10A side) of active region 12, and second termination region 15B is provided on the second side surface 5B side (second connection surface 10B side) of active region 12.

[0031] The semiconductor device 1 includes a main surface insulating film 16 that covers the first main surface 3. The main surface insulating film 16 selectively covers the active surface 8, the outer peripheral surface 9, and the first to fourth connecting surfaces 10A to 10D. The main surface insulating film 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0032] In this embodiment, the main surface insulating film 16 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 16 includes a silicon oxide film made of an oxide of the chip 2. In this embodiment, the main surface insulating film 16 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the wall portion of the main surface insulating film 16 may be formed at a distance inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9.

[0033] FIG. 5 is an enlarged plan view showing the layout of the active region 12. FIG. 6 is an enlarged plan view showing the layout of the peripheral region 14. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 5. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 6. FIG. 10 is a cross-sectional view taken along line XX shown in FIG. 6. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 6. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 6.

[0034] 6 shows the layout on the first peripheral region 14A side. Since the layout on the second peripheral region 14B side is substantially the same as the layout on the first peripheral region 14A side, the layout on the first peripheral region 14A side will be mainly described below. The layout on the second peripheral region 14B side can be obtained by replacing "third connecting surface 10C" with "fourth connecting surface 10D" in the following description.

[0035] 5 to 12, semiconductor device 1 includes p-type (second conductivity type) body region 17 formed in a surface layer portion of first main surface 3 (active surface 8). Body region 17 is formed at an interval from the bottom of first semiconductor region 6 toward active surface 8. Body region 17 is formed in a layer shape extending along active surface 8. Body region 17 may be formed over the entire active surface 8 and exposed from first to fourth connecting surfaces 10A to 10D.

[0036] Semiconductor device 1 includes n-type source region 18 formed in a surface layer portion of first main surface 3 (active surface 8) in active region 12. Specifically, source region 18 is formed in the surface layer portion of body region 17 at a distance from the bottom of body region 17 toward active surface 8. Source region 18 is not formed in peripheral region 14 or termination region 15.

[0037] Of course, the source region 18 may be formed in the peripheral region 14 and the termination region 15 to the extent that it does not affect the control of the channel. The source region 18 has a higher n-type impurity concentration than the first semiconductor region 6. The source region 18 forms a channel of the MISFET together with the first semiconductor region 6 in the body region 17.

[0038] The semiconductor device 1 includes a plurality of trench gate structures 20 formed in the first main surface 3 (active surface 8) in the active region 12. A gate potential VG as a first potential is applied to the plurality of trench gate structures 20. The plurality of trench gate structures 20 control inversion and non-inversion of channels in the body region 17. The plurality of trench gate structures 20 are each formed in a strip shape extending in a first direction X in a plan view and are arranged at intervals in a second direction Y.

[0039] In this embodiment, the plurality of trench gate structures 20 are arranged inward of the active surface 8 at intervals from the periphery of the active surface 8. Specifically, the plurality of trench gate structures 20 are arranged at intervals in the first direction X and the second direction Y from the first to fourth connecting surfaces 10A to 10D.

[0040] The plurality of trench gate structures 20 define an active region 12 inside the active surface 8, and at the same time, define a peripheral region 14 and a termination region 15 together with the periphery of the active surface 8. The plurality of trench gate structures 20 penetrate the body region 17 and the source region 18 to reach the first semiconductor region 6. The plurality of trench gate structures 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0041] One trench gate structure 20 will be described below. The trench gate structure 20 has a first width W1 in the second direction Y and a first depth D1 in the normal direction Z. The first width W1 may be 0.1 μm or more and 3 μm or less. The first width W1 is preferably 0.5 μm or more and 2 μm or less. The first depth D1 is less than the aforementioned peripheral depth DO. The first depth D1 may be 0.1 μm or more and 3 μm or less. The first depth D1 is preferably 0.5 μm or more and 1.5 μm or less.

[0042] The trench gate structure 20 includes a gate trench 21, a gate insulating film 22, and a buried gate electrode 23. The gate trench 21 is formed in the active surface 8 and defines the wall surface of the trench gate structure 20. The gate insulating film 22 covers the wall surface of the gate trench 21 and is connected to the main surface insulating film 16 at the active surface 8. The gate insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0043] In this embodiment, the gate insulating film 22 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 22 includes a silicon oxide film made of an oxide of the chip 2. The buried gate electrode 23 is embedded in the gate trench 21 across the gate insulating film 22 and faces the channel across the gate insulating film 22. The buried gate electrode 23 may include conductive polysilicon.

[0044] The semiconductor device 1 includes a plurality of first trench source structures 25 formed in the first main surface 3 (active surface 8) in the active region 12. A source potential VS serving as a second potential different from the first potential is applied to the plurality of first trench source structures 25. The source potential VS may be a reference potential (for example, ground potential) that serves as an operation reference.

[0045] The plurality of first trench source structures 25 are each arranged in a region between two adjacent trench gate structures 20. The plurality of first trench source structures 25 are arranged alternately with the plurality of trench gate structures 20 in the second direction Y in a plan view, and are each formed in a strip shape extending in the first direction X. In this embodiment, the plurality of first trench source structures 25 are extended from the active region 12 to the peripheral region 14. The plurality of first trench source structures 25 are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D.

[0046] In this embodiment, the plurality of first trench source structures 25 penetrate both the third connection surface 10C and the fourth connection surface 10D and are exposed from both the third connection surface 10C and the fourth connection surface 10D. The plurality of first trench source structures 25 face the trench gate structure 20 in the second direction Y in the active region 12, but do not face the trench gate structure 20 in the second direction Y in the peripheral region 14.

[0047] The plurality of first trench source structures 25 penetrate the body region 17 and the source region 18 in the active region 12 to reach the first semiconductor region 6, and also penetrate the body region 17 in the peripheral region 14. The plurality of first trench source structures 25 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0048] One first trench source structure 25 will now be described. The first trench source structure 25 has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z. The second width W2 is preferably approximately equal to the first width W1 described above. The second width W2 may be 0.1 μm or more and 3 μm or less. The second width W2 is preferably 0.5 μm or more and 2 μm or less.

[0049] The second depth D2 is equal to or greater than the first depth D1. In this embodiment, the second depth D2 is greater than the first depth D1. The second depth D2 is preferably 1.5 to 3 times the first depth D1. In this embodiment, the second depth D2 is approximately equal to the outer peripheral depth DO. The second depth D2 may be 0.1 μm to 5 μm. It is particularly preferable that the second depth D2 be 2.5 μm or less.

[0050] The first trench source structure 25 is disposed at a first distance I1 from the trench gate structure 20 in the second direction Y. The first distance I1 is preferably 0.5 to 2 times the first width W1 (second width W2). It is particularly preferable that the first distance I1 be less than the first width W1 (second width W2). The first distance I1 may be 0.1 μm to 2.5 μm. The first distance I1 is preferably 0.5 μm to 1.5 μm.

[0051] The first trench source structure 25 includes a first source trench 26, a first source insulating film 27, and a first source buried electrode 28. The first source trench 26 is formed in the active surface 8 and defines a wall surface of the first trench source structure 25. The sidewall of the first source trench 26 communicates with the third connection surface 10C and the fourth connection surface 10D. The bottom wall of the first source trench 26 communicates with the outer peripheral surface 9.

[0052] The first source insulating film 27 covers the wall surface of the first source trench 26 and is connected to the main surface insulating film 16 at the active surface 8. The first source insulating film 27 is connected to the main surface insulating film 16 at the communicating portion of the third connecting surface 10C, the communicating portion of the fourth connecting surface 10D, and the communicating portion of the outer peripheral surface 9. The first source insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0053] In this embodiment, the first source insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first source insulating film 27 includes a silicon oxide film made of an oxide of the chip 2. The first source buried electrode 28 is buried in the first source trench 26 with the first source insulating film 27 sandwiched therebetween. The first source buried electrode 28 may include conductive polysilicon.

[0054] The semiconductor device 1 includes a plurality of second trench source structures 30 formed in the first main surface 3 (active surface 8) in the peripheral region 14. A source potential VS is applied to the plurality of second trench source structures 30. The plurality of second trench source structures 30 are arranged in a region between the periphery (third connection surface 10C) of the active surface 8 and the plurality of trench gate structures 20. The plurality of second trench source structures 30 are arranged in a region between two first trench source structures 25 adjacent to each other in the second direction Y, and face the plurality of trench gate structures 20 in a one-to-one correspondence in the first direction X.

[0055] The second trench source structures 30 are each formed in a strip shape extending in the first direction X in a plan view. In this embodiment, the second trench source structures 30 penetrate the third connection surface 10C and are exposed from the third connection surface 10C. The second trench source structures 30 penetrate the body region 17 to reach the first semiconductor region 6. The second trench source structures 30 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0056] One second trench source structure 30 will now be described. The second trench source structure 30 has a third width W3 in the second direction Y and a third depth D3 in the normal direction Z. The third width W3 is preferably approximately equal to the first width W1 described above. The third width W3 is preferably approximately equal to the second width W2 described above. The third width W3 may be 0.1 μm or more and 3 μm or less. The third width W3 is preferably 0.5 μm or more and 2 μm or less.

[0057] The third depth D3 is equal to or greater than the first depth D1 described above. In this embodiment, the third depth D3 is greater than the first depth D1. The third depth D3 is preferably 1.5 to 3 times the first depth D1. In this embodiment, the third depth D3 is approximately equal to the second depth D2 described above. The third depth D3 is approximately equal to the outer periphery depth DO described above. The third depth D3 may be 0.1 μm to 5 μm. It is particularly preferable that the third depth D3 be 2.5 μm or less.

[0058] The second trench source structure 30 is disposed in the second direction Y at a second distance I2 from the first trench source structure 25. The second distance I2 is preferably 0.5 to 2 times the second width W2 (third width W3). It is particularly preferable that the second distance I2 be less than the second width W2 (third width W3). The second distance I2 is preferably approximately equal to the first distance I1. The second distance I2 may be 0.1 μm to 2.5 μm. The second distance I2 is preferably 0.5 μm to 1.5 μm.

[0059] The second trench source structure 30 is disposed in the first direction X at a third distance I3 from the trench gate structure 20. The third distance I3 is preferably 0.5 to 2 times the first width W1 (third width W3). The third distance I3 is preferably 0.5 to 2 times the first distance I1 (second distance I2). It is particularly preferable that the third distance I3 be 1.5 times or less the first distance I1 (second distance I2). The third distance I3 may be approximately equal to the first distance I1 (second distance I2). The third distance I3 may be 0.1 μm to 2.5 μm. The third distance I3 is preferably 0.5 μm to 1.5 μm.

[0060] The second trench source structure 30 includes a second source trench 31, a second source insulating film 32, and a second source buried electrode 33. The second source trench 31 is formed in the active surface 8 and defines a wall surface of the second trench source structure 30. A sidewall of the second source trench 31 communicates with the third connection surface 10C. A bottom wall of the second source trench 31 communicates with the outer peripheral surface 9.

[0061] The second source insulating film 32 covers the wall surface of the second source trench 31 and is connected to the main surface insulating film 16 at the active surface 8. The second source insulating film 32 is connected to the main surface insulating film 16 at the communicating portion of the third connection surface 10C and the communicating portion of the outer peripheral surface 9. The second source insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0062] In this embodiment, the second source insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second source insulating film 32 includes a silicon oxide film made of an oxide of the chip 2. The second source buried electrode 33 is buried in the second source trench 31 with the second source insulating film 32 sandwiched therebetween. The second source buried electrode 33 may include conductive polysilicon.

[0063] The semiconductor device 1 includes a plurality of p-type first well regions 35 formed in the active region 12 in regions along the plurality of trench gate structures 20. In this embodiment, the first well regions 35 have a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the first well regions 35 may be lower than that of the body region 17.

[0064] The multiple first well regions 35 cover the wall surfaces of the corresponding trench gate structures 20 at intervals from adjacent first trench source structures 25, and are electrically connected to the body region 17 in the surface layer portion of the active surface 8. The multiple first well regions 35 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 with part of the first semiconductor region 6 in between. The multiple first well regions 35 form pn junctions with the first semiconductor region 6.

[0065] The semiconductor device 1 includes a plurality of p-type second well regions 36 formed in the active region 12 and the peripheral region 14 in regions along the plurality of first trench source structures 25. In this embodiment, the second well regions 36 have a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the second well regions 36 may be lower than that of the body region 17. It is preferable that the p-type impurity concentration of the second well regions 36 be approximately equal to the p-type impurity concentration of the first well region 35.

[0066] The second well regions 36 cover the wall surfaces of the corresponding first trench source structures 25 at intervals from the adjacent trench gate structures 20, and are electrically connected to the body region 17 in the surface portion of the active surface 8. The second well regions 36 cover the wall surfaces of the corresponding first trench source structures 25 in the active region 12 and the peripheral region 14, and are exposed from the third connection surface 10C and the fourth connection surface 10D.

[0067] The second well regions 36 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the second well regions 36 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the first well regions 35. The second well regions 36 form pn junctions with the first semiconductor region 6.

[0068] The semiconductor device 1 includes a plurality of p-type third well regions 37 formed in the peripheral region 14 in regions along the plurality of second trench source structures 30. In this embodiment, the third well regions 37 have a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the third well regions 37 may be lower than that of the body region 17. It is preferable that the p-type impurity concentration of the third well regions 37 be approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36).

[0069] The plurality of third well regions 37 cover the wall surfaces of the corresponding second trench source structures 30 at intervals from the adjacent trench gate structures 20 and first trench source structures 25, and are electrically connected to the body region 17 in the surface portion of the active surface 8. Of course, the third well regions 37 may be integrated with the first well region 35 in the region between the trench gate structures 20 and the second trench source structures 30. The plurality of third well regions 37 are exposed from the third connection surface 10C.

[0070] The plurality of third well regions 37 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the plurality of third well regions 37 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the plurality of first well regions 35. The bottoms of the plurality of third well regions 37 are formed at approximately the same depth as the bottoms of the plurality of second well regions 36. The plurality of third well regions 37 form pn junctions with the first semiconductor region 6.

[0071] The semiconductor device 1 includes a plurality of p-type first contact regions 38 formed in the active region 12 in regions along the plurality of first trench source structures 25. The first contact regions 38 have a higher p-type impurity concentration than the body region 17. In this embodiment, the p-type impurity concentration of the first contact regions 38 is higher than that of the second well region 36.

[0072] The plurality of first contact regions 38 cover the wall surfaces of the corresponding first trench source structures 25 in the corresponding second well regions 36. The plurality of first contact regions 38 are formed in a one-to-many correspondence with each of the first trench source structures 25. The plurality of first contact regions 38 are formed at intervals along the corresponding first trench source structures 25.

[0073] The plurality of first contact regions 38 are extended from within the corresponding second well region 36 to the surface portion of the body region 17 along the wall surfaces of the corresponding first trench source structures 25 and are exposed from the active surface 8. The plurality of first contact regions 38 are formed in the active region 12 and are not formed in the peripheral region 14. In other words, the plurality of first contact regions 38 face the trench gate structure 20 in the second direction Y, but do not face the second trench source structure 30 in the second direction Y. The first contact regions 38 are not formed in the third well region 37.

[0074] In this embodiment, the multiple first contact regions 38 are each formed in a strip shape extending in the first direction X in a plan view. The length of the multiple first contact regions 38 in the first direction X is preferably equal to or greater than the second width W2 described above. The length of the multiple first contact regions 38 is preferably greater than the distance between two first contact regions 38 adjacent to each other in the first direction X.

[0075] The plurality of first contact regions 38 along one first trench source structure 25 face the plurality of first contact regions 38 along another first trench source structure 25 in the second direction Y. That is, in this embodiment, the plurality of first contact regions 38 are arranged in a matrix form at intervals in the first direction X and the second direction Y as a whole in a plan view.

[0076] The first contact regions 38 along one first trench source structure 25 may be arranged offset in the first direction X so as to face the second direction Y in a region between the first contact regions 38 along another first trench source structure 25. In other words, the first contact regions 38 may be arranged in a staggered pattern as a whole with intervals in the first direction X and the second direction Y in a plan view.

[0077] The semiconductor device 1 includes a plurality of gate connection electrode films 39 covering respective ends of the plurality of trench gate structures 20 on the first main surface 3 (active surface 8) in the active region 12. Specifically, the plurality of gate connection electrode films 39 are disposed on the main surface insulating film 16. The plurality of gate connection electrode films 39 cover inner portions of the plurality of trench gate structures 20 and respective ends of the corresponding trench gate structures 20 at intervals from the plurality of first trench source structures 25 and the plurality of second trench source structures 30.

[0078] The multiple gate connection electrode films 39 are arranged alternately with the multiple first trench source structures 25 in the second direction Y in plan view. In this embodiment, the multiple gate connection electrode films 39 are each formed in a strip shape extending in the first direction X. The multiple gate connection electrode films 39 do not face the multiple second trench source structures 30 in the second direction Y in plan view. Below, one gate connection electrode film 39 will be described.

[0079] The gate connection electrode film 39 is connected to the corresponding buried gate electrode 23 in a portion covering the corresponding trench gate structure 20. In this embodiment, the gate connection electrode film 39 is formed integrally with the corresponding buried gate electrode 23. That is, the gate connection electrode film 39 is formed by a portion of the buried gate electrode 23 being extended in the form of a film onto the active surface 8 (main surface insulating film 16). Of course, the gate connection electrode film 39 may be formed separately from the buried gate electrode 23.

[0080] The gate connection electrode film 39 has an electrode surface 39a extending along the active surface 8. In this embodiment, the gate connection electrode film 39 is formed in a tapered shape (a truncated quadrangular pyramid shape) from the active surface 8 toward the electrode surface 39a in a cross-sectional view. The electrode surface 39a is preferably formed to be wider than the trench gate structure 20 in the second direction Y. In other words, the electrode surface 39a preferably has a portion facing the trench gate structure 20 in the normal direction Z and a portion facing a region outside the trench gate structure 20 (i.e., the main surface insulating film 16) in the normal direction Z.

[0081] In this embodiment, the gate connection electrode film 39 includes conductive polysilicon. The gate connection electrode film 39 has an electrode thickness TE. The electrode thickness TE is preferably 0.5 times or more the first width W1 (second width W2) described above. The electrode thickness TE is preferably equal to or less than the outer circumferential depth DO described above. The electrode thickness TE is preferably equal to or less than the second depth D2 described above. It is particularly preferable that the electrode thickness TE be less than the second depth D2 (outer circumferential depth DO).

[0082] The electrode thickness TE is preferably equal to or less than the first depth D1. It is particularly preferable that the electrode thickness TE is less than the first depth D1. The electrode thickness TE may be 0.05 μm or more and 2.5 μm or less. The electrode thickness TE is preferably 0.5 μm or more and 1.5 μm or less. Of course, the electrode thickness TE may be greater than the first depth D1. Furthermore, the electrode thickness TE may be equal to or greater than the outer circumferential depth DO (second depth D2).

[0083] 13 is an enlarged plan view showing the layout of the termination region 15 (first termination region 15A). FIG. 14 is an enlarged plan view showing the layout of the gate resistor 40. FIG. 15 is an enlarged plan view showing the inner part of the gate resistor 40. FIG. 16 is an enlarged plan view showing the peripheral part of the gate resistor 40.

[0084] Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 15. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 15. Fig. 19 is a cross-sectional view taken along line XIX-XIX shown in Fig. 16. Fig. 20 is a cross-sectional view taken along line XX-XX shown in Fig. 16. Fig. 21 is a cross-sectional view taken along line XXI-XXI shown in Fig. 16. Fig. 22 is a cross-sectional view taken along line XXII-XXII shown in Fig. 16. Fig. 23 is an enlarged plan view showing a main part of gate resistor 40.

[0085] 13 to 23 , semiconductor device 1 includes gate resistor 40 formed on first main surface 3 (active surface 8) in first termination region 15A. Gate resistor 40 is incorporated in chip 2 (first termination region 15A) as a resistor electrically connected to the gate (trench gate structure 20) of the MISFET.

[0086] The gate resistor 40 is disposed in a region on the first side surface 5A side (first connecting surface 10A side) of the active region 12, and faces the active region 12 in the second direction Y. The gate resistor 40 is disposed at a distance from the peripheral region 14 in the first direction X so as not to face the peripheral region 14 in the second direction Y. In this embodiment, the gate resistor 40 is disposed between the center of the first side surface 5A (first connecting surface 10A) and the active region 12.

[0087] The gate resistor 40 includes at least one (in this embodiment, a plurality of) trench resistor structures 41 formed on the first main surface 3 (active surface 8) in the first termination region 15A. A gate potential VG as a first potential is applied to the plurality of trench resistor structures 41, but the plurality of trench resistor structures 41 do not contribute to channel control.

[0088] The plurality of trench resistance structures 41 are each formed in a strip shape extending in the first direction X and are arranged at intervals in the second direction Y. The plurality of trench resistance structures 41 penetrates the body region 17 to reach the first semiconductor region 6. The plurality of trench resistance structures 41 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0089] In this embodiment, the plurality of trench resistance structures 41 includes a plurality of first trench resistance structures 42 and a plurality of second trench resistance structures 43. The plurality of first trench resistance structures 42 are formed on the active surface 8 in the first termination region 15A at intervals from the periphery of the active surface 8. The plurality of first trench resistance structures 42 are each formed in a strip shape extending in the first direction X and are arranged at intervals in the second direction Y.

[0090] The multiple first trench resistance structures 42 face the first trench source structure 25 in the second direction Y. The multiple first trench resistance structures 42 are arranged at intervals from the second trench source structure 30 in the first direction X so as not to face the second trench source structure 30 in the second direction Y. The multiple first trench resistance structures 42 penetrate the body region 17 to reach the first semiconductor region 6. The multiple first trench resistance structures 42 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0091] One first trench resistor structure 42 will be described below. The first trench resistor structure 42 has a first resistor length L1 in the first direction X. The first resistor length L1 is arbitrary and is adjusted appropriately depending on the resistance value to be achieved. The first trench resistor structure 42 has a fourth width W4 in the second direction Y and a fourth depth D4 in the normal direction Z. The fourth width W4 is preferably approximately equal to the first width W1 described above. The fourth width W4 may be 0.1 μm or more and 3 μm or less. The fourth width W4 is preferably 0.5 μm or more and 2 μm or less.

[0092] The fourth depth D4 is less than the second depth D2 described above. The fourth depth D4 is less than the outer circumferential depth DO described above. The fourth depth D4 is preferably approximately equal to the first depth D1 described above. The fourth depth D4 may be 0.1 μm or more and 3 μm or less. The fourth depth D4 is preferably 0.5 μm or more and 1.5 μm or less.

[0093] In this embodiment, the outermost first trench resistance structure 42 on the active region 12 side is arranged adjacent to the outermost first trench source structure 25 in the second direction Y at the first distance I1 from the outermost first trench source structure 25. In this embodiment, the outermost first trench resistance structure 42 is arranged at a distance in the first direction X from the outermost second trench source structure 30 so as not to face the outermost second trench source structure 30 in the second direction Y.

[0094] The first trench resistor structure 42 includes a first trench 44, a first insulating film 45, and a first buried electrode 46. The first buried electrode 46 may be referred to as a "first buried resistor." The first trench 44 is formed in the active surface 8 and defines a wall surface of the first trench resistor structure 42. The first insulating film 45 covers the wall surface of the first trench 44 and is connected to the main surface insulating film 16 at the active surface 8. The first insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0095] In this embodiment, the first insulating film 45 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 45 includes a silicon oxide film made of an oxide of the chip 2. The first buried electrode 46 is buried in the first trench 44 with the first insulating film 45 sandwiched therebetween. The first buried electrode 46 may include conductive polysilicon.

[0096] The plurality of second trench resistance structures 43 are formed in the active surface 8 at intervals from the periphery of the active surface 8 in the first termination region 15A. The plurality of second trench resistance structures 43 are each arranged in a region between two adjacent first trench resistance structures 42. The plurality of second trench resistance structures 43 are arranged alternately with the plurality of first trench resistance structures 42 in the second direction Y. The plurality of second trench resistance structures 43 are each formed in a strip shape extending in the first direction X in a plan view.

[0097] The plurality of second trench resistance structures 43 face the trench gate structure 20 and the first trench source structure 25 in the second direction Y. The plurality of second trench resistance structures 43 are arranged at intervals from the second trench source structure 30 in the first direction X so as not to face the second trench source structure 30 in the second direction Y. The plurality of second trench resistance structures 43 penetrate the body region 17 to reach the first semiconductor region 6. The plurality of second trench resistance structures 43 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0098] One second trench resistor structure 43 will be described below. The second trench resistor structure 43 has a second resistor length L2 in the first direction X. The second resistor length L2 is arbitrary and is adjusted appropriately depending on the resistance value to be achieved. In this embodiment, the second resistor length L2 is less than the first resistor length L1. That is, both ends of the second trench resistor structure 43 are set back inward relative to both ends of the first trench resistor structure 42. Of course, the second resistor length L2 may be approximately equal to the first resistor length L1. Alternatively, the second resistor length L2 may be greater than the first resistor length L1.

[0099] The second trench resistor structure 43 has a fifth width W5 in the second direction Y and a fifth depth D5 in the normal direction Z. The fifth width W5 is preferably approximately equal to the aforementioned fourth width W4. The fifth width W5 is preferably approximately equal to the aforementioned second width W2 (first width W1). The fifth width W5 may be 0.1 μm or more and 3 μm or less. The fifth width W5 is preferably 0.5 μm or more and 2 μm or less.

[0100] The fifth depth D5 is equal to or greater than the fourth depth D4 (first depth D1) described above. In this embodiment, the fifth depth D5 is greater than the fourth depth D4 (first depth D1). The fifth depth D5 is preferably 1.5 to 3 times the fourth depth D4 (first depth D1). The fifth depth D5 is preferably approximately equal to the second depth D2 described above. The fifth depth D5 is preferably approximately equal to the outer peripheral depth DO described above. The fifth depth D5 may be 0.1 μm to 5 μm. It is particularly preferable that the fifth depth D5 be 2.5 μm or less.

[0101] The second trench resistor structure 43 is disposed in the second direction Y at a fourth interval I4 from the first trench resistor structure 42. The fourth interval I4 is preferably 0.5 to 2 times the fourth width W4 (fifth width W5). It is particularly preferable that the fourth interval I4 be less than the fourth width W4 (fifth width W5). The fourth interval I4 is preferably approximately equal to the first interval I1. The fourth interval I4 may be 0.1 μm to 2.5 μm. The fourth interval I4 is preferably 0.5 μm to 1.5 μm.

[0102] The second trench resistor structure 43 includes a second trench 47, a second insulating film 48, and a second buried electrode 49. The second buried electrode 49 may be referred to as a "first buried resistor." The second trench 47 is formed in the active surface 8 and defines the wall surface of the second trench resistor structure 43. The second insulating film 48 covers the wall surface of the second trench 47 and is connected to the main surface insulating film 16 at the active surface 8. The second insulating film 48 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0103] In this embodiment, the second insulating film 48 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 48 includes a silicon oxide film made of an oxide of the chip 2. The second buried electrode 49 is buried in the second trench 47 with the second insulating film 48 sandwiched therebetween. The second buried electrode 49 may include conductive polysilicon.

[0104] The gate resistor 40 includes a resistive film 50 covering at least one trench resistor structure 41 (multiple in this embodiment) on the first main surface 3 (active surface 8). The resistive film 50 includes at least one of a conductive polysilicon film and an alloy crystal film. The alloy crystal film includes alloy crystals composed of a metal element and a non-metal element. The alloy crystal film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film. In this embodiment, the resistive film 50 includes conductive polysilicon.

[0105] The resistive film 50 is disposed on the main surface insulating film 16, and has a portion covering the active surface 8 and a portion covering the plurality of trench resistance structures 41. In this embodiment, the resistive film 50 covers all of the plurality of trench resistance structures 41 in the short direction (second direction Y) of the plurality of trench resistance structures 41. The resistive film 50 is connected to the first buried electrode 46 and the second buried electrode 49 in the portion covering the plurality of trench resistance structures 41.

[0106] In this embodiment, the resistive film 50 is formed integrally with the first buried electrode 46 and the second buried electrode 49. In other words, the resistive film 50 is made up of a portion of the first buried electrode 46 and a portion of the second buried electrode 49 that are extended in a film form onto the active surface 8 (main surface insulating film 16). Of course, the resistive film 50 may be formed separately from the first buried electrode 46 and the second buried electrode 49.

[0107] The resistive film 50 faces the trench gate structure 20 and the first trench source structure 25 in the second direction Y. The resistive film 50 is arranged at a distance from the second trench source structure 30 in the first direction X so as not to face the second trench source structure 30 in the second direction Y. In this embodiment, the resistive film 50 is formed in a band shape extending in the first direction X in a plan view. The planar shape of the resistive film 50 is arbitrary and is adjusted appropriately depending on the resistance value to be achieved.

[0108] The resistive film 50 preferably has a third resistance length L3 in the first direction X that is shorter than the first resistance length L1 of the first trench resistance structure 42 and the second resistance length L2 of the second trench resistance structure 43. In this case, the resistive film 50 preferably covers inner portions of the trench resistance structures 41 at a distance inward from both ends of the trench resistance structures 41 in the longitudinal direction (first direction X) of the trench resistance structures 41. In other words, the resistive film 50 preferably exposes both ends of the first trench resistance structures 42 and both ends of the second trench resistance structures 43.

[0109] By setting back the resistive film 50 inward relative to both end portions of the plurality of trench resistance structures 41, it is possible to prevent the resistive film 50 from facing the first main surface 3 in a region closer to the periphery of the active surface 8 than both end portions of the plurality of trench resistance structures 41. Therefore, in a region outside both end portions of the plurality of trench resistance structures 41, the generation of an undesired potential difference (electric field) between the first main surface 3 and the resistive film 50 is prevented.

[0110] Of course, the resistive film 50 may cover the entire areas of the plurality of trench resistive structures 41. That is, the third resistive length L3 may be greater than the first resistive length L1. Furthermore, the resistive film 50 may expose both ends of the plurality of first trench resistive structures 42 and cover both ends of the plurality of second trench resistive structures 43. That is, the third resistive length L3 may be smaller than the first resistive length L1 and larger than the second resistive length L2.

[0111] The resistive film 50 has a resistor thickness TR in the normal direction Z. The resistor thickness TR is adjusted as appropriate depending on the resistance value to be achieved. That is, the resistance value of the resistive film 50 is adjusted by increasing or decreasing the resistor thickness TR and the third resistor length L3. The resistor thickness TR is preferably 0.5 times or more the aforementioned fourth width W4 (fifth width W5).

[0112] If the resistor thickness TR satisfies this condition, when a conductive polysilicon film is formed by CVD to fill the first trench 44 and the second trench 47 and cover the first main surface 3 (active surface 8), a portion of the conductive polysilicon film can be used to form the first buried electrode 46, the second buried electrode 49, and the resistor film 50. The resistor thickness TR is preferably equal to or less than the aforementioned peripheral depth DO. The resistor thickness TR is preferably equal to or less than the aforementioned fifth depth D5 (second depth D2).

[0113] It is particularly preferable that the resistor thickness TR be less than the fifth depth D5. It is preferable that the resistor thickness TR be equal to or less than the aforementioned fourth depth D4 (first depth D1). It is particularly preferable that the resistor thickness TR be less than the fourth depth D4. The resistor thickness TR may be less than the aforementioned electrode thickness TE. The resistor thickness TR may be greater than the electrode thickness TE. The resistor thickness TR may be approximately equal to the electrode thickness TE. The resistor thickness TR may be 0.05 μm or more and 2.5 μm or less. It is preferable that the resistor thickness TR be 0.5 μm or more and 1.5 μm or less.

[0114] Of course, the resistor thickness TR may be greater than the fourth depth D4. The resistor thickness TR may also be equal to or greater than the outer circumferential depth DO (fifth depth D5). Furthermore, when the resistor film 50 is made of an alloy crystal film, the resistor thickness TR may be less than the fourth depth D4. In this case, the resistor thickness TR may be 0.1 nm or more and 100 nm or less.

[0115] 13 to 23 , semiconductor device 1 includes a dummy structure 55 formed on first main surface 3 (active surface 8) in first termination region 15A. Dummy structure 55 is incorporated in active surface 8 (first termination region 15A) for one purpose of alleviating local electric field concentration in the vicinity of gate resistor 40 and improving breakdown voltage (e.g., breakdown voltage). The presence or absence of dummy structure 55 is optional, and a configuration without dummy structure 55 may also be employed.

[0116] The dummy structure 55 includes a first dummy structure 56 and a second dummy structure 57. The first dummy structure 56 is arranged in a region on the third side surface 5C side (the third connecting surface 10C side) of the gate resistor 40. The first dummy structure 56 faces the gate resistor 40 in the first direction X, and faces the active region 12 and the first peripheral region 14A in the second direction Y. The second dummy structure 57 is arranged in a region on the fourth side surface 5D side (the fourth connecting surface 10D side) of the gate resistor 40.

[0117] The second dummy structure 57 faces the first dummy structure 56 in the first direction X, with the gate resistor 40 interposed therebetween, and faces the active region 12 and the second peripheral region 14B in the second direction Y. Since the layout of the second dummy structure 57 is substantially the same as the layout of the first dummy structure 56, the configuration of the first dummy structure 56 will be described below. The layout of the second dummy structure 57 can be obtained by replacing "third connecting surface 10C" with "fourth connecting surface 10D" in the following description.

[0118] The first dummy structure 56 includes at least one (in this embodiment, multiple) dummy trench structures 60 formed in the first main surface 3 (active surface 8) in the first termination region 15A. A source potential VS as a second potential is applied to the multiple dummy trench structures 60. The multiple dummy trench structures 60 are each formed in a strip shape extending in the first direction X and are arranged at intervals in the second direction Y.

[0119] The plurality of dummy trench structures 60 face the plurality of trench resistor structures 41 in a one-to-one correspondence in the first direction X. The plurality of dummy trench structures 60 face the first trench source structure 25 and the second trench source structure 30 in the second direction Y. The plurality of dummy trench structures 60 penetrate the body region 17 to reach the first semiconductor region 6. In this embodiment, the plurality of dummy trench structures 60 penetrate the third connection surface 10C and are exposed from the third connection surface 10C. The plurality of trench gate structures 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0120] In this embodiment, the multiple dummy trench structures 60 include multiple first dummy trench structures 61 and multiple second dummy trench structures 62. The multiple first dummy trench structures 61 are arranged in regions around the periphery of the active surface 8 and between the multiple first trench resistance structures 42. The multiple first dummy trench structures 61 are each formed in a strip shape extending in the first direction X and are arranged at intervals in the second direction Y.

[0121] The multiple first dummy trench structures 61 face the multiple first trench resistance structures 42 in a one-to-one correspondence in the first direction X. That is, the first trench resistance structures 42 to which the gate potential VG is applied and the first dummy trench structures 61 to which the source potential VS is applied face each other in the first direction X. The multiple first dummy trench structures 61 face the first trench source structures 25 and the second trench source structures 30 in the second direction Y.

[0122] In this embodiment, the plurality of first dummy trench structures 61 penetrate the third connecting surface 10C and are exposed from the third connecting surface 10C. The plurality of first dummy trench structures 61 penetrate the body region 17 to reach the first semiconductor region 6. The plurality of first dummy trench structures 61 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0123] One first dummy trench structure 61 will be described below. The first dummy trench structure 61 has a sixth width W6 in the second direction Y and a sixth depth D6 in the normal direction Z. The sixth width W6 is preferably approximately equal to the aforementioned fourth width W4. The sixth width W6 is preferably approximately equal to the aforementioned first width W1. The sixth width W6 may be 0.1 μm or more and 3 μm or less. The sixth width W6 is preferably 0.5 μm or more and 2 μm or less.

[0124] The sixth depth D6 is less than the fifth depth D5 (second depth D2) described above. The sixth depth D6 is less than the outer peripheral depth DO described above. The sixth depth D6 is preferably approximately equal to the fourth depth D4 (first depth D1) described above. The sixth depth D6 may be 0.1 μm or more and 3 μm or less. The sixth depth D6 is preferably 0.5 μm or more and 1.5 μm or less.

[0125] The first dummy trench structure 61 is disposed in the first direction X at a fifth interval I5 from the first trench resistor structure 42. The fifth interval I5 is preferably 0.5 to 2 times the fourth width W4 (sixth width W6). The fifth interval I5 is preferably 0.5 to 2 times the aforementioned fourth interval I4. It is particularly preferable that the fifth interval I5 be 1.5 times or less the fourth interval I4. The fifth interval I5 may be approximately equal to the fourth interval I4. The fifth interval I5 may be 0.1 μm to 2.5 μm. The fifth interval I5 is preferably 0.5 μm to 1.5 μm.

[0126] In this embodiment, the outermost first dummy trench structure 61 on the active region 12 side is arranged adjacent to the outermost first trench source structure 25 in the second direction Y, with the aforementioned first distance I1 between them.

[0127] The first dummy trench structure 61 includes a first dummy trench 63, a first dummy insulating film 64, and a first dummy buried electrode 65. The first dummy trench 63 is formed in the active surface 8 and defines the wall surface of the first dummy trench structure 61. The sidewall and bottom wall of the first dummy trench 63 communicate with the third connecting surface 10C.

[0128] The first dummy insulating film 64 covers the wall surfaces of the first dummy trenches 63 and is connected to the main surface insulating film 16 at the active surface 8. The first dummy insulating film 64 is connected to the main surface insulating film 16 at the communicating portion of the third connecting surface 10C. The first dummy insulating film 64 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0129] In this embodiment, the first dummy insulating film 64 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first dummy insulating film 64 includes a silicon oxide film made of an oxide of the chip 2. The first dummy buried electrode 65 is buried in the first dummy trench 63 with the first dummy insulating film 64 sandwiched therebetween. The first dummy buried electrode 65 may include conductive polysilicon.

[0130] The second dummy trench structures 62 are arranged in a region between the periphery of the active surface 8 and the second trench resistance structures 43. The second dummy trench structures 62 are arranged in a region between two first dummy trench structures 61 adjacent to each other in the second direction Y. The second dummy trench structures 62 are arranged alternately with the first dummy trench structures 61 in the second direction Y, and face the second trench resistance structures 43 in a one-to-one correspondence in the first direction X.

[0131] That is, the second trench resistance structure 43 to which the gate potential VG is applied and the second dummy trench structure 62 to which the source potential VS is applied face each other in the first direction X. The multiple second dummy trench structures 62 are each formed in a strip shape extending in the first direction X in a plan view.

[0132] The second dummy trench structures 62 face the first trench source structure 25 and the second trench source structure 30 in the second direction Y. The second dummy trench structures 62 have portions that extend toward the ends of the second trench resistance structures 43 relative to the ends of the first trench resistance structures 42.

[0133] Specifically, the second dummy trench structures 62 extend toward the ends of the second trench resistance structures 43 relative to the region between the first trench resistance structure 42 and the first dummy trench structure 61. As a result, the ends of the second dummy trench structures 62 face the first trench resistance structure 42 in the second direction Y. In other words, the second dummy trench structures 62 have a portion facing the first trench resistance structure 42 in the second direction Y and a portion facing the first dummy trench structure 61 in the second direction Y.

[0134] In this embodiment, the second dummy trench structures 62 penetrate the third connecting surface 10C and are exposed from the third connecting surface 10C. The second dummy trench structures 62 penetrate the body region 17 to reach the first semiconductor region 6. The second dummy trench structures 62 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0135] One second dummy trench structure 62 will be described below. The second dummy trench structure 62 has a seventh width W7 in the second direction Y and a seventh depth D7 in the normal direction Z. The seventh width W7 is preferably approximately equal to the fifth width W5 described above. The seventh width W7 is preferably approximately equal to the second width W2 (first width W1) described above. The seventh width W7 may be 0.1 μm or more and 3 μm or less. The seventh width W7 is preferably 0.5 μm or more and 2 μm or less.

[0136] The seventh depth D7 is equal to or greater than the sixth depth D6 (fourth depth D4). In this embodiment, the seventh depth D7 is greater than the sixth depth D6 (fourth depth D4). The seventh depth D7 is preferably 1.5 to 3 times the sixth depth D6 (fourth depth D4). The seventh depth D7 is preferably approximately equal to the fifth depth D5 (second depth D2). In this embodiment, the seventh depth D7 is approximately equal to the outer peripheral depth DO. The seventh depth D7 may be 0.1 μm to 5 μm. It is particularly preferable that the seventh depth D7 be 2.5 μm or less.

[0137] The second dummy trench structure 62 is disposed at a sixth interval I6 from the first dummy trench structure 61 in the second direction Y. The sixth interval I6 is preferably 0.5 to 2 times the sixth width W6 (seventh width W7). It is particularly preferable that the sixth interval I6 be less than the sixth width W6 (seventh width W7).

[0138] The sixth interval I6 is preferably approximately equal to the aforementioned fourth interval I4. The sixth interval I6 is preferably approximately equal to the aforementioned first interval I1. The sixth interval I6 may be equal to or greater than 0.1 μm and equal to or less than 2.5 μm. The sixth interval I6 is preferably equal to or greater than 0.5 μm and equal to or less than 1.5 μm.

[0139] The second dummy trench structure 62 is disposed in the first direction X at a seventh distance I7 from the second trench resistor structure 43. The seventh distance I7 is preferably 0.5 to 2 times the sixth width W6 (seventh width W7). The seventh distance I7 is preferably 0.5 to 2 times the sixth width W6 (seventh width W7).

[0140] It is particularly preferable that the seventh interval I7 be 1.5 times or less the sixth interval I6 (fourth interval I4). It is preferable that the seventh interval I7 be approximately equal to the aforementioned fifth interval I5. The seventh interval I7 may be approximately equal to the sixth interval I6 (fourth interval I4). The seventh interval I7 may be 0.1 μm or more and 2.5 μm or less. It is preferable that the seventh interval I7 be 0.5 μm or more and 1.5 μm or less.

[0141] The second dummy trench structure 62 includes a second dummy trench 66, a second dummy insulating film 67, and a second dummy buried electrode 68. The second dummy trench 66 is formed in the active surface 8 and defines the wall surface of the second dummy trench structure 62. The sidewall of the second dummy trench 66 communicates with the third connection surface 10C. The bottom wall of the second dummy trench 66 communicates with the outer peripheral surface 9.

[0142] The second dummy insulating film 67 covers the wall surfaces of the second dummy trenches 66 and is connected to the main surface insulating film 16 at the active surface 8. The second dummy insulating film 67 is connected to the main surface insulating film 16 at the communicating portion of the third connecting surface 10C and the communicating portion of the outer peripheral surface 9. The second dummy insulating film 67 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0143] In this embodiment, the second dummy insulating film 67 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second dummy insulating film 67 includes a silicon oxide film made of an oxide of the chip 2. The second dummy buried electrode 68 is buried in the second dummy trench 66 with the second dummy insulating film 67 sandwiched therebetween. The second dummy buried electrode 68 may include conductive polysilicon.

[0144] 23 , the semiconductor device 1 includes a plurality of main mesas 70, a plurality of first mesas 71, and a plurality of second mesas 72. Each main mesa 70 is partitioned into a region between the first trench resistor structure 42 and the second trench resistor structure 43, and a region between the first dummy trench structure 61 and the second dummy trench structure 62. Each main mesa 70 extends in a strip shape in the first direction X. The width of each main mesa 70 in the second direction Y is determined by the aforementioned fourth interval I4 and sixth interval I6.

[0145] Each first mesa portion 71 is defined in a region between the first trench resistor structure 42 and the first dummy trench structure 61, and is connected to the main mesa portion 70. Each first mesa portion 71 is a region where a voltage drop occurs between the gate potential VG and the source potential VS in the first direction X. The width of each first mesa portion 71 in the first direction X is determined by the aforementioned fifth interval I5.

[0146] In this embodiment, each first mesa portion 71 faces the second dummy trench structure 62 in the second direction Y, but is shifted toward the second dummy trench structure 62 with respect to the end of the second trench resistance structure 43 so as not to face the second trench resistance structure 43 in the second direction Y. Each first mesa portion 71 is formed at an interval from the periphery of the resistance film 50 in the first direction X, and does not face the resistance film 50 in the normal direction Z.

[0147] Therefore, electrical interference of the resistive film 50 with each first mesa portion 71 is suppressed, and electrical interference of each first mesa portion 71 with the resistive film 50 is suppressed. Of course, when a resistive film 50 wider than the plurality of trench resistance structures 41 is formed, each first mesa portion 71 may face the resistive film 50 in the normal direction Z.

[0148] Each first mesa portion 71 defines a T-shaped mesa together with one main mesa portion 70 in plan view. From another perspective, each first mesa portion 71 defines an H-shaped mesa together with two main mesa portions 70 in plan view. In this embodiment, the multiple first mesa portions 71 are formed on the same straight line along the second direction Y. Of course, the multiple first mesa portions 71 may be formed shifted from each other in the first direction X so as not to be positioned on the same straight line along the second direction Y.

[0149] Each second mesa portion 72 is defined in a region between the second trench resistor structure 43 and the second dummy trench structure 62, and is connected to the main mesa portion 70. Each second mesa portion 72 is a region where a voltage drop occurs between the gate potential VG and the source potential VS in the first direction X. The width of each second mesa portion 72 in the first direction X is determined by the aforementioned seventh interval I7.

[0150] Each second mesa portion 72 is formed at a distance from the first mesa portion 71 in the first direction X so as not to face the first mesa portion 71 in the second direction Y. In this embodiment, each second mesa portion 72 faces the first trench resistance structure 42 in the second direction Y, and is shifted toward the first trench resistance structure 42 with respect to the end of the first dummy trench structure 61 so as not to face the first dummy trench structure 61 in the second direction Y.

[0151] Each second mesa portion 72 is formed at an interval in the first direction X from the periphery of the resistive film 50 in a plan view, and does not face the resistive film 50 in the normal direction Z. Therefore, electrical interference of the resistive film 50 with each second mesa portion 72 is suppressed, and electrical interference of each second mesa portion 72 with the resistive film 50 is also suppressed. Of course, when a resistive film 50 wider than the plurality of trench resistance structures 41 is formed, each second mesa portion 72 may face the resistive film 50 in the normal direction Z.

[0152] Each second mesa portion 72 defines a T-shaped mesa together with one main mesa portion 70 in plan view. From another perspective, each second mesa portion 72 defines an H-shaped mesa together with two main mesa portions 70 in plan view. In this embodiment, the multiple second mesa portions 72 are formed on the same straight line along the second direction Y.

[0153] Of course, the second mesa portions 72 may be formed offset from one another in the first direction X so as not to be positioned on the same straight line in the second direction Y. Even in this case, the second mesa portions 72 are formed at intervals from the first mesa portion 71 in the first direction X so as not to face the first mesa portion 71 in the second direction Y.

[0154] The semiconductor device 1 includes a plurality of p-type fourth well regions 75 formed in the first termination region 15A in regions along the plurality of first trench resistance structures 42. In this embodiment, the fourth well regions 75 have a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the fourth well regions 75 may be lower than that of the body region 17. It is preferable that the p-type impurity concentration of the fourth well regions 75 be approximately equal to the p-type impurity concentration of the first well region 35.

[0155] The plurality of fourth well regions 75 cover the wall surfaces of the corresponding first trench resistance structures 42 at intervals from the second trench resistance structures 43, the first dummy trench structures 61, and the second dummy trench structures 62, and are electrically connected to the body region 17 in the surface portion of the active surface 8.

[0156] Each fourth well region 75 includes a portion covering the wall surface of each first trench resistance structure 42 in each first mesa portion 71, and faces each first dummy trench structure 61 in the first direction X. In this embodiment, each fourth well region 75 has a portion facing the second trench resistance structure 43 in the second direction Y, and a portion facing the second dummy trench structure 62 in the second direction Y.

[0157] The multiple fourth well regions 75 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the multiple fourth well regions 75 are located on the active surface 8 side relative to the depth positions of the bottoms of the multiple second well regions 36. The bottoms of the multiple fourth well regions 75 are formed at approximately the same depth as the bottoms of the multiple first well regions 35. The multiple fourth well regions 75 form pn junctions with the first semiconductor region 6.

[0158] The semiconductor device 1 includes a plurality of p-type fifth well regions 76 formed in the first termination region 15A in regions along the plurality of second trench resistance structures 43. In this embodiment, the fifth well regions 76 have a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the fifth well regions 76 may be lower than that of the body region 17. It is preferable that the p-type impurity concentration of the fifth well regions 76 be approximately equal to the p-type impurity concentration of the plurality of fourth well regions 75 (second well regions 36).

[0159] The plurality of fifth well regions 76 cover the wall surfaces of the corresponding second trench resistance structures 43 at intervals from the first trench resistance structure 42, the first dummy trench structure 61, and the second dummy trench structure 62, and are electrically connected to the body region 17 in the surface portion of the active surface 8. Each fifth well region 76 includes a portion covering the wall surface of each second trench resistance structure 43 in each second mesa portion 72, and faces the second dummy trench structure 62 in the first direction X. In this embodiment, each fifth well region 76 faces the first trench resistance structure 42 in the second direction Y, but does not face the first dummy trench structure 61 in the second direction Y.

[0160] The plurality of fifth well regions 76 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The bottoms of the plurality of fifth well regions 76 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the plurality of fourth well regions 75 (first well regions 35). The bottoms of the plurality of fifth well regions 76 are formed at approximately the same depth as the bottoms of the plurality of second well regions 36. The plurality of fifth well regions 76 form pn junctions with the first semiconductor region 6.

[0161] The semiconductor device 1 includes a plurality of p-type sixth well regions 77 formed in the first termination region 15A in regions along the plurality of first dummy trench structures 61. In this embodiment, the sixth well regions 77 have a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the sixth well regions 77 may be lower than that of the body region 17. It is preferable that the p-type impurity concentration of the sixth well regions 77 be approximately equal to the p-type impurity concentration of the fourth well region 75 (first well region 35).

[0162] The plurality of sixth well regions 77 cover the wall surfaces of the corresponding first dummy trench structures 61 at intervals from the first trench resistance structure 42, the second trench resistance structure 43, and the second dummy trench structure 62, and are electrically connected to the body region 17 in the surface portion of the active surface 8. Each sixth well region 77 includes a portion covering the wall surface of each first dummy trench structure 61 in each first mesa portion 71, and faces the first trench resistance structure 42 in the first direction X.

[0163] Each sixth well region 77 may be formed in each first mesa portion 71 at a distance from each fourth well region 75, or may be integrated with each fourth well region 75. Each sixth well region 77 faces the second dummy trench structure 62 in the second direction Y, but does not face the second trench resistance structure 43 in the second direction Y.

[0164] The plurality of sixth well regions 77 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The bottoms of the plurality of sixth well regions 77 are located closer to the active surface 8 than the depth positions of the bottoms of the plurality of fifth well regions 76 (second well regions 36). The bottoms of the plurality of sixth well regions 77 are formed at approximately the same depth as the bottoms of the plurality of fourth well regions 75 (first well regions 35). The plurality of sixth well regions 77 form pn junctions with the first semiconductor region 6.

[0165] The semiconductor device 1 includes a plurality of p-type seventh well regions 78 formed in the first termination region 15A in regions along the plurality of second dummy trench structures 62. In this embodiment, the seventh well regions 78 have a higher p-type impurity concentration than the body region 17. Of course, the p-type impurity concentration of the seventh well regions 78 may be lower than that of the body region 17. It is preferable that the p-type impurity concentration of the seventh well regions 78 be approximately equal to the p-type impurity concentration of the fifth well region 76 (second well region 36).

[0166] The multiple seventh well regions 78 cover the wall surfaces of the corresponding second dummy trench structures 62 at intervals from the first trench resistance structure 42, the second trench resistance structure 43, and the first dummy trench structure 61, and are electrically connected to the body region 17 in the surface portion of the active surface 8. Each seventh well region 78 includes a portion covering the wall surface of each second dummy trench structure 62 in each second mesa portion 72, and faces the second trench resistance structure 43 in the first direction X.

[0167] Each seventh well region 78 may be formed in each second mesa portion 72 at a distance from each fifth well region 76, or may be integrated with each fifth well region 76. Each seventh well region 78 has a portion facing the first dummy trench structure 61 in the second direction Y, and a portion facing the first trench resistance structure 42 in the second direction Y.

[0168] The multiple seventh well regions 78 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The bottoms of the multiple seventh well regions 78 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the multiple sixth well regions 77 (fourth well regions 75). The bottoms of the multiple seventh well regions 78 are formed at approximately the same depth as the bottoms of the multiple fifth well regions 76 (second well regions 36). The multiple seventh well regions 78 form pn junctions with the first semiconductor region 6.

[0169] The semiconductor device 1 includes a plurality of p-type second contact regions 79 formed in the first termination region 15A in regions along the plurality of second trench resistance structures 43. The second contact regions 79 have a higher p-type impurity concentration than the body region 17. The p-type impurity concentration of the second contact regions 79 is higher than the fifth well region 76. It is preferable that the p-type impurity concentration of the second contact regions 79 be approximately equal to the p-type impurity concentration of the first contact region 38.

[0170] The second contact regions 79 cover the wall surfaces of the corresponding second trench resistance structures 43 in the corresponding fifth well regions 76. The second contact regions 79 are formed in a one-to-many correspondence with the second trench resistance structures 43. The second contact regions 79 are formed at intervals along the corresponding second trench resistance structures 43. The second contact regions 79 are extended from the corresponding fifth well regions 76 along the wall surfaces of the corresponding second trench resistance structures 43 to the surface layer of the body region 17 and exposed from the active surface 8.

[0171] In this embodiment, the multiple second contact regions 79 are each formed in a strip shape extending in the first direction X in a plan view. The length of the multiple second contact regions 79 in the first direction X is preferably equal to or greater than the fifth width W5 described above. The length of the multiple second contact regions 79 is preferably greater than the distance between two second contact regions 79 adjacent to each other in the first direction X. The length of the multiple second contact regions 79 is preferably less than the distance between the first mesa portion 71 and the second mesa portion 72. The length of the multiple second contact regions 79 is preferably approximately equal to the length of the multiple first contact regions 38.

[0172] The multiple second contact regions 79 include an outermost second contact region 79 that covers a region along the end of each second trench resistance structure 43. The outermost second contact region 79 is preferably formed at a distance from the second mesa portion 72. In other words, the outermost second contact region 79 preferably faces the first trench resistance structure 42 in the second direction Y, but does not face the first dummy trench structure 61 in the second direction Y.

[0173] For example, in the first direction X, the distance between the second mesa portion 72 and the outermost second contact region 79 may be less than the length of the second contact region 79. The distance between the second mesa portion 72 and the outermost second contact region 79 may be less than the fifth width W5 described above. It is particularly preferable that the distance between the second mesa portion 72 and the outermost second contact region 79 be less than the width (seventh interval I7) of the second mesa portion 72.

[0174] The multiple second contact regions 79 along one second trench resistance structure 43 face the multiple second contact regions 79 along the other second trench resistance structures 43 in the second direction Y. That is, in this embodiment, the multiple second contact regions 79 are arranged in a matrix with gaps in between in the first direction X and the second direction Y as a whole in a plan view. The multiple second contact regions 79 may face the multiple first contact regions 38 in the second direction Y. In this case, the multiple second contact regions 79 may be arranged in a matrix together with the multiple first contact regions 38.

[0175] The multiple second contact regions 79 along one second trench resistance structure 43 may be arranged offset in the first direction X so as to face in the second direction Y regions between the multiple second contact regions 79 along other second trench resistance structures 43. That is, the multiple second contact regions 79 may be arranged in a staggered pattern overall in a plan view with intervals in the first direction X and the second direction Y. The multiple second contact regions 79 may face in the second direction Y regions between the multiple first contact regions 38. In this case, the multiple second contact regions 79 may be arranged in a staggered pattern together with the multiple first contact regions 38.

[0176] The semiconductor device 1 includes a plurality of p-type third contact regions 80 formed in the first termination region 15A in regions along the plurality of second dummy trench structures 62. The third contact regions 80 have a higher p-type impurity concentration than the body region 17. The p-type impurity concentration of the third contact regions 80 is higher than the seventh well region 78. It is preferable that the p-type impurity concentration of the third contact regions 80 be approximately equal to the p-type impurity concentration of the second contact region 79 (first contact region 38).

[0177] The plurality of third contact regions 80 cover the wall surfaces of the corresponding second dummy trench structures 62 in the corresponding seventh well regions 78. The plurality of third contact regions 80 are formed in a one-to-many correspondence with each second dummy trench structure 62. The plurality of third contact regions 80 are formed at intervals along the corresponding second dummy trench structures 62. The plurality of third contact regions 80 are extended from the corresponding seventh well regions 78 along the wall surfaces of the corresponding second dummy trench structures 62 to the surface layer portion of the body region 17 and are exposed from the active surface 8.

[0178] In this embodiment, the multiple third contact regions 80 are each formed in a strip shape extending in the first direction X in a plan view. The length of the multiple third contact regions 80 in the first direction X is preferably equal to or greater than the seventh width W7 described above. The length of the multiple third contact regions 80 is preferably greater than the distance between two adjacent third contact regions 80 in the first direction X. The length of the multiple third contact regions 80 is preferably less than the distance between the first mesa portion 71 and the second mesa portion 72. The length of the multiple third contact regions 80 is preferably approximately equal to the length of the multiple second contact regions 79 (first contact regions 38).

[0179] The multiple third contact regions 80 face the first dummy trench structures 61 in the second direction Y in a region on the third connection surface 10C side of the first mesa portion 71. The multiple third contact regions 80 are formed at intervals along each second dummy trench structure 62 so that the first mesa portion 71 is located between two adjacent third contact regions 80. It is preferable that the multiple third contact regions 80 are formed at intervals from the first mesa portion 71 in the first direction X so as not to face the first mesa portion 71.

[0180] For example, in the first direction X, the distance between the first mesa portion 71 and the third contact region 80 is preferably less than the length of the third contact region 80. The distance between the first mesa portion 71 and the third contact region 80 is preferably less than the seventh width W7 described above. It is particularly preferable that the distance between the first mesa portion 71 and the third contact region 80 be less than the width (fifth interval I5) of the first mesa portion 71.

[0181] The multiple third contact regions 80 include at least one (in this example, one) outermost third contact region 80 formed in the range between the first mesa portion 71 and the second mesa portion 72. The outermost third contact region 80 faces the first trench resistor structure 42 in the second direction Y. The outermost third contact region 80, together with the outermost second contact region 79, sandwiches the second mesa portion 72 therebetween.

[0182] The outermost third contact region 80 is preferably formed at a distance from the first mesa portion 71 and the second mesa portion 72 in the first direction X. In other words, the outermost third contact region 80 preferably faces the first trench resistance structure 42 in the second direction Y, but does not face the first dummy trench structure 61 in the second direction Y.

[0183] For example, in the first direction X, the distance between the second mesa portion 72 and the third contact region 80 is preferably less than the length of the third contact region 80. The distance between the second mesa portion 72 and the third contact region 80 is preferably less than the aforementioned seventh width W7.

[0184] It is particularly preferable that the distance between the second mesa portion 72 and the outermost third contact region 80 be less than the width (seventh interval I7) of the second mesa portion 72. It is preferable that the distance between the outermost second contact region 79 and the outermost third contact region 80 adjacent to each other across the second mesa portion 72 be approximately equal to the distance between two adjacent third contact regions 80 across the first mesa portion 71.

[0185] The multiple third contact regions 80 along one second dummy trench structure 62 face the multiple third contact regions 80 along other second dummy trench structures 62 in the second direction Y. That is, in this embodiment, the multiple third contact regions 80 are arranged in a matrix with gaps in the first direction X and the second direction Y as a whole in a plan view. In this case, the multiple third contact regions 80 may be arranged in a matrix together with the multiple second contact regions 79. Furthermore, the multiple third contact regions 80 may be arranged in a matrix together with the multiple first contact regions 38.

[0186] The multiple third contact regions 80 along one second dummy trench structure 62 may be arranged offset in the first direction X so as to face the multiple third contact regions 80 along another second dummy trench structure 62 in the second direction Y. In other words, the multiple third contact regions 80 may be arranged in a staggered pattern overall in a plan view with intervals in the first direction X and the second direction Y. In this case, the multiple third contact regions 80 may be arranged in a staggered pattern together with the multiple second contact regions 79. Furthermore, the multiple third contact regions 80 may be arranged in a staggered pattern together with the multiple first contact regions 38.

[0187] 13 , semiconductor device 1 includes a termination dummy structure 85 formed on first main surface 3 (active surface 8) in first termination region 15A. Termination dummy structure 85 is incorporated in active surface 8 (first termination region 15A) for one purpose of alleviating local electric field concentration in the vicinity of gate resistor 40 and improving breakdown voltage (e.g., breakdown voltage). The presence or absence of termination dummy structure 85 is optional, and a configuration not including termination dummy structure 85 may also be employed.

[0188] The termination dummy structure 85 is arranged in a region on the first side surface 5A side (first connection surface 10A side) of the gate resistor 40. The termination dummy structure 85 is formed at the end edge of the active surface 8. The termination dummy structure 85 faces the gate resistor 40 and the dummy structure 55 in the second direction Y. The termination dummy structure 85 faces the active region 12 in the second direction Y with the gate resistor 40 therebetween, faces the first peripheral region 14A in the second direction Y with the first dummy structure 56 therebetween, and faces the second peripheral region 14B in the second direction Y with the second dummy structure 57 therebetween.

[0189] The termination dummy structure 85 will be specifically described below with reference to Figures 24 to 26. Figure 24 is an enlarged plan view showing the layout of the termination dummy structure 85. Figure 25 is a further enlarged plan view showing the layout of the termination dummy structure 85. Figure 26 is a cross-sectional view taken along line XXVI-XXVI shown in Figure 25.

[0190] 24 to 26 , termination dummy structure 85 includes at least one trench termination structure 86 (in this embodiment, multiple trench termination structures 86) formed in first termination region 15A. A source potential VS is applied to the multiple trench termination structures 86 as a second potential. The multiple trench termination structures 86 are each formed in a strip shape extending in first direction X and are arranged at intervals in second direction Y. The multiple trench termination structures 86 face second trench resistor structure 43 and second dummy trench structure 62 in second direction Y.

[0191] The plurality of trench termination structures 86 are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D. In this embodiment, the trench termination structure 86 penetrates both the third connection surface 10C and the fourth connection surface 10D and is exposed from both the third connection surface 10C and the fourth connection surface 10D. The plurality of trench termination structures 86 penetrates the body region 17 to reach the first semiconductor region 6. The plurality of trench termination structures 86 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0192] One trench termination structure 86 will be described below. The trench termination structure 86 has an eighth width W8 in the second direction Y and an eighth depth D8 in the normal direction Z. The eighth width W8 is preferably approximately equal to the fifth width W5 (second width W2) described above. The eighth width W8 may be 0.1 μm or more and 3 μm or less. The eighth width W8 is preferably 0.5 μm or more and 2 μm or less.

[0193] The eighth depth D8 is equal to or greater than the fourth depth D4 (first depth D1) described above. In this embodiment, the eighth depth D8 is greater than the fourth depth D4 (first depth D1). The eighth depth D8 is preferably 1.5 to 3 times the fourth depth D4 (first depth D1). In this embodiment, the eighth depth D8 is approximately equal to the fifth depth D5 (second depth D2) described above. The eighth depth D8 is approximately equal to the outer circumferential depth DO described above. The eighth depth D8 may be 0.1 μm to 5 μm. It is particularly preferable that the eighth depth D8 be 2.5 μm or less.

[0194] The multiple trench termination structures 86 are arranged at an eighth interval I8 from one another in the second direction Y. The eighth interval I8 is preferably 0.5 to 2 times the eighth width W8. It is particularly preferable that the eighth interval I8 be less than the eighth width W8. It is preferable that the eighth width W8 be approximately equal to the aforementioned fourth interval I4 (first interval I1). The eighth width W8 may be 0.1 μm to 2.5 μm. It is preferable that the eighth width W8 be 0.5 μm to 1.5 μm.

[0195] In this embodiment, the outermost trench termination structure 86 on the gate resistor 40 side is arranged adjacent to the outermost second trench resistance structure 43 in the second direction Y at the fourth interval I4 described above from the outermost second trench resistance structure 43. In addition, in this embodiment, the outermost trench termination structure 86 is arranged adjacent to the outermost second dummy trench structure 62 in the second direction Y at the sixth interval I6 described above from the outermost second dummy trench structure 62.

[0196] The trench termination structure 86 includes a termination trench 87, a termination insulating film 88, and a termination buried electrode 89. The termination trench 87 is formed in the active surface 8 and defines the wall surface of the trench termination structure 86. The sidewall of the termination trench 87 communicates with the third connection surface 10C. The bottom wall of the termination trench 87 communicates with the outer peripheral surface 9.

[0197] The termination insulating film 88 covers the wall surface of the termination trench 87 and is connected to the main surface insulating film 16 at the active surface 8. The termination insulating film 88 is connected to the main surface insulating film 16 at the communicating portion of the third connecting surface 10C and the communicating portion of the outer peripheral surface 9. The termination insulating film 88 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0198] In this embodiment, the termination insulating film 88 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the termination insulating film 88 includes a silicon oxide film made of an oxide of the chip 2. The termination buried electrode 89 is buried in the termination trench 87 with the termination insulating film 88 sandwiched therebetween. The termination buried electrode 89 may include conductive polysilicon.

[0199] Semiconductor device 1 includes a plurality of p-type eighth well regions 90 formed in first termination region 15A in regions along the plurality of trench termination structures 86. In this embodiment, eighth well region 90 has a higher p-type impurity concentration than body region 17. Of course, the p-type impurity concentration of eighth well region 90 may be lower than that of body region 17. The p-type impurity concentration of eighth well region 90 is preferably approximately equal to the p-type impurity concentration of second well region 36 (first well region 35).

[0200] The plurality of eighth well regions 90 cover the wall surfaces of the corresponding trench termination structures 86 at intervals from adjacent trench termination structures 86, and are electrically connected to body region 17 in the surface portion of active surface 8. The plurality of eighth well regions 90 extend in a strip shape along the corresponding trench termination structures 86 in a plan view, and are exposed from third connection surface 10C and fourth connection surface 10D.

[0201] The multiple eighth well regions 90 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the multiple eighth well regions 90 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the multiple first well regions 35. The bottoms of the multiple eighth well regions 90 are formed at approximately the same depth as the bottoms of the multiple second well regions 36. The multiple eighth well regions 90 form pn junctions with the first semiconductor region 6.

[0202] 4 again, semiconductor device 1 includes dummy structures 55 and termination dummy structures 85 formed on first main surface 3 (active surface 8) in second termination region 15B. Semiconductor device 1 does not include gate resistor 40 in second termination region 15B. Dummy structures 55 on the second termination region 15B side are arranged in a region on the fourth side surface 5D side (fourth connection surface 10D side) of active region 12, and face active region 12 and peripheral region 14 in second direction Y.

[0203] Similar to the first dummy structure 56 on the first termination region 15A side, the dummy structure 55 on the second termination region 15B side includes a plurality of dummy trench structures 60 (a plurality of first dummy trench structures 61 and a plurality of second dummy trench structures 62). The plurality of dummy trench structures 60 on the second termination region 15B side penetrate both the third connection surface 10C and the fourth connection surface 10D and are exposed from both the third connection surface 10C and the fourth connection surface 10D. Otherwise, the configuration of the dummy structure 55 on the second termination region 15B side is similar to the configuration of the dummy structure 55 (first dummy structure 56) on the first termination region 15A side.

[0204] The termination dummy structure 85 on the second termination region 15B side has a configuration similar to the configuration of the termination dummy structure 85 on the first termination region 15A side. Other descriptions of the termination dummy structure 85 on the second termination region 15B side are the same as those of the termination dummy structure 85 on the first termination region 15A side.

[0205] Although specific illustrations are omitted, semiconductor device 1 also includes, in second termination region 15B, a plurality of sixth well regions 77, a plurality of seventh well regions 78, a plurality of second contact regions 79, and a plurality of eighth well regions 90. The descriptions of the sixth well region 77, the seventh well region 78, the second contact region 79, and the eighth well region 90 on the first termination region 15A side apply to the descriptions of the sixth well region 77, the seventh well region 78, the second contact region 79, and the eighth well region 90 on the second termination region 15B side.

[0206] Next, the structure of peripheral region 13 will be described with reference to the cross-sectional view of Fig. 28. Referring to Fig. 28, semiconductor device 1 includes a p-type outer well region 91 formed in a surface layer portion of peripheral surface 9. Outer well region 91 has a lower p-type impurity concentration than first contact region 38.

[0207] In this embodiment, the p-type impurity concentration of the outer well region 91 is higher than that of the body region 17. Of course, the p-type impurity concentration of the outer well region 91 may be lower than that of the body region 17. It is preferable that the outer well region 91 has a p-type impurity concentration approximately equal to that of the first well region 35 (second well region 36).

[0208] The outer well region 91 is formed in a plan view at a distance from the periphery of the outer peripheral surface 9 (first to fourth side surfaces 5A to 5D) toward the active surface 8, and extends in a band shape along the active surface 8. In this embodiment, the outer well region 91 is formed in a ring shape (specifically, a quadrangular ring) that surrounds the active surface 8 in a plan view. The outer well region 91 extends from the surface layer portion of the outer peripheral surface 9 toward the surface layer portions of the first to fourth connecting surfaces 10A to 10D, and covers the first to fourth connecting surfaces 10A to 10D.

[0209] The outer well region 91 is electrically connected to the body region 17 in a surface layer portion of the active surface 8. The outer well region 91 is connected to the second well region 36 at the communication portion between the third connection surface 10C (fourth connection surface 10D) and the first trench source structure 25. The outer well region 91 is connected to the third well region 37 at the communication portion between the third connection surface 10C (fourth connection surface 10D) and the second trench source structure 30.

[0210] The outer well region 91 is connected to the sixth well region 77 at the communication portion between the third connection surface 10C (fourth connection surface 10D) and the first dummy trench structure 61. The outer well region 91 is connected to the seventh well region 78 at the communication portion between the third connection surface 10C (fourth connection surface 10D) and the second dummy trench structure 62. The outer well region 91 is connected to the eighth well region 90 at the communication portion between the third connection surface 10C (fourth connection surface 10D) and the trench termination structure 86.

[0211] The outer well region 91 is formed at a distance from the bottom of the first semiconductor region 6 toward the outer circumferential surface 9, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6. The outer well region 91 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first trench source structure 25 (second trench resistance structure 43). The bottom of the outer well region 91 is located closer to the bottom of the first semiconductor region 6 than the bottom of the first contact region 38. The bottom of the outer well region 91 is preferably formed at a depth substantially equal to the bottom of the second well region 36. The outer well region 91 forms a pn junction with the first semiconductor region 6.

[0212] The semiconductor device 1 includes a p-type outer contact region 92 formed in a surface layer portion of the outer well region 91. The outer contact region 92 has a higher p-type impurity concentration than the body region 17. The p-type impurity concentration of the outer contact region 92 is higher than that of the outer well region 91. It is preferable that the p-type impurity concentration of the outer contact region 92 be approximately equal to the p-type impurity concentration of the first contact region 38 (second contact region 79).

[0213] The outer contact region 92 is formed in the surface layer portion of the outer well region 91 at a distance from the periphery of the active surface 8 (first to fourth connection surfaces 10A to 10D) and the periphery of the outer peripheral surface 9 (first to fourth side surfaces 5A to 5D) in plan view, and is formed in a band shape extending along the active surface 8. In this embodiment, the outer contact region 92 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in plan view.

[0214] The outer contact region 92 is formed at a distance from the bottom of the outer well region 91 toward the outer peripheral surface 9, and faces the first semiconductor region 6 across a part of the outer well region 91. The outer contact region 92 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first trench source structure 25 (second trench resistance structure 43). The bottom of the outer contact region 92 is preferably formed at a depth position substantially equal to the bottom of the first contact region 38 (second contact region 79).

[0215] Semiconductor device 1 includes at least one (preferably two to twenty) p-type field region 93 formed in a surface layer portion of outer peripheral surface 9 in a region between the periphery of outer peripheral surface 9 and outer well region 91. In this embodiment, semiconductor device 1 includes four field regions 93. The multiple field regions 93 are formed in an electrically floating state and relieve the electric field within chip 2 at outer peripheral surface 9.

[0216] The number, width, depth, p-type impurity concentration, etc. of the field regions 93 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The field regions 93 may have a lower p-type impurity concentration than the outer contact region 92. The field regions 93 may have a higher p-type impurity concentration than the outer well region 91. The field regions 93 may have a lower p-type impurity concentration than the outer well region 91.

[0217] The multiple field regions 93 are arranged at intervals from the outer well region 91 side to the peripheral edge side of the outer peripheral surface 9. The multiple field regions 93 are formed in a band shape extending along the active surface 8 in a plan view. In this embodiment, the multiple field regions 93 are formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8 in a plan view.

[0218] The plurality of field regions 93 are formed at intervals from the bottom of the first semiconductor region 6 toward the outer circumferential surface 9, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The plurality of field regions 93 are located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first trench source structure 25. The bottoms of the plurality of field regions 93 are located closer to the bottom of the first semiconductor region 6 than the bottom of the first contact region 38. The bottoms of the plurality of field regions 93 may be formed at a depth position substantially equal to the bottom of the second well region 36.

[0219] The semiconductor device 1 includes a sidewall wiring 95 formed on the outer peripheral surface 9 so as to cover at least one of the first to fourth connecting surfaces 10A to 10D. Specifically, the sidewall wiring 95 is disposed on the main surface insulating film 16. The sidewall wiring 95 also functions as a sidewall structure that reduces a step formed between the active surface 8 and the outer peripheral surface 9.

[0220] The sidewall wiring 95 is preferably formed in a strip shape extending along at least one of the third connecting surface 10C and the fourth connecting surface 10D. In this embodiment, the sidewall wiring 95 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connecting surfaces 10A to 10D so as to surround the active surface 8 in a plan view. The portions of the sidewall wiring 95 that cover the four corners of the active surface 8 are formed in a curved shape toward the outer peripheral surface 9.

[0221] The sidewall wiring 95 includes a portion extending in a film-like manner along the outer peripheral surface 9 and a portion extending in a film-like manner along the first to fourth connecting surfaces 10A to 10D. The portion of the sidewall wiring 95 located on the outer peripheral surface 9 may cover the outer peripheral surface 9 in a region on the outer peripheral surface 9 side of the active surface 8. The portion of the sidewall wiring 95 located on the outer peripheral surface 9 may have a thickness less than the thickness of the active plateau 11 (peripheral depth DO).

[0222] The sidewall wiring 95 faces the outer well region 91 on the outer peripheral surface 9, with the main surface insulating film 16 therebetween. The sidewall wiring 95 may also face the outer contact region 92, with the main surface insulating film 16 therebetween. In this embodiment, the sidewall wiring 95 is formed at a distance from the field region 93 toward the active surface 8 in plan view.

[0223] The sidewall wiring 95 faces the second well region 36, the third well region 37, the sixth well region 77, the seventh well region 78, the eighth well region 90, and the outer well region 91 at the first to fourth connecting surfaces 10A to 10D, with the main surface insulating film 16 interposed therebetween. In this embodiment, the sidewall wiring 95 also faces the body region 17, with the main surface insulating film 16 interposed therebetween.

[0224] The sidewall wiring 95 covers the exposed portions of the first trench source structure 25, the second trench source structure 30, the first dummy trench structure 61, the second dummy trench structure 62, and the trench termination structure 86 at the first to fourth connection surfaces 10A to 10D.

[0225] As a result, the sidewall wiring 95 is electrically connected to the first trench source structure 25, the second trench source structure 30, the first dummy trench structure 61, the second dummy trench structure 62, and the trench termination structure 86. In other words, the sidewall wiring 95 applies the source potential VS to the connection target from the outer circumferential surface 9 side.

[0226] The sidewall wiring 95 has an overlapping portion 96 that extends from at least one of the first to fourth connecting surfaces 10A to 10D onto the edge of the active surface 8. The overlapping portion 96 covers the active surface 8 in a film-like manner in plan view and is formed in a band shape that extends along the edge of the active surface 8. In this form, the overlapping portion 96 is formed in a ring shape (specifically, a quadrangular ring) that surrounds the inner portion of the active surface 8 in plan view.

[0227] The overlap portion 96 is electrically connected to the first trench source structure 25 , the second trench source structure 30 , the first dummy trench structure 61 , the second dummy trench structure 62 and the trench termination structure 86 above the active surface 8 .

[0228] In this embodiment, the sidewall wiring 95 includes conductive polysilicon and is formed integrally with the first buried source electrode 28, the second buried source electrode 33, the first dummy buried electrode 65, the second dummy buried electrode 68, and the terminal buried electrode 89. Of course, the sidewall wiring 95 may be formed separately from the first buried source electrode 28, the second buried source electrode 33, the first dummy buried electrode 65, the second dummy buried electrode 68, and the terminal buried electrode 89.

[0229] The semiconductor device 1 includes an interlayer insulating film 99 that covers the main surface insulating film 16. The interlayer insulating film 99 covers the active surface 8, the outer peripheral surface 9, and the first to fourth connecting surfaces 10A to 10D with the main surface insulating film 16 sandwiched therebetween. The interlayer insulating film 99 covers the trench gate structure 20, the first trench source structure 25, the second trench source structure 30, the first trench resistor structure 42, the second trench resistor structure 43, the first dummy trench structure 61, the second dummy trench structure 62, and the trench termination structure 86 on the active surface 8.

[0230] The interlayer insulating film 99 covers the resistive film 50 in the first termination region 15A, and also covers the plurality of trench resistance structures 41 with the resistive film 50 in between. The interlayer insulating film 99 covers the outer well region 91, the outer contact region 92, and the plurality of field regions 93 with the main surface insulating film 16 in between at the outer peripheral surface 9. The interlayer insulating film 99 covers the sidewall wiring 95 at the first to fourth connecting surfaces 10A to 10D.

[0231] In this embodiment, the interlayer insulating film 99 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the wall portions of the interlayer insulating film 99 may be formed at intervals inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9. The interlayer insulating film 99 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer insulating film 99 includes a silicon oxide film.

[0232] 1 to 13, semiconductor device 1 includes a gate electrode 100 disposed on an interlayer insulating film 99. Gate electrode 100 has a resistance value lower than that of gate resistor 40. Specifically, gate electrode 100 has a resistance value lower than that of trench resistor structure 41. Gate electrode 100 also has a resistance value lower than that of resistive film 50.

[0233] The gate electrode 100 is preferably thicker than the resistive film 50. The gate electrode 100 is preferably thicker than the interlayer insulating film 99. The gate electrode 100 may have a thickness of 0.5 μm or more and 10 μm or less. The thickness of the gate electrode 100 is preferably 1 μm or more and 5 μm or less.

[0234] The gate electrode 100 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. The gate electrode 100 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the gate electrode 100 has a layered structure including a Ti film and an Al alloy film (an AlSiCu alloy film in this embodiment) stacked in this order from the chip 2 side. The gate electrode 100 may also be referred to as a "gate metal."

[0235] In this embodiment, the gate electrode 100 includes a gate pad 101, a gate wiring 102, and a gate sub-pad 103. A gate potential VG is applied to the gate pad 101 from the outside. In this embodiment, the gate pad 101 is disposed in a region along the center of the first connection surface 10A in a plan view.

[0236] In this embodiment, gate pad 101 is disposed on an inner portion of active surface 8 at a distance from the periphery of active surface 8, and is not disposed on outer peripheral surface 9. Gate pad 101 is disposed in a region overlapping active region 12 and first termination region 15A in plan view. Gate pad 101 covers a plurality of trench gate structures 20 and a plurality of first trench source structures 25 in active region 12 with interlayer insulating film 99 interposed therebetween.

[0237] The gate pad 101 is arranged in a region overlapping the gate resistor 40 in a plan view. In this embodiment, the gate pad 101 is formed at a distance from the dummy structure 55 and the termination dummy structure 85 in a plan view. Of course, the gate pad 101 may be arranged in a region overlapping either or both of the dummy structure 55 and the termination dummy structure 85 in a plan view.

[0238] The gate pad 101 penetrates the interlayer insulating film 99 in the first termination region 15A and is electrically connected to the gate resistor 40. Specifically, the gate pad 101 penetrates the interlayer insulating film 99 and is connected to the resistive film 50. In this embodiment, the gate pad 101 penetrates the interlayer insulating film 99 and is connected to the center of the resistive film 50.

[0239] The gate pad 101 faces one or more (in this embodiment, multiple) trench resistance structures 41 with the resistive film 50 interposed therebetween. In this embodiment, the gate pad 101 faces a plurality of first trench resistance structures 42 and a plurality of second trench resistance structures 43 with the resistive film 50 interposed therebetween.

[0240] In this embodiment, the gate pad 101 includes a pad main body 104 and an extraction portion 105. The pad main body 104 is a portion to which a gate potential VG is applied from the outside. In this embodiment, the pad main body 104 is disposed on a portion of the interlayer insulating film 99 that covers the active region 12, and faces the gate resistor 40 in the second direction Y in plan view.

[0241] The pad body 104 covers the trench gate structures 20 and the first trench source structures 25 with the interlayer insulating film 99 sandwiched therebetween. In this embodiment, the pad body 104 is formed to be wider than the gate resistor 40 (trench gate structures 20) in the first direction X.

[0242] In this embodiment, the pad body 104 is formed in a quadrangular shape in a plan view. The pad body 104 preferably has a planar area of ​​25% or less of the planar area of ​​the first main surface 3. The planar area of ​​the pad body 104 is preferably 10% or less of the planar area of ​​the first main surface 3.

[0243] The lead-out portion 105 is a portion that electrically connects the pad main body 104 to the gate resistor 40. The lead-out portion 105 is led out in a strip shape from the pad main body 104 onto a portion of the interlayer insulating film 99 that covers the gate resistor 40. In this embodiment, the lead-out portion 105 is formed to be narrower than the pad main body 104 in the first direction X. Specifically, the lead-out portion 105 is formed to be narrower than the gate resistor 40 (trench gate structure 20) in the first direction X.

[0244] The lead-out portion 105 is connected to the gate resistor 40 via a first resistor opening 106 formed in the interlayer insulating film 99. Specifically, the lead-out portion 105 is connected to the resistive film 50 within the first resistor opening 106. In other words, the lead-out portion 105 is electrically connected to the plurality of trench resistor structures 41 via the resistive film 50.

[0245] As a result, the pad body 104 is electrically connected to the plurality of trench resistance structures 41 and the resistance film 50 via the lead-out portion 105. The lead-out portion 105 faces one or more (a plurality in this embodiment) trench resistance structures 41 with the resistance film 50 interposed therebetween. In this embodiment, the lead-out portion 105 faces the plurality of first trench resistance structures 42 and the plurality of second trench resistance structures 43 with the resistance film 50 interposed therebetween.

[0246] The gate wiring 102 is selectively routed from the first termination region 15A toward the active region 12 so as to transmit the gate potential VG applied to the gate pad 101 to the plurality of trench gate structures 20. In this embodiment, the gate wiring 102 is disposed on an inner portion of the active surface 8 at a distance from the periphery of the active surface 8, and is not disposed on the outer circumferential surface 9.

[0247] In this embodiment, the gate wiring 102 is disposed on the interlayer insulating film 99 at a distance from the gate pad 101 in the first termination region 15A. The gate wiring 102 penetrates the interlayer insulating film 99 at a position different from the gate pad 101 and is electrically connected to the gate resistor 40. Specifically, the gate wiring 102 penetrates the interlayer insulating film 99 and is connected to the resistance film 50. As a result, the gate wiring 102 is electrically connected to the gate pad 101 via the multiple trench resistance structures 41 and the resistance film 50.

[0248] The gate wiring 102 faces one or more (in this embodiment, multiple) trench resistance structures 41 with the resistance film 50 sandwiched therebetween. In this embodiment, the gate wiring 102 faces a plurality of first trench resistance structures 42 and a plurality of second trench resistance structures 43 with the resistance film 50 sandwiched therebetween. The gate wiring 102 extends in a line shape in the active region 12 so as to intersect (specifically, orthogonally intersect) the plurality of trench gate structures 20, and penetrates the interlayer insulating film 99 to be electrically connected to the plurality of trench gate structures 20.

[0249] In this embodiment, the gate wiring 102 includes a first gate wiring 102A, a second gate wiring 102B, and a third gate wiring 102C. The first gate wiring 102A is arranged in a region on the third connection surface 10C side of the gate pad 101, and extends in a line along the first connection surface 10A and the third connection surface 10C. The first gate wiring 102A is electrically connected to the gate pad 101 via a gate resistor 40 in the first termination region 15A, and is electrically connected to a plurality of trench gate structures 20 in the active region 12.

[0250] Specifically, the first gate wiring 102A extends linearly in the first direction X so as to cover the gate resistor 40 and the dummy structure 55 (first dummy structure 56) in the first termination region 15A. The first gate wiring 102A is disposed on a portion of the interlayer insulating film 99 that covers the gate resistor 40, with a gap between the gate pad 101 and the interlayer insulating film 99.

[0251] The first gate wiring 102A is connected to the gate resistor 40 via a second resistor opening 107 formed in the interlayer insulating film 99 at a distance from the first resistor opening 106. The first gate wiring 102A is connected to a region on one end side (the third connection surface 10C side) of the gate resistor 40 at a distance from the connection position of the gate pad 101.

[0252] The first gate wiring 102A is connected to the resistive film 50 in the second resistance opening 107. That is, the first gate wiring 102A is electrically connected to the plurality of trench resistance structures 41 via the resistive film 50. The first gate wiring 102A faces one or more (a plurality in this embodiment) trench resistance structures 41 with the resistive film 50 sandwiched therebetween. In this embodiment, the first gate wiring 102A faces the plurality of first trench resistance structures 42 and the plurality of second trench resistance structures 43 with the resistive film 50 sandwiched therebetween.

[0253] The first gate wiring 102A extends in a line shape in the second direction Y so as to intersect (specifically, perpendicular to) the plurality of trench gate structures 20 in the active region 12. The first gate wiring 102A is electrically connected to the plurality of gate connection electrode films 39 via the plurality of gate openings 108 formed in the interlayer insulating film 99. As a result, the first gate wiring 102A is electrically connected to the plurality of trench gate structures 20 via the plurality of gate connection electrode films 39.

[0254] The connection height position of the first gate wiring 102A with respect to the gate connecting electrode film 39 may be substantially equal to the connection height position of the first gate wiring 102A with respect to the resistive film 50. Of course, the connection height position of the first gate wiring 102A with respect to the gate connecting electrode film 39 may be located closer to the active surface 8 than the connection height position of the second gate wiring 102B with respect to the resistive film 50. Furthermore, the connection height position of the first gate wiring 102A with respect to the gate connecting electrode film 39 may be located higher than the connection height position of the second gate wiring 102B with respect to the resistive film 50.

[0255] The second gate wiring 102B is disposed in a region on the fourth connection surface 10D side of the gate pad 101, and extends in a line along the first connection surface 10A and the fourth connection surface 10D. The second gate wiring 102B is electrically connected to the gate pad 101 via the gate resistor 40 in the first termination region 15A, and is electrically connected to the plurality of trench gate structures 20 in the active region 12. In this embodiment, the second gate wiring 102B is electrically connected to the plurality of trench gate structures 20 electrically connected to the first gate wiring 102A.

[0256] Specifically, the second gate wiring 102B extends linearly in the first direction X so as to cover the gate resistor 40 and the dummy structure 55 (second dummy structure 57) in the first termination region 15A. The second gate wiring 102B is disposed on a portion of the interlayer insulating film 99 that covers the gate resistor 40, with a gap between them and the gate pad 101.

[0257] The second gate wiring 102B is connected to the gate resistor 40 via a third resistor opening 109 formed in the interlayer insulating film 99 at a distance from the first resistor opening 106 and the second resistor opening 107. The second gate wiring 102B is connected to a region on the other end side (the fourth connection surface 10D side) of the gate resistor 40 at a distance from the connection position of the gate pad 101.

[0258] The second gate wiring 102B is connected to the resistive film 50 in the third resistance opening 109. That is, the second gate wiring 102B is electrically connected to the plurality of trench resistance structures 41 via the resistive film 50. The second gate wiring 102B faces one or more (multiple in this embodiment) trench resistance structures 41 with the resistive film 50 sandwiched between them. In this embodiment, the second gate wiring 102B faces the plurality of first trench resistance structures 42 and the plurality of second trench resistance structures 43 with the resistive film 50 sandwiched between them.

[0259] The second gate wiring 102B extends in a line shape in the second direction Y so as to intersect (specifically, perpendicular to) the plurality of trench gate structures 20 in the active region 12. The second gate wiring 102B is electrically connected to the plurality of gate connection electrode films 39 via the plurality of gate openings 108 formed in the interlayer insulating film 99. As a result, the second gate wiring 102B is electrically connected to the plurality of trench gate structures 20 via the plurality of gate connection electrode films 39.

[0260] The connection height position of the second gate wiring 102B with respect to the gate connecting electrode film 39 may be substantially equal to the connection height position of the second gate wiring 102B with respect to the resistance film 50. Of course, the connection height position of the second gate wiring 102B with respect to the gate connecting electrode film 39 may be located closer to the active surface 8 than the connection height position of the second gate wiring 102B with respect to the resistance film 50. Furthermore, the connection height position of the second gate wiring 102B with respect to the gate connecting electrode film 39 may be located higher than the connection height position of the second gate wiring 102B with respect to the resistance film 50.

[0261] The third gate wiring 102C is disposed in a region on the second connection surface 10B side of the gate pad 101, and extends in a line shape in the region between the gate pad 101 and the second connection surface 10B along the second direction Y. In this embodiment, the third gate wiring 102C is connected to the first gate wiring 102A and the second gate wiring 102B in the first termination region 15A, and is electrically connected to the plurality of trench gate structures 20 in the active region 12.

[0262] That is, the third gate wiring 102C is electrically connected to the gate resistor 40 via the first gate wiring 102A, and is electrically connected to the gate resistor 40 via the second gate wiring 102B. The portion of the first gate wiring 102A connected to the gate resistor 40 and the portion of the second gate wiring 102B connected to the gate resistor 40 may be considered as part of the third gate wiring 102C. In this embodiment, the third gate wiring 102C is electrically connected to a plurality of trench gate structures 20 that are electrically connected to the first gate wiring 102A and the second gate wiring 102B in the active region 12.

[0263] The third gate wiring 102C includes a line portion 110, a first branch portion 111, and a second branch portion 112. The line portion 110 extends linearly in the second direction Y in the region between the gate pad 101 and the second connecting surface 10B. The line portion 110 has a first end portion on the gate pad 101 side and a second end portion on the second connecting surface 10B side. The first end portion is formed at a distance from the gate pad 101 toward the second connecting surface 10B. The second end portion is formed at a distance from the second connecting surface 10B toward the gate pad 101.

[0264] The line portion 110 is electrically connected to the plurality of trench gate structures 20 via a plurality of gate openings 108 formed in the interlayer insulating film 99. A plurality of gate connection electrode films 39 may be formed to cover inner portions of the plurality of trench gate structures 20. In this case, the line portion 110 is electrically connected to the plurality of trench gate structures 20 via the plurality of gate connection electrode films 39.

[0265] In this case, the connection height position of the line portion 110 with respect to the gate connecting electrode film 39 may be substantially equal to the connection height position of the first gate wiring 102A (second gate wiring 102B) with respect to the resistive film 50. Of course, the connection height position of the line portion 110 with respect to the gate connecting electrode film 39 may be located closer to the active surface 8 than the connection height position of the second gate wiring 102B with respect to the resistive film 50. Furthermore, the connection height position of the line portion 110 with respect to the gate connecting electrode film 39 may be located higher than the connection height position of the second gate wiring 102B with respect to the resistive film 50.

[0266] The first branch portion 111 connects the line portion 110 and the first gate wiring 102A. The first branch portion 111 is drawn out from the first end of the line portion 110 to one side (the third connection surface 10C side) and extends in a strip shape along the gate pad 101. The first branch portion 111 is connected to a portion of the first gate wiring 102A that covers the dummy structure 55 (first dummy structure 56).

[0267] Of course, the first branch portion 111 may be connected to a portion of the first gate wiring 102A that covers the gate resistor 40. The first branch portion 111, in a portion extending in the second direction Y, is electrically connected to a plurality of trench gate structures 20 via a plurality of gate openings 108 formed in the interlayer insulating film 99. The first branch portion 111 may also be electrically connected to a plurality of trench gate structures 20 via a plurality of gate connection electrode films 39.

[0268] The second branch portion 112 connects the line portion 110 and the second gate wiring 102B. The second branch portion 112 is drawn out from the first end of the line portion 110 to the other side (the fourth connection surface 10D side) and extends in a band shape along the periphery of the gate pad 101. The second branch portion 112 faces the first branch portion 111 in the first direction X, with the gate pad 101 interposed therebetween. The second branch portion 112 is connected to a portion of the second gate wiring 102B that covers the dummy structure 55 (second dummy structure 57).

[0269] Of course, the second branch portion 112 may be connected to a portion of the second gate wiring 102B that covers the gate resistor 40. The second branch portion 112, in a portion extending in the second direction Y, is electrically connected to the plurality of trench gate structures 20 via the plurality of gate openings 108 formed in the interlayer insulating film 99. The second branch portion 112 may also be electrically connected to the plurality of trench gate structures 20 via the plurality of gate connection electrode films 39.

[0270] The gate subpad 103 is disposed on the interlayer insulating film 99 so as to be electrically connected to the gate pad 101 via the gate resistor 40. In this embodiment, the gate subpad 103 is disposed at a distance from the gate pad 101 toward the third connection surface 10C, and faces the gate pad 101 in the first direction X.

[0271] The gate subpad 103 is spaced apart from the first termination region 15A in plan view and disposed on a portion of the interlayer insulating film 99 that covers the active region 12. The gate subpad 103 faces the dummy structure 55 (first dummy structure 56) in the second direction Y in plan view.

[0272] The gate subpad 103 is formed narrower than the gate pad 101 and wider than the gate wiring 102. The gate subpad 103 faces the plurality of trench gate structures 20 and the plurality of first trench source structures 25 with the interlayer insulating film 99 sandwiched therebetween. In this embodiment, the gate subpad 103 is electrically connected to the gate wiring 102. In this embodiment, the gate subpad 103 is connected to the third gate wiring 102C (first branch portion 111). The gate subpad 103 may be disposed at any location as long as it is connected to at least one of the first to third gate wirings 102A to 102C.

[0273] 27 in addition to FIG. 13, the connection configuration of the gate electrode 100 and the gate resistor 40 will be described below. FIG. 27 is an electrical circuit diagram showing the connection configuration of the gate electrode 100 and the gate resistor 40. In FIG. 27, the trench gate structure 20 is indicated by a circuit symbol indicating a MISFET.

[0274] 13 and 27, the gate wiring 102 is electrically connected to the gate pad 101 via a gate resistor 40. In this embodiment, the gate resistor 40 includes a parallel resistor circuit 113 made up of a first resistor portion R1 and a second resistor portion R2. The first resistor portion R1 is formed by a portion of the gate resistor 40 located between the connection portion of the gate pad 101 and the connection portion of the first gate wiring 102A. On the other hand, the second resistor portion R2 is formed by a portion of the gate resistor 40 located between the connection portion of the gate pad 101 and the connection portion of the second gate wiring 102B.

[0275] That is, the first gate wiring 102A is electrically connected to the gate pad 101 via the first resistor R1, and the second gate wiring 102B is electrically connected to the gate pad 101 via the second resistor R2. The resistance value of the first resistor R1 is adjusted by increasing or decreasing the distance between the connection portion of the gate pad 101 and the connection portion of the first gate wiring 102A.

[0276] The resistance value of the second resistor R2 is adjusted by increasing or decreasing the distance between the connection portion of the gate pad 101 and the connection portion of the second gate wiring 102B. The resistance value of the second resistor R2 may be equal to or greater than the resistance value of the first resistor R1, may be less than the resistance value of the first resistor R1, or may be approximately equal to the resistance value of the first resistor R1.

[0277] In this embodiment, the second gate wiring 102B is electrically connected to the trench gate structure 20 that is electrically connected to the first gate wiring 102A. Therefore, the second resistance portion R2 is connected in parallel to the first resistance portion R1, thereby forming a resistive parallel circuit 113. In this embodiment, the third gate wiring 102C is electrically connected to the trench gate structure 20 that is electrically connected to the first gate wiring 102A and the second gate wiring 102B.

[0278] Therefore, one gate wiring 102 including the first to third gate wirings 102A to 102C is electrically connected to the resistive parallel circuit 113 and the trench gate structure 20. The resistance value of the gate resistor 40 (i.e., the resistance value between the gate pad 101 and the gate wiring 102) is measured indirectly by measuring the resistance value between the gate pad 101 and the gate subpad 103.

[0279] The gate resistor 40 reduces the switching speed during switching operation to suppress surge current. In other words, the gate resistor 40 suppresses noise caused by surge current. Because the gate resistor 40 is formed on the first main surface 3 (active surface 8), it is not externally connected to the semiconductor device 1. Therefore, by incorporating the gate resistor 40 on the first main surface 3, the number of components mounted on a circuit board can be reduced.

[0280] Since the gate resistor 40 includes a trench resistor structure 41 embedded in the thickness direction of the chip 2, the area occupied by the gate resistor 40 relative to the first main surface 3 is limited. Therefore, a reduction in the area of ​​the active region 12 due to the introduction of the gate resistor 40 is suppressed. In particular, since the gate resistor 40 is disposed in the termination region 15, a reduction in the area of ​​the active region 12 is appropriately suppressed.

[0281] In this embodiment, the gate resistor 40 has a configuration similar to that on the active region 12 side. Therefore, the electrical influence of the gate resistor 40 on the active region 12 is suppressed, and the electrical influence of the active region 12 on the gate resistor 40 is suppressed. As a result, fluctuations in the electrical characteristics on the active region 12 side are suppressed, and fluctuations in the electrical characteristics on the gate resistor 40 side are suppressed.

[0282] The gate resistor 40 does not necessarily have to have the parallel resistor circuit 113 including the first resistor portion R1 and the second resistor portion R2. Therefore, the gate resistor 40 may be composed of only the first resistor portion R1 or the second resistor portion R2. Such a configuration can be achieved by changing the connection configuration of the gate wiring 102 with respect to the gate resistor 40.

[0283] For example, when the gate resistor 40 is made up of only the first resistance portion R1, the gate wiring 102 (second gate wiring 102B) can be electrically disconnected from the gate resistor 40. When the gate resistor 40 is made up of only the second resistance portion R2, the gate wiring 102 (first gate wiring 102A) can be electrically disconnected from the gate resistor 40. The gate wiring 102 does not need to include all of the first to third gate wirings 102A to 102C at the same time, and it is sufficient if it includes at least one of the first to third gate wirings 102A to 102C.

[0284] 1 to 13 , the semiconductor device 1 includes a source electrode 120 disposed on an interlayer insulating film 99 and spaced apart from the gate electrode 100. The source electrode 120 has a resistance value lower than that of the gate resistor 40. The source electrode 120 is preferably thicker than the resistive film 50. The source electrode 120 is preferably thicker than the interlayer insulating film 99. The source electrode 120 may have a thickness of 0.5 μm or more and 10 μm or less. The thickness of the source electrode 120 is preferably 1 μm or more and 5 μm or less. The thickness of the source electrode 120 is preferably approximately equal to the thickness of the gate electrode 100.

[0285] The source electrode 120 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. The source electrode 120 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the source electrode 120 has a layered structure including a Ti film and an Al alloy film (an AlSiCu alloy film in this embodiment) stacked in this order from the chip 2 side. The source electrode 120 may also be referred to as a "source metal."

[0286] In this embodiment, the source electrode 120 includes a first source pad 121, a second source pad 122, a first source sub-pad 123, a second source sub-pad 124, and a source wiring 125. A source potential VS for the main source is applied from the outside to the first source pad 121. The first source pad 121 is disposed on a portion of the interlayer insulating film 99 that covers the active region 12, in a region between the first gate wiring 102A and the third gate wiring 102C.

[0287] In this embodiment, first source pad 121 covers active region 12 at a distance from peripheral region 14 and termination region 15 in plan view. Of course, first source pad 121 may be disposed in a region overlapping either or both of peripheral region 14 and termination region 15 in plan view.

[0288] The first source pad 121 faces the plurality of trench gate structures 20 with the interlayer insulating film 99 interposed therebetween. The first source pad 121 is electrically connected to the plurality of first trench source structures 25, the source regions 18, and the plurality of first contact regions 38 via a plurality of source openings 126 formed in the interlayer insulating film 99. The first source pad 121 preferably has a planar area larger than that of the gate pad 101.

[0289] A source potential VS for the main source is externally applied to the second source pad 122. The second source pad 122 is disposed on a portion of the interlayer insulating film 99 that covers the active region 12, in a region between the second gate wiring 102B and the third gate wiring 102C.

[0290] In this embodiment, the second source pad 122 covers the active region 12 at a distance from the peripheral region 14 and the termination region 15 in a plan view. Of course, the second source pad 122 may be arranged in a region that overlaps with either or both of the peripheral region 14 and the termination region 15 in a plan view. The second source pad 122 faces the plurality of trench gate structures 20 with the interlayer insulating film 99 interposed therebetween.

[0291] The second source pad 122 is electrically connected to the plurality of first trench source structures 25, the source region 18, and the plurality of first contact regions 38 via a plurality of source openings 126 formed in the interlayer insulating film 99. The second source pad 122 preferably has a planar area larger than that of the gate pad 101. When the third gate wiring 102C is not formed, the second source pad 122 may be formed integrally with the first source pad 121.

[0292] A source potential VS for source sensing is externally applied to the first source subpad 123. In this embodiment, the first source subpad 123 is disposed on a portion of the interlayer insulating film 99 that covers the active region 12, in a region between the gate pad 101 and the first gate wiring 102A (third connection surface 10C).

[0293] The first source subpad 123 has a planar area smaller than that of the first source pad 121 and is formed integrally with the first source pad 121. The planar area of ​​the first source subpad 123 is preferably larger than that of the gate subpad 103. It is particularly preferable that the planar area of ​​the first source subpad 123 is larger than that of the gate pad 101.

[0294] In a plan view, first source subpad 123 covers active region 12 at a distance from peripheral region 14 and termination region 15. Of course, first source subpad 123 may be arranged in a region overlapping either or both of peripheral region 14 and termination region 15.

[0295] The first source subpad 123 faces the plurality of trench gate structures 20 across the interlayer insulating film 99. The first source subpad 123 is electrically connected to the plurality of first trench source structures 25, the source regions 18, and the plurality of first contact regions 38 via a plurality of source openings 126 formed in the interlayer insulating film 99.

[0296] A source potential VS for source sensing is externally applied to the second source subpad 124. In this embodiment, the second source subpad 124 is disposed on a portion of the interlayer insulating film 99 that covers the active region 12, in a region between the gate pad 101 and the second gate wiring 102B (fourth connecting surface 10D).

[0297] In this embodiment, the second source subpad 124 has a planar area smaller than that of the second source pad 122 and is formed integrally with the second source pad 122. The planar area of ​​the second source subpad 124 is preferably larger than that of the gate subpad 103. It is particularly preferable that the planar area of ​​the second source subpad 124 be larger than that of the gate pad 101.

[0298] The second source subpad 124 covers the active region 12 at a distance from the peripheral region 14 and the termination region 15 in a plan view. Of course, the second source subpad 124 may be arranged in a region overlapping either or both of the peripheral region 14 and the termination region 15 in a plan view. The second source subpad 124 faces the multiple trench gate structures 20 with the interlayer insulating film 99 interposed therebetween. The second source subpad 124 is electrically connected to the multiple first trench source structures 25, the source regions 18, and the multiple first contact regions 38 via multiple source openings 126 formed in the interlayer insulating film 99.

[0299] The total plane area of ​​the first source pad 121, the second source pad 122, the first source sub-pad 123, and the second source sub-pad 124 is preferably 50% to 90% of the plane area of ​​the first main surface 3. It is particularly preferable that the total plane area be 75% or more of the plane area of ​​the first main surface 3.

[0300] The source wiring 125 transmits the source potential VS applied to the first source pad 121 and the second source pad 122 to other regions. In this embodiment, the source wiring 125 is drawn out from the first source pad 121 and the second source pad 122 so as to be located closer to the outer periphery region 13 than the gate wiring 102.

[0301] The source wiring 125 passes from the active surface 8 side through the first to fourth connecting surfaces 10A to 10D and is drawn out to the outer peripheral surface 9 side. The source wiring 125 is formed in a strip shape extending along the first to fourth connecting surfaces 10A to 10D. In other words, the source wiring 125 faces the sidewall wiring 95 with the interlayer insulating film 99 in between. In this embodiment, the source wiring 125 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connecting surfaces 10A to 10D and surrounds the gate wiring 102.

[0302] The source wiring 125 is electrically connected to the sidewall wiring 95 and the outer contact region 92 via an outer opening 127 formed in the interlayer insulating film 99. The outer opening 127 is formed in a strip or ring shape extending along the sidewall wiring 95 and the outer contact region 92. The source potential VS applied to the source wiring 125 is transmitted via the sidewall wiring 95 to the first trench source structure 25, the second trench source structure 30, the first dummy trench structure 61, the second dummy trench structure 62, and the trench termination structure 86.

[0303] The semiconductor device 1 includes an upper insulating film 130 that selectively covers the gate electrode 100, the source electrode 120, and the interlayer insulating film 99 on the first main surface 3. The upper insulating film 130 includes a gate pad opening 131 that exposes an inner portion of the gate pad 101 and a gate subpad opening 132 that exposes an inner portion of the gate subpad 103.

[0304] The upper insulating film 130 covers the peripheral portion of the gate pad 101, the peripheral portion of the gate subpad 103, and the entire area of ​​the gate wiring 102. The gate pad opening 131 is formed in a quadrangular shape in a plan view. The gate subpad opening 132 is also formed in a quadrangular shape in a plan view. The gate subpad opening 132 has a planar area smaller than the planar area of ​​the gate pad opening 131.

[0305] The upper insulating film 130 includes a first source pad opening 133 exposing an inner portion of the first source pad 121, a second source pad opening 134 exposing an inner portion of the second source pad 122, a first source subpad opening 135 exposing an inner portion of the first source subpad 123, and a second source subpad opening 136 exposing an inner portion of the second source subpad 124. The upper insulating film 130 covers the peripheral portion of the first source pad 121, the peripheral portion of the second source pad 122, the peripheral portion of the first source subpad 123, the peripheral portion of the second source subpad 124, and the entire area of ​​the source wiring 125.

[0306] The first source pad opening 133 is formed in a rectangular shape in a plan view. The first source pad opening 133 has a planar area larger than the planar area of ​​the gate subpad opening 132. The planar area of ​​the first source pad opening 133 is preferably larger than the planar area of ​​the gate pad opening 131.

[0307] The second source pad opening 134 is formed in a rectangular shape in a plan view. The second source pad opening 134 has a plan area larger than the plan area of ​​the gate subpad opening 132. The plan area of ​​the second source pad opening 134 is preferably larger than the plan area of ​​the gate pad opening 131. The plan area of ​​the second source pad opening 134 is preferably approximately equal to the plan area of ​​the first source pad opening 133.

[0308] The first source subpad opening 135 is formed in a rectangular shape in a plan view. The first source subpad opening 135 has a planar area smaller than that of the first source pad opening 133. The planar area of ​​the first source subpad opening 135 is preferably larger than that of the gate subpad opening 132. In this embodiment, the planar area of ​​the first source subpad opening 135 is larger than that of the gate pad opening 131. Of course, the planar area of ​​the first source subpad opening 135 may be smaller than that of the gate pad opening 131.

[0309] The second source subpad opening 136 is formed in a rectangular shape in a plan view. The second source subpad opening 136 has a planar area smaller than the planar area of ​​the second source pad opening 134. The planar area of ​​the second source subpad opening 136 is preferably larger than the planar area of ​​the gate subpad opening 132.

[0310] In this embodiment, the planar area of ​​the second source subpad opening 136 is larger than the planar area of ​​the gate pad opening 131. Of course, the planar area of ​​the second source subpad opening 136 may be smaller than the planar area of ​​the gate pad opening 131. It is preferable that the planar area of ​​the second source subpad opening 136 is approximately equal to the planar area of ​​the first source subpad opening 135.

[0311] The upper insulating film 130 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2, and defines a dicing street 137 between itself and the periphery of the chip 2. The dicing street 137 is formed in a band shape extending along the periphery of the chip 2 in plan view. In this embodiment, the dicing street 137 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8 in plan view. In this embodiment, the dicing street 137 exposes the interlayer insulating film 99.

[0312] Of course, when the main surface insulating film 16 and the interlayer insulating film 99 expose the outer peripheral surface 9, the dicing street 137 may also expose the outer peripheral surface 9. The dicing street 137 may have a width of 1 μm or more and 200 μm or less. The width of the dicing street 137 is the width in a direction perpendicular to the extension direction of the dicing street 137. The width of the dicing street 137 is preferably 5 μm or more and 50 μm or less.

[0313] The upper insulating film 130 preferably has a thickness greater than the thickness of the gate electrode 100 and the thickness of the source electrode 120. The thickness of the upper insulating film 130 is preferably less than the thickness of the chip 2. The thickness of the upper insulating film 130 may be 3 μm or more and 35 μm or less. The thickness of the upper insulating film 130 is preferably 25 μm or less.

[0314] In this embodiment, the upper insulating film 130 has a laminated structure including an inorganic insulating film 140 and an organic insulating film 141 laminated in this order from the chip 2 side. The upper insulating film 130 only needs to include at least one of the inorganic insulating film 140 and the organic insulating film 141, and does not necessarily need to include both the inorganic insulating film 140 and the organic insulating film 141 at the same time.

[0315] The inorganic insulating film 140 selectively covers the gate electrode 100, the source electrode 120, and the interlayer insulating film 99, and defines a portion of the gate pad opening 131, a portion of the gate subpad opening 132, a portion of the first source pad opening 133, a portion of the second source pad opening 134, a portion of the first source subpad opening 135, a portion of the second source subpad opening 136, and a portion of the dicing street 137.

[0316] The inorganic insulating film 140 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film 140 preferably includes an insulating material different from that of the interlayer insulating film 99. The inorganic insulating film 140 preferably includes a silicon nitride film. The inorganic insulating film 140 preferably has a thickness less than that of the interlayer insulating film 99. The thickness of the inorganic insulating film 140 may be 0.1 μm or more and 5 μm or less.

[0317] The organic insulating film 141 selectively covers the inorganic insulating film 140 and defines a portion of the gate pad opening 131, a portion of the gate subpad opening 132, a portion of the first source pad opening 133, a portion of the second source pad opening 134, a portion of the first source subpad opening 135, a portion of the second source subpad opening 136, and a portion of the dicing street 137.

[0318] The organic insulating film 141 may expose the inorganic insulating film 140 at the wall surface of the gate pad opening 131. The organic insulating film 141 may expose the inorganic insulating film 140 at the wall surface of the gate subpad opening 132. The organic insulating film 141 may expose the inorganic insulating film 140 at the wall surface of the first source pad opening 133. The organic insulating film 141 may expose the inorganic insulating film 140 at the wall surface of the second source pad opening 134.

[0319] The organic insulating film 141 may expose the inorganic insulating film 140 at the wall surface of the first source subpad opening 135. The organic insulating film 141 may expose the inorganic insulating film 140 at the wall surface of the second source subpad opening 136. The organic insulating film 141 may expose the inorganic insulating film 140 at the wall surface of the dicing street 137. Of course, the organic insulating film 141 may cover the entire inorganic insulating film 140 so that the inorganic insulating film 140 is not exposed.

[0320] The organic insulating film 141 is preferably made of a resin film other than a thermosetting resin. The organic insulating film 141 may be made of a light-transmitting resin or a transparent resin. The organic insulating film 141 may be made of a negative-type or positive-type photosensitive resin film. The organic insulating film 141 is preferably made of a polyimide film, a polyamide film, or a polybenzoxazole film. In this embodiment, the organic insulating film 141 includes a polybenzoxazole film.

[0321] The organic insulating film 141 preferably has a thickness greater than that of the inorganic insulating film 140. The thickness of the organic insulating film 141 preferably exceeds that of the interlayer insulating film 99. It is particularly preferable that the thickness of the organic insulating film 141 exceeds that of the gate electrode 100 and that of the source electrode 120. The thickness of the organic insulating film 141 may be 3 μm or more and 30 μm or less. The thickness of the organic insulating film 141 is preferably 20 μm or less.

[0322] The semiconductor device 1 includes a drain electrode 150 covering the second main surface 4. The drain electrode 150 forms ohmic contact with the second semiconductor region 7 exposed from the second main surface 4. The drain electrode 150 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. A breakdown voltage that can be applied between the source electrode 120 and the drain electrode 150 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.

[0323] As described above, the semiconductor device 1 includes a chip 2, a gate resistor 40, a gate pad 101, and a gate wiring 102. The chip 2 has a first main surface 3. The gate resistor 40 includes a trench resistance structure 41 formed on the first main surface 3. The gate pad 101 has a lower resistance value than the trench resistance structure 41 and is arranged on the first main surface 3 so as to be electrically connected to the trench resistance structure 41. The gate wiring 102 has a lower resistance value than the trench resistance structure 41 and is arranged on the first main surface 3 so as to be electrically connected to the gate pad 101 via the trench resistance structure 41.

[0324] According to this structure, the trench resistance structure 41 is incorporated into the chip 2 in the region between the gate pad 101 and the gate wiring 102, so that the area occupied by the gate resistor 40 relative to the first main surface 3 can be limited. The resistance value of the gate resistor 40 is adjusted by adjusting the depth and length of the trench resistance structure 41. Therefore, an increase in the area occupied by the gate resistor 40 relative to the first main surface 3 can be suppressed. Therefore, in a configuration including the gate resistor 40, it is possible to provide a semiconductor device 1 having a novel layout that contributes to miniaturization.

[0325] In such a structure, it is preferable that the gate pad 101 has a portion located directly above the trench resistance structure 41. With this structure, the gate resistor 40 is disposed in a region directly below the gate pad 101, thereby suppressing an increase in the area occupied by the gate resistor 40 relative to the first main surface 3. It is also preferable that the gate wiring 102 has a portion located directly above the trench resistance structure 41. With this structure, it is preferable that the gate resistor 40 is disposed in a region directly below the gate wiring 102, thereby suppressing an increase in the area occupied by the gate resistor 40 relative to the first main surface 3.

[0326] It is preferable that the trench resistance structure 41 does not contribute to channel control. This structure can appropriately suppress malfunctions caused by the trench resistance structure 41. It is preferable that the gate resistor 40 includes a resistive film 50 that covers the trench resistance structure 41. This structure can adjust the resistance value of the gate resistor 40 by utilizing both the trench resistance structure 41 and the resistive film 50.

[0327] In this case, the gate pad 101 is preferably electrically connected to the trench resistance structure 41 via the resistive film 50. According to this structure, the resistive film 50 can appropriately electrically connect the gate pad 101 to the trench resistance structure 41. The gate pad 101 preferably has a portion that faces the trench resistance structure 41 with the resistive film 50 interposed therebetween.

[0328] The gate wiring 102 is preferably electrically connected to the trench resistance structure 41 via the resistive film 50. According to this structure, the resistive film 50 can appropriately electrically connect the gate wiring 102 to the trench resistance structure 41. In this case, the gate wiring 102 preferably has a portion that faces the trench resistance structure 41 with the resistive film 50 interposed therebetween.

[0329] The resistive film 50 may have a portion covering the first main surface 3 and a portion covering the trench resistor structure 41. With this structure, the resistance value of the resistive film 50 can be adjusted by utilizing the region on the first main surface 3 and the region on the trench resistor structure 41. Also, the influence caused by an alignment error of the gate pad 101 with respect to the resistive film 50 and the influence caused by an alignment error of the gate wiring 102 can be reduced. In this case, the gate pad 101 may have a portion facing the first main surface 3 with the resistive film 50 interposed therebetween. Also, the gate wiring 102 may have a portion facing the first main surface 3 with the resistive film 50 interposed therebetween.

[0330] The semiconductor device 1 may include an interlayer insulating film 99 that covers the resistive film 50. In this case, the gate pad 101 preferably penetrates the interlayer insulating film 99 and is connected to the resistive film 50. In addition, the gate wiring 102 preferably penetrates the interlayer insulating film 99 and is connected to the resistive film 50.

[0331] A plurality of trench resistance structures 41 are preferably formed on the first main surface 3. With this structure, the resistance value of the gate resistor 40 can be adjusted by utilizing the plurality of trench resistance structures 41. The plurality of trench resistance structures 41 preferably include a first trench resistance structure 42 and a second trench resistance structure 43 that is deeper than the first trench resistance structure 42.

[0332] According to this structure, the resistance value of the gate resistor 40 can be adjusted by utilizing the first trench resistor structure 42 and the second trench 47 structure, which have different depths. In particular, the second trench resistor structure 43 can increase the resistance of the gate resistor 40 in the thickness direction of the chip 2. Therefore, for example, when a resistive film 50 is provided, the film thickness of the resistive film 50 can also be reduced.

[0333] The semiconductor device 1 preferably includes an active region 12, a peripheral region 13, and a termination region 15. The active region 12 is provided in an inner portion of the first main surface 3. The peripheral region 13 is provided in a peripheral portion of the first main surface 3. The termination region 15 is provided between the active region 12 and the peripheral region 13. In such a layout, the trench resistor structure 41 is preferably formed in the termination region 15. This layout makes it possible to appropriately suppress a reduction in the area of ​​the active region 12 that would otherwise occur if a gate resistor 40 were introduced.

[0334] In this case, it is preferable that the gate pad 101 is electrically connected to the trench resistance structure 41 in the termination region 15. It is also preferable that the gate wiring 102 is electrically connected to the gate pad 101 via the trench resistance structure 41 in the termination region 15.

[0335] The semiconductor device 1 preferably includes a trench gate structure 20 formed on the first main surface 3 in the active region 12. In this case, the gate wiring 102 is preferably electrically connected to the trench gate structure 20 in the active region 12. According to this structure, a gate resistor 40 (trench resistor structure 41) can be electrically interposed between the gate pad 101 and the trench gate structure 20.

[0336] The semiconductor device 1 may include a first trench source structure 25 formed in the first main surface 3 adjacent to the trench gate structure 20 in the active region 12, and to which a source potential VS is applied. In this case, the first trench source structure 25 may be formed deeper than the trench gate structure 20. In such a structure, the multiple trench resistance structures 41 preferably include a first trench resistance structure 42 formed relatively shallowly in correspondence with the trench gate structure 20, and a second trench resistance structure 43 formed relatively deep in correspondence with the first trench source structure 25.

[0337] According to this structure, a corresponding structure is formed between the active region 12 and the termination region 15, thereby suppressing bias in the electric field between the active region 12 and the termination region 15. Therefore, the electrical influence of the gate resistor 40 on the active region 12 is suppressed, and the electrical influence of the active region 12 on the gate resistor 40 is suppressed. In this case, it is preferable that the first trench resistor structure 42 has a depth approximately equal to that of the trench gate structure 20. It is also preferable that the second trench resistor structure 43 has a depth approximately equal to that of the first trench source structure 25.

[0338] Preferably, semiconductor device 1 further includes a dummy trench structure 60 formed on first main surface 3 adjacent to trench resistance structure 41 in termination region 15. Dummy trench structure 60 preferably does not contribute to channel control. With this structure, malfunctions caused by trench resistance structure 41 can be appropriately suppressed.

[0339] A source potential VS is preferably applied to the dummy trench structure 60. With this structure, the electric field in the region near the trench resistance structure 41 can be alleviated by the dummy trench structure 60. In this case, it is preferable that a plurality of dummy trench structures 60 are formed on the first main surface 3. With this structure, the electric field in the region near the trench resistance structure 41 in the termination region 15 can be alleviated by the plurality of dummy trench structures 60.

[0340] The multiple dummy trench structures 60 preferably include a first dummy trench structure 61 and a second dummy trench structure 62 that is deeper than the first dummy trench structure 61. With this structure, the electric field near the trench resistor structure 41 can be alleviated by the first dummy trench structure 61 and the second dummy trench structure 62.

[0341] Such a structure is particularly effective when a first trench source structure 25 that is deeper than the trench gate structure 20 is formed in the active region 12. Also, such a structure is particularly effective when a second trench resistor structure 43 that is deeper than the first trench resistor structure 42 is formed in the termination region 15.

[0342] The semiconductor device 1 may include an active surface 8 formed in an inner portion of the first main surface 3, an outer peripheral surface 9 formed on the periphery of the first main surface 3 so as to be recessed from the active surface 8 in the thickness direction of the chip 2, and an active plateau 11 defined on the first main surface 3 by first to fourth connection surfaces 10A to 10D connecting the active surface 8 and the outer peripheral surface 9. In this case, the active region 12 is provided on the active surface 8, the outer peripheral region 13 is provided on the outer peripheral surface 9, and the termination region 15 is provided on the active surface 8.

[0343] The semiconductor device 1 preferably includes an n-type first semiconductor region 6 formed in a surface layer portion of the first main surface 3. In this case, the trench resistor structure 41 is formed on the first main surface 3 so as to be located within the first semiconductor region 6.

[0344] In such a structure, the semiconductor device 1 preferably includes a p-type fourth well region 75 (fifth well region 76) formed in the first semiconductor region 6 in a region along the trench resistor structure 41 so as to form a p-n junction with the first semiconductor region 6. According to this structure, the withstand voltage (e.g., breakdown voltage) can be improved by a depletion layer that spreads from the fourth well region 75 (fifth well region 76).

[0345] The semiconductor device 1 may include a gate subpad 103 arranged on the first major surface 3 so as to have a lower resistance value than the trench resistor structure 41 and to be electrically connected to the gate pad 101 via the trench resistor structure 41.

[0346] According to this structure, the resistance value between the gate pad 101 and the gate wiring 102 can be indirectly measured by measuring the resistance value between the gate pad 101 and the gate subpad 103. The gate subpad 103 is preferably formed narrower than the gate pad 101 and wider than the gate wiring 102. The gate subpad 103 may be connected to the gate wiring 102.

[0347] The semiconductor device 1 may include a p-type outer well region 91 formed in a surface layer portion of the first main surface 3 in the peripheral region 13. With this structure, the outer well region 91 can alleviate the electric field in the peripheral region 13. The semiconductor device 1 may include at least one p-type field region 93 formed in a surface layer portion of the first main surface 3 in the peripheral region 13. With this structure, the field region 93 can alleviate the electric field in the peripheral region 13.

[0348] From another perspective, the semiconductor device 1 includes a chip 2, a first trench resistance structure 42 (first trench structure), a first dummy trench structure 61 (second trench structure), a second trench resistance structure 43 (third trench structure), a second dummy trench structure 62 (fourth trench structure), a first mesa portion 71, and a second mesa portion 72. The chip 2 has a first main surface 3. The first trench resistance structure 42 is formed on the first main surface 3. The first dummy trench structure 61 is formed on the first main surface 3 so as to be adjacent to the first trench resistance structure 42 in the first direction X.

[0349] The second trench resistance structure 43 is formed on the first main surface 3 so as to be adjacent to the first trench resistance structure 42 in a second direction Y perpendicular to the first direction X. The second dummy trench structure 62 is formed on the first main surface 3 so as to be adjacent to the second trench resistance structure 43 in the first direction X. The first mesa portion 71 is defined in a region between the first trench resistance structure 42 and the first dummy trench structure 61. The second mesa portion 72 is defined in the region between the second trench resistance structure 43 and the second dummy trench structure 62 so as to be shifted in the first direction X with respect to the first mesa portion 71.

[0350] This structure can prevent the electric field generated in the second mesa portion 72 from interfering with the electric field generated in the first mesa portion 71. This can prevent the electric field concentration in the first mesa portion 71 and the electric field concentration in the second mesa portion 72. Therefore, it is possible to provide a semiconductor device 1 having a novel layout that can improve the withstand voltage (for example, breakdown voltage).

[0351] Such a structure is particularly effective in a case where an electric field caused by a potential difference between the first dummy trench structure 61 and the first trench resistance structure 42 is generated in the first mesa portion 71, and an electric field caused by a potential difference between the second dummy trench structure 62 and the second trench resistance structure 43 is generated in the second mesa portion 72. Therefore, a potential different from that applied to the first trench resistance structure 42 may be applied to the first dummy trench structure 61, and a potential different from that applied to the second trench resistance structure 43 may be applied to the second dummy trench structure 62.

[0352] A first potential may be applied to the first trench resistance structure 42 and the second trench resistance structure 43, and a second potential different from the first potential may be applied to the first dummy trench structure 61 and the second dummy trench structure 62. The first potential may be a gate potential VG, and the second potential may be a source potential VS.

[0353] The second dummy trench structure 62 is preferably formed on the first main surface 3 so as to be adjacent to the first dummy trench structure 61 in the second direction Y. The second trench resistance structure 43 may be formed deeper than the first trench resistance structure 42. In this case, the second dummy trench structure 62 is preferably formed deeper than the first dummy trench structure 61.

[0354] This structure can mitigate bias in the electric field caused by the difference in depth between the first trench resistance structure 42 and the second trench resistance structure 43. In this case, the first dummy trench structure 61 is preferably formed to a depth substantially equal to that of the first trench resistance structure 42. Furthermore, the second dummy trench structure 62 is preferably formed to a depth substantially equal to that of the second trench resistance structure 43.

[0355] The semiconductor device 1 includes a main mesa 70 defined between the first trench resistor structure 42 and the second trench resistor structure 43. In this case, the first mesa 71 and the second mesa 72 are connected to the main mesa 70. The width of the first mesa 71 in the first direction X is preferably 0.5 to 2 times the width of the main mesa 70 in the second direction Y. Furthermore, the width of the second mesa 72 in the first direction X is preferably 0.5 to 2 times the width of the main mesa 70 in the second direction Y.

[0356] The first trench resistor structure 42 preferably extends in a strip shape in the first direction X. The second trench resistor structure 43 preferably extends in a strip shape in the first direction X. The first dummy trench structure 61 preferably extends in a strip shape in the first direction X. The second dummy trench structure 62 preferably extends in a strip shape in the first direction X.

[0357] The semiconductor device 1 may include an active surface 8 formed on the inner side of the first main surface 3, an outer peripheral surface 9 formed on the periphery of the first main surface 3 so as to be recessed from the active surface 8 in the thickness direction of the chip 2, and an active plateau 11 defined on the first main surface 3 by first to fourth connection surfaces 10A to 10D connecting the active surface 8 and the outer peripheral surface 9. In this case, the first trench resistor structure 42, the second trench resistor structure 43, the first dummy trench structure 61, and the second dummy trench structure 62 are preferably formed on the active surface 8.

[0358] The first trench resistor structure 42 and the second trench resistor structure 43 are preferably formed on the active surface 8 at intervals from the first to fourth connecting surfaces 10A to 10D. The first dummy trench structure 61 may be formed on the active surface 8 so as to be exposed from the third connecting surface 10C (fourth connecting surface 10D). The second dummy trench structure 62 may be formed on the active surface 8 so as to be exposed from the third connecting surface 10C (fourth connecting surface 10D).

[0359] The semiconductor device 1 may include a sidewall structure disposed on the outer peripheral surface 9 so as to cover at least one of the first to fourth connecting surfaces 10A to 10D. In this case, the sidewall structure preferably includes a sidewall wiring 95 electrically connected to the first dummy trench structure 61 and the second dummy trench structure 62. With this structure, the sidewall wiring 95 can apply a potential different from the potentials applied to the first trench resistance structure 42 and the second trench resistance structure 43 to the first dummy trench structure 61 and the second dummy trench structure 62 from the outer peripheral surface 9 side.

[0360] The semiconductor device 1 may include an n-type first semiconductor region 6 formed in a surface layer portion of the first main surface 3. The semiconductor device 1 may include a p-type body region 17 formed in a surface layer portion of the first semiconductor region 6. In this case, the first trench resistance structure 42, the second trench resistance structure 43, the first dummy trench structure 61, and the second dummy trench structure 62 preferably penetrate the body region 17 to reach the first semiconductor region 6.

[0361] It is preferable that the first trench resistance structure 42 and the second trench resistance structure 43 do not contribute to channel control. According to this structure, malfunctions caused by the first trench resistance structure 42 and the second trench resistance structure 43 can be appropriately suppressed. It is preferable that the first dummy trench structure 61 and the second dummy trench structure 62 do not contribute to channel control. According to this structure, it is possible to appropriately suppress malfunctions caused by the first dummy trench structure 61 and the second dummy trench structure 62.

[0362] The semiconductor device 1 may include a p-type second contact region 79 formed in a region along the second trench resistance structure 43 in the first semiconductor region 6. In this case, the second contact region 79 is preferably formed in a region along the second trench resistance structure 43 at a distance from the second mesa portion 72.

[0363] It is particularly preferable that the second contact region 79 is formed so as to be shifted in the first direction X with respect to the first mesa portion 71. In this case, it is preferable that the second contact region 79 does not face the first mesa portion 71 in the second direction Y. With this structure, the electric field associated with the first mesa portion 71 and the electric field associated with the second mesa portion 72 can be appropriately alleviated.

[0364] The semiconductor device 1 may include a p-type third contact region 80 formed in a region along the second dummy trench structure 62 in the first semiconductor region 6. In this case, the third contact region 80 is preferably formed in a region along the second dummy trench structure 62 and spaced apart from the second mesa portion 72. It is particularly preferable that the third contact region 80 be formed offset in the first direction X with respect to the first mesa portion 71. In this case, it is preferable that the third contact region 80 does not face the first mesa portion 71 in the second direction Y.

[0365] The chip 2 preferably includes a single crystal of a wide bandgap semiconductor. The single crystal of a wide bandgap semiconductor is effective in improving electrical characteristics. Furthermore, the single crystal of a wide bandgap semiconductor has a relatively high hardness, which suppresses deformation of the chip 2, while enabling the chip 2 to be thinned and have an increased planar area.

[0366] Thinning the chip 2 and increasing its planar area are also effective in improving electrical characteristics. For example, the chip 2 may have a first main surface 3 having an area of ​​1 mm square or more in a plan view. For example, the chip 2 may have a thickness of 200 μm or less. It is preferable that the chip 2 have a thickness of 100 μm or less in a cross-sectional view.

[0367] Various modified examples applicable to the embodiment will be described below with reference to FIGS. 29 to 34. FIG. 29 is a cross-sectional view showing a trench resistance structure 41 according to a first modified example. The trench resistance structure 41 according to the above-described embodiment includes a second trench resistance structure 43 having a fifth depth D5 that is greater than the fourth depth D4 (first depth D1) of the first trench resistance structure 42. In contrast, the trench resistance structure 41 according to the first modified example includes a second trench resistance structure 43 having a fifth depth D5 that is approximately equal to the fourth depth D4 of the first trench resistance structure 42.

[0368] That is, the trench resistance structure 41 according to the first modification has a structure that can be considered to include only a plurality of first trench resistance structures 42, and not a plurality of second trench resistance structures 43. In this example, the second contact region 79 is not formed in the region along the second trench resistance structure 43, but the second contact region 79 may be formed in the region along the second trench resistance structure 43.

[0369] 30 is a cross-sectional view showing a trench resistor structure 41 according to the second modification. The trench resistor structure 41 according to the above embodiment includes a first trench resistor structure 42 having a fourth depth D4 that is approximately equal to the first depth D1 of the trench gate structure 20. In contrast, the trench resistor structure 41 according to the second modification includes a first trench resistor structure 42 having a fourth depth D4 that is approximately equal to the second depth D2 of the first trench source structure 25.

[0370] That is, the trench resistance structure 41 according to the second modification has a structure that can be considered to include only a plurality of second trench resistance structures 43, and not a plurality of first trench resistance structures 42. In this example, the second contact region 79 is formed in a region along the first trench resistance structure 42, but the second contact region 79 does not have to be formed in a region along the first trench resistance structure 42.

[0371] 31 is an enlarged plan view showing a trench resistance structure 41 according to a third modification. The trench resistance structure 41 according to the above-described embodiment includes a second trench resistance structure 43 having both ends set back inward relative to both ends of the first trench resistance structure 42. In contrast, the trench resistance structure 41 according to the third modification includes a second trench resistance structure 43 having a second resistance length L2 that is longer than the first resistance length L1. Both ends of the second trench resistance structure 43 protrude further toward the outer circumferential surface 9 than both ends of the first trench resistance structure 42.

[0372] As in the above-described embodiment, the resistive film 50 has a third resistance length L3 in the first direction X that is shorter than the first resistance length L1 of the first trench resistance structure 42 and the second resistance length L2 of the second trench resistance structure 43. Of course, the resistive film 50 may cover the entire areas of the multiple trench resistance structures 41.

[0373] That is, the third resistance length L3 may be greater than the second resistance length L2. Furthermore, the resistance film 50 may cover both ends of the plurality of first trench resistance structures 42 and expose both ends of the plurality of second trench resistance structures 43. That is, the third resistance length L3 may be greater than the first resistance length L1 and less than the second resistance length L2.

[0374] In this example, the first dummy trench structure 61 has a portion that extends toward the end of the first trench resistance structure 42 relative to the end of the second trench resistance structure 43. As a result, the end of the first dummy trench structure 61 faces the first trench resistance structure 42 in the first direction X and faces the second trench resistance structure 43 in the second direction Y. On the other hand, the second dummy trench structure 62 is disposed in a region between two first dummy trench structures 61 adjacent to each other in the second direction Y, faces the second trench resistance structure 43 in the first direction X, and faces the first dummy trench structure 61 in the second direction Y.

[0375] In this example, each first mesa portion 71 faces the second trench resistance structure 43 in the second direction Y, but is shifted toward the second trench resistance structure 43 with respect to the end of the second dummy trench structure 62 so as not to face the second dummy trench structure 62 in the second direction Y. Each first mesa portion 71 is formed at an interval from the periphery of the resistance film 50 in the first direction X, and does not face the resistance film 50 in the normal direction Z.

[0376] Therefore, electrical interference of the resistive film 50 with each first mesa portion 71 is suppressed, and electrical interference of each first mesa portion 71 with the resistive film 50 is suppressed. Of course, when a resistive film 50 wider than the plurality of trench resistance structures 41 is formed, each first mesa portion 71 may face the resistive film 50 in the normal direction Z.

[0377] Each first mesa portion 71 defines a T-shaped mesa together with the main mesa portion 70 in plan view. From another perspective, each first mesa portion 71 defines an H-shaped mesa together with the two main mesa portions 70 in plan view. In this embodiment, the multiple first mesa portions 71 are formed on the same straight line along the second direction Y. Of course, the multiple first mesa portions 71 may be formed shifted from each other in the first direction X so as not to be positioned on the same straight line along the second direction Y.

[0378] On the other hand, in this example, each second mesa portion 72 faces the first dummy trench structure 61 in the second direction Y, but is shifted toward the first dummy trench structure 61 with respect to the end of the first trench resistance structure 42 so as not to face the first trench resistance structure 42 in the second direction Y. Each second mesa portion 72 is formed at an interval from the periphery of the resistance film 50 in the first direction X in plan view, and does not face the resistance film 50 in the normal direction Z.

[0379] Therefore, electrical interference of the resistive film 50 with each second mesa portion 72 is suppressed, and electrical interference of each second mesa portion 72 with the resistive film 50 is suppressed. Of course, when a resistive film 50 wider than the plurality of trench resistance structures 41 is formed, each second mesa portion 72 may face the resistive film 50 in the normal direction Z.

[0380] Each second mesa portion 72 defines a T-shaped mesa together with one main mesa portion 70 in plan view. From another perspective, each second mesa portion 72 defines an H-shaped mesa together with two main mesa portions 70 in plan view. In this embodiment, the multiple second mesa portions 72 are formed on the same straight line along the second direction Y.

[0381] Of course, the second mesa portions 72 may be formed offset from one another in the first direction X so as not to be positioned on the same straight line in the second direction Y. Even in this case, the second mesa portions 72 are formed at intervals from the first mesa portion 71 in the first direction X so as not to face the first mesa portion 71 in the second direction Y.

[0382] As in the embodiment, the multiple second contact regions 79 are formed at intervals in a region along each second trench resistance structure 43. The multiple second contact regions 79 are formed at intervals along each second trench resistance structure 43 so that the first mesa portion 71 is located between two adjacent second contact regions 79. In this example, the multiple second contact regions 79 are formed at intervals from the first mesa portion 71 in the first direction X so as not to face the first mesa portion 71.

[0383] For example, in the first direction X, the distance between the first mesa portion 71 and the second contact region 79 is preferably less than the length of the second contact region 79. The distance between the first mesa portion 71 and the second contact region 79 is preferably less than the fifth width W5 of the second trench resistor structure 43. It is particularly preferable that the distance between the first mesa portion 71 and the second contact region 79 be less than the width (fifth interval I5) of the first mesa portion 71.

[0384] The multiple second contact regions 79 include at least one (in this example, one) outermost second contact region 79 formed in the range between the first mesa portion 71 and the second mesa portion 72. The outermost second contact region 79 faces the first dummy trench structure 61 in the second direction Y.

[0385] The outermost second contact region 79 is preferably formed at a distance from the first mesa portion 71 and the second mesa portion 72 in the first direction X. In other words, the outermost second contact region 79 preferably faces the first dummy trench structure 61 in the second direction Y, but does not face the first trench resistance structure 42 in the second direction Y.

[0386] For example, in the first direction X, the distance between the second mesa portion 72 and the outermost second contact region 79 is preferably less than the length of the outermost second contact region 79. The distance between the second mesa portion 72 and the outermost second contact region 79 is preferably less than the fifth width W5 of the second trench resistor structure 43. It is particularly preferable that the distance between the second mesa portion 72 and the outermost second contact region 79 be less than the width (seventh interval I7) of the second mesa portion 72.

[0387] As in the embodiment, the multiple third contact regions 80 are formed at intervals in regions along each second dummy trench structure 62. In this embodiment, the multiple third contact regions 80 face the first dummy trench structures 61 in the second direction Y, but do not face the first trench resistance structure 42 in the second direction Y.

[0388] The multiple third contact regions 80 include an outermost third contact region 80 that covers a region along the end of the second dummy trench structure 62. The outermost third contact region 80 is formed so as to sandwich the second mesa portion 72 together with the outermost second contact region 79. The outermost third contact region 80 is preferably formed at a distance from the second mesa portion 72 in the first direction X.

[0389] For example, in the first direction X, the distance between the second mesa portion 72 and the outermost third contact region 80 is preferably less than the length of the outermost third contact region 80. It is particularly preferable that the distance between the second mesa portion 72 and the outermost third contact region 80 be less than the seventh width W7 of the dummy trench structure 60.

[0390] It is particularly preferable that the distance between the second mesa portion 72 and the outermost third contact region 80 be less than the width (seventh interval I7) of the second mesa portion 72. It is preferable that the distance between the outermost second contact region 79 and the outermost third contact region 80 adjacent to each other across the second mesa portion 72 be approximately equal to the distance between two adjacent second contact regions 79 across the first mesa portion 71.

[0391] 32 is an enlarged plan view showing a gate pad 101 according to a modification. The gate pad 101 according to the above embodiment includes a pad body 104 that is wider than the gate resistor 40 (trench gate structure 20) in the first direction X, and an extension portion 105 that is narrower than the gate resistor 40 (trench gate structure 20) in the first direction X.

[0392] In contrast, the gate pad 101 according to the modification includes a pad main body 104 narrower than the gate resistor 40 (trench gate structure 20) in the first direction X, and a lead-out portion 105 narrower than the gate resistor 40 (trench gate structure 20) in the first direction X. In this example, the lead-out portion 105 has a width in the first direction X that is approximately equal to that of the pad main body 104.

[0393] 33 is a cross-sectional view showing a chip 2 according to a first modification. Referring to Fig. 33, the semiconductor device 1 may include a second semiconductor region 7 having a thickness smaller than that of the first semiconductor region 6 inside the chip 2. In other words, the chip 2 may include an epitaxial layer that is thicker than the semiconductor substrate.

[0394] 34 is a cross-sectional view showing a chip 2 according to a second modification. Referring to FIG. 34, the semiconductor device 1 may include only the first semiconductor region 6 without the second semiconductor region 7 inside the chip 2. In this case, the first semiconductor region 6 is exposed from the first main surface 3, the second main surface 4, and the first to fourth side surfaces 5A to 5D of the chip 2. That is, in this embodiment, the chip 2 does not have a semiconductor substrate, but has a single-layer structure made of an epitaxial layer.

[0395] The above-described embodiments may be implemented in other forms. In the above-described embodiments, the "first conductivity type" is "n-type" and the "second conductivity type" is "p-type." However, in the above-described embodiments, the "first conductivity type" may be "p-type" and the "second conductivity type" may be "n-type." A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and the accompanying drawings.

[0396] In the above-described embodiment, the n-type second semiconductor region 7 has been described. However, a p-type second semiconductor region 7 may also be employed. In this case, an IGBT (Insulated Gate Bipolar Transistor) is formed instead of the MISFET. In this case, in the above description, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT. The p-type second semiconductor region 7 may be an impurity region containing p-type impurities introduced into a surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0397] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following clauses may be replaced with "wide bandgap semiconductor device," "SiC semiconductor device," "semiconductor switching device," "SiC-MISFET," etc., as necessary.

[0398] [A1] A semiconductor device (1) including: a chip (2) having a main surface (3); a gate resistor (40) including a trench resistor structure (41-43) formed on the main surface (3); a gate pad (101) having a lower resistance value than the trench resistor structure (41-43) and arranged on the main surface (3) so as to be electrically connected to the trench resistor structure (41-43); and a gate wiring (102) having a lower resistance value than the trench resistor structure (41-43) and arranged on the main surface (3) so as to be electrically connected to the gate pad (101) via the trench resistor structure (41-43).

[0399] [A2] The semiconductor device (1) according to A1, wherein the gate pad (101) has a portion located directly above the trench resistance structure (41-43), and the gate wiring (102) has a portion located directly above the trench resistance structure (41-43).

[0400] [A3] The semiconductor device (1) according to A1 or A2, wherein the trench resistor structure (41 to 43) does not contribute to channel control.

[0401] [A4] The semiconductor device (1) according to any one of A1 to A3, wherein the gate resistor (40) includes a resistive film (50) covering the trench resistor structure (41 to 43), the gate pad (101) is electrically connected to the resistive film (50), and the gate wiring (102) is electrically connected to the resistive film (50).

[0402] [A5] The semiconductor device (1) according to A4, wherein the resistive film (50) has a portion covering the main surface (3) and a portion covering the trench resistive structures (41 to 43).

[0403] [A6] The semiconductor device (1) according to A4 or A5, wherein the gate pad (101) faces the trench resistance structure (41-43) across the resistive film (50), and the gate wiring (102) faces the trench resistance structure (41-43) across the resistive film (50).

[0404] [A7] The semiconductor device (1) according to any one of A4 to A6, further comprising an insulating film (99) covering the resistive film (50), the gate pad (101) penetrating the insulating film (99) and connected to the resistive film (50), and the gate wiring (102) penetrating the insulating film (99) and connected to the resistive film (50).

[0405] [A8] The semiconductor device (1) according to any one of A1 to A7, wherein a plurality of the trench resistance structures (41 to 43) are formed on the main surface (3).

[0406] [A9] The semiconductor device (1) according to A8, wherein the plurality of trench resistance structures (41 to 43) include a first trench resistance structure (42) and a second trench resistance structure (43) that is deeper than the first trench resistance structure (42).

[0407] [A10] The semiconductor device (1) according to any one of A1 to A9, further comprising: an active region (12) provided in an inner portion of the main surface (3); an outer peripheral region (13) provided in a peripheral portion of the main surface (3); and a termination region (15) provided between the active region (12) and the outer peripheral region (13), wherein the trench resistance structure (41-43) is formed on the main surface (3) in the termination region (15), the gate pad (101) is electrically connected to the trench resistance structure (41-43) in the termination region (15), and the gate wiring (102) is electrically connected to the gate pad (101) via the trench resistance structure (41-43) in the termination region (15).

[0408] [A11] The semiconductor device (1) according to A10, further comprising a trench gate structure (20) formed on the main surface (3) in the active region (12), wherein the gate wiring (102) is electrically connected to the trench gate structure (20) in the active region (12).

[0409] [A12] The semiconductor device (1) according to A11, further comprising a trench source structure (25, 30) formed in the main surface (3) adjacent to the trench gate structure (20) in the active region (12).

[0410] [A13] The semiconductor device (1) according to A12, wherein the trench source structure (25, 30) is deeper than the trench gate structure (20).

[0411] [A14] The semiconductor device (1) according to any one of A10 to A13, further comprising a dummy trench structure (60-62) formed on the main surface (3) so as to be adjacent to the trench resistance structure (41-43) in the termination region (15).

[0412] [A15] The semiconductor device (1) according to A14, wherein a plurality of the dummy trench structures (60 to 62) are formed on the main surface (3).

[0413] [A16] The semiconductor device (1) according to A15, wherein the plurality of dummy trench structures (60-62) include a first dummy trench structure (61) and a second dummy trench structure (62) that is deeper than the first dummy trench structure (61).

[0414] [A17] The semiconductor device (1) according to any one of A10 to A16, further comprising: a first surface portion (8) formed in the inner portion of the main surface (3); a second surface portion (9) formed on the periphery of the main surface (3) so as to be recessed from the first surface portion (8) in the thickness direction of the chip (2); and an active plateau (11) defined on the main surface (3) by connection surface portions (10A to 10D) connecting the first surface portion (8) and the second surface portion (9), wherein the active region (12) is provided on the first surface portion (8), the outer peripheral region (13) is provided on the second surface portion (9), and the termination region (15) is provided on the first surface portion (8).

[0415] [A18] The semiconductor device (1) according to any one of A1 to A17, further comprising: a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); the trench resistance structure (41-43) formed on the main surface (3) so as to be located within the semiconductor region (6); and a well region (75, 76) of a second conductivity type (p-type) formed in the semiconductor region (6) in a region along the trench resistance structure (41-43) so as to form a pn junction with the semiconductor region (6).

[0416] [A19] The semiconductor device (1) according to any one of A1 to A18, further comprising a gate subpad (103) arranged on the main surface (3) so as to have a resistance value lower than that of the trench resistance structure (41 to 43) and to be electrically connected to the gate pad (101) via the trench resistance structure (41 to 43).

[0417] [A20] The semiconductor device (1) according to A19, wherein the gate subpad (103) is formed narrower than the gate pad (101) and wider than the gate wiring (102).

[0418] [B1] A chip (2) having a main surface (3), a first groove structure (42) formed on the main surface (3), a second groove structure (61) formed on the main surface (3) adjacent to the first groove structure (42) in a first direction (X), a third groove structure (43) formed on the main surface (3) adjacent to the first groove structure (42) in a second direction (Y) perpendicular to the first direction (X), and a third groove structure (43) formed on the main surface (3) adjacent to the first groove structure (42) in the first direction (X). a fourth groove structure (62) formed on the main surface (3) adjacent to a structure (43); a first mesa portion (71) defined in a region between the first groove structure (42) and the second groove structure (61); and a second mesa portion (72) defined in a region between the third groove structure (43) and the fourth groove structure (62) and shifted in the first direction (X) with respect to the first mesa portion (71).

[0419] [B2] The semiconductor device (1) described in B1, wherein a potential different from that applied to the first groove structure (42) is applied to the second groove structure (61), and a potential different from that applied to the third groove structure (43) is applied to the fourth groove structure (62).

[0420] [B3] A semiconductor device (1) according to B2, wherein a first potential is applied to the first groove structure (42), a second potential different from the first potential is applied to the second groove structure (61), the first potential is applied to the third groove structure (43), and the second potential is applied to the fourth groove structure (62).

[0421] [B4] The semiconductor device (1) according to B3, wherein the first potential is a gate potential (VG) and the second potential is a source potential (VS).

[0422] [B5] A semiconductor device (1) according to any one of B1 to B4, wherein the fourth groove structure (62) is formed on the main surface (3) so as to be adjacent to the second groove structure (61) in the second direction (Y).

[0423] [B6] The semiconductor device (1) described in any one of B1 to B5, wherein the third groove structure (43) is formed deeper than the first groove structure (42), and the fourth groove structure (62) is formed deeper than the second groove structure (61).

[0424] [B7] The semiconductor device (1) described in B6, wherein the second groove structure (61) is formed to a depth approximately equal to that of the first groove structure (42), and the fourth groove structure (62) is formed to a depth approximately equal to that of the third groove structure (43).

[0425] [B8] A semiconductor device (1) according to any one of B1 to B7, further comprising a main mesa portion (70) partitioned into a region between the first groove structure (42) and the third groove structure (43), and a region between the second groove structure (61) and the fourth groove structure (62), wherein the first mesa portion (71) is connected to the main mesa portion (70), and the second mesa portion (72) is connected to the main mesa portion (70).

[0426] [B9] The semiconductor device (1) described in B8, wherein the width of the first mesa portion (71) in the first direction (X) is 0.5 to 2 times the width of the main mesa portion (70) in the second direction (Y), and the width of the second mesa portion (72) in the first direction (X) is 0.5 to 2 times the width of the main mesa portion (70) in the second direction (Y).

[0427] [B10] The semiconductor device (1) according to any one of B1 to B9, wherein the first groove structure (42) extends in a strip shape in the first direction (X), the second groove structure (61) extends in a strip shape in the first direction (X), the third groove structure (43) extends in a strip shape in the first direction (X), and the fourth groove structure (62) extends in a strip shape in the first direction (X).

[0428] [B11] A semiconductor device (1) according to any one of B1 to B10, further comprising a first surface portion (8) formed in an inner portion of the main surface (3), a second surface portion (9) formed on the periphery of the main surface (3) so as to be recessed from the first surface portion (8) in the thickness direction of the chip (2), and an active plateau (11) defined on the main surface (3) by connection surface portions (10A to 10D) connecting the first surface portion (8) and the second surface portion (9), wherein the first groove structure (42) is formed in the first surface portion (8), the second groove structure (61) is formed in the first surface portion (8), the third groove structure (43) is formed in the first surface portion (8), and the fourth groove structure (62) is formed in the first surface portion (8).

[0429] [B12] The semiconductor device (1) described in B11, wherein the first groove structure (42) is formed in the first surface portion (8) at a distance from the connection surface portion (10A to 10D), the second groove structure (61) is formed in the first surface portion (8) so as to be exposed from the connection surface portion (10A to 10D), the third groove structure (43) is formed in the first surface portion (8) at a distance from the connection surface portion (10A to 10D), and the fourth groove structure (62) is formed in the first surface portion (8) so as to be exposed from the connection surface portion (10A to 10D).

[0430] [B13] The semiconductor device (1) according to B11 or B12, further comprising a sidewall structure arranged on the second surface portion (9) so as to cover the connection surface portions (10A to 10D).

[0431] [B14] The semiconductor device (1) according to B13, wherein the sidewall structure comprises a sidewall wiring (95) electrically connected to the second trench structure (61) and the fourth trench structure (62).

[0432] [B15] The semiconductor device (1) according to any one of B1 to B14, further comprising: a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); and a body region (17) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (6), wherein the first trench structure (42) penetrates the body region (17) to reach the semiconductor region (6), the second trench structure (61) penetrates the body region (17) to reach the semiconductor region (6), the third trench structure (43) penetrates the body region (17) to reach the semiconductor region (6), and the fourth trench structure (62) penetrates the body region (17) to reach the semiconductor region (6).

[0433] [B16] The semiconductor device (1) described in B15 further includes a first contact region (79) of a second conductivity type (p-type) formed in a region along the third trench structure (43) in the semiconductor region (6), and a second contact region (80) of a second conductivity type (p-type) formed in a region along the fourth trench structure (62) in the semiconductor region (6).

[0434] [B17] The semiconductor device (1) described in B16, wherein the first contact region (79) is formed in a region along the third groove structure (43) at a distance from the second mesa portion (72), and the second contact region (80) is formed in a region along the fourth groove structure (62) at a distance from the second mesa portion (72).

[0435] [B18] The semiconductor device (1) described in B16 or B17, wherein the first contact region (79) is formed offset in the first direction (X) with respect to the first mesa portion (71), and the second contact region (80) is formed offset in the first direction (X) with respect to the first mesa portion (71).

[0436] [B19] The semiconductor device (1) according to any one of B1 to B18, further comprising an insulating film (99) covering the first trench structure (42), and a gate electrode (100) arranged on the insulating film (99) so as to face the first trench structure (42) with the insulating film (99) interposed therebetween.

[0437] [B20] The semiconductor device (1) according to any one of B1 to B19, wherein the chip (2) includes a wide band gap semiconductor.

[0438] Although the embodiments have been described in detail above, these are merely specific examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiments.

[0439] REFERENCE SIGNS LIST 1 semiconductor device 2 chip 3 first main surface 6 first semiconductor region 8 active surface (first surface portion) 9 outer peripheral surface (second surface portion) 10A first connection surface (connection surface portion) 10B second connection surface (connection surface portion) 10C third connection surface (connection surface portion) 10D fourth connection surface (connection surface portion) 11 active plateau 12 active region 13 outer peripheral region 15 termination region 17 body region 20 trench gate structure 25 first trench source structure 30 second trench source structure 40 gate resistor 41 trench resistor structure 42 first trench resistor structure (first groove structure) 43 second trench resistor structure (third groove structure) 50 resistor film 60 dummy trench structure 61 first dummy trench structure (second groove structure) 62 second dummy trench structure (fourth groove structure) 70 Main mesa portion 71 First mesa portion 72 Second mesa portion 75 Fourth well region 76 Fifth well region 79 Second contact region 80 Third contact region 95 Sidewall wiring 99 Interlayer insulating film 101 Gate pad 102 Gate wiring 103 Gate subpad X First direction Y Second direction

Claims

1. a chip having a major surface; a gate resistor including a trench resistor structure formed on the main surface; a gate pad having a resistance value lower than that of the trench resistor structure and disposed on the main surface so as to be electrically connected to the trench resistor structure; a gate wiring having a resistance value lower than that of the trench resistance structure and arranged on the main surface so as to be electrically connected to the gate pad via the trench resistance structure.

2. A semiconductor device as described in claim 1, wherein a plurality of the trench resistor structures are formed on the main surface.

3. The semiconductor device described in claim 2, wherein the multiple trench resistance structures include a first trench resistance structure and a second trench resistance structure deeper than the first trench resistance structure.

4. An active region provided in an inner portion of the main surface; an outer peripheral region provided on a peripheral portion of the main surface; a termination region disposed between the active region and the periphery region, the trench resistor structure is formed in the major surface in the termination region; the gate pad is electrically connected to the trench resistor structure in the termination region; The semiconductor device according to claim 1 , wherein said gate wiring is electrically connected to said gate pad through said trench resistor structure in said termination region.

5. The semiconductor device as described in claim 4, further comprising a dummy trench structure formed on the main surface adjacent to the trench resistor structure in the termination region.

6. A semiconductor device as described in claim 5, wherein a plurality of the dummy trench structures are formed on the main surface.

7. The semiconductor device as described in claim 6, wherein the plurality of dummy trench structures include a first dummy trench structure and a second dummy trench structure deeper than the first dummy trench structure.

8. The semiconductor device further includes an active plateau defined on the main surface by a first surface portion formed on an inner portion of the main surface, a second surface portion formed on a peripheral portion of the main surface so as to be recessed from the first surface portion in a thickness direction of the chip, and a connecting surface portion connecting the first surface portion and the second surface portion; The active region is provided on the first surface portion, The outer circumferential region is provided on the second surface portion, The semiconductor device according to claim 4 , wherein said termination region is provided on said first surface portion.

9. The semiconductor device according to claim 8, further comprising a trench gate structure formed on the main surface in the active region, The semiconductor device according to claim 4 , wherein said gate wiring is electrically connected to said trench gate structure in said active region.

10. The semiconductor device of claim 9, further comprising a trench source structure formed on the main surface adjacent to the trench gate structure in the active region.

11. The semiconductor device of claim 10, wherein the trench source structure is deeper than the trench gate structure.

12. A semiconductor device as described in claim 1, further comprising a gate subpad having a lower resistance value than the trench resistor structure and arranged on the main surface so as to be electrically connected to the gate pad via the trench resistor structure.

13. The semiconductor device of claim 12, wherein the gate subpad is formed narrower than the gate pad and wider than the gate wiring.

14. the gate pad has a portion located directly above the trench resistor structure; 14. The semiconductor device according to claim 1, wherein the gate wiring has a portion located directly above the trench resistor structure.

15. The semiconductor device according to claim 1, wherein the trench resistor structure does not contribute to channel control.

16. the gate resistor includes a resistive film covering the trench resistor structure, the gate pad is electrically connected to the resistive film; 14. The semiconductor device according to claim 1, wherein the gate wiring is electrically connected to the resistive film.

17. 17. The semiconductor device according to claim 16, wherein said resistive film has a portion covering said main surface and a portion covering said trench resistor structure.

18. the gate pad faces the trench resistor structure with the resistor film therebetween; The semiconductor device according to claim 16 , wherein the gate wiring faces the trench resistor structure with the resistor film therebetween.

19. Further comprising an insulating film covering the resistive film, the gate pad is connected to the resistive film through the insulating film; The semiconductor device according to claim 16 , wherein the gate wiring penetrates the insulating film and is connected to the resistive film.

20. a first conductivity type semiconductor region formed in a surface layer portion of the main surface; the trench resistor structure formed on the main surface so as to be located within the semiconductor region; The semiconductor device according to any one of claims 1 to 13, further comprising: a well region of a second conductivity type formed in the semiconductor region in a region along the trench resistor structure so as to form a pn junction with the semiconductor region.