Semiconductor apparatus

Abstract

This semiconductor apparatus comprises: a chip that has a first main surface as a device surface and a second main surface as a non-device surface; and a drift slope region of a first conductivity type that is formed in the chip and has a concentration profile such that the impurity concentration in the end on the first main surface side is lower than the impurity concentration in the end on the second main surface side.

Description

Semiconductor Devices

[0001] This application claims priority from Japanese Patent Application No. 2022-061171 filed on March 31, 2022, the entire content of which is incorporated herein by reference. The present invention relates to a semiconductor device.

[0002] Patent Document 1 discloses a semiconductor device including a drift layer. The drift layer includes a first region, a second region, and a third region. The first region has a first impurity concentration n1, the second region has a second impurity concentration n2, and the third region has a third impurity concentration n3. The first to third impurity concentrations n1 to n3 are set to values ​​that satisfy the condition "n2<n1<n3" in consideration of cosmic ray tolerance.

[0003] Japanese Patent Application Laid-Open No. 2006-245475

[0004] One embodiment provides a semiconductor device with excellent reliability.

[0005] One embodiment provides a semiconductor device including: a chip having a first main surface as a device surface and a second main surface as a non-device surface; and a first conductivity type drift gradient region formed within the chip, the drift gradient region having a concentration profile in which the impurity concentration at an end on the first main surface side is lower than the impurity concentration at an end on the second main surface side.

[0006] The above and other objects, features, and advantages will become apparent from the following description of the embodiments with reference to the accompanying drawings.

[0007] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3A is a diagram illustrating the concentration distribution in a chip together with the drift gradient region according to the first embodiment. FIG. 3B is a diagram illustrating the concentration distribution in a chip together with the drift gradient region according to the second embodiment. FIG. 4 is a plan view showing a semiconductor device according to the second embodiment. FIG. 5 is a cross-sectional view taken along line VV in FIG. 4. FIG. 6A is a diagram illustrating the concentration distribution in a chip together with the drift gradient region according to the first embodiment. FIG. 6B is a diagram illustrating the concentration distribution in a chip together with the drift gradient region according to the second embodiment. FIG. 7 is a plan view showing a main part of the semiconductor device shown in FIG. 3. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. FIG. 9 is an enlarged cross-sectional view showing the peripheral portion of a chip. FIG. 10 is a cross-sectional view showing a modified chip corresponding to FIG. 2. FIG. 11 is a cross-sectional view showing a modified chip corresponding to FIG. 2. FIG. 12 is a diagram illustrating a modified chip corresponding to FIG. 3A.

[0008] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0009] When the phrase "substantially equal" is used in a description in which a comparison target is present, this phrase includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not attached with the intent of limiting the names of each structure.

[0010] Fig. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Referring to Figs. 1 and 2, in this embodiment, the semiconductor device 1A includes a chip 2 that includes a single crystal of a wide bandgap semiconductor and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In other words, the semiconductor device 1A is a "wide bandgap semiconductor device."

[0011] The chip 2 may be referred to as a "semiconductor chip" or a "wide bandgap semiconductor chip." A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).

[0012] In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1A is a "SiC semiconductor device." The hexagonal SiC single crystal has a plurality of polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may be made of another polytype.

[0013] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 is a device surface on which the main structure of the functional device is formed. The second main surface 4 is a non-device surface opposite the first main surface 3. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2. The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of a SiC single crystal.

[0014] In this case, it is preferable that the first main surface 3 is formed by the silicon surface of the SiC single crystal, and the second main surface 4 is formed by the carbon surface of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be greater than 0° and not more than 10°. The off angle is preferably not more than 5°. The second main surface 4 may be a ground surface having grinding marks, or a smooth surface without grinding marks.

[0015] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. The first to fourth side surfaces 5A to 5D may be ground surfaces having grinding marks, or may be smooth surfaces without grinding marks.

[0016] The chip 2 may have a thickness of 5 μm or more and 200 μm or less. The thickness of the chip 2 may be set to a value belonging to any one of the following ranges: 5 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, and 175 μm or more and 200 μm or less. The thickness of the chip 2 is preferably 100 μm or less.

[0017] The first to fourth side surfaces 5A to 5D may have lengths of 0.5 mm or more and 20 mm or less in plan view. The lengths of the first to fourth side surfaces 5A to 5D may be set to a value belonging to any one of the ranges of 0.5 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The lengths of the first to fourth side surfaces 5A to 5D are preferably 5 mm or more.

[0018] The semiconductor device 1A includes an n-type (first conductivity type) base region 6 formed in a region on the second main surface 4 side inside the chip 2. The base region 6 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the base region 6 is exposed from the entire second main surface 4. In other words, the base region 6 forms the second main surface 4. In this embodiment, the base region 6 is made of a SiC substrate (semiconductor substrate).

[0019] The base region 6 may have a thickness of 1 μm or more and 200 μm or less. The thickness of the base region 6 may be 150 μm or less, 100 μm or less, 50 μm or less, or 40 μm or less. The thickness of the base region 6 may be 5 μm or more. The thickness of the base region 6 is preferably 10 μm or more. By reducing the thickness of the base region 6, the resistance value caused by the base region 6 in the chip 2 can be reduced.

[0020] The semiconductor device 1A includes an n-type buffer region 7 formed inside the chip 2 in a region on the first main surface 3 side of the base region 6. The buffer region 7 is formed in a layer shape extending along the base region 6 so as to be connected to the base region 6, and is exposed from the first to fourth side surfaces 5A to 5D.

[0021] In this embodiment, the buffer region 7 is made of an epitaxial layer (specifically, a SiC epitaxial layer) stacked on the base region 6 (SiC substrate). The buffer region 7 may have a thickness of 0.1 μm or more and 5 μm or less. The thickness of the buffer region 7 is preferably 1 μm or more and 3 μm or less.

[0022] The semiconductor device 1A includes an n-type drift gradient region 8 formed in a region inside the chip 2 on the first main surface 3 side relative to the buffer region 7. The drift gradient region 8 may also be referred to as a "drift region." The drift gradient region 8 is formed in a layer shape extending along the base region 6 so as to be connected to the buffer region 7, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the drift gradient region 8 is exposed from the entire first main surface 3. In other words, the drift gradient region 8 forms the first main surface 3.

[0023] In this embodiment, the drift gradient region 8 is made of an epitaxial layer (specifically, a SiC epitaxial layer) stacked on the buffer region 7 (epitaxial layer). The drift gradient region 8 is preferably thicker than the buffer region 7. The drift gradient region 8 may have a thickness of 1 μm or more and 50 μm or less. The thickness of the drift gradient region 8 is preferably 3 μm or more and 30 μm or less. It is particularly preferable that the thickness of the drift gradient region 8 is 25 μm or less.

[0024] Specific configurations of the base region 6, buffer region 7, and drift gradient region 8 will be described below with reference to Figures 3A and 3B. Figure 3A is a diagram for explaining the concentration distribution in the chip 2 together with the drift gradient region 8 according to the first embodiment (hereinafter referred to as "drift gradient region 8A"). Figure 3B is a diagram for explaining the concentration distribution in the chip 2 together with the drift gradient region 8 according to the second embodiment (hereinafter referred to as "drift gradient region 8B").

[0025] 3A and 3B, the base region 6 has an n-type first concentration C1. The first concentration C1 may be referred to as a "base concentration." The first concentration C1 is adjusted to a substantially constant value from the second main surface 4 side toward the first main surface 3 side. The first concentration C1 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The first concentration C1 may be set to the following range: １８ cm －３ 1x10 or more １９ cm －３It is preferable to set it in the following range.

[0026] The buffer region 7 has an impurity concentration lower than the impurity concentration of the base region 6. The n-type impurity concentration of the buffer region 7 is 1×10 １６ cm －３ 1x10 or more ２０ cm －３ The n-type impurity concentration of the buffer region 7 may be set to the following range: １７ cm －３ 1x10 or more １９ cm －３ It is preferable that the concentration of the buffer region 7 is set to the following range: In this embodiment, the buffer region 7 has a concentration profile that decreases from a first concentration C1 to a second concentration C2 that is less than the first concentration C1 toward the first main surface 3. The second concentration C2 may be referred to as a "buffer concentration."

[0027] In this embodiment, the buffer region 7 includes a first transition region 9, a holding region 10, and a second transition region 11, which are formed in this order from the base region 6 side. The first transition region 9 has a concentration profile that gradually decreases from a first concentration C1 to a third concentration C3 that is less than the first concentration C1 from the base region 6 toward the first main surface 3 side.

[0028] The third concentration C3 may be referred to as an “intermediate buffer concentration.” The holding region 10 has a substantially constant third concentration C3 from the first transition region 9 toward the first major surface 3. The second transition region 11 has a concentration profile that gradually decreases from the third concentration C3 toward the first major surface 3 from the holding region 10 to a second concentration C2 that is less than the third concentration C3.

[0029] The drift gradient region 8 has a concentration profile in which the impurity concentration at the end on the first main surface 3 side is lower than the impurity concentration at the end on the second main surface 4 side. The drift gradient region 8 has a lower n-type impurity concentration than the base region 6. Specifically, the drift gradient region 8 has a lower n-type impurity concentration than the buffer region 7. The n-type impurity concentration of the drift gradient region 8 is 1×10 １４ cm －３ 1x10 or more １７ cm －３The n-type impurity concentration of the drift gradient region 8 may be set to the following range: １５ cm －３ 1x10 or more １７ cm －３ It is preferable to set it in the following range.

[0030] 3A , the semiconductor device 1A may include an n-type drift gradient region 8A according to the first embodiment as an example of the drift gradient region 8. The drift gradient region 8A has a concentration profile in which the n-type impurity concentration gradually decreases from the buffer region 7 side (the second main surface 4 side) toward the first main surface 3 side within the chip 2. Specifically, the n-type impurity concentration decreases from a second concentration C2 toward the first main surface 3 side from the buffer region 7 side to a fourth concentration C4 that is less than the second concentration C2. The fourth concentration C4 may be referred to as a "drift concentration."

[0031] The n-type impurity concentration decreases in a downward slope at a constant rate from the second concentration C2 to the fourth concentration C4. In other words, in this embodiment, the n-type impurity concentration gradually decreases in a linear fashion (first-order linear fashion) from the second concentration C2 to the fourth concentration C4.

[0032] The drift gradient region 8A is configured to form a first electric field distribution E1 within the chip 2. The first electric field distribution E1 has a profile in which the electric field strength increases monotonically from the buffer region 7 side toward the first main surface 3 side. That is, the first electric field distribution E1 has a maximum electric field strength at the end on the first main surface 3 side and a minimum electric field strength at the end on the buffer region 7 side.

[0033] In the first electric field distribution E1, the rate of increase in the electric field strength on the first main surface 3 side is smaller than the rate of increase in the electric field strength on the buffer region 7 side. Furthermore, the rate of increase in the electric field strength gradually decreases from the buffer region 7 side toward the first main surface 3 side. Therefore, the first electric field distribution E1 gradually increases in a curved shape (quadratic curve shape) from the buffer region 7 side toward the first main surface 3 side.

[0034] 3A shows the concentration profile of the drift region 8C according to the reference example (see the two-dot chain line). The drift region 8C according to the reference example is formed with a constant second concentration C2 from the buffer region 7 side toward the first main surface 3 side. The drift region 8C according to the reference example forms a reference electric field distribution ER within the chip 2. The reference electric field distribution ER has a profile in which the electric field strength monotonically increases at a constant rate from the buffer region 7 side toward the first main surface 3 side.

[0035] The reference electric field distribution ER has a maximum electric field strength at the end on the first main surface 3 side and a minimum electric field strength at the end on the buffer region 7 side. The maximum electric field strength of the reference electric field distribution ER is higher than the maximum electric field strength of the first electric field distribution E1. The minimum electric field strength of the reference electric field distribution ER is approximately equal to the minimum electric field strength of the first electric field distribution E1. The reference electric field distribution ER has a first intersection P1 where it intersects with the first electric field distribution E1 midway through the thickness range of the drift region 8C (drift gradient region 8).

[0036] A first area SA1 is formed in a thickness range between the first main surface 3 and the first intersection P1, the range being equal to or larger than the first electric field distribution E1 and equal to or smaller than the reference electric field distribution ER. A second area SA2 is formed in a thickness range between the buffer region 7 and the first intersection P1, the range being equal to or larger than the reference electric field distribution ER and equal to or smaller than the first electric field distribution E1.

[0037] In this case, it is preferable that the second area SA2 is adjusted to be approximately equal to the first area SA1. According to this structure, the breakdown voltage when the drift gradient region 8A according to the first embodiment is formed is approximately equal to the breakdown voltage when the drift region 8C according to the reference example is formed.

[0038] 3B , the semiconductor device 1A may include an n-type drift gradient region 8B according to the second embodiment as an example of the drift gradient region 8. The drift gradient region 8B has a concentration profile in which the n-type impurity concentration gradually decreases from the buffer region 7 side (second main surface 4 side) toward the first main surface 3 side within the chip 2. Specifically, the n-type impurity concentration decreases from a second concentration C2 to a fourth concentration C4 that is less than the second concentration C2 from the buffer region 7 toward the first main surface 3.

[0039] In this embodiment, the n-type impurity concentration is decreased in a stepwise manner. That is, the n-type impurity concentration is decreased in a stepwise manner from the second concentration C2 to the fourth concentration C4. The n-type impurity concentration may be decreased in a single stepwise manner, or in multiple steps of two or more steps. The number of steps in which the n-type impurity concentration is decreased is arbitrary. Therefore, the n-type impurity concentration may be decreased in multiple steps of four or more steps.

[0040] In this embodiment, the drift gradient region 8B has a configuration in which the n-type impurity concentration decreases in three steps. Specifically, the drift gradient region 8B includes a first step region 12, a first step transition region 13, a second step region 14, a second step transition region 15, and a third step region 16.

[0041] The first step region 12 has a substantially constant second concentration C2 from the buffer region 7 toward the first major surface 3. The first step transition region 13 has a concentration gradient that gradually decreases from the second concentration C2 to a fifth concentration C5 that is less than the second concentration C2 from the first step region 12 toward the first major surface 3. The fifth concentration C5 may also be referred to as an "intermediate drift concentration."

[0042] Second step region 14 has a substantially constant fifth concentration C5 from first step transition region 13 toward first major surface 3. Second step transition region 15 has a concentration gradient that gradually decreases from fifth concentration C5 to fourth concentration C4, which is less than fifth concentration C5, from second step region 14 toward first major surface 3. Third step region 16 has a substantially constant fourth concentration C4 from second step transition region 15 toward first major surface 3.

[0043] The drift gradient region 8B forms a second electric field distribution E2 within the chip 2. The second electric field distribution E2 has a profile in which the electric field strength increases monotonically from the buffer region 7 side toward the first main surface 3 side. That is, the second electric field distribution E2 has a maximum electric field strength at the end on the first main surface 3 side and a minimum electric field strength at the end on the buffer region 7 side.

[0044] In the second electric field distribution E2, the rate of increase in the electric field strength on the first main surface 3 side is smaller than the rate of increase in the electric field strength on the buffer region 7 side. Furthermore, the rate of increase in the electric field strength gradually decreases from the buffer region 7 side toward the first main surface 3 side. Specifically, the rate of increase in the electric field strength in the second step region 14 is smaller than the rate of increase in the electric field strength in the first step region 12, and the rate of increase in the electric field strength in the third step region 16 is smaller than the rate of increase in the electric field strength in the second step region 14. Therefore, the second electric field distribution E2 gradually increases in a polygonal line from the buffer region 7 side toward the first main surface 3 side.

[0045] 3B shows the concentration profile of the drift region 8C according to the reference example and the reference electric field distribution ER of the drift region 8C according to the reference example (see the two-dot chain line), as in FIG. 3A. The maximum electric field strength of the reference electric field distribution ER is greater than the maximum electric field strength of the second electric field distribution E2. The minimum electric field strength of the reference electric field distribution ER is approximately equal to the minimum electric field strength of the second electric field distribution E2. The reference electric field distribution ER has a second intersection point P2 where it intersects with the second electric field distribution E2 midway through the thickness range of the drift region 8C (drift gradient region 8).

[0046] A first area SB1 is formed in the thickness range between the first main surface 3 and the second intersection P2, in a range equal to or larger than the second electric field distribution E2 and equal to or smaller than the reference electric field distribution ER. A second area SB2 is formed in the thickness range between the buffer region 7 and the second intersection P2, in a range equal to or larger than the reference electric field distribution ER and equal to or smaller than the second electric field distribution E2.

[0047] In this case, it is preferable that the second area SB2 is adjusted to be approximately equal to the first area SB1. According to this structure, the breakdown voltage when the drift gradient region 8B according to the second embodiment is formed is approximately equal to the breakdown voltage when the drift region 8C according to the reference example is formed.

[0048] 2 again, the semiconductor device 1A includes an n-type diode region 20 formed on the first main surface 3. The diode region 20 is formed in a surface layer portion of the drift gradient region 8. Specifically, the diode region 20 is formed in the surface layer portion of the drift gradient region 8 by utilizing a part of the drift gradient region 8.

[0049] The semiconductor device 1A includes a p-type (second conductivity type) guard region 21 formed in a surface layer portion of the first main surface 3 along the diode region 20. In this embodiment, the guard region 21 is formed in a surface layer portion of the drift gradient region 8 so as to define the diode region 20 from the peripheral edge side of the first main surface 3. The guard region 21 is formed in a strip shape extending along the diode region 20 in a plan view. The guard region 21 is formed in a ring shape (a quadrangular ring shape in this embodiment) surrounding the diode region 20 in a plan view.

[0050] Semiconductor device 1A includes at least one (preferably two to 20) p-type field region 22 formed in a surface layer portion of first main surface 3 in a region between the periphery of first main surface 3 and guard region 21. In this embodiment, semiconductor device 1A includes four field regions 22.

[0051] In this embodiment, the plurality of field regions 22 are formed in the surface layer portion of the drift gradient region 8. The plurality of field regions 22 relieve the electric field within the chip 2 at the peripheral portion of the first main surface 3. The number, width, depth, p-type impurity concentration, etc. of the field regions 22 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0052] The plurality of field regions 22 are arranged at intervals from the guard region 21 toward the peripheral edge of the first main surface 3. The plurality of field regions 22 are formed in a band shape extending along the peripheral edge of the first main surface 3 in a plan view. In this embodiment, the plurality of field regions 22 are formed in a ring shape (specifically, a quadrangular ring) surrounding the diode region 20 (guard region 21) in a plan view.

[0053] The semiconductor device 1A includes an insulating film 23 that selectively covers the first main surface 3. The insulating film 23 covers a plurality of field regions 22 in the peripheral portion of the first main surface 3, and has contact openings 24 that expose inner edge portions of the diode region 20 and the guard region 21 in the inner portion of the first main surface 3.

[0054] The insulating film 23 may be continuous with the periphery of the first main surface 3 and may form a single ground surface together with the first to fourth side surfaces 5A to 5D. Of course, the insulating film 23 may be formed at a distance inward from the periphery of the first main surface 3, exposing the drift gradient region 8 (drift gradient region 8) from the periphery of the first main surface 3.

[0055] The semiconductor device 1A includes a first polarity electrode 25 (first principal surface electrode) disposed on the first principal surface 3. The first polarity electrode 25 may also be referred to as an "anode electrode." The first polarity electrode 25 is disposed inward from the periphery of the first principal surface 3 with a gap therebetween. In this embodiment, the first polarity electrode 25 is formed in a rectangular shape that follows the periphery of the first principal surface 3 in a plan view. The first polarity electrode 25 extends into the contact opening 24 from above the insulating film 23 and is electrically connected to the inner edges of the diode region 20 and the guard region 21. In other words, the first polarity electrode 25 is electrically connected to the drift gradient region 8 within the contact opening 24.

[0056] The first polarity electrode 25 forms a Schottky junction with the diode region 20 (i.e., the drift gradient region 8). This forms an SBD structure 26, which is an example of a device structure. The plane area of ​​the first polarity electrode 25 is preferably 50% or more of the first main surface 3. It is particularly preferable that the plane area of ​​the first polarity electrode 25 is 75% or more of the first main surface 3. The first polarity electrode 25 may have a thickness of 0.5 μm or more and 15 μm or less. The first polarity electrode 25 is preferably thicker than the insulating film 23.

[0057] The semiconductor device 1A includes a second polarity electrode 27 (second principal surface electrode) covering the second principal surface 4. The second polarity electrode 27 may be referred to as a "cathode electrode." The second polarity electrode 27 forms ohmic contact with the base region 6 exposed from the second principal surface 4. The second polarity electrode 27 may cover the entire second principal surface 4 so as to be continuous with the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). The second polarity electrode 27 may cover the second principal surface 4 at a distance inward from the periphery of the chip 2.

[0058] The breakdown voltage that can be applied between the first polarity electrode 25 and the second polarity electrode 27 may be 500 V or more and 3000 V or less. In other words, the chip 2 may be formed so that a breakdown voltage of 500 V or more and 3000 V or less can be applied between the first main surface 3 and the second main surface 4. The chip 2 is formed so that, depending on the voltage application conditions, the electric field strength on the first main surface 3 side as a device surface is higher than the electric field strength on the second main surface 4 side as a non-device surface.

[0059] One known cause of accidental failures in semiconductor devices is single event burnout (SEB), which is caused by cosmic rays that fall on Earth from space. The cosmic rays that fall on Earth react with the nuclei of atoms that make up the atmosphere to produce neutrons, which are radiation (high-energy particles) that are relatively highly penetrating and difficult to shield against.

[0060] Neutrons collide with semiconductor devices, causing electric field abnormalities inside the semiconductor device and generating local overvoltages and overcurrents. This results in SEB breakdown. Although the probability of SEB breakdown occurring is extremely low, the mode of breakdown is often fatal. In particular, SEB breakdown tends to occur due to high electric field areas inside semiconductor devices. Therefore, it is necessary to reduce the electric field strength in high electric field areas and increase cosmic ray tolerance (SEB breakdown tolerance).

[0061] The semiconductor device 1A includes a chip 2 and an n-type drift gradient region 8. The chip 2 has a first main surface 3 as a device surface and a second main surface 4 as a non-device surface. The drift gradient region 8 is formed within the chip 2 and has a concentration profile in which the impurity concentration at the end on the first main surface 3 side is lower than the impurity concentration at the end on the second main surface 4 side (see FIGS. 3A and 3B ).

[0062] When a voltage drop with respect to the second main surface 4 occurs between the first main surface 3 and the second main surface 4, an electric field distribution is formed in the drift gradient region 8 in which the electric field strength increases from the second main surface 4 side toward the first main surface 3 side. In other words, the electric field strength on the first main surface 3 side in the drift gradient region 8 becomes higher than the electric field strength on the second main surface 4 side in the drift gradient region 8.

[0063] In this electric field distribution, the drift gradient region 8 reduces the electric field strength on the first main surface 3 side (see FIGS. 3A and 3B). This suppresses the effect of cosmic rays (neutrons) on the high electric field portion in the drift gradient region 8, thereby suppressing the occurrence of local overvoltages and overcurrents caused by cosmic rays (neutrons). As a result, cosmic ray tolerance is improved and SEB breakdown can be suppressed. This makes it possible to provide a semiconductor device 1A with excellent reliability.

[0064] However, if the electric field strength on the first principal surface 3 side is reduced, the cosmic ray tolerance is improved, but there is a concern that the breakdown voltage (withstand voltage) may decrease. Therefore, it is preferable that the drift gradient region 8 has a concentration profile that gradually decreases from the second principal surface 4 side toward the first principal surface 3 side (see FIGS. 3A and 3B ).

[0065] This structure makes it possible to increase the electric field strength on the second main surface 4 side while maintaining a reduced state of the electric field strength on the first main surface 3 side (see FIGS. 3A and 3B ). As a result, the decrease in breakdown voltage (withstand voltage) caused by the decrease in electric field strength on the first main surface 3 side can be compensated for by the increase in breakdown voltage (withstand voltage) caused by the increase in electric field strength on the second main surface 4 side. Therefore, it is possible to improve cosmic ray tolerance while maintaining the withstand voltage.

[0066] The drift gradient region 8 preferably forms an electric field distribution in which the electric field strength increases monotonically from the second main surface 4 side toward the first main surface 3 side (see FIGS. 3A and 3B ). The drift gradient region 8 preferably forms an electric field distribution in which the rate of increase in the electric field strength on the first main surface 3 side is smaller than the rate of increase in the electric field strength on the second main surface 4 side (see FIGS. 3A and 3B ).

[0067] The drift gradient region 8 may have a concentration profile in which the n-type impurity concentration decreases in a downward slope toward the first main surface 3 (see FIG. 3A).The drift gradient region 8 may have a concentration profile in which the n-type impurity concentration decreases in a downward stepwise manner toward the first main surface 3 (see FIG. 3B).

[0068] The chip 2 preferably includes a single crystal of a wide bandgap semiconductor. This structure makes it possible to provide a wide bandgap semiconductor device (semiconductor device 1A) as a power semiconductor device capable of applying high voltages and high electric fields. Because wide bandgap semiconductor devices are used in high-voltage, high-electric field environments, they have a higher risk of SEB breakdown than Si semiconductor devices. In this regard, the drift gradient region 8 can improve cosmic ray tolerance by reducing the electric field strength on the first main surface 3 side, thereby suppressing SEB breakdown. Therefore, reliability can be improved even when the semiconductor device 1A is made of a wide bandgap semiconductor device.

[0069] Furthermore, the semiconductor device 1A as a wide bandgap semiconductor device can indirectly improve the reliability of the applications it is installed in by reducing the risk of SEB breakdown. For example, by installing the semiconductor device 1A as a wide bandgap semiconductor device in vehicles that use motors as their drive source, such as hybrid cars, electric cars, and fuel cell cars, the power consumption of these applications can be reduced while improving safety.

[0070] The chip 2 preferably includes a SiC single crystal, which is an example of a single crystal of a wide bandgap semiconductor. In this case, a SiC semiconductor device (semiconductor device 1A) with excellent reliability can be provided. The breakdown voltage that can be applied between the first main surface 3 and the second main surface 4 may be 500 V or more and 3000 V or less. The chip 2 may have a thickness of 200 μm or less. The chip 2 preferably has a thickness of 150 μm or less.

[0071] The chip 2 may have a first main surface 3 with a planar area of ​​1 mm square or more. A chip 2 with a relatively large planar area improves current handling capacity, thereby improving electrical characteristics. However, increasing the planar area of ​​the chip 2 increases the risk of cosmic ray collisions. In this regard, the drift gradient region 8 can improve cosmic ray tolerance by reducing the electric field strength on the side of the first main surface 3 with a relatively large planar area. Therefore, SEB breakdown can be suppressed even when a first main surface 3 with a relatively large planar area is adopted.

[0072] The drift gradient region 8 may form the first main surface 3. In this case, the semiconductor device 1A may include a first polarity electrode 25 arranged on the drift gradient region 8 so as to form a Schottky junction with the drift gradient region 8. This structure makes it possible to provide the semiconductor device 1A having an SBD structure 26. The semiconductor device 1A may also include a second polarity electrode 27 arranged on the second main surface 4. This structure makes it possible to provide the semiconductor device 1A having a vertical SBD structure 26 in which a forward current flows from the first main surface 3 to the second main surface 4.

[0073] The semiconductor device 1A may include an n-type diode region 20 formed by utilizing a part of the drift gradient region 8. The semiconductor device 1A may include a p-type guard region 21 formed along the diode region 20 in a surface layer portion of the first main surface 3. In this case, the first polarity electrode 25 may cover the diode region 20 and the guard region 21 so as to form a Schottky junction with the diode region 20 and be electrically connected to the guard region 21.

[0074] The semiconductor device 1A may include an n-type base region 6 formed in a region on the second main surface 4 side within the chip 2. The semiconductor device 1A may include a buffer region 7 formed in a region on the first main surface 3 side of the base region 6 within the chip 2. In this case, the drift gradient region 8 is preferably formed in a region on the first main surface 3 side of the buffer region 7 within the chip 2. The buffer region 7 preferably has a lower impurity concentration than the base region 6. The drift gradient region 8 preferably has a lower impurity concentration than the buffer region 7.

[0075] The buffer region 7 preferably has a thickness less than that of the base region 6. The drift gradient region 8 preferably has a thickness greater than that of the buffer region 7. The base region 6 may have a thickness of 1 μm or more and 200 μm or less. The buffer region 7 may have a thickness of 0.1 μm or more and 5 μm or less. The drift gradient region 8 may have a thickness of 1 μm or more and 50 μm or less.

[0076] FIG. 4 is a plan view showing a semiconductor device 1B according to a second embodiment. FIG. 5 is a cross-sectional view taken along line VV shown in FIG. 3. FIG. 6A is a diagram illustrating the concentration distribution in the chip 2 together with the drift gradient region 8A according to the first embodiment. FIG. 6B is a diagram illustrating the concentration distribution in the chip 2 together with the drift gradient region 8B according to the second embodiment. FIG. 7 is a plan view showing a main part of the semiconductor device 1B shown in FIG. 3. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 7. FIG. 9 is an enlarged cross-sectional view showing the peripheral portion of the chip 2.

[0077] 4 to 6B, the semiconductor device 1B includes a chip 2, a base region 6, a buffer region 7, and a drift gradient region 8, similar to the semiconductor device 1A described above. Referring to Fig. 6A, the semiconductor device 1B may include a drift gradient region 8A according to the first embodiment. Referring to Fig. 6B, the semiconductor device 1B may include a drift gradient region 8B according to the second embodiment. The chip 2, the base region 6, the buffer region 7, and the drift gradient region 8 (8A, 8B) have the same configurations as those of the semiconductor device 1A.

[0078] In this embodiment, the semiconductor device 1B includes an n-type high-concentration drift region 30 formed in a region of the chip 2 on the first main surface 3 side with respect to the drift gradient region 8. The high-concentration drift region 30 is formed in a layer shape extending along the drift gradient region 8 so as to be connected to the drift gradient region 8, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the high-concentration drift region 30 is exposed from the entire first main surface 3. In other words, the high-concentration drift region 30 forms the first main surface 3.

[0079] The drift high concentration region 30 has a higher n-type impurity concentration than the drift gradient region 8. The n-type impurity concentration of the drift high concentration region 30 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ It is preferable that the concentration be set within the following range: In this embodiment, the drift high concentration region 30 is made of an epitaxial layer (specifically, a SiC epitaxial layer) stacked on the drift gradient region 8 (epitaxial layer).

[0080] The high-concentration drift region 30 is preferably thicker than the buffer region 7. The thickness of the high-concentration drift region 30 is preferably less than the thickness of the drift gradient region 8. The thickness of the high-concentration drift region 30 may be 1 μm or more and 10 μm or less. The thickness of the high-concentration drift region 30 is preferably 3 μm or more and 5 μm or less.

[0081] 6A and 6B , the drift high-concentration region 30 includes a high-concentration transition region 31 and a high-concentration retention region 32. The high-concentration transition region 31 has a concentration profile that gradually increases from a fourth concentration C4 to a sixth concentration C6 higher than the fourth concentration C4 from the drift gradient region 8 toward the first main surface 3. The sixth concentration C6 may also be referred to as a “high drift concentration.”

[0082] The high-concentration holding region 32 has a substantially constant sixth concentration C6 from the high-concentration transition region 31 toward the first main surface 3. The sixth concentration C6 is less than the first concentration C1 of the base region 6. It is preferable that the sixth concentration C6 be higher than the second concentration C2 of the buffer region 7 and lower than the third concentration C3 of the buffer region 7.

[0083] 4 and 5 , the semiconductor device 1B includes an active surface 41, an outer surface 42, and first to fourth connecting surfaces 43A to 43D formed on the first main surface 3. The active surface 41, the outer surface 42, and the first to fourth connecting surfaces 43A to 43D define a mesa portion 44 (plateau) on the first main surface 3.

[0084] The active surface 41 may be referred to as the “first surface portion,” the outer surface 42 may be referred to as the “second surface portion,” and the first to fourth connecting surfaces 43A to 43D may be referred to as the “connecting surface portions.” The active surface 41, the outer surface 42, and the first to fourth connecting surfaces 43A to 43D (i.e., the mesa portion 44) may be considered to be components of the chip 2 (first main surface 3).

[0085] The active surface 41 is formed in an inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 41 is formed by the high-concentration drift region 30. Specifically, the active surface 41 is formed by the high-concentration retention region 32. The active surface 41 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 41 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0086] The outer surface 42 is located on the periphery of the first main surface 3 and is recessed from the active surface 41 in the thickness direction of the chip 2 (toward the second main surface 4). The outer surface 42 is recessed to a depth less than the thickness of the high-concentration drift region 30 so as to expose the high-concentration drift region 30. Specifically, the outer surface 42 is formed at a distance from the high-concentration transition region 31 and is formed by the high-concentration retention region 32.

[0087] The outer side surface 42 extends in a band shape along the active surface 41 in a plan view and is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 41. The outer side surface 42 has a flat surface extending in the first direction X and the second direction Y and is formed substantially parallel to the active surface 41. The outer side surface 42 is continuous with the first to fourth side surfaces 5A to 5D.

[0088] The first connecting surface 43A is located on the first side surface 5A side, the second connecting surface 43B is located on the second side surface 5B side, the third connecting surface 43C is located on the third side surface 5C side, and the fourth connecting surface 43D is located on the fourth side surface 5D side. The first connecting surface 43A and the second connecting surface 43B extend in the first direction X and face the second direction Y. The third connecting surface 43C and the fourth connecting surface 43D extend in the second direction Y and face the first direction X.

[0089] The first to fourth connection surfaces 43A to 43D extend in the normal direction Z and connect the active surface 41 and the outer surface 42. The first to fourth connection surfaces 43A to 43D are formed by the drift high-concentration region 30. Specifically, the first to fourth connection surfaces 43A to 43D are formed at intervals from the high-concentration transition region 31 and are formed by the high-concentration holding region 32.

[0090] The first to fourth connection surfaces 43A to 43D may extend substantially perpendicularly between the active surface 41 and the outer surface 42 so as to define the quadrangular prism-shaped mesa portion 44. The first to fourth connection surfaces 43A to 43D may be inclined obliquely downward from the active surface 41 toward the outer surface 42 so as to define the quadrangular pyramid-shaped mesa portion 44.

[0091] As described above, the semiconductor device 1B includes a mesa portion 44 formed in the high-concentration drift region 30 on the first main surface 3. The mesa portion 44 is formed only in the high-concentration drift region 30, and does not expose the drift gradient region 8. Specifically, the mesa portion 44 is formed in the high-concentration holding region 32, and does not expose the high-concentration transition region 31.

[0092] The semiconductor device 1B includes, as an example of a device structure, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure 50 formed on the active surface 41 (first main surface 3). In Fig. 5, the MISFET structure 50 is shown in a simplified form by dashed lines. The MISFET structure 50 and the structure on the outer side surface 42 side will be specifically described below.

[0093] 7 to 9 , the MISFET structure 50 includes a p-type (second conductivity type) body region 51 formed in a surface layer portion of the active surface 41. The body region 51 is formed in a surface layer portion of the drift high-concentration region 30 at a distance from the drift gradient region 8 toward the active surface 41. Specifically, the body region 51 is formed in a surface layer portion of the high-concentration holding region 32 at a distance from the high-concentration transition region 31 toward the active surface 41, and is formed in a layer shape extending along the active surface 41. The body region 51 may be exposed from a portion of the first to fourth connecting surfaces 43A to 43D.

[0094] The MISFET structure 50 includes an n-type source region 52 formed in a surface layer portion of a body region 51. The source region 52 has a higher n-type impurity concentration than the high-concentration drift region 30. The source region 52 is formed at an interval from the bottom of the body region 51 toward the active surface 41.

[0095] The source region 52 is formed in a layer shape extending along the active surface 41. The source region 52 may be exposed from the entire active surface 41. The source region 52 may be exposed from parts of the first to fourth connection surfaces 43A to 43D. The source region 52 forms a channel in the body region 51 between the source region 52 and the high-concentration drift region 30.

[0096] The MISFET structure 50 includes a plurality of trench gate structures 53 formed on the active surface 41. The plurality of trench gate structures 53 are arranged at intervals in the first direction X in a plan view, and are each formed in a strip shape extending in the second direction Y. The plurality of trench gate structures 53 are formed in the surface layer portion of the high-concentration drift region 30 at intervals from the drift gradient region 8 toward the active surface 41.

[0097] Specifically, the plurality of trench gate structures 53 are formed at intervals from the high concentration transition region 31 toward the active surface 41, and extend through the body region 51 and the source region 52 to the high concentration holding region 32. The plurality of trench gate structures 53 control the inversion and non-inversion of the channel in the body region 51.

[0098] In this embodiment, each trench gate structure 53 includes a gate trench 53 a, a gate insulating film 53 b, and a buried gate electrode 53 c. The gate trench 53 a is formed in the active surface 41 and defines the wall surface of the trench gate structure 53. The gate insulating film 53 b covers the wall surface of the gate trench 53 a. The buried gate electrode 53 c is buried in the gate trench 53 a with the gate insulating film 53 b sandwiched therebetween and faces the channel with the gate insulating film 53 b sandwiched therebetween.

[0099] The MISFET structure 50 includes a plurality of trench source structures 54 formed in the active surface 41. The plurality of trench source structures 54 are each arranged in a region between a pair of adjacent trench gate structures 53 in the active surface 41. The plurality of trench source structures 54 are each formed in a strip shape extending in the second direction Y in a plan view.

[0100] The plurality of trench source structures 54 are formed in the surface layer of the drift high-concentration region 30 at intervals from the drift gradient region 8 toward the active surface 41. Specifically, the plurality of trench source structures 54 are formed at intervals from the high-concentration transition region 31 toward the active surface 41, and extend through the body region 51 and the source region 52 to the high-concentration holding region 32.

[0101] The trench source structures 54 are formed deeper than the trench gate structures 53. The trench source structures 54 may have a depth that is 1.5 to 4 times greater than the depth of the trench gate structures 53. The depth of the trench source structures 54 is preferably 2.5 times or less than the depth of the trench gate structures 53. In this embodiment, the trench source structures 54 have a depth that is approximately equal to the depth of the outer surface 42. Of course, the trench source structures 54 may also have a depth that is approximately equal to the depth of the trench gate structures 53.

[0102] Each trench source structure 54 includes a source trench 54 a, a source insulating film 54 b, and a source buried electrode 54 c. The source trench 54 a is formed in the active surface 41 and defines the wall surface of the trench source structure 54. The source insulating film 54 b covers the wall surface of the source trench 54 a. The source buried electrode 54 c is buried in the source trench 54 a with the source insulating film 54 b sandwiched therebetween.

[0103] The MISFET structure 50 includes a plurality of p-type contact regions 60 formed in regions along the plurality of trench source structures 54 within the chip 2. The plurality of contact regions 60 have a higher p-type impurity concentration than the body region 51. Each contact region 60 covers the sidewall and bottom wall of each trench source structure 54 and is electrically connected to the body region 51. Each contact region 60 is formed in the drift high-concentration region 30 at a distance from the drift gradient region 8 toward the active surface 41. Specifically, each contact region 60 is formed in the high-concentration holding region 32 at a distance from the high-concentration transition region 31 toward the active surface 41.

[0104] The MISFET structure 50 includes a plurality of p-type well regions 61 formed in regions along the plurality of trench source structures 54 within the chip 2. Each well region 61 may have a p-type impurity concentration higher than that of the body region 51 and lower than that of the contact region 60. Each well region 61 covers the corresponding trench source structure 54 with the corresponding contact region 60 sandwiched therebetween.

[0105] Each well region 61 covers the sidewalls and bottom wall of the corresponding trench source structure 54 and is electrically connected to the body region 51 and the contact region 60. Each well region 61 is formed in the drift high-concentration region 30 at a distance from the drift gradient region 8 toward the active surface 41. Specifically, each well region 61 is formed in the high-concentration retention region 32 at a distance from the high-concentration transition region 31 toward the active surface 41.

[0106] 9 , semiconductor device 1B includes a p-type outer contact region 62 formed in a surface layer portion of outer side surface 42. Outer contact region 62 has a p-type impurity concentration that exceeds the p-type impurity concentration of body region 51. Outer contact region 62 preferably has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of contact region 60.

[0107] The outer contact region 62 is formed at a distance from the periphery of the active surface 41 and the periphery of the outer side surface 42 in plan view, and is formed in a band shape extending along the active surface 41. In this embodiment, the outer contact region 62 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 41 in plan view.

[0108] The outer contact region 62 is formed in a surface layer portion of the high-concentration drift region 30 at a distance from the drift gradient region 8 toward the outer surface 42. Specifically, the outer contact region 62 is formed in the high-concentration holding region 32 at a distance from the high-concentration transition region 31 toward the outer surface 42. The outer contact region 62 is located on the bottom side of the high-concentration drift region 30 with respect to the bottom walls of the multiple trench gate structures 53 (trench source structures 54).

[0109] The semiconductor device 1B includes a p-type outer well region 63 formed in a surface layer portion of the outer side surface 42. The outer well region 63 has a p-type impurity concentration lower than the p-type impurity concentration of the outer contact region 62. It is preferable that the p-type impurity concentration of the outer well region 63 be approximately equal to the p-type impurity concentration of the well region 61.

[0110] The outer well region 63 is formed in a region between the active surface 41 and the outer contact region 62 in plan view, and is formed in a band shape extending along the active surface 41. In this embodiment, the outer well region 63 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 41 in plan view.

[0111] The outer well region 63 is formed in a surface layer portion of the drift high-concentration region 30 at a distance from the drift gradient region 8 toward the outer surface 42. Specifically, the outer well region 63 is formed in the high-concentration holding region 32 at a distance from the high-concentration transition region 31 toward the outer surface 42. The outer well region 63 is located on the bottom side of the drift high-concentration region 30 with respect to the bottom walls of the multiple trench gate structures 53 (trench source structures 54).

[0112] The outer well region 63 is electrically connected to the outer contact region 62. In this embodiment, the outer well region 63 extends from the outer contact region 62 side toward the first to fourth connection surfaces 43A to 43D, and covers the first to fourth connection surfaces 43A to 43D. The outer well region 63 is electrically connected to the body region 51 in a surface layer portion of the active surface 41.

[0113] Semiconductor device 1B includes at least one (preferably two to twenty) p-type field region 64 formed in the surface layer portion of outer side surface 42 in a region between the periphery of outer side surface 42 and outer contact region 62. In this embodiment, semiconductor device 1B includes five field regions 64. The multiple field regions 64 relieve the electric field within chip 2 at outer side surface 42. The number, width, depth, p-type impurity concentration, etc. of field region 64 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0114] The field regions 64 are arranged at intervals from the outer contact region 62 side to the peripheral edge side of the outer side surface 42. The field regions 64 are formed in a strip shape extending along the active surface 41 in a plan view. In this embodiment, the field regions 64 are formed in a ring shape (specifically, a square ring) surrounding the active surface 41 in a plan view.

[0115] The plurality of field regions 64 are formed in the surface layer of the drift high-concentration region 30 at intervals from the drift gradient region 8 toward the outer surface 42. Specifically, the plurality of field regions 64 are formed in the high-concentration holding region 32 at intervals from the high-concentration transition region 31 toward the outer surface 42.

[0116] The multiple field regions 64 are located on the bottom side of the high-concentration drift region 30 relative to the bottom walls of the multiple trench gate structures 53 (trench source structures 54). The multiple field regions 64 may be formed deeper than the outer contact region 62. The innermost field region 64 may be connected to the outer contact region 62.

[0117] The semiconductor device 1B includes a main surface insulating film 70 covering the first main surface 3. The main surface insulating film 70 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 70 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 70 include a silicon oxide film made of an oxide of the chip 2.

[0118] The main surface insulating film 70 covers the active surface 41, the outer side surface 42, and the first to fourth connection surfaces 43A to 43D. The main surface insulating film 70 is continuous with the gate insulating film 53b and the source insulating film 54b, and covers the active surface 41 so as to expose the buried gate electrode 53c and the buried source electrode 54c. The main surface insulating film 70 covers the outer side surface 42 and the first to fourth connection surfaces 43A to 43D so as to cover the outer contact region 62, the outer well region 63, and the plurality of field regions 64.

[0119] The main surface insulating film 70 may be continuous with the first to fourth side surfaces 5A to 5D. In this case, the outer wall of the main surface insulating film 70 may form a single ground surface together with the first to fourth side surfaces 5A to 5D. Of course, the outer wall of the main surface insulating film 70 may be formed at a distance inward from the periphery of the outer surface 42, exposing the high-concentration drift region 30 from the periphery of the outer surface 42.

[0120] The semiconductor device 1B includes a sidewall structure 71 formed on the main surface insulating film 70 so as to cover at least one of the first to fourth connecting surfaces 43A to 43D on the outer side surface 42. In this embodiment, the sidewall structure 71 is formed in a ring shape (quadratic ring shape) surrounding the active surface 41 in a plan view.

[0121] The sidewall structure 71 may have a portion that extends over the active surface 41. The sidewall structure 71 may include an inorganic insulator or polysilicon. The sidewall structure 71 may be a sidewall interconnect that is electrically connected to the trench source structure 54.

[0122] The semiconductor device 1B includes an interlayer insulating film 72 formed on a main surface insulating film 70. The interlayer insulating film 72 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer insulating film 72 includes a silicon oxide film. The interlayer insulating film 72 covers the active surface 41, the outer side surface 42, and the first to fourth connecting surfaces 43A to 43D with the main surface insulating film 70 sandwiched therebetween.

[0123] Specifically, the interlayer insulating film 72 covers the active surface 41, the outer side surface 42, and the first to fourth connection surfaces 43A to 43D via the sidewall structure 71. The interlayer insulating film 72 covers the MISFET structure 50 on the active surface 41 side, and covers the outer contact region 62, the outer well region 63, and the plurality of field regions 64 on the outer side surface 42 side.

[0124] In this embodiment, the interlayer insulating film 72 is continuous with the first to fourth side surfaces 5A to 5D. The outer wall of the interlayer insulating film 72 may form a single ground surface together with the first to fourth side surfaces 5A to 5D. Of course, the outer wall of the interlayer insulating film 72 may be formed at a distance inward from the periphery of the outer surface 42, exposing the high-concentration drift region 30 from the periphery of the outer surface 42.

[0125] The semiconductor device 1B includes a gate electrode 73 disposed on the first main surface 3 (interlayer insulating film 72). The gate electrode 73 is disposed in an inner portion of the first main surface 3 at a distance from the periphery of the first main surface 3. In this embodiment, the gate electrode 73 is disposed on the active surface 41. Specifically, the gate electrode 73 is disposed in a region on the periphery of the active surface 41 that is close to the center of the third connection surface 43C (third side surface 5C).

[0126] In this embodiment, the gate electrode 73 is formed in a quadrangular shape in a plan view. Of course, the gate electrode 73 may be formed in a polygonal shape other than a quadrangular shape, a circular shape, or an elliptical shape in a plan view. The gate electrode 73 preferably has a planar area of ​​25% or less of the first main surface 3. The planar area of ​​the gate electrode 73 may be 10% or less of the first main surface 3. The gate electrode 73 may have a thickness of 0.5 μm or more and 15 μm or less.

[0127] The semiconductor device 1B includes a source electrode 74 disposed on the first main surface 3 (interlayer insulating film 72) at a distance from the gate electrode 73. The source electrode 74 is disposed on an inner portion of the first main surface 3 at a distance from the periphery of the first main surface 3. In this embodiment, the source electrode 74 is disposed on the active surface 41. In this embodiment, the source electrode 74 has a main electrode portion 75 and at least one (in this embodiment, multiple) extraction electrode portions 76A, 76B.

[0128] The main electrode portion 75 is disposed in a region on the fourth side surface 5D (fourth connection surface 43D) side at a distance from the gate electrode 73 in a plan view, and faces the gate electrode 73 in the first direction X. In this embodiment, the main electrode portion 75 is formed in a polygonal shape (specifically, a quadrilateral shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0129] The plurality of lead-out electrodes 76A, 76B include a first lead-out electrode 76A on one side (the side of the first side surface 5A) and a second lead-out electrode 76B on the other side (the side of the second side surface 5B). The first lead-out electrode 76A is led out from the main electrode 75 to a region located on one side (the side of the first side surface 5A) in the second direction Y with respect to the gate electrode 73 in a plan view, and faces the gate electrode 73 in the second direction Y.

[0130] The second extension electrode portion 76B is extended from the main electrode portion 75 to a region located on the other side in the second direction Y (the second side surface 5B side) of the gate electrode 73 in a plan view, and faces the gate electrode 73 in the second direction Y. In other words, the multiple extension electrode portions 76A, 76B sandwich the gate electrode 73 from both sides in the second direction Y in a plan view.

[0131] The source electrode 74 (main electrode portion 75 and lead electrode portions 76A, 76B) penetrates the interlayer insulating film 72 and the main surface insulating film 70, and is electrically connected to the plurality of trench source structures 54, the source region 52, and the plurality of well regions 61. Of course, the source electrode 74 may not have the lead electrode portions 76A, 76B and may consist of only the main electrode portion 75.

[0132] The source electrode 74 has a planar area that exceeds the planar area of ​​the gate electrode 73. The planar area of ​​the source electrode 74 is preferably 50% or more of the first main surface 3. It is particularly preferable that the planar area of ​​the source electrode 74 is 75% or more of the first main surface 3. The source electrode 74 may have a thickness of 0.5 μm or more and 15 μm or less. The source electrode 74 preferably contains the same conductive material as the gate electrode 73.

[0133] The semiconductor device 1B includes at least one (in this embodiment, multiple) gate wirings 77A, 77B extending from the gate electrode 73 onto the first main surface 3 (interlayer insulating film 72). The multiple gate wirings 77A, 77B preferably include the same conductive material as the gate electrode 73. In this embodiment, the multiple gate wirings 77A, 77B cover the active surface 41 but do not cover the outer side surface 42. The multiple gate wirings 77A, 77B are extended to the region between the periphery of the active surface 41 and the source electrode 74 in a plan view, and extend in a strip shape along the source electrode 74.

[0134] Specifically, the multiple gate wirings 77A, 77B include a first gate wiring 77A and a second gate wiring 77B. The first gate wiring 77A is drawn from the gate electrode 73 to a region on the first side surface 5A side in a plan view. The first gate wiring 77A has a portion that extends in a strip shape in the second direction Y along the third side surface 5C and a portion that extends in a strip shape in the first direction X along the first side surface 5A. The second gate wiring 77B is drawn from the gate electrode 73 to a region on the second side surface 5B side in a plan view. The second gate wiring 77B has a portion that extends in a strip shape in the second direction Y along the third side surface 5C and a portion that extends in a strip shape in the first direction X along the second side surface 5B.

[0135] The multiple gate wirings 77A, 77B intersect (specifically, orthogonally intersect) both ends of the multiple trench gate structures 53 at the peripheral portion of the active surface 41 (first main surface 3). The multiple gate wirings 77A, 77B penetrate the interlayer insulating film 72 and are electrically connected to the multiple trench gate structures 53. The multiple gate wirings 77A, 77B may be directly connected to the multiple trench gate structures 53, or may be electrically connected to the multiple trench gate structures 53 via a conductive film.

[0136] The semiconductor device 1B includes a source wiring 78 extending from the source electrode 74 onto the first main surface 3 (interlayer insulating film 72). The source wiring 78 preferably includes the same conductive material as the source electrode 74. The source wiring 78 is formed in a strip shape extending along the periphery of the active surface 41 in a region closer to the outer surface 42 than the plurality of gate wirings 77A, 77B. In this embodiment, the source wiring 78 is formed in a ring shape (specifically, a quadrangular ring) surrounding the gate electrode 73, the source electrode 74, and the plurality of gate wirings 77A, 77B in a plan view.

[0137] The source wiring 78 covers the sidewall structure 71 with the interlayer insulating film 72 sandwiched therebetween, and is drawn out from the active surface 41 side to the outer surface 42 side. The source wiring 78 preferably covers the entire sidewall structure 71 around the entire periphery. The source wiring 78 has a portion that penetrates the interlayer insulating film 72 and the main surface insulating film 70 on the outer surface 42 side and is connected to the outer surface 42 (specifically, the outer contact region 62). The source wiring 78 may penetrate the interlayer insulating film 72 and be electrically connected to the sidewall structure 71.

[0138] The semiconductor device 1B includes a drain electrode 79 covering the second main surface 4. The drain electrode 79 forms ohmic contact with the base region 6 exposed from the second main surface 4. The drain electrode 79 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain electrode 79 may cover the second main surface 4 at a distance inward from the periphery of the chip 2.

[0139] The breakdown voltage that can be applied between source electrode 74 and drain electrode 79 may be 500 V or more and 3000 V or less. In other words, chip 2 may be formed so that a breakdown voltage of 500 V or more and 3000 V or less can be applied between first main surface 3 and second main surface 4. Chip 2 is also formed so that, depending on the voltage application conditions, the electric field strength on the first main surface 3 side as a device surface is higher than the electric field strength on the second main surface 4 side as a non-device surface.

[0140] As described above, the semiconductor device 1B includes a chip 2 and an n-type drift gradient region 8. The chip 2 has a first main surface 3 as a device surface and a second main surface 4 as a non-device surface. The drift gradient region 8 is formed within the chip 2 and has a concentration profile in which the impurity concentration at the end on the first main surface 3 side is lower than the impurity concentration at the end on the second main surface 4 side (see FIGS. 6A and 6B ).

[0141] When a voltage drop with respect to the second main surface 4 occurs between the first main surface 3 and the second main surface 4, an electric field distribution is formed in the drift gradient region 8 in which the electric field strength increases from the second main surface 4 side toward the first main surface 3 side. In other words, the electric field strength on the first main surface 3 side in the drift gradient region 8 becomes higher than the electric field strength on the second main surface 4 side in the drift gradient region 8.

[0142] In this electric field distribution, the drift gradient region 8 reduces the electric field strength on the first main surface 3 side. This suppresses the effect of cosmic rays (neutrons) on the high electric field portion in the drift gradient region 8, thereby suppressing the occurrence of local overvoltages and overcurrents caused by cosmic rays (neutrons). As a result, cosmic ray tolerance is improved, and SEB breakdown can be suppressed. Therefore, a semiconductor device 1B with excellent reliability can be provided.

[0143] However, if the electric field strength on the first principal surface 3 side is reduced, the cosmic ray resistance is improved, but there is a concern that the breakdown voltage (withstand voltage) may decrease. Therefore, it is preferable that the drift gradient region 8 has a concentration profile that gradually decreases from the second principal surface 4 side toward the first principal surface 3 side (see FIGS. 6A and 6B ).

[0144] This structure makes it possible to increase the electric field strength on the second main surface 4 side while maintaining a reduced state of the electric field strength on the first main surface 3 side. As a result, the decrease in breakdown voltage (withstand voltage) caused by the decrease in electric field strength on the first main surface 3 side can be compensated for by the increase in breakdown voltage (withstand voltage) caused by the increase in electric field strength on the second main surface 4 side. Therefore, it is possible to improve cosmic ray resistance while maintaining the withstand voltage.

[0145] The drift gradient region 8 preferably forms an electric field distribution in which the electric field strength increases monotonically from the second main surface 4 side toward the first main surface 3 side. The drift gradient region 8 preferably forms an electric field distribution in which the rate of increase in the electric field strength on the first main surface 3 side is smaller than the rate of increase in the electric field strength on the second main surface 4 side.

[0146] The drift gradient region 8 may have a concentration profile in which the n-type impurity concentration decreases in a downward slope toward the first main surface 3 (see FIG. 6A). The drift gradient region 8 may have a concentration profile in which the n-type impurity concentration decreases in a downward stepwise manner toward the first main surface 3 (see FIG. 6B).

[0147] The semiconductor device 1B preferably includes a high-concentration drift region 30 formed in a region on the first main surface 3 side of the drift gradient region 8 within the chip 2, and having a higher impurity concentration than the drift gradient region 8. According to this structure, the high-concentration drift region 30 can form a region on the first main surface 3 side that has a lower resistance than the drift gradient region 8. The high-concentration drift region 30 may have a thickness less than the thickness of the drift gradient region 8.

[0148] The drift high-concentration region 30 preferably has a high-concentration transition region 31 in which the impurity concentration increases from the drift gradient region 8 toward the first main surface 3, and a high-concentration retention region 32 in which the impurity concentration is approximately constant from the high-concentration transition region 31 toward the first main surface 3. The high-concentration retention region 32 is preferably thicker than the high-concentration transition region 31.

[0149] The semiconductor device 1B preferably includes a trench gate structure 53 formed on the first main surface 3 so as to be located within the high-concentration drift region 30. This structure can improve the cosmic ray tolerance of a structure including the trench gate structure 53.

[0150] In this case, the trench gate structure 53 is preferably formed in the high-concentration drift region 30 at a distance from the drift gradient region 8 toward the first main surface 3. This structure can suppress changes in the shape of the drift gradient region 8 that accompany the introduction of the trench gate structure 53. In other words, it can suppress changes in the electric field distribution in the drift gradient region 8 that are caused by the trench gate structure 53. This allows the structure having the trench gate structure 53 to have improved cosmic ray tolerance.

[0151] Furthermore, with this structure, a part of the high-concentration drift region 30 can be interposed in the region between the drift gradient region 8 and the trench gate structure 53. This makes it possible to reduce the current spreading resistance along the surface direction of the first main surface 3 by utilizing the high-concentration drift region 30 located directly below the trench gate structure 53.

[0152] The semiconductor device 1B preferably includes a trench source structure 54 formed in the first main surface 3 so as to be located within the high-concentration drift region 30. This structure can improve the cosmic ray tolerance of the structure including the trench source structure 54. The trench source structure 54 is preferably formed adjacent to the trench gate structure 53.

[0153] The trench source structure 54 is preferably formed in the high-concentration drift region 30 at a distance from the drift gradient region 8 toward the first main surface 3. This structure can suppress changes in the shape of the drift gradient region 8 that accompany the introduction of the trench source structure 54. In other words, it can suppress changes in the electric field distribution in the drift gradient region 8 that are caused by the trench source structure 54. This can improve the cosmic ray tolerance of a structure having the trench source structure 54.

[0154] Furthermore, with this structure, a part of the high-concentration drift region 30 can be interposed in the region between the drift gradient region 8 and the trench source structure 54. This makes it possible to reduce the current spreading resistance along the surface direction of the first main surface 3 by utilizing the high-concentration drift region 30 located directly below the trench source structure 54.

[0155] The trench source structure 54 may be formed deeper than the trench gate structure 53. The trench source structure 54 may be formed shallower than the trench gate structure 53. The trench source structure 54 may be formed to a depth approximately equal to that of the trench gate structure 53.

[0156] The semiconductor device 1B preferably includes a mesa portion 44 defined on the first main surface 3. The mesa portion 44 is defined on the first main surface 3 by an active surface 41 formed on the inner portion of the first main surface 3, an outer side surface 42 formed on the periphery of the first main surface 3 so as to be recessed toward the second main surface 4, and first to fourth connection surfaces 43A to 43D connecting the active surface 41 and the outer side surface 42.

[0157] In such a structure, the active surface 41 is preferably formed by the high-concentration drift region 30. The outer surface 42 is preferably formed by the high-concentration drift region 30. In other words, it is preferable that the mesa portion 44 is formed only in the high-concentration drift region 30, and that the drift gradient region 8 is not exposed.

[0158] This structure can suppress changes in the shape of the drift gradient region 8 due to the introduction of the mesa portion 44. In other words, it can suppress fluctuations in the electric field distribution in the drift gradient region 8 due to the mesa portion 44. This can improve the cosmic ray tolerance in a structure having the mesa portion 44.

[0159] The semiconductor device 1B may include a p-type outer contact region 62 formed in the high-concentration drift region 30 in a surface layer portion of the outer side surface 42. The semiconductor device 1B may include a p-type outer well region 63 formed in the high-concentration drift region 30 in a surface layer portion of the outer side surface 42. The outer well region 63 may have a portion covering the first to fourth connection surfaces 43A to 43D. The semiconductor device 1B may include at least one p-type field region 64 formed in the high-concentration drift region 30 in a surface layer portion of the outer side surface 42.

[0160] The semiconductor device 1B may include an n-type base region 6 formed in a region on the second main surface 4 side within the chip 2. The semiconductor device 1B may include a buffer region 7 formed in a region on the first main surface 3 side with respect to the base region 6 within the chip 2. In this case, the drift gradient region 8 is preferably formed in a region on the first main surface 3 side with respect to the buffer region 7 within the chip 2.

[0161] The buffer region 7 preferably has a lower impurity concentration than the base region 6. The drift gradient region 8 preferably has a lower impurity concentration than the buffer region 7. The drift high-concentration region 30 preferably has a lower impurity concentration than the base region 6. The drift high-concentration region 30 preferably has an impurity concentration higher than the minimum value of the impurity concentration of the buffer region 7. The drift gradient region 8 is preferably thicker than the buffer region 7.

[0162] Modified examples of the chip 2 that can be applied to each of the above-described embodiments will be described below with reference to FIGS. 10 to 12. FIG. 10 corresponds to FIG. 2 and is a cross-sectional view showing a first modified example of the chip 2. FIG. 11 corresponds to FIG. 2 and is a cross-sectional view showing a second modified example of the chip 2. FIG. 12 corresponds to FIG. 3A and is a view showing a third modified example of the chip 2. FIGS. 10 to 12 show a form in which the chip 2 according to the first to third modified examples is applied to the semiconductor device 1A according to the first embodiment, but the configuration of the chip 2 according to the first to third modified examples may also be applied to the semiconductor device 1B according to the second embodiment.

[0163] 10 , the chip 2 according to the first modification includes a base region 6 having a thickness less than that of the drift gradient region 8. In this case, the base region 6 may have a thickness of 0.1 μm or more and less than 50 μm. The thickness of the base region 6 may be 5 μm or more (preferably 10 μm or more). Such a structure is formed by thinning the chip 2 from the second main surface 4 side by grinding, etching, or the like.

[0164] 11 , the chip 2 according to the second modification does not have the base region 6 or the buffer region 7, but only includes the drift gradient region 8. That is, the chip 2 according to the second modification does not have a semiconductor substrate, but has a single-layer structure made of an epitaxial layer. The drift gradient region 8 is exposed from the second main surface 4 of the chip 2. Such a structure is formed by thinning the chip 2 from the second main surface 4 side by grinding, etching, or the like.

[0165] 12 , the chip 2 according to the third modification includes a buffer region 7 having a concentration profile that continuously decreases from a first concentration C1 to a second concentration C2 from the base region 6 toward the first main surface 3. In other words, the buffer region 7 does not include the first transition region 9, the holding region 10, or the second transition region 11, but has a single transition region 80 that continuously decreases from the first concentration C1 to the second concentration C2.

[0166] The above-described embodiments can be implemented in other forms. For example, the features disclosed in the above-described embodiments can be combined as appropriate. That is, a form including at least two of the features disclosed in the first and second embodiments can be adopted.

[0167] In the second embodiment described above, the chip 2 has the mesa portion 44. However, a chip 2 having a flat first main surface 3 without the mesa portion 44 may be employed. In this case, the sidewall structure 71 is removed. Of course, in the first embodiment described above, a chip 2 having the mesa portion 44 may be employed. In this case, the SBD structure 26 is formed on the active surface 41.

[0168] In the second embodiment described above, a configuration having the source wiring 78 has been shown. However, a configuration not having the source wiring 78 may also be employed. In the second embodiment described above, the trench gate structure 53 that controls the channel inside the chip 2 has been shown. However, a planar gate structure that controls the channel from above the first main surface 3 may also be employed.

[0169] In the above-described embodiments, the SBD structure 26 and the MISFET structure 50 are formed in different chips 2. However, the SBD structure 26 and the MISFET structure 50 may be formed in different regions of the first main surface 3 of the same chip 2. In this case, the SBD structure 26 may be formed as a freewheeling diode of the MISFET structure 50. Furthermore, in this case, the source electrode 74 may also serve as the first polarity electrode 25, and the drain electrode 79 may also serve as the second polarity electrode 27.

[0170] In the above-described embodiments, the "first conductivity type" is "n-type" and the "second conductivity type" is "p-type." However, in the above-described embodiments, the "first conductivity type" may be "p-type" and the "second conductivity type" may be "n-type." A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and the accompanying drawings.

[0171] In the second embodiment described above, the n-type base region 6 is shown. However, a p-type base region 6 may be employed. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure 50. In this case, in the above description, the "source" of the MISFET structure 50 is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure 50 is replaced with the "collector" of the IGBT structure. The p-type base region 6 may be an impurity region containing p-type impurities introduced into a surface layer portion of the second main surface 4 of the chip 2 by ion implantation.

[0172] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in each of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiment. The "semiconductor device" in the following clauses may be replaced with "wide bandgap semiconductor device," "SiC semiconductor device," "semiconductor switching device," "semiconductor rectifier device," etc., as necessary.

[0173] [A1] A semiconductor device (1A, 1B) including: a chip (2) having a first main surface (3) as a device surface and a second main surface (4) as a non-device surface; and a drift gradient region (8, 8A, 8B) of a first conductivity type (n-type) formed in the chip (2) and having a concentration profile in which the impurity concentration at the end on the first main surface (3) side is lower than the impurity concentration at the end on the second main surface (4) side.

[0174] [A2] The semiconductor device (1A, 1B) described in A1, wherein the drift gradient region (8, 8A, 8B) has a concentration profile in which the impurity concentration gradually decreases from the second main surface (4) side toward the first main surface (3) side.

[0175] [A3] The semiconductor device (1A, 1B) according to A1 or A2, wherein the chip (2) includes a single crystal of a wide band gap semiconductor.

[0176] [A4] The semiconductor device (1A, 1B) according to A3, wherein the chip (2) includes a SiC single crystal.

[0177] [A5] The semiconductor device (1A, 1B) described in any one of A1 to A4, wherein the drift gradient region (8, 8A, 8B) forms an electric field distribution in which the electric field strength monotonically increases from the second main surface (4) side toward the first main surface (3) side.

[0178] [A6] A semiconductor device (1A, 1B) according to any one of A1 to A5, wherein the drift gradient region (8, 8A, 8B) forms an electric field distribution in which the rate of increase in electric field strength on the first main surface (3) side is smaller than the rate of increase in electric field strength on the second main surface (4) side.

[0179] [A7] The semiconductor device (1A, 1B) described in any one of A1 to A6, wherein the drift gradient region (8, 8A, 8B) has a concentration profile in which the impurity concentration decreases in a downward slope from the second main surface (4) side toward the first main surface (3) side.

[0180] [A8] The semiconductor device (1A, 1B) described in any one of A1 to A6, wherein the drift gradient region (8, 8A, 8B) has a concentration profile in which the impurity concentration decreases in a stepwise manner from the second main surface (4) side toward the first main surface (3) side.

[0181] [A9] The semiconductor device (1A, 1B) according to any one of A1 to A8, wherein the drift gradient region (8, 8A, 8B) forms the first main surface (3).

[0182] [A10] The semiconductor device (1A, 1B) according to A9, further comprising an electrode (25) arranged on the drift gradient region (8, 8A, 8B) and forming a Schottky junction with the drift gradient region (8, 8A, 8B).

[0183] [A11] The semiconductor device (1A, 1B) according to A10, further including: a diode region (20) of a first conductivity type (n-type) formed using a part of the drift gradient region (8, 8A, 8B); and a guard region (21) of a second conductivity type (p-type) formed along the diode region (20) in a surface layer portion of the first main surface (3), wherein the electrode (25) forms a Schottky junction with the diode region (20) and covers the diode region (20) and the guard region (21) so as to be electrically connected to the guard region (21).

[0184] [A12] The semiconductor device (1A, 1B) according to any one of A1 to A8, further including a first conductivity type (n-type) high concentration drift region (30) formed in the chip (2) on the first main surface (3) side relative to the drift gradient region (8, 8A, 8B) and having a higher impurity concentration than the drift gradient region (8, 8A, 8B).

[0185] [A13] The semiconductor device (1A, 1B) according to A12, wherein the high concentration drift region (30) has a thickness less than the thickness of the drift gradient region (8, 8A, 8B).

[0186] [A14] The semiconductor device (1A, 1B) according to A12 or A13, further comprising a trench gate structure (53) formed in the first main surface (3) so as to be located within the drift high concentration region (30).

[0187] [A15] The semiconductor device (1A, 1B) according to A14, wherein the trench gate structure (53) is formed at an interval from the drift gradient region (8, 8A, 8B) on the first main surface (3) side.

[0188] [A16] The semiconductor device (1A, 1B) according to any one of A12 to A15, further comprising a trench source structure (54) formed in the first main surface (3) so as to be located within the drift high concentration region (30).

[0189] [A17] A semiconductor device (1A, 1B) according to A16, wherein the trench source structure (54) is formed at an interval from the drift gradient region (8, 8A, 8B) on the first main surface (3) side.

[0190] [A18] A semiconductor device (1A, 1B) described in any one of A1 to A17, further including a base region (6) formed in the chip (2) on the second main surface (4) side, and a buffer region (7) formed in the chip (2) on the first main surface (3) side relative to the base region (6), and the drift gradient region (8, 8A, 8B) is formed in the chip (2) on the first main surface (3) side relative to the buffer region (7).

[0191] [A19] The semiconductor device (1A, 1B) according to A18, wherein the drift gradient region (8, 8A, 8B) is thicker than the buffer region (7).

[0192] [A20] A semiconductor device (1A, 1B) according to A18 or A19, further comprising: a base region (6) of a first conductivity type (n-type); and a buffer region (7) of the first conductivity type (n-type) having a lower impurity concentration than the base region (6), wherein the drift gradient region (8, 8A, 8B) has a lower impurity concentration than the buffer region (7).

[0193] [B1] A semiconductor device (1B) including: a chip (2) having a first main surface (3) as a device surface and a second main surface (4) as a non-device surface; drift gradient regions (8, 8A, 8B) of a first conductivity type (n-type) formed in the chip (2) and having a concentration profile in which the impurity concentration at an end on the first main surface (3) side is lower than the impurity concentration at an end on the second main surface (4) side; and a drift high concentration region (30) of a first conductivity type (n-type) formed in the chip (2) on the first main surface (3) side of the drift gradient region (8, 8A, 8B) and having a higher impurity concentration than the drift gradient region (8, 8A, 8B).

[0194] [B2] The semiconductor device (1B) according to B1, wherein the chip (2) is made of a single crystal of a wide bandgap semiconductor.

[0195] [B3] The semiconductor device (1B) according to B1 or B2, wherein the drift gradient region has a concentration profile in which the impurity concentration gradually decreases from the second main surface (4) side toward the first main surface (3) side.

[0196] [B4] A semiconductor device (1B) according to any one of B1 to B3, wherein the drift gradient region (8, 8A, 8B) has a concentration profile in which the impurity concentration decreases in a downward slope toward the first main surface (3).

[0197] [B5] A semiconductor device (1B) according to any one of B1 to B3, wherein the drift gradient region (8, 8A, 8B) has a concentration profile in which the impurity concentration decreases in a stepwise manner toward the first main surface (3).

[0198] [B6] A semiconductor device (1B) according to any one of B1 to B5, wherein the drift gradient region (8, 8A, 8B) extends in a layered manner along the first main surface (3), and the drift high concentration region (30) extends in a layered manner along the first main surface (3).

[0199] [B7] The semiconductor device (1B) according to any one of B1 to B6, wherein the high concentration drift region (30) forms the first main surface (3).

[0200] [B8] The semiconductor device (1B) according to any one of B1 to B7, wherein the high concentration drift region (30) has a thickness less than the thickness of the drift gradient region (8, 8A, 8B).

[0201] [B9] A semiconductor device (1B) according to any one of B1 to B8, wherein the drift high concentration region (30) includes a concentration transition region (31) in which the impurity concentration increases from the drift gradient region (8, 8A, 8B) toward the first main surface (3), and a concentration retention region (32) formed at a constant impurity concentration from the concentration transition region (31) toward the first main surface (3).

[0202] [B10] The semiconductor device (1B) according to B9, wherein the concentration maintaining region (32) is thicker than the concentration transition region (31).

[0203] [B11] A semiconductor device (1B) according to any one of B1 to B10, further comprising a trench gate structure (53) formed in an inner portion of the first main surface (3) so as to be located within the drift high concentration region (30).

[0204] [B12] The semiconductor device (1B) according to B11, wherein the trench gate structure (53) is formed at an interval from the drift gradient region (8, 8A, 8B) toward the first main surface (3).

[0205] [B13] A semiconductor device (1B) according to B11 or B12, further comprising a trench source structure (54) formed in an inner portion of the first main surface (3) adjacent to the trench gate structure (53) so as to be located within the drift high concentration region (30).

[0206] [B14] The semiconductor device (1B) according to B13, wherein the trench source structure (54) is deeper than the trench gate structure (53).

[0207] [B15] The semiconductor device (1B) according to B13 or B14, wherein the trench source structure (54) is formed at an interval from the drift gradient region (8, 8A, 8B) on the first main surface (3) side.

[0208] [B16] A semiconductor device (1B) according to any one of B1 to B15, further comprising a mesa portion (44) defined on the first main surface (3) by a first surface portion (41) formed on the inner side of the first main surface (3), a second surface portion (42) formed on the periphery of the first main surface (3) so as to be recessed toward the second main surface (4), and connection surface portions (43A to 43D) connecting the first surface portion (41) and the second surface portion (42).

[0209] [B17] The semiconductor device (1B) according to B16, wherein the first surface portion (41) is formed by the drift high concentration region (30), and the second surface portion (42) is formed by the drift high concentration region (30) at a distance from the drift gradient region (8, 8A, 8B).

[0210] [B18] The semiconductor device (1B) according to B16 or B17, further comprising at least one field region (64) of a second conductivity type (p-type) formed in the drift high concentration region (30) in the surface layer portion of the second surface portion (42).

[0211] [B19] A semiconductor device (1B) described in any one of B1 to B18, further including a base region (6) formed in the chip (2) on the second main surface (4) side, and a buffer region (7) formed in the chip (2) on the first main surface (3) side relative to the base region (6), and the drift gradient region (8, 8A, 8B) is formed in the chip (2) on the first main surface (3) side relative to the buffer region (7).

[0212] [B20] A semiconductor device (1B) according to any one of B1 to B19, further comprising: a gate electrode (73) arranged on the first main surface (3); a source electrode (74) arranged on the first main surface (3) at a distance from the gate electrode (73); and a drain electrode (79) arranged on the second main surface (4).

[0213] [C1] A semiconductor device (1A, 1B) including: a chip (2) having a first main surface (3) as a device surface and a second main surface (4) as a non-device surface; a base region (6) of a first conductivity type (n-type) formed in the chip (2) on the second main surface (4) side; a buffer region (7) of a first conductivity type (n-type) formed in the chip (2) on the first main surface (3) side of the base region (6) and having a lower impurity concentration than the base region (6); and a drift gradient region (8, 8A, 8B) of a first conductivity type (n-type) formed in the chip (2) on the first main surface (3) side of the buffer region (7), having a lower impurity concentration than the buffer region (7), and having a concentration profile in which the impurity concentration on the first main surface (3) side is lower than the impurity concentration on the buffer region (7) side.

[0214] [C2] The semiconductor device (1A, 1B) described in C1, wherein the drift gradient region (8, 8A, 8B) has a concentration profile in which the impurity concentration gradually decreases from the buffer region (7) side toward the first main surface (3).

[0215] [C3] The semiconductor device (1A, 1B) described in C1 or C2, wherein the drift gradient region (8, 8A, 8B) forms an electric field distribution in which the electric field strength monotonically increases from the buffer region (7) side toward the first main surface (3).

[0216] [C4] A semiconductor device (1A, 1B) described in any one of C1 to C3, wherein the drift gradient region (8, 8A, 8B) forms an electric field distribution in which the rate of increase in electric field strength on the first main surface (3) side is smaller than the rate of increase in electric field strength on the buffer region (7) side.

[0217] Although the embodiments have been described in detail above, these are merely specific examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiments.

[0218] 1A Semiconductor device 1B Semiconductor device 2 Chip 3 First main surface 4 Second main surface 6 Base region 7 Buffer region 8 Drift gradient region 8A Drift gradient region 8B Drift gradient region 20 Diode region 21 Guard region 25 First electrode 27 Second electrode 30 High concentration drift region 31 High concentration transition region 32 High concentration retention region 41 First surface portion 42 Second surface portion 43A First connection surface portion 43B Second connection surface portion 43C Third connection surface portion 43D Fourth connection surface portion 44 Mesa portion 53 Trench gate structure 54 Trench source structure 73 Gate electrode 74 Source electrode 79 Drain electrode

Claims

1. a chip having a first main surface as a device surface and a second main surface as a non-device surface; a first conductivity type drift gradient region formed in the chip and having a concentration profile in which an impurity concentration at an end portion on the first main surface side is lower than an impurity concentration at an end portion on the second main surface side.

2. 2 . The semiconductor device according to claim 1 , wherein the drift gradient region has the concentration profile in which the impurity concentration gradually decreases from the second main surface side toward the first main surface side.

3. The semiconductor device according to claim 1 , wherein the chip includes a single crystal of a wide band gap semiconductor.

4. The semiconductor device according to claim 3 , wherein the chip comprises a SiC single crystal.

5. 2 . The semiconductor device according to claim 1 , wherein said drift gradient region forms an electric field distribution in which the electric field strength increases monotonically from said second main surface side to said first main surface side.

6. 2 . The semiconductor device according to claim 1 , wherein said drift gradient region forms an electric field distribution in which an increasing rate of the electric field strength on said first main surface side is smaller than an increasing rate of the electric field strength on said second main surface side.

7. 2 . The semiconductor device according to claim 1 , wherein the drift gradient region has a concentration profile in which the impurity concentration decreases in a downward gradient from the second main surface side to the first main surface side.

8. 2 . The semiconductor device according to claim 1 , wherein the drift gradient region has a concentration profile in which the impurity concentration decreases in a stepwise manner from the second main surface side to the first main surface side.

9. 9. The semiconductor device according to claim 1, wherein the drift gradient region forms the first main surface.

10. The semiconductor device of claim 9 , further comprising an electrode disposed over the drift gradient region and forming a Schottky junction with the drift gradient region.

11. a first conductivity type diode region formed by utilizing a portion of the drift gradient region; a second conductivity type guard region formed along the diode region in a surface layer portion of the first main surface, 11. The semiconductor device according to claim 10, wherein the electrode forms a Schottky junction with the diode region and covers the diode region and the guard region so as to be electrically connected to the guard region.

12. 9. The semiconductor device according to claim 1, further comprising a first conductivity type drift high concentration region formed on the first main surface side of the drift gradient region in the chip and having a higher impurity concentration than the drift gradient region.

13. The semiconductor device according to claim 12 , wherein the drift high concentration region has a thickness less than a thickness of the drift gradient region.

14. The semiconductor device according to claim 12 , further comprising a trench gate structure formed in said first main surface so as to be located within said drift high concentration region.

15. The semiconductor device according to claim 14 , wherein the trench gate structure is formed on a side of the first main surface away from the drift gradient region.

16. The semiconductor device according to claim 12 , further comprising a trench source structure formed in said first main surface so as to be located within said drift high concentration region.

17. The semiconductor device according to claim 16 , wherein the trench source structure is formed on a side of the first main surface away from the drift gradient region.

18. a base region formed on the second main surface side within the chip; a buffer region formed on the first main surface side of the base region in the chip, 9. The semiconductor device according to claim 1, wherein the drift gradient region is formed on the first main surface side of the buffer region within the chip.

19. The semiconductor device of claim 18 , wherein the drift gradient region is thicker than the buffer region.

20. the base region of a first conductivity type; the buffer region of the first conductivity type having a lower impurity concentration than the base region; The semiconductor device according to claim 18 , wherein the drift gradient region has a lower impurity concentration than the buffer region.