Sic semiconductor device

Abstract

A semiconductor device (1A) comprises: a chip (2) that comprises a SiC single crystal and has a major surface (3); a trench structure (20) that includes a first sidewall (22A) extending in an a-axis direction of the SiC single crystal and a second sidewall (22B) extending in an m-axis direction of the SiC single crystal, and that is formed on the major surface; and a first conductivity-type contact region (50) that is formed in a region inside the chip along the trench structure and spaced apart from the second sidewall in the a-axis direction.

Description

SiC semiconductor device

[0001] This application claims priority from Japanese Patent Application No. 2022-061147 filed on March 31, 2022, the entire content of which is incorporated herein by reference. The present invention relates to a SiC semiconductor device.

[0002] FIG. 8 of Patent Document 1 discloses a SiC vertical power MOSFET including an n-type drift layer, a trench structure formed in the n-type drift layer, and a high-concentration p-type base region formed in the n-type drift layer in a region along the bottom wall of the trench structure.

[0003] US Patent Application Publication No. 2014 / 0145209

[0004] One embodiment provides a semiconductor device capable of improving electrical characteristics.

[0005] One embodiment provides a SiC semiconductor device including: a chip including a SiC single crystal and having a main surface; a trench structure formed on the main surface, the trench structure having a first sidewall extending in the a-axis direction of the SiC single crystal and a second sidewall extending in the m-axis direction of the SiC single crystal; and a first conductivity type contact region formed within the chip in a region along the trench structure and spaced apart from the second sidewall in the a-axis direction.

[0006] One embodiment provides a SiC semiconductor device including: a chip including a SiC single crystal and having a main surface; a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface; a body region of a second conductivity type formed in a surface layer portion of the semiconductor region; a trench source structure formed in the main surface so as to penetrate the body region, the trench source structure having a first sidewall extending in an a-axis direction of the SiC single crystal and a second sidewall extending in an m-axis direction of the SiC single crystal; a trench gate structure formed in the main surface so as to penetrate the body region and spaced apart in the a-axis direction from the second sidewall of the trench source structure; a source region of the first conductivity type formed in a region along the trench gate structure in the surface layer portion of the body region; and a contact region of a second conductivity type formed within the chip in a region along the trench source structure and spaced apart in the a-axis direction from the second sidewall of the trench source structure.

[0007] The above and other objects, features, and advantages will become apparent from the following description of the embodiments with reference to the accompanying drawings.

[0008] FIG. 1 is a plan view showing a SiC semiconductor device according to a first embodiment. FIG. 2 is a plan view showing a layout of a first main surface. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 is an enlarged plan view showing a main portion of the first main surface. FIG. 5 is an enlarged plan view showing another main portion of the first main surface. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5. FIG. 8 is an enlarged plan view showing a region including a second trench structure and a third trench structure. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 8. FIG. 10 is a cross-sectional view taken along line XX in FIG. 8. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 8. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 8. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 8. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 8. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 8 . FIG. 16 is a cross-sectional view showing the peripheral portion of the chip. FIG. 17 is a plan view showing a SiC semiconductor device according to a second embodiment. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 17 . FIG. 19 is a plan view showing a SiC semiconductor device according to a third embodiment. FIG. 20 is a plan view showing a SiC semiconductor device according to a fourth embodiment. FIG. 21 is a plan view showing a SiC semiconductor device according to a fifth embodiment. FIG. 22 is a plan view showing a SiC semiconductor device according to a sixth embodiment. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 22 . FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 22 . FIG. 25 is a plan view showing a SiC semiconductor device according to a seventh embodiment. FIG. 26 is a plan view showing a SiC semiconductor device according to an eighth embodiment. FIG. 27 is a plan view showing a SiC semiconductor device according to a ninth embodiment. FIG. 28 is a plan view showing a SiC semiconductor device according to a tenth embodiment. FIG. 29 is a cross-sectional view showing a modification of the second trench structure.

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When the phrase "substantially equal" is used in a description in which a comparison target is present, this phrase includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not attached with the intent of limiting the names of each structure.

[0011] FIG. 1 is a plan view showing a SiC semiconductor device 1A according to a first embodiment. FIG. 2 is a plan view showing the layout of a first main surface 3. FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. 2. FIG. 4 is an enlarged plan view showing a main portion of the first main surface 3. FIG. 5 is an enlarged plan view showing another main portion of the first main surface 3. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 5.

[0012] FIG. 8 is an enlarged plan view showing a region including the second trench structure 20 and the third trench structure 30. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 8. FIG. 10 is a cross-sectional view taken along line XX shown in FIG. 8. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 8. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 8. FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. 8. FIG. 14 is a cross-sectional view taken along line XIV-XIV shown in FIG. 8. FIG. 15 is a cross-sectional view taken along line XV-XV shown in FIG. 8. FIG. 16 is a cross-sectional view showing the peripheral portion of the chip 2.

[0013] 1 to 16 , a SiC semiconductor device 1A is a SiC semiconductor switching device including a SiC-MISFET (Metal Insulator Semiconductor Field Effect Transistor). In this embodiment, the SiC semiconductor device 1A includes a chip 2 that includes a hexagonal SiC single crystal and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). The hexagonal SiC single crystal has a plurality of polytypes including a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, a 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may include other polytypes.

[0014] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed by the c-plane of the SiC single crystal. Specifically, the first main surface 3 is formed by the silicon surface ((0001) plane) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) plane) of the SiC single crystal.

[0015] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view (hereinafter simply referred to as "plan view") seen from the c-axis direction (

[0001] direction) of the SiC single crystal. The c-axis direction is the normal direction to the c-plane. The c-axis direction also corresponds to the thickness direction of the chip 2. The first main surface 3 and the second main surface 4 may have an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane.

[0016] The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and not greater than 10°. The off-angle is preferably not greater than 5°. When the first main surface 3 (second main surface 4) has an off-angle, the c-axis is inclined in the off-direction by the amount of the off-angle with respect to the normal to the first main surface 3 (second main surface 4). For convenience, the attached drawings illustrate the c-axis extending along the normal to the first main surface 3 (second main surface 4). The second main surface 4 may be a ground surface having grinding marks, or a smooth surface without grinding marks.

[0017] The first side surface 5A and the second side surface 5B extend in the a-axis direction of the SiC single crystal and face the m-axis direction ([1-100] direction) of the SiC single crystal. That is, the first side surface 5A and the second side surface 5B are formed by the m-plane ((1-100) plane) of the SiC single crystal. The third side surface 5C and the fourth side surface 5D extend in the m-axis direction of the SiC single crystal and face the a-axis direction of the SiC single crystal.

[0018] That is, the third side surface 5C and the fourth side surface 5D are formed by the a-plane ((11-20) plane) of the SiC single crystal. The first to fourth side surfaces 5A to 5D may be ground surfaces having grinding marks, or may be smooth surfaces having no grinding marks. The c-axis direction may be referred to as the "thickness direction," the a-axis direction as the "first direction," and the m-axis direction as the "second direction."

[0019] The chip 2 may have a thickness of 5 μm or more and 350 μm or less. The thickness of the chip 2 may be set to a value belonging to any one of the ranges of 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, and 300 μm or more and 350 μm or less. The thickness of the chip 2 is preferably 150 μm or less.

[0020] The first to fourth side surfaces 5A to 5D may have lengths of 0.5 mm or more and 20 mm or less in plan view. The lengths of the first to fourth side surfaces 5A to 5D may be set to a value belonging to any one of the ranges of 0.5 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The lengths of the first to fourth side surfaces 5A to 5D are preferably 5 mm or more.

[0021] The SiC semiconductor device 1A includes an n-type first semiconductor region 6 formed in a region (surface layer portion) on the first main surface 3 side in the chip 2. The first semiconductor region 6 has a surface area of ​​1.0×10 １５ cm －３ Above 1.0 x 10 １７ cm －３The first semiconductor region 6 may have the following n-type impurity concentration (peak value): The first semiconductor region 6 is formed in a layer shape extending along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0022] In this embodiment, the first semiconductor region 6 is made of a SiC epitaxial layer. The first semiconductor region 6 may have a thickness of 1 μm or more and 50 μm or less. The thickness of the first semiconductor region 6 is preferably 5 μm or more and 30 μm or less. The thickness of the first semiconductor region 6 is particularly preferably 25 μm or less.

[0023] The SiC semiconductor device 1A includes an n-type second semiconductor region 7 formed in a region (surface layer portion) on the second main surface 4 side within the chip 2. The second semiconductor region 7 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6 and is electrically connected to the first semiconductor region 6.

[0024] The second semiconductor region 7 is 1.0×10 １８ cm －３ Above 1.0 x 10 ２１ cm －３ The second semiconductor region 7 may have the following n-type impurity concentration (peak value): In this embodiment, the second semiconductor region 7 is made of a SiC substrate. That is, the chip 2 has a layered structure including a SiC substrate and a SiC epitaxial layer.

[0025] The second semiconductor region 7 may have a thickness of 1 μm or more and 350 μm or less. The thickness of the second semiconductor region 7 is preferably 5 μm or more and 50 μm or less. The thickness of the second semiconductor region 7 is particularly preferably 5 μm or more and 20 μm or less. The thickness of the second semiconductor region 7 is preferably 10 μm or more. The thickness of the second semiconductor region 7 may be greater than the thickness of the first semiconductor region 6. The thickness of the second semiconductor region 7 may be less than the thickness of the first semiconductor region 6.

[0026] The SiC semiconductor device 1A includes an active surface 8, an outer surface 9, and first to fourth connecting surfaces 10A to 10D formed on a first main surface 3. The active surface 8, the outer surface 9, and the first to fourth connecting surfaces 10A to 10D define an active plateau 11 on the first main surface 3. The active surface 8 may be referred to as a "first surface portion," the outer surface 9 may be referred to as a "second surface portion," and the first to fourth connecting surfaces 10A to 10D may be referred to as a "connecting surface portion." The active surface 8, the outer surface 9, and the first to fourth connecting surfaces 10A to 10D (i.e., the active plateau 11) may be considered to be components of the chip 2 (first main surface 3).

[0027] The active surface 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 8 has a flat surface formed by the c-plane (Si-plane). In this embodiment, the active surface 8 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0028] The outer side surface 9 is located outside the active surface 8 and is recessed from the active surface 8 in the thickness direction of the chip 2 (toward the second main surface 4). Specifically, the outer side surface 9 is recessed to a depth less than the thickness of the first semiconductor region 6 so as to expose the first semiconductor region 6. The outer side surface 9 extends in a band shape along the active surface 8 in a plan view and is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8. The outer side surface 9 has a flat surface formed by the c-plane (Si-plane) and is formed approximately parallel to the active surface 8. The outer side surface 9 is continuous with the first to fourth side surfaces 5A to 5D.

[0029] The first to fourth connection surfaces 10A to 10D extend in the c-axis direction and connect the active surface 8 and the outer surface 9. The first connection surface 10A is located on the first side surface 5A side, the second connection surface 10B is located on the second side surface 5B side, the third connection surface 10C is located on the third side surface 5C side, and the fourth connection surface 10D is located on the fourth side surface 5D side.

[0030] The first connecting surface 10A and the second connecting surface 10B extend in the a-axis direction in a plan view and face each other in the m-axis direction. That is, the first side surface 5A and the second side surface 5B are formed by m-planes. The third connecting surface 10C and the fourth connecting surface 10D extend in the m-axis direction in a plan view and face each other in the a-axis direction. That is, the third side surface 5C and the fourth side surface 5D are formed by a-planes.

[0031] The first to fourth connection surfaces 10A to 10D may extend substantially perpendicularly between the active surface 8 and the outer side surface 9 so as to define a quadrangular pillar-shaped active plateau 11. The first to fourth connection surfaces 10A to 10D may be inclined obliquely downward from the active surface 8 toward the outer side surface 9 so as to define a quadrangular pyramid-shaped active plateau 11. In this manner, the SiC semiconductor device 1A includes an active plateau 11 defined in a protruding shape in the first semiconductor region 6 on the first main surface 3. The active plateau 11 is formed only in the first semiconductor region 6, and is not formed in the second semiconductor region 7.

[0032] The SiC semiconductor device 1A includes a p-type body region 12 formed in a surface layer portion of the active surface 8. The body region 12 has a density of 1.0×10 １６ cm －３ Above 1.0 x 10 １９ cm －３ The body region 12 may have the following p-type impurity concentration (peak value): The body region 12 is formed in a surface layer portion of the first semiconductor region 6 at a distance from the bottom of the first semiconductor region 6 toward the active surface 8, and faces the second semiconductor region 7 with a part of the first semiconductor region 6 interposed therebetween. The body region 12 is formed in a layer shape extending along the active surface 8. The body region 12 may be exposed from the first to fourth connecting faces 10A to 10D.

[0033] The SiC semiconductor device 1A includes a first trench structure 15 formed in the active surface 8. A gate potential is applied to the first trench structure 15. The first trench structure 15 may also be referred to as a "trench gate wiring structure." The first trench structure 15 penetrates the body region 12 and reaches the first semiconductor region 6. The first trench structure 15 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8, and faces the second semiconductor region 7 with a portion of the first semiconductor region 6 interposed therebetween. The first trench structure 15 preferably has a depth approximately equal to the depth of the outer side surface 9.

[0034] The first trench structure 15 is formed in the peripheral portion of the active surface 8 at a distance from the peripheral edge of the active surface 8 (the first to fourth connecting surfaces 10A to 10D), and extends in a band shape so as to surround the inner portion of the active surface 8. In this embodiment, the first trench structure 15 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connecting surfaces 10A to 10D.

[0035] The first trench structure 15 includes a pad portion 15a and a line portion 15b. The pad portion 15a is disposed on the periphery of the active surface 8 at a distance from the center of the third connecting surface 10C and is formed in a rectangular shape in a plan view. The line portion 15b extends in a strip shape from the pad portion 15a and extends along the periphery of the active surface 8 so as to surround the inner part of the active surface 8. The line portion 15b is formed narrower than the pad portion 15a.

[0036] The first trench structure 15 includes a first trench 16, a first insulating film 17, and a first buried electrode 18. The first trench 16 may be referred to as a "wiring trench," the first insulating film 17 may be referred to as a "wiring insulating film," and the first buried electrode 18 may be referred to as a "wiring buried electrode." The first trench 16 is formed in the active surface 8 and defines the wall surface of the first trench structure 15.

[0037] The first insulating film 17 coats the wall surface of the first trench 16 in a film-like manner. The first insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 17 include a silicon oxide film made of an oxide of the chip 2.

[0038] The first buried electrode 18 is buried in the first trench 16 with the first insulating film 17 sandwiched therebetween. The first buried electrode 18 may protrude above the first main surface 3. The first buried electrode 18 may have a portion that is drawn out from the first trench 16 onto the first main surface 3. The first buried electrode 18 may include conductive polysilicon.

[0039] The SiC semiconductor device 1A includes a plurality of second trench structures 20 formed in the active surface 8. A source potential is applied to the plurality of second trench structures 20. The second trench structures 20 may also be referred to as "trench source structures." The plurality of second trench structures 20 are formed inward of the active surface 8 at intervals from the first trench structures 15. The plurality of second trench structures 20 penetrate the body region 12 and reach the first semiconductor region 6.

[0040] The plurality of second trench structures 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The plurality of second trench structures 20 preferably have a depth approximately equal to that of the first trench structure 15. The plurality of second trench structures 20 preferably have a depth approximately equal to that of the outer side surface 9. The second trench structures 20 are preferably formed narrower than the first trench structures 15.

[0041] The plurality of second trench structures 20 are arranged at intervals in the a-axis direction and the m-axis direction in plan view. The plurality of second trench structures 20 may be arranged in a matrix in plan view. In this case, the SiC semiconductor device 1A includes the plurality of second trench structures 20 arranged at intervals so as to face each other in the a-axis direction and the m-axis direction.

[0042] The multiple second trench structures 20 may be arranged in a staggered pattern in a plan view. In this case, the SiC semiconductor device 1A may include multiple groups of multiple second trench structures 20 arranged in a line at intervals in the a-axis direction and arranged at intervals in the m-axis direction. In this case, the multiple second trench structures 20 belonging to one group are arranged shifted in the a-axis direction so as to face a region (e.g., an intermediate portion) between the multiple second trench structures 20 belonging to the other group in the m-axis direction.

[0043] Of course, the SiC semiconductor device 1A may include a plurality of groups each including a plurality of second trench structures 20 arranged in a line at intervals in the m-axis direction and arranged at intervals in the a-axis direction, in which case the plurality of second trench structures 20 belonging to one group are arranged shifted in the m-axis direction so as to face a region (e.g., an intermediate portion) between the plurality of second trench structures 20 belonging to the other group in the a-axis direction.

[0044] The configuration of one second trench structure 20 will be described below. Referring to FIGS. 8 to 15 , in this embodiment, the second trench structure 20 is formed in a ring shape (specifically, a square ring shape) extending in the a-axis direction and the m-axis direction in plan view. The second trench structure 20 includes an inner wall 21, an outer wall 22, and a bottom wall 23.

[0045] The inner sidewalls 21 form the inner edges of the second trench structures 20 and are formed in a quadrangular shape extending in the a-axis and m-axis directions in plan view. Specifically, the inner sidewalls 21 include a pair of first inner sidewalls 21A and a pair of second inner sidewalls 21B.

[0046] The pair of first inner side walls 21A extend in the a-axis direction and face each other in the m-axis direction. That is, the pair of first inner side walls 21A are defined by m-planes. The pair of second inner side walls 21B extend in the m-axis direction to be connected to the pair of first inner side walls 21A and face each other in the a-axis direction. That is, the pair of second inner side walls 21B are defined by a-planes. The inner side walls 21 define a rectangular first mesa portion 24 on the active surface 8.

[0047] The outer wall 22 forms the outer edge of the second trench structure 20 and surrounds the inner wall 21 in a plan view. The outer wall 22 is formed in a quadrangular shape extending in the a-axis direction and the m-axis direction. Specifically, the outer wall 22 includes a pair of first outer walls 22A and a pair of second outer walls 22B.

[0048] The pair of first outer walls 22A extend in the a-axis direction and face each other in the m-axis direction. That is, the pair of first outer walls 22A are defined by m-planes. The pair of second outer walls 22B extend in the m-axis direction to be connected to the pair of first outer walls 22A and face each other in the a-axis direction. That is, the pair of second outer walls 22B are defined by a-planes.

[0049] The bottom wall 23 connects the inner wall 21 and the outer wall 22 and is formed in a ring shape (specifically, a rectangular ring shape) extending in the a-axis direction and the m-axis direction in plan view. Specifically, the bottom wall 23 includes a pair of first bottom walls 23A and a pair of second bottom walls 23B.

[0050] The pair of first bottom walls 23A extend in a strip-like manner in the a-axis direction. The pair of second bottom walls 23B extend in a strip-like manner in the m-axis direction so as to be connected to the pair of first bottom walls 23A. The bottom walls 23 are formed by the c-plane. When the active surface 8 (first main surface 3) has an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane, the bottom walls 23 may have an off-direction and off-angle similar to the active surface 8 (first main surface 3).

[0051] The second trench structure 20 includes a second trench 25, a second insulating film 26, and a second buried electrode 27. The second trench 25 may be referred to as a "source trench," the second insulating film 26 may be referred to as a "source insulating film," and the second buried electrode 27 may be referred to as a "source buried electrode." The second trench 25 is formed in the active surface 8 and defines the wall surfaces (inner wall 21, outer wall 22, and bottom wall 23) of the second trench structure 20.

[0052] The second insulating film 26 coats the wall surface of the second trench 25 in a film-like manner. The second insulating film 26 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second insulating film 26 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 26 includes a silicon oxide film made of an oxide of the chip 2. The second buried electrode 27 is buried in the second trench 25 with the second insulating film 26 sandwiched therebetween. The second buried electrode 27 may include conductive polysilicon.

[0053] The SiC semiconductor device 1A includes a third trench structure 30 formed in the active surface 8 at a distance from the plurality of second trench structures 20. A gate potential is applied to the third trench structure 30. The third trench structure 30 may also be referred to as a "trench gate structure." The third trench structure 30 penetrates the body region 12 and reaches the first semiconductor region 6.

[0054] The third trench structure 30 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6. The third trench structure 30 preferably has a depth approximately equal to that of the first trench structure 15 (second trench structure 20). The third trench structure 30 preferably has a depth approximately equal to that of the outer side surface 9. The third trench structure 30 is preferably formed narrower than the first trench structure 15. The width of the third trench structure 30 is preferably approximately equal to the width of the second trench structure 20.

[0055] The third trench structure 30 is formed in a lattice shape extending in the a-axis and m-axis directions in the regions between the second trench structures 20 so as to surround the second trench structures 20 in a plan view. In other words, the third trench structure 30 is formed in a ring shape (specifically, a quadrangular ring shape) surrounding each second trench structure 20 in a plan view. The third trench structure 30 defines a plurality of second mesas 31 extending in a ring shape (specifically, a quadrangular ring shape) between itself and the outer walls 22 of the second trench structures 20. The third trench structure 30 is electrically and mechanically connected to the first trench structure 15 at the peripheral portion of the active surface 8.

[0056] Specifically, the third trench structure 30 includes a plurality of third trench structures 30A extending in the a-axis direction and a plurality of third trench structures 30B extending in the m-axis direction. The plurality of third trench structures 30A are formed at intervals in the m-axis direction from the plurality of first outer walls 22A so as to face the plurality of first outer walls 22A in the m-axis direction, and extend in a band-like manner in the a-axis direction through the region between the plurality of first outer walls 22A. The plurality of third trench structures 30A are electrically and mechanically connected to the first trench structure 15 at the peripheral portion of the active surface 8.

[0057] Each third trench structure 30A has a pair of first gate sidewalls 32 extending in the a-axis direction and a first gate bottom wall 33 extending in the a-axis direction. The pair of first gate sidewalls 32 are formed by the m-plane, and the first gate bottom wall 33 is formed by the c-plane. When the active surface 8 (first main surface 3) has an off-angle tilted at a predetermined angle in a predetermined off-direction with respect to the c-plane, the first gate bottom wall 33 may have an off-direction and off-angle similar to the active surface 8 (first main surface 3).

[0058] The plurality of third trench structures 30B are formed at intervals in the a-axis direction from the plurality of second outer walls 22B so as to face the plurality of second outer walls 22B in the a-axis direction, and extend in a band-like manner in the m-axis direction through the region between the plurality of second outer walls 22B. The plurality of third trench structures 30B intersect (specifically, orthogonally) with the plurality of third trench structures 30A in the inner portion of the active surface 8, and together with the plurality of third trench structures 30A, form a plurality of trench intersections 34.

[0059] In this configuration, the trench intersections 34 each form a cross in plan view. When the second trench structures 20 are arranged in a staggered pattern in plan view, the trench intersections 34 each form a T-junction in plan view. The third trench structures 30B are electrically and mechanically connected to the first trench structures 15 at the peripheral portions of the active surface 8.

[0060] Each third trench structure 30B has a pair of second gate sidewalls 35 extending in the m-axis direction and a second gate bottom wall 36 extending in the m-axis direction. The pair of second gate sidewalls 35 are formed of the a-plane, and the second gate bottom wall 36 is formed of the c-plane. When the active surface 8 (first major surface 3) has an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane, the second gate bottom wall 36 may have the same off-direction and off-angle as the active surface 8 (first major surface 3). A trench intersection 34 is formed by the intersection of the first gate bottom wall 33 and the second gate bottom wall 36.

[0061] The third trench structure 30 includes a third trench 37, a third insulating film 38, and a third buried electrode 39. The third trench 37 may be referred to as a "gate trench," the third insulating film 38 may be referred to as a "gate insulating film," and the third buried electrode 39 may be referred to as a "gate buried electrode." The third trench 37 is formed in the active surface 8 and defines the wall surface of the third trench structure 30. The third trench 37 communicates with the first trench 16 at the peripheral portion of the active surface 8.

[0062] The third insulating film 38 coats the wall surface of the third trench 37 in a film-like manner. The third insulating film 38 is connected to the first insulating film 17 at the communicating portion between the first trench 16 and the third trench 37. The third insulating film 38 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the third insulating film 38 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the third insulating film 38 include a silicon oxide film made of an oxide of the chip 2.

[0063] The third buried electrode 39 is buried in the third trench 37 with the third insulating film 38 sandwiched therebetween. The third buried electrode 39 is electrically and mechanically connected to the first buried electrode 18 at the communicating portion between the first trench 16 and the third trench 37. The third buried electrode 39 may include conductive polysilicon.

[0064] The SiC semiconductor device 1A includes a plurality of n-type source regions 40 formed in a region along the third trench structure 30 in a surface layer portion of the body region 12. Specifically, the plurality of source regions 40 are formed in a plurality of second mesas 31 in the surface layer portion of the body region 12. Each source region 40 has a higher n-type impurity concentration than the first semiconductor region 6. The n-type impurity concentration (peak value) of the source region 40 is 1.0×10 １８ cm －３ Above 1.0 x 10 ２１ cm －３ The plurality of source regions 40 are formed at intervals from the bottom of the body region 12 toward the active surface 8 , and are formed in layers extending along the active surface 8 .

[0065] In this embodiment, each source region 40 is formed in a ring shape (specifically, a square ring shape) extending along the second mesa portion 31 so as to surround each second trench structure 20 in a plan view, and is connected to the second trench structure 20 and the third trench structure 30. Each source region 40 is exposed from the first outer sidewall 22A and the second outer sidewall 22B of the second trench structure 20, and is exposed from the first gate sidewall 32 and the second gate sidewall 35 of the third trench structure 30. Each source region 40, together with the first semiconductor region 6, forms a channel in the body region 12.

[0066] 8 to 15, the SiC semiconductor device 1A includes a plurality of p-type well regions 41 formed in regions along the second trench structures 20 in the chip 2. In this embodiment, the plurality of well regions 41 have a higher p-type impurity concentration than the body region 12. Of course, the plurality of well regions 41 may have a lower p-type impurity concentration than the body region 12. The p-type impurity concentration (peak value) of the well region 41 is 1.0×10 １６ cm －３ Above 1.0 x 10 １８ cm －３ It may be the following:

[0067] The configuration of one well region 41 will be specifically described below. In this embodiment, the well region 41 includes a well bottom wall portion 42, a well inner wall portion 43, and a well outer wall portion 44. The well bottom wall portion 42 may be referred to as the "first well portion," the well inner wall portion 43 may be referred to as the "second well portion," and the well outer wall portion 44 may be referred to as the "third well portion."

[0068] The well bottom wall portion 42 is formed in a region along the bottom wall 23 of the second trench structure 20. Specifically, the well bottom wall portion 42 is formed in a region along the pair of first bottom walls 23A and the pair of second bottom walls 23B. The well bottom wall portion 42 is formed in a ring shape (specifically, a square ring shape) extending along the bottom wall 23 of the second trench structure 20 in a plan view, and covers the entire bottom wall 23 of the second trench structure 20. The well bottom wall portion 42 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8, and faces the second semiconductor region 7 with a portion of the first semiconductor region 6 in between.

[0069] The well inner wall portion 43 is extended from the well bottom wall portion 42 toward the inner sidewall 21 of the second trench structure 20 and is formed in a region along the inner sidewall 21. Specifically, the well inner wall portion 43 is formed in the first mesa portion 24 in a region along the pair of first inner sidewalls 21A and the pair of second inner sidewalls 21B.

[0070] The well inner wall portion 43 is formed in a ring shape (specifically, a square ring shape) extending along the inner wall 21 so as to surround the inner portion of the body region 12 in a plan view. The well inner wall portion 43 is connected to the body region 12 at a surface portion of the first mesa portion 24. The thickness of the well inner wall portion 43 measured from the inner wall 21 is smaller than the thickness of the well bottom wall portion 42 measured from the bottom wall 23.

[0071] The well outer wall portion 44 is extended from the bottom wall 23 side of the second trench structure 20 toward the outer wall 22 side of the second trench structure 20 and is formed in a region along the outer wall 22. Specifically, the well outer wall portion 44 is formed in the second mesa portion 31 in a region along the pair of first outer walls 22A and the pair of second outer walls 22B.

[0072] The well outer wall 44 is formed in the second mesa portion 31 in a ring shape (specifically, a square ring shape) surrounding the second trench structure 20 at a distance from the third trench structure 30. The well outer wall 44 is connected to the body region 12 in a surface layer portion of the second mesa portion 31. The thickness of the well outer wall 44 measured from the outer wall 22 is smaller than the thickness of the well bottom wall 42 measured from the bottom wall 23.

[0073] 8 to 15, SiC semiconductor device 1A includes a plurality of p-type contact regions 50 formed in regions along the corresponding second trench structures 20 in chip 2. Specifically, the plurality of contact regions 50 are formed in regions along the corresponding second trench structures 20 in the corresponding well regions 41.

[0074] The plurality of contact regions 50 have a p-type impurity concentration higher than that of the body region 12. The plurality of contact regions 50 have a p-type impurity concentration higher than that of the well region 41. The p-type impurity concentration (peak value) of the contact region 50 is 1.0×10 １７ cm －３ Above 1.0 x 10 ２１ cm －３ The contact region 50 preferably contains aluminum (Al) as a p-type impurity.

[0075] The configuration of one contact region 50 will be described in detail below. The contact region 50 is formed in the well region 41 at a distance in the a-axis direction from a pair of second outer sidewalls 22B of the second trench structure 20. In this embodiment, the contact region 50 includes a first contact region 51, a second contact region 52, and a third contact region 53. The first to third contact regions 51 to 53 are formed in a cell region surrounded by the third trench structure 30, with different positional relationships (relative positions) with respect to one second trench structure 20.

[0076] The first contact region 51 is formed in the well region 41 at a distance from the pair of second outer sidewalls 22B of the second trench structure 20 in the a-axis direction, and is not formed in a region along the pair of second outer sidewalls 22B. The first contact region 51 is formed in the well region 41 at a distance from the pair of second inner sidewalls 21B of the second trench structure 20 in the a-axis direction, and is not formed in a region along the pair of second inner sidewalls 21B.

[0077] The first contact region 51 is formed in a region along one of the first bottom walls 23A of the second trench structure 20, spaced apart in the a-axis direction from the pair of second bottom walls 23B in the well region 41, but is not formed in a region along the pair of second bottom walls 23B. The first contact region 51 is preferably formed in a region along the widthwise middle portion of one of the first bottom walls 23A in a plan view.

[0078] In this embodiment, the first contact region 51 includes a first bottom wall portion 54, a first inner wall portion 55, and a first outer wall portion 56. The first bottom wall portion 54 may be referred to as the "first contact portion," the first inner wall portion 55 may be referred to as the "second contact portion," and the first outer wall portion 56 may be referred to as the "third contact portion."

[0079] The first bottom wall portion 54 is formed in a region along one of the first bottom walls 23A within the well region 41 (well bottom wall portion 42) and spaced apart from the pair of second bottom walls 23B. The first bottom wall portion 54 is preferably formed in a region along the center of the first bottom wall 23A. The first bottom wall portion 54 is formed at a distance from the bottom of the well region 41 toward the first bottom wall 23A, and faces the first semiconductor region 6 across a portion of the well region 41.

[0080] The first inner wall portion 55 is extended from the first bottom wall portion 54 along the m-axis direction within the well region 41 (well inner wall portion 43) toward one of the first inner side walls 21A of the second trench structure 20, and is formed in a region along one of the first inner side walls 21A. The first inner wall portion 55 is formed in a region along the inner portion of the first inner side wall 21A, spaced apart from the pair of second inner side walls 21B in the a-axis direction. The first inner wall portion 55 is preferably formed in a region along the central portion of the first inner side wall 21A. The first inner wall portion 55 is extended from within the well region 41 into the body region 12 in the first mesa portion 24.

[0081] The first inner wall portion 55 has a first exposed portion 57 exposed from the active surface 8 in the first mesa portion 24. The first exposed portion 57 extends in a layered manner along the active surface 8 with a gap therebetween from the bottom of the body region 12 toward the active surface 8, and faces the first semiconductor region 6 with a part of the body region 12 interposed therebetween. The thickness of the first inner wall portion 55 measured from the first inner sidewall 21A is smaller than the thickness of the first bottom wall portion 54 measured from the first bottom wall 23A.

[0082] The first outer wall portion 56 is extended from the first bottom wall portion 54 in the well region 41 (well outer wall portion 44) along the m-axis direction toward one of the first outer walls 22A of the second trench structure 20, and is formed in a region along one of the first outer walls 22A. The first outer wall portion 56 is formed in a region along the inner portion of the first outer wall 22A, spaced apart from the pair of second outer walls 22B in the a-axis direction. The first outer wall portion 56 is preferably formed in a region along the central portion of the first outer wall 22A. The first outer wall portion 56 is extended from the well region 41 into the body region 12 in the second mesa portion 31.

[0083] The first outer wall portion 56 has a second exposed portion 58 exposed from the active surface 8 in the second mesa portion 31. The second exposed portion 58 extends in a layered manner along the active surface 8 with a gap therebetween from the bottom of the body region 12 toward the active surface 8, and faces the first semiconductor region 6 with a part of the body region 12 sandwiched between them. The second exposed portion 58 is formed with a gap therebetween from the third trench structure 30 toward the second trench structure 20, and is connected to the source region 40. The thickness of the first outer wall portion 56 measured from the first outer sidewall 22A is smaller than the thickness of the first bottom wall portion 54 measured from the first bottom wall 23A.

[0084] The second contact region 52 is formed in the well region 41 in a region different from the first contact region 51, spaced apart in the a-axis direction from the pair of second outer sidewalls 22B of the second trench structure 20, and is not formed in a region along the pair of second outer sidewalls 22B. The second contact region 52 is formed in the well region 41 in a region spaced apart in the a-axis direction from the pair of second inner sidewalls 21B of the second trench structure 20, and is not formed in a region along the pair of second inner sidewalls 21B.

[0085] The second contact region 52 is formed in the well region 41 in a region along the other first bottom wall 23A of the second trench structure 20, spaced apart in the a-axis direction from the pair of second bottom walls 23B of the second trench structure 20, but not in a region along the pair of second bottom walls 23B. The second contact region 52 is preferably formed in a region facing the first contact region 51 in the m-axis direction in plan view. The second contact region 52 is preferably formed in a region along the widthwise middle portion of the other first bottom wall 23A in plan view.

[0086] In this embodiment, the second contact region 52 includes a second bottom wall portion 59, a second inner wall portion 60, and a second outer wall portion 61. The second bottom wall portion 59 may be referred to as the "first contact portion," the second inner wall portion 60 may be referred to as the "second contact portion," and the second outer wall portion 61 may be referred to as the "third contact portion."

[0087] The second bottom wall portion 59 is formed in a region along the other first bottom wall 23A within the well region 41 (well bottom wall portion 42) at a distance from the pair of second bottom walls 23B. The second bottom wall portion 59 is preferably formed in a region along the center of the first bottom wall 23A. The second bottom wall portion 59 faces the first semiconductor region 6 across a portion of the well region 41.

[0088] The second inner wall portion 60 is extended from the second bottom wall portion 59 along the m-axis direction in the well region 41 (well inner wall portion 43) toward the other first inner wall 21A of the second trench structure 20, and is formed in a region along the other first inner wall 21A. The second inner wall portion 60 is formed in a region along the inner portion of the first inner wall 21A, spaced apart from the pair of second inner walls 21B in the a-axis direction. The second inner wall portion 60 is preferably formed in a region along the central portion of the first inner wall 21A. The second inner wall portion 60 is extended from the well region 41 into the body region 12 in the first mesa portion 24.

[0089] The second inner wall portion 60 has a third exposed portion 62 exposed from the active surface 8 in the first mesa portion 24. The third exposed portion 62 extends in a layered manner along the active surface 8 with a gap therebetween from the bottom of the body region 12 toward the active surface 8, and faces the first semiconductor region 6 with a part of the body region 12 interposed therebetween. The thickness of the second inner wall portion 60 measured from the first inner side wall 21A is smaller than the thickness of the second bottom wall portion 59 measured from the first bottom wall 23A.

[0090] The second outer wall portion 61 is extended from the second bottom wall portion 59 along the m-axis direction within the well region 41 (well outer wall portion 44) toward the other first outer wall 22A of the second trench structure 20, and is formed in a region along the other first outer wall 22A. The second outer wall portion 61 is formed in a region along the inner portion of the first outer wall 22A, spaced apart from the pair of second outer walls 22B in the a-axis direction. The second outer wall portion 61 is preferably formed in a region along the central portion of the first outer wall 22A. The second outer wall portion 61 is extended from within the well region 41 into the body region 12 in the second mesa portion 31.

[0091] The second outer wall portion 61 has a fourth exposed portion 63 exposed from the active surface 8 in the second mesa portion 31. The fourth exposed portion 63 extends in a layered manner along the active surface 8 with a gap therebetween from the bottom of the body region 12 toward the active surface 8, and faces the first semiconductor region 6 with a part of the body region 12 sandwiched between them. The fourth exposed portion 63 is formed with a gap therebetween from the third trench structure 30 toward the second trench structure 20, and is connected to the source region 40. The thickness of the second outer wall portion 61 measured from the first outer sidewall 22A is smaller than the thickness of the second bottom wall portion 59 measured from the first bottom wall 23A.

[0092] The third contact region 53 is formed in a surface layer portion of the body region 12 in the first mesa portion 24. The third contact region 53 extends in a layered manner along the active surface 8 at a distance from the bottom of the body region 12 toward the active surface 8, and faces the first semiconductor region 6 across a part of the body region 12. The third contact region 53 is preferably formed in the body region 12 at a distance in the a-axis direction from the pair of second inner sidewalls 21B of the second trench structure 20.

[0093] That is, it is preferable that the third contact region 53 is not formed in a region along the pair of second inner sidewalls 21B. The third contact region 53 is formed in a strip shape extending in the m-axis direction in the first mesa portion 24, and is connected to the first exposed portion 57 of the first contact region 51 and the third exposed portion 62 of the second contact region 52.

[0094] That is, in this embodiment, the contact region 50 integrally includes the first to third contact regions 51 to 53 and is formed in a band shape extending in the m-axis direction in plan view. In this embodiment, the contact region 50 has a first width W1 in the m-axis direction and a second width W2 in the a-axis direction that is less than the first width W1.

[0095] The first width W1 is larger than the width of the second trench structure 20. The width of the second trench structure 20 is the width in a direction perpendicular to the direction in which the second trench structure 20 extends. The first width W1 is larger than the width of the second inner sidewall 21B of the second trench structure 20. The first width W1 is larger than the width of the second outer sidewall 22B of the second trench structure 20.

[0096] The second width W2 is smaller than the width of the first outer sidewall 22A of the second trench structure 20. The second width W2 is smaller than the width of the first inner sidewall 21A of the second trench structure 20. The second width W2 is preferably smaller than the width of the second trench structure 20. Of course, the second width W2 may be larger than the width of the second trench structure 20.

[0097] 8 to 15 , the SiC semiconductor device 1A includes a plurality of p-type gate well regions 65 formed in regions along a plurality of trench intersections 34 in the chip 2. The plurality of gate well regions 65 have a lower p-type impurity concentration than the contact region 50. In this embodiment, the plurality of gate well regions 65 have a higher p-type impurity concentration than the body region 12. Of course, the plurality of gate well regions 65 may have a lower p-type impurity concentration than the body region 12.

[0098] The plurality of gate well regions 65 preferably have a p-type impurity concentration substantially equal to that of the well region 41. The p-type impurity concentration (peak value) of the gate well region 65 is 1.0×10 １６ cm －３ Above 1.0 x 10 １８ cm －３ The plurality of gate well regions 65 are formed in regions along the plurality of trench intersections 34 at intervals in the a-axis direction and the m-axis direction, and expose regions of the bottom wall (first gate bottom wall 33 and second gate bottom wall 36) of the third trench structure 30 outside the plurality of trench intersections 34.

[0099] Each gate well region 65 covers the first gate sidewall 32 of the third trench structure 30A and the second gate sidewall 35 of the third trench structure 30B at the corner of each second mesa portion 31, and is connected to the body region 12 at the surface portion of each second mesa portion 31. The multiple gate well regions 65 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 with part of the first semiconductor region 6 in between. The bottoms of the multiple gate well regions 65 are preferably formed at a depth position substantially equal to the bottom of the well region 41.

[0100] 6 and 7 , SiC semiconductor device 1A includes a wiring well region 66 formed in chip 2 in a region along the wall surface of first trench structure 15. Wiring well region 66 has a lower p-type impurity concentration than contact region 50. In this embodiment, wiring well region 66 has a higher p-type impurity concentration than body region 12.

[0101] Of course, the wiring well region 66 may have a p-type impurity concentration lower than that of the body region 12. The wiring well region 66 preferably has a p-type impurity concentration approximately equal to that of the well region 41. The p-type impurity concentration (peak value) of the wiring well region 66 is 1.0×10 １６ cm －３ Above 1.0 x 10 １８ cm －３ It may be the following:

[0102] The wiring well region 66 is formed in the pad portion 15a and the line portion 15b of the first trench structure 15 in regions along the inner wall, outer wall, and bottom wall of the first trench structure 15, and is connected to the body region 12 in a surface layer portion of the active surface 8. The wiring well region 66 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8, and faces the second semiconductor region 7 with a part of the first semiconductor region 6 in between. The bottom of the wiring well region 66 is preferably formed at a depth position substantially equal to the bottom of the well region 41.

[0103] 16 , SiC semiconductor device 1A includes a p-type outer well region 67 formed in a surface layer portion of outer side surface 9. Outer well region 67 has a lower p-type impurity concentration than contact region 50. In this embodiment, outer well region 67 has a higher p-type impurity concentration than body region 12.

[0104] Of course, the outer well region 67 may have a p-type impurity concentration lower than that of the body region 12. The outer well region 67 preferably has a p-type impurity concentration approximately equal to that of the well region 41. The p-type impurity concentration (peak value) of the outer well region 67 is 1.0×10 １６ cm －３ Above 1.0 x 10 １８cm －３ It may be the following:

[0105] The outer well region 67 is formed at a distance from the periphery of the outer side surface 9 (first to fourth side surfaces 5A to 5D) toward the active surface 8 in a plan view, and extends in a band shape along the active surface 8. In this embodiment, the outer well region 67 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8 in a plan view. The outer well region 67 extends from the surface layer portion of the outer side surface 9 toward the surface layer portions of the first to fourth connection surfaces 10A to 10D, and covers the first to fourth connection surfaces 10A to 10D. The outer well region 67 is electrically connected to the body region 12 in the surface layer portion of the active surface 8.

[0106] The outer well region 67 is formed at a distance from the bottom of the first semiconductor region 6 toward the outer surface 9, and faces the second semiconductor region 7 across a part of the first semiconductor region 6. The outer well region 67 is located closer to the bottom of the first semiconductor region 6 than the bottom walls 23 of the multiple second trench structures 20. The bottom of the outer well region 67 is located closer to the bottom of the first semiconductor region 6 than the bottoms of the contact region 50 (first bottom wall portion 54 and second bottom wall portion 59). The bottom of the outer well region 67 is preferably formed at a depth position substantially equal to the bottom of the well region 41.

[0107] The SiC semiconductor device 1A includes a p-type outer contact region 68 formed in a surface layer portion of the outer well region 67. The outer contact region 68 has a higher p-type impurity concentration than the body region 12. The outer contact region 68 has a higher p-type impurity concentration than the outer well region 67.

[0108] The outer contact region 68 preferably has a p-type impurity concentration that is approximately equal to that of the contact region 50. The p-type impurity concentration (peak value) of the outer contact region 68 is 1.0×10 １７ cm －３ Above 1.0 x 10 ２１ cm －３ The outer contact region 68 preferably contains aluminum (Al) as a p-type impurity.

[0109] The outer contact region 68 is formed in the surface layer portion of the outer well region 67 at a distance from the periphery of the active surface 8 (first to fourth connection surfaces 10A to 10D) and the periphery of the outer side surface 9 (first to fourth side surfaces 5A to 5D) in plan view, and is formed in a band shape extending along the active surface 8. In this embodiment, the outer contact region 68 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in plan view.

[0110] The outer contact region 68 is formed at a distance from the bottom of the outer well region 67 toward the outer surface 9, and faces the first semiconductor region 6 across a part of the outer well region 67. The outer contact region 68 is located closer to the bottom of the first semiconductor region 6 than the bottom walls 23 of the plurality of second trench structures 20. The bottom of the outer contact region 68 is preferably formed at a depth position substantially equal to the bottom of the contact region 50 (first bottom wall portion 54 and second bottom wall portion 59).

[0111] The SiC semiconductor device 1A includes at least one (preferably two or more and twenty or less) p-type field region 69 formed in a surface layer portion of the outer surface 9 in a region between the periphery of the outer surface 9 and the outer well region 67. In this embodiment, the SiC semiconductor device 1A includes four field regions 69. The multiple field regions 69 are formed in an electrically floating state and relieve the electric field within the chip 2 at the outer surface 9.

[0112] The number, width, depth, p-type impurity concentration, etc. of the field regions 69 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The plurality of field regions 69 may have a p-type impurity concentration lower than that of the outer contact region 68. The plurality of field regions 69 may have a p-type impurity concentration higher than that of the outer well region 67. The plurality of field regions 69 may have a p-type impurity concentration lower than that of the outer well region 67. The p-type impurity concentration (peak value) of the field region 69 is 1.0×10 １６ cm －３ Above 1.0 x 10 ２１ cm －３ It may be the following:

[0113] The field regions 69 are arranged at intervals from the outer contact region 68 side to the peripheral edge of the outer side surface 9. The field regions 69 are formed in strip shapes extending along the active surface 8 in a plan view. In this embodiment, the field regions 69 are formed in a ring shape (specifically, a square ring) surrounding the active surface 8 in a plan view.

[0114] The plurality of field regions 69 are formed at intervals from the bottom of the first semiconductor region 6 toward the outer side surface 9, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The plurality of field regions 69 are located closer to the bottom of the first semiconductor region 6 than the bottom walls 23 of the plurality of second trench structures 20. The bottoms of the plurality of field regions 69 are located closer to the bottom of the first semiconductor region 6 than the bottoms of the contact region 50 (first bottom wall portion 54 and second bottom wall portion 59). The bottoms of the plurality of field regions 69 may be formed at a depth position substantially equal to the bottom of the well region 41.

[0115] The SiC semiconductor device 1A includes a main surface insulating film 70 that covers the first main surface 3. The main surface insulating film 70 has a layered structure including a first main surface insulating film 71 and a second main surface insulating film 72. The first main surface insulating film 71 covers the active surface 8, the outer side surface 9, and the first to fourth connecting surfaces 10A to 10D.

[0116] The first main surface insulating film 71 is continuous with the first insulating film 17 and the third insulating film 38 on the active surface 8, and exposes the first buried electrode 18, the second buried electrode 27, and the third buried electrode 39. The main surface insulating film 70 covers the outer contact region 68, the outer well region 67, and the plurality of field regions 69 on the outer side surface 9 and the first to fourth connecting surfaces 10A to 10D.

[0117] The first main surface insulating film 71 may be continuous with the first to fourth side surfaces 5A to 5D. In this case, the outer wall of the first main surface insulating film 71 may be made of a ground surface having grinding marks. The outer wall of the first main surface insulating film 71 may form a single ground surface together with the first to fourth side surfaces 5A to 5D. Of course, the outer wall of the first main surface insulating film 71 may be made of a smooth surface without grinding marks. Furthermore, the outer wall of the first main surface insulating film 71 may be formed at a distance inward from the periphery of the outer surface 9, exposing the first semiconductor region 6 from the periphery of the outer surface 9.

[0118] The first main surface insulating film 71 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first main surface insulating film 71 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first main surface insulating film 71 include a silicon oxide film made of an oxide of the chip 2.

[0119] The second main surface insulating film 72 covers the active surface 8, the outer side surface 9, and the first to fourth connecting surfaces 10A to 10D with the first main surface insulating film 71 in between. The second main surface insulating film 72 covers the first trench structure 15 and the third trench structure 30 on the active surface 8. The second main surface insulating film 72 covers the outer contact region 68, the outer well region 67, and the plurality of field regions 69 on the outer side surface 9 and the first to fourth connecting surfaces 10A to 10D.

[0120] In this embodiment, the second main surface insulating film 72 is continuous with the first to fourth side surfaces 5A to 5D. The outer wall of the second main surface insulating film 72 may be made of a ground surface having grinding marks. The outer wall of the second main surface insulating film 72 may form a single ground surface together with the first to fourth side surfaces 5A to 5D. Of course, the outer wall of the second main surface insulating film 72 may be made of a smooth surface without grinding marks. Furthermore, the outer wall of the second main surface insulating film 72 may be formed at a distance inward from the periphery of the outer surface 9, exposing the first semiconductor region 6 from the periphery of the outer surface 9.

[0121] The second main surface insulating film 72 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second main surface insulating film 72 has a single-layer structure made of a silicon oxide film.

[0122] The SiC semiconductor device 1A includes a sidewall structure 73 arranged in a main surface insulating film 70 so as to cover at least one of the first to fourth connecting surfaces 10A to 10D on the outer side surface 9. Specifically, the sidewall structure 73 is arranged on a first main surface insulating film 71 and is covered by a second main surface insulating film 72. In this embodiment, the sidewall structure 73 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8 in a plan view. The sidewall structure 73 may include an inorganic insulator or polysilicon.

[0123] The SiC semiconductor device 1A includes one or more (one in this embodiment) first gate openings 74 formed in the main surface insulating film 70. The first gate openings 74 expose the pad portions 15a of the first trench structures 15. The SiC semiconductor device 1A includes one or more (one in this embodiment) second gate openings 75 formed in the main surface insulating film 70. The second gate openings 75 extend in a strip shape along the line portions 15b of the first trench structures 15, and expose the first buried electrodes 18 of the line portions 15b.

[0124] The SiC semiconductor device 1A includes a plurality of source openings 76 formed at intervals in the main surface insulating film 70. The plurality of source openings 76 expose the corresponding second trench structures 20, the corresponding first mesa portions 24, and the corresponding second mesa portions 31. The plurality of source openings 76 expose the body region 12 and the contact region 50 from the corresponding first mesa portions 24, and expose the source region 40 and the contact region 50 from the corresponding second mesa portions 31. In this embodiment, each source opening 76 is formed in a quadrangular shape in a plan view.

[0125] The SiC semiconductor device 1A includes one or more (one in this embodiment) outer openings 77 formed in the main surface insulating film 70. The outer openings 77 extend in a strip-like or annular shape along the outer contact region 68, exposing the outer contact region 68.

[0126] The SiC semiconductor device 1A includes a gate electrode 80 disposed on a main surface insulating film 70. The gate electrode 80 may also be referred to as a "gate main surface electrode." The gate electrode 80 includes a gate pad electrode 81 and a gate line electrode 82. The gate pad electrode 81 is disposed on the pad portion 15a of the first trench structure 15 at a distance from the periphery of the active surface 8. In this embodiment, the gate pad electrode 81 is formed in a quadrangular shape in a plan view. The gate pad electrode 81 extends from above the main surface insulating film 70 into the first gate opening 74 and is electrically connected to the first buried electrode 18 of the pad portion 15a.

[0127] The gate line electrode 82 is drawn out from the gate pad electrode 81 onto the line portion 15b of the first trench structure 15. In this embodiment, the gate line electrode 82 covers the line portion 15b at a distance from the periphery of the active surface 8. The gate line electrode 82 is formed in a strip shape extending along the line portion 15b in a plan view.

[0128] In this embodiment, the gate line electrode 82 extends along the first to third side surfaces 5A to 5C (first to third connecting surfaces 10A to 10C), and has a pair of open ends 83 in the portion along the fourth side surface 5D (fourth connecting surface 10D). The gate line electrode 82 extends from above the main surface insulating film 70 into the second gate opening 75, and is electrically connected to the first buried electrode 18 of the line portion 15b.

[0129] The gate electrode 80 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. The gate electrode 80 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the gate electrode 80 has a layered structure including a Ti film, a TiN film, and an Al alloy film (an AlCu alloy film in this embodiment) layered in this order from the chip 2 side.

[0130] The SiC semiconductor device 1A includes a source electrode 85 disposed on the main surface insulating film 70 at a distance from the gate electrode 80. The source electrode 85 may also be referred to as a "source main surface electrode." The source electrode 85 includes a source pad electrode 86 and a source line electrode 87.

[0131] The source pad electrode 86 is disposed on the main surface insulating film 70 in a region defined by the gate pad electrode 81 and the gate line electrode 82, and covers the second trench structures 20 and the third trench structures 30. The source pad electrode 86 is formed in a polygonal shape having a recess that is recessed along the gate pad electrode 81 in a plan view.

[0132] The source pad electrode 86 covers the plurality of third trench structures 30 with the main surface insulating film 70 interposed therebetween, and extends into the plurality of source openings 76 from above the main surface insulating film 70. The source pad electrode 86 is electrically connected to the second buried electrode 27 of the corresponding second trench structure 20, the corresponding first mesa portion 24, and the corresponding second mesa portion 31 in the corresponding source opening 76. The source pad electrode 86 is electrically connected to the body region 12 and the contact region 50 in the corresponding first mesa portion 24, and is electrically connected to the source region 40 and the contact region 50 in the corresponding second mesa portion 31.

[0133] The source line electrode 87 is drawn in a strip shape from the source pad electrode 86 to the outer surface 9. Specifically, the source line electrode 87 passes through the region between the pair of open ends 83 of the gate line electrode 82 from the source pad electrode 86 and is drawn onto the outer surface 9. The source line electrode 87 has a portion that faces the sidewall structure 73 in the region between the active surface 8 and the outer surface 9, with the second main surface insulating film 72 sandwiched therebetween.

[0134] The source line electrode 87 extends in a strip shape along the outer contact region 68 in plan view. In this embodiment, the source line electrode 87 is formed in a ring shape (specifically, a quadrangular ring) surrounding the gate pad electrode 81, the gate line electrode 82, and the source pad electrode 86 in plan view. The source line electrode 87 enters the outer opening 77 from above the main surface insulating film 70 and is electrically connected to the outer contact region 68.

[0135] The source electrode 85 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. The source electrode 85 may also include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the source electrode 85 has a layered structure including a Ti film and an Al alloy film (an AlSiCu alloy film in this embodiment) stacked in this order from the chip 2 side. In other words, the source electrode 85 includes the same conductive material as the gate electrode 80.

[0136] The SiC semiconductor device 1A includes a drain electrode 88 covering the second main surface 4. The drain electrode 88 is electrically connected to the second main surface 4. The drain electrode 88 forms an ohmic contact with the second semiconductor region 7 exposed from the second main surface 4. The drain electrode 88 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. A breakdown voltage that can be applied between the source electrode 85 and the drain electrode 88 may be 500 V or more and 3000 V or less.

[0137] As described above, SiC semiconductor device 1A includes chip 2, second trench structure 20 (trench structure), and p-type contact region 50. Chip 2 includes SiC single crystal and has first main surface 3. Second trench structure 20 has first outer wall 22A (first sidewall) and second outer wall 22B (second sidewall), and is formed on first main surface 3.

[0138] The first outer wall 22A extends in the a-axis direction of the SiC single crystal. The second outer wall 22B extends in the m-axis direction of the SiC single crystal. That is, the first outer wall 22A is formed by the m-plane of the SiC single crystal, and the second outer wall 22B is formed by the a-plane of the SiC single crystal. The contact region 50 is formed in a region along the second trench structure 20 within the chip 2, spaced apart from the second outer wall 22B in the a-axis direction.

[0139] When the contact region 50 along the second outer sidewall 22B is formed in the chip 2, the modification of the SiC single crystal accompanying the introduction of the contact region 50 may cause crystal defects along the a-plane of the SiC single crystal (so-called a-plane defects) to occur in the region along the second outer sidewall 22B, originating from the contact region 50. These types of crystal defects degrade the electrical characteristics of the SiC semiconductor device.

[0140] In contrast, in the SiC semiconductor device 1A, the contact region 50 is formed at a distance in the a-axis direction from the second outer sidewall 22B within the chip 2. Therefore, a-plane defects (crystal defects) originating from the contact region 50 can be suppressed in the region along the second outer sidewall 22B within the chip 2.

[0141] This makes it possible to provide a SiC semiconductor device 1A with improved electrical characteristics. For example, by suppressing a-plane defects originating from the contact region 50, it is possible to suppress an increase in resistance value caused by the a-plane defects. For example, suppressing a-plane defects is effective in suppressing an increase in on-resistance Ron caused by the a-plane defects.

[0142] The second trench structure 20 preferably has a bottom wall 23 connecting the first outer sidewall 22A and the second outer sidewall 22B, and the contact region 50 is preferably formed in a region along at least one of the bottom wall 23 and the second outer sidewall 22B within the chip 2. In this case, the contact region 50 along both the bottom wall 23 and the second outer sidewall 22B can increase the formation region of the contact region 50 while suppressing a-plane defects. This reduces the resistance caused by the contact region 50, thereby improving electrical characteristics.

[0143] The contact region 50 is preferably formed in a strip shape extending in the m-axis direction. This structure also makes it possible to increase the formation area of ​​the contact region 50 while suppressing a-plane defects. The contact region 50 preferably has a first width W1 in the m-axis direction and a second width W2 in the a-axis direction that is less than the first width W1.

[0144] This structure allows the distance between the second outer wall 22B and the contact region 50 to be increased. This reduces the influence of misalignment and a-plane defects in the region along the second outer wall 22B within the chip 2. In this case, the second width W2 is preferably less than the width of the first outer wall 22A of the second trench structure 20. Alternatively, the first width W1 may be equal to or greater than the width of the second outer wall 22B of the second trench structure 20.

[0145] The SiC semiconductor device 1A preferably includes a p-type well region 41 formed in a region along the second outer sidewall 22B within the chip 2. In this case, the contact region 50 preferably has a higher p-type impurity concentration than the well region 41. This structure makes it possible to improve the breakdown voltage by utilizing a depletion layer that spreads from the well region 41 while suppressing a-plane defects originating from the contact region 50.

[0146] The well region 41 is preferably formed in a region along the second trench structure 20 within the chip 2. In this case, the contact region 50 is preferably formed in the well region 41. The well region 41 is preferably formed in a region along at least one of the bottom wall 23 and the second outer sidewall 22B within the chip 2. The well region 41 along both the bottom wall 23 and the second outer sidewall 22B can appropriately improve the breakdown voltage.

[0147] The SiC semiconductor device 1A preferably includes a p-type body region 12 formed in a surface layer portion of the first main surface 3. In this case, the second trench structure 20 is preferably formed in the first main surface 3 so as to penetrate the body region 12. Furthermore, the contact region 50 preferably has a higher impurity concentration than the body region 12.

[0148] The second trench structure 20 may be formed in a ring shape in a plan view. The second trench structure 20 preferably has a first bottom wall 23A extending in a strip shape in the a-axis direction and a second bottom wall 23B extending in a strip shape in the m-axis direction. In this case, the contact region 50 is preferably formed in a region along the first bottom wall 23A and spaced apart from the second bottom wall 23B in the a-axis direction. This structure can suppress a-plane defects originating from the contact region 50 in the region along the second bottom wall 23B in the chip 2.

[0149] The SiC semiconductor device 1A may include a first mesa portion 24 defined on the first main surface 3 by the second trench structure 20. In this case, the contact region 50 preferably has a portion of the first mesa portion 24 that is located in a surface layer portion of the first main surface 3. This structure makes it possible to expand the formation area of ​​the contact region 50 by utilizing the first mesa portion 24 while suppressing a-plane defects in the region along the second outer wall 22B.

[0150] The SiC semiconductor device 1A preferably includes a third trench structure 30 formed on the first main surface 3 at a distance from the second trench structure 20. In this case, the SiC semiconductor device 1A preferably includes an n-type source region 40 formed in a region along the third trench structure 30 in a surface layer portion of the first main surface 3.

[0151] The third trench structure 30 may be formed on the first main surface 3 at a distance in the a-axis direction from the second outer wall 22B of the second trench structure 20 so as to extend in the m-axis direction. This structure makes it possible to suppress a-plane defects originating from the contact region 50 in the region between the second trench structure 20 and the third trench structure 30. The third trench structure 30 may be formed on the first main surface 3 at a distance in the m-axis direction from the first outer wall 22A of the second trench structure 20 so as to extend in the a-axis direction. The third trench structure 30 may be formed in a ring shape surrounding the second trench structure 20 in a plan view.

[0152] From another perspective, the SiC semiconductor device 1A may include a chip 2, an n-type first semiconductor region 6, a p-type body region 12, a second trench structure 20 as a trench source structure, a third trench structure 30 as a trench gate structure, an n-type source region 40, and a p-type contact region 50. The chip 2 includes a SiC single crystal and has a first main surface 3. The first semiconductor region 6 is formed in a surface layer portion of the first main surface 3. The body region 12 is formed in a surface layer portion of the first semiconductor region 6.

[0153] The second trench structure 20 has a first outer wall 22A (first side wall) and a second outer wall 22B (second side wall), and is formed on the first main surface 3. The first outer wall 22A extends in the a-axis direction of the SiC single crystal. The second outer wall 22B extends in the m-axis direction of the SiC single crystal. In other words, the first outer wall 22A is formed by the m-plane of the SiC single crystal, and the second outer wall 22B is formed by the a-plane of the SiC single crystal.

[0154] The third trench structure 30 is formed in the first main surface 3 at a distance in the a-axis direction from the second outer wall 22B of the second trench structure 20 so as to penetrate the body region 12. The source region 40 is formed in a region along the third trench structure 30 in a surface layer portion of the body region 12. The contact region 50 is formed within the chip 2 in a region along the second trench structure 20 at a distance in the a-axis direction from the second outer wall 22B of the second trench structure 20.

[0155] This structure can suppress a-plane defects (crystal defects) originating from the contact region 50 in the region between the second trench structure 20 and the third trench structure 30. This makes it possible to provide a SiC semiconductor device 1A that can improve electrical characteristics. For example, by suppressing a-plane defects originating from the contact region 50, it is possible to suppress an increase in resistance value caused by the a-plane defects. For example, suppressing a-plane defects is effective in suppressing an increase in on-resistance Ron caused by the a-plane defects.

[0156] Fig. 17 corresponds to Fig. 8 and is a plan view showing a SiC semiconductor device 1B according to a second embodiment. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 17. The SiC semiconductor device 1B is a device that achieves the same effects as the SiC semiconductor device 1A. The aforementioned SiC semiconductor device 1A includes a contact region 50 formed of first to third contact regions 51 to 53.

[0157] In contrast, contact region 50 in SiC semiconductor device 1B does not include third contact region 53, but includes only first contact region 51 and second contact region 52. Of course, contact region 50 may be composed of only one of first contact region 51 and second contact region 52.

[0158] The first contact region 51 and the second contact region 52 have a first width Wa in the m-axis direction and a second width Wb in the a-axis direction. The first width Wa is less than the width of the second outer sidewall 22B of the second trench structure 20. The first width Wa is less than the width of the second inner sidewall 21B of the second trench structure 20. The first width Wa is greater than the width of the second trench structure 20.

[0159] The second width Wb is less than the width of the first outer sidewall 22A of the second trench structure 20. The second width Wb is less than the width of the first inner sidewall 21A of the second trench structure 20. The second width Wb is less than the first width Wa. The second width Wb is preferably smaller than the width of the second trench structure 20. Of course, the second width Wb may be larger than the width of the second trench structure 20. Furthermore, the second width Wb may be larger than the first width Wa as long as it is less than the width of the first inner sidewall 21A.

[0160] 19 is a plan view showing a SiC semiconductor device 1C according to a third embodiment, corresponding to FIG. 8. The SiC semiconductor device 1C is a device that achieves the same effects as the SiC semiconductor device 1A. The aforementioned SiC semiconductor device 1A includes a contact region 50 that is configured by first to third contact regions 51 to 53, each having a uniform second width W2 in the a-axis direction.

[0161] In contrast, the contact region 50 of the SiC semiconductor device 1C is composed of a first contact region 51 having a second width W2 in the a-axis direction, a second contact region 52 having the second width W2 in the a-axis direction, and a third contact region 53 having a third width W3 in the a-axis direction that is different from the second width W2. Specifically, the third width W3 is greater than the second width W2 and equal to or less than the width of the first inner side wall 21A. It is preferable that the third width W3 be less than the width of the first inner side wall 21A.

[0162] The third contact region 53 may be formed so as to be in contact with the pair of second inner side walls 21B at a distance from the pair of first inner side walls 21A. The third contact region 53 may be formed so as to be in contact with the pair of first inner side walls 21A at a distance from the pair of second inner side walls 21B. The third contact region 53 may be formed over the entire surface layer portion of the body region 12 in the first mesa portion 24. In this case, the third contact region 53 may be in contact with the pair of first inner side walls 21A and the pair of second inner side walls 21B of the second trench structure 20.

[0163] 20 is a plan view showing a SiC semiconductor device 1D according to the fourth embodiment, corresponding to FIG. 8. The SiC semiconductor device 1D is a device that achieves the same effects as the SiC semiconductor device 1A. The aforementioned SiC semiconductor device 1A includes a contact region 50 that is configured by first to third contact regions 51 to 53, each having a uniform second width W2 in the a-axis direction.

[0164] In contrast, the contact region 50 of the SiC semiconductor device 1D is composed of a first contact region 51 having a second width W2 in the a-axis direction, a second contact region 52 also having the second width W2 in the a-axis direction, and a third contact region 53 having a third width W3 in the a-axis direction that is different from the second width W2. Specifically, the third width W3 is less than the second width W2.

[0165] 21 corresponds to FIG. 8 and is a plan view showing a SiC semiconductor device 1E according to a fifth embodiment. The SiC semiconductor device 1E is a device that achieves the same effects as the SiC semiconductor device 1A. The aforementioned SiC semiconductor device 1A includes a contact region 50 having a third contact region 53 connected to a first contact region 51 and a second contact region 52.

[0166] In contrast, the contact region 50 of the SiC semiconductor device 1E has a third contact region 53 formed in the surface layer portion of the body region 12 in the first mesa portion 24, spaced apart from the first contact region 51 and the second contact region 52. The third contact region 53 may be formed wider or narrower than the first contact region 51 (second contact region 52) in the a-axis direction.

[0167] Fig. 22 corresponds to Fig. 8 and is a plan view showing a SiC semiconductor device 1F according to a sixth embodiment. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII shown in Fig. 22. Fig. 24 is a cross-sectional view taken along line XXIV-XXIV shown in Fig. 22. The SiC semiconductor device 1F is a device that achieves the same effects as the SiC semiconductor device 1A. The aforementioned SiC semiconductor device 1A includes a second trench structure 20 formed in an annular shape extending in the a-axis direction and the m-axis direction in plan view.

[0168] In contrast, the SiC semiconductor device 1F includes a second trench structure 20 formed in a quadrangular shape having four sides extending in the a-axis direction and the m-axis direction in plan view. The second trench structure 20 includes a second trench 25, a second insulating film 26, and a second buried electrode 27, similar to the first embodiment.

[0169] In this embodiment, the second trench structure 20 includes sidewalls 90 and a bottom wall 91. The sidewalls 90 are formed in a rectangular shape extending in the a-axis direction and the m-axis direction in a plan view. Specifically, the sidewalls 90 include a pair of first sidewalls 90A and a pair of second sidewalls 90B. The pair of first sidewalls 90A extend in the a-axis direction and face each other in the m-axis direction. That is, the pair of first sidewalls 90A are defined by an m-plane. The pair of second sidewalls 90B extend in the m-axis direction to be connected to the pair of first sidewalls 90A and face each other in the a-axis direction. That is, the pair of second sidewalls 90B are defined by an a-plane.

[0170] Bottom wall 91 is formed in a rectangular shape extending flat along the a-axis and m-axis directions in a plan view, and connects a pair of first side walls 90A and a pair of second side walls 90B. Bottom wall 91 is formed by the c-plane. When active surface 8 (first main surface 3) has an off-angle tilted at a predetermined angle in a predetermined off-direction with respect to the c-plane, bottom wall 91 may have an off-direction and off-angle similar to active surface 8 (first main surface 3).

[0171] As in the first embodiment, the third trench structure 30 is formed in a lattice shape (annular shape) extending in the a-axis direction and the m-axis direction in the regions between the second trench structures 20 so as to surround the second trench structures 20 in a plan view. In this embodiment, the third trench structure 30 defines a plurality of mesa portions 92 extending annularly (specifically, quadrangularly) between itself and the sidewalls 90 of the second trench structures 20.

[0172] As in the first embodiment, the third trench structure 30 includes a plurality of third trench structures 30A and a plurality of third trench structures 30B. In this embodiment, the plurality of third trench structures 30A are formed at intervals in the m-axis direction from the plurality of first sidewalls 90A so as to face the plurality of first sidewalls 90A in the m-axis direction, and extend in a band-like manner in the a-axis direction through the region between the plurality of first sidewalls 90A. In this embodiment, the plurality of third trench structures 30B are formed at intervals in the a-axis direction from the plurality of second sidewalls 90B so as to face the plurality of second sidewalls 90B in the a-axis direction, and extend in a band-like manner in the m-axis direction through the region between the plurality of second sidewalls 90B.

[0173] In this embodiment, the well region 41 includes a well bottom wall 93 and a well side wall 94. The well bottom wall 93 may be referred to as a "first well portion," and the well side wall 94 may be referred to as a "second well portion." The well bottom wall 93 is formed in a region along the bottom wall 91 of the second trench structure 20. Specifically, the well bottom wall 93 covers the entire bottom wall 91. The well bottom wall 93 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6.

[0174] The well sidewall portion 94 is extended from the well bottom wall portion 93 side toward the sidewall 90 of the second trench structure 20 and is formed in a region along the sidewall 90. Specifically, the well sidewall portion 94 is formed in a region along the pair of first sidewalls 90A and the pair of second sidewalls 90B in the mesa portion 92.

[0175] The well sidewall 94 is formed in the mesa portion 92 in a ring shape (specifically, a square ring shape) surrounding the second trench structure 20 at a distance from the third trench structure 30. The well sidewall 94 is connected to the body region 12 in a surface layer portion of the mesa portion 92. The thickness of the well sidewall 94 measured from the sidewall 90 is smaller than the thickness of the well bottom wall 93 measured from the bottom wall 91.

[0176] In this embodiment, the contact region 50 is formed in the well region 41 in a region along the second trench structure 20 at a distance from the pair of second sidewalls 90B of the second trench structure 20 in the a-axis direction, but is not formed in a region along the pair of second sidewalls 90B. The contact region 50 is preferably formed in a region along the center of the bottom wall 91 in a plan view.

[0177] In this embodiment, the contact region 50 includes a bottom wall portion 95, a first side wall portion 96, and a second side wall portion 97. The bottom wall portion 95 may be referred to as the "first contact portion," the first side wall portion 96 may be referred to as the "second contact portion," and the second side wall portion 97 may be referred to as the "third contact portion."

[0178] The bottom wall portion 95 is formed in a region along the inner portion of the bottom wall 91 within the well region 41 (well bottom wall portion 93) and spaced apart in the a-axis direction from the pair of second side walls 90B. The bottom wall portion 95 is formed in a band shape extending in the m-axis direction along the bottom wall 91 in a plan view. It is preferable that the bottom wall portion 95 covers the center portion of the bottom wall 91 in a plan view.

[0179] The first sidewall portion 96 is extended from the bottom wall portion 95 in the well region 41 (well sidewall portion 94) along the m-axis direction toward one first sidewall 90A of the second trench structure 20, and is formed in a region along one first sidewall 90A. The first sidewall portion 96 is formed in a region along the inner portion of the first sidewall 90A, spaced apart from the pair of second sidewalls 90B in the a-axis direction. It is preferable that the first sidewall portion 96 covers the center portion of the second sidewall 90B in a plan view. The first sidewall portion 96 is extended from the well region 41 into the body region 12 in the mesa portion 92.

[0180] The first sidewall 96 has a first exposed portion 98 exposed from the active surface 8 in the mesa portion 92. The first exposed portion 98 extends in a layered manner along the active surface 8 with a gap therebetween from the bottom of the body region 12 toward the active surface 8, and faces the first semiconductor region 6 with a part of the body region 12 sandwiched between them. The first exposed portion 98 is formed with a gap therebetween from the third trench structure 30 toward the second trench structure 20, and is connected to the source region 40. The thickness of the first sidewall 96 measured from the first sidewall 96 is smaller than the thickness of the bottom wall 95 measured from the bottom wall 91.

[0181] The second sidewall portion 97 is extended from the bottom wall portion 95 along the m-axis direction within the well region 41 (well sidewall portion 94) toward the other first sidewall 90A of the second trench structure 20, and is formed in a region along the other first sidewall 90A. The second sidewall portion 97 is formed in a region along the inner portion of the first sidewall 90A, spaced apart from the pair of second sidewalls 90B in the a-axis direction. The second sidewall portion 97 is extended from within the well region 41 into the body region 12 in the mesa portion 92.

[0182] The second sidewall 97 has a second exposed portion 99 exposed from the active surface 8 in the mesa portion 92. The second exposed portion 99 extends in a layered manner along the active surface 8 with a gap therebetween from the bottom of the body region 12 toward the active surface 8, and faces the first semiconductor region 6 with a part of the body region 12 sandwiched between them. The second exposed portion 99 is formed with a gap therebetween from the third trench structure 30 toward the second trench structure 20, and is connected to the source region 40. The thickness of the second sidewall 97 measured from the first sidewall 96 is smaller than the thickness of the bottom wall 95 measured from the bottom wall 91.

[0183] In this embodiment, the contact region 50 is formed in a strip shape extending in the m-axis direction in a plan view. In this embodiment, the contact region 50 has a first width W1 in the m-axis direction and a second width W2 in the a-axis direction that is less than the first width W1. The first width W1 is greater than the width of the second trench structure 20. The first width W1 is greater than the width of the second sidewall 90B of the second trench structure 20. The second width W2 is smaller than the width of the first sidewall 90A of the second trench structure 20.

[0184] As described above, SiC semiconductor device 1F includes chip 2, second trench structure 20 (trench structure), and p-type contact region 50. Chip 2 includes SiC single crystal and has first main surface 3. Second trench structure 20 has first sidewall 90A and second sidewall 90B, and is formed on first main surface 3.

[0185] The first sidewall 90A extends in the a-axis direction of the SiC single crystal. The second sidewall 90B extends in the m-axis direction of the SiC single crystal. That is, the first sidewall 90A is formed by the m-plane of the SiC single crystal, and the second sidewall 90B is formed by the a-plane of the SiC single crystal. The contact region 50 is formed in a region along the second trench structure 20 within the chip 2, spaced apart from the second sidewall 90B in the a-axis direction.

[0186] This structure can suppress a-plane defects (crystal defects) originating from the contact region 50 in the region along the second sidewall 90B in the chip 2. This makes it possible to provide a SiC semiconductor device 1F that can improve electrical characteristics. For example, by suppressing a-plane defects originating from the contact region 50, it is possible to suppress an increase in resistance value caused by the a-plane defects. For example, suppressing a-plane defects is effective in suppressing an increase in on-resistance Ron caused by the a-plane defects.

[0187] From another perspective, the SiC semiconductor device 1F may include a chip 2, an n-type first semiconductor region 6, a p-type body region 12, a second trench structure 20 as a trench source structure, a third trench structure 30 as a trench gate structure, an n-type source region 40, and a p-type contact region 50. The chip 2 includes a SiC single crystal and has a first main surface 3. The first semiconductor region 6 is formed in a surface layer portion of the first main surface 3. The body region 12 is formed in a surface layer portion of the first semiconductor region 6.

[0188] The second trench structure 20 has a first sidewall 90A and a second sidewall 90B, and is formed on the first main surface 3. The first sidewall 90A extends in the a-axis direction of the SiC single crystal. The second sidewall 90B extends in the m-axis direction of the SiC single crystal. In other words, the first sidewall 90A is formed by the m-plane of the SiC single crystal, and the second sidewall 90B is formed by the a-plane of the SiC single crystal.

[0189] The third trench structure 30 is formed in the first main surface 3 at a distance in the a-axis direction from the second sidewall 90B of the second trench structure 20 so as to penetrate the body region 12. The source region 40 is formed in a region along the third trench structure 30 in a surface layer portion of the body region 12. The contact region 50 is formed within the chip 2 in a region along the second trench structure 20 at a distance in the a-axis direction from the second sidewall 90B of the second trench structure 20.

[0190] This structure can suppress a-plane defects (crystal defects) originating from the contact region 50 in the region between the second trench structure 20 and the third trench structure 30. This makes it possible to provide a SiC semiconductor device 1F that can improve electrical characteristics. For example, by suppressing a-plane defects originating from the contact region 50, it is possible to suppress an increase in resistance value caused by the a-plane defects. For example, suppressing a-plane defects is effective in suppressing an increase in on-resistance Ron caused by the a-plane defects.

[0191] 25 is a plan view showing a SiC semiconductor device 1G according to the seventh embodiment, corresponding to FIG. 22. The SiC semiconductor device 1G is a device that exhibits the same effects as the SiC semiconductor device 1F. The contact region 50 of the SiC semiconductor device 1F includes a bottom wall portion 95 that extends in a band shape in the m-axis direction along the bottom wall 91 in a plan view.

[0192] On the other hand, the SiC semiconductor device 1G has a structure in which a portion of the bottom wall portion 95 of the SiC semiconductor device 1F that is located along the center of the bottom wall 91 has been removed. That is, the bottom wall portion 95 of the SiC semiconductor device 1G has an opening in the center of the bottom wall 91 that leaves the well region 41. In the SiC semiconductor device 1G, the opening reduces the area in which the bottom wall portion 95 is formed. Of course, a contact region 50 that does not have a bottom wall portion 95 may also be employed.

[0193] Fig. 26 corresponds to Fig. 22 and is a plan view showing a SiC semiconductor device 1H according to the eighth embodiment. SiC semiconductor device 1H has a modified form of contact region 50 in SiC semiconductor device 1G, and is a device that achieves the same effects as SiC semiconductor device 1H.

[0194] Specifically, the bottom wall portion 95 of the SiC semiconductor device 1H has a plurality of openings. In this embodiment, the plurality of openings are formed at intervals in the m-axis direction. Of course, the plurality of openings may also be formed at intervals in the a-axis direction. Furthermore, three or more openings may also be formed at intervals in the m-axis direction and the a-axis direction.

[0195] 22 and is a plan view showing a SiC semiconductor device 1I according to the ninth embodiment. The SiC semiconductor device 1I is a device that exhibits the same effects as the SiC semiconductor device 1F. The aforementioned SiC semiconductor device 1F includes a contact region 50 having a uniform second width W2 in the a-axis direction.

[0196] In contrast, in the contact region 50 of the SiC semiconductor device 1I, the bottom wall 95 has a wide portion that protrudes toward one or both (in this embodiment, both) of the pair of second side walls 90B in a plan view. The wide portion covers the bottom wall 91 at a distance from the pair of second side walls 90B in the a-axis direction. The wide portion also covers the bottom wall 91 at a distance from the pair of first side walls 90A in the m-axis direction. In other words, the width of the wide portion exceeds the second width W2 but is less than the width of the first side wall 90A. The width of the wide portion may be half or more of the width of the first side wall 90A.

[0197] In a plan view, the bottom wall portion 95 preferably covers 50% or more and less than 100% of the area of ​​the bottom wall 91. The above ratio (the ratio of the planar area of ​​the bottom wall portion 95 to the planar area of ​​the bottom wall 91) may be set to a value belonging to any one of the ranges of 50% or more and 60% or less, 60% or more and 70% or less, 70% or more and 80% or less, 80% or more and 90% or less, and 90% or more and less than 100%.

[0198] 22 and is a plan view showing a SiC semiconductor device 1J according to the tenth embodiment. The SiC semiconductor device 1J is a device that exhibits the same effects as the SiC semiconductor device 1F. The aforementioned SiC semiconductor device 1F includes a contact region 50 having a uniform second width W2 in the a-axis direction.

[0199] In contrast, in the contact region 50 of the SiC semiconductor device 1J, the bottom wall portion 95 has a narrow portion recessed toward one or both (in this embodiment, both) of the pair of second side walls 90B in a plan view. The width of the narrow portion is less than the second width W2. The width of the narrow portion may be ½ or less of the second width W2. The width of the narrow portion may be 1 / 10 or more of the second width W2.

[0200] Fig. 29 is a cross-sectional view showing a modified example of the second trench structure 20. Fig. 29 shows an example in which the modified second trench structure 20 is applied to the SiC semiconductor device 1A according to the first embodiment, but the modified second trench structure 20 may also be applied to the SiC semiconductor devices 1B to 1F according to the second to sixth embodiments.

[0201] The second trench structure 20 according to each of the above-described embodiments includes a second trench 25, a second insulating film 26, and a second buried electrode 27. In contrast, the second trench structure 20 according to the modified example does not include the second insulating film 26. The second buried electrode 27 is buried directly in the second trench 25, and is electrically and mechanically connected to the chip 2 within the second trench 25.

[0202] The aforementioned source region 40, well region 41 and contact region 50 are electrically and mechanically connected to the second buried electrode 27 in the portions along the wall surfaces (inner sidewall 21, outer sidewall 22 and bottom wall 23) of the second trench structure 20.

[0203] The second buried electrode 27 may be formed by utilizing a part of the source electrode 85 (source pad electrode 86). In other words, the source electrode 85 (source pad electrode 86) may be formed so as to extend from above the main surface insulating film 70 (active surface 8) into the plurality of second trenches 25. In this case, the source electrode 85 (source pad electrode 86) includes the plurality of second buried electrodes 27 electrically and mechanically connected to the chip 2 in the plurality of second trenches 25.

[0204] The above-described embodiments can be implemented in other forms. In the above-described embodiments, an example was shown in which the second semiconductor region 7 was formed in the chip 2. However, a structure without the second semiconductor region 7 may be employed. In this case, the first semiconductor region 6 is exposed from the first main surface 3, the second main surface 4, and the first to fourth side surfaces 5A to 5D of the chip 2. In other words, the chip 2 may have a single-layer structure made of a SiC epitaxial layer without including a SiC substrate.

[0205] In each of the above-described embodiments, an "n-type" region may be replaced with a "p-type" region, and a "p-type" region may be replaced with an "n-type" region. A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings. When "p-type" is referred to as the "first conductivity type," "n-type" may be referred to as the "second conductivity type." When "n-type" is referred to as the "first conductivity type," "p-type" may be referred to as the "second conductivity type."

[0206] In the above-described embodiments, the second semiconductor region 7 is of "n-type." However, a second semiconductor region 7 of "p-type" may be employed. In this case, a SiC-IGBT (Insulated Gate Bipolar Transistor) is formed instead of the SiC-MISFET. In this case, in the above description, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT. The second semiconductor region 7 of "p-type" may be made of a "p-type" SiC substrate, or may be formed by introducing p-type impurities into the surface layer of the second main surface 4 of the chip 2 (epitaxial layer) by ion implantation.

[0207] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each item to the embodiments. The "SiC semiconductor device" in the following items may be replaced with "semiconductor device," "SiC semiconductor switching device," or "SiC-MISFET" as necessary.

[0208] [A1] A SiC semiconductor device (1A-1J) including: a chip (2) including a SiC single crystal and having a main surface (3); a trench structure (20) having a first sidewall (22A, 90A) extending in the a-axis direction of the SiC single crystal and a second sidewall (22B, 90B) extending in the m-axis direction of the SiC single crystal, and formed in the main surface (3); and a first conductivity type (p-type) contact region (50) formed in the chip (2) in a region along the trench structure (20) and spaced from the second sidewall (22B, 90B) in the a-axis direction.

[0209] [A2] The SiC semiconductor device (1A-1J) described in A1, wherein the trench structure has a bottom wall (23, 91) connecting the first side wall (22A, 90A) and the second side wall (22B, 90B), and the contact region (50) is formed in the chip (2) in a region along the bottom wall (23, 91) of the trench structure (20).

[0210] [A3] A SiC semiconductor device (1A-1J) according to A1 or A2, wherein the contact region (50) is formed in a region along the first sidewall (22A, 90A) of the trench structure (20) within the chip (2).

[0211] [A4] The SiC semiconductor device (1A to 1J) according to any one of A1 to A3, wherein the contact region (50) is formed in a strip shape extending in the m-axis direction.

[0212] [A5] The contact region (50) has a first width (W1, Wa) in the m-axis direction and a second width (W2, Wb) in the a-axis direction that is less than the first width (W1, Wa). A SiC semiconductor device (1A-1J) described in any one of A1 to A4.

[0213] [A6] The SiC semiconductor device (1A to 1J) according to A5, wherein the second width (W2, Wb) is less than the width of the first sidewall (22A, 90A).

[0214] [A7] The SiC semiconductor device (1A-1J) according to A5 or A6, wherein the first width (W1, Wa) is equal to or greater than the width of the second sidewall (22B, 90B).

[0215] [A8] The SiC semiconductor device (1A-1J) according to any one of A1 to A7, further including a well region (41) of a first conductivity type (p-type) formed in a region along the second sidewall (22B, 90B) within the chip (2), wherein the contact region (50) has a higher impurity concentration than the well region (41).

[0216] [A9] The SiC semiconductor device (1A-1J) described in A8, wherein the well region (41) is formed in a region along the trench structure (20) within the chip (2), and the contact region (50) is formed within the well region (41).

[0217] [A10] The SiC semiconductor device (1A-1J) according to any one of A1 to A9, further comprising a body region (12) of a first conductivity type (p-type) formed in a surface layer portion of the main surface (3), the trench structure (20) being formed in the main surface (3) so as to penetrate the body region (12), and the contact region (50) having a higher impurity concentration than the body region (12).

[0218] [A11] The SiC semiconductor device (1A to 1J) according to any one of A1 to A10, wherein the trench structure (20) is formed in a ring shape in a planar view.

[0219] [A12] The SiC semiconductor device (1A to 1J) according to A11, further comprising a mesa portion (24) defined on the main surface (3) by the trench structure (20), wherein the contact region (50) has a portion of the mesa portion (24) located on a surface portion of the main surface (3).

[0220] [A13] The SiC semiconductor device (1A to 1J) according to any one of A1 to A12, wherein the trench structure (20) is formed in a quadrangular shape in plan view.

[0221] [A14] The SiC semiconductor device (1A to 1J) according to any one of A1 to A13, wherein a source potential is applied to the trench structure (20).

[0222] [A15] The SiC semiconductor device (1A-1J) according to any one of A1 to A14, further comprising a second trench structure (30) formed on the main surface (3) at a distance from the trench structure (20) and to which a gate potential is applied.

[0223] [A16] The SiC semiconductor device (1A-1J) described in A15, wherein the second trench structure (30) is formed on the main surface (3) at a distance from the second sidewall (22B, 90B) of the trench structure (20) in the a-axis direction and extends in the m-axis direction.

[0224] [A17] The SiC semiconductor device (1A-1J) according to A15 or A16, wherein the second trench structure (30) is formed on the main surface (3) at a distance from the first sidewall (22A, 90A) of the trench structure (20) in the m-axis direction and extends in the a-axis direction.

[0225] [A18] A SiC semiconductor device (1A to 1J) according to any one of A15 to A17, wherein the second trench structure (30) is formed in a ring shape surrounding the trench structure (20) in a planar view.

[0226] [A19] The SiC semiconductor device (1A-1J) according to any one of A15 to A18, further comprising a second conductivity type (n-type) source region (40) formed in a region along the second trench structure (30) in a surface layer portion of the main surface (3).

[0227] [A20] A chip (2) including a SiC single crystal and having a main surface (3), a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3), a body region (12) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (6), a trench source structure (20) having a first sidewall (22A, 90A) extending in an a-axis direction of the SiC single crystal and a second sidewall (22B, 90B) extending in an m-axis direction of the SiC single crystal, and formed in the main surface (3) so as to penetrate the body region (12), and a trench gate structure (30) formed on the main surface (3) at a distance from the second sidewall (22B, 90B) of the body region (20) in the a-axis direction; a first conductivity type (n-type) source region (40) formed in a region along the trench gate structure (30) in a surface layer portion of the body region (12); and a second conductivity type (p-type) contact region (50) formed in the chip (2) in a region along the trench source structure (20) at a distance from the second sidewall (22B, 90B) of the trench source structure (20) in the a-axis direction.

[0228] Although the embodiments have been described in detail above, these are merely specific examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiments.

[0229] DESCRIPTION OF SYMBOLS 1A SiC semiconductor device 1B SiC semiconductor device 1C SiC semiconductor device 1D SiC semiconductor device 1E SiC semiconductor device 1F SiC semiconductor device 1G SiC semiconductor device 1H SiC semiconductor device 1I SiC semiconductor device 1J SiC semiconductor device 2 Chip 3 First main surface 6 First semiconductor region 12 Body region 20 Second trench structure (trench source structure) 22A First side wall 22B Second side wall 23 Bottom wall 24 First mesa portion 30 Third trench structure (trench gate structure) 40 Source region 41 Well region 50 Contact region 90A First side wall 90B Second side wall 91 Bottom wall W1 First width W2 Second width Wa First width Wb Second width

Claims

1. A chip including a SiC single crystal and having a main surface; a trench structure formed on the main surface, the trench structure having a first sidewall extending in an a-axis direction of the SiC single crystal and a second sidewall extending in an m-axis direction of the SiC single crystal; a first conductivity type contact region formed in the chip in a region along the trench structure and spaced from the second sidewall in the a-axis direction.

2. The SiC semiconductor device as described in claim 1, wherein a source potential is applied to the trench structure.

3. The SiC semiconductor device as described in claim 1, wherein the contact region has a first width in the m-axis direction and a second width in the a-axis direction that is less than the first width.

4. A SiC semiconductor device as described in claim 3, wherein the second width is less than the width of the first side wall.

5. A SiC semiconductor device as described in claim 3, wherein the first width is greater than or equal to the width of the second side wall.

6. The semiconductor device further includes a well region of a first conductivity type formed in a region along the second sidewall within the chip, The SiC semiconductor device according to claim 1 , wherein the contact region has a higher impurity concentration than the well region.

7. The well region is formed in a region along the trench structure within the chip, The SiC semiconductor device according to claim 6 , wherein the contact region is formed in the well region.

8. A SiC semiconductor device described in any one of claims 1 to 7, further comprising a second trench structure formed on the main surface spaced apart from the trench structure and to which a gate potential is applied.

9. A SiC semiconductor device as described in claim 8, wherein the second trench structure is formed on the main surface at a distance from the second side wall of the trench structure in the a-axis direction and extends in the m-axis direction.

10. A SiC semiconductor device as described in claim 8, wherein the second trench structure is formed on the main surface at a distance from the first sidewall of the trench structure in the m-axis direction and extends in the a-axis direction.

11. A SiC semiconductor device as described in Claim 8, wherein the second trench structure is formed in a ring shape surrounding the trench structure in a planar view.

12. A SiC semiconductor device as described in claim 8, further comprising a source region of a second conductivity type formed in a surface portion of the main surface in a region along the second trench structure.

13. A SiC semiconductor device described in any one of claims 1 to 7, wherein the trench structure is formed in a ring shape when viewed in a planar view.

14. Further comprising a mesa portion defined on the main surface by the trench structure, The SiC semiconductor device according to claim 13 , wherein the contact region has a portion located in a surface layer portion of the main surface in the mesa portion.

15. A SiC semiconductor device described in any one of claims 1 to 7, wherein the trench structure is formed in a rectangular shape when viewed in a planar view.

16. the trench structure has a bottom wall connecting the first sidewall and the second sidewall; 8. The SiC semiconductor device according to claim 1, wherein the contact region is formed in the chip in a region along the bottom wall of the trench structure.

17. 8. The SiC semiconductor device according to claim 1, wherein the contact region is formed in the chip in a region along the first sidewall of the trench structure.

18. The SiC semiconductor device according to claim 1, wherein the contact region is formed in a band shape extending in the m-axis direction.

19. a body region of a first conductivity type formed in a surface layer portion of the main surface, the trench structure is formed in the main surface so as to penetrate the body region; 8. The SiC semiconductor device according to claim 1, wherein the contact region has a higher impurity concentration than the body region.

20. A chip including a SiC single crystal and having a main surface; a first conductivity type semiconductor region formed in a surface layer portion of the main surface; a body region of a second conductivity type formed in a surface layer portion of the semiconductor region; a trench source structure formed in the main surface so as to penetrate the body region, the trench source structure having a first sidewall extending in an a-axis direction of the SiC single crystal and a second sidewall extending in an m-axis direction of the SiC single crystal; a trench gate structure formed on the main surface at a distance from the second sidewall of the trench source structure in the a-axis direction so as to penetrate the body region; a first conductivity type source region formed in a surface portion of the body region along the trench gate structure; a contact region of a second conductivity type formed in the chip in a region along the trench source structure and spaced apart from the second sidewall of the trench source structure in the a-axis direction.