Semiconductor device

Abstract

This semiconductor device includes: a chip having a first main surface on one side and a second main surface on another side; an IGBT region provided to an inner portion of the first main surface; an outer peripheral region provided to a peripheral edge portion of the first main surface; a well region of a first conductivity-type formed in a surface layer portion of the first main surface in the outer peripheral region so as to demarcate the IGBT region; an insulating film covering the well region; a well connection electrode embedded in the insulating film so as to connect to the well region; and a cathode region of a second conductivity-type which is formed in a surface layer portion of the second main surface in the outer peripheral region so as to oppose the well connection electrode, and that constitutes a diode together with the well region.

Description

Semiconductor Devices

[0001] This application claims priority to Japanese Patent Application No. 2022-061086 filed on March 31, 2022, and Japanese Patent Application No. 2022-061087 filed on March 31, 2022, the entire contents of which are incorporated herein by reference. The present invention relates to a semiconductor device.

[0002] Patent Document 1 discloses a semiconductor device including a reverse conducting-insulating gate bipolar transistor (RC-IGBT).

[0003] US Patent Application Publication No. 2010 / 0090248

[0004] One embodiment provides a semiconductor device capable of improving electrical characteristics.

[0005] One embodiment provides a semiconductor device including: a chip having a first main surface on one side and a second main surface on the other side; an IGBT region provided in an inner portion of the first main surface; a peripheral region provided on the periphery of the first main surface; a well region of a first conductivity type formed in a surface layer portion of the first main surface in the peripheral region so as to partition the IGBT region; an insulating film covering the well region; a well connection electrode embedded in the insulating film so as to be connected to the well region; and a cathode region of a second conductivity type formed in a surface layer portion of the second main surface in the peripheral region so as to face the well connection electrode and which forms a diode with the well region.

[0006] One embodiment provides a semiconductor device including: a chip having a first main surface on one side and a second main surface on the other side; an IGBT region provided in an inner portion of the first main surface; a peripheral region provided on a periphery of the first main surface; a first conductivity type well region formed in a surface layer portion of the first main surface in the peripheral region so as to partition the IGBT region; an insulating film covering the well region; a well connection electrode embedded in the insulating film so as to be connected to the well region; a gate electrode arranged on the insulating film at a distance from the well connection electrode so as to face the well region; and a second conductivity type cathode region formed along the second main surface at a distance from a gate reference position immediately below the center of the gate electrode to the well connection electrode side so as to face the well region in the surface layer portion of the second main surface, the cathode region constituting a diode together with the well region.

[0007] One embodiment provides a semiconductor device including: a chip having a first main surface on one side and a second main surface on the other side; an IGBT region provided in an inner portion of the first main surface; an outer periphery region provided on a peripheral portion of the first main surface; a first conductivity type well region formed in a surface layer portion of the first main surface in the outer periphery region so as to partition the IGBT region; an insulating film covering the well region; a first well connection electrode embedded in the insulating film so as to be connected to the well region; a second well connection electrode embedded in the insulating film at a distance from the first well connection electrode on the peripheral side of the chip so as to be connected to the well region; and a second conductivity type cathode region formed at a distance along the second main surface from an intermediate reference position immediately below the middle between the first well connection electrode and the second well connection electrode so as to face the well region in the surface layer portion of the second main surface, and constituting a diode with the well region.

[0008] One embodiment provides a semiconductor device including: a chip having a first main surface on one side and a second main surface on the other side; an IGBT region provided in an inner portion of the first main surface; a peripheral region provided on a periphery of the first main surface; a first conductivity type well region formed in a surface layer portion of the first main surface in the peripheral region so as to partition the IGBT region; an insulating film covering the well region; a well connection electrode embedded in the insulating film so as to be connected to the well region; an emitter pad electrode arranged on the insulating film so as to be electrically connected to the well region via the well connection electrode; and a second conductivity type cathode region formed in a surface layer portion of the second main surface in the peripheral region so as to face the well connection electrode and to form a diode with the well region.

[0009] One embodiment provides a semiconductor device including: a chip having a first main surface on one side and a second main surface on the other side; an IGBT region provided in an inner portion of the first main surface; a peripheral region provided on a peripheral edge of the first main surface; a first conductivity type well region formed in a surface layer portion of the first main surface in the peripheral region so as to partition the IGBT region; an insulating film covering the well region; a well connection electrode embedded in the insulating film so as to be connected to the well region; an emitter electrode arranged on the insulating film so as to be electrically connected to the well region via the well connection electrode; and a second conductivity type cathode region formed in the surface layer portion of the second main surface in the peripheral region so as to face the well connection electrode and which forms a diode with the well region.

[0010] one embodiment provides a semiconductor device including: a chip having a first main surface on one side and a second main surface on the other side; an IGBT region provided in an inner portion of the first main surface; an outer periphery region provided on a peripheral portion of the first main surface; a first conductivity type well region formed in a surface layer portion of the first main surface in the outer periphery region so as to partition the IGBT region; an insulating film covering the well region; a first well connection electrode embedded in the insulating film so as to be connected to the well region; a second well connection electrode embedded in the insulating film at a distance from the first well connection electrode toward the peripheral edge of the chip so as to be connected to the well region; a gate electrode arranged on the insulating film in a region between the first well connection electrode and the second well connection electrode so as to face the well region; and a second conductivity type cathode region arranged along the second main surface at a distance from a gate reference position immediately below a center of the gate electrode so as to face the well region in the surface layer portion of the second main surface, the cathode region constituting a diode with the well region.

[0011] one embodiment provides a semiconductor device including: a chip having a first main surface on one side and a second main surface on the other side; an IGBT region provided in an inner portion of the first main surface; an outer periphery region provided on a peripheral portion of the first main surface; a first conductivity type well region formed in a surface layer portion of the first main surface in the outer periphery region so as to partition the IGBT region; an insulating film covering the well region; a gate wiring arranged inside the insulating film so as to face the well region; a first well connection electrode embedded in the insulating film at a distance from the gate wiring toward the IGBT region so as to be connected to the well region; a second well connection electrode embedded in the insulating film at a distance from the gate wiring toward the peripheral edge of the chip so as to be connected to the well region; and a second conductivity type cathode region arranged along the second main surface at a distance from a gate reference position immediately below the center of the gate wiring so as to face the well region in the surface layer portion of the second main surface, the cathode region constituting a diode together with the well region.

[0012] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIG. 2 is a plan view showing an example layout in a first main surface. FIG. 3 is a plan view showing an example layout of well regions, gate wiring, and cathode regions. FIG. 4 is a plan view showing a main portion of a chip. FIG. 5 is a cross-sectional view showing a cross-sectional structure along line VV shown in FIG. 4, together with a cathode region according to a first layout example. FIG. 6 is a cross-sectional view showing a cross-sectional structure along line VI-VI shown in FIG. 4, together with a cathode region according to the first layout example. FIG. 7 is a cross-sectional view showing a cross-sectional structure along line VII-VII shown in FIG. 4, together with a cathode region according to the first layout example. FIG. 8 is a cross-sectional view showing a cross-sectional structure of a peripheral portion of a chip, together with a cathode region according to the first layout example. FIG. 9 is a cross-sectional view for explaining the location of the cathode region. FIG. 10 is a cross-sectional view showing the current density of a forward current when the cathode region is positioned at the gate reference position. FIG. 11 is a cross-sectional view showing the current density of a forward current when the cathode region is positioned at the first well reference position. FIG. 12 is a cross-sectional view showing the current density of the forward current when the cathode region is positioned at the second well reference position. FIG. 13 is a graph showing the relationship between the forward current and forward voltage for the cases of FIGS. 10 to 12. FIG. 14A is a graph showing the relationship between the location of the cathode region and the forward current IF. FIG. 14B is a graph illustrating a first setting example of the prohibited range, first allowed range, and second allowed range based on the results of FIG. 14A. FIG. 14C is a graph illustrating a second setting example of the prohibited range, first allowed range, and second allowed range based on the results of FIG. 14A. FIG. 15 is a graph showing the relationship between the peak surge current and forward voltage when the location of the cathode region is adjusted. FIG. 16 is a cross-sectional view showing the cross-sectional structure of the peripheral portion of the chip together with the cathode region according to the second layout example. FIG. 17 is a cross-sectional view showing the cross-sectional structure of the peripheral portion of the chip together with the cathode region according to the third layout example. 18 is a cross-sectional view showing the cross-sectional structure of the peripheral portion of the chip together with the cathode region according to the fourth layout example, FIG. 19 is a cross-sectional view showing the cross-sectional structure of the peripheral portion of the chip together with the cathode region according to the fifth layout example, and FIG. 20 is a cross-sectional view showing the cross-sectional structure of the peripheral portion of the chip together with the cathode region according to the sixth layout example.

[0013] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0014] When the phrase "substantially equal" is used in a description in which a comparison target is present, this phrase includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not attached with the intent of limiting the names of each structure.

[0015] Fig. 1 is a plan view showing a semiconductor device 1 according to one embodiment. Fig. 2 is a plan view showing an example of a layout in a first main surface 3. Fig. 3 is a plan view showing an example of a layout of a well region 31, a gate pad wiring 44, a gate line wiring 45, and a cathode region 80. Fig. 4 is a plan view showing a main part of a chip 2.

[0016] Fig. 5 is a cross-sectional view showing the cross-sectional structure along line VV shown in Fig. 4 together with the cathode region 80A according to the first layout example. Fig. 6 is a cross-sectional view showing the cross-sectional structure along line VI-VI shown in Fig. 4 together with the cathode region 80A according to the first layout example. Fig. 7 is a cross-sectional view showing the cross-sectional structure along line VII-VII shown in Fig. 4 together with the cathode region 80A according to the first layout example. Fig. 8 is a cross-sectional view showing the cross-sectional structure of the peripheral portion of the chip 2 together with the cathode region 80A according to the first layout example.

[0017] 1 to 8, a semiconductor device 1 is an RC-IGBT (Insulated Gate Bipolar Transistor) semiconductor device (semiconductor switching device) having an RC-IGBT (Reverse Conducting - IGBT) that is integrally provided with an IGBT and a diode. The diode is a free wheel diode for the IGBT.

[0018] The semiconductor device 1 includes a hexahedral (specifically, rectangular parallelepiped) chip 2. The chip 2 may also be referred to as a "semiconductor chip." In this embodiment, the chip 2 has a single-layer structure made of a silicon single crystal substrate (semiconductor substrate). The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.

[0019] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2. The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0020] The semiconductor device 1 includes an IGBT region 6 provided in an inner portion of the first main surface 3. The IGBT region 6 is a region having an IGBT structure and may also be referred to as an "active region." In this embodiment, the IGBT region 6 is formed in a polygonal shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view. Specifically, the IGBT region 6 has a recess recessed from the center of the side along the third side surface 5C toward the fourth side surface 5D in a plan view. The recess is recessed in a polygonal shape (a quadrangular shape in this embodiment) in a plan view.

[0021] The semiconductor device 1 includes a pad region 7 provided in a region defined by a recess in the IGBT region 6 on the first main surface 3. The pad region 7 is set to have a polygonal shape (a square shape in this embodiment) in a plan view. The semiconductor device 1 also includes a peripheral region 8 provided on the periphery of the chip 2. The peripheral region 8 is provided in a ring shape (a square ring shape) extending along the first to fourth side surfaces 5A to 5D so as to surround the IGBT region 6. The peripheral region 8 is connected to the pad region 7 at a portion extending along the third side surface 5C.

[0022] The semiconductor device 1 includes an n-type (first conductivity type) drift region 9 formed inside the chip 2. The drift region 9 is formed throughout the interior of the chip 2. In this embodiment, the chip 2 is made of an n-type semiconductor substrate (an n-type semiconductor chip), and the drift region 9 is formed using the chip 2.

[0023] The semiconductor device 1 includes an n-type buffer region 10 formed in a surface layer portion of the second main surface 4. In this embodiment, the buffer region 10 is formed in a layer shape extending along the entire area of ​​the second main surface 4. The buffer region 10 is exposed from the first to fourth side surfaces 5A to 5D. The buffer region 10 has a higher n-type impurity concentration than the drift region 9. The presence or absence of the buffer region 10 is optional, and a configuration without the buffer region 10 may also be employed.

[0024] The semiconductor device 1 includes a p-type (second conductivity type) collector region 11 formed in a surface layer portion of the second main surface 4. The collector region 11 is formed in a surface layer portion of the buffer region 10 on the second main surface 4 side. In this embodiment, the collector region 11 is formed in a layer shape extending along the second main surface 4 over the entire area of ​​the second main surface 4. The collector region 11 is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0025] The semiconductor device 1 includes a trench isolation structure 12 formed in the first main surface 3 so as to define the IGBT region 6. A gate potential is applied to the trench isolation structure 12. The trench isolation structure 12 surrounds the IGBT region 6 and separates the IGBT region 6 from the peripheral region 8 and the pad region 7. In this embodiment, the trench isolation structure 12 is formed in a polygonal ring shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0026] The trench isolation structure 12 may have a width of 0.5 μm or more and 5 μm or less. The width of the trench isolation structure 12 is the width in a direction perpendicular to the direction in which the trench isolation structure 12 extends. The width of the trench isolation structure 12 is preferably 1 μm or more and 2.5 μm or less. The trench isolation structure 12 may have a depth of 1 μm or more and 20 μm or less. The depth of the trench isolation structure 12 is preferably 4 μm or more and 10 μm or less.

[0027] The trench isolation structure 12 includes an isolation trench 13, an isolation insulating film 14, and an isolation buried electrode 15. The isolation trench 13 is dug down from the first main surface 3 toward the second main surface 4, and defines the wall surface of the trench isolation structure 12. The isolation insulating film 14 is formed in a film shape along the wall surface of the isolation trench 13, and defines a recess space within the isolation trench 13.

[0028] The isolation insulating film 14 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The isolation insulating film 14 preferably has a single-layer structure made of a single insulating film. It is particularly preferable that the isolation insulating film 14 includes a silicon oxide film made of an oxide of the chip 2.

[0029] The isolated buried electrode 15 is buried in the isolation trench 13 with the isolation insulating film 14 sandwiched therebetween. In this embodiment, the isolated buried electrode 15 is made of conductive polysilicon. A gate potential is applied to the isolated buried electrode 15.

[0030] The semiconductor device 1 includes an IGBT structure 16 formed in the IGBT region 6. The IGBT structure 16 may also be referred to as a "FET (Field Effect Transistor) structure." The IGBT structure 16 includes a p-type base region 17 formed in the IGBT region 6 in a surface layer portion of the first main surface 3. The base region 17 may also be referred to as a "body region" or a "channel region." The base region 17 is formed shallower than the trench isolation structure 12 and has a bottom located closer to the first main surface 3 than the bottom wall of the trench isolation structure 12. The base region 17 extends in a layered manner along the first main surface 3 and contacts the inner circumferential wall of the trench isolation structure 12.

[0031] The IGBT structure 16 includes a plurality of trench gate structures 18 formed on the first main surface 3 in the IGBT region 6. A gate potential is applied to the plurality of trench gate structures 18. The plurality of trench gate structures 18 penetrate the base region 17 to reach the drift region 9. The plurality of trench gate structures 18 are arranged at intervals in the first direction X in a plan view, and are each formed in a band shape extending in the second direction Y. In other words, the plurality of trench gate structures 18 are arranged in a stripe shape extending in the second direction Y.

[0032] Each of the trench gate structures 18 has a first end 18A on one side (the first side surface 5A side) and a second end 18B on the other side (the second side surface 5B side) in the longitudinal direction (second direction Y). The first end 18A and the second end 18B are mechanically and electrically connected to the trench isolation structure 12.

[0033] That is, the plurality of trench gate structures 18, together with the trench isolation structure 12, constitute one ladder-shaped trench gate structure 18. The connection portion between the trench isolation structure 12 and the trench gate structure 18 may be considered as part of the trench isolation structure 12 or may be considered as part of the trench gate structure 18.

[0034] The plurality of trench gate structures 18 may be arranged at intervals of 0.5 μm to 5 μm in the first direction X. The intervals between the plurality of trench gate structures 18 are preferably 1 μm to 3 μm. Each trench gate structure 18 may have a width of 0.5 μm to 5 μm. The width of each trench gate structure 18 is the width in a direction perpendicular to the direction in which each trench gate structure 18 extends.

[0035] The width of each trench gate structure 18 is preferably 1 μm or more and 2.5 μm or less. The width of each trench gate structure 18 is preferably approximately equal to the width of the trench isolation structure 12. Each trench gate structure 18 may have a depth of 1 μm or more and 20 μm or less. The depth of each trench gate structure 18 is preferably 4 μm or more and 10 μm or less. The depth of each trench gate structure 18 is preferably approximately equal to the depth of the trench isolation structure 12.

[0036] The configuration of one trench gate structure 18 will be described below. The trench gate structure 18 includes a gate trench 19, a gate insulating film 20, and a buried gate electrode 21. The gate trench 19 is dug down from the first main surface 3 toward the second main surface 4, and defines the wall surfaces of the trench gate structure 18. In this embodiment, the gate trench 19 communicates with the isolation trench 13 at both longitudinal ends (first end 18A and second end 18B). Specifically, the sidewalls of the gate trench 19 communicate with the sidewalls of the isolation trench 13, and the bottom wall of the gate trench 19 communicates with the bottom wall of the isolation trench 13.

[0037] The gate insulating film 20 is formed in a film shape along the wall surface of the gate trench 19, and defines a recess space within the gate trench 19. The gate insulating film 20 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film.

[0038] The gate insulating film 20 preferably has a single-layer structure made of a single insulating film. It is particularly preferable that the gate insulating film 20 includes a silicon oxide film made of an oxide of the chip 2. In this embodiment, the gate insulating film 20 is made of the same insulating film as the isolation insulating film 14. The gate insulating film 20 is connected to the isolation insulating film 14 at the communicating portion between the isolation trench 13 and the gate trench 19.

[0039] The buried gate electrode 21 is buried in the gate trench 19 with the gate insulating film 20 sandwiched therebetween. In this embodiment, the buried gate electrode 21 is made of conductive polysilicon. A gate potential is applied to the buried gate electrode 21. The buried gate electrode 21 is connected to the buried isolation electrode 15 at the communicating portion between the isolation trench 13 and the gate trench 19.

[0040] The IGBT structure 16 includes a plurality of n-type emitter regions 22 formed in regions along the plurality of trench gate structures 18 in the surface layer portion of the base region 17. Each of the plurality of emitter regions 22 has a higher n-type impurity concentration than the drift region 9.

[0041] The plurality of emitter regions 22 are arranged on both sides of the plurality of trench gate structures 18, and are each formed in a strip shape extending along the plurality of trench gate structures 18 in a plan view. It is preferable that the emitter regions 22 are not formed in a region defined by the trench isolation structure 12 and the ends (first end 18 a / second end 18 b) of the trench gate structures 18 in the surface layer portion of the base region 17.

[0042] The IGBT structure 16 includes a plurality of contact holes 23 formed in the first main surface 3 to expose the emitter regions 22. The plurality of contact holes 23 are formed in regions between pairs of adjacent trench gate structures 18 spaced apart from the plurality of trench gate structures 18. Each of the plurality of contact holes 23 may be formed in a tapered shape such that the opening width narrows from the opening toward the bottom wall.

[0043] In this embodiment, the multiple contact holes 23 penetrate the emitter region 22 to reach the base region 17. Of course, the multiple contact holes 23 may be spaced from the bottom of the emitter region 22 toward the first main surface 3 so as not to reach the base region 17. The multiple contact holes 23 are each formed in a strip shape extending along the multiple trench gate structures 18 in a plan view. In terms of the longitudinal direction (second direction Y), the multiple contact holes 23 are shorter than the multiple trench gate structures 18.

[0044] The IGBT structure 16 includes a plurality of p-type contact regions 24 formed in regions different from the plurality of emitter regions 22 in a surface layer portion of the base region 17. The plurality of contact regions 24 have a higher p-type impurity concentration than the base region 17. The plurality of contact regions 24 are each formed in a strip shape extending along the corresponding contact hole 23 in a plan view. The bottom of each of the plurality of contact regions 24 is formed in a region between the bottom wall of the corresponding contact hole 23 and the bottom of the base region 17.

[0045] The semiconductor device 1 includes a p-type pad well region 30 formed in the surface layer of the first main surface 3 in the pad region 7 so as to define the IGBT region 6 (see FIG. 3 ). The pad well region 30 may also be referred to as a "pad anode region." In this embodiment, the pad well region 30 has a higher p-type impurity concentration than the base region 17. Of course, the pad well region 30 may also have a lower p-type impurity concentration than the base region 17.

[0046] The pad well region 30 is formed in the pad region 7 at a distance from the periphery of the chip 2 toward the IGBT region 6. The pad well region 30 is formed in a polygonal shape (a square shape in this embodiment) that matches the pad region 7 in a plan view.

[0047] Although a specific cross-sectional view is omitted, the pad well region 30 contacts the trench isolation structure 12. The pad well region 30 is formed deeper than the base region 17. Specifically, the pad well region 30 is formed deeper than the trench isolation structure 12 (the plurality of trench gate structures 18).

[0048] The pad well region 30 has a portion covering the bottom wall of the trench isolation structure 12. The pad well region 30 has a peripheral portion extending from the pad region 7 into the IGBT region 6. The peripheral portion of the pad well region 30 has portions covering the bottom walls of the plurality of trench gate structures 18 across the trench isolation structure 12.

[0049] The peripheral portion of the pad well region 30 covers the sidewalls of the trench isolation structure 12 and the sidewalls of the plurality of trench gate structures 18 in the IGBT region 6, and is connected to the base region 17 in the surface layer portion of the first main surface 3. In other words, the pad well region 30 is electrically connected to the base region 17 and the plurality of emitter regions 22 in the IGBT region 6.

[0050] The semiconductor device 1 includes a p-type well region 31 formed in the outer peripheral region 8 in a surface layer portion of the first main surface 3 so as to define the IGBT region 6. The well region 31 may also be referred to as an "anode region." In this embodiment, the well region 31 has a higher p-type impurity concentration than the base region 17. Of course, the well region 31 may also have a lower p-type impurity concentration than the base region 17. It is preferable that the well region 31 has a p-type impurity concentration approximately equal to that of the pad well region 30.

[0051] The well region 31 is formed at a distance from the periphery of the chip 2 toward the IGBT region 6. The well region 31 is formed in a layer shape extending along the first main surface 3 and is exposed from the first main surface 3. The well region 31 is formed in a band shape extending along the IGBT region 6 in a plan view. Specifically, the well region 31 is formed in a ring shape surrounding the IGBT region 6 in a plan view, and has four sides parallel to the periphery of the chip 2. The well region 31 has an inner edge 31a on the IGBT region 6 side and an outer edge 31b on the periphery of the chip 2.

[0052] The well region 31 is formed integrally with the pad well region 30 in a portion extending along the third side surface 5C. That is, the well region 31 integrally includes the pad well region 30 extended from the outer peripheral region 8 side to the pad region 7 side. The width of the well region 31 may be 10 μm or more and 100 μm or less. The width of the well region 31 is preferably 40 μm or more and 80 μm or less.

[0053] The well region 31 is formed deeper than the base region 17. Specifically, the well region 31 is formed deeper than the trench isolation structure 12 (the plurality of trench gate structures 18). The well region 31 is in contact with the trench isolation structure 12. The well region 31 has a portion that covers the bottom wall of the trench isolation structure 12. An inner edge 31 a of the well region 31 is drawn from the outer periphery region 8 into the IGBT region 6 and is located within the IGBT region 6.

[0054] Well region 31 has a portion that crosses trench isolation structure 12 and covers the bottom walls of the plurality of trench gate structures 18. Well region 31 covers the side walls of trench isolation structure 12 and the side walls of the plurality of trench gate structures 18 in IGBT region 6, and is connected to base region 17 in a surface layer portion of first main surface 3. That is, inner edge 31 a of well region 31 is electrically connected to base region 17 and emitter region 22 in IGBT region 6.

[0055] The semiconductor device 1 includes at least one (in this embodiment, multiple) p-type field region 32 formed in the surface layer portion of the first main surface 3 in the peripheral region 8. The number of field regions 32 is arbitrary and may be between 1 and 20. The number of field regions 32 is typically between 3 and 10.

[0056] The plurality of field regions 32 may have a higher p-type impurity concentration than the base region 17. The plurality of field regions 32 may have a higher p-type impurity concentration than the well region 31. Of course, the plurality of field regions 32 may have a p-type impurity concentration approximately equal to that of the well region 31. The plurality of field regions 32 are formed in an electrically floating state.

[0057] The plurality of field regions 32 are formed in a region between the periphery of chip 2 and well region 31, with a gap therebetween. The plurality of field regions 32 are formed in a band shape extending along well region 31 in plan view. In this embodiment, the plurality of field regions 32 are formed in a ring shape (quadratic ring shape) surrounding well region 31 in plan view.

[0058] The plurality of field regions 32 are preferably formed deeper than the base region 17. The plurality of field regions 32 are preferably formed shallower than the well region 31. The plurality of field regions 32 are preferably formed shallower than the well region 31 by a depth of 0.1 μm to 1 μm (preferably 0.5 μm or less) relative to the depth position of the bottom of the well region 31, for example.

[0059] The plurality of field regions 32 are preferably formed to a constant depth. The spacing between the plurality of field regions 32 is preferably arranged so that it gradually increases toward the periphery of the chip 2. The plurality of field regions 32 preferably each have a width smaller than that of the well region 31. The outermost field region 32 of the plurality of field regions 32 is preferably formed to be wider than the other field regions 32.

[0060] The width of each field region 32 may be 1 μm or more and 50 μm or less. The width of each field region 32 may be set to a value within any of the following ranges: 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, and 40 μm or more and 50 μm or less. The width of each field region 32 is preferably 10 μm or more and 30 μm or less.

[0061] The semiconductor device 1 includes an n-type channel stop region 33 formed in the surface layer of the first main surface 3 at an interval from the plurality of field regions 32 toward the periphery of the chip 2 in the peripheral region 8. The channel stop region 33 has a higher n-type impurity concentration than the drift region 9. The channel stop region 33 may be exposed from the first to fourth side surfaces 5A to 5D.

[0062] The channel stop region 33 is formed in a band shape extending along the periphery of the chip 2 in plan view. In this embodiment, the channel stop region 33 is formed in a ring shape (quadratic ring shape) surrounding the plurality of field regions 32 in plan view. The channel stop region 33 is formed in an electrically floating state.

[0063] The semiconductor device 1 includes an insulating film 40 that selectively covers the first main surface 3. In this embodiment, the insulating film 40 has a layered structure including a main surface insulating film 41 (first insulating film) and an interlayer insulating film 42 (second insulating film).

[0064] The main surface insulating film 41 selectively covers the first main surface 3 in the IGBT region 6, the peripheral region 8, and the pad region 7. The main surface insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The main surface insulating film 41 preferably has a single-layer structure made of a single insulating film.

[0065] It is particularly preferable that the main surface insulating film 41 includes a silicon oxide film made of an oxide of the chip 2. In this embodiment, the main surface insulating film 41 is made of the same insulating film as the gate insulating film 20. The main surface insulating film 41 covers the first main surface 3 so as to expose the trench isolation structure 12 and the plurality of trench gate structures 18.

[0066] Specifically, the main surface insulating film 41 is connected to the isolation insulating film 14 and the gate insulating film 20, and exposes the isolation buried electrode 15 and the gate buried electrode 21. The main surface insulating film 41 covers the pad well region 30, the well region 31, the field region 32, and the channel stop region 33 in the pad region 7 and the peripheral region 8.

[0067] The interlayer insulating film 42 covers the main surface insulating film 41. The interlayer insulating film 42 is thicker than the main surface insulating film 41. The interlayer insulating film 42 may have a single-layer structure made of a single insulating film, or a stacked structure including multiple insulating films. The interlayer insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The interlayer insulating film 42 may include at least one of a non-doped silicate glass (NSG) film, a phosphorus silicate glass (PSG) film, and a boron phosphorus silicate glass (BPSG) film, which are examples of silicon oxide films.

[0068] The interlayer insulating film 42 covers the main surface insulating film 41 in the IGBT region 6, the peripheral region 8, and the pad region 7. The interlayer insulating film 42 covers the main surface insulating film 41, the trench isolation structure 12, and the plurality of trench gate structures 18 in the IGBT region 6. The interlayer insulating film 42 covers the pad well region 30, the well region 31, the field region 32, and the channel stop region 33 with the main surface insulating film 41 sandwiched therebetween in the pad region 7 and the peripheral region 8.

[0069] The semiconductor device 1 includes a gate wiring 43 arranged in the form of a film inside the insulating film 40. In this embodiment, the gate wiring 43 is made of a conductive polysilicon film. In this embodiment, the gate wiring 43 includes a gate pad wiring 44, a gate line wiring 45, and a plurality of gate connection wirings 46. The gate line wiring 45 may also be called a "gate finger wiring."

[0070] The gate pad wiring 44 is disposed inside a portion of the insulating film 40 that covers the pad region 7, and faces the pad well region 30 in the thickness direction of the chip 2. Specifically, the gate pad wiring 44 is disposed in the form of a film on the main surface insulating film 41, and is covered by the interlayer insulating film 42. The gate pad wiring 44 is formed in a polygonal shape (a quadrangle in this embodiment) that matches the pad region 7 in a plan view. The peripheral portion of the gate pad wiring 44 may be located within the pad region 7.

[0071] Of course, the peripheral portion of the gate pad wiring 44 may be drawn from the pad region 7 toward the IGBT region 6. In this case, the peripheral portion of the gate pad wiring 44 may be drawn from above the main surface insulating film 41 onto a portion of the trench isolation structure 12 that defines the pad region 7, and connected to the isolated buried electrode 15. Furthermore, the peripheral portion of the gate pad wiring 44 may cover a portion (first end 18A or second end 18B) of the multiple trench gate structures 18, and may be connected to the multiple buried gate electrodes 21.

[0072] The gate line wiring 45 is disposed inside the portion of the insulating film 40 that covers the peripheral region 8, and faces the well region 31 in the thickness direction of the chip 2. Specifically, the gate line wiring 45 is disposed in the form of a film on the main surface insulating film 41, and is covered by the interlayer insulating film 42. In this embodiment, the gate line wiring 45 is disposed only in the portion of the insulating film 40 that covers the well region 31.

[0073] That is, the gate line wiring 45 faces an inner portion of the well region 31 at a distance from the outer edge 31b and the inner edge 31a of the well region 31 in a plan view. The entire gate line wiring 45 faces the well region 31 with the main surface insulating film 41 therebetween. The gate line wiring 45 extends in a strip shape along the well region 31 in a plan view. It is preferable that the gate line wiring 45 partitions the IGBT region 6 from multiple directions in a plan view.

[0074] In this embodiment, the gate line wiring 45 is formed in a strip shape extending along the first to fourth side surfaces 5A to 5D in a plan view, and partitions the IGBT region 6 from four directions. The gate line wiring 45 may be formed in an endless strip shape or a strip shape with edges so as to surround the IGBT region 6. In this embodiment, the gate line wiring 45 is formed in a ring shape (specifically, a quadrangular ring shape) surrounding the IGBT region 6.

[0075] The gate line wiring 45 is formed integrally with the gate pad wiring 44 in a portion extending along the third side surface 5C. That is, the gate line wiring 45 integrally includes the gate pad wiring 44 drawn from the peripheral region 8 to the pad region 7. The gate line wiring 45 has a width smaller than the width of the well region 31. The width of the gate line wiring 45 may be 10 μm or more and 100 μm or less. The width of the gate line wiring 45 is preferably 15 μm or more and 60 μm or less.

[0076] The plurality of gate connection wirings 46 are disposed inside the insulating film 40 so as to electrically connect the gate line wiring 45 to the plurality of trench gate structures 18. The plurality of gate connection wirings 46 are drawn from a portion of the gate line wiring 45 extending along the first side surface 5A toward the first ends 18A of the plurality of trench gate structures 18. The plurality of gate connection wirings 46 are also drawn from a portion of the gate line wiring 45 extending along the second side surface 5B toward the second ends 18B of the plurality of trench gate structures 18.

[0077] The plurality of gate connection wirings 46 are arranged at intervals along the gate line wiring 45 on the first side surface 5A side and are drawn out toward the trench isolation structure 12. The plurality of gate connection wirings 46 are preferably arranged at equal intervals in the first direction X. The plurality of gate connection wirings 46 are drawn out from above the main surface insulating film 41 onto the trench isolation structure 12 on the first side surface 5A side and connected to the isolation buried electrode 15. In this embodiment, the plurality of gate connection wirings 46 respectively cover the first ends 18A of the plurality of trench gate structures 18 and are connected to the plurality of gate buried electrodes 21.

[0078] Similarly, the plurality of gate connection wirings 46 are arranged at intervals along the gate line wirings 45 on the second side surface 5B side, and are drawn out toward the trench isolation structure 12. The plurality of gate connection wirings 46 are preferably arranged at equal intervals in the first direction X. The plurality of gate connection wirings 46 are drawn out from above the main surface insulating film 41 onto the trench isolation structure 12 on the second side surface 5B side, and connected to the isolated buried electrode 15.

[0079] In this embodiment, the plurality of gate connection wirings 46 respectively cover the second ends 18B of the plurality of trench gate structures 18 and are connected to the plurality of gate buried electrodes 21. In this embodiment, the gate wiring 43 is formed from the same conductive material as the isolated buried electrode 15 and the plurality of gate buried electrodes 21, and is composed of lead-out portions that are led out from the isolated buried electrode 15 and the plurality of gate buried electrodes 21 onto the main surface insulating film 41.

[0080] The semiconductor device 1 has a plurality of emitter openings 50 that expose the plurality of emitter regions 22 in a portion of the insulating film 40 that covers the IGBT region 6. The plurality of emitter openings 50 are formed in a one-to-one correspondence with the plurality of contact holes 23, and each communicates with the corresponding contact hole 23. The plurality of emitter openings 50 are each formed in a strip shape that extends along the corresponding contact hole 23 in a plan view.

[0081] The semiconductor device 1 includes a plurality of emitter connection electrodes 51 embedded in the insulating film 40 so as to be electrically connected to the plurality of emitter regions 22. The plurality of emitter connection electrodes 51 are embedded in a plurality of emitter openings 50. The plurality of emitter connection electrodes 51 extend from the plurality of emitter openings 50 into the plurality of contact holes 23 and are electrically connected to the emitter regions 22 and contact regions 24.

[0082] Each emitter-connecting electrode 51 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In this embodiment, each emitter-connecting electrode 51 has a layered structure including a Ti-based metal film and a W-based metal film.

[0083] The Ti-based metal may include at least one of a pure Ti film (a Ti film with a purity of 99% or more) and a Ti alloy film (hereinafter the same). The Ti alloy film may be a TiN film (hereinafter the same). The W-based metal may include at least one of a pure W film (a W film with a purity of 99% or more) and a W alloy film (hereinafter the same).

[0084] The Al-based metal may include at least one of a pure Al film (an Al film with a purity of 99% or more) and an Al alloy film (hereinafter the same). The Al alloy film may include at least one of an AlCu alloy, an AlSi alloy, and an AlSiCu alloy (hereinafter the same). The Cu-based metal may include at least one of a pure Cu film (a Cu film with a purity of 99% or more) and a Cu alloy film (hereinafter the same).

[0085] The semiconductor device 1 includes at least one gate opening 52 (in this embodiment, a plurality of gate openings 52) that selectively exposes the gate line wiring 45 in a portion of the insulating film 40 that covers the gate line wiring 45. In this embodiment, a plurality of gate openings 52 are formed, but a single gate opening 52 may also be formed.

[0086] The multiple gate openings 52 are spaced apart from the inner and outer edges of the gate line wiring 45 to expose the inner portions of the gate line wiring 45. The multiple gate openings 52 are formed at intervals from one another from the IGBT region 6 toward the peripheral edge of the chip 2, and extend in a strip shape along the gate line wiring 45. Each gate opening 52 may be formed in an endless strip shape or a strip shape with edges so as to surround the IGBT region 6. In this embodiment, each gate opening 52 is formed in a ring shape (specifically, a square ring shape) surrounding the IGBT region 6.

[0087] Although specific illustrations are omitted, the semiconductor device 1 may include at least one (in this embodiment, multiple) gate openings 52 that selectively expose the gate pad wiring 44 in the portion of the insulating film 40 that covers the gate pad wiring 44.

[0088] The semiconductor device 1 includes at least one gate connection electrode 53 (in this embodiment, multiple gate connection electrodes 53) embedded in the insulating film 40 so as to be electrically connected to the gate line wiring 45. Each gate connection electrode 53 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In this embodiment, each gate connection electrode 53 has a stacked structure including a Ti-based metal film and a W-based metal film.

[0089] The plurality of gate connection electrodes 53 are embedded in the plurality of gate openings 52 in a one-to-one correspondence, respectively. The plurality of gate connection electrodes 53 are electrically connected to the gate line wiring 45 in the corresponding gate openings 52. When the gate openings 52 that expose the gate pad wiring 44 are formed in the insulating film 40, the gate connection electrodes 53 that are electrically connected to the gate pad wiring 44 may be formed in the gate openings 52.

[0090] The semiconductor device 1 includes a plurality of well openings 54 that selectively expose the well region 31 in a portion of the insulating film 40 that covers the peripheral region 8. The plurality of well openings 54 include at least one (a plurality in this embodiment) first well opening 55 and at least one (a plurality in this embodiment) second well opening 56. In this embodiment, a plurality of first well openings 55 are formed, but a single first well opening 55 may also be formed. Furthermore, a plurality of second well openings 56 are formed, but a single second well opening 56 may also be formed.

[0091] The plurality of first well openings 55 expose the well region 31 on the IGBT region 6 side. Specifically, the plurality of first well openings 55 are formed at intervals from the middle of the well region 31 in the width direction toward the inner edge 31 a of the well region 31, selectively exposing the region of the well region 31 on the inner edge 31 a side. More specifically, the plurality of first well openings 55 are formed at intervals from the gate line wiring 45 toward the inner edge 31 a of the well region 31, selectively exposing the inner edge portion of the well region 31.

[0092] The multiple first well openings 55 are formed at intervals from one another from the IGBT region 6 side toward the peripheral edge of the chip 2, and extend in a strip shape along the well region 31. Each first well opening 55 has a portion extending in the first direction X along the well region 31 and a portion extending in the second direction Y along the well region 31.

[0093] Each first well opening 55 includes a plurality of segment openings 55a formed at intervals so as to expose regions between the plurality of gate connection wirings 46 in the portion extending in the first direction X. In other words, the plurality of segment openings 55a are formed at intervals from the plurality of gate connection wirings 46 so as not to expose the plurality of gate connection wirings 46.

[0094] The plurality of segment openings 55 a are arranged in a region surrounded by the trench isolation structure 12 (the plurality of trench gate structures 18), the gate line wiring 45, and the plurality of gate connection wirings 46. The plurality of segment openings 55 a are each formed in a strip shape extending in the first direction X.

[0095] The plurality of second well openings 56 expose the well region 31 on the peripheral side of the chip 2. Specifically, the plurality of second well openings 56 are formed at intervals from the middle of the well region 31 in the width direction toward the outer edge 31b of the well region 31, selectively exposing the region of the well region 31 on the outer edge 31b side. More specifically, the plurality of second well openings 56 are formed at intervals from the gate line wiring 45 toward the outer edge 31b of the well region 31, selectively exposing the outer edge portion of the well region 31.

[0096] The multiple second well openings 56 are formed at intervals from one another from the IGBT region 6 side toward the peripheral edge of the chip 2, and extend in a band shape along the well region 31. Each second well opening 56 may be formed in an endless band shape or in a band shape with edges so as to surround the IGBT region 6. In this embodiment, each second well opening 56 is formed in a ring shape (specifically, a square ring shape) surrounding the IGBT region 6.

[0097] The semiconductor device 1 includes a plurality of well connection electrodes 57 embedded in the insulating film 40 so as to be electrically connected to the well region 31. Each well connection electrode 57 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In this embodiment, each well connection electrode 57 has a stacked structure including a Ti-based metal film and a W-based metal film.

[0098] The multiple well-connecting electrodes 57 include at least one (multiple in this embodiment) first well-connecting electrode 58 and at least one (multiple in this embodiment) second well-connecting electrode 59. In this embodiment, multiple first well-connecting electrodes 58 are formed, but a single well-connecting electrode 57 may also be formed. Also, multiple second well-connecting electrodes 59 are formed, but a single well-connecting electrode 57 may also be formed.

[0099] The plurality of first well connection electrodes 58 are connected to the well region 31 on the inner edge 31a side (the IGBT region 6 side) of the well region 31. Specifically, the plurality of first well connection electrodes 58 are embedded in the plurality of first well openings 55 in a one-to-one correspondence, respectively.

[0100] That is, the plurality of first well-connecting electrodes 58 are formed at intervals from the middle of the well region 31 in the width direction toward the inner edge 31a of the well region 31, and are electrically connected to the region on the inner edge 31a side of the well region 31. The plurality of first well-connecting electrodes 58 are also formed at intervals from the gate line wiring 45 in the region on the inner edge 31a side of the well region 31, and are electrically connected to the inner edge portion of the well region 31.

[0101] The second well connection electrodes 59 are connected to the well region 31 on the outer edge 31b side of the well region 31 (the peripheral edge side of the chip 2). Specifically, the second well connection electrodes 59 are embedded in the second well openings 56 in a one-to-one correspondence, respectively.

[0102] That is, the plurality of second well connection electrodes 59 are formed at intervals from the middle of the well region 31 in the width direction toward the outer edge 31b of the well region 31, and are electrically connected to the region on the outer edge 31b side of the well region 31. The plurality of second well connection electrodes 59 are also formed at intervals from the gate line wiring 45 in the region on the outer edge 31b side of the well region 31, and are electrically connected to the outer edge of the well region 31.

[0103] The semiconductor device 1 includes a gate electrode 60 disposed on the insulating film 40. The gate electrode 60 is made of a different conductive material from the gate wiring 43. In this embodiment, the gate electrode 60 is made of a metal film and has a lower resistance value than the gate wiring 43. The gate electrode 60 may also be referred to as a "gate metal." The gate electrode 60 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In this embodiment, the gate electrode 60 has a stacked structure including a Ti-based metal film and an Al-based metal film.

[0104] The gate electrode 60 includes a gate pad electrode 61 and a gate line electrode 62. The gate line electrode 62 may also be referred to as a "gate finger electrode." The gate pad electrode 61 is disposed on a portion of the insulating film 40 that covers the gate pad wiring 44. In this embodiment, the gate pad electrode 61 is formed in a polygonal shape (a quadrangular shape in this embodiment) that matches the pad region 7 in a plan view.

[0105] The gate pad electrode 61 faces the gate pad wiring 44 across a part of the insulating film 40 (interlayer insulating film 42) in the thickness direction of the chip 2. The gate pad electrode 61 faces the pad well region 30 across the insulating film 40 and the gate pad wiring 44 in the thickness direction of the chip 2. When the gate connection electrode 53 is connected to the gate pad wiring 44, the gate pad electrode 61 may be electrically connected to the gate connection electrode 53 via the gate connection electrode 53.

[0106] The gate pad electrode 61 may have a planar area equal to or larger than the planar area of ​​the pad region 7, or may have a planar area smaller than the planar area of ​​the pad region 7. The gate pad electrode 61 may have a planar area equal to or larger than the planar area of ​​the gate pad wiring 44, or may have a planar area smaller than the planar area of ​​the gate pad wiring 44.

[0107] The gate pad electrode 61 may be formed at a distance from the plurality of trench gate structures 18 in a plan view, or may face the plurality of trench gate structures 18 with the insulating film 40 interposed therebetween. The gate pad electrode 61 may be formed at a distance from the trench isolation structure 12 in a plan view, or may face the trench isolation structure 12 with the insulating film 40 interposed therebetween.

[0108] The gate line electrode 62 is disposed on the insulating film 40 on a portion covering the gate line wiring 45. The gate line electrode 62 is formed integrally with the gate pad electrode 61, and is drawn out in a strip shape from the gate pad electrode 61 onto the insulating film 40. In this embodiment, the gate line electrode 62 is drawn out from the gate pad electrode 61 onto the insulating film 40 to a region between the first well connection electrode 58 and the second well connection electrode 59.

[0109] The gate line electrode 62 is disposed at a distance from the first well connection electrode 58 and the second well connection electrode 59, and covers the plurality of gate connection electrodes 53. In other words, the gate line electrode 62 is disposed at a distance from the first well connection electrode 58 toward the outer edge 31b of the well region 31 (toward the periphery of the chip 2), and is disposed at a distance from the second well connection electrode 59 toward the inner edge 31a of the well region 31 (toward the IGBT region 6). The gate line electrode 62 is electrically connected to the gate line wiring 45 via the plurality of gate connection electrodes 53.

[0110] The gate line electrode 62 faces the gate line electrode 62 across a part of the insulating film 40 in the thickness direction of the chip 2. The gate line electrode 62 faces the well region 31 across the insulating film 40 and the gate line electrode 62 in the thickness direction of the chip 2. The gate line electrode 62 has a width smaller than the width of the well region 31. It is preferable that the gate line electrode 62 has a width smaller than the width of the gate line wiring 45. Of course, the gate line electrode 62 may have a width equal to or larger than the width of the gate line wiring 45.

[0111] The gate line electrodes 62 extend in a strip shape along the gate line wiring 45 in a plan view. The gate line electrodes 62 preferably partition the IGBT region 6 from multiple directions in a plan view. In this embodiment, the gate line electrodes 62 are formed in a strip shape extending along the first to fourth side faces 5A to 5D in a plan view, and partition the IGBT region 6 from four directions.

[0112] The gate line electrode 62 may be formed in an endless strip shape or in a strip shape with edges so as to surround the IGBT region 6. In this embodiment, the gate line electrode 62 is formed in a ring shape (specifically, a quadrangular ring shape) so as to surround the IGBT region 6, and has a pair of open ends 63 in the portion extending along the fourth side surface 5D.

[0113] The semiconductor device 1 includes an emitter electrode 65 disposed on the insulating film 40 and spaced apart from the gate electrode 60. The emitter electrode 65 is made of a different conductive material from that of the gate wiring 43. In this embodiment, the emitter electrode 65 is made of a metal film and has a lower resistance value than the gate wiring 43. The emitter electrode 65 may also be referred to as an "emitter metal."

[0114] The emitter electrode 65 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In this embodiment, the emitter electrode 65 has a layered structure including a Ti-based metal film and an Al-based metal film. In other words, the emitter electrode 65 is formed of the same material as the gate electrode 60.

[0115] The emitter electrode 65 includes an emitter pad electrode 66 and an emitter line electrode 67. The emitter line electrode 67 may also be referred to as an "emitter finger electrode." The emitter pad electrode 66 is disposed on a portion of the insulating film 40 that covers the IGBT region 6. Specifically, the emitter pad electrode 66 is disposed at a distance from the gate pad electrode 61 and the gate line electrode 62, and is formed in a polygonal shape having a recess that is recessed along the gate pad electrode 61 in a plan view.

[0116] The emitter pad electrode 66 collectively covers the plurality of trench gate structures 18 and the plurality of emitter connecting electrodes 51. The emitter pad electrode 66 faces the plurality of trench gate structures 18 across the insulating film 40, and is electrically connected to the plurality of emitter regions 22 via the plurality of emitter connecting electrodes 51. The emitter pad electrode 66 has an emitter lead-out portion 68 that is led out from the IGBT region 6 to the outer periphery region 8 across the region immediately above the trench isolation structure 12 so as to face the well region 31 in the thickness direction of the chip 2.

[0117] The emitter lead-out portion 68 (emitter pad electrode 66) covers a region on the inner edge 31a side of the well region 31 relative to the widthwise intermediate portion of the well region 31. Specifically, the emitter lead-out portion 68 covers the inner edge of the well region 31 at a distance from the gate line electrode 62 toward the IGBT region 6, and collectively covers the plurality of first well connection electrodes 58. As a result, the emitter pad electrode 66 is electrically connected to the inner edge of the well region 31 via the plurality of first well connection electrodes 58.

[0118] The emitter line electrode 67 is formed integrally with the emitter pad electrode 66 and is drawn out from the emitter pad electrode 66 onto the insulating film 40. Specifically, the emitter line electrode 67 passes through the region between the pair of open ends 63 of the gate line electrode 62 on the insulating film 40 and is drawn out in a strip shape from the emitter pad electrode 66 to the outer circumferential region 8.

[0119] The emitter line electrode 67 is routed over a portion of the insulating film 40 that covers the well region 31. In other words, the emitter line electrode 67 faces the well region 31 across the insulating film 40 in the thickness direction of the chip 2. The emitter line electrode 67 is arranged at a distance from the gate line electrode 62 toward the outer edge 31b of the well region 31 (toward the peripheral edge of the chip 2) so as to cover the multiple second well connection electrodes 59. As a result, the emitter line electrode 67 is electrically connected to the outer edge of the well region 31 via the multiple second well connection electrodes 59.

[0120] The emitter line electrode 67 extends in a strip shape along the outer edge 31b of the well region 31 in a plan view. The emitter line electrode 67 preferably defines the IGBT region 6 from multiple directions in a plan view. In this embodiment, the emitter line electrode 67 is formed in a strip shape extending along the first to fourth side surfaces 5A to 5D in a plan view, defining the IGBT region 6 from four directions. The well region 31 may be formed in an endless strip shape or a strip shape with edges so as to surround the IGBT region 6. In this embodiment, the emitter line electrode 67 is formed in a ring shape (specifically, a square ring shape) surrounding the IGBT region 6.

[0121] The emitter line electrode 67 preferably has a width less than the width of the well region 31. The emitter line electrode 67 is preferably arranged at a distance from the region directly above the innermost field region 32 toward the well region 31. The emitter line electrode 67 is preferably arranged at a distance from the region directly above the outer edge 31b of the well region 31 toward the inner edge 31a of the well region 31. The region of the emitter line electrode 67 other than the portion connected to the emitter pad electrode 66 is preferably arranged only in the region facing the well region 31.

[0122] The insulating film 40 includes at least one field opening 70 (in this embodiment, multiple field openings 70) that selectively expose each field region 32 in the peripheral region 8. The multiple field openings 70 expose corresponding field regions 32 in a one-to-many correspondence. Of course, a single field opening 70 may expose corresponding field regions 32 in a one-to-one correspondence. The multiple field openings 70 are formed in a strip shape extending along the corresponding field regions 32. In this embodiment, the multiple field openings 70 are formed in an annular shape (quadratic annular shape) extending along the corresponding field regions 32.

[0123] The semiconductor device 1 includes at least one field connection electrode 71 (in this embodiment, multiple field connection electrodes 71) embedded in the insulating film 40 so as to be electrically connected to the corresponding field region 32. Each field connection electrode 71 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. In this embodiment, each field connection electrode 71 has a layered structure including a Ti-based metal film and a W-based metal film.

[0124] The plurality of field connection electrodes 71 are embedded in the plurality of field openings 70 in a one-to-one correspondence, respectively. The plurality of field connection electrodes 71 are electrically connected to the corresponding field regions 32 in the corresponding field openings 70. In this form, the plurality of field connection electrodes 71 are formed in an electrically floating state.

[0125] The semiconductor device 1 includes a plurality of field electrodes 72 formed on the insulating film 40 in the peripheral region 8. The plurality of field electrodes 72 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. The plurality of field electrodes 72 may have a layered structure including a Ti-based metal film and an Al-based metal film. The plurality of field electrodes 72 are formed in an electrically floating state.

[0126] The plurality of field electrodes 72 are formed in a one-to-one correspondence with the corresponding field regions 32. Each field electrode 72 collectively covers the corresponding plurality of field connection electrodes 71. Each field electrode 72 is electrically connected to the corresponding field region 32 via the corresponding plurality of field connection electrodes 71.

[0127] The multiple field electrodes 72 are formed in strip shapes extending along the corresponding field regions 32. In this embodiment, the multiple field electrodes 72 are formed in ring shapes (square ring shapes) extending along the corresponding field regions 32. The outermost field electrode 72 includes a field lead portion 72a that is led out toward the periphery of the chip 2, and may be formed wider than the other field electrodes 72.

[0128] The insulating film 40 includes a channel stop opening 73 that exposes the channel stop region 33 in the peripheral region 8. The channel stop opening 73 is formed in a strip shape extending along the channel stop region 33. In this embodiment, the channel stop opening 73 is formed in a ring shape (quadratic ring shape) extending along the channel stop region 33 and communicating with the periphery of the chip 2.

[0129] The semiconductor device 1 includes a channel stop electrode 74 formed on the insulating film 40 in the peripheral region 8. The channel stop electrode 74 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. The channel stop electrode 74 may have a layered structure including a Ti-based metal film and an Al-based metal film. The channel stop electrode 74 is formed in an electrically floating state.

[0130] The channel stop electrode 74 is formed in a strip shape extending along the channel stop region 33. In this embodiment, the channel stop electrode 74 is formed in a ring shape (quadratic ring shape) extending along the channel stop region 33. The channel stop electrode 74 enters the channel stop opening 73 from above the insulating film 40 and is electrically connected to the channel stop region 33. The channel stop electrode 74 may be formed at a distance from the periphery of the chip 2 toward the IGBT region 6 so as to expose the peripheral portion of the first main surface 3 (channel stop region 33).

[0131] The semiconductor device 1 includes a collector electrode 75 covering the second main surface 4. The collector electrode 75 is electrically connected to the collector region 11 exposed from the second main surface 4. The collector electrode 75 forms an ohmic contact with the collector region 11. The collector electrode 75 may cover the entire second main surface 4 so as to be continuous with the periphery of the chip 2 (first to fourth side surfaces 5A to 5D).

[0132] Collector electrode 75 may have a single-film structure or a multilayer structure including at least one of a Ti film, a Ni film, a Pd film, an Au film, an Ag film, and an Al film. Collector electrode 75 preferably includes at least a Ti film that directly covers second main surface 4. Collector electrode 75 may have a multilayer structure including, for example, a Ti film, a Ni film, a Pd film, and an Au film that are stacked in this order from the second main surface 4 side.

[0133] 5 to 7, semiconductor device 1 includes an n-type cathode region 80 formed in a surface layer portion of second main surface 4 in peripheral region 8. The basic structure of cathode region 80 will be described below. Cathode region 80 has an n-type impurity concentration higher than the p-type impurity concentration of collector region 11, and is a region in which the conductivity type of a portion of collector region 11 is converted from p-type to n-type. Cathode region 80 preferably has a higher n-type impurity concentration than drift region 9 (buffer region 10).

[0134] The cathode region 80 extends in a layered form along the second main surface 4 and is exposed from the second main surface 4. The cathode region 80 penetrates the collector region 11 so as to be connected to the buffer region 10. The cathode region 80 forms an ohmic contact with the above-mentioned collector electrode 75. In this embodiment, the cathode region 80 is disposed at a location facing the well region 31 in the thickness direction of the chip 2, and forms a diode 81 together with the well region 31. The diode 81 is formed as a freewheeling diode for the IGBT structure 16.

[0135] The cathode region 80 may be formed in an endless or edged band shape in a plan view so as to surround the IGBT region 6. In this embodiment, the cathode region 80 is formed in a ring shape (specifically, a quadrangular ring shape) so as to surround the IGBT region 6. The cathode region 80 is arranged so that the well region 31 has a portion facing the cathode region 80 and a portion facing the collector region 11 in the thickness direction of the chip 2.

[0136] That is, the cathode region 80 is formed narrower than the well region 31 so as not to face the entire well region 31 in the thickness direction of the chip 2. The width of the cathode region 80 may be 5 μm or more and 90 μm or less. The width of the cathode region 80 is preferably 10 μm or more and 40 μm or less.

[0137] The cathode region 80 is preferably formed at a distance from the base region 17 on the peripheral edge side of the second main surface 4 so as not to face the base region 17 at least in the thickness direction of the chip 2. The cathode region 80 is preferably formed at a distance from the plurality of trench gate structures 18 on the peripheral edge side of the second main surface 4 so as not to face the plurality of trench gate structures 18 in the thickness direction of the chip 2. It is particularly preferable that the cathode region 80 is formed at a distance from the trench isolation structures 12 on the peripheral edge side of the second main surface 4 so as not to face the trench isolation structures 12 in the thickness direction of the chip 2.

[0138] That is, it is preferable that the cathode region 80 is formed at a distance from the IGBT region 6 toward the peripheral edge of the chip 2 so as not to face the IGBT region 6 in the thickness direction of the chip 2. That is, it is preferable that the cathode region 80 is formed only in the outer peripheral region 8, and not in the IGBT region 6. In this case, it is possible to suppress the electrical influence from the IGBT region 6 to the diode 81, and to suppress the electrical influence from the diode 81 to the IGBT region 6.

[0139] The ratio of the planar area of ​​the cathode region 80 to the planar area of ​​the second main surface 4 is preferably 0.1% or more and 10% or less. The ratio of the planar area of ​​the cathode region 80 may fall within any one of the ranges of 0.1% or more and 1% or less, 1% or more and 2% or less, 2% or more and 4% or less, 4% or more and 6% or less, 6% or more and 8% or less, and 8% or more and 10% or less.

[0140] When a forward voltage VF of the diode 81 is applied between the emitter electrode 65 and the collector electrode 75, a forward current IF flows through the diode 81. In this configuration, the forward current IF flows from the first well-connection electrode 58 and the second well-connection electrode 59 to the cathode region 80. The electrical characteristics of the diode 81 during forward operation vary depending on the location of the cathode region 80. The relationship between the location of the cathode region 80 and the electrical characteristics of the diode 81 will be described below with reference to FIGS. 9 to 16 .

[0141] 9 is a cross-sectional view illustrating the location of the cathode region 80. Referring to FIG. 9, a gate reference position PG, a first well reference position PW1, and a second well reference position PW2 are set as locations for the cathode region 80. The gate reference position PG is a position directly below the center of the gate line electrode 62. In this embodiment, the gate reference position PG is also a position directly below the center of the gate line wiring 45. Therefore, the gate reference position PG may be set directly below the center of the gate line electrode 62 or directly below the center of the gate line wiring 45.

[0142] The first well reference position PW1 is a position directly below the first well connecting electrode 58. When a single first well connecting electrode 58 is formed, the first well reference position PW1 is a position directly below the center of the single first well connecting electrode 58. When a plurality of first well connecting electrodes 58 are formed, the first well reference position PW1 is a position directly below the midpoint between the innermost first well connecting electrode 58 arranged on the IGBT region 6 side and the outermost first well connecting electrode 58 arranged on the peripheral edge side of the chip 2.

[0143] The second well reference position PW2 is a position directly below the second well connecting electrode 59. When a single second well connecting electrode 59 is formed, the second well reference position PW2 is a position directly below the center of the single second well connecting electrode 59. When a plurality of second well connecting electrodes 59 are formed, the second well reference position PW2 is a position directly below the midpoint between the innermost second well connecting electrode 59 arranged on the IGBT region 6 side and the outermost second well connecting electrode 59 arranged on the peripheral edge side of the chip 2.

[0144] 10 is a cross-sectional view showing the current density of the forward current IF when the cathode region 80 is located at the gate reference position PG. FIG. 11 is a cross-sectional view showing the current density of the forward current IF when the cathode region 80 is located at the first well reference position PW1. FIG. 12 is a cross-sectional view showing the current density of the forward current IF when the cathode region 80 is located at the second well reference position PW2. In FIGS. 10 to 12, the width of the cathode region 80 is fixed to a constant value (here, 10 μm).

[0145] 10 , when the cathode region 80 is disposed at the gate reference position PG, a first current path CP1 is formed from the plurality of first well connecting electrodes 58, detouring into the region immediately below the gate line electrode 62, and heading toward the cathode region 80, and a second current path CP2 is formed from the plurality of second well connecting electrodes 59, detouring into the region immediately below the gate line electrode 62, and heading toward the cathode region 80. The current density of the forward current IF is sparse in both the first current path CP1 and the second current path CP2.

[0146] 11 , when the cathode region 80 is disposed at the first well reference position PW1, a first current path CP1 is formed that runs linearly from the plurality of first well connecting electrodes 58 to the cathode region 80, and a second current path CP2 is formed that runs from the plurality of second well connecting electrodes 59 to the region directly below the gate line electrode 62 and then runs toward the cathode region 80. The current density of the forward current IF is dense in the first current path CP1 and sparse in the second current path CP2.

[0147] 12, when the cathode region 80 is disposed at the second well reference position PW2, a first current path CP1 is formed from the plurality of first well connecting electrodes 58, going around to the region directly below the gate line electrode 62 and heading toward the cathode region 80, and a second current path CP2 is formed from the plurality of second well connecting electrodes 59, heading linearly toward the cathode region 80. The current density of the forward current IF is sparse in the first current path CP1 and dense in the second current path CP2.

[0148] Fig. 13 is a graph summarizing the relationship between forward current IF and forward voltage VF for the cases of Fig. 10 to Fig. 12. In Fig. 13, the vertical axis represents forward current IF [A], and the horizontal axis represents forward voltage VF [V]. Fig. 13 shows a first characteristic S1, a second characteristic S2, and a third characteristic S3.

[0149] The first characteristic S1 represents the characteristic when the cathode region 80 is located at the gate reference position PG. The second characteristic S2 represents the characteristic when the cathode region 80 is located at the first well reference position PW1. The third characteristic S3 represents the characteristic when the cathode region 80 is located at the second well reference position PW2.

[0150] The forward current IF according to the second characteristic S2 was higher than the forward current IF according to the first characteristic S1. The forward current IF according to the third characteristic S3 was also higher than the forward current IF according to the first characteristic S1. The forward current IF according to the second characteristic S2 was also higher than the forward current IF according to the third characteristic S3. This indicates that it is preferable to position the cathode region 80 away from the gate reference position PG in order to prevent a detour current path. It also indicates that it is preferable to position the cathode region 80 at either or both of the first well reference position PW1 and the second well reference position PW2.

[0151] 14A is a graph showing the relationship between the location of the cathode region 80 and the forward current IF. In FIG. 14, the vertical axis represents the forward current IF [A], and the horizontal axis represents the position of the cathode region 80. FIG. 14A shows the result when the location of the cathode region 80 is moved from the first well reference position PW1 toward the periphery of the chip 2. In this example, the location of the cathode region 80 is moved to the region immediately below the third field region 32 counting from the well region 31 side. The width of the cathode region 80 is fixed to a constant value (here, 10 μm).

[0152] 14A , the forward current IF gradually decreased as the location of the cathode region 80 moved from the first well reference position PW1 toward the gate reference position PG. The forward current IF gradually increased as the location of the cathode region 80 moved from the gate reference position PG toward the second well reference position PW2. The forward current IF gradually decreased as the location of the cathode region 80 moved from the second well reference position PW2 toward the periphery of the chip 2.

[0153] The forward current IF has a first maximum value v1 when the cathode region 80 is located at the first well reference position PW1. The forward current IF has a minimum value v2 when the cathode region 80 is located at the gate reference position PG. The forward current IF has a second maximum value v3 when the cathode region 80 is located at the second well reference position PW2.

[0154] When the cathode region 80 is positioned near the midpoint between the first well reference position PW1 and the gate reference position PG, the forward current IF assumes a value near the intermediate value between the first maximum value v1 and the minimum value v2. The value near the intermediate value between the first maximum value v1 and the minimum value v2 is also a value near the first inflection point v4 between the first maximum value v1 and the minimum value v2.

[0155] When the cathode region 80 was located near the midpoint between the second well reference position PW2 and the gate reference position PG, the forward current IF took a value near the intermediate value between the second maximum value v3 and the minimum value v2. The value near the intermediate value between the second maximum value v3 and the minimum value v2 is also a value near the second inflection point v5 between the second maximum value v3 and the minimum value v2.

[0156] From the above, it has been found that it is preferable to set a prohibited range 82 on the second main surface 4 that prohibits the placement of the cathode region 80 near the gate reference position PG. It has also been found that it is preferable to set a first allowed range 83 on the second main surface 4 that allows the placement of a part or the whole of the cathode region 80 near the first well reference position PW1. It has also been found that it is preferable to set a second allowed range 84 on the second main surface 4 that allows the placement of a part or the whole of the cathode region 80 near the second well reference position PW2.

[0157] 14B is a graph illustrating a first setting example of prohibited range 82, first allowed range 83, and second allowed range 84 based on the result of Fig. 14A. Referring to Fig. 14B, when cathode region 80 is disposed in a region on the side of first well reference position PW1, prohibited range 82 and first allowed range 83 may be set based on a first reference distance Da between first well reference position PW1 and gate reference position PG.

[0158] In this case, the prohibited range 82 is set to a range not exceeding half the first reference distance Da from the gate reference position PG. The prohibited range 82 is set on the IGBT region 6 side from the first well reference position PW1. In this case, the cathode region 80 is disposed at a distance of at least half the first reference distance Da from the gate reference position PG toward the first well reference position PW1.

[0159] On the other hand, the first allowable range 83 is set within a range not exceeding half the first reference distance Da from the first well reference position PW1. The first allowable range 83 is set on the IGBT region 6 side and the gate reference position PG side from the first well reference position PW1. In this case, at least a portion of the cathode region 80 is disposed within a range not exceeding half the first reference distance Da from the first well reference position PW1.

[0160] When the cathode region 80 is positioned in the region on the second well reference position PW2 side, the prohibited range 82 and the second allowed range 84 are set based on the second reference distance Db between the second well reference position PW2 and the gate reference position PG.

[0161] In this case, the prohibited range 82 is set to a range not exceeding half the second reference distance Db from the gate reference position PG. The prohibited range 82 is set on the second well reference position PW2 side from the gate reference position PG. In this case, the cathode region 80 is disposed at least half the second reference distance Db away from the gate reference position PG toward the second well reference position PW2.

[0162] On the other hand, the second allowable range 84 is set within a range not exceeding half the second reference distance Db from the second well reference position PW2. The second allowable range 84 is set on the peripheral side of the chip 2 and on the gate reference position PG side from the second well reference position PW2. In this case, at least a portion of the cathode region 80 is disposed within a range not exceeding half the second reference distance Db from the second well reference position PW2.

[0163] When the cathode region 80 is positioned in both the region on the first well reference position PW1 side and the region on the second well reference position PW2 side, the prohibited range 82 is set to a range not exceeding 1 / 2 the first reference distance Da from the gate reference position PG to the first well reference position PW1 side, and a range not exceeding 1 / 2 the second reference distance Db from the gate reference position PG to the second well connection electrode 59 side.

[0164] On the other hand, the first allowable range 83 is set within a range not exceeding half the distance of the first reference distance Da with respect to the first well reference position PW1. The first allowable range 83 is set toward the IGBT region 6 and the gate reference position PG with respect to the first well reference position PW1. On the other hand, the second allowable range 84 is set within a range not exceeding half the distance of the second reference distance Db with respect to the second well reference position PW2. The second allowable range 84 is set toward the periphery of the chip 2 and the gate reference position PG with respect to the second well reference position PW2.

[0165] The first reference distance Da may be 1 μm or more and 50 μm or less. The first reference distance Da may be set to a value belonging to any of the following ranges: 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or more and 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or more and 45 μm or more and 50 μm or less. The first reference distance Da is preferably 10 μm or more and 30 μm or less. The first reference distance Da is particularly preferably 10 μm or more and 20 μm or less.

[0166] The second reference distance Db may be less than the first reference distance Da or may be greater than or equal to the first reference distance Da. In this embodiment, the second reference distance Db is greater than the first reference distance Da. The second reference distance Db may be 1 μm or greater and 100 μm or less. The second reference distance Db may be set to a value belonging to any of the following ranges: 1 μm or greater and 5 μm or less, 5 μm or greater and 10 μm or less, 10 μm or greater and 20 μm or less, 20 μm or greater and 30 μm or less, 30 μm or greater and 40 μm or less, 40 μm or greater and 50 μm or less, 50 μm or greater and 60 μm or less, 60 μm or greater and 70 μm or less, 70 μm or greater and 80 μm or less, 80 μm or greater and 90 μm or less, and 90 μm or greater and 100 μm or less. The second reference distance Db is preferably 10 μm or greater and 60 μm or less. It is particularly preferable that the second reference distance Db be 20 μm or more and 40 μm or less.

[0167] 14C is a graph illustrating a second setting example of the prohibited range 82, the first allowed range 83, and the second allowed range 84 based on the results of FIG. 14A . Referring to FIG. 14C , the forward current IF takes a first maximum value v1 when the cathode region 80 is located at the first well reference position PW1. The forward current IF takes a second maximum value v3 when the cathode region 80 is located at the second well reference position PW2. The forward current IF takes a value near the minimum value v2 when the cathode region 80 is located near the intermediate reference position PW3, which is immediately below the middle between the first well reference position PW1 and the second well reference position PW2.

[0168] When the cathode region 80 was positioned near the midpoint between the first well reference position PW1 and the midpoint PW3, the forward current IF took a value near the midpoint between the first maximum value v1 and the minimum value v2 (a value near the first inflection point v4).When the cathode region 80 was positioned near the midpoint between the second well reference position PW2 and the midpoint PW3, the forward current IF took a value near the midpoint between the second maximum value v3 and the minimum value v2 (a value near the second inflection point v5).

[0169] For the above reasons, the prohibited range 82, the first allowed range 83, and the second allowed range 84 may be set based on the third reference distance Dc between the first well reference position PW1 and the second well reference position PW2. The third reference distance Dc is also the sum of the first reference distance Da and the second reference distance Db (Dc = Da + Db) shown in FIG. 14B . That is, in the second setting example, the prohibited range 82, the first allowed range 83, and the second allowed range 84 are set based on the third reference distance Dc without using the first reference distance Da and the second reference distance Db.

[0170] In this case, the prohibited range 82 may be set to a range not exceeding a distance of ¼ of the third reference distance Dc from an intermediate reference position PW3 immediately below the middle between the first well reference position PW1 and the second well reference position PW2. When the cathode region 80 is disposed in an area on the first well reference position PW1 side, the prohibited range 82 is set on the first well reference position PW1 side with reference to the intermediate reference position PW3. When the cathode region 80 is disposed in an area on the second well reference position PW2 side, the prohibited range 82 is set on the second well reference position PW2 side with reference to the intermediate reference position PW3.

[0171] On the other hand, the first allowable range 83 is set within a range not exceeding one-quarter of the third reference distance Dc with respect to the first well reference position PW1. The first allowable range 83 is set toward the IGBT region 6 and the gate reference position PG with respect to the first well reference position PW1. On the other hand, the second allowable range 84 is set within a range not exceeding one-quarter of the third reference distance Dc with respect to the second well reference position PW2. The second allowable range 84 is set toward the IGBT region 6 and the gate reference position PG with respect to the second well reference position PW2.

[0172] 14B and 14C , the cathode region 80 is preferably disposed in a region outside the prohibited range 82. With this structure, a current detouring path is suppressed in the region between the first well-connecting electrode 58 and the second well-connecting electrode 59, thereby suppressing a decrease in the forward current I F .

[0173] When the cathode region 80 is disposed in a region on the first well reference position PW1 side, it is preferable that a part or the entirety of the cathode region 80 be disposed within the first allowable range 83. With this structure, the current path between the first well connection electrode 58 and the cathode region 80 is shortened, thereby increasing the forward current IF. In this case, it is preferable that the cathode region 80 be disposed at the first well reference position PW1. With this structure, a current path that linearly connects the first well connection electrode 58 and the cathode region 80 is formed, thereby making it possible to appropriately increase the forward current IF.

[0174] When the cathode region 80 is disposed in a region on the second well reference position PW2 side, it is preferable that a part or the entirety of the cathode region 80 be disposed within the second allowable range 84. With this structure, the current path between the second well connection electrode 59 and the cathode region 80 is shortened, thereby increasing the forward current IF. In this case, it is preferable that the cathode region 80 be disposed at the second well reference position PW2. With this structure, a current path that linearly connects the second well connection electrode 59 and the cathode region 80 is formed, thereby making it possible to appropriately increase the forward current IF.

[0175] 15 is a graph showing the relationship between the peak surge current IFSM and the forward voltage VF when the location of the cathode region 80 is adjusted. In FIG. 15, the vertical axis represents the peak surge current IFSM [A], and the horizontal axis represents the forward voltage VF [V]. The peak surge current IFSM is the peak value of the commercial limit half-wave current (50 Hz or 60 Hz) for one cycle or more that is permissible without causing breakdown.

[0176] 15 shows first to sixth plot points P1 to P6. The first to third plot points P1 to P3 show the characteristics when the cathode region 80 is arranged at a distance from the well region 31 towards the periphery of the chip 2. The locations of the cathode regions 80 approach the well region 31 in the order of the first plot point P1, the second plot point P2, and the third plot point P3.

[0177] The fourth to sixth plot points P4 to P6 show the characteristics when the cathode region 80 is arranged in a position facing the well region 31. The locations of the cathode region 80 approach the second well reference position PW2 from the outer edge 31b side of the well region 31 in the order of the fourth plot point P4, the fifth plot point P5, and the sixth plot point P6. The sixth plot point P6 shows the characteristics when the cathode region 80 is arranged at the second well reference position PW2. At the first to sixth plot points P1 to P6, the width of the cathode region 80 is fixed to a constant value (10 μm in this case).

[0178] With reference to the first to sixth plot points P1 to P6, the peak surge currents IFSM associated with the first to third plot points P1 to P3 were higher than the peak surge currents IFSM associated with the fourth to sixth plot points P4 to P6. The peak surge current IFSM associated with the sixth plot point P6 was also higher than the peak surge currents IFSM associated with the first to fifth plot points P1 to P5. Therefore, it was found that it is preferable to arrange the cathode region 80 in a region immediately below the well region 31. It was also found that it is preferable to arrange the cathode region 80 at the second well reference position PW2.

[0179] 5 to 7 , the semiconductor device 1 may include, as the cathode region 80, a cathode region 80A according to a first layout example formed in consideration of the above-described measurement results. The cathode region 80A is formed at a distance from the gate reference position PG along the second main surface 4. Specifically, the cathode region 80A is arranged at a distance from the gate reference position PG toward the second well reference position PW2 along the second main surface 4.

[0180] The cathode region 80A is located in the second allowed range 84 and is not located in the prohibited range 82. Here, the prohibited range 82 and the second allowed range 84 according to the first setting example or the second setting example may be applied. The cathode region 80A is located at the second well reference position PW2 and faces the plurality of second well connection electrodes 59 in the thickness direction of the chip 2. The cathode region 80A is located at a distance from the gate line electrode 62 toward the second well reference position PW2 so as not to face the gate line electrode 62 in the thickness direction of the chip 2.

[0181] The cathode region 80A is arranged at a distance from a position directly below the center of the gate line wiring 45 toward the second well reference position PW2. The cathode region 80A is arranged at a distance from a position directly below the plurality of gate connection electrodes 53 toward the second well reference position PW2 so as not to face the plurality of gate connection electrodes 53 in the thickness direction of the chip 2. The cathode region 80A is arranged at a distance from the gate line wiring 45 toward the second well reference position PW2 so as not to face the gate line wiring 45 in the thickness direction of the chip 2.

[0182] The cathode region 80A has a width less than that of the emitter line electrode 67. Of course, the cathode region 80A may have a width equal to or greater than that of the emitter line electrode 67. The cathode region 80A is formed at a distance from a position directly below the outer edge 31b of the well region 31 toward the second well reference position PW2. The cathode region 80A is formed only in a region of the surface layer portion of the second main surface 4 that faces the well region 31 in the thickness direction of the chip 2.

[0183] 16 is a cross-sectional view showing the cross-sectional structure of the peripheral portion of the chip 2 together with the cathode region 80B according to the second layout example. Referring to FIG. 16, the semiconductor device 1 may include the cathode region 80B according to the second layout example as the cathode region 80. The cathode region 80B is formed at a distance from the gate reference position PG along the second main surface 4. Specifically, the cathode region 80B is arranged at a distance from the gate reference position PG toward the first well reference position PW1 along the second main surface 4.

[0184] The cathode region 80B is located in the first allowed range 83 and is not located in the prohibited range 82. Here, the prohibited range 82 and the second allowed range 84 according to the first setting example or the second setting example may be applied. The cathode region 80B is located at the first well reference position PW1 and faces the multiple first well connection electrodes 58 in the thickness direction of the chip 2. The cathode region 80B is located at a distance from the gate line electrode 62 toward the first well reference position PW1 so as not to face the gate line electrode 62 in the thickness direction of the chip 2.

[0185] The cathode region 80B is arranged at a distance from a position directly below the center of the gate line wiring 45 toward the first well reference position PW1. The cathode region 80B is arranged at a distance from a position directly below the plurality of gate connection electrodes 53 toward the first well reference position PW1 so as not to face the plurality of gate connection electrodes 53 in the thickness direction of the chip 2. The cathode region 80B is arranged at a distance from the gate line wiring 45 toward the first well reference position PW1 so as not to face the gate line wiring 45 in the thickness direction of the chip 2.

[0186] It is preferable that the cathode region 80B is formed at a distance from a position directly below the inner edge 31a of the well region 31 toward the first well reference position PW1, regardless of the first allowable range 83. In other words, the cathode region 80B is formed only in a region in the surface layer portion of the second main surface 4 that faces the well region 31 in the thickness direction of the chip 2.

[0187] Furthermore, the cathode region 80B is preferably formed at a distance from the plurality of trench gate structures 18 on the peripheral side of the second main surface 4 so as not to face the plurality of trench gate structures 18 in the thickness direction of the chip 2. It is particularly preferable that the cathode region 80B is formed at a distance from the trench isolation structure 12 on the peripheral side of the second main surface 4 so as not to face the trench isolation structure 12 in the thickness direction of the chip 2.

[0188] That is, it is preferable that the cathode region 80B is formed at a distance from the IGBT region 6 toward the peripheral edge of the chip 2 so as not to face the IGBT region 6 in the thickness direction of the chip 2. That is, it is preferable that the cathode region 80B is formed only in the outer peripheral region 8, and not in the IGBT region 6. In this case, it is possible to suppress the electrical influence from the IGBT region 6 to the diode 81, and to suppress the electrical influence from the diode 81 to the IGBT region 6.

[0189] 17 is a cross-sectional view showing the cross-sectional structure of the peripheral portion of the chip 2 together with a cathode region 80C according to the third layout example. Referring to FIG. 17 , the semiconductor device 1 may include a cathode region 80C according to the third layout example as the cathode region 80. The cathode region 80C includes a first cathode region 80C1 disposed on the first well reference position PW1 side and a second cathode region 80C2 disposed on the second well reference position PW2 side, spaced apart from the first cathode region 80C1.

[0190] The first cathode region 80C1 is formed in the same layout as the cathode region 80 according to the second layout example (see FIG. 16 ). The second cathode region 80C2 is formed in the same layout as the cathode region 80 according to the first layout example (see FIG. 5 ). The second cathode region 80C2 faces the first cathode region 80C1 in the surface layer portion of the second main surface 4, with part of the collector region 11 sandwiched therebetween.

[0191] A part of the collector region 11 faces the gate line wiring 45, the gate connection electrode 53, and the gate line electrode 62 in the thickness direction of the chip 2. It is preferable that a part of the collector region 11 faces the entire gate line electrode 62 in the thickness direction of the chip 2. It is preferable that a part of the collector region 11 faces the entire gate line wiring 45 in the thickness direction of the chip 2.

[0192] 18 is a cross-sectional view showing the cross-sectional structure of the peripheral portion of chip 2 together with cathode region 80D according to the fourth layout example. Referring to Fig. 18, semiconductor device 1 may include cathode region 80D according to the fourth layout example as cathode region 80. Cathode region 80D has an opposing portion 85 opposing well region 31 in the thickness direction of chip 2, and a cathode extraction portion 86 extracted from opposing portion 85 toward the peripheral edge of chip 2.

[0193] The facing portion 85 is arranged at a distance from the gate reference position PG toward the second well reference position PW2 along the second main surface 4. The facing portion 85 is arranged in the second allowed range 84 and is not arranged in the prohibited range 82. Here, the prohibited range 82 and the second allowed range 84 according to the first setting example or the second setting example may be applied.

[0194] The facing portion 85 is disposed at the second well reference position PW2, and faces the plurality of second well connection electrodes 59 in the thickness direction of the chip 2. The facing portion 85 is disposed at a distance from the gate line electrode 62 toward the second well reference position PW2 so as not to face the gate line electrode 62 in the thickness direction of the chip 2.

[0195] The facing portion 85 is arranged at a distance from a position directly below the center of the gate line wiring 45 toward the second well reference position PW2. The facing portion 85 is arranged at a distance from a position directly below the center of the plurality of gate connection electrodes 53 toward the second well reference position PW2 so as not to face the plurality of gate connection electrodes 53 in the thickness direction of the chip 2. The facing portion 85 is arranged at a distance from the gate line wiring 45 toward the second well reference position PW2 so as not to face the gate line wiring 45 in the thickness direction of the chip 2.

[0196] The cathode lead-out portion 86 is led out from the facing portion 85 to the peripheral edge side of the chip 2, crossing a position directly below the outer edge 31b of the well region 31. The cathode lead-out portion 86 is formed at a distance from the multiple field regions 32 (the innermost field region 32) toward the well region 31 so as not to face the multiple field regions 32 in the thickness direction of the chip 2. The cathode region 80D may have a width less than the width of the emitter line electrode 67, or may have a width greater than or equal to the width of the emitter line electrode 67.

[0197] 19 is a cross-sectional view showing the cross-sectional structure of the peripheral portion of chip 2 together with cathode region 80E according to the fifth layout example. Referring to Fig. 19, semiconductor device 1 may include cathode region 80E according to the fifth layout example as cathode region 80. Cathode region 80E has a modified form of cathode region 80D according to the fourth layout example described above.

[0198] Specifically, cathode region 80E includes a cathode lead-out portion 86 that faces at least one field region 32 (at least the innermost field region 32) in the thickness direction of chip 2. Cathode lead-out portion 86 is formed at a distance from the region directly below the outermost field region 32 (field electrode 72) toward well region 31 so as not to face the outermost field region 32 (field electrode 72) in the thickness direction of chip 2.

[0199] The cathode region 80E may have a width less than the width of the emitter line electrode 67, or may have a width equal to or greater than the width of the emitter line electrode 67. The cathode region 80E may have a width less than the width of the well region 31, or may have a width equal to or greater than the width of the well region 31. The cathode region 80E according to the fifth layout example may be applied to the first cathode region 80C1 according to the third layout example.

[0200] 20 is a cross-sectional view showing the cross-sectional structure of the peripheral portion of the chip 2 together with the cathode region 80F according to the sixth layout example. Referring to Fig. 20, the semiconductor device 1 may include the cathode region 80F according to the sixth layout example as the cathode region 80. The cathode region 80F has a modified form of the cathode region 80E according to the fifth layout example.

[0201] Specifically, the cathode region 80F includes a cathode lead-out portion 86 that faces all of the field regions 32 (field electrodes 72) in the thickness direction of the chip 2. The cathode lead-out portion 86 is formed at a distance from the region directly below the channel stop region 33 toward the well region 31 so as not to face the channel stop region 33 in the thickness direction of the chip 2. The cathode lead-out portion 86 does not face the channel stop electrode 74 either.

[0202] The cathode region 80F may have a width equal to or greater than the width of the emitter line electrode 67. The cathode region 80F may have a width equal to or greater than the width of the well region 31. The cathode region 80F according to the sixth layout example may be applied to the first cathode region 80C1 according to the third layout example.

[0203] As described above, the semiconductor device 1 includes the chip 2, the IGBT region 6, the peripheral region 8, the p-type well region 31, the insulating film 40, the well connection electrode 57, and the n-type cathode region 80. The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The IGBT region 6 is provided in an inner portion of the first main surface 3. The peripheral region 8 is provided on the periphery of the chip 2. The well region 31 is formed in a surface layer portion of the first main surface 3 in the peripheral region 8 so as to define the IGBT region 6.

[0204] The insulating film 40 covers the well region 31. The well connection electrode 57 is embedded in the insulating film 40 so as to be connected to the well region 31. The cathode region 80 is formed in the surface layer of the second main surface 4 in the peripheral region 8 so as to face the well connection electrode 57, and constitutes a diode 81 together with the well region 31. This structure allows the formation of a current path that linearly connects the well connection electrode 57 and the cathode region 80. This makes it possible to increase the forward current IF of the diode 81 during forward operation. Therefore, it is possible to provide a semiconductor device 1 that can improve electrical characteristics.

[0205] The semiconductor device 1 preferably includes a gate line electrode 62 disposed on the insulating film 40 at a distance from the well-connecting electrode 57 so as to face the well region 31. In this case, the cathode region 80 is preferably formed along the second main surface 4 at a distance from a position directly below the center of the gate line electrode 62.

[0206] This structure can prevent a current from detouring into the region immediately below the gate line electrode 62 in the region between the well connection electrode 57 and the cathode region 80. Therefore, it is preferable that the cathode region 80 does not face the gate line electrode 62. This structure can appropriately prevent a current from detouring into the region immediately below the gate line electrode 62.

[0207] The well connection electrode 57 may include either or both of a first well connection electrode 58 arranged on the inner edge 31a side of the well region 31 and a second well connection electrode 59 arranged on the outer edge 31b side of the well region 31.

[0208] When the well connection electrode 57 includes the first well connection electrode 58, the gate line electrode 62 is disposed at a distance from the first well connection electrode 58 toward the outer edge 31b of the well region 31 (toward the periphery of the chip 2). In this case, the cathode region 80 is formed at a distance from a position directly below the center of the gate line electrode 62 toward the inner edge 31a of the well region 31 (toward the IGBT region 6) along the second main surface 4. This structure makes it possible to form a current path that linearly connects the first well connection electrode 58 and the cathode region 80.

[0209] In this case, the semiconductor device 1 preferably includes an emitter pad electrode 66. The emitter pad electrode 66 is disposed on the insulating film 40 at a distance from the gate line electrode 62 toward the IGBT region 6 so as to be electrically connected to the well region 31 via the first well connection electrode 58. The cathode region 80 faces the emitter pad electrode 66 in the thickness direction of the chip 2. This structure allows the formation of a current path that linearly connects the emitter pad electrode 66 and the cathode region 80.

[0210] When the well connection electrode 57 includes the second well connection electrode 59, the gate line electrode 62 may be disposed at a distance from the second well connection electrode 59 toward the inner edge 31 a of the well region 31 (toward the IGBT region 6). In this case, the cathode region 80 may be formed at a distance from a position directly below the center of the gate line electrode 62 toward the outer edge 31 b of the well region 31 (toward the periphery of the chip 2) along the second main surface 4. This structure allows the formation of a current path that linearly connects the second well connection electrode 59 and the cathode region 80.

[0211] In this case, the semiconductor device 1 preferably includes an emitter line electrode 67. The emitter line electrode 67 is arranged on the insulating film 40 at a distance from the gate line electrode 62 toward the periphery of the chip 2 so as to be electrically connected to the well region 31 via the second well connection electrode 59. The cathode region 80 also faces the emitter line electrode 67. This structure allows the formation of a current path that linearly connects the emitter line electrode 67 and the cathode region 80. The emitter line electrode 67 may be arranged only in the region facing the well region 31.

[0212] The semiconductor device 1 may include a gate line wiring 45 and a gate connecting electrode 53. The gate line wiring 45 is disposed inside the insulating film 40 so as to face the well region 31. The gate connecting electrode 53 is embedded in the insulating film 40 so as to be connected to the gate line wiring 45. In this case, the gate line electrode 62 is electrically connected to the gate line wiring 45 via the gate connecting electrode 53.

[0213] In this structure, the cathode region 80 is preferably formed at a distance along the second main surface 4 from a position directly below the center of the gate line wiring 45. This structure can prevent a current from detouring into the region directly below the gate line wiring 45. In this case, it is preferable that the cathode region 80 does not face the gate connection electrode 53. It is also preferable that the cathode region 80 does not face the gate line wiring 45. These structures can appropriately prevent a current from detouring into the region directly below the gate line wiring 45. The gate line electrode 62 may be formed narrower than the gate line wiring 45.

[0214] The cathode region 80 is preferably formed only in the surface layer portion of the second main surface 4 in a region facing the well region 31. With this structure, the current path of the forward current IF can be reliably limited to the region between the well region 31 and the cathode region 80. Therefore, a decrease in the forward current IF can be appropriately suppressed. Furthermore, with this structure, the peak surge current IFSM can also be improved.

[0215] Of course, the cathode region 80 may include an opposing portion 85 opposing the well region 31 and a cathode extraction portion 86 extracted from the opposing portion 85 toward the peripheral edge of the chip 2. Even with this structure, a current path is formed that linearly connects the well connection electrode 57 and the cathode region 80, thereby suppressing a decrease in the forward current IF. Furthermore, this structure can also improve the peak surge current IFSM.

[0216] The semiconductor device 1 may include a p-type field region 32 formed in the surface layer portion of the first main surface 3 of the peripheral region 8 at a distance from the well region 31 toward the periphery of the chip 2. In this case, the cathode lead-out portion 86 may be formed so as not to face the field region 32, or may be formed so as to face the field region 32.

[0217] The semiconductor device 1 may include an n-type channel stop region 33 formed in the surface layer portion of the first main surface 3 of the peripheral region 8 at a distance from the field region 32 toward the peripheral edge of the chip 2. In this case, it is preferable that the cathode lead-out portion 86 is formed so as not to face the channel stop region 33.

[0218] From another perspective, the semiconductor device 1 includes a chip 2, an IGBT region 6, a peripheral region 8, a well region 31, an insulating film 40, a well connection electrode 57, a gate line electrode 62, and a cathode region 80. The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The IGBT region 6 is provided in an inner portion of the first main surface 3. The peripheral region 8 is provided in a peripheral portion of the chip 2. The well region 31 is formed in a surface layer portion of the first main surface 3 in the peripheral region 8 so as to define the IGBT region 6.

[0219] The insulating film 40 covers the well region 31. The well-connecting electrode 57 is embedded in the insulating film 40 so as to be connected to the well region 31. The gate line electrode 62 is disposed on the insulating film 40 at a distance from the well-connecting electrode 57 so as to face the well region 31.

[0220] The cathode region 80 is formed in the surface layer portion of the second main surface 4 so as to face the well region 31, and forms a diode 81 together with the well region 31. The cathode region 80 is arranged along the second main surface 4 at an interval from the gate reference position PG directly below the center of the gate line electrode 62 toward the well connection electrode 57.

[0221] This structure can prevent a current from detouring into the region directly below the gate line electrode 62 in the region between the well connection electrode 57 and the cathode region 80, and can also shorten the current path between the well connection electrode 57 and the cathode region 80. This increases the forward current IF of the diode 81 during forward operation. This makes it possible to provide a semiconductor device 1 with improved electrical characteristics.

[0222] The well connection electrode 57 may include either or both of a first well connection electrode 58 arranged on the inner edge 31a side of the well region 31 and a second well connection electrode 59 arranged on the outer edge 31b side of the well region 31.

[0223] When the well-connecting electrode 57 includes the first well-connecting electrode 58, it is preferable that the cathode region 80 is not disposed in a range (prohibited range 82) that does not exceed half the distance from the gate reference position PG of the first reference distance Da, where Da is the distance between the center of the gate line electrode 62 and the first well-connecting electrode 58. This structure appropriately suppresses a current detouring path that goes around to the region directly below the gate line electrode 62, thereby increasing the forward current IF.

[0224] When the distance between the center of the gate line electrode 62 and the well connecting electrode 57 is defined as a first reference distance Da, the cathode region 80 preferably has a portion that is located in a range (first allowable range 83) that does not exceed half the distance of the first reference distance Da from the first well reference position PW1 directly below the first well connecting electrode 58. With this structure, the forward current IF can be appropriately increased.

[0225] Therefore, it is particularly preferable that the cathode region 80 has a portion located in a range (first allowed range 83) not exceeding 1 / 2 of the first reference distance Da from the first well reference position PW1, and is not located in a range (prohibited range 82) not exceeding 1 / 2 of the first reference distance Da from the gate reference position PG.

[0226] When the well-connecting electrode 57 includes the second well-connecting electrode 59, it is preferable that the cathode region 80 is not disposed in a range (prohibited range 82) that does not exceed half the distance from the gate reference position PG of the second reference distance Db, where Db is the distance between the center of the gate line electrode 62 and the second well-connecting electrode 59. This structure appropriately suppresses a current detouring path that goes around to the region directly below the gate line electrode 62, thereby increasing the forward current IF.

[0227] When the distance between the center of the gate line electrode 62 and the well connecting electrode 57 is defined as a second reference distance Db, the cathode region 80 preferably has a portion that is located in a range (second allowable range 84) that does not exceed half the distance of the second reference distance Db from the second well reference position PW2 immediately below the second well connecting electrode 59. With this structure, the forward current IF can be increased appropriately.

[0228] Therefore, it is particularly preferable that the cathode region 80 has a portion located in a range (second allowed range 84) not exceeding 1 / 2 the second reference distance Db from the second well reference position PW2, and not located in a range (prohibited range 82) not exceeding 1 / 2 the second reference distance Db from the gate reference position PG.

[0229] From another perspective, the semiconductor device 1 includes a chip 2, an IGBT region 6, a peripheral region 8, a well region 31, an insulating film 40, a first well connection electrode 58, a second well connection electrode 59, and a cathode region 80. The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The IGBT region 6 is provided in an inner portion of the first main surface 3. The peripheral region 8 is provided in a peripheral portion of the chip 2. The well region 31 is formed in a surface layer portion of the first main surface 3 in the peripheral region 8 so as to define the IGBT region 6. The insulating film 40 covers the well region 31.

[0230] The first well connection electrode 58 is buried in the insulating film 40 so as to be connected to the well region 31. The second well connection electrode 59 is buried in the insulating film 40 at a distance from the first well connection electrode 58 towards the periphery of the chip 2 so as to be connected to the well region 31. The cathode region 80 is formed in the surface layer portion of the second main surface 4 so as to face the well region 31, and forms a diode 81 together with the well region 31. The cathode region 80 is formed at a distance along the second main surface 4 from an intermediate reference position PW3 immediately below the middle between the first well connection electrode 58 and the second well connection electrode 59.

[0231] This structure can prevent a current from detouring into the region immediately below the middle between the first well-connecting electrode 58 and the second well-connecting electrode 59. This can increase the forward current IF of the diode 81 during forward operation. This can provide a semiconductor device 1 with improved electrical characteristics.

[0232] In this case, when the distance between the first well-connecting electrode 58 and the second well-connecting electrode 59 is defined as a third reference distance Dc, the cathode region 80 is preferably not disposed in a range (prohibited range 82) that does not exceed ¼ of the distance from the intermediate reference position PW3. This structure makes it possible to appropriately suppress a current detouring path that goes around to a region immediately below the intermediate position between the first well-connecting electrode 58 and the second well-connecting electrode 59.

[0233] The cathode region 80 may be disposed at a distance from the position of the intermediate reference position PW3 toward the first well connection electrode 58. This structure shortens the current path between the first well connection electrode 58 and the cathode region 80, thereby increasing the forward current IF.

[0234] In this case, when the distance between the first well connection electrode 58 and the second well connection electrode 59 is the third reference distance Dc, it is preferable that the cathode region 80 has a portion that is located within a range (first allowable range 83) that does not exceed 1 / 4 of the third reference distance Dc from the first well reference position PW1 directly below the first well connection electrode 58.

[0235] This structure shortens the current path between the first well connecting electrode 58 and the cathode region 80, thereby appropriately increasing the forward current IF. Therefore, it is preferable that the cathode region 80 has a portion that overlaps with the first well reference position PW1. This structure allows the formation of a current path that linearly connects the first well connecting electrode 58 and the cathode region 80, thereby appropriately increasing the forward current IF.

[0236] The cathode region 80 may be disposed at a distance from the position of the intermediate reference position PW3 toward the second well connection electrode 59. This structure shortens the current path between the second well connection electrode 59 and the cathode region 80, thereby increasing the forward current IF.

[0237] In this case, when the distance between the first well connection electrode 58 and the second well connection electrode 59 is the third reference distance Dc, it is preferable that the cathode region 80 has a portion that is located within a range (second allowable range 84) that does not exceed 1 / 4 of the third reference distance Dc from the second well reference position PW2 directly below the second well connection electrode 59.

[0238] This structure shortens the current path between the second well connecting electrode 59 and the cathode region 80, thereby appropriately increasing the forward current IF. Therefore, it is preferable that the cathode region 80 has a portion that overlaps with the second well reference position PW2. This structure allows the formation of a current path that linearly connects the second well connecting electrode 59 and the cathode region 80, thereby appropriately increasing the forward current IF.

[0239] The above-described embodiment can be implemented in further other forms. In the above-described embodiment, an example was shown in which the multiple emitter connecting electrodes 51 were separate from the emitter pad electrode 66 (emitter electrode 65). However, the multiple emitter connecting electrodes 51 may be formed by utilizing a portion of the emitter pad electrode 66. In other words, the emitter pad electrode 66 may be disposed on the insulating film 40 so as to extend into the multiple emitter openings 50. In this case, the multiple portions of the emitter pad electrode 66 located within the multiple emitter openings 50 are formed as the multiple emitter connecting electrodes 51.

[0240] In the above-described embodiment, an example has been shown in which the multiple gate connection electrodes 53 are separate from the gate electrode 60 (gate line electrode 62). However, the multiple gate connection electrodes 53 may be formed by utilizing a portion of the gate electrode 60. In other words, the gate electrode 60 may be disposed on the insulating film 40 so as to extend into the multiple gate openings 52. In this case, multiple portions of the gate electrode 60 located within the multiple gate openings 52 are formed as the multiple gate connection electrodes 53.

[0241] In the above-described embodiment, an example has been shown in which the plurality of first well connecting electrodes 58 are separate from the emitter pad electrode 66 (emitter electrode 65). However, the plurality of first well connecting electrodes 58 may be formed by utilizing a portion of the emitter pad electrode 66. In other words, the emitter pad electrode 66 may be disposed on the insulating film 40 so as to extend into the plurality of first well openings 55. In this case, the plurality of portions of the emitter pad electrode 66 located within the plurality of first well connecting electrodes 58 are formed as the plurality of first well connecting electrodes 58.

[0242] In the above-described embodiment, an example has been shown in which the plurality of second well connecting electrodes 59 are separate from the emitter line electrode 67 (emitter electrode 65). However, the plurality of second well connecting electrodes 59 may be formed by utilizing a portion of the emitter line electrode 67. In other words, the emitter line electrode 67 may be disposed on the insulating film 40 so as to extend into the plurality of second well openings 56. In this case, the plurality of portions of the emitter line electrode 67 located within the plurality of second well openings 56 are formed as the plurality of second well connecting electrodes 59.

[0243] In the above-described embodiment, an example has been shown in which the multiple field connection electrodes 71 are separate from the field electrode 72. However, the multiple field connection electrodes 71 may be formed by using a portion of the field electrode 72. In other words, the field electrode 72 may be disposed on the insulating film 40 so as to extend into the multiple field openings 70. In this case, the multiple portions of the field electrode 72 located within the multiple field openings 70 are formed as the multiple field connection electrodes 71.

[0244] In the above-described embodiments, the chip 2 is made of a silicon single crystal substrate. However, the chip 2 may be made of a wide bandgap semiconductor single crystal substrate. For example, the chip 2 may be made of a silicon carbide (SiC) single crystal substrate, a GaN single crystal substrate, or the like.

[0245] In the above-described embodiments, the n-type semiconductor regions may be replaced with p-type semiconductor regions, and the p-type semiconductor regions may be replaced with n-type semiconductor regions. A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings.

[0246] In the above-described embodiment, the first direction X and the second direction Y are defined by the extending directions of the first to fourth side surfaces 5A to 5D. However, the first direction X and the second direction Y may be any directions as long as they maintain a mutually intersecting (specifically, perpendicular) relationship. For example, the first direction X may be a direction intersecting the first to fourth side surfaces 5A to 5D, and the second direction Y may be a direction intersecting the first to fourth side surfaces 5A to 5D.

[0247] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following clauses may be replaced with a "semiconductor switching device" or an "RC-IGBT semiconductor device."

[0248] [A1] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, an IGBT region (6) provided in the inner part of the first main surface (3), an outer peripheral region (8) provided on the periphery of the first main surface (3), a first conductivity type (p-type) well region (31) formed in the surface layer part of the first main surface (3) in the outer peripheral region (8) so as to partition the IGBT region (6), and an insulating film covering the well region (31). a film (40); well-connecting electrodes (57, 58, 59) embedded in the insulating film (40) so as to be connected to the well region (31); and cathode regions (80, 80A-80F) of a second conductivity type (n-type) formed in a surface layer portion of the second main surface (4) in the peripheral region (8) so as to face the well-connecting electrodes (57, 58, 59), and constituting a diode (81) together with the well region (31).

[0249] [A2] The semiconductor device (1) according to A1, further comprising a gate electrode (62) arranged on the insulating film (40) at a distance from the well connection electrode (57, 58, 59) so as to face the well region (31).

[0250] [A3] The semiconductor device (1) according to A2, wherein the cathode regions (80, 80A to 80F) are formed at intervals along the second main surface (4) from a position directly below the center of the gate electrode (62).

[0251] [A4] The semiconductor device (1) according to A2 or A3, wherein the gate electrode (62) is disposed at a distance from the well connection electrode (57, 58, 59) toward the IGBT region (6).

[0252] [A5] The semiconductor device (1) described in A4, wherein the cathode regions (80, 80A to 80F) are formed at intervals along the second main surface (4) from a position directly below the center of the gate electrode (62) to the peripheral edge side of the chip (2).

[0253] [A6] The semiconductor device (1) according to A4 or A5 further includes an emitter electrode (67) arranged on the insulating film (40) at a distance from the gate electrode (62) toward the peripheral edge of the chip (2) and electrically connected to the well region (31) via the well connection electrode (57, 58, 59), and the cathode region (80, 80A-80F) faces the emitter electrode (67).

[0254] [A7] The semiconductor device (1) according to A6, wherein the emitter electrode (67) is disposed only in a region facing the well region (31) in a cross-sectional view.

[0255] [A8] The semiconductor device (1) according to A2 or A3, wherein the gate electrode (62) is arranged at a distance from the well connection electrode (57, 58, 59) toward the periphery of the chip (2).

[0256] [A9] The semiconductor device (1) described in A8, wherein the cathode regions (80, 80A to 80F) are formed at intervals along the second main surface (4) from a position directly below the center of the gate electrode (62) toward the IGBT region (6).

[0257] [A10] The semiconductor device (1) according to A8 or A9, further comprising an emitter pad electrode (66) arranged on the insulating film (40) at a distance from the gate electrode (62) toward the IGBT region (6) so as to be electrically connected to the well region (31) via the well connection electrode (57, 58, 59), and the cathode region (80, 80A-80F) faces the emitter pad electrode (66).

[0258] [A11] The semiconductor device (1) according to any one of A2 to A10, wherein the cathode region (80, 80A to 80F) does not face the gate electrode (62).

[0259] [A12] The semiconductor device (1) according to any one of A2 to A11, further comprising: a gate wiring (45) arranged inside the insulating film (40) so as to face the well region (31); and a gate connection electrode (53) embedded in the insulating film (40) so as to be connected to the gate wiring (45), wherein the gate electrode (62) is electrically connected to the gate wiring (45) via the gate connection electrode (53).

[0260] [A13] The semiconductor device (1) according to A12, wherein the cathode regions (80, 80A to 80F) are formed at intervals along the second main surface (4) from a position directly below the center of the gate wiring (45).

[0261] [A14] The semiconductor device (1) according to A12 or A13, wherein the cathode region (80, 80A to 80F) does not face the gate connection electrode (53).

[0262] [A15] The semiconductor device (1) according to any one of A12 to A14, wherein the cathode region (80, 80A to 80F) does not face the gate wiring (45).

[0263] [A16] The semiconductor device (1) according to any one of A12 to A15, wherein the gate electrode (62) is formed narrower than the gate wiring (45).

[0264] [A17] A semiconductor device (1) according to any one of A1 to A16, wherein the cathode region (80, 80A-80F) is formed only in a region facing the well region (31) in the surface layer portion of the second main surface (4).

[0265] [A18] A semiconductor device (1) according to any one of A1 to A16, wherein the cathode region (80, 80A-80F) includes an opposing portion (85) opposing the well region (31), and an extraction portion (86) extracted from the opposing portion (85) toward the periphery of the chip (2).

[0266] [A19] A semiconductor device (1) described in A18, further including a field region (32) of a first conductivity type (p-type) formed in the surface layer portion of the first main surface (3) at a distance from the well region (31) toward the periphery of the chip (2) in the peripheral region (8), and the lead-out portion (86) does not face the field region (32).

[0267] [A20] A semiconductor device (1) described in A18, further including a field region (32) of a first conductivity type (p-type) formed in the surface layer portion of the first main surface (3) at a distance from the well region (31) toward the periphery of the chip (2) in the peripheral region (8), and the lead-out portion (86) faces the field region (32).

[0268] [A21] The semiconductor device (1) according to any one of A1 to A20, further comprising a base region (17) of a first conductivity type (p-type) formed in a surface layer portion of the first main surface (3) in the IGBT region (6).

[0269] [A22] The semiconductor device (1) according to A21, wherein the cathode region does not face the base region (17).

[0270] [A23] The semiconductor device (1) according to A21 or A22, wherein the well region (31) is deeper than the base region (17).

[0271] [A24] A semiconductor device (1) according to any one of A21 to A23, wherein the well region (31) is drawn out from the outer peripheral region (8) to the IGBT region (6) and has a portion connected to the base region (17).

[0272] [A25] The semiconductor device (1) according to any one of A1 to A24, further comprising a trench gate structure (18) formed on the first main surface (3) in the IGBT region (6).

[0273] [A26] The semiconductor device (1) according to A25, wherein the cathode region does not face the trench gate structure (18).

[0274] [A27] A semiconductor device (1) described in A25 or A26, wherein the well region (31) is extended from the outer peripheral region (8) to the IGBT region (6) and has a portion covering the bottom wall of the trench gate structure (18).

[0275] [B1] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, an IGBT region (6) provided in an inner portion of the first main surface (3), an outer peripheral region (8) provided on the periphery of the first main surface (3), a well region (31) of a first conductivity type (p-type) formed in a surface layer portion of the first main surface (3) in the outer peripheral region (8) so as to partition the IGBT region (6), an insulating film (40) covering the well region (31), and well connection electrodes (57, 58, 59) embedded in the insulating film (40) so as to be connected to the well region (31), The semiconductor device (1) includes: a gate electrode (62) arranged on the insulating film (40) at a distance from the well-connecting electrode (57, 58, 59) so as to face the well region (31); and a cathode region (80, 80A-80F) of a second conductivity type (n-type) formed along the second main surface (4) at a distance from a gate reference position (PG) directly below the center of the gate electrode (62) toward the well-connecting electrode (57, 58, 59) so as to face the well region (31) in a surface layer portion of the second main surface (4), and constituting a diode (81) with the well region (31).

[0276] [B2] The semiconductor device (1) according to B1, wherein when the distance between the center of the gate electrode (62) and the well connection electrode (57, 58, 59) is defined as a reference distance (Da, Db), the cathode region (80, 80A-80F) is not disposed in a range (82) that does not exceed 1 / 2 of the reference distance (Da, Db) from the gate reference position (PG) toward the well connection electrode (57, 58, 59).

[0277] [B3] The semiconductor device (1) according to B1, wherein when the distance between the center of the gate electrode (62) and the well connection electrode (57, 58, 59) is defined as a reference distance (Da, Db), the cathode region (80, 80A-80F) has a portion disposed within a range (83, 84) not exceeding ½ of the reference distance (Da, Db) from a well reference position (PW1, PW2) directly below the well connection electrode (57, 58, 59).

[0278] [B4] The semiconductor device (1) described in B3, wherein the cathode region (80, 80A to 80F) is not disposed within a range (82) from the gate reference position (PG) toward the well connection electrode (57, 58, 59) that does not exceed 1 / 2 of the reference distance (Da, Db).

[0279] [B5] The semiconductor device (1) according to any one of B1 to B4, wherein the cathode region (80, 80A to 80F) has a portion facing the well-connecting electrode (57, 58, 59).

[0280] [B6] The semiconductor device (1) according to any one of B1 to B5, wherein the cathode region (80, 80A to 80F) does not face the gate electrode (62).

[0281] [B7] The semiconductor device (1) according to any one of B1 to B6, wherein the gate electrode (62) is arranged at a distance from the well connection electrode (57, 58, 59) toward the IGBT region (6), and the cathode region (80, 80A-80F) is arranged at a distance from the gate reference position (PG) toward the well connection electrode (57, 58, 59) along the second main surface (4).

[0282] [B8] The semiconductor device (1) according to B7, wherein the cathode region (80, 80A to 80F) is formed only in a region facing the well region (31) in a surface layer portion of the second main surface (4).

[0283] [B9] The semiconductor device (1) described in B7, wherein the cathode region (80, 80A to 80F) includes an opposing portion (85) facing the well region (31), and an extension portion (86) extended from the opposing portion (85) toward the periphery of the chip (2).

[0284] [B10] The semiconductor device (1) described in B9 further includes a field region (32) of a first conductivity type (p-type) formed in the surface layer portion of the first main surface (3) at a distance from the well region (31) toward the periphery of the chip (2) in the peripheral region (8), and the lead-out portion (86) does not face the field region (32).

[0285] [B11] The semiconductor device (1) described in B9 further includes a field region (32) of a first conductivity type (p-type) formed in the surface layer portion of the first main surface (3) at a distance from the well region (31) toward the periphery of the chip (2) in the peripheral region (8), and the lead-out portion (86) faces the field region (32).

[0286] [B12] A semiconductor device (1) according to B11, further comprising a channel stop region (33) of a second conductivity type (n-type) formed in the surface layer portion of the first main surface (3) at a distance from the field region (32) toward the periphery of the chip (2) in the peripheral region (8), and the lead-out portion (86) does not face the channel stop region (33).

[0287] [B13] The semiconductor device (1) according to any one of B7 to B12, further comprising an emitter electrode (67) arranged on the insulating film (40) so as to be electrically connected to the well region (31) via the well connection electrode (57, 58, 59).

[0288] [B14] A semiconductor device (1) according to any one of B1 to B6, wherein the gate electrode (62) is arranged at a distance from the well connection electrode (57, 58, 59) on the peripheral side of the chip (2), and the cathode region (80, 80A-80F) is arranged at a distance from the gate reference position (PG) on the IGBT region (6) side along the second main surface (4).

[0289] [B15] The semiconductor device (1) according to B14, wherein the cathode region (80, 80A to 80F) is formed only in a region facing the well region (31) in a surface layer portion of the second main surface (4).

[0290] [B16] The semiconductor device (1) according to B14 or B15, further comprising an emitter pad electrode (66) arranged on the insulating film (40) so as to be electrically connected to the well region (31) via the well connection electrode (57, 58, 59).

[0291] [B17] The semiconductor device (1) according to any one of B1 to B16, further comprising: a gate wiring (45) arranged inside the insulating film (40) so as to face the well region (31); and a gate connection electrode (53) embedded in the insulating film (40) so as to be connected to the gate wiring (45), wherein the gate electrode (62) is electrically connected to the gate wiring (45) via the gate connection electrode (53).

[0292] [B18] The semiconductor device (1) according to B17, wherein the cathode region (80, 80A to 80F) does not face the gate connection electrode (53).

[0293] [B19] The semiconductor device (1) according to B17 or B18, wherein the cathode region (80, 80A to 80F) does not face the gate wiring (45).

[0294] [B20] The semiconductor device (1) according to any one of B1 to B19, further comprising a collector region (11) of a first conductivity type (p-type) formed in a surface layer portion of the second main surface (4), and the cathode region (80) has a second conductivity type impurity concentration higher than the first conductivity type impurity concentration of the collector region (11).

[0295] [B21] The semiconductor device (1) according to any one of B1 to B20, further comprising a base region (17) of a first conductivity type (p-type) formed in a surface layer portion of the first main surface (3) in the IGBT region (6).

[0296] [B22] The semiconductor device (1) according to B21, wherein the cathode region does not face the base region (17).

[0297] [B23] The semiconductor device (1) according to B21 or B22, wherein the well region (31) is deeper than the base region (17).

[0298] [B24] A semiconductor device (1) according to any one of B21 to B23, wherein the well region (31) is drawn out from the peripheral region (8) to the IGBT region (6) and has a portion connected to the base region (17).

[0299] [B25] The semiconductor device (1) according to any one of B1 to B24, further comprising a trench gate structure (18) formed on the first main surface (3) in the IGBT region (6).

[0300] [B26] The semiconductor device (1) according to B25, wherein the cathode region does not face the trench gate structure (18).

[0301] [B27] A semiconductor device (1) according to B25 or B26, wherein the well region (31) is extended from the peripheral region (8) to the IGBT region (6) and has a portion covering the bottom wall of the trench gate structure (18).

[0302] [C1] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, an IGBT region (6) provided in an inner portion of the first main surface (3), an outer peripheral region (8) provided on the periphery of the first main surface (3), a well region (31) of a first conductivity type (p-type) formed in a surface layer portion of the first main surface (3) in the outer peripheral region (8) so as to partition the IGBT region (6), an insulating film (40) covering the well region (31), a first well connection electrode (58) buried in the insulating film (40) so as to be connected to the well region (31), and a well region (31) a second well connection electrode (59) embedded in the insulating film (40) at a distance from the first well connection electrode (58) toward the periphery of the chip (2) so as to be connected to the first well connection electrode (58); and a cathode region (80, 80A-80F) of a second conductivity type (n-type) that is formed at a distance along the second main surface (4) from an intermediate reference position (PW3) immediately below the middle between the first well connection electrode (58) and the second well connection electrode (59) so as to face the well region (31) in a surface layer portion of the second main surface (4), and that forms a diode (81) with the well region (31).

[0303] [C2] The semiconductor device (1) described in C1, wherein when the distance between the first well connection electrode (58) and the second well connection electrode (59) is a reference distance (Dc), the cathode region (80, 80A to 80F) is not positioned in a range (82) that does not exceed 1 / 4 of the reference distance (Dc) from the intermediate reference position (PW3).

[0304] [C3] The semiconductor device (1) according to C1, wherein the cathode region (80, 80A to 80F) is arranged at an interval from the intermediate reference position (PW3) toward the first well connection electrode (58).

[0305] [C4] When the distance between the first well connection electrode (58) and the second well connection electrode (59) is taken as a reference distance (Dc), the cathode region (80, 80A to 80F) is not positioned in a range (82) from the intermediate reference position (PW3) toward the first well connection electrode (58) that does not exceed 1 / 4 of the reference distance (Dc).

[0306] [C5] When the distance between the first well connection electrode (58) and the second well connection electrode (59) is taken as a reference distance (Dc), the cathode region (80, 80A to 80F) has a portion arranged in a range (83) not exceeding 1 / 4 of the reference distance (Dc) from a first well reference position (PW1) directly below the first well connection electrode (58) toward the intermediate reference position (PW3).

[0307] [C6] The semiconductor device (1) described in C5, wherein the cathode region (80, 80A to 80F) is not positioned within a range (82) from the intermediate reference position (PW3) toward the first well connection electrode (58) that does not exceed 1 / 4 of the reference distance (Dc).

[0308] [C7] The semiconductor device (1) according to any one of C3 to C6, wherein the cathode region (80, 80A to 80F) faces the first well connection electrode (58).

[0309] [C8] The semiconductor device (1) according to C1, wherein the cathode region (80, 80A to 80F) is arranged at an interval from the intermediate reference position (PW3) toward the second well connection electrode (59).

[0310] [C9] The semiconductor device (1) described in C8, wherein when the distance between the first well connection electrode (58) and the second well connection electrode (59) is defined as a reference distance (Dc), the cathode region (80, 80A-80F) is not positioned within a range (82) from the intermediate reference position (PW3) toward the second well connection electrode (59) that does not exceed 1 / 4 of the reference distance (Dc).

[0311] [C10] When the distance between the first well connection electrode (58) and the second well connection electrode (59) is taken as a reference distance (Dc), the cathode region (80, 80A to 80F) has a portion arranged in a range (84) not exceeding 1 / 4 of the reference distance (Dc) from a second well reference position (PW2) directly below the second well connection electrode (59) toward the intermediate reference position (PW3).

[0312] [C11] The semiconductor device (1) described in C10, wherein the cathode region (80, 80A to 80F) is not positioned within a range (82) from the intermediate reference position (PW3) toward the second well connection electrode (59) that does not exceed 1 / 4 of the reference distance (Dc).

[0313] [C12] The semiconductor device (1) according to any one of C8 to C11, wherein the cathode region (80, 80A to 80F) faces the second well connection electrode (59).

[0314] [C13] The semiconductor device (1) described in C1, wherein the cathode region (80, 80A to 80F) includes a first cathode region (80C1) formed at a distance from the intermediate reference position (PW3) toward the first well connection electrode (58), and a second cathode region (80C2) formed at a distance from the intermediate reference position (PW3) toward the second well connection electrode (59).

[0315] [C14] When the distance between the first well connection electrode (58) and the second well connection electrode (59) is a reference distance (Dc), the first cathode region (80C1) is not positioned in a range (82) from the intermediate reference position (PW3) toward the first well connection electrode (58) that does not exceed 1 / 4 of the reference distance (Dc).

[0316] [C15] When the distance between the first well connection electrode (58) and the second well connection electrode (59) is a reference distance (Dc), the first cathode region (80C1) has a portion arranged in a range (83) not exceeding 1 / 4 of the reference distance (Dc) from a first well reference position (PW1) directly below the first well connection electrode (58) toward the intermediate reference position (PW3).

[0317] [C16] The semiconductor device (1) described in C15, wherein the first cathode region (80C1) is not positioned within a range (82) from the intermediate reference position (PW3) toward the first well connection electrode (58) that does not exceed 1 / 4 of the reference distance (Dc).

[0318] [C17] A semiconductor device (1) according to C16, wherein when the distance between the first well connection electrode (58) and the second well connection electrode (59) is a reference distance (Dc), the second cathode region (80C2) is not positioned within a range (82) from the intermediate reference position (PW3) toward the second well connection electrode (59) that does not exceed 1 / 4 of the reference distance (Dc).

[0319] [C18] When the distance between the first well connection electrode (58) and the second well connection electrode (59) is a reference distance (Dc), the second cathode region (80C2) has a portion arranged in a range (84) not exceeding 1 / 4 of the reference distance (Dc) from a second well reference position (PW2) directly below the second well connection electrode (59) toward the intermediate reference position (PW3).

[0320] [C19] The semiconductor device (1) described in C18, wherein the second well connection electrode (59) is not positioned within a range (82) from the intermediate reference position (PW3) toward the second well connection electrode (59) that does not exceed 1 / 4 of the reference distance (Dc).

[0321] [C20] The semiconductor device (1) according to any one of C1 to C19, further comprising an emitter pad electrode (66) arranged on the insulating film (40) so as to be electrically connected to the well region (31) via the first well connection electrode (58).

[0322] [C21] The semiconductor device (1) according to any one of C1 to C20, further comprising an emitter electrode (67) arranged on the insulating film (40) so as to be electrically connected to the well region (31) via the second well connection electrode (59).

[0323] [C22] A semiconductor device (1) according to any one of C1 to C21, further comprising a gate electrode (62) arranged on the insulating film (40) in a region between the first well connection electrode (58) and the second well connection electrode (59) so as to face the well region (31), and the cathode region (80, 80A-80F) is formed at a distance along the second main surface (4) from a gate reference position (PG) directly below the center of the gate electrode (62).

[0324] [C23] The semiconductor device (1) according to any one of C1 to C21, further comprising a gate wiring (45) arranged inside the insulating film (40) so as to face the well region (31), the first well connection electrode (58) being embedded in the insulating film (40) at a distance from the gate wiring (45) toward the IGBT region (6), the second well connection electrode (59) being embedded in the insulating film (40) at a distance from the gate wiring (45) toward the periphery of the chip (2), and the cathode region (80, 80A-80F) being formed at a distance along the second main surface (4) from a gate reference position (PG) directly below the center of the gate wiring (45).

[0325] [C24] The semiconductor device (1) described in C23 further includes: a gate connection electrode (53) embedded in the insulating film (40) so as to be connected to the gate wiring (45); and a gate electrode (62) arranged on the insulating film (40) in a region between the first well connection electrode (58) and the second well connection electrode (59) so as to be electrically connected to the gate wiring (45) via the gate connection electrode (53).

[0326] [C25] The semiconductor device (1) according to any one of C1 to C24, further comprising a collector region (11) of a first conductivity type (p-type) formed in a surface layer portion of the second main surface (4), and the cathode region (80) has a second conductivity type impurity concentration higher than the first conductivity type impurity concentration of the collector region (11).

[0327] [C26] A semiconductor device (1) according to any one of C1 to C25, further comprising a base region (17) of a first conductivity type (p-type) formed in a surface layer portion of the first main surface (3) in the IGBT region (6).

[0328] [C27] The semiconductor device (1) according to C26, wherein the cathode region does not face the base region (17).

[0329] [C28] The semiconductor device (1) according to C26 or C27, wherein the well region (31) is deeper than the base region (17).

[0330] [C29] A semiconductor device (1) according to any one of C26 to C28, wherein the well region (31) is drawn from the peripheral region (8) to the IGBT region (6) and has a portion connected to the base region (17).

[0331] [C30] The semiconductor device (1) according to any one of C1 to C29, further comprising a trench gate structure (18) formed on the first main surface (3) in the IGBT region (6).

[0332] [C31] The semiconductor device (1) according to C30, wherein the cathode region does not face the trench gate structure (18).

[0333] [C32] A semiconductor device (1) according to C30 or C31, wherein the well region (31) is extended from the peripheral region (8) to the IGBT region (6) and has a portion covering the bottom wall of the trench gate structure (18).

[0334] [D1] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, an IGBT region (6) provided in the inner part of the first main surface (3), an outer peripheral region (8) provided on the periphery of the first main surface (3), a well region (31) of a first conductivity type (p-type) formed in a surface layer part of the first main surface (3) in the outer peripheral region (8) so as to partition the IGBT region (6), an insulating film (40) covering the well region (31), and a dielectric film (40) connected to the well region (31). a well connection electrode (57, 58) buried in the insulating film (40); an emitter pad electrode (66) arranged on the insulating film (40) so as to be electrically connected to the well region (31) via the well connection electrode (57, 58); and a cathode region (80, 80A-80F) of a second conductivity type (n-type) formed in a surface layer portion of the second main surface (4) in the outer peripheral region (8) so as to face the well connection electrode (57, 58), and constituting a diode (81) with the well region (31).

[0335] [D2] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, an IGBT region (6) provided in the inner part of the first main surface (3), an outer peripheral region (8) provided on the periphery of the first main surface (3), a well region (31) of a first conductivity type (p-type) formed in the surface layer part of the first main surface (3) in the outer peripheral region (8) so as to partition the IGBT region (6), an insulating film (40) covering the well region (31), and a dielectric film (40) connected to the well region (31). a well connection electrode (57, 59) buried in the insulating film (40); an emitter electrode (67) arranged on the insulating film (40) so as to be electrically connected to the well region (31) via the well connection electrode (57, 59); and a cathode region (80, 80A-80F) of a second conductivity type (n-type) formed in a surface layer portion of the second main surface (4) in the outer peripheral region (8) so as to face the well connection electrode (57, 59), and constituting a diode (81) with the well region (31).

[0336] [D3] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, an IGBT region (6) provided in the inner part of the first main surface (3), an outer peripheral region (8) provided on the periphery of the first main surface (3), a well region (31) of a first conductivity type (p-type) formed in the surface layer part of the first main surface (3) in the outer peripheral region (8) so as to partition the IGBT region (6), an insulating film (40) covering the well region (31), a first well connection electrode (58) buried in the insulating film (40) so as to be connected to the well region (31), and a line extending from the first well connection electrode (58) to the chip (2) so as to be connected to the well region (31). a second well connection electrode (59) embedded in the insulating film (40) at a distance from the periphery of the well region (31); a gate electrode (62) arranged in a region between the first well connection electrode (58) and the second well connection electrode (59) on the insulating film (40) so as to face the well region (31); and a cathode region (80, 80A-80F) of a second conductivity type (n-type) arranged at a distance from a gate reference position (PG) directly below the center of the gate electrode (62) along the second main surface (4) so ​​as to face the well region (31) in a surface layer portion of the second main surface (4), and constituting a diode (81) with the well region (31).

[0337] [D4] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, an IGBT region (6) provided in an inner portion of the first main surface (3), an outer peripheral region (8) provided on the periphery of the first main surface (3), a well region (31) of a first conductivity type (p-type) formed in a surface layer portion of the first main surface (3) in the outer peripheral region (8) so as to partition the IGBT region (6), an insulating film (40) covering the well region (31), a gate wiring (45) arranged inside the insulating film (40) so as to face the well region (31), and a wiring (45) extending from the gate wiring (45) to the IGBT so as to be connected to the well region (31). The semiconductor device (1) includes: a first well connection electrode (58) embedded in the insulating film (40) at a distance on the region (6) side; a second well connection electrode (59) embedded in the insulating film (40) at a distance from the gate wiring (45) on the peripheral edge side of the chip (2) so as to be connected to the well region (31); and a cathode region (80, 80A-80F) of a second conductivity type (n-type) that is arranged at a distance along the second main surface (4) from a gate reference position (PG) directly below the center of the gate wiring (45) so as to face the well region (31) in a surface layer portion of the second main surface (4), and that forms a diode (81) with the well region (31).

[0338] Although the embodiments have been described in detail above, these are merely specific examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiments.

[0339] REFERENCE SIGNS LIST 1 semiconductor device 2 chip 3 first main surface 4 second main surface 6 IGBT region 8 peripheral region 11 collector region 17 base region 18 trench gate structure 31 well region 32 field region 33 channel stop region 40 insulating film 45 gate line wiring 53 gate connection electrode 57 well connection electrode 58 first well connection electrode 59 second well connection electrode 62 gate line electrode 66 emitter pad electrode 67 emitter line electrode 80 cathode region 80A cathode region 80B cathode region 80C cathode region 80C1 first cathode region 80C2 second cathode region 80D cathode region 80E cathode region 80F cathode region 81 diode 85 facing portion 86 cathode lead-out portion Da first reference distance Db first reference distance Dc Third reference distance PG Gate reference position PW1 First well reference position PW2 Second well reference position

Claims

1. a chip having a first major surface on one side and a second major surface on the other side; an IGBT region provided in an inner portion of the first main surface; An outer peripheral region provided on a peripheral portion of the first main surface; a well region of a first conductivity type formed in a surface layer portion of the first main surface in the outer circumferential region so as to partition the IGBT region; an insulating film covering the well region; a well connection electrode embedded in the insulating film so as to be connected to the well region; a cathode region of a second conductivity type formed in a surface layer portion of the second main surface in the outer circumferential region so as to face the well connection electrode, the cathode region constituting a diode together with the well region.

2. 2. The semiconductor device according to claim 1, further comprising a gate electrode arranged on said insulating film at a distance from said well connection electrode so as to face said well region.

3. 3. The semiconductor device according to claim 2, wherein said cathode region is formed along said second main surface at a distance from a position directly below a center of said gate electrode.

4. 3. The semiconductor device according to claim 2, wherein said gate electrode is disposed on a side of said IGBT region away from said well connecting electrode.

5. 5. The semiconductor device according to claim 4, wherein said cathode region is formed along said second main surface at intervals from a position directly under a center of said gate electrode toward a peripheral edge of said chip.

6. an emitter electrode disposed on the insulating film at a distance from the gate electrode toward the periphery of the chip, the emitter electrode being electrically connected to the well region via the well connection electrode; 5. The semiconductor device according to claim 4, wherein said cathode region faces said emitter electrode.

7. 7. The semiconductor device according to claim 6, wherein said emitter electrode is disposed only in a region facing said well region in a cross-sectional view.

8. 3. The semiconductor device according to claim 2, wherein said gate electrode is disposed at a distance from said well connection electrode toward a periphery of said chip.

9. 9. The semiconductor device according to claim 8, wherein said cathode region is formed along said second main surface at an interval from a position directly under a center of said gate electrode toward said IGBT region.

10. an emitter pad electrode is disposed on the insulating film at a distance from the gate electrode toward the IGBT region, and is electrically connected to the well region via the well connection electrode; 9. The semiconductor device according to claim 8, wherein said cathode region faces said emitter pad electrode.

11. The semiconductor device according to claim 2 , wherein said cathode region does not face said gate electrode.

12. a gate wiring disposed inside the insulating film so as to face the well region; a gate connection electrode embedded in the insulating film so as to be connected to the gate wiring; The semiconductor device according to claim 2 , wherein the gate electrode is electrically connected to the gate wiring via the gate connection electrode.

13. The semiconductor device according to claim 12 , wherein the cathode region is formed along the second main surface at an interval from a position directly below a center of the gate wiring.

14. The semiconductor device according to claim 12 , wherein the cathode region does not face the gate connection electrode.

15. The semiconductor device according to claim 12 , wherein the cathode region does not face the gate wiring.

16. The semiconductor device according to claim 12 , wherein the gate electrode is formed to be narrower than the gate wiring.

17. 17. The semiconductor device according to claim 1, wherein the cathode region is formed only in a region facing the well region in a surface layer portion of the second main surface.

18. 17. The semiconductor device according to claim 1, wherein the cathode region includes an opposing portion opposing the well region, and an extended portion extended from the opposing portion toward a periphery of the chip.

19. a field region of a first conductivity type formed in a surface layer portion of the first main surface at a distance from the well region toward a periphery of the chip in the outer periphery region, The semiconductor device according to claim 18 , wherein the lead portion does not face the field region.

20. a field region of a first conductivity type formed in a surface layer portion of the first main surface at a distance from the well region toward a periphery of the chip in the outer periphery region, The semiconductor device according to claim 18 , wherein the lead portion faces the field region.