Sic semiconductor device

Abstract

This SiC semiconductor device (1A) contains: a chip (2) which contains an SiC monocrystal and has a main surface (3); a trench structure (20) which has side walls (21, 22) and a bottom wall (23) and is formed in the main surface; and a first conductive contact region (50) which contains a first region (51) that is formed in a region extending along the side walls in a surface layer portion of the main surface, and a second region (52) that is formed in a region extending along the bottom wall in the chip and has an impurity concentration lower than the impurity concentration of the first region.

Description

SiC semiconductor device

[0001] This application claims priority from Japanese Patent Application No. 2022-061145 filed on March 31, 2022, the entire content of which is incorporated herein by reference. The present invention relates to a SiC semiconductor device.

[0002] FIG. 8 of Patent Document 1 discloses a SiC vertical power MOSFET including an n-type drift layer, a trench structure formed in the n-type drift layer, and a high-concentration p-type base region formed in the n-type drift layer in a region along the bottom wall of the trench structure.

[0003] US Patent Application Publication No. 2014 / 0145209

[0004] One embodiment provides a semiconductor device capable of improving electrical characteristics.

[0005] One embodiment provides a SiC semiconductor device including: a chip including a SiC single crystal and having a main surface; a trench structure having sidewalls and a bottom wall and formed in the main surface; a first region formed in a surface portion of the main surface in a region along the sidewall; and a first conductivity type contact region including a second region formed within the chip in a region along the bottom wall and having an impurity concentration lower than the impurity concentration of the first region.

[0006] One embodiment provides a SiC semiconductor device including a chip including a SiC single crystal and having a main surface; a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface; a body region of a second conductivity type formed in a surface layer portion of the semiconductor region; a trench source structure having sidewalls and a bottom wall and formed in the main surface to penetrate the body region; a trench gate structure formed in the main surface to penetrate the body region and spaced apart from the trench source structure; a source region of the first conductivity type formed in a region along the trench gate structure in the surface layer portion of the body region; a first region formed in a region along the sidewall of the trench source structure in the surface layer portion of the body region; and a contact region of the first conductivity type formed in the chip in a region along the bottom wall of the trench source structure, the contact region including a second region having an impurity concentration lower than the impurity concentration of the first region.

[0007] The above and other objects, features, and advantages will become apparent from the following description of the embodiments with reference to the accompanying drawings.

[0008] FIG. 1 is a plan view showing a SiC semiconductor device according to a first embodiment. FIG. 2 is a plan view showing a layout of a first main surface. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 is an enlarged plan view showing a main portion of the first main surface. FIG. 5 is an enlarged plan view showing another main portion of the first main surface. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5. FIG. 8 is an enlarged plan view showing a region including a second trench structure and a third trench structure. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 8. FIG. 10 is a cross-sectional view taken along line XX in FIG. 8. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 8. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 8. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 8. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 8. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 8 . FIG. 16A is an enlarged cross-sectional view showing a configuration in which a region including the second trench structure and the contact region is cut in the m-axis direction. FIG. 16B is an enlarged cross-sectional view showing a configuration in which a region including the second trench structure and the contact region is cut in the a-axis direction. FIG. 17 is a cross-sectional view showing a peripheral portion of a chip. FIG. 18 is a plan view showing a SiC semiconductor device according to a second embodiment. FIG. 19 is a plan view showing a SiC semiconductor device according to a third embodiment. FIG. 20 is a plan view showing a SiC semiconductor device according to a fourth embodiment. FIG. 21 is a plan view showing a SiC semiconductor device according to a fifth embodiment. FIG. 22 is a plan view showing a SiC semiconductor device according to a sixth embodiment. FIG. 23 is a plan view showing a SiC semiconductor device according to a seventh embodiment. FIG. 24 is a plan view showing a SiC semiconductor device according to an eighth embodiment. FIG. 25 is a plan view showing a SiC semiconductor device according to a ninth embodiment. FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 25 . Fig. 27 is a cross-sectional view taken along line XXVII-XXVII in Fig. 25. Fig. 28A is an enlarged cross-sectional view showing the configuration when a region including the second trench structure and the contact region is cut in the m-axis direction. Fig. 28B is an enlarged cross-sectional view showing the configuration when a region including the second trench structure and the contact region is cut in the a-axis direction.Fig. 29 is a plan view showing a SiC semiconductor device according to the tenth embodiment. Fig. 30 is a plan view showing a SiC semiconductor device according to the eleventh embodiment. Fig. 31 is a plan view showing a SiC semiconductor device according to the twelfth embodiment. Fig. 32 is a plan view showing a SiC semiconductor device according to the thirteenth embodiment. Fig. 33 is a plan view showing a SiC semiconductor device according to the fourteenth embodiment. Fig. 34 is a plan view showing a SiC semiconductor device according to the fifteenth embodiment. Fig. 35 is a cross-sectional view showing a modified example of the second trench structure.

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When the phrase "substantially equal" is used in a description in which a comparison target is present, this phrase includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not attached with the intent of limiting the names of each structure.

[0011] FIG. 1 is a plan view showing a SiC semiconductor device 1A according to a first embodiment. FIG. 2 is a plan view showing the layout of a first main surface 3. FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. 2. FIG. 4 is an enlarged plan view showing a main portion of the first main surface 3. FIG. 5 is an enlarged plan view showing another main portion of the first main surface 3. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 5.

[0012] Fig. 8 is an enlarged plan view showing a region including the second trench structure 20 and the third trench structure 30. Fig. 9 is a cross-sectional view taken along line IX-IX shown in Fig. 8. Fig. 10 is a cross-sectional view taken along line XX shown in Fig. 8. Fig. 11 is a cross-sectional view taken along line XI-XI shown in Fig. 8. Fig. 12 is a cross-sectional view taken along line XII-XII shown in Fig. 8. Fig. 13 is a cross-sectional view taken along line XIII-XIII shown in Fig. 8.

[0013] 14 is a cross-sectional view taken along line XIV-XIV in FIG. 8. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 8. FIG. 16A is an enlarged cross-sectional view showing the configuration when a region including the second trench structure 20 and the contact region 50 is cut in the m-axis direction. FIG. 16B is an enlarged cross-sectional view showing the configuration when a region including the second trench structure 20 and the contact region 50 is cut in the a-axis direction. FIG. 17 is a cross-sectional view showing the peripheral portion of the chip 2.

[0014] 1 to 17 , a SiC semiconductor device 1A is a SiC semiconductor switching device including a SiC-MISFET (Metal Insulator Semiconductor Field Effect Transistor). In this embodiment, the SiC semiconductor device 1A includes a chip 2 that includes a hexagonal SiC single crystal and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). The hexagonal SiC single crystal has a plurality of polytypes including a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, a 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may include other polytypes.

[0015] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed by the c-plane of the SiC single crystal. Specifically, the first main surface 3 is formed by the silicon surface ((0001) plane) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) plane) of the SiC single crystal.

[0016] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view (hereinafter simply referred to as "plan view") seen from the c-axis direction (

[0001] direction) of the SiC single crystal. The c-axis direction is the normal direction to the c-plane. The c-axis direction also corresponds to the thickness direction of the chip 2. The first main surface 3 and the second main surface 4 may have an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane.

[0017] The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and not greater than 10°. The off-angle is preferably not greater than 5°. When the first main surface 3 (second main surface 4) has an off-angle, the c-axis is inclined in the off-direction by the amount of the off-angle with respect to the normal to the first main surface 3 (second main surface 4). For convenience, the attached drawings illustrate the c-axis extending along the normal to the first main surface 3 (second main surface 4). The second main surface 4 may be a ground surface having grinding marks, or a smooth surface without grinding marks.

[0018] The first side surface 5A and the second side surface 5B extend in the a-axis direction of the SiC single crystal and face the m-axis direction ([1-100] direction) of the SiC single crystal. That is, the first side surface 5A and the second side surface 5B are formed by the m-plane ((1-100) plane) of the SiC single crystal. The third side surface 5C and the fourth side surface 5D extend in the m-axis direction of the SiC single crystal and face the a-axis direction of the SiC single crystal.

[0019] That is, the third side surface 5C and the fourth side surface 5D are formed by the a-plane ((11-20) plane) of the SiC single crystal. The first to fourth side surfaces 5A to 5D may be ground surfaces having grinding marks, or may be smooth surfaces having no grinding marks. The c-axis direction may be referred to as the "thickness direction," the a-axis direction as the "first direction," and the m-axis direction as the "second direction."

[0020] The chip 2 may have a thickness of 5 μm or more and 350 μm or less. The thickness of the chip 2 may be set to a value belonging to any one of the ranges of 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, and 300 μm or more and 350 μm or less. The thickness of the chip 2 is preferably 150 μm or less.

[0021] The first to fourth side surfaces 5A to 5D may have lengths of 0.5 mm or more and 20 mm or less in plan view. The lengths of the first to fourth side surfaces 5A to 5D may be set to a value belonging to any one of the ranges of 0.5 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The lengths of the first to fourth side surfaces 5A to 5D are preferably 5 mm or more.

[0022] The SiC semiconductor device 1A includes an n-type first semiconductor region 6 formed in a region (surface layer portion) on the first main surface 3 side in the chip 2. The first semiconductor region 6 has a surface area of ​​1.0×10 １５ cm －３ Above 1.0 x 10 １７ cm －３ The first semiconductor region 6 may have the following n-type impurity concentration (maximum value): The first semiconductor region 6 is formed in a layer shape extending along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0023] In this embodiment, the first semiconductor region 6 is made of a SiC epitaxial layer. The first semiconductor region 6 may have a thickness of 1 μm or more and 50 μm or less. The thickness of the first semiconductor region 6 is preferably 5 μm or more and 30 μm or less. The thickness of the first semiconductor region 6 is particularly preferably 25 μm or less.

[0024] The SiC semiconductor device 1A includes an n-type second semiconductor region 7 formed in a region (surface layer portion) on the second main surface 4 side within the chip 2. The second semiconductor region 7 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6 and is electrically connected to the first semiconductor region 6.

[0025] The second semiconductor region 7 is 1.0×10 １８ cm －３ Above 1.0 x 10 ２１ cm －３ The second semiconductor region 7 may have the following n-type impurity concentration (maximum value): In this embodiment, the second semiconductor region 7 is made of a SiC substrate. That is, the chip 2 has a layered structure including a SiC substrate and a SiC epitaxial layer.

[0026] The second semiconductor region 7 may have a thickness of 1 μm or more and 350 μm or less. The thickness of the second semiconductor region 7 is preferably 5 μm or more and 50 μm or less. The thickness of the second semiconductor region 7 is particularly preferably 5 μm or more and 20 μm or less. The thickness of the second semiconductor region 7 is preferably 10 μm or more. The thickness of the second semiconductor region 7 may be greater than the thickness of the first semiconductor region 6. The thickness of the second semiconductor region 7 may be less than the thickness of the first semiconductor region 6.

[0027] The SiC semiconductor device 1A includes an active surface 8, an outer surface 9, and first to fourth connecting surfaces 10A to 10D formed on a first main surface 3. The active surface 8, the outer surface 9, and the first to fourth connecting surfaces 10A to 10D define an active plateau 11 on the first main surface 3. The active surface 8 may be referred to as a "first surface portion," the outer surface 9 may be referred to as a "second surface portion," and the first to fourth connecting surfaces 10A to 10D may be referred to as a "connecting surface portion." The active surface 8, the outer surface 9, and the first to fourth connecting surfaces 10A to 10D (i.e., the active plateau 11) may be considered to be components of the chip 2 (first main surface 3).

[0028] The active surface 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 8 has a flat surface formed by the c-plane (Si-plane). In this embodiment, the active surface 8 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0029] The outer side surface 9 is located outside the active surface 8 and is recessed from the active surface 8 in the thickness direction of the chip 2 (toward the second main surface 4). Specifically, the outer side surface 9 is recessed to a depth less than the thickness of the first semiconductor region 6 so as to expose the first semiconductor region 6. The outer side surface 9 extends in a band shape along the active surface 8 in a plan view and is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8. The outer side surface 9 has a flat surface formed by the c-plane (Si-plane) and is formed approximately parallel to the active surface 8. The outer side surface 9 is continuous with the first to fourth side surfaces 5A to 5D.

[0030] The first to fourth connection surfaces 10A to 10D extend in the c-axis direction and connect the active surface 8 and the outer surface 9. The first connection surface 10A is located on the first side surface 5A side, the second connection surface 10B is located on the second side surface 5B side, the third connection surface 10C is located on the third side surface 5C side, and the fourth connection surface 10D is located on the fourth side surface 5D side.

[0031] The first connecting surface 10A and the second connecting surface 10B extend in the a-axis direction in a plan view and face each other in the m-axis direction. That is, the first side surface 5A and the second side surface 5B are formed by m-planes. The third connecting surface 10C and the fourth connecting surface 10D extend in the m-axis direction in a plan view and face each other in the a-axis direction. That is, the third side surface 5C and the fourth side surface 5D are formed by a-planes.

[0032] The first to fourth connection surfaces 10A to 10D may extend substantially perpendicularly between the active surface 8 and the outer side surface 9 so as to define a quadrangular pillar-shaped active plateau 11. The first to fourth connection surfaces 10A to 10D may be inclined obliquely downward from the active surface 8 toward the outer side surface 9 so as to define a quadrangular pyramid-shaped active plateau 11. In this manner, the SiC semiconductor device 1A includes an active plateau 11 defined in a protruding shape in the first semiconductor region 6 on the first main surface 3. The active plateau 11 is formed only in the first semiconductor region 6, and is not formed in the second semiconductor region 7.

[0033] The SiC semiconductor device 1A includes a p-type body region 12 formed in a surface layer portion of the active surface 8. The body region 12 has a density of 1.0×10 １６ cm －３ Above 1.0 x 10 １９ cm －３ The body region 12 may have the following p-type impurity concentration (maximum value): The body region 12 is formed in a surface layer portion of the first semiconductor region 6 at a distance from the bottom of the first semiconductor region 6 toward the active surface 8, and faces the second semiconductor region 7 with a part of the first semiconductor region 6 in between. The body region 12 is formed in a layer shape extending along the active surface 8. The body region 12 may be exposed from the first to fourth connecting faces 10A to 10D.

[0034] The SiC semiconductor device 1A includes a first trench structure 15 formed in the active surface 8. A gate potential is applied to the first trench structure 15. The first trench structure 15 may also be referred to as a "trench gate wiring structure." The first trench structure 15 penetrates the body region 12 and reaches the first semiconductor region 6. The first trench structure 15 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8, and faces the second semiconductor region 7 with a portion of the first semiconductor region 6 interposed therebetween. The first trench structure 15 preferably has a depth approximately equal to the depth of the outer side surface 9.

[0035] The first trench structure 15 is formed in the peripheral portion of the active surface 8 at a distance from the peripheral edge of the active surface 8 (the first to fourth connecting surfaces 10A to 10D), and extends in a band shape so as to surround the inner portion of the active surface 8. In this embodiment, the first trench structure 15 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connecting surfaces 10A to 10D.

[0036] The first trench structure 15 includes a pad portion 15a and a line portion 15b. The pad portion 15a is disposed on the periphery of the active surface 8 at a distance from the center of the third connecting surface 10C and is formed in a rectangular shape in a plan view. The line portion 15b extends in a strip shape from the pad portion 15a and extends along the periphery of the active surface 8 so as to surround the inner part of the active surface 8. The line portion 15b is formed narrower than the pad portion 15a.

[0037] The first trench structure 15 includes a first trench 16, a first insulating film 17, and a first buried electrode 18. The first trench 16 may be referred to as a "wiring trench," the first insulating film 17 may be referred to as a "wiring insulating film," and the first buried electrode 18 may be referred to as a "wiring buried electrode." The first trench 16 is formed in the active surface 8 and defines the wall surface of the first trench structure 15.

[0038] The first insulating film 17 coats the wall surface of the first trench 16 in a film-like manner. The first insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 17 include a silicon oxide film made of an oxide of the chip 2.

[0039] The first buried electrode 18 is buried in the first trench 16 with the first insulating film 17 sandwiched therebetween. The first buried electrode 18 may protrude above the first main surface 3. The first buried electrode 18 may have a portion that is drawn out from the first trench 16 onto the first main surface 3. The first buried electrode 18 may include conductive polysilicon.

[0040] The SiC semiconductor device 1A includes a plurality of second trench structures 20 formed in the active surface 8. A source potential is applied to the plurality of second trench structures 20. The second trench structures 20 may also be referred to as "trench source structures." The plurality of second trench structures 20 are formed inward of the active surface 8 at intervals from the first trench structures 15. The plurality of second trench structures 20 penetrate the body region 12 and reach the first semiconductor region 6.

[0041] The plurality of second trench structures 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The plurality of second trench structures 20 preferably have a depth approximately equal to that of the first trench structure 15. The plurality of second trench structures 20 preferably have a depth approximately equal to that of the outer side surface 9. The second trench structures 20 are preferably formed narrower than the first trench structures 15.

[0042] The plurality of second trench structures 20 are arranged at intervals in the a-axis direction and the m-axis direction in plan view. The plurality of second trench structures 20 may be arranged in a matrix in plan view. In this case, the SiC semiconductor device 1A includes the plurality of second trench structures 20 arranged at intervals so as to face each other in the a-axis direction and the m-axis direction.

[0043] The multiple second trench structures 20 may be arranged in a staggered pattern in a plan view. In this case, the SiC semiconductor device 1A may include multiple groups of multiple second trench structures 20 arranged in a line at intervals in the a-axis direction and arranged at intervals in the m-axis direction. In this case, the multiple second trench structures 20 belonging to one group are arranged shifted in the a-axis direction so as to face a region (e.g., an intermediate portion) between the multiple second trench structures 20 belonging to the other group in the m-axis direction.

[0044] Of course, the SiC semiconductor device 1A may include a plurality of groups each including a plurality of second trench structures 20 arranged in a line at intervals in the m-axis direction and arranged at intervals in the a-axis direction, in which case the plurality of second trench structures 20 belonging to one group are arranged shifted in the m-axis direction so as to face a region (e.g., an intermediate portion) between the plurality of second trench structures 20 belonging to the other group in the a-axis direction.

[0045] The configuration of one second trench structure 20 will be described below. Referring to FIGS. 8 to 15 , in this embodiment, the second trench structure 20 is formed in a ring shape (specifically, a square ring shape) extending in the a-axis direction and the m-axis direction in plan view. The second trench structure 20 includes an inner wall 21, an outer wall 22, and a bottom wall 23.

[0046] The inner sidewalls 21 form the inner edges of the second trench structures 20 and are formed in a quadrangular shape extending in the a-axis and m-axis directions in plan view. Specifically, the inner sidewalls 21 include a pair of first inner sidewalls 21A and a pair of second inner sidewalls 21B.

[0047] The pair of first inner side walls 21A extend in the a-axis direction and face each other in the m-axis direction. That is, the pair of first inner side walls 21A are defined by m-planes. The pair of second inner side walls 21B extend in the m-axis direction to be connected to the pair of first inner side walls 21A and face each other in the a-axis direction. That is, the pair of second inner side walls 21B are defined by a-planes. The inner side walls 21 define a rectangular first mesa portion 24 on the active surface 8.

[0048] The outer wall 22 forms the outer edge of the second trench structure 20 and surrounds the inner wall 21 in a plan view. The outer wall 22 is formed in a quadrangular shape extending in the a-axis direction and the m-axis direction. Specifically, the outer wall 22 includes a pair of first outer walls 22A and a pair of second outer walls 22B.

[0049] The pair of first outer walls 22A extend in the a-axis direction and face each other in the m-axis direction. That is, the pair of first outer walls 22A are defined by m-planes. The pair of second outer walls 22B extend in the m-axis direction to be connected to the pair of first outer walls 22A and face each other in the a-axis direction. That is, the pair of second outer walls 22B are defined by a-planes.

[0050] The bottom wall 23 connects the inner wall 21 and the outer wall 22 and is formed in a ring shape (specifically, a rectangular ring shape) extending in the a-axis direction and the m-axis direction in plan view. Specifically, the bottom wall 23 includes a pair of first bottom walls 23A and a pair of second bottom walls 23B.

[0051] The pair of first bottom walls 23A extend in a strip-like manner in the a-axis direction. The pair of second bottom walls 23B extend in a strip-like manner in the m-axis direction so as to be connected to the pair of first bottom walls 23A. The bottom walls 23 are formed by the c-plane. When the active surface 8 (first main surface 3) has an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane, the bottom walls 23 may have an off-direction and off-angle similar to the active surface 8 (first main surface 3).

[0052] The second trench structure 20 includes a second trench 25, a second insulating film 26, and a second buried electrode 27. The second trench 25 may be referred to as a "source trench," the second insulating film 26 may be referred to as a "source insulating film," and the second buried electrode 27 may be referred to as a "source buried electrode." The second trench 25 is formed in the active surface 8 and defines the wall surfaces (inner wall 21, outer wall 22, and bottom wall 23) of the second trench structure 20.

[0053] The second insulating film 26 coats the wall surface of the second trench 25 in a film-like manner. The second insulating film 26 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second insulating film 26 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 26 includes a silicon oxide film made of an oxide of the chip 2. The second buried electrode 27 is buried in the second trench 25 with the second insulating film 26 sandwiched therebetween. The second buried electrode 27 may include conductive polysilicon.

[0054] The SiC semiconductor device 1A includes a third trench structure 30 formed in the active surface 8 at a distance from the plurality of second trench structures 20. A gate potential is applied to the third trench structure 30. The third trench structure 30 may also be referred to as a "trench gate structure." The third trench structure 30 penetrates the body region 12 and reaches the first semiconductor region 6.

[0055] The third trench structure 30 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6. The third trench structure 30 preferably has a depth approximately equal to that of the first trench structure 15 (second trench structure 20). The third trench structure 30 preferably has a depth approximately equal to that of the outer side surface 9. The third trench structure 30 is preferably formed narrower than the first trench structure 15. The width of the third trench structure 30 is preferably approximately equal to the width of the second trench structure 20.

[0056] The third trench structure 30 is formed in a lattice shape extending in the a-axis and m-axis directions in the regions between the second trench structures 20 so as to surround the second trench structures 20 in a plan view. In other words, the third trench structure 30 is formed in a ring shape (specifically, a quadrangular ring shape) surrounding each second trench structure 20 in a plan view. The third trench structure 30 defines a plurality of second mesas 31 extending in a ring shape (specifically, a quadrangular ring shape) between itself and the outer walls 22 of the second trench structures 20. The third trench structure 30 is electrically and mechanically connected to the first trench structure 15 at the peripheral portion of the active surface 8.

[0057] Specifically, the third trench structure 30 includes a plurality of third trench structures 30A extending in the a-axis direction and a plurality of third trench structures 30B extending in the m-axis direction. The plurality of third trench structures 30A are formed at intervals in the m-axis direction from the plurality of first outer walls 22A so as to face the plurality of first outer walls 22A in the m-axis direction, and extend in a band-like manner in the a-axis direction through the region between the plurality of first outer walls 22A. The plurality of third trench structures 30A are electrically and mechanically connected to the first trench structure 15 at the peripheral portion of the active surface 8.

[0058] Each third trench structure 30A has a pair of first gate sidewalls 32 extending in the a-axis direction and a first gate bottom wall 33 extending in the a-axis direction. The pair of first gate sidewalls 32 are formed by the m-plane, and the first gate bottom wall 33 is formed by the c-plane. When the active surface 8 (first main surface 3) has an off-angle tilted at a predetermined angle in a predetermined off-direction with respect to the c-plane, the first gate bottom wall 33 may have an off-direction and off-angle similar to the active surface 8 (first main surface 3).

[0059] The plurality of third trench structures 30B are formed at intervals in the a-axis direction from the plurality of second outer walls 22B so as to face the plurality of second outer walls 22B in the a-axis direction, and extend in a band-like manner in the m-axis direction through the region between the plurality of second outer walls 22B. The plurality of third trench structures 30B intersect (specifically, orthogonally) with the plurality of third trench structures 30A in the inner portion of the active surface 8, and together with the plurality of third trench structures 30A, form a plurality of trench intersections 34.

[0060] In this configuration, the trench intersections 34 each form a cross in plan view. When the second trench structures 20 are arranged in a staggered pattern in plan view, the trench intersections 34 each form a T-junction in plan view. The third trench structures 30B are electrically and mechanically connected to the first trench structures 15 at the peripheral portions of the active surface 8.

[0061] Each third trench structure 30B has a pair of second gate sidewalls 35 extending in the m-axis direction and a second gate bottom wall 36 extending in the m-axis direction. The pair of second gate sidewalls 35 are formed of the a-plane, and the second gate bottom wall 36 is formed of the c-plane. When the active surface 8 (first major surface 3) has an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane, the second gate bottom wall 36 may have the same off-direction and off-angle as the active surface 8 (first major surface 3). A trench intersection 34 is formed by the intersection of the first gate bottom wall 33 and the second gate bottom wall 36.

[0062] The third trench structure 30 includes a third trench 37, a third insulating film 38, and a third buried electrode 39. The third trench 37 may be referred to as a "gate trench," the third insulating film 38 may be referred to as a "gate insulating film," and the third buried electrode 39 may be referred to as a "gate buried electrode." The third trench 37 is formed in the active surface 8 and defines the wall surface of the third trench structure 30. The third trench 37 communicates with the first trench 16 at the peripheral portion of the active surface 8.

[0063] The third insulating film 38 coats the wall surface of the third trench 37 in a film-like manner. The third insulating film 38 is connected to the first insulating film 17 at the communicating portion between the first trench 16 and the third trench 37. The third insulating film 38 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the third insulating film 38 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the third insulating film 38 include a silicon oxide film made of an oxide of the chip 2.

[0064] The third buried electrode 39 is buried in the third trench 37 with the third insulating film 38 sandwiched therebetween. The third buried electrode 39 is electrically and mechanically connected to the first buried electrode 18 at the communicating portion between the first trench 16 and the third trench 37. The third buried electrode 39 may include conductive polysilicon.

[0065] The SiC semiconductor device 1A includes a plurality of n-type source regions 40 formed in a region along the third trench structure 30 in a surface layer portion of the body region 12. Specifically, the plurality of source regions 40 are formed in a plurality of second mesas 31 in the surface layer portion of the body region 12. Each source region 40 has a higher n-type impurity concentration than the first semiconductor region 6. The n-type impurity concentration (maximum value) of the source region 40 is 1.0×10 １８ cm －３ Above 1.0 x 10 ２１ cm －３ The plurality of source regions 40 are formed at intervals from the bottom of the body region 12 toward the active surface 8 , and are formed in layers extending along the active surface 8 .

[0066] In this embodiment, each source region 40 is formed in a ring shape (specifically, a square ring shape) extending along the second mesa portion 31 so as to surround each second trench structure 20 in a plan view, and is connected to the second trench structure 20 and the third trench structure 30. Each source region 40 is exposed from the first outer sidewall 22A and the second outer sidewall 22B of the second trench structure 20, and is exposed from the first gate sidewall 32 and the second gate sidewall 35 of the third trench structure 30. Each source region 40, together with the first semiconductor region 6, forms a channel in the body region 12.

[0067] 8 to 15, the SiC semiconductor device 1A includes a plurality of p-type well regions 41 formed in regions along the second trench structures 20 in the chip 2. In this embodiment, the plurality of well regions 41 have a higher p-type impurity concentration than the body region 12. Of course, the plurality of well regions 41 may have a lower p-type impurity concentration than the body region 12. The p-type impurity concentration (maximum value) of the well region 41 is 1.0×10 １６ cm －３ Above 1.0 x 10 １９ cm －３ It may be the following:

[0068] The configuration of one well region 41 will be specifically described below. In this embodiment, the well region 41 includes a well bottom wall portion 42, a first well sidewall portion 43, and a second well sidewall portion 44. The well bottom wall portion 42 may be referred to as the "first well portion," the first well sidewall portion 43 may be referred to as the "second well portion," and the second well sidewall portion 44 may be referred to as the "third well portion."

[0069] The well bottom wall portion 42 is formed in a region along the bottom wall 23 of the second trench structure 20. Specifically, the well bottom wall portion 42 is formed in a region along the pair of first bottom walls 23A and the pair of second bottom walls 23B. The well bottom wall portion 42 is formed in a ring shape (specifically, a square ring shape) extending along the bottom wall 23 of the second trench structure 20 in a plan view, and covers the entire bottom wall 23 of the second trench structure 20. The well bottom wall portion 42 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8, and faces the second semiconductor region 7 with a portion of the first semiconductor region 6 in between.

[0070] The first well sidewall portion 43 is extended from the well bottom wall portion 42 toward the inner sidewall 21 of the second trench structure 20 and is formed in a region along the inner sidewall 21. Specifically, the first well sidewall portion 43 is formed in the first mesa portion 24 in a region along the pair of first inner sidewalls 21A and the pair of second inner sidewalls 21B.

[0071] The first well sidewall 43 is formed in a ring shape (specifically, a square ring shape) extending along the inner wall 21 so as to surround the inner portion of the body region 12 in a plan view. The first well sidewall 43 is connected to the body region 12 at a surface portion of the first mesa 24. The thickness of the first well sidewall 43 measured from the inner wall 21 is smaller than the thickness of the well bottom wall 42 measured from the bottom wall 23.

[0072] The second well sidewall portion 44 is extended from the bottom wall 23 side of the second trench structure 20 to the outer sidewall 22 side of the second trench structure 20, and is formed in a region along the outer sidewall 22. Specifically, the second well sidewall portion 44 is formed in the second mesa portion 31 in a region along the pair of first outer sidewalls 22A and the pair of second outer sidewalls 22B.

[0073] The second well sidewall 44 is formed in the second mesa 31 in a ring shape (specifically, a square ring shape) surrounding the second trench structure 20 at a distance from the third trench structure 30. The second well sidewall 44 is connected to the body region 12 in a surface layer portion of the second mesa 31. The thickness of the second well sidewall 44 measured from the outer wall 22 is smaller than the thickness of the well bottom wall 42 measured from the bottom wall 23.

[0074] 8 to 15, SiC semiconductor device 1A includes a plurality of p-type contact regions 50 formed in regions along the corresponding second trench structures 20 in chip 2. Specifically, the plurality of contact regions 50 are formed in regions along the corresponding second trench structures 20 in the corresponding well regions 41.

[0075] The plurality of contact regions 50 have a higher p-type impurity concentration than the body region 12. The plurality of contact regions 50 have a higher p-type impurity concentration than the well region 41. The p-type impurity concentration (maximum value) of the contact region 50 is 1.0×10 １７ cm －３ Above 1.0 x 10 ２１ cm －３ The contact region 50 preferably contains aluminum (Al) as a p-type impurity.

[0076] The configuration of one contact region 50 will be described in detail below. The contact region 50 includes at least one first region 51 (a plurality of first regions 51 in this embodiment) formed in a surface layer portion of the active surface 8 in the second mesa portion 31. Specifically, the plurality of first regions 51 are formed in a surface layer portion of the body region 12 in the second mesa portion 31. The plurality of first regions 51 are each formed in a region along the outer sidewall 22 of the second trench structure 20. In this embodiment, the plurality of first regions 51 are formed at intervals along the circumferential direction of the outer sidewall 22.

[0077] Specifically, the plurality of first regions 51 include a pair of first regions 51A formed in a region along the pair of first outer walls 22A and a pair of first regions 51B formed in a region along the pair of second outer walls 22B. The pair of first regions 51A are preferably formed narrower in the a-axis direction than the first outer walls 22A. In this embodiment, the pair of first regions 51A are formed narrower in the a-axis direction than the first inner walls 21A.

[0078] The pair of first regions 51A are formed in regions along the pair of first outer walls 22A and spaced apart from the pair of second outer walls 22B in the a-axis direction. The pair of first regions 51A are preferably opposed to each other in the m-axis direction. The pair of first regions 51A are preferably formed in regions along central portions of the pair of first outer walls 22A. Of course, the pair of first regions 51A may be shifted from each other in the a-axis direction so as not to oppose each other in the m-axis direction.

[0079] The width of each first region 51A in the a-axis direction is preferably ½ or less of the width of the first outer wall 22A in the a-axis direction. It is particularly preferably ¼ or less of the width of the first outer wall 22A in the a-axis direction. The width of each first region 51A in the a-axis direction may be 1 / 10 or more of the width of the first outer wall 22A in the a-axis direction.

[0080] The pair of first regions 51B are preferably formed narrower in the m-axis direction than the second outer walls 22B. In this embodiment, the pair of first regions 51B are formed narrower in the m-axis direction than the second inner walls 21B. The pair of first regions 51B are formed in regions along the pair of second outer walls 22B and spaced apart from the pair of first outer walls 22A in the m-axis direction.

[0081] The pair of first regions 51B preferably face each other in the a-axis direction. The pair of first regions 51B are preferably formed in a region along the center of the second outer wall 22B. Of course, the pair of first regions 51B may be shifted from each other in the m-axis direction so as not to face each other in the a-axis direction.

[0082] The width of each first region 51B in the m-axis direction is preferably ½ or less of the width of the second outer wall 22B in the m-axis direction. It is particularly preferably ¼ or less of the width of the second outer wall 22B in the m-axis direction. The width of each first region 51B in the m-axis direction may be 1 / 10 or more of the width of the second outer wall 22B in the m-axis direction.

[0083] 16A and 16B , first region 51 is formed at a distance from the bottom of body region 12 toward active surface 8, and faces first semiconductor region 6 across a part of body region 12. In other words, first region 51 has a bottom located within body region 12. First region 51 is formed at a distance from third trench structure 30 toward second trench structure 20, and is connected to source region 40.

[0084] The first region 51 has a concentration gradient in which the p-type impurity concentration decreases from the active surface 8 side toward the bottom side. In other words, the first region 51 includes a first high-concentration region 51H on the active surface 8 side and a first low-concentration region 51L on the bottom side, and has a concentration gradient in which the p-type impurity concentration decreases from the first high-concentration region 51H toward the first low-concentration region 51L.

[0085] When an intermediate value between the maximum and minimum values ​​of the p-type impurity concentration is set in the first region 51, the first high-concentration region 51H is a region between the maximum and intermediate values ​​of the p-type impurity concentration, while the first low-concentration region 51L is a region between the intermediate value and the minimum value of the p-type impurity concentration.

[0086] The maximum and minimum values ​​of the p-type impurity concentration of the first high-concentration region 51H are higher than the maximum value of the p-type impurity concentration of the body region 12. The maximum value of the p-type impurity concentration of the first high-concentration region 51H is 1.0×10 １９ cm －３ Above 1.0 x 10 ２１ cm －３ The first heavily doped region 51H extends in a layer shape along the active surface 8 and is connected to the second trench structure 20 and the source region 40.

[0087] The maximum and minimum values ​​of the p-type impurity concentration of the first low-concentration region 51L are equal to or less than the minimum value of the first high-concentration region 51H, and are higher than the maximum value of the p-type impurity concentration of the body region 12. The minimum value of the p-type impurity concentration of the first low-concentration region 51L is preferably 1 / 1000 to 1 / 2 of the maximum value of the p-type impurity concentration of the first high-concentration region 51H. The minimum value of the p-type impurity concentration of the first low-concentration region 51L is 1.0×10 １７ cm －３ Above 1.0 x 10 ２０ cm －３ The first low concentration region 51L extends in a layer shape along the first high concentration region 51H (active surface 8), and is connected to the second trench structure 20 and the source region 40.

[0088] The first low-concentration region 51L may have a thickness equal to or greater than the thickness of the first high-concentration region 51H, or may have a thickness less than the thickness of the first high-concentration region 51H. That is, the boundary between the first high-concentration region 51H and the first low-concentration region 51L may be located closer to the active surface 8 than the middle portion of the first region 51 in the thickness direction, or may be located closer to the bottom of the first region 51. When considering contact resistance, it is preferable to form the first high-concentration region 51H thick. That is, it is preferable that the first low-concentration region 51L have a thickness less than the thickness of the first high-concentration region 51H.

[0089] The contact region 50 includes at least one second region 52 (in this embodiment, multiple second regions 52) formed in a region along the bottom wall 23 of the second trench structure 20 in the chip 2. Specifically, the multiple second regions 52 are each formed in a region along the bottom wall 23 of the second trench structure 20 at a distance from the bottom of the body region 12 in the well region 41. In other words, the multiple second regions 52 are formed in the well bottom wall portion 42.

[0090] In this embodiment, the multiple second regions 52 are formed at intervals along the circumferential direction of the bottom wall 23. Specifically, the multiple second regions 52 include a pair of second regions 52A formed in regions along the pair of first bottom walls 23A, and a pair of second regions 52B formed in regions along the pair of second bottom walls 23B.

[0091] The pair of second regions 52A are preferably formed narrower in the a-axis direction than the first outer wall 22A. In this embodiment, the pair of second regions 52A are formed narrower in the a-axis direction than the first inner wall 21A. The pair of second regions 52A are formed in regions along the pair of first bottom walls 23A and spaced apart from the pair of second bottom walls 23B in the a-axis direction. The pair of second regions 52A are preferably opposed to each other in the m-axis direction.

[0092] The pair of second regions 52A are preferably formed in regions along the central portions of the pair of first bottom walls 23A. In this embodiment, the pair of second regions 52A face the pair of first regions 51A in the m-axis direction. Of course, the pair of second regions 52A may be shifted from each other in the a-axis direction so as not to face each other in the m-axis direction. In this case, it is preferable that one second region 52A faces one adjacent first region 51A in the m-axis direction, and the other second region 52B faces the other adjacent first region 51A in the m-axis direction.

[0093] The width of each second region 52A in the a-axis direction is preferably ½ or less of the width of the first bottom wall 23A in the a-axis direction. It is particularly preferable that the width of each second region 52A in the a-axis direction be ¼ or less of the width of the first bottom wall 23A in the a-axis direction. The width of each second region 52A in the a-axis direction may be 1 / 10 or more of the width of the first bottom wall 23A in the a-axis direction. It is preferable that the width of each second region 52A in the a-axis direction be approximately equal to the width of each first region 51A in the a-axis direction.

[0094] The pair of second regions 52B are preferably formed narrower in the m-axis direction than the second outer walls 22B. In this embodiment, the pair of second regions 52B are formed narrower in the m-axis direction than the second inner walls 21B. The pair of second regions 52B are formed in regions along the pair of second bottom walls 23B, spaced apart from the pair of first bottom walls 23A in the m-axis direction. The pair of second regions 52B are preferably opposed to each other in the a-axis direction.

[0095] The pair of second regions 52B are preferably formed in regions along the central portions of the pair of second bottom walls 23B. In this embodiment, the pair of second regions 52B face the pair of first regions 51B in the a-axis direction. Of course, the pair of second regions 52B may be shifted from each other in the m-axis direction so as not to face each other in the a-axis direction. In this case, it is preferable that one second region 52B faces one adjacent first region 51B in the a-axis direction, and the other second region 52B faces the other adjacent first region 51B in the a-axis direction.

[0096] The width of each second region 52B in the m-axis direction is preferably ½ or less of the width of the second bottom wall 23B in the m-axis direction. It is particularly preferable that the width of each second region 52B in the m-axis direction be ¼ or less of the width of the second bottom wall 23B in the m-axis direction. The width of each second region 52B in the m-axis direction may be 1 / 10 or more of the width of the second bottom wall 23B in the m-axis direction. It is preferable that the width of each second region 52B in the m-axis direction be approximately equal to the width of each first region 51B in the m-axis direction.

[0097] 16A and 16B , the second region 52 is formed at a distance from the bottom of the well region 41 toward the bottom wall 23 of the second trench structure 20, and faces the first semiconductor region 6 across a part of the well region 41. That is, the second region 52 has a bottom located within the well region 41. The second region 52 extends in a layered manner along the bottom wall 23, and is connected to the bottom wall 23 of the second trench structure 20.

[0098] Unlike the first region 51, the second region 52 does not include the first high-concentration region 51H or the first low-concentration region 51L. The maximum value of the p-type impurity concentration of the second region 52 is lower than the maximum value of the p-type impurity concentration of the first region 51. The second region 52 may have a substantially constant p-type impurity concentration in the thickness direction. The second region 52 may have a concentration gradient in which the p-type impurity concentration decreases from the bottom wall 23 toward the well region 41. In this case, the rate of decrease of the p-type impurity concentration in the second region 52 is less than the rate of decrease of the p-type impurity concentration in the first region 51.

[0099] The maximum value of the p-type impurity concentration of the second region 52 is lower than the maximum value of the p-type impurity concentration of the first high-concentration region 51H and higher than the maximum value of the p-type impurity concentration of the well region 41. The maximum value of the p-type impurity concentration of the second region 52 is preferably equal to or lower than the median value of the p-type impurity concentration of the first region 51. The minimum value of the p-type impurity concentration of the second region 52 is preferably approximately equal to the minimum value of the p-type impurity concentration of the first low-concentration region 51L.

[0100] The maximum value of the p-type impurity concentration of the second region 52 is preferably 1 / 1000 to 1 / 2 of the maximum value of the p-type impurity concentration of the first high concentration region 51H. １７cm －３ Above 1.0 x 10 ２０ cm －３ When the p-type impurity concentration of the first low-concentration region 51L increases with the introduction of the first high-concentration region 51H, the maximum value of the p-type impurity concentration of the second region 52 may be less than the maximum value of the p-type impurity concentration of the first low-concentration region 51L.

[0101] The second region 52 has a thickness greater than that of the first high-concentration region 51H. The second region 52 also has a thickness greater than that of the first low-concentration region 51L. The thickness of the second region 52 may be equal to or less than that of the first region 51, or may be greater than that of the first region 51. It is preferable that the thickness of the second region 52 be approximately equal to the thickness of the first region 51.

[0102] The contact region 50 includes at least one third region 53 (one in this embodiment) formed in a surface layer portion of the active surface 8 in the first mesa portion 24. Specifically, the third region 53 is formed in a surface layer portion of the body region 12 in the first mesa portion 24. In this embodiment, the third region 53 is formed throughout the entire surface layer portion of the body region 12 in the first mesa portion 24, and is connected to the inner sidewall 21 of the second trench structure 20.

[0103] Specifically, the third region 53 is connected to the pair of first inner side walls 21A and the pair of second inner side walls 21B. The third region 53 is formed at a distance from the bottom of the body region 12 toward the active surface 8, and faces the first semiconductor region 6 with a part of the body region 12 interposed therebetween. In other words, the third region 53 has a bottom located within the body region 12.

[0104] The third region 53 has a concentration gradient in which the p-type impurity concentration decreases from the active surface 8 side toward the bottom side. In other words, the third region 53 includes a second high-concentration region 53H on the active surface 8 side and a second low-concentration region 53L on the bottom side, and has a concentration gradient in which the p-type impurity concentration decreases from the second high-concentration region 53H toward the second low-concentration region 53L.

[0105] When an intermediate value between the maximum and minimum values ​​of the p-type impurity concentration is set in the third region 53, the second high-concentration region 53H is a region between the maximum and intermediate values ​​of the p-type impurity concentration, while the second low-concentration region 53L is a region between the intermediate value and the minimum value of the p-type impurity concentration.

[0106] The maximum and minimum values ​​of the p-type impurity concentration of the second high-concentration region 53H are higher than the maximum value of the p-type impurity concentration of the body region 12. The maximum value of the p-type impurity concentration of the second high-concentration region 53H is 1.0×10 １９ cm －３ Above 1.0 x 10 ２１ cm －３ In this embodiment, the p-type impurity concentration of the second high-concentration region 53H is substantially equal to the p-type impurity concentration of the first high-concentration region 51H of the first region 51. The second high-concentration region 53H extends in a layered manner along the active surface 8 and is connected to the inner side walls 21 (the first inner side walls 21A and the second inner side walls 21B) of the second trench structure 20.

[0107] The maximum and minimum values ​​of the p-type impurity concentration of the second low-concentration region 53L are equal to or less than the minimum value of the second high-concentration region 53H and are higher than the maximum value of the p-type impurity concentration of the body region 12. The minimum value of the p-type impurity concentration of the second low-concentration region 53L is preferably 1 / 1000 to 1 / 2 of the maximum value of the p-type impurity concentration of the second high-concentration region 53H. The minimum value of the p-type impurity concentration of the second low-concentration region 53L is 1.0×10 １７ cm －３ Above 1.0 x 10 ２０ cm －３ It may be the following:

[0108] In this embodiment, the p-type impurity concentration of the second low-concentration region 53L is approximately equal to the p-type impurity concentration of the first low-concentration region 51L of the first region 51. The second low-concentration region 53L extends in a layered manner along the second high-concentration region 53H (active surface 8) and is connected to the inner sidewalls 21 (first inner sidewall 21A and second inner sidewall 21B) of the second trench structure 20.

[0109] The second low-concentration region 53L may have a thickness equal to or greater than the thickness of the second high-concentration region 53H, or may have a thickness less than the thickness of the second high-concentration region 53H. In other words, the boundary between the second high-concentration region 53H and the second low-concentration region 53L may be located on the active surface 8 side relative to the middle portion of the third region 53 in the thickness direction, or may be located on the bottom side of the third region 53.

[0110] Considering the contact resistance, it is preferable to form the second high-concentration region 53H thick. That is, it is preferable that the second low-concentration region 53L has a thickness less than that of the second high-concentration region 53H. In this embodiment, the second high-concentration region 53H has a thickness approximately equal to that of the first high-concentration region 51H, and the first high-concentration region 51H has a thickness approximately equal to that of the second high-concentration region 53H.

[0111] The relationship in p-type impurity concentration between the second high-concentration region 53H and the second region 52 is substantially the same as the relationship in p-type impurity concentration between the first high-concentration region 51H and the second region 52. In addition, the relationship in p-type impurity concentration between the second low-concentration region 53L and the second region 52 is substantially the same as the relationship in p-type impurity concentration between the first low-concentration region 51L and the second region 52.

[0112] The contact region 50 includes at least one (in this embodiment, multiple) first connection regions 54 formed in a region along the outer sidewall 22 of the second trench structure 20 in the chip 2. Specifically, the multiple first connection regions 54 are each formed in a region along the outer sidewall 22 of the second trench structure 20 in the well region 41 so as to connect the first region 51 and the second region 52 that are adjacent in the vertical direction. In other words, the multiple second regions 52 are formed in the second well sidewall portion 44.

[0113] Specifically, the multiple first connection regions 54 include a pair of first connection regions 54A formed in a region along the pair of first outer side walls 22A within the chip 2, and a pair of first connection regions 54B formed in a region along the pair of second outer side walls 22B within the chip 2. The pair of first connection regions 54A are formed in a region along the corresponding first outer side walls 22A so as to connect the first region 51A and second region 52A that are adjacent in the vertical direction.

[0114] The pair of first connection regions 54A are preferably formed narrower in the a-axis direction than the first outer walls 22A. In this embodiment, the pair of first connection regions 54A are formed narrower in the a-axis direction than the first inner walls 21A. The pair of first connection regions 54A are formed in regions along the pair of first outer walls 22A and spaced apart from the pair of second outer walls 22B in the a-axis direction. The pair of first connection regions 54A are preferably formed in regions along the central portions of the pair of first outer walls 22A. The formation locations of the pair of first connection regions 54A are adjusted depending on the formation locations of the corresponding first regions 51A and second regions 52A.

[0115] The width of each first connection region 54A in the a-axis direction is preferably ½ or less of the width of the first outer wall 22A in the a-axis direction. It is particularly preferable that the width of each first connection region 54A in the a-axis direction be ¼ or less of the width of the first outer wall 22A in the a-axis direction. The width of each first connection region 54A in the a-axis direction may be 1 / 10 or more of the width of the first outer wall 22A in the a-axis direction. It is preferable that the width of each first connection region 54A in the a-axis direction be approximately equal to the width of each first region 51A and the width of each second region 52A in the a-axis direction.

[0116] The pair of first connection regions 54B are formed in regions along the corresponding second outer walls 22B so as to connect the first region 51B and the second region 52B that are adjacent in the up-down direction. The pair of first connection regions 54B are preferably formed narrower than the second outer walls 22B in the m-axis direction. In this embodiment, the pair of first connection regions 54B are formed narrower than the second inner walls 21B in the m-axis direction.

[0117] The pair of first connection regions 54B are formed in regions along the pair of second outer walls 22B and spaced apart from the pair of first outer walls 22A in the m-axis direction. The pair of first connection regions 54A are preferably formed in regions along central portions of the pair of second outer walls 22B. The formation locations of the pair of first connection regions 54B are adjusted depending on the formation locations of the corresponding first region 51B and second region 52B.

[0118] The width in the m-axis direction of each first connection region 54B is preferably ½ or less of the width in the m-axis direction of the second outer wall 22B. It is particularly preferable that the width in the m-axis direction of each first connection region 54B be ¼ or less of the width in the m-axis direction of the second outer wall 22B. The width in the m-axis direction of each first connection region 54B may be 1 / 10 or more of the width in the m-axis direction of the second outer wall 22B. It is preferable that the width in the m-axis direction of each first connection region 54B is approximately equal to the width in the m-axis direction of each first region 51B and the width in the m-axis direction of each second region 52B.

[0119] 16A and 16B , the first connection region 54 is formed in a layer shape extending in the c-axis direction along the outer wall 22 of the second trench structure 20 so as to be drawn from within the well region 41 (second well sidewall portion 44) into the body region 12. The first connection region 54 is connected to the first region 51 on the surface layer side of the active surface 8, and is connected to the second region 52 on the bottom wall 23 side of the second trench structure 20. Specifically, the first connection region 54 is connected to the first low-concentration region 51L of the first region 51. The first connection region 54 faces the first semiconductor region 6 in the horizontal direction, with a portion of the well region 41 (second well sidewall portion 44) sandwiched therebetween.

[0120] Unlike the first region 51, the first connection region 54 does not include the first high-concentration region 51H or the first low-concentration region 51L. The maximum value of the p-type impurity concentration in the first connection region 54 is lower than the maximum value of the p-type impurity concentration in the first region 51. The first connection region 54 may have a substantially constant p-type impurity concentration in the horizontal direction. The first connection region 54 may have a concentration gradient in which the p-type impurity concentration decreases in the horizontal direction from the outer wall 22 of the second trench structure 20. In this case, the rate of decrease in the p-type impurity concentration in the first connection region 54 is less than the rate of decrease in the p-type impurity concentration in the first region 51.

[0121] The maximum and minimum values ​​of the p-type impurity concentration of the first connection region 54 are lower than the maximum value of the p-type impurity concentration of the first high-concentration region 51H and higher than the maximum value of the p-type impurity concentration of the well region 41. The maximum value of the p-type impurity concentration of the first connection region 54 is preferably equal to or lower than the median value of the p-type impurity concentration of the first region 51. The minimum value of the p-type impurity concentration of the first connection region 54 is preferably approximately equal to the minimum value of the p-type impurity concentration of the first low-concentration region 51L.

[0122] The maximum value of the p-type impurity concentration of the first connection region 54 is preferably 1 / 1000 to 1 / 2 of the maximum value of the p-type impurity concentration of the first high concentration region 51H. １７ cm －３ Above 1.0 x 10 ２０ cm －３ When the p-type impurity concentration of the first low-concentration region 51L increases with the introduction of the first high-concentration region 51H, the maximum value of the p-type impurity concentration of the first connection region 54 may be less than the maximum value of the p-type impurity concentration of the first low-concentration region 51L.

[0123] The thickness of the first connection region 54 measured from the outer wall 22 is smaller than the thickness of the first region 51 measured from the active surface 8. The thickness of the first connection region 54 measured from the outer wall 22 is smaller than the thickness of the second region 52 measured from the bottom wall 23 of the second trench structure 20. The thickness of the first connection region 54 may be equal to or smaller than the thickness of the first high concentration region 51H, or may be larger than the thickness of the first high concentration region 51H.

[0124] The thickness of the first connection region 54 may be equal to or less than the thickness of the first low-concentration region 51 L, or may be greater than the thickness of the first low-concentration region 51 L. The relationship between the p-type impurity concentration and thickness of the first connection region 54 and the third region 53 is similar to the relationship between the p-type impurity concentration and thickness of the first connection region 54 and the first region 51, and therefore a description thereof will be omitted.

[0125] The contact region 50 includes at least one (in this embodiment, multiple) second connection regions 55 formed in a region along the inner sidewall 21 of the second trench structure 20 in the chip 2. Specifically, the multiple second connection regions 55 are formed in regions along the inner sidewall 21 of the second trench structure 20 in the well region 41 so as to connect the multiple second regions 52 and the multiple third regions 53, respectively. In other words, the multiple second regions 52 are formed in the first well sidewall portion 43.

[0126] Specifically, the multiple second connection regions 55 include a pair of second connection regions 55A formed in a region along the pair of first inner side walls 21A within the chip 2, and a pair of second connection regions 55B formed in a region along the pair of second inner side walls 21B within the chip 2. The pair of second connection regions 55A are formed in a region along the corresponding first inner side walls 21A so as to connect the pair of second region 52A and third region 53.

[0127] The pair of second connection regions 55A are preferably formed narrower in the a-axis direction than the first inner side walls 21A. The pair of second connection regions 55A are formed in regions along the pair of first inner side walls 21A and spaced apart from the pair of second inner side walls 21B in the a-axis direction. The pair of second connection regions 55A are preferably formed in regions along the central portions of the pair of first inner side walls 21A. The formation locations of the pair of second connection regions 55A are adjusted depending on the formation locations of the corresponding second regions 52A.

[0128] The width of each second connection region 55A in the a-axis direction is preferably ½ or less of the width of the first inner side wall 21A in the a-axis direction. It is particularly preferable that the width of each second connection region 55A in the a-axis direction be ⅓ or less of the width of the first inner side wall 21A in the a-axis direction. The width of each second connection region 55A in the a-axis direction may be 1 / 10 or more of the width of the first inner side wall 21A in the a-axis direction. It is preferable that the width of each second connection region 55A in the a-axis direction be approximately equal to the width of each second region 52A in the a-axis direction.

[0129] The pair of second connection regions 55B are formed in regions along the corresponding second inner walls 21B so as to connect the pair of second regions 52B and the pair of third regions 53. The pair of second connection regions 55B are preferably formed narrower than the second inner walls 21B in the m-axis direction. The pair of second connection regions 55B are formed in regions along the pair of second inner walls 21B, spaced apart from the pair of first inner walls 21A in the m-axis direction. The pair of second connection regions 55B are preferably formed in regions along the central portions of the pair of second inner walls 21B. The formation locations of the pair of second connection regions 55B are adjusted depending on the formation locations of the corresponding second regions 52B.

[0130] The width of each second connection region 55B in the m-axis direction is preferably ½ or less of the width of the second inner wall 21B in the m-axis direction. It is particularly preferable that the width of each second connection region 55B in the m-axis direction be ⅓ or less of the width of the second inner wall 21B in the m-axis direction. The width of each second connection region 55B in the m-axis direction may be 1 / 10 or more of the width of the second inner wall 21B in the m-axis direction. It is preferable that the width of each second connection region 55B in the m-axis direction be approximately equal to the width of each second region 52B in the m-axis direction.

[0131] 16A and 16B , the second connection region 55 is formed in a layer shape extending in the c-axis direction along the inner wall 21 of the second trench structure 20 so as to be drawn from within the well region 41 (first well sidewall portion 43) into the body region 12. The second connection region 55 is connected to the second region 52 on the bottom wall 23 side of the second trench structure 20, and is connected to the third region 53 on the surface layer side of the active surface 8. Specifically, the second connection region 55 is connected to the second low-concentration region 53L of the third region 53. The second connection region 55 faces the first semiconductor region 6 in the horizontal direction, with a part of the well region 41 (first well sidewall portion 43) sandwiched therebetween.

[0132] Unlike the first region 51, the second connection region 55 does not include the first high-concentration region 51H or the first low-concentration region 51L. The maximum value of the p-type impurity concentration in the second connection region 55 is lower than the maximum value of the p-type impurity concentration in the first region 51. The second connection region 55 may have a substantially constant p-type impurity concentration in the horizontal direction. The second connection region 55 may have a concentration gradient in which the p-type impurity concentration decreases in the horizontal direction from the inner wall 21 of the second trench structure 20. In this case, the rate of decrease in the p-type impurity concentration in the second connection region 55 is less than the rate of decrease in the p-type impurity concentration in the first region 51.

[0133] The maximum and minimum values ​​of the p-type impurity concentration of the second connection region 55 are lower than the maximum value of the p-type impurity concentration of the first high-concentration region 51H and higher than the maximum value of the p-type impurity concentration of the well region 41. The maximum value of the p-type impurity concentration of the second connection region 55 is preferably equal to or lower than the median value of the p-type impurity concentration of the first region 51. The minimum value of the p-type impurity concentration of the first connection region 54 is preferably approximately equal to the minimum value of the p-type impurity concentration of the first low-concentration region 51L.

[0134] The maximum value of the p-type impurity concentration of the second connection region 55 is preferably 1 / 1000 to 1 / 2 of the maximum value of the p-type impurity concentration of the first high concentration region 51H. １７ cm －３ Above 1.0 x 10 ２０ cm －３ When the p-type impurity concentration of the first low-concentration region 51L increases with the introduction of the first high-concentration region 51H, the maximum value of the p-type impurity concentration of the second connection region 55 may be less than the maximum value of the p-type impurity concentration of the first low-concentration region 51L.

[0135] The thickness of the second connection region 55 measured from the inner sidewall 21 is smaller than the thickness of the first region 51 measured from the active surface 8. The thickness of the second connection region 55 measured from the inner sidewall 21 is smaller than the thickness of the second region 52 measured from the bottom wall 23 of the second trench structure 20. The thickness of the second connection region 55 may be equal to or smaller than the thickness of the first high concentration region 51H, or may be larger than the thickness of the first high concentration region 51H.

[0136] The thickness of the second connection region 55 may be equal to or less than the thickness of the first low-concentration region 51 L, or may be greater than the thickness of the first low-concentration region 51 L. The relationship between the p-type impurity concentration and thickness of the second connection region 55 and the third region 53 is similar to the relationship between the p-type impurity concentration and thickness of the second connection region 55 and the first region 51, and therefore a description thereof will be omitted.

[0137] 8 to 15 , the SiC semiconductor device 1A includes a plurality of p-type gate well regions 65 formed in regions along a plurality of trench intersections 34 in the chip 2. The plurality of gate well regions 65 have a lower p-type impurity concentration than the contact region 50. In this embodiment, the plurality of gate well regions 65 have a higher p-type impurity concentration than the body region 12. Of course, the plurality of gate well regions 65 may have a lower p-type impurity concentration than the body region 12.

[0138] The plurality of gate well regions 65 preferably have a p-type impurity concentration substantially equal to that of the well region 41. The p-type impurity concentration (maximum value) of the gate well region 65 is 1.0×10 １６ cm －３ Above 1.0 x 10 １９ cm －３ The plurality of gate well regions 65 are formed in regions along the plurality of trench intersections 34 at intervals in the a-axis direction and the m-axis direction, and expose regions of the bottom wall (first gate bottom wall 33 and second gate bottom wall 36) of the third trench structure 30 outside the plurality of trench intersections 34.

[0139] Each gate well region 65 covers the first gate sidewall 32 of the third trench structure 30A and the second gate sidewall 35 of the third trench structure 30B at the corner of each second mesa portion 31, and is connected to the body region 12 at the surface portion of each second mesa portion 31. The multiple gate well regions 65 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 with part of the first semiconductor region 6 in between. The bottoms of the multiple gate well regions 65 are preferably formed at a depth position substantially equal to the bottom of the well region 41.

[0140] 6 and 7 , SiC semiconductor device 1A includes a wiring well region 66 formed in chip 2 in a region along the wall surface of first trench structure 15. Wiring well region 66 has a lower p-type impurity concentration than contact region 50. In this embodiment, wiring well region 66 has a higher p-type impurity concentration than body region 12.

[0141] Of course, the wiring well region 66 may have a p-type impurity concentration lower than that of the body region 12. The wiring well region 66 preferably has a p-type impurity concentration approximately equal to that of the well region 41. The p-type impurity concentration (maximum value) of the wiring well region 66 is 1.0×10 １６ cm －３ Above 1.0 x 10 １９ cm －３ It may be the following:

[0142] The wiring well region 66 is formed in the pad portion 15a and the line portion 15b of the first trench structure 15 in regions along the inner wall, outer wall, and bottom wall of the first trench structure 15, and is connected to the body region 12 in a surface layer portion of the active surface 8. The wiring well region 66 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8, and faces the second semiconductor region 7 with a part of the first semiconductor region 6 in between. The bottom of the wiring well region 66 is preferably formed at a depth position substantially equal to the bottom of the well region 41.

[0143] 17 , SiC semiconductor device 1A includes a p-type outer well region 67 formed in a surface layer portion of outer side surface 9. Outer well region 67 has a lower p-type impurity concentration than contact region 50. In this embodiment, outer well region 67 has a higher p-type impurity concentration than body region 12.

[0144] Of course, the outer well region 67 may have a p-type impurity concentration lower than that of the body region 12. The outer well region 67 preferably has a p-type impurity concentration approximately equal to that of the well region 41. The p-type impurity concentration (maximum value) of the outer well region 67 is 1.0×10 １６ cm －３ Above 1.0 x 10 １９cm －３ It may be the following:

[0145] The outer well region 67 is formed at a distance from the periphery of the outer side surface 9 (first to fourth side surfaces 5A to 5D) toward the active surface 8 in a plan view, and extends in a band shape along the active surface 8. In this embodiment, the outer well region 67 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8 in a plan view. The outer well region 67 extends from the surface layer portion of the outer side surface 9 toward the surface layer portions of the first to fourth connection surfaces 10A to 10D, and covers the first to fourth connection surfaces 10A to 10D. The outer well region 67 is electrically connected to the body region 12 in the surface layer portion of the active surface 8.

[0146] The outer well region 67 is formed at a distance from the bottom of the first semiconductor region 6 toward the outer surface 9, and faces the second semiconductor region 7 across a part of the first semiconductor region 6. The outer well region 67 is located closer to the bottom of the first semiconductor region 6 than the bottom walls 23 of the multiple second trench structures 20. The bottom of the outer well region 67 is located closer to the bottom of the first semiconductor region 6 than the bottom of the contact region 50 (the bottom of the second region 52). The bottom of the outer well region 67 is preferably formed at a depth position substantially equal to the bottom of the well region 41.

[0147] The SiC semiconductor device 1A includes a p-type outer contact region 68 formed in a surface layer portion of the outer well region 67. The outer contact region 68 is formed in a band shape extending along the active surface 8, spaced apart from the periphery of the active surface 8 (first to fourth connection surfaces 10A to 10D) and the periphery of the outer side surface 9 (first to fourth side surfaces 5A to 5D) in a plan view. In this embodiment, the outer contact region 68 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in a plan view.

[0148] The outer contact region 68 is formed at a distance from the bottom of the outer well region 67 toward the outer surface 9, and faces the first semiconductor region 6 across a part of the outer well region 67. The outer contact region 68 is located closer to the bottom of the first semiconductor region 6 than the bottom walls 23 of the plurality of second trench structures 20. The bottom of the outer contact region 68 is preferably formed at a depth position substantially equal to the bottom of the contact region 50 (the bottom of the second region 52).

[0149] The outer contact region 68 has a higher p-type impurity concentration than the body region 12. The outer contact region 68 has a higher p-type impurity concentration than the outer well region 67. The p-type impurity concentration (maximum value) of the outer contact region 68 is 1.0×10 １７ cm －３ Above 1.0 x 10 ２１ cm －３ The outer contact region 68 preferably has a p-type impurity concentration substantially equal to that of the first region 51 of the contact region 50. The outer contact region 68 preferably contains aluminum (Al) as the p-type impurity.

[0150] That is, in this embodiment, the outer contact region 68 has a concentration gradient in which the p-type impurity concentration decreases from the outer side surface 9 toward the bottom. In other words, the outer contact region 68 includes a third high concentration region 68H on the outer side surface 9 side and a third low concentration region 68L on the bottom side, and has a concentration gradient in which the p-type impurity concentration decreases from the third high concentration region 68H toward the third low concentration region 68L.

[0151] When an intermediate value between the maximum and minimum values ​​of the p-type impurity concentration is set in the outer contact region 68, the third high-concentration region 68H is a region between the maximum and intermediate values ​​of the p-type impurity concentration, while the third low-concentration region 68L is a region between the intermediate value and the minimum value of the p-type impurity concentration.

[0152] The maximum and minimum values ​​of the p-type impurity concentration of the third high-concentration region 68H are higher than the p-type impurity concentration of the outer well region 67. The maximum value of the p-type impurity concentration of the third high-concentration region 68H is 1.0×10 １９ cm －３ Above 1.0 x 10 ２１ cm －３ The p-type impurity concentration of the third high-concentration region 68H is preferably approximately equal to the p-type impurity concentration of the first high-concentration region 51H. The third high-concentration region 68H extends in a band shape (annular in this embodiment) along the outer side surface 9 in plan view and is exposed from the outer side surface 9.

[0153] The maximum and minimum values ​​of the p-type impurity concentration of the third low-concentration region 68L are equal to or less than the minimum value of the first high-concentration region 51H and are higher than the maximum value of the p-type impurity concentration of the outer well region 67. The minimum value of the p-type impurity concentration of the third low-concentration region 68L is preferably 1 / 1000 to 1 / 2 of the maximum value of the p-type impurity concentration of the third high-concentration region 68H.

[0154] The minimum value of the p-type impurity concentration of the third low-concentration region 68L is 1.0×10 １７ cm －３ Above 1.0 x 10 ２０ cm －３ The p-type impurity concentration of the third low-concentration region 68L is preferably approximately equal to the p-type impurity concentration of the first low-concentration region 51L. The third low-concentration region 68L extends in a band shape (annular in this embodiment) along the outer side surface 9 in plan view.

[0155] The third low-concentration region 68L may have a thickness equal to or greater than the thickness of the third high-concentration region 68H, or may have a thickness less than the thickness of the third high-concentration region 68H. That is, the boundary between the third high-concentration region 68H and the third low-concentration region 68L may be located closer to the outer surface 9 than the middle portion of the outer well region 67 in the thickness direction, or may be located closer to the bottom of the outer well region 67. When considering contact resistance, it is preferable to form the third high-concentration region 68H thick. That is, it is preferable that the third low-concentration region 68L have a thickness less than the thickness of the third high-concentration region 68H.

[0156] The SiC semiconductor device 1A includes at least one (preferably two or more and twenty or less) p-type field region 69 formed in a surface layer portion of the outer surface 9 in a region between the periphery of the outer surface 9 and the outer well region 67. In this embodiment, the SiC semiconductor device 1A includes four field regions 69. The multiple field regions 69 are formed in an electrically floating state and relieve the electric field within the chip 2 at the outer surface 9.

[0157] The number, width, depth, p-type impurity concentration, etc. of the field regions 69 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The plurality of field regions 69 may have a p-type impurity concentration lower than that of the outer contact region 68. The plurality of field regions 69 may have a p-type impurity concentration higher than that of the outer well region 67. The plurality of field regions 69 may have a p-type impurity concentration lower than that of the outer well region 67. The p-type impurity concentration (maximum value) of the field region 69 is 1.0×10 １６ cm －３ Above 1.0 x 10 ２１ cm －３ It may be the following:

[0158] The field regions 69 are arranged at intervals from the outer contact region 68 side to the peripheral edge side of the outer side surface 9. The field regions 69 are formed in strip shapes extending along the active surface 8 in plan view. In this embodiment, the field regions 69 are formed in an annular shape (specifically, a rectangular annular shape) surrounding the active surface 8 in plan view.

[0159] The plurality of field regions 69 are formed at intervals from the bottom of the first semiconductor region 6 toward the outer side surface 9, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The plurality of field regions 69 are located closer to the bottom of the first semiconductor region 6 than the bottom walls 23 of the plurality of second trench structures 20. The bottoms of the plurality of field regions 69 are located closer to the bottom of the first semiconductor region 6 than the bottom of the contact region 50 (the bottom of the second region 52). The bottoms of the plurality of field regions 69 may be formed at a depth position substantially equal to the bottom of the well region 41.

[0160] The SiC semiconductor device 1A includes a main surface insulating film 70 that covers the first main surface 3. The main surface insulating film 70 has a layered structure including a first main surface insulating film 71 and a second main surface insulating film 72. The first main surface insulating film 71 covers the active surface 8, the outer side surface 9, and the first to fourth connecting surfaces 10A to 10D.

[0161] The first main surface insulating film 71 is continuous with the first insulating film 17 and the third insulating film 38 on the active surface 8, and exposes the first buried electrode 18, the second buried electrode 27, and the third buried electrode 39. The main surface insulating film 70 covers the outer contact region 68, the outer well region 67, and the plurality of field regions 69 on the outer side surface 9 and the first to fourth connecting surfaces 10A to 10D.

[0162] The first main surface insulating film 71 may be continuous with the first to fourth side surfaces 5A to 5D. In this case, the outer wall of the first main surface insulating film 71 may be made of a ground surface having grinding marks. The outer wall of the first main surface insulating film 71 may form a single ground surface together with the first to fourth side surfaces 5A to 5D. Of course, the outer wall of the first main surface insulating film 71 may be made of a smooth surface without grinding marks. Furthermore, the outer wall of the first main surface insulating film 71 may be formed at a distance inward from the periphery of the outer surface 9, exposing the first semiconductor region 6 from the periphery of the outer surface 9.

[0163] The first main surface insulating film 71 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first main surface insulating film 71 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first main surface insulating film 71 include a silicon oxide film made of an oxide of the chip 2.

[0164] The second main surface insulating film 72 covers the active surface 8, the outer side surface 9, and the first to fourth connecting surfaces 10A to 10D with the first main surface insulating film 71 in between. The second main surface insulating film 72 covers the first trench structure 15 and the third trench structure 30 on the active surface 8. The second main surface insulating film 72 covers the outer contact region 68, the outer well region 67, and the plurality of field regions 69 on the outer side surface 9 and the first to fourth connecting surfaces 10A to 10D.

[0165] In this embodiment, the second main surface insulating film 72 is continuous with the first to fourth side surfaces 5A to 5D. The outer wall of the second main surface insulating film 72 may be made of a ground surface having grinding marks. The outer wall of the second main surface insulating film 72 may form a single ground surface together with the first to fourth side surfaces 5A to 5D. Of course, the outer wall of the second main surface insulating film 72 may be made of a smooth surface without grinding marks. Furthermore, the outer wall of the second main surface insulating film 72 may be formed at a distance inward from the periphery of the outer surface 9, exposing the first semiconductor region 6 from the periphery of the outer surface 9.

[0166] The second main surface insulating film 72 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second main surface insulating film 72 has a single-layer structure made of a silicon oxide film.

[0167] The SiC semiconductor device 1A includes a sidewall structure 73 arranged in a main surface insulating film 70 so as to cover at least one of the first to fourth connecting surfaces 10A to 10D on the outer side surface 9. Specifically, the sidewall structure 73 is arranged on a first main surface insulating film 71 and is covered by a second main surface insulating film 72. In this embodiment, the sidewall structure 73 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8 in a plan view. The sidewall structure 73 may include an inorganic insulator or polysilicon.

[0168] The SiC semiconductor device 1A includes one or more (one in this embodiment) first gate openings 74 formed in the main surface insulating film 70. The first gate openings 74 expose the pad portions 15a of the first trench structures 15. The SiC semiconductor device 1A includes one or more (one in this embodiment) second gate openings 75 formed in the main surface insulating film 70. The second gate openings 75 extend in a strip shape along the line portions 15b of the first trench structures 15, and expose the first buried electrodes 18 of the line portions 15b.

[0169] The SiC semiconductor device 1A includes a plurality of source openings 76 formed at intervals in the main surface insulating film 70. The plurality of source openings 76 expose the corresponding second trench structures 20, the corresponding first mesa portions 24, and the corresponding second mesa portions 31. The plurality of source openings 76 expose the second high-concentration regions 53H of the contact region 50 from the corresponding first mesa portions 24, and expose the source region 40 and the first high-concentration regions 51H of the contact region 50 from the corresponding second mesa portions 31. In this embodiment, each source opening 76 is formed in a quadrangular shape in a plan view.

[0170] The SiC semiconductor device 1A includes one or more (one in this embodiment) outer openings 77 formed in the main surface insulating film 70. The outer openings 77 extend in a strip-like or annular shape along the outer contact regions 68, exposing the outer contact regions 68. Specifically, the outer openings 77 expose the third high-concentration regions 68H of the outer contact regions 68.

[0171] The SiC semiconductor device 1A includes a gate electrode 80 disposed on a main surface insulating film 70. The gate electrode 80 may also be referred to as a "gate main surface electrode." The gate electrode 80 includes a gate pad electrode 81 and a gate line electrode 82. The gate pad electrode 81 is disposed on the pad portion 15a of the first trench structure 15 at a distance from the periphery of the active surface 8. In this embodiment, the gate pad electrode 81 is formed in a quadrangular shape in a plan view. The gate pad electrode 81 extends from above the main surface insulating film 70 into the first gate opening 74 and is electrically connected to the first buried electrode 18 of the pad portion 15a.

[0172] The gate line electrode 82 is drawn out from the gate pad electrode 81 onto the line portion 15b of the first trench structure 15. In this embodiment, the gate line electrode 82 covers the line portion 15b at a distance from the periphery of the active surface 8. The gate line electrode 82 is formed in a strip shape extending along the line portion 15b in a plan view.

[0173] In this embodiment, the gate line electrode 82 extends along the first to third side surfaces 5A to 5C (first to third connecting surfaces 10A to 10C), and has a pair of open ends 83 in the portion along the fourth side surface 5D (fourth connecting surface 10D). The gate line electrode 82 extends from above the main surface insulating film 70 into the second gate opening 75, and is electrically connected to the first buried electrode 18 of the line portion 15b.

[0174] The gate electrode 80 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. The gate electrode 80 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the gate electrode 80 has a layered structure including a Ti film, a TiN film, and an Al alloy film (an AlCu alloy film in this embodiment) layered in this order from the chip 2 side.

[0175] The SiC semiconductor device 1A includes a source electrode 85 disposed on the main surface insulating film 70 at a distance from the gate electrode 80. The source electrode 85 may also be referred to as a "source main surface electrode." The source electrode 85 includes a source pad electrode 86 and a source line electrode 87.

[0176] The source pad electrode 86 is disposed on the main surface insulating film 70 in a region defined by the gate pad electrode 81 and the gate line electrode 82, and covers the second trench structures 20 and the third trench structures 30. The source pad electrode 86 is formed in a polygonal shape having a recess that is recessed along the gate pad electrode 81 in a plan view.

[0177] The source pad electrode 86 covers the plurality of third trench structures 30 with the main surface insulating film 70 interposed therebetween, and extends into the plurality of source openings 76 from above the main surface insulating film 70. The source pad electrode 86 is electrically connected, within the corresponding source opening 76, to the second buried electrode 27 of the corresponding second trench structure 20, the corresponding first mesa portion 24, and the corresponding second mesa portion 31.

[0178] The source pad electrode 86 is electrically connected to the third region 53 (second high concentration region 53H) of the contact region 50 in the corresponding first mesa portion 24, and is electrically connected to the source region 40 and the first region 51 (first high concentration region 51H) of the contact region 50 in the corresponding second mesa portion 31.

[0179] The source line electrode 87 is drawn in a strip shape from the source pad electrode 86 to the outer surface 9. Specifically, the source line electrode 87 passes through the region between the pair of open ends 83 of the gate line electrode 82 from the source pad electrode 86 and is drawn onto the outer surface 9. The source line electrode 87 has a portion that faces the sidewall structure 73 in the region between the active surface 8 and the outer surface 9, with the second main surface insulating film 72 sandwiched therebetween.

[0180] The source line electrode 87 extends in a strip shape along the outer contact region 68 in plan view. In this embodiment, the source line electrode 87 is formed in a ring shape (specifically, a quadrangular ring) surrounding the gate pad electrode 81, the gate line electrode 82, and the source pad electrode 86 in plan view. The source line electrode 87 extends from above the main surface insulating film 70 into the outer opening 77 and is electrically connected to the third high concentration region 68H of the outer contact region 68.

[0181] The source electrode 85 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. The source electrode 85 may also include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the source electrode 85 has a layered structure including a Ti film and an Al alloy film (an AlSiCu alloy film in this embodiment) stacked in this order from the chip 2 side. In other words, the source electrode 85 includes the same conductive material as the gate electrode 80.

[0182] The SiC semiconductor device 1A includes a drain electrode 88 covering the second main surface 4. The drain electrode 88 is electrically connected to the second main surface 4. The drain electrode 88 forms an ohmic contact with the second semiconductor region 7 exposed from the second main surface 4. The drain electrode 88 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. A breakdown voltage that can be applied between the source electrode 85 and the drain electrode 88 may be 500 V or more and 3000 V or less.

[0183] As described above, SiC semiconductor device 1A includes chip 2, second trench structure 20 (trench structure), and p-type contact region 50. Chip 2 includes SiC single crystal and has first main surface 3. Second trench structure 20 has outer wall 22 (side wall) and bottom wall 23, and is formed on first main surface 3. Contact region 50 includes first region 51 and second region 52. First region 51 is formed in a region along outer wall 22 in a surface layer portion of first main surface 3. Second region 52 has a p-type impurity concentration lower than the p-type impurity concentration of first region 51, and is formed in a region along bottom wall 23 within chip 2.

[0184] One possible method for reducing the contact resistance caused by the contact region 50 is to increase the concentration of the contact region 50. For example, by increasing the concentration of both the region along the surface portion of the first main surface 3 and the region along the bottom wall 23 of the second trench structure 20 in the contact region 50, the contact resistance can be effectively reduced.

[0185] However, when the contact region 50 is highly concentrated in the region along the bottom wall 23 of the second trench structure 20, crystal defects in the SiC single crystal may occur due to modifications of the SiC single crystal that accompany the highly concentrated contact region 50. These types of crystal defects degrade the electrical characteristics of the SiC semiconductor device. In particular, the electrical characteristics of the SiC semiconductor device are susceptible to the influence of crystal defects in the region along the bottom wall 23 of the second trench structure 20.

[0186] In contrast, contact region 50 in SiC semiconductor device 1A has first region 51 with a relatively high concentration on the surface layer side of first main surface 3, and second region 52 with a lower concentration than first region 51 on the bottom wall 23 side of second trench structure 20. This makes it possible to reduce contact resistance by first region 51, while suppressing crystal defects originating from second region 52 in the region along bottom wall 23 in chip 2. Therefore, it is possible to provide SiC semiconductor device 1A with improved electrical characteristics.

[0187] For example, suppressing crystal defects can suppress leakage current caused by the crystal defects. For example, suppressing crystal defects is effective in suppressing the drain cutoff current IDSS. The drain cutoff current IDSS is the leakage current that flows between the drain and source when the gate and source are short-circuited. Furthermore, suppressing crystal defects can suppress an increase in resistance caused by the crystal defects. For example, suppressing crystal defects is effective in suppressing the on-resistance Ron.

[0188] The first region 51 preferably includes a first high-concentration region 51H and a first low-concentration region 51L. The first high-concentration region 51H is located on the first main surface 3 side and has a relatively high p-type impurity concentration. The first low-concentration region 51L has a p-type impurity concentration lower than that of the first high-concentration region 51H and is located on the bottom side. In this case, the second region 52 preferably has a p-type impurity concentration lower than that of the first high-concentration region 51H. This structure allows the first region 51 to be appropriately concentrated while appropriately suppressing the second region 52 from being highly concentrated.

[0189] The SiC semiconductor device 1A preferably includes a p-type body region 12 formed in a surface layer portion of the first main surface 3. In this case, the second trench structure 20 is formed in the first main surface 3 so as to penetrate the body region 12. The first region 51 preferably has a p-type impurity concentration higher than the p-type impurity concentration of the body region 12, and is formed in a surface layer portion of the body region 12. Furthermore, the second region 52 preferably has a p-type impurity concentration higher than the p-type impurity concentration of the body region 12.

[0190] The SiC semiconductor device 1A preferably includes a p-type well region 41 formed in a region along the bottom wall 23 in the chip 2. In this case, the first region 51 preferably has a p-type impurity concentration higher than the p-type impurity concentration of the well region 41. The second region 52 preferably has a p-type impurity concentration higher than the p-type impurity concentration of the well region 41, and is formed in a region along the bottom wall 23 in the well region 41. These structures enable the breakdown voltage to be improved by utilizing a depletion layer that spreads from the well region 41, while suppressing crystal defects originating from the contact region 50.

[0191] The contact region 50 preferably includes a first connection region 54 formed in a region along the outer sidewall 22 within the chip 2 so as to connect the first region 51 and the second region 52. This structure reduces the contact resistance in the region between the first region 51 and the second region 52. The first connection region 54 preferably has a p-type impurity concentration lower than the p-type impurity concentration of the first region 51. This structure suppresses crystal defects originating from the first connection region 54.

[0192] The thickness of the first connection region 54 relative to the outer wall 22 is preferably smaller than the thickness of the first region 51 relative to the first main surface 3. The thickness of the first connection region 54 relative to the outer wall 22 is preferably smaller than the thickness of the second region 52 relative to the bottom wall 23.

[0193] The chip 2 preferably includes a SiC single crystal made of a hexagonal crystal. This structure can suppress crystal defects (so-called m-plane defects) that occur along the m-plane of the SiC single crystal starting from the second region 52. For example, suppressing the m-plane defects can appropriately suppress leakage current caused by the m-plane defects. For example, suppressing the m-plane defects is particularly effective in suppressing the drain cutoff current IDSS caused by the m-plane defects.

[0194] Furthermore, this structure can suppress crystal defects (so-called a-plane defects) that occur along the a-plane of the SiC single crystal starting from the second region 52. For example, suppressing a-plane defects can appropriately suppress an increase in resistance caused by the a-plane defects. For example, suppressing a-plane defects is effective in suppressing an increase in on-resistance Ron caused by the a-plane defects. The increase in leakage current caused by m-plane defects and the increase in resistance caused by a-plane defects are caused by the physical properties of the SiC single crystal.

[0195] In this case, the outer wall 22 preferably includes a first outer wall 22A extending in the a-axis direction of the SiC single crystal and a second outer wall 22B extending in the m-axis direction of the SiC single crystal. That is, the first outer wall 22A is preferably formed by an m-plane of the SiC single crystal, and the second outer wall 22B is preferably formed by an a-plane of the SiC single crystal.

[0196] At least one first region 51 may be formed in either one or both of the first outer wall 22A and the second outer wall 22B. When at least one first region 51 is formed in a region along the first outer wall 22A, the first region 51 is preferably formed in a region along the first outer wall 22A at a distance from the second outer wall 22B in the a-axis direction.

[0197] This structure can reduce the formation area of ​​the first region 51 along the outer sidewall 22. This can suppress m-plane defects and a-plane defects originating from the first region 51 in the chip 2. This structure is particularly effective in suppressing a-plane defects originating from the first region 51 in the region along the second outer sidewall 22B in the chip 2.

[0198] When at least one first region 51 is formed in a region along the second outer wall 22B, it is preferable that the first region 51 is formed in a region along the second outer wall 22B at a distance from the first outer wall 22A in the m-axis direction.

[0199] This structure can reduce the formation area of ​​the first region 51 along the outer sidewall 22. Therefore, it is possible to suppress m-plane defects and a-plane defects originating from the first region 51 in the region along the outer sidewall 22 in the chip 2. Such a structure is particularly effective in suppressing m-plane defects originating from the first region 51 in the region along the first outer sidewall 22A in the chip 2.

[0200] The second region 52 is preferably formed in a region along the bottom wall 23 at a distance from the second outer wall 22B in the a-axis direction. This structure reduces the area in which the second region 52 is formed along the bottom wall 23. This makes it possible to suppress m-plane defects and a-plane defects originating from the second region 52 in the region along the bottom wall 23 in the chip 2. This structure is particularly effective in suppressing a-plane defects originating from the second region 52 in the region along the second outer wall 22B in the chip 2.

[0201] The second region 52 is preferably formed in a region along the bottom wall 23 at a distance from the first outer wall 22A in the m-axis direction. This structure reduces the area in which the second region 52 is formed along the bottom wall 23. This makes it possible to suppress m-plane defects and a-plane defects originating from the second region 52 in the region along the bottom wall 23 in the chip 2. This structure is particularly effective in suppressing m-plane defects originating from the second region 52 in the region along the first outer wall 22A in the chip 2.

[0202] At least one first connection region 54 may be formed on either or both of the first outer wall 22A and the second outer wall 22B. When at least one first connection region 54 is formed in a region along the first outer wall 22A, the first connection region 54 is preferably formed in a region along the first outer wall 22A spaced apart from the second outer wall 22B in the a-axis direction.

[0203] This structure can reduce the area where the first connection region 54 is formed along the outer sidewall 22. This can suppress m-plane defects and a-plane defects originating from the first connection region 54 within the chip 2. This structure is particularly effective in suppressing a-plane defects originating from the first connection region 54 in the region along the second outer sidewall 22B within the chip 2.

[0204] When at least one first connection region 54 is formed in a region along the second outer wall 22B, it is preferable that the first connection region 54 is formed in a region along the second outer wall 22B spaced apart from the first outer wall 22A in the m-axis direction.

[0205] This structure can reduce the formation area of ​​the first connection region 54 along the outer sidewall 22. Therefore, it is possible to suppress m-plane defects and a-plane defects originating from the first connection region 54 in the region along the outer sidewall 22 in the chip 2. This structure is particularly effective in suppressing a-plane defects originating from the first connection region 54 in the region along the first outer sidewall 22A in the chip 2.

[0206] The second trench structure 20 may be formed in a ring shape in a plan view. The second trench structure 20 preferably has a first bottom wall 23A extending in a strip shape in the a-axis direction and a second bottom wall 23B extending in a strip shape in the m-axis direction. In this case, at least one second region 52 may be formed in either or both of the first bottom wall 23A and the second bottom wall 23B.

[0207] When at least one second region 52 is formed in a region along the second bottom wall 23B, the second region 52 is preferably formed in a region along the second bottom wall 23B at a distance from the first bottom wall 23A in the m-axis direction. This structure reduces the area in which the second region 52 is formed along the bottom wall 23. Therefore, m-plane defects and a-plane defects originating from the second region 52 can be suppressed. This structure can suppress m-plane defects originating from the second region 52 in the region along the first bottom wall 23A in the chip 2.

[0208] When at least one second region 52 is formed in a region along the first bottom wall 23A, the second region 52 is preferably formed in a region along the first bottom wall 23A at a distance from the second bottom wall 23B in the a-axis direction. This structure reduces the formation area of ​​the second region 52 along the bottom wall 23. Therefore, m-plane defects and a-plane defects originating from the second region 52 can be suppressed. This structure can suppress a-plane defects originating from the second region 52 in the region along the second bottom wall 23B in the chip 2.

[0209] The SiC semiconductor device 1A may include a first mesa portion 24 defined on the first main surface 3 by the second trench structure 20. In this case, the contact region 50 preferably has a third region 53 located in the surface layer portion of the first main surface 3 in the first mesa portion 24. This structure allows the formation region of the contact region 50 to be expanded by utilizing the first mesa portion 24. Therefore, the contact resistance can be reduced while suppressing crystal defects originating from the second region 52.

[0210] The SiC semiconductor device 1A preferably includes a third trench structure 30 formed on the first main surface 3 at a distance from the second trench structure 20. In this case, the SiC semiconductor device 1A preferably includes an n-type source region 40 formed in a region along the third trench structure 30 in a surface layer portion of the first main surface 3.

[0211] The third trench structure 30 may be formed on the first main surface 3 at a distance in the m-axis direction from the first outer wall 22A of the second trench structure 20 so as to extend in the a-axis direction. The third trench structure 30 may be formed on the first main surface 3 at a distance in the a-axis direction from the second outer wall 22B of the second trench structure 20 so as to extend in the m-axis direction. The third trench structure 30 may be formed in a ring shape surrounding the second trench structure 20 in a plan view. These structures make it possible to suppress crystal defects originating from the second region 52 in the region between the second trench structure 20 and the third trench structure 30.

[0212] From another perspective, as described above, SiC semiconductor device 1A includes chip 2, second trench structure 20 (trench structure), and p-type contact region 50. Chip 2 includes SiC single crystal and has first main surface 3. Second trench structure 20 has inner wall 21 (side wall) and bottom wall 23, and is formed on first main surface 3. Contact region 50 includes third region 53 and second region 52. Third region 53 is formed in a region along inner wall 21 in a surface layer portion of first main surface 3. Second region 52 has a p-type impurity concentration lower than the p-type impurity concentration of third region 53, and is formed in a region along bottom wall 23 within chip 2.

[0213] This structure reduces contact resistance by the third region 53, while suppressing crystal defects originating from the second region 52 in the region along the bottom wall 23 within the chip 2. This provides a SiC semiconductor device 1A with improved electrical characteristics. For example, suppressing crystal defects can suppress leakage current caused by the crystal defects. For example, suppressing crystal defects is effective in suppressing the drain cutoff current IDSS. Furthermore, suppressing crystal defects can suppress an increase in resistance caused by the crystal defects. For example, suppressing crystal defects is effective in suppressing the on-resistance Ron.

[0214] The third region 53 preferably includes a second high-concentration region 53H and a second low-concentration region 53L. The second high-concentration region 53H is located on the first main surface 3 side and has a relatively high p-type impurity concentration. The second low-concentration region 53L has a p-type impurity concentration lower than that of the second high-concentration region 53H and is located on the bottom side. In this case, the second region 52 preferably has a p-type impurity concentration lower than that of the second high-concentration region 53H. This structure allows the third region 53 to be appropriately concentrated while appropriately suppressing the second region 52 from becoming highly concentrated.

[0215] From another perspective, SiC semiconductor device 1A may include chip 2, n-type first semiconductor region 6, p-type body region 12, second trench structure 20 as a trench source structure, third trench structure 30 as a trench gate structure, n-type source region 40, and p-type contact region 50. Chip 2 includes SiC single crystal and has first main surface 3. First semiconductor region 6 is formed in a surface layer portion of first main surface 3.

[0216] The body region 12 is formed in a surface layer portion of the first semiconductor region 6. The second trench structure 20 has outer walls 22 (side walls) and a bottom wall 23, and is formed in the first main surface 3. The third trench structure 30 is formed in the first main surface 3 at a distance from the second trench structure 20 so as to penetrate the body region 12. The source region 40 is formed in a region along the third trench structure 30 in the surface layer portion of the body region 12.

[0217] The contact region 50 includes a first region 51 and a second region 52. The first region 51 is formed in a region along the outer sidewall 22 of the second trench structure 20 in the surface layer portion of the first main surface 3. The second region 52 has a p-type impurity concentration lower than the p-type impurity concentration of the first region 51, and is formed in a region along the bottom wall 23 of the second trench structure 20 within the chip 2.

[0218] This structure can suppress crystal defects originating from the second region 52 in the region between the second trench structure 20 and the third trench structure 30. This makes it possible to provide a SiC semiconductor device 1A that can improve electrical characteristics. For example, suppressing crystal defects can suppress leakage current caused by the crystal defects. For example, suppressing crystal defects is effective in suppressing the drain cutoff current IDSS. Furthermore, suppressing crystal defects can suppress an increase in resistance caused by the crystal defects. For example, suppressing crystal defects is effective in suppressing the on-resistance Ron.

[0219] 18 corresponds to FIG. 8 and is a plan view showing a SiC semiconductor device 1B according to the second embodiment. SiC semiconductor device 1B is a device that achieves the same effects as SiC semiconductor device 1A. The aforementioned SiC semiconductor device 1A includes a contact region 50 having a pair of second regions 52A and a pair of second regions 52B.

[0220] In contrast, the contact region 50 of the SiC semiconductor device 1B does not include the pair of second regions 52B. In this case, it is preferable that the contact region 50 does not include at least one or all of the pair of first regions 51B, the pair of first connection regions 54B, and the pair of second connection regions 55B. The distance between the third trench structure 30B and the second region 52A is greater than the distance between the third trench structure 30A and the second region 52A.

[0221] According to the SiC semiconductor device 1B, the formation area of ​​the second region 52 can be reduced, and crystal defects originating from the second region 52 can be suppressed. Furthermore, this structure can suppress a-plane defects originating from the second region 52 in the region between the second trench structure 20 and the third trench structure 30B (the region extending along the a-plane of the SiC single crystal). Therefore, such a structure is effective in suppressing an increase in resistance value (on-resistance) due to a-plane defects.

[0222] 19 is a plan view showing a SiC semiconductor device 1C according to a third embodiment, corresponding to FIG. 8. SiC semiconductor device 1C has a modified form of contact region 50 in SiC semiconductor device 1B, and is a device that achieves the same effects as SiC semiconductor device 1B.

[0223] Specifically, the contact region 50 of the SiC semiconductor device 1C includes a third region 53 extending in a band shape in the m-axis direction at a distance from the pair of second inner side walls 21B in the a-axis direction. In this case, it is preferable that the contact region 50 does not include a pair of second connection regions 55B. In other words, it is preferable that the contact region 50 is formed in a band shape extending in the m-axis direction at a distance from the pair of second inner side walls 21B in a plan view.

[0224] 20 corresponds to FIG. 8 and is a plan view showing a SiC semiconductor device 1D according to the fourth embodiment. The SiC semiconductor device 1D is a device that achieves the same effects as the SiC semiconductor device 1A. The aforementioned SiC semiconductor device 1A includes a contact region 50 having a pair of second regions 52A and a pair of second regions 52B.

[0225] In contrast, the contact region 50 of the SiC semiconductor device 1D does not include the pair of second regions 52A. In this case, it is preferable that the contact region 50 does not include at least one or all of the pair of first regions 51A, the pair of first connection regions 54A, and the pair of second connection regions 55A. The distance between the third trench structure 30A and the second region 52B is greater than the distance between the third trench structure 30B and the second region 52A.

[0226] This structure reduces the formation area of ​​the second region 52, thereby suppressing crystal defects originating from the second region 52. Furthermore, this structure also suppresses m-plane defects originating from the second region 52 in the region between the second trench structure 20 and the third trench structure 30A (the region extending along the m-plane of the SiC single crystal). Therefore, such a structure is effective in suppressing an increase in leakage current (drain cutoff current IDSS) caused by m-plane defects.

[0227] 21 corresponds to FIG. 8 and is a plan view showing a SiC semiconductor device 1E according to the fifth embodiment. SiC semiconductor device 1E has a modified form of contact region 50 of SiC semiconductor device 1D and is a device that achieves the same effects as SiC semiconductor device 1D. Specifically, contact region 50 of SiC semiconductor device 1E includes third regions 53 that extend in a strip-like shape in the a-axis direction at an interval in the m-axis direction from a pair of first inner side walls 21A.

[0228] In this case, it is preferable that the contact region 50 does not include the pair of second connection regions 55A. In other words, it is preferable that the contact region 50 is formed in a strip shape extending in the a-axis direction at an interval in the m-axis direction from the pair of first inner side walls 21A in a plan view.

[0229] The contact region 50 of the SiC semiconductor device 1E may be formed simultaneously with the contact region 50 of the SiC semiconductor device 1C. In this case, a cross-shaped contact region 50 is formed having a portion extending in a strip shape in the a-axis direction and a portion extending in a strip shape in the m-axis direction in plan view.

[0230] 22 corresponds to FIG. 8 and is a plan view showing a SiC semiconductor device 1F according to a sixth embodiment. The SiC semiconductor device 1F is a device that achieves the same effects as the SiC semiconductor device 1A. The aforementioned SiC semiconductor device 1A includes a contact region 50 having a pair of second regions 52A and a pair of second regions 52B.

[0231] In contrast, contact region 50 of SiC semiconductor device 1F includes one second region 52A and one second region 52B. Contact region 50 includes one first region 51A, one first region 51B, one first connection region 54A, one first connection region 54B, one second connection region 55A, and one second connection region 55B, corresponding to one second region 52A and one second region 52B.

[0232] One first connection region 54A connects one first region 51A and one second region 52A. One first connection region 54B connects one first region 51B and one second region 52B. One second connection region 55A connects one second region 52A and one third region 53. One second connection region 55B connects one second region 52B and one third region 53.

[0233] In this embodiment, similarly to the first embodiment, the third region 53 is formed throughout the surface layer portion of the body region 12 within the first mesa portion 24. Of course, the third region 53 may extend in an L-shape between one second region 52A and one second region 52B in a plan view.

[0234] When considering one second trench structure 20 and the other second trench structure 20, the location where the second region 52A is formed for one second trench structure 20 may be the same as or different from the location where the second region 52A is formed for the other second trench structure 20. Furthermore, when considering one second trench structure 20 and the other second trench structure 20, the location where the second region 52B is formed for one second trench structure 20 may be the same as or different from the location where the second region 52B is formed for the other second trench structure 20.

[0235] This structure can suppress m-plane defects and a-plane defects originating from the second region 52. Such a structure is effective in suppressing an increase in resistance (on-resistance) caused by a-plane defects and suppressing an increase in leakage current (drain cutoff current IDSS) caused by m-plane defects.

[0236] 23 is a plan view showing a SiC semiconductor device 1G according to the seventh embodiment. The SiC semiconductor device 1G is a device that achieves the same effects as the SiC semiconductor device 1A. The SiC semiconductor device 1A includes a pair of first regions 51A formed in regions that extend along portions of the pair of first outer side walls 22A, and a pair of first regions 51B formed in regions that extend along portions of the pair of second outer side walls 22B.

[0237] In contrast, the SiC semiconductor device 1G includes a pair of first regions 51A formed in regions extending along the entire areas of the pair of first outer walls 22A and a pair of first regions 51B formed in regions extending along the entire areas of the pair of second outer walls 22B. In other words, in this embodiment, the contact region 50 includes one first region 51 surrounding the outer wall 22 of the second trench structure 20.

[0238] In this case, the contact region 50 may include a pair of second regions 52A formed in an area extending along the entire area of ​​the pair of second bottom walls 23B, and a pair of second regions 52B formed in an area extending along the entire area of ​​the pair of second bottom walls 23B. In other words, the contact region 50 may include one second region 52 formed in an area extending along the entire area of ​​the bottom wall 23.

[0239] Furthermore, the contact region 50 may include a pair of first connection regions 54A formed in a region that extends along the entire area of ​​the pair of first outer walls 22A, and a pair of first connection regions 54B formed in a region that extends along the entire area of ​​the pair of second outer walls 22B. In other words, the contact region 50 may include one first connection region 54 formed in a region that extends along the entire area of ​​the outer wall 22.

[0240] Furthermore, the contact region 50 may include a pair of second connection regions 55A formed in a region that extends along the entire area of ​​the pair of first inner walls 21A, and a pair of second connection regions 55B formed in a region that extends along the entire area of ​​the pair of second inner walls 21B. In other words, the contact region 50 may include one second connection region 55 formed in a region that extends along the entire area of ​​the inner wall 21.

[0241] 24 corresponds to FIG. 8 and is a plan view showing a SiC semiconductor device 1H according to the eighth embodiment. The SiC semiconductor device 1H is a device that achieves the same effects as the SiC semiconductor device 1A. The aforementioned SiC semiconductor device 1A includes a contact region 50 having a first region 51, a second region 52, and a third region 53. In contrast, the contact region 50 of the SiC semiconductor device 1H includes the second region 52 and the third region 53, but does not include the first region 51. In this case, it is preferable that the contact region 50 does not include the first connection region 54.

[0242] Fig. 25 corresponds to Fig. 8 and is a plan view showing a SiC semiconductor device 1I according to the ninth embodiment. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI shown in Fig. 25. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII shown in Fig. 25. Fig. 28A is an enlarged cross-sectional view showing the configuration when a region including second trench structure 20 and contact region 50 is cut in the m-axis direction. Fig. 28B is an enlarged cross-sectional view showing the configuration when a region including second trench structure 20 and contact region 50 is cut in the a-axis direction.

[0243] The SiC semiconductor device 1I is a device that achieves the same effects as the SiC semiconductor device 1A. The aforementioned SiC semiconductor device 1A includes a second trench structure 20 formed in an annular shape extending in the a-axis direction and the m-axis direction in a plan view. In contrast, the SiC semiconductor device 1I includes a second trench structure 20 formed in a quadrangular shape having four sides extending in the a-axis direction and the m-axis direction in a plan view. The second trench structure 20 includes a second trench 25, a second insulating film 26, and a second buried electrode 27, as in the first embodiment.

[0244] In this embodiment, the second trench structure 20 includes sidewalls 90 and a bottom wall 91. The sidewalls 90 are formed in a rectangular shape extending in the a-axis direction and the m-axis direction in a plan view. Specifically, the sidewalls 90 include a pair of first sidewalls 90A and a pair of second sidewalls 90B. The pair of first sidewalls 90A extend in the a-axis direction and face each other in the m-axis direction. That is, the pair of first sidewalls 90A are defined by an m-plane. The pair of second sidewalls 90B extend in the m-axis direction to be connected to the pair of first sidewalls 90A and face each other in the a-axis direction. That is, the pair of second sidewalls 90B are defined by an a-plane.

[0245] Bottom wall 91 is formed in a rectangular shape extending flat along the a-axis and m-axis directions in a plan view, and connects a pair of first side walls 90A and a pair of second side walls 90B. Bottom wall 91 is formed by the c-plane. When active surface 8 (first main surface 3) has an off-angle tilted at a predetermined angle in a predetermined off-direction with respect to the c-plane, bottom wall 91 may have an off-direction and off-angle similar to active surface 8 (first main surface 3).

[0246] As in the first embodiment, the third trench structure 30 is formed in a lattice shape (annular shape) extending in the a-axis direction and the m-axis direction in the regions between the second trench structures 20 so as to surround the second trench structures 20 in a plan view. In this embodiment, the third trench structure 30 defines a plurality of mesa portions 92 extending annularly (specifically, quadrangularly) between itself and the sidewalls 90 of the second trench structures 20.

[0247] As in the first embodiment, the third trench structure 30 includes a plurality of third trench structures 30A and a plurality of third trench structures 30B. In this embodiment, the plurality of third trench structures 30A are formed at intervals in the m-axis direction from the plurality of first sidewalls 90A so as to face the plurality of first sidewalls 90A in the m-axis direction, and extend in a band-like manner in the a-axis direction through the region between the plurality of first sidewalls 90A. In this embodiment, the plurality of third trench structures 30B are formed at intervals in the a-axis direction from the plurality of second sidewalls 90B so as to face the plurality of second sidewalls 90B in the a-axis direction, and extend in a band-like manner in the m-axis direction through the region between the plurality of second sidewalls 90B.

[0248] In this embodiment, the well region 41 includes a well bottom wall 42 and a second well sidewall 44, but does not include the first well sidewall 43. The second well sidewall 44 may be simply referred to as a "well sidewall." The well bottom wall 42 is formed in a region along the bottom wall 91 of the second trench structure 20. Specifically, the well bottom wall 42 covers the entire bottom wall 91. The well bottom wall 42 is formed at a distance from the bottom of the first semiconductor region 6 toward the active surface 8, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6.

[0249] The second well sidewall portion 44 is extended from the well bottom wall portion 42 side toward the sidewall 90 of the second trench structure 20 and is formed in a region along the sidewall 90. Specifically, the second well sidewall portion 44 is formed in a region along the pair of first sidewalls 90A and the pair of second sidewalls 90B in the mesa portion 92.

[0250] The second well sidewall 44 is formed in a ring shape (specifically, a square ring shape) surrounding the second trench structure 20 at a distance from the third trench structure 30 in the mesa portion 92. The second well sidewall 44 is connected to the body region 12 in a surface layer portion of the mesa portion 92. The thickness of the second well sidewall 44 measured from the sidewall 90 is smaller than the thickness of the well bottom wall 42 measured from the bottom wall 91.

[0251] In this embodiment, the contact region 50 includes a first region 51, a second region 52, and a first connection region 54, but does not include a third region 53 or a second connection region 55. The first connection region 54 may be simply referred to as a "connection region." The first region 51 includes a pair of first regions 51A and a pair of first regions 51B, as in the first embodiment.

[0252] In this embodiment, the pair of first regions 51A are formed in regions along the pair of first sidewalls 90A of the second trench structure 20. The pair of first regions 51A are preferably formed to be narrower in the a-axis direction than the first sidewalls 90A. The pair of first regions 51A are formed in regions along the pair of first sidewalls 90A and spaced apart in the a-axis direction from the pair of second sidewalls 90B.

[0253] The pair of first regions 51A preferably face each other in the m-axis direction. The pair of first regions 51A are preferably formed in regions along the central portions of the pair of first side walls 90A. Of course, the pair of first regions 51A may be shifted from each other in the a-axis direction so as not to face each other in the m-axis direction.

[0254] The width of each first region 51A in the a-axis direction is preferably ½ or less of the width of the first side wall 90A in the a-axis direction. It is particularly preferable that the width of each first region 51A in the a-axis direction be ¼ or less of the width of the first side wall 90A in the a-axis direction. The width of each first region 51A in the a-axis direction may be 1 / 10 or more of the width of the first side wall 90A in the a-axis direction.

[0255] In this embodiment, the pair of first regions 51B are formed in regions along the pair of second sidewalls 90B of the second trench structure 20. The pair of first regions 51B are preferably formed to be narrower in the m-axis direction than the second sidewalls 90B. The pair of first regions 51B are formed in regions along the pair of second sidewalls 90B and spaced apart in the m-axis direction from the pair of first sidewalls 90A.

[0256] The pair of first regions 51B preferably face each other in the a-axis direction. The pair of first regions 51B are preferably formed in a region along the center of the second side wall 90B. Of course, the pair of first regions 51B may be shifted from each other in the m-axis direction so as not to face each other in the a-axis direction.

[0257] The width of each first region 51B in the m-axis direction is preferably ½ or less of the width of the second side wall 90B in the m-axis direction. It is particularly preferable that the width of each first region 51B in the m-axis direction be ¼ or less of the width of the second side wall 90B in the m-axis direction. The width of each first region 51B in the m-axis direction may be 1 / 10 or more of the width of the second side wall 90B in the m-axis direction.

[0258] As in the first embodiment, the first region 51 includes a first high-concentration region 51H on the active surface 8 side and a first low-concentration region 51L on the bottom side. Other configurations of the first region 51 are the same as in the first embodiment, and therefore other descriptions of the first region 51 will be omitted.

[0259] In this embodiment, the second region 52 covers the entire bottom wall 91 of the second trench structure 20. As in the first embodiment, the second region 52 has a p-type impurity concentration that is lower than the p-type impurity concentration of the first region 51. Other configurations of the second region 52 are the same as in the first embodiment, and therefore other descriptions of the second region 52 will be omitted.

[0260] As in the first embodiment, the first connection region 54 includes a pair of first connection regions 54A and a pair of first connection regions 54B. The pair of first connection regions 54A are formed in regions along the corresponding first outer side walls 22A so as to connect the first region 51A and the second region 52 that are adjacent in the up-down direction. It is preferable that the pair of first connection regions 54A be formed narrower in the a-axis direction than the first side walls 90A.

[0261] The pair of first connection regions 54A are formed in regions along the pair of first side walls 90A and spaced apart from the pair of second side walls 90B in the a-axis direction. The pair of first connection regions 54A are preferably formed in regions along the central portions of the pair of first side walls 90A. The formation locations of the pair of first connection regions 54A are adjusted depending on the formation locations of the corresponding first regions 51A.

[0262] The width of each first connection region 54A in the a-axis direction is preferably ½ or less of the width of the first sidewall 90A in the a-axis direction. It is particularly preferable that the width of each first connection region 54A in the a-axis direction be ¼ or less of the width of the first sidewall 90A in the a-axis direction. The width of each first connection region 54A in the a-axis direction may be 1 / 10 or more of the width of the first sidewall 90A in the a-axis direction. It is preferable that the width of each first connection region 54A in the a-axis direction be approximately equal to the width of each first region 51A in the a-axis direction.

[0263] The pair of first connection regions 54B are formed in regions along the corresponding second side walls 90B so as to connect the first region 51B and the second region 52 that are adjacent in the vertical direction. The pair of first connection regions 54B are preferably formed to be narrower in the m-axis direction than the second side walls 90B.

[0264] The pair of first connection regions 54B are formed in regions along the pair of second side walls 90B at intervals in the m-axis direction from the pair of first side walls 90A. The pair of first connection regions 54A are preferably formed in regions along the centers of the pair of second side walls 90B. The formation locations of the pair of first connection regions 54B are adjusted depending on the formation locations of the corresponding first regions 51B.

[0265] The width of each first connection region 54B in the m-axis direction is preferably ½ or less of the width of the second side wall 90B in the m-axis direction. It is particularly preferable that the width of each first connection region 54B in the m-axis direction be ¼ or less of the width of the second side wall 90B in the m-axis direction. The width of each first connection region 54B in the m-axis direction may be 1 / 10 or more of the width of the second side wall 90B in the m-axis direction. It is preferable that the width of each first connection region 54B in the m-axis direction be approximately equal to the width of each first region 51B in the m-axis direction.

[0266] The thickness of the first connection region 54 measured from the sidewall 90 is smaller than the thickness of the first region 51 measured from the active surface 8. The thickness of the first connection region 54 measured from the sidewall 90 is smaller than the thickness of the second region 52 measured from the bottom wall 23 of the second trench structure 20. Other configurations of the first connection region 54 are the same as those in the first embodiment, and therefore other descriptions of the first connection region 54 will be omitted.

[0267] 29 corresponds to FIG. 25 and is a plan view showing a SiC semiconductor device 1J according to the tenth embodiment. The SiC semiconductor device 1J is a device that achieves the same effects as the SiC semiconductor device 1I. The aforementioned SiC semiconductor device 1I includes a contact region 50 having a pair of first regions 51A and a pair of first regions 51B. In contrast, the contact region 50 of the SiC semiconductor device 1J does not include a pair of first regions 51B. In this case, it is preferable that the contact region 50 does not include a pair of first connection regions 54B.

[0268] This structure reduces the formation area of ​​the first region 51, thereby suppressing crystal defects originating from the first region 51. Furthermore, this structure also suppresses a-plane defects originating from the first region 51 in the region between the second trench structure 20 and the third trench structure 30B (the region extending along the a-plane of the SiC single crystal). Therefore, such a structure is effective in suppressing an increase in resistance (on-resistance) due to a-plane defects.

[0269] 30 corresponds to FIG. 25 and is a plan view showing a SiC semiconductor device 1K according to the eleventh embodiment. The SiC semiconductor device 1K has a modified form of the contact region 50 of the SiC semiconductor device 1J, and is a device that achieves the same effects as the SiC semiconductor device 1I. Specifically, the contact region 50 of the SiC semiconductor device 1K includes second regions 52 that extend in a strip shape in the m-axis direction at a distance from a pair of second sidewalls 90B in the a-axis direction.

[0270] The second region 52 extends in a band shape in the m-axis direction in the region between the pair of first regions 51A. The distance between the third trench structure 30B and the second region 52 is greater than the distance between the third trench structure 30A and the second region 52. The pair of first connection regions 54A connect the second region 52 to the pair of first regions 51A. As a result, the contact region 50 is formed in a band shape extending in the m-axis direction at a distance from the pair of second sidewalls 90B in a plan view.

[0271] This structure reduces the formation area of ​​the second region 52, thereby suppressing crystal defects originating from the second region 52. Furthermore, this structure also suppresses a-plane defects originating from the second region 52 in the region between the second trench structure 20 and the third trench structure 30B (the region extending along the a-plane of the SiC single crystal). Therefore, such a structure is effective in suppressing an increase in resistance (on-resistance) due to a-plane defects.

[0272] 31 corresponds to FIG. 25 and is a plan view showing a SiC semiconductor device 1L according to the twelfth embodiment. The SiC semiconductor device 1L is a device that achieves the same effects as the SiC semiconductor device 1I. The SiC semiconductor device 1I described above includes a contact region 50 having a pair of first regions 51A and a pair of first regions 51B. In contrast, the contact region 50 of the SiC semiconductor device 1L does not include a pair of first regions 51A. In this case, it is preferable that the contact region 50 does not include a pair of first connection regions 54A.

[0273] This structure reduces the formation area of ​​the first region 51, thereby suppressing crystal defects originating from the first region 51. This structure also suppresses m-plane defects originating from the first region 51 in the region between the second trench structure 20 and the third trench structure 30A (the region extending along the m-plane of the SiC single crystal). Therefore, such a structure is effective in suppressing an increase in resistance (on-resistance) due to m-plane defects.

[0274] 32 corresponds to FIG. 25 and is a plan view showing a SiC semiconductor device 1M according to the thirteenth embodiment. The SiC semiconductor device 1M has a modified form of the contact region 50 of the SiC semiconductor device 1L, and is a device that achieves the same effects as the SiC semiconductor device 1I. Specifically, the contact region 50 of the SiC semiconductor device 1M includes second regions 52 that extend in a strip shape in the a-axis direction at an interval in the m-axis direction from a pair of first sidewalls 90A.

[0275] The second region 52 extends in a band shape in the a-axis direction in the region between the pair of first regions 51B. The distance between the third trench structure 30A and the second region 52 is greater than the distance between the third trench structure 30B and the second region 52. The pair of first connection regions 54B connect the second region 52 to the pair of first regions 51B. As a result, the contact region 50 is formed in a band shape extending in the a-axis direction at a distance in the m-axis direction from the pair of first sidewalls 90A in a plan view.

[0276] This structure reduces the formation area of ​​the second region 52, thereby suppressing crystal defects originating from the second region 52. Furthermore, this structure also suppresses m-plane defects originating from the second region 52 in the region between the second trench structure 20 and the third trench structure 30A (the region extending along the m-plane of the SiC single crystal). Therefore, such a structure is effective in suppressing an increase in leakage current (drain cutoff current IDSS) caused by m-plane defects.

[0277] The contact region 50 of the SiC semiconductor device 1M may be formed simultaneously with the contact region 50 of the SiC semiconductor device 1K. In this case, a cross-shaped contact region 50 is formed having a portion extending in a strip shape in the a-axis direction and a portion extending in a strip shape in the m-axis direction in plan view.

[0278] 33 corresponds to FIG. 25 and is a plan view showing a SiC semiconductor device 1N according to the fourteenth embodiment. The SiC semiconductor device 1N is a device that achieves the same effects as the SiC semiconductor device 1I. The aforementioned SiC semiconductor device 1I includes a contact region 50 having a pair of first regions 51A and a pair of first regions 51B.

[0279] In contrast, the contact region 50 of the SiC semiconductor device 1N includes one first region 51A and one first region 51B. The contact region 50 includes one first connection region 54A and one first connection region 54B corresponding to the one first region 51A and one first region 51B.

[0280] One first connection region 54A connects the first region 51A and the second region 52. One first connection region 54B connects the first region 51B and the second region 52. In this embodiment, the second region 52 covers the entire bottom wall 91 of the second trench structure 20. Of course, the second region 52 may extend in an L-shape between the first region 51A and the first region 51B in a plan view.

[0281] When considering one second trench structure 20 and the other second trench structure 20, the location where the first region 51A is formed for one second trench structure 20 may be the same as or different from the location where the first region 51A is formed for the other second trench structure 20. Furthermore, when considering one second trench structure 20 and the other second trench structure 20, the location where the first region 51B is formed for one second trench structure 20 may be the same as or different from the location where the first region 51B is formed for the other second trench structure 20.

[0282] This structure can suppress m-plane defects and a-plane defects originating from the first region 51. Such a structure is effective in suppressing an increase in resistance (on-resistance) caused by a-plane defects and suppressing an increase in leakage current (drain cutoff current IDSS) caused by m-plane defects.

[0283] 34 corresponds to FIG. 25 and is a plan view showing a SiC semiconductor device 1O according to the fifteenth embodiment. The SiC semiconductor device 1O is a device that achieves the same effects as the SiC semiconductor device 1I. The SiC semiconductor device 1I described above includes a pair of first regions 51A formed in regions along portions of the pair of first side walls 90A and a pair of first regions 51B formed in regions along portions of the pair of second side walls 90B.

[0284] In contrast, the SiC semiconductor device 1O includes a pair of first regions 51A formed in regions extending along the entire areas of the pair of first sidewalls 90A and a pair of first regions 51B formed in regions extending along the entire areas of the pair of second sidewalls 90B. That is, in this embodiment, the contact region 50 includes one first region 51 surrounding the sidewall 90 of the second trench structure 20.

[0285] Furthermore, the contact region 50 may include a pair of first connection regions 54A formed in a region that extends along the entire area of ​​the pair of first side walls 90A, and a pair of first connection regions 54B formed in a region that extends along the entire area of ​​the pair of second side walls 90B. In other words, the contact region 50 may include one first connection region 54 formed in a region that extends along the entire area of ​​the side wall 90.

[0286] Fig. 35 is a cross-sectional view showing a modified example of the second trench structure 20. Fig. 35 shows an example in which the modified second trench structure 20 is applied to the SiC semiconductor device 1A according to the first embodiment, but the modified second trench structure 20 may also be applied to the SiC semiconductor devices 1B to 1O according to the second to fifteenth embodiments.

[0287] The second trench structure 20 according to each of the above-described embodiments includes a second trench 25, a second insulating film 26, and a second buried electrode 27. In contrast, the second trench structure 20 according to the modified example does not include the second insulating film 26. The second buried electrode 27 is buried directly in the second trench 25, and is electrically and mechanically connected to the chip 2 within the second trench 25.

[0288] The aforementioned source region 40, well region 41 and contact region 50 are electrically and mechanically connected to the second buried electrode 27 in the portions along the wall surfaces (inner sidewall 21, outer sidewall 22 and bottom wall 23) of the second trench structure 20.

[0289] The second buried electrode 27 may be formed by utilizing a part of the source electrode 85 (source pad electrode 86). In other words, the source electrode 85 (source pad electrode 86) may be formed so as to extend from above the main surface insulating film 70 (active surface 8) into the plurality of second trenches 25. In this case, the source electrode 85 (source pad electrode 86) includes the plurality of second buried electrodes 27 electrically and mechanically connected to the chip 2 in the plurality of second trenches 25.

[0290] The above-described embodiments can be implemented in other forms. In the above-described embodiments, an example was shown in which the second semiconductor region 7 was formed in the chip 2. However, a structure without the second semiconductor region 7 may be employed. In this case, the first semiconductor region 6 is exposed from the first main surface 3, the second main surface 4, and the first to fourth side surfaces 5A to 5D of the chip 2. In other words, the chip 2 may have a single-layer structure made of a SiC epitaxial layer without including a SiC substrate.

[0291] In each of the above-described embodiments, an "n-type" region may be replaced with a "p-type" region, and a "p-type" region may be replaced with an "n-type" region. A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings. When "p-type" is referred to as the "first conductivity type," "n-type" may be referred to as the "second conductivity type." When "n-type" is referred to as the "first conductivity type," "p-type" may be referred to as the "second conductivity type."

[0292] In the above-described embodiments, the second semiconductor region 7 is of "n-type." However, a second semiconductor region 7 of "p-type" may be employed. In this case, a SiC-IGBT (Insulated Gate Bipolar Transistor) is formed instead of the SiC-MISFET. In this case, in the above description, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT. The second semiconductor region 7 of "p-type" may be made of a "p-type" SiC substrate, or may be formed by introducing p-type impurities into the surface layer of the second main surface 4 of the chip 2 (epitaxial layer) by ion implantation.

[0293] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each item to the embodiments. The "SiC semiconductor device" in the following items may be replaced with "semiconductor device," "SiC semiconductor switching device," or "SiC-MISFET" as necessary.

[0294] [A1] A SiC semiconductor device (1A-1O) including: a chip (2) including a SiC single crystal and having a main surface (3); a trench structure (20) having side walls (21, 22, 90) and a bottom wall (23, 91) and formed in the main surface (3); a first region (51, 53) formed in a surface portion of the main surface (3) along the side walls (21, 22, 90); and a contact region (50) of a first conductivity type (p-type) including a second region (52) formed in a region along the bottom wall (23, 91) within the chip (2) and having an impurity concentration lower than the impurity concentration of the first region (51, 53).

[0295] [A2] The SiC semiconductor device (1A to 1O) according to A1, wherein a source potential is applied to the trench structure (20).

[0296] [A3] The SiC semiconductor device (1A-1O) according to A1 or A2, wherein the first region (51, 53) includes a high concentration region (51H, 53H) located on the main surface (3) side and a low concentration region (51L, 53L) located on the bottom side and having an impurity concentration lower than the impurity concentration of the high concentration region (51H, 53H), and the second region (52) has an impurity concentration lower than the impurity concentration of the high concentration region (51H, 53H).

[0297] [A4] The SiC semiconductor device (1A-1O) according to any one of A1 to A3, further comprising a body region (12) of a first conductivity type (p-type) formed in a surface layer portion of the main surface (3), the trench structure (20) being formed in the main surface (3) so as to penetrate the body region (12), the first region (51, 53) having an impurity concentration higher than the impurity concentration of the body region (12), and formed in a surface layer portion of the body region (12), and the second region (52) having an impurity concentration higher than the impurity concentration of the body region (12).

[0298] [A5] The SiC semiconductor device (1A-1O) according to any one of A1 to A4, further including a well region (41) of a first conductivity type (p-type) formed in a region along the bottom wall (23, 91) in the chip (2), wherein the first region (51, 53) has an impurity concentration higher than the impurity concentration of the well region (41), and the second region (52) has an impurity concentration higher than the impurity concentration of the well region (41), and is formed in the well region (41) in a region along the bottom wall (23, 91).

[0299] [A6] The SiC semiconductor device (1A-1O) described in any one of A1 to A5, wherein the contact region (50) further includes a connection region (54, 55) formed in a region along the sidewall (21, 22, 90) within the chip (2) to connect the first region (51, 53) and the second region (52).

[0300] [A7] The SiC semiconductor device (1A-1O) according to A6, wherein the connection region (54, 55) has an impurity concentration lower than the impurity concentration of the first region (51, 53).

[0301] [A8] The SiC semiconductor device (1A-1O) described in A6 or A7, wherein the thickness of the connection region (54, 55) based on the side wall (21, 22, 90) is smaller than the thickness of the first region (51, 53) based on the main surface (3).

[0302] [A9] A SiC semiconductor device (1A-1O) described in any one of A6 to A8, wherein the thickness of the connection region (54, 55) based on the side wall (21, 22, 90) is smaller than the thickness of the second region (52) based on the bottom wall (23, 91).

[0303] [A10] The SiC semiconductor device (1A-1O) described in any one of A1 to A9, wherein the chip (2) includes the SiC single crystal consisting of a hexagonal crystal, and the side walls (21, 22, 90) include a first side wall (21A, 22A, 90A) extending in the a-axis direction of the SiC single crystal and a second side wall (21B, 22B, 90B) extending in the m-axis direction of the SiC single crystal.

[0304] [A11] The SiC semiconductor device (1A-1O) according to A10, wherein the first region (51, 53) is formed in a region along the first side wall (21A, 22A, 90A).

[0305] [A12] The SiC semiconductor device (1A-1O) described in A11, wherein the first region (51, 53) is formed in a region along the first side wall (21A, 22A, 90A) at a distance from the second side wall (21B, 22B, 90B) in the a-axis direction.

[0306] [A13] A SiC semiconductor device (1A-1O) according to any one of A10 to A12, wherein at least one of the first regions (51, 53) is formed in a region along the second sidewall (21B, 22B, 90B).

[0307] [A14] The SiC semiconductor device (1A-1O) described in A13, wherein the first region (51, 53) is formed in a region along the second side wall (21B, 22B, 90B) at a distance from the first side wall (21A, 22A, 90A) in the m-axis direction.

[0308] [A15] The SiC semiconductor device (1A-1O) according to any one of A1 to A14, further comprising a second trench structure (30) formed on the main surface (3) at a distance from the trench structure (20) and to which a gate potential is applied.

[0309] [A16] The SiC semiconductor device (1A-1O) according to A15, wherein the first region (51, 53) is formed at an interval from the second trench structure (30) toward the trench structure (20).

[0310] [A17] The SiC semiconductor device (1A-1O) according to A15 or A16, wherein the second trench structure (30) is formed in a ring shape surrounding the trench structure (20) in a planar view.

[0311] [A18] The SiC semiconductor device (1A-1O) according to any one of A15 to A17, further comprising a second conductivity type source region formed in a region along the second trench structure (30) in the surface layer portion of the main surface (3).

[0312] [A19] The SiC semiconductor device (1A to 1O) according to A18, wherein the first region (51, 53) is connected to the source region.

[0313] [A20] A chip (2) including a SiC single crystal and having a main surface (3), a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3), a body region (12) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (6), a trench source structure (20) having sidewalls (21, 22, 90) and a bottom wall (23, 91) and formed in the main surface (3) so as to penetrate the body region (12), a trench gate structure (30) formed in the main surface (3) at a distance from the trench source structure (20) so as to penetrate the body region (12), and a trench gate structure (30) formed in the main surface (3) so as to penetrate the body region (12). a first conductivity type (n-type) source region formed in a region along the trench gate structure (30) in a surface layer portion of the body region (12); first regions (51, 53) formed in a region along the side walls (21, 22, 90) of the trench source structure (20) in a surface layer portion of the body region (12); and a first conductivity type (p-type) contact region (50) including a second region (52) formed in a region along the bottom wall (23, 91) of the trench source structure (20) in the chip (2), the second region (52) having an impurity concentration lower than the impurity concentration of the first regions (51, 53).

[0314] Although the embodiments have been described in detail above, these are merely specific examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiments.

[0315] 1A SiC semiconductor device 1B SiC semiconductor device 1C SiC semiconductor device 1D SiC semiconductor device 1E SiC semiconductor device 1F SiC semiconductor device 1G SiC semiconductor device 1H SiC semiconductor device 1I SiC semiconductor device 1J SiC semiconductor device 1K SiC semiconductor device 1L SiC semiconductor device 1M SiC semiconductor device 1O SiC semiconductor device 2 Chip 3 First main surface 6 First semiconductor region 12 Body region 20 Second trench structure 21 Inner side wall 21A First inner side wall 21B Second inner side wall 22 Outer side wall 22A First outer side wall 22B Second outer side wall 23 Bottom wall 23A First bottom wall 23B Second bottom wall 30 Third trench structure 41 Well region 50 Contact region 51 First region 51H First high concentration region 51L First low concentration region 52 Second region 53 Third region 53H Second high concentration region 53L Second low concentration region 54 First connection region 55 Second connection region 90 Side wall 90A First side wall 90B Second side wall 91 Bottom wall

Claims

1. A chip including a SiC single crystal and having a main surface; a trench structure formed in the major surface, the trench structure having sidewalls and a bottom wall; a first region formed in a surface portion of the main surface in a region along the side wall, and a first conductivity type contact region including a second region formed in the chip in a region along the bottom wall and having an impurity concentration lower than an impurity concentration of the first region.

2. The SiC semiconductor device according to claim 1 , wherein a source potential is applied to said trench structure.

3. the first region includes a high concentration region located on the main surface side, and a low concentration region located on a bottom side and having an impurity concentration lower than the impurity concentration of the high concentration region; The SiC semiconductor device according to claim 1 , wherein the second region has an impurity concentration lower than an impurity concentration of the high concentration region.

4. The chip includes the SiC single crystal having a hexagonal crystal structure, 2. The SiC semiconductor device according to claim 1, wherein the sidewalls include a first sidewall extending in an a-axis direction of the SiC single crystal, and a second sidewall extending in an m-axis direction of the SiC single crystal.

5. The SiC semiconductor device according to claim 4 , wherein said first region is formed in a region along said first sidewall.

6. The SiC semiconductor device according to claim 5 , wherein the first region is formed in a region along the first sidewall and spaced from the second sidewall in the a-axis direction.

7. The SiC semiconductor device according to claim 4 , wherein said first region is formed in a region along said second sidewall.

8. The SiC semiconductor device according to claim 7 , wherein the first region is formed in a region along the second sidewall and spaced from the first sidewall in the m-axis direction.

9. A SiC semiconductor device as described in claim 1, wherein the contact region includes a connection region formed in a region along the sidewall within the chip to connect the first region and the second region.

10. A SiC semiconductor device as described in claim 9, wherein the connection region has an impurity concentration lower than the impurity concentration of the first region.

11. A SiC semiconductor device as described in Claim 9, wherein a thickness of the connection region based on the sidewall is smaller than a thickness of the first region based on the main surface.

12. A SiC semiconductor device as described in claim 9, wherein the thickness of the connection region based on the side wall is smaller than the thickness of the second region based on the bottom wall.

13. The semiconductor device further includes a body region of a first conductivity type formed in a surface layer portion of the main surface, the trench structure is formed in the main surface so as to penetrate the body region; the first region has an impurity concentration higher than an impurity concentration of the body region and is formed in a surface layer portion of the body region; The SiC semiconductor device according to any one of claims 1 to 12, wherein the second region has an impurity concentration higher than an impurity concentration of the body region.

14. The semiconductor device further includes a well region of a first conductivity type formed in a region along the bottom wall within the chip, the first region has an impurity concentration higher than an impurity concentration of the well region; The SiC semiconductor device according to any one of claims 1 to 12, wherein the second region has an impurity concentration higher than an impurity concentration of the well region, and is formed in a region along the bottom wall within the well region.

15. The SiC semiconductor device according to any one of claims 1 to 12, further comprising a second trench structure formed in the main surface at a distance from the trench structure and to which a gate potential is applied.

16. The SiC semiconductor device according to claim 15 , wherein the first region is formed at a distance from the second trench structure toward the trench structure.

17. The SiC semiconductor device according to claim 15 , wherein the second trench structure is formed in a ring shape surrounding the trench structure in a plan view.

18. The SiC semiconductor device according to claim 15 , further comprising a second conductivity type source region formed in a surface layer portion of the main surface in a region along the second trench structure.

19. The SiC semiconductor device of claim 18 , wherein the first region is connected to the source region.

20. A chip including a SiC single crystal and having a main surface; a first conductivity type semiconductor region formed in a surface layer portion of the main surface; a body region of a second conductivity type formed in a surface layer portion of the semiconductor region; a trench source structure formed in the major surface through the body region, the trench source structure having sidewalls and a bottom wall; a trench gate structure formed in the major surface and spaced from the trench source structure so as to penetrate the body region; a first conductivity type source region formed in a surface portion of the body region along the trench gate structure; a first region formed in a surface portion of the body region in a region along the side wall of the trench source structure, and a second conductivity type contact region formed in the chip in a region along the bottom wall of the trench source structure, the second conductivity type contact region including a second region having an impurity concentration lower than an impurity concentration of the first region.