Gate drive circuit, power-good circuit, overcurrent sensing circuit, oscillation prevention circuit, switching control circuit and switching power supply device

Abstract

The present invention is configured in a manner such that: a high-side pre-driver (21) has a first high-side transistor (HPM1) and a second high-side transistor (HPM2); a low-side pre-driver (22) has a third high-side transistor (LPM1) and a fourth high-side transistor (LPM2); and a delay is provided between a first gate signal (pgHS1) for turning the first high-side transistor on and a second gate signal (pgHS2) for turning the second high-side transistor on, and / or between a third gate signal (pgLS1) for turning the third high-side transistor on and a fourth gate signal (pgLS2) for turning the fourth high-side transistor on.

Description

Gate drive circuit, power good circuit, overcurrent detection circuit, oscillation prevention circuit, switching control circuit, and switching power supply device

[0001] The invention disclosed in this specification relates to a gate drive circuit, a power-good circuit, an overcurrent detection circuit, an oscillation prevention circuit, and a switching control circuit and a switching power supply device that include the overcurrent detection circuit or the oscillation prevention circuit.

[0002] A gate drive circuit for driving the gates of a high-side transistor and a low-side transistor connected in series has been known (see, for example, Patent Document 1). For example, the high-side transistor and the low-side transistor are configured by N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0003] When one of the high-side transistor and the low-side transistor turns on (switches from an off state to an on state) and the other turns off (switches from an on state to an off state), a voltage change occurs at the node where the high-side transistor and the low-side transistor are connected. This causes a change in Vds (drain-source voltage) of the transistor that turns off. If the slew rate (slope of change over time) of the voltage change at the node is large, the Vgs (gate-source voltage) of the transistor that turns off increases, which can cause the transistor to self-turn on.

[0004] Also, a power supply integrated circuit (IC) equipped with a power good circuit has been known. The power good circuit has a function of outputting a flag when the output voltage of the power supply circuit reaches a set voltage value (see, for example, Patent Document 2). This allows, for example, an external IC (such as a central processing unit (CPU)) of the power supply IC to be notified that the output voltage has risen normally.

[0005] Furthermore, conventionally, in a switching power supply device that switches upper and lower transistors complementarily, a lower overcurrent detection circuit that detects an overcurrent flowing through the lower transistor is sometimes provided (see, for example, Patent Document 3).

[0006] Furthermore, switching power supplies having an error amplifier have been developed (see, for example, Patent Document 4). In switching power supplies having an error amplifier, the error amplifier generates an error signal corresponding to the difference between a feedback voltage and a reference voltage, and a switching control circuit controls a switching element based on the error signal.

[0007] In the switching power supply device proposed in Patent Document 4, a capacitor provided between the output terminal of the error amplifier and the ground terminal prevents the error amplifier from oscillating.

[0008] JP 2022-15863 A JP 2021-93841 A JP 2014-150675 A JP 2014-117042 A

[0009] However, conventional gate drive circuits have room for improvement in terms of the function of suppressing self-turn-on of transistors (first problem).

[0010] Furthermore, the conventional power-good circuit has room for improvement in the flag output operation when the power supply IC is started (second problem).

[0011] Furthermore, the conventional lower-side current detection circuit has room for improvement in terms of overcurrent detection omissions (third problem).

[0012] Furthermore, in a switching power supply device having an error amplifier, it is possible to provide an additional circuit connected to a signal line that transmits an error signal. In this case, if the additional circuit has two poles, oscillation of the additional circuit cannot be prevented by only a capacitor provided between the output terminal of the error amplifier and the ground terminal (fourth problem).

[0013] For example, a gate drive circuit according to one aspect of the present disclosure is a gate drive circuit that drives a half bridge in which a high-side transistor to be driven and a low-side transistor to be driven are connected in series between a power supply voltage and a ground potential, the gate drive circuit comprising: a high-side pre-driver configured to drive a gate of the high-side transistor to be driven; and a low-side pre-driver configured to drive the gate of the low-side transistor to be driven, wherein the high-side pre-driver has a first high-side transistor and a second high-side transistor, and the low-side pre-driver has a third high-side transistor and a fourth high-side transistor, and a delay is provided between at least one of a first gate signal that turns on the first high-side transistor and a second gate signal that turns on the second high-side transistor, and between a third gate signal that turns on the third high-side transistor and a fourth gate signal that turns on the fourth high-side transistor.

[0014] Also, a power-good circuit according to one aspect of the present disclosure includes: a first output transistor having a first terminal connected to a power-good terminal and a second terminal connected to an application terminal of ground potential; a resistor for applying a voltage based on a first power supply voltage to a control terminal of the first output transistor; a first inverter stage that uses a second power supply voltage as a power supply voltage and is configured to be able to input a control input signal; and a second output transistor having a control terminal connected to the output terminal of the first inverter stage, a first terminal connected to the power-good terminal, and a second terminal connected to an application terminal of ground potential, wherein the power-good terminal can be pulled up to the second power supply voltage.

[0015] Also, an overcurrent detection circuit disclosed in this specification is configured to detect an overcurrent flowing through a circuit in which a first switch and a second switch are connected in series, the second switch is provided on a lower potential side than the first switch, and an inductor is connected to a connection node between the first switch and the second switch. The overcurrent detection circuit includes: a first current generating circuit configured to generate a first current corresponding to a current flowing through the second switch; a second current generating circuit configured to generate a second current that is greater than zero when the second switch switches from off to on and that fluctuates in synchronization with the switching of the first switch and the second switch; and a comparator configured to compare voltages corresponding to the first current and the second current with a threshold value.

[0016] The switching control circuit disclosed in this specification includes the overcurrent detection circuit configured as described above, and a control unit configured to control the first switch and the second switch.

[0017] The switching power supply device disclosed in this specification includes the switching control circuit configured as described above, the first switch, and the second switch.

[0018] The present specification also discloses an oscillation prevention circuit including a signal line, a first circuit, a capacitor connected to the signal line, and a resistor provided between the signal line and the first circuit. The first circuit has two poles. The first circuit, the capacitor, and the resistor each have two poles and one zero.

[0019] The switching control circuit disclosed in this specification includes an oscillation prevention circuit having the above-described configuration, an error amplifier having an output terminal connected to the signal line, and a control unit configured to control a switching element based on the output voltage of the error amplifier.

[0020] The switching power supply device disclosed in this specification includes the switching control circuit configured as described above and the switching element.

[0021] According to the invention disclosed in this specification, it is possible to suppress the self-turn-on of a transistor while suppressing a decrease in efficiency.

[0022] Furthermore, according to the invention disclosed in this specification, it is possible to appropriately perform a flag output operation when the power supply IC is started up.

[0023] Furthermore, according to the invention disclosed in this specification, it is possible to prevent overcurrent from being missed when it is detected.

[0024] According to the invention disclosed in this specification, it is possible to prevent oscillation of the first circuit having two poles.

[0025] FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a diagram illustrating a specific configuration example of a gate drive circuit. FIG. 3 is a diagram illustrating a configuration example of a first high-side drive unit. FIG. 4 is a timing chart illustrating operation when a high-side transistor is turned on and a low-side transistor is turned off. FIG. 5 is a timing chart illustrating operation when a high-side transistor is turned off and a low-side transistor is turned on in an embodiment of the present disclosure. FIG. 6 is a diagram illustrating a configuration example of a first low-side drive unit. FIG. 7 is a diagram illustrating a configuration of a gate drive circuit according to a second embodiment of the present disclosure. FIG. 8 is a diagram illustrating a configuration example of a high-side gate voltage monitor unit. FIG. 9 is a diagram illustrating a configuration example of a first low-side drive unit. FIG. 10 is a timing chart illustrating operation when a high-side transistor is turned off and a low-side transistor is turned on in the second embodiment. FIG. 11 is a timing chart illustrating operation when a high-side transistor is turned off and a low-side transistor is turned on in an embodiment of the present disclosure. FIG. 12 is a diagram illustrating a configuration of a semiconductor device according to an exemplary embodiment of the present disclosure. FIG. 13 is a diagram illustrating a portion of the internal configuration of the semiconductor device. FIG. 14 is a diagram illustrating a configuration example of a pre-regulator. FIG. 15 is a diagram showing the configuration of a power-good circuit according to a comparative example. FIG. 16 is a timing chart showing the operation of the power-good circuit according to the comparative example at the start-up of the power supply IC. FIG. 17 is a diagram showing the configuration of a power-good circuit according to a first embodiment of the present disclosure. FIG. 18 is a timing chart showing the operation of the power-good circuit according to the first embodiment at the start-up and shutdown of the power supply IC. FIG. 19 is a diagram showing the configuration of a power-good circuit according to a second embodiment of the present disclosure. FIG. 20 is a timing chart showing the operation of the power-good circuit according to the second embodiment at the start-up and shutdown of the power supply IC. FIG. 21 is a diagram showing the configuration of a power-good circuit according to a third embodiment of the present disclosure. FIG. 22 is a timing chart showing the operation of the power-good circuit according to the third embodiment at the start-up and shutdown of the power supply IC. FIG. 23 is a diagram showing the overall configuration of a switching power supply device.FIG. 24 is a diagram showing the internal configuration of a semiconductor device. FIG. 25 is a diagram showing a comparative example of a low-side overcurrent detection circuit. FIG. 26 is a timing chart showing ideal waveforms of voltages and currents at various components of a switching power supply device. FIG. 27 is a timing chart showing actual waveforms of voltages and currents at various components of a switching power supply device. FIG. 28 is a diagram showing a first embodiment of a low-side overcurrent detection circuit. FIG. 29 is a diagram showing a first configuration example of a current generation circuit. FIG. 30 is a timing chart showing actual waveforms of voltages and currents at various components of a switching power supply device having the low-side overcurrent detection circuit of the first embodiment. FIG. 31 is a diagram showing a second configuration example of a current generation circuit. FIG. 32 is a diagram showing a third configuration example of a current generation circuit. FIG. 33 is a diagram showing a fourth configuration example of a current generation circuit. FIG. 34 is a diagram showing a fifth configuration example of a current generation circuit. FIG. 35A is a diagram showing a modified example of the first circuit. FIG. 35B is a diagram showing another modified example of the first circuit. FIG. 36A is a diagram showing a modified example of the second circuit. FIG. 36B is a diagram showing another modified example of the second circuit. FIG. 36C is a diagram showing yet another modified example of the second circuit. FIG. 37 is a timing chart showing actual waveforms of voltages and currents at various components of a switching power supply device having a current generating circuit according to a fifth exemplary configuration. FIG. 38 is a diagram showing a second embodiment of a lower-side overcurrent detection circuit. FIG. 39 is a timing chart showing actual waveforms of voltages and currents at various components of a switching power supply device having a lower-side overcurrent detection circuit according to the second exemplary embodiment. FIG. 40 is a diagram showing a third embodiment of a lower-side overcurrent detection circuit. FIG. 41 is a diagram showing the overall configuration of a switching power supply device. FIG. 42 is a diagram showing the internal configuration of a semiconductor device. FIG. 43 is a diagram showing an example configuration of an error amplifier, an upper-side clamp circuit, and a lower-side clamp circuit. FIG. 44 is a diagram showing the frequency characteristics of a lower-side clamp circuit. FIG. 45 is a diagram showing the frequency characteristics of an upper-side clamp circuit. FIG. 46 is a diagram showing the frequency characteristics of an upper-side clamp circuit, a capacitor, and a resistor. FIG. 47 is a diagram showing an example configuration of a differential amplifier.

[0026] In this specification, a MOS field effect transistor (MOSFET [Metal-Oxide-Semiconductor Field Effect Transistor]) refers to a field effect transistor whose gate structure is made up of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-type, N-type, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor.

[0027] In this specification, the reference voltage means a voltage that is constant under ideal conditions, but in reality it is a voltage that may fluctuate slightly due to temperature changes and the like.

[0028] In addition, in the first to fourth disclosed technologies described below, the reference numerals indicating the components and signals in each technology are not related to each other. That is, the same reference numerals may indicate different components or signals.

[0029] <<First Disclosed Technology>> <<1. First Embodiment>> <Configuration of Semiconductor Device> Figure 1 is a diagram showing the configuration of a semiconductor device 1 according to a first embodiment of the present disclosure. The semiconductor device 1 is a device in which a power supply IC having a DC / DC converter function is packaged. As shown in Figure 1, the semiconductor device 1 has a high-side transistor HM, a low-side transistor LM, a gate drive circuit 2, a control logic unit 3, and a switch 4 integrated together.

[0030] An inductor L, an output capacitor Cout, and a boot capacitor Cbst are provided outside the semiconductor device 1. These external elements and the semiconductor device 1 constitute a step-down DC / DC converter.

[0031] The high-side transistor HM and the low-side transistor LM are both configured by NMOS transistors (N-channel MOSFETs). The drain of the high-side transistor HM is connected to the terminal to which the input voltage Vin is applied. The source of the high-side transistor HM is connected to the drain of the low-side transistor LM. The source of the low-side transistor LM is connected to the terminal to which the ground potential is applied. In other words, the high-side transistor HM and the low-side transistor LM are connected in series between the input voltage Vin and the ground potential. The high-side transistor HM and the low-side transistor LM form a so-called half bridge.

[0032] A node Nsw, at which the source of the high-side transistor HM and the drain of the low-side transistor LM are connected, is connected to one end of an inductor L. The other end of the inductor L is connected to one end of an output capacitor Cout. The other end of the output capacitor Cout is connected to a terminal to which a ground potential is applied. An output voltage Vout is generated at one end of the output capacitor Cout.

[0033] The gate drive circuit 2 is a circuit that drives the gates of the high-side transistor HM and the low-side transistor LM, and includes a high-side pre-driver 21 and a low-side pre-driver 22 .

[0034] The high-side pre-driver 21 drives the gate of the high-side transistor HM based on a control signal input from the control logic unit 3. The low-side pre-driver 22 drives the gate of the low-side transistor LM based on a control signal input from the control logic unit 3. The pre-drivers 21 and 22 complementarily switch-drive the transistors HM and LM, thereby converting the input voltage Vin into the output voltage Vout.

[0035] The boot capacitor Cbst and the switch 4 are used to configure a bootstrap. One end of the boot capacitor Cbst is connected to one end of the inductor L. The other end of the boot capacitor Cbst is connected to the high-side pre-driver 21. The other end of the boot capacitor Cbst is connected to an application terminal of a power supply voltage Vcc via the switch 4. The power supply voltage Vcc is an internal voltage generated by an LDO (Low Dropout) based on the input voltage Vin, for example.

[0036] When the high-side transistor HM is in the off state and the low-side transistor LM is in the on state, the switch 4 is turned on, and the boot capacitor Cbst is charged. When the high-side transistor HM is in the on state and the low-side transistor LM is in the off state, the switch 4 is turned off, and the boot voltage Vbst generated in the boot capacitor Cbst is supplied to the high-side pre-driver 21. Because the boot voltage Vbst is higher than the input voltage Vin, the high-side transistor HM, which is an NMOS transistor, can be turned on.

[0037] 2 is a diagram showing a specific configuration example of the gate drive circuit 2. The high-side pre-driver 21 has a first high-side PMOS transistor (P-channel MOSFET) HPM1, a second high-side PMOS transistor HPM2, a first high-side NMOS transistor HNM1, and a second high-side NMOS transistor HNM2. The high-side pre-driver 21 further has a first high-side drive unit (high-side PMOS drive unit) 211 that drives the high-side PMOS transistors HPM1 and HPM2, and a second high-side drive unit (high-side NMOS drive unit) 212 that drives the high-side NMOS transistors HNM1 and HNM2.

[0038] The sources of the high-side PMOS transistors HPM1 and HPM2 are connected to a node to which the boot voltage Vbst is applied. The drains of the high-side PMOS transistors HPM1 and HPM2 are connected to the drains of the high-side NMOS transistors HNM1 and HNM2. The sources of the high-side NMOS transistors HNM1 and HNM2 are connected to a node to which the switch voltage Vsw generated at the node Nsw is applied. The node to which the drains of the high-side PMOS transistors HPM1 and HPM2 and the drains of the high-side NMOS transistors HNM1 and HNM2 are connected is connected to the gate of the high-side transistor HM.

[0039] The first high-side driver 211 applies gate signals pgHS1 and pgHS2 to the gates of the high-side PMOS transistors HPM1 and HPM2, respectively, to drive the gates of the high-side PMOS transistors HPM1 and HPM2. The second high-side driver 212 applies gate signals ngHS1 and ngHS2 to the gates of the high-side NMOS transistors HNM1 and HNM2, respectively, to drive the gates of the high-side NMOS transistors HNM1 and HNM2.

[0040] The first high-side driver 211 outputs gate signals pgHS1 and pgHS2 at a logic level corresponding to the logic level of the high-side control signal Sph input from the control logic unit 3. The second high-side driver 212 outputs gate signals ngHS1 and ngHS2 at a logic level corresponding to the logic level of the high-side control signal Snh input from the control logic unit 3.

[0041] The low-side pre-driver 22 includes a first low-side PMOS transistor LPM1, a second low-side PMOS transistor LPM2, a first low-side NMOS transistor LNM1, and a second low-side NMOS transistor LNM2. The low-side pre-driver 22 further includes a first low-side driver (low-side PMOS driver) 221 that drives the low-side PMOS transistors LPM1 and LPM2, and a second low-side driver (low-side NMOS driver) 222 that drives the low-side NMOS transistors LNM1 and LNM2.

[0042] The sources of the low-side PMOS transistors LPM1 and LPM2 are connected to a terminal to which the power supply voltage Vcc is applied. The drains of the low-side PMOS transistors LPM1 and LPM2 are connected to the drains of the low-side NMOS transistors LNM1 and LNM2. The sources of the low-side NMOS transistors LNM1 and LNM2 are connected to a terminal to which the ground potential is applied. The node at which the drains of the low-side PMOS transistors LPM1 and LPM2 and the drains of the low-side NMOS transistors LNM1 and LNM2 are connected is connected to the gate of the low-side transistor LM.

[0043] The first low-side driver 221 applies gate signals pgLS1 and pgLS2 to the gates of the low-side PMOS transistors LPM1 and LPM2, respectively, to drive the gates of the low-side PMOS transistors LPM1 and LPM2. The second low-side driver 222 applies gate signals ngLS1 and ngLS2 to the gates of the low-side NMOS transistors LNM1 and LNM2, respectively, to drive the gates of the low-side NMOS transistors LNM1 and LNM2.

[0044] The first low-side driver 221 outputs gate signals pgLS1 and pgLS2 at a logic level corresponding to the logic level of the low-side control signal Spl input from the control logic unit 3. The second low-side driver 222 outputs gate signals ngLS1 and ngLS2 at a logic level corresponding to the logic level of the low-side control signal Snl input from the control logic unit 3.

[0045] <Configuration of High-Side Driver> Here, we will explain the configuration of the high-side drivers 211 and 212. Fig. 3 is a diagram showing an example configuration of the first high-side driver 211. The first high-side driver 211 has a first high-side gate signal generator 2111 that generates a gate signal pgHS1 based on the high-side control signal Sph, and a second high-side gate signal generator 2112 that generates a gate signal pgHS2 based on the high-side control signal Sph.

[0046] The first high-side gate signal generation unit 2111 is composed of five inverters 211A. Each inverter 211A is composed of a PMOS transistor and an NMOS transistor connected in series between the boot voltage Vbst and the switch voltage Vsw. The high-side control signal Sph is input to the first-stage inverter 211A, and the gate signal pgHS1 is output from the last-stage inverter 211A.

[0047] The second high-side gate signal generation unit 2112 is composed of five inverters 211B. Each inverter 211B is composed of a PMOS transistor and an NMOS transistor connected in series between the boot voltage Vbst and the switch voltage Vsw. The high-side control signal Sph is input to the first-stage inverter 211B, and the gate signal pgHS2 is output from the last-stage inverter 211B.

[0048] The number of stages of the inverters 211A and 211B is not limited to five.

[0049] The second high-side driver 212 has a configuration in which the high-side control signal Sph in the configuration shown in FIG. 3 is replaced with the high-side control signal Snh, and the gate signals pgHS1 and pgHS2 are replaced with the gate signals ngHS1 and ngHS2.

[0050] <Operation when high-side transistor is turned on> Figure 4 is a timing chart showing the operation when the high-side transistor HM is turned on and the low-side transistor LM is turned off. Figure 4 shows the case of normal operation. Normal operation refers to the operation when current flows from node Nsw to the inductor L side (solid arrow in Figure 1). Note that Figure 4 shows three patterns, which will be described later.

[0051] 4 shows, from top to bottom, example waveforms of the switch voltage Vsw, the high-side gate voltage HG, the low-side gate voltage LG, the gate signals ngHS1 and ngHS2, the gate signal pgHS1, and the gate signal pgHS2. The high-side gate voltage HG (FIG. 2) is the voltage applied to the gate of the high-side transistor HM with respect to the switch voltage Vsw, i.e., the Vgs of the high-side transistor HM. The low-side gate voltage LG (FIG. 2) is the voltage applied to the gate of the low-side transistor LM with respect to the ground potential, i.e., the Vgs of the low-side transistor LM.

[0052] The left side of Figure 4 shows, as a comparison with the embodiment of the present disclosure, the operation when no delay is provided in the gate signals pgHS1 and pgHS2. Initially, the high-side transistor HM is in the off state, and the low-side transistor LM is in the on state. Here, the low-side pre-driver 22 begins discharging the gate of the low-side transistor LM (timing t1). At this time, with the low-side PMOS transistors LPM1 and LPM2 in the off state, the low-side NMOS transistors LNM1 and LNM2 are turned on, and the low-side gate voltage LG begins to decrease.

[0053] At this time, the current flowing through the low-side transistor LM increases the voltage drop across the low-side transistor LM, causing the switch voltage Vsw to decrease, and the low-side gate voltage LG to decrease to the ground potential (timing t2).

[0054] On the other hand, in the high-side pre-driver 21, after the gate signals ngHS1 and ngHS2 switch from high level to low level to turn off the high-side NMOS transistors HNM1 and HNM2, the gate signals pgHS1 and pgHS2 switch from high level to low level to turn on the high-side PMOS transistors HPM1 and HPM2. Therefore, a dead time (a period when they are simultaneously off) is provided.

[0055] The levels of the gate signals pgHS1 and pgHS2 change at timing t1, and the high-side gate voltage HG begins to rise. From timing t2, as the high-side gate voltage HG rises, the switch voltage Vsw rises. As the high-side gate voltage HG rises, the on-resistance of the high-side transistor HM decreases, reducing the voltage drop across the high-side transistor HM, and therefore the switch voltage Vsw rises.

[0056] Then, the switch voltage Vsw reaches the input voltage Vin (timing t3). The high-side gate voltage HG continues to rise after timing t3 and reaches the boot voltage Vbst at timing t4.

[0057] As described above, in the operation shown on the left side of FIG. 4 , the gate signals pgHS1 and pgHS2 are not delayed, and are simultaneously switched to a low level. If the sizes of the high-side PMOS transistors HPM1 and HPM2 are designed to increase the drive capability of the high-side transistor HM, the slope of the increase in the high-side gate voltage HG during the period (t2 to t3) in which the switch voltage Vsw increases becomes steeper, and the slew rate of the switch voltage Vsw increases. As a result, in the operation shown on the left side of FIG. 4 , a change in the Vds of the low-side transistor LM may raise the Vgs of the low-side transistor LM, potentially causing self-turn-on of the low-side transistor LM.

[0058] Therefore, in the operation shown in the center of Fig. 4, the driving capability of the high-side transistor HM by the high-side PMOS transistors HPM1 and HPM2 is reduced. Note that no delay is provided for the control of the gate signals pgHS1 and pgHS2, as in the left side of Fig. 4.

[0059] In this case, the slew rate of the switch voltage Vsw is reduced, suppressing self-turn-on of the low-side transistor LM (t2 to t3 in the center of FIG. 4). However, the rising slope of the high-side gate voltage HG becomes smaller after timing t3, and the time it takes for the high-side gate voltage HG to reach the boot voltage Vbst becomes longer (t3 to t4). This increases the on-resistance loss of the high-side transistor HM, resulting in a decrease in efficiency.

[0060] Therefore, in the embodiment of the present disclosure, the operation is as shown on the right side of Fig. 4. Here, a delay Dly is provided in the gate signal pgHS2 relative to the gate signal pgHS1. The delay time of the delay Dly is set so that the gate signal pgHS2 switches to low level at timing t3 when the switch voltage Vsw reaches the input voltage Vin.

[0061] As a result, first, at timing t1, the gate signal pgHS1 is switched to low level to turn on the high-side PMOS transistor HPM1. Then, at timing t3, the gate signal pgHS2 is switched to low level to turn on the high-side PMOS transistor HPM2. Therefore, during the period (t2 to t3) in which the switch voltage Vsw rises, only HPM1 of the high-side PMOS transistors HPM1 and HPM2 is on, reducing the drive capability, decreasing the slope of the high-side gate voltage HG, and reducing the slew rate of the switch Vsw. Furthermore, when the switch voltage Vsw reaches the input voltage Vin, both high-side PMOS transistors HPM1 and HPM2 are turned on, increasing the drive capability and increasing the slope of the high-side gate voltage HG. Therefore, the time (t3 to t4) until the high-side gate voltage HG reaches the boot voltage Vbst is shortened. In other words, according to this embodiment, self-turn-on of the low-side transistor LM can be suppressed while suppressing a decrease in efficiency.

[0062] To switch the gate signals pgHS1 and pgHS2 to low level, the first high-side driver 211 configured as shown in Fig. 3 switches the high-side control signal Sph to high level. The gate signal generators 2111 and 2112 switch the gate signals pgHS1 and pgHS2 with a delay from the switching of the high-side control signal Sph. This delay is caused by the on-resistance of the transistors in the inverters 211A and 211B and the capacitance of the wiring and transistor gates.

[0063] To provide a delay to the gate signals pgHS1 and pgHS2, the size of the NMOS transistor in the first-stage inverter 211B in the high-side gate signal generation units 2111 and 2112 is made smaller than the size of the NMOS transistor in the first-stage inverter 211A, thereby adjusting the on-resistance. Since the size of the transistors in the subsequent-stage inverters 211A and 211B must be increased to ensure driving capability, and adjusting the on-resistance is difficult, the size is adjusted in the first-stage inverter. For example, the size of the transistors in the second-stage inverter may be adjusted in addition to the first-stage inverter.

[0064] <Operation when Low-Side Transistor is Turned On> Figure 5 is a timing chart showing the operation when the high-side transistor HM is turned off and the low-side transistor LM is turned on in the embodiment of the present disclosure. Figure 5 shows the case of reverse current operation. Reverse current operation refers to the operation when current flows from inductor L to node Nsw (the dashed arrow in Figure 1).

[0065] 5 shows, from the top to bottom, examples of waveforms of the switch voltage Vsw, the high-side gate voltage HG, the low-side gate voltage LG, the gate signals ngLS1 and ngLS2, the gate signal pgLS1, and the gate signal pgLS2. As shown in FIG. 5, a delay is provided for the gate signals pgLS1 and pgLS2.

[0066] Initially, the high-side transistor HM is on and the low-side transistor LM is off. Then, the high-side pre-driver 21 starts discharging the gate of the high-side transistor HM (timing t11). At this time, the high-side PMOS transistors HPM1 and HPM2 are off, the high-side NMOS transistors HNM1 and HNM2 are turned on, and the high-side gate voltage HG starts to decrease.

[0067] At this time, the current flowing through the high-side transistor HM increases the voltage drop across the high-side transistor HM, causing the switch voltage Vsw to rise. The high-side gate voltage HG drops to the switch voltage Vsw (timing t12).

[0068] On the other hand, in the low-side pre-driver 22, after the gate signals ngLS1 and ngLS2 are switched from high level to low level to turn off the low-side NMOS transistors LNM1 and LNM2, the gate signal pgLS1 is switched from high level to low level to turn on the low-side PMOS transistor LPM1. Therefore, a dead time is provided.

[0069] The level of the gate signal pgLS1 switches at timing t11, and the low-side gate voltage LG starts to rise. From timing t12, as the low-side gate voltage LG rises, the switch voltage Vsw drops. As the low-side gate voltage LG rises, the on-resistance of the low-side transistor LM decreases, and the voltage drop across the low-side transistor LM decreases, so the switch voltage Vsw drops.

[0070] Then, the switch voltage Vsw reaches the ground potential (timing t13). At this point, the gate signal pgLS2 is switched to low level, turning on the low-side PMOS transistor LPM2. The low-side gate voltage LG continues to rise after timing t13 and reaches the power supply voltage Vcc at timing t14.

[0071] As a result, first, at timing t11, the gate signal pgLS1 is switched to low level to turn on the low-side PMOS transistor LPM1, and then, at timing t13, the gate signal pgLS2 is switched to low level to turn on the low-side PMOS transistor LPM2. Therefore, during the period (t12 to t13) in which the switch voltage Vsw decreases, only LPM1 of the low-side PMOS transistors LPM1 and LPM2 is on, suppressing the drive capability, reducing the slope of the low-side gate voltage LG, and decreasing the slew rate of the switch Vsw. Furthermore, when the switch voltage Vsw reaches ground potential, both low-side PMOS transistors LPM1 and LPM2 are switched on, increasing the drive capability and increasing the slope of the low-side gate voltage LG. Therefore, the time (t13 to t14) until the low-side gate voltage LG reaches the power supply voltage Vcc is shortened. That is, according to this embodiment, it is possible to suppress the self-turn-on of the high-side transistor HM and also suppress a decrease in efficiency.

[0072] 6 is a diagram showing an example of the configuration of the first low-side driver 221. The first low-side driver 221 has a first low-side gate signal generator 2211 that generates a gate signal pgLS1 based on the low-side control signal Spl, and a second low-side gate signal generator 2212 that generates a gate signal pgLS2 based on the low-side control signal Spl.

[0073] The first low-side gate signal generation unit 2211 is composed of five inverters 221A. Each inverter 221A is composed of a PMOS transistor and an NMOS transistor connected in series between the power supply voltage Vcc and the ground potential. The low-side control signal Spl is input to the first-stage inverter 221A, and the gate signal pgLS1 is output from the last-stage inverter 221A.

[0074] The second low-side gate signal generation unit 2212 is composed of five inverters 221B. Each inverter 221B is composed of a PMOS transistor and an NMOS transistor connected in series between the power supply voltage Vcc and the ground potential. The low-side control signal Spl is input to the first-stage inverter 221B, and the gate signal pgLS2 is output from the last-stage inverter 221B.

[0075] The number of stages of the inverters 221A and 221B is not limited to five.

[0076] The second low-side driver 222 has the same configuration as that shown in FIG. 6, except that the low-side control signal Spl is replaced with the low-side control signal Snl, and the gate signals pgLS1 and pgLS2 are replaced with the gate signals ngLS1 and ngLS2.

[0077] To provide a delay to the gate signals pgLS1 and pgLS2, the size of the NMOS transistor in the first-stage inverter 221B in the low-side gate signal generation units 2211 and 2212 is made smaller than the size of the NMOS transistor in the first-stage inverter 221A, thereby adjusting the on-resistance. Since the size of the transistor in the subsequent-stage inverters 221A and 221B needs to be increased to ensure driving capability, and adjusting the on-resistance is difficult, the size is adjusted in the first-stage inverter. For example, the size of the transistor in the second-stage inverter may be adjusted in addition to the first-stage inverter.

[0078] <<2. Second Embodiment>> Figure 7 is a diagram showing the configuration of a gate drive circuit 2 according to a second embodiment of the present disclosure. Compared to the configuration of the first embodiment (Figure 2) described above, the gate drive circuit 2 shown in Figure 7 further includes a high-side gate voltage monitor unit 23. Note that, in the second embodiment, as in the first embodiment, a delay is provided in the gate signals pgHS1 and pgHS2 due to the configuration of the first high-side drive unit 211 in the high-side pre-driver 21. This makes it possible to suppress self-turn-on of the low-side transistor and suppress a decrease in efficiency when the high-side transistor HM is turned on (during normal operation).

[0079] <Configuration of High-Side Gate Voltage Monitor Unit> Fig. 8 is a diagram showing an example configuration of the high-side gate voltage monitor unit 23. The high-side gate voltage monitor unit 23 shown in Fig. 8 includes a resistor 23A, switches 23B and 23C, and inverters 23D and 23E. The switch 23B is configured by an NMOS transistor. The switch 23C is configured by a PMOS transistor.

[0080] One end of resistor 23A is connected to the gate of high-side transistor HM. The other end of resistor 23A is connected to the input end of inverter 23D via switch 23B. Inverters 23D and 23E each have a PMOS transistor and an NMOS transistor connected in series between the power supply voltage Vcc and ground potential. The output end of inverter 23D is connected to the input end of inverter 23E. A switch 23C is connected between the application end of power supply voltage Vcc and the input end of inverter 23D.

[0081] The switches 23B and 23C are controlled by an enable signal EN. When the enable signal EN is at a low level, the switch 23B is turned off, the switch 23C is turned on, and the PMOS transistors of the inverters 23D and 23E are turned off. This disables the high-side gate voltage monitor unit 23.

[0082] On the other hand, when the enable signal EN is at a high level, the switch 23B is in an on state, the switch 23C is in an off state, and the high-side gate voltage monitor unit 23 is enabled. In this case, since the high-side gate voltage HG is based on the switch voltage Vsw, when the switch voltage Vsw is at a low level and the high-side gate voltage HG is at a low level, the monitor signal HG_MOM output from the inverter 23E is at a low level.

[0083] <Configuration of Low-Side Driver> Fig. 9 is a diagram showing an example configuration of a first low-side driver 221 according to the second embodiment. The first low-side driver 221 shown in Fig. 9 includes a first low-side gate signal generator 2211 that generates a gate signal pgLS1 based on the low-side control signal Spl, and a second low-side gate signal generator 2212 that generates a gate signal pgLS2 based on the low-side control signal Spl. The low-side drivers 2211 and 2212 have the same configuration as that shown in Fig. 6 described above.

[0084] The first low-side driver 221 according to this embodiment further includes an inverter 221C and an AND circuit 221D. The monitor signal HG_MOM is input to the inverter 221C. The output of the inverter 221C is input to one input terminal of the AND circuit 221C, and the low-side control signal Spl is input to the other input terminal. The output of the AND circuit 221D is input to the second low-side gate signal generator 2212.

[0085] With this configuration, when the low-side control signal Spl rises to high level, the gate signal pgLS1 first falls to low level. Then, when the monitor signal HG_MOM falls to low level, the output of the AND circuit 221D rises to high level and the gate signal pgLS2 falls to low level. Therefore, a delay can be provided in the gate signal pgLS2 relative to the gate signal pgLS1.

[0086] <Operation when low-side transistor is turned on (reverse current operation)> Fig. 10 is a timing chart showing the operation when the high-side transistor HM is turned off and the low-side transistor LM is turned on in the second embodiment. Fig. 10 shows the case of reverse current operation.

[0087] 5 (first embodiment) is in the monitor signal HG_MON. In FIG. 10, the low-side control signal Spl first switches to a high level, and the gate signal pgLS1 switches to a low level at timing t11.

[0088] Thereafter, when the switch voltage Vsw drops to near ground potential, the high-side gate voltage monitor 23 switches the monitor signal HG_MON to low level. Then, the gate signal pgLS2 is switched to low level. Thus, in this embodiment, a delay is provided in the gate signals pgLS1 and pgHS2, so that, similar to the first embodiment, self-turn-on of the high-side transistor HM can be suppressed while a decrease in efficiency can be suppressed.

[0089] 11 is a timing chart showing the operation when the high-side transistor HM is turned off and the low-side transistor LM is turned on in the embodiment of the present disclosure.

[0090] 11 shows the operation in the first embodiment. In this case, first, the high-side pre-driver 21 starts discharging the gate of the high-side transistor HM, and the high-side gate voltage HG starts to decrease.

[0091] The switch voltage Vsw starts to decrease from timing t21. Due to the decrease in the high-side gate voltage HG, the on-resistance of the high-side transistor HM increases, the voltage drop in the high-side transistor HM increases, and the switch voltage Vsw decreases.

[0092] Then, at timing t22 when the switch voltage Vsw approaches ground potential, the gate signal pgLS1 is switched to low level. This turns on the low-level PMOS transistor LPM1, and the low-side gate voltage LG begins to rise. Thereafter, at timing t23, the gate signal pgLS2 is switched to low level. This turns on the low-level PMOS transistor LPM2, and the low-side gate voltage LG continues to rise and reaches the power supply voltage Vcc (timing t24).

[0093] Thus, when the low-side transistor LM turns on during normal operation, the low-side gate voltage LG begins to rise after the switch voltage Vsw transitions, so the slope of the low-side gate voltage LG is unrelated to the slew rate of the switch voltage Vsw. Therefore, according to the first embodiment, the gate signal pgLS2 is delayed by a certain amount relative to the gate signal pgLS1, which lengthens the time (t22 to t24) until the low-side gate voltage LG reaches the power supply voltage Vcc, resulting in reduced efficiency. Furthermore, the delay in the rise of the low-side gate voltage LG also delays the rise of the switch voltage Vsw.

[0094] Meanwhile, the right side of FIG. 11 shows the operation in the second embodiment. In this case, the monitor signal HG_MON is switched to low level at timing t22, when the switch voltage Vsw approaches ground potential. Therefore, the gate signal pgLS2 is switched to low level with almost no delay relative to pgLS1. As a result, from timing t22 onward, the low-side gate voltage LG rises while the driving capability is high, and the slope of the low-side gate voltage LG becomes steeper. Therefore, the time (t22 to t24) until the low-side gate voltage LG reaches the power supply voltage Vcc is shortened, and a decrease in efficiency is suppressed.

[0095] In this way, the second embodiment can suppress a decrease in efficiency both during reverse flow operation and normal operation.

[0096] <3. Others> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0097] For example, the present disclosure is not limited to application to DC / DC converters, but can also be applied to driving transistors in inverter circuits that perform DC / AC conversion.

[0098] <4. Supplementary Note> As described above, a gate drive circuit (2) according to one aspect of the present disclosure is a gate drive circuit for driving a half bridge in which a high-side transistor (HM) to be driven and a low-side transistor (LM) to be driven are connected in series between a power supply voltage (Vin) and a ground potential, and includes: a high-side pre-driver (21) configured to drive a gate of the high-side transistor to be driven; and a low-side pre-driver (22) configured to drive a gate of the low-side transistor to be driven, wherein the high-side pre-driver has a first high-side transistor (HPM1) and a second high-side transistor (HPM2), and the low-side pre-driver has a third high-side transistor (LPM1) and a fourth high-side transistor (LPM2), and between a first gate signal (pgHS1) that turns on the first high-side transistor and a second gate signal (pgHS2) that turns on the second high-side transistor, A delay is provided between at least one of a third gate signal (pgLS1) that turns on the third high-side transistor and a fourth gate signal (pgLS2) that turns on the fourth high-side transistor (first configuration).

[0099] In addition, in the first configuration, the high-side pre-driver (21) may be configured to include a high-side drive unit (211) configured to generate the first gate signal (pgHS1) and the second gate signal (pgHS2) based on a high-side control input signal (Sph) (second configuration).

[0100] Furthermore, in the second configuration, the high-side drive unit (211) may include: a first high-side gate signal generation unit (2111) having a plurality of first inverters (211A) and configured to generate the first gate signal (pgHS1); and a second high-side gate signal generation unit (2112) having a plurality of second inverters (211B) and configured to generate the second gate signal (pgHS2), and at least any of the second inverters in the second high-side gate signal generation unit may be configured to have a smaller transistor size than at least any of the first inverters in the first high-side gate signal generation unit (third configuration).

[0101] In addition, in the third configuration, the second inverter (211B) in the first stage of the second high-side gate signal generation unit (2112) may be configured to have a smaller transistor size than the first inverter (211A) in the first stage of the first high-side gate signal generation unit (2111) (fourth configuration).

[0102] In addition, in any of the first to fourth configurations, the low-side pre-driver (22) may be configured to include a low-side drive unit (221) configured to generate the third gate signal (pgLS1) and the fourth gate signal (pgLS2) based on a low-side control input signal (Spl) (fifth configuration).

[0103] Furthermore, in the fifth configuration, the low-side driving unit (221) may have: a first low-side gate signal generating unit (2211) having a plurality of third inverters (221A) and configured to generate the third gate signal (pgLS1); and a second low-side gate signal generating unit (2212) having a plurality of fourth inverters (221B) and configured to generate the fourth gate signal (pgLS2), and at least any of the fourth inverters in the second low-side gate signal generating unit may have a smaller transistor size than at least any of the third inverters in the first low-side gate signal generating unit (sixth configuration).

[0104] In addition, in the sixth configuration, the fourth inverter (221B) in the first stage of the second low-side gate signal generation unit (2212) may be configured to have a smaller transistor size than the third inverter (221A) in the first stage of the first low-side gate signal generation unit (2211) (seventh configuration).

[0105] Furthermore, in any of the first to seventh configurations, a monitor unit (23) may be provided for monitoring whether the gate voltage (HG) of the high-side transistor (HM) to be driven is at a low level and whether the voltage (Vsw) of a node (Nsw) to which the high-side transistor to be driven and the low-side transistor (LM) to be driven are connected is at a low level, and the fourth gate signal (pgLS2) may be generated based on a monitor signal (HG_MON) output from the monitor unit (eighth configuration).

[0106] Furthermore, in the eighth configuration, the monitor unit (23) may be configured to include a resistor (23A) having a first end connected to the gate of the driven transistor (HM), and inverter stages (23D, 23E) having input ends connected to the second end of the resistor (ninth configuration).

[0107] 12 is a diagram showing the configuration of a semiconductor device 1 according to an exemplary embodiment of the present disclosure. The semiconductor device 1 is a device in which a power supply IC having a DC / DC converter function is packaged. As shown in FIG. 12 , the semiconductor device 1 has external terminals for establishing electrical connection with the outside, including a VIN (input voltage) terminal, an EN (enable) terminal, a PGND (power ground) terminal, a VREG (constant voltage) terminal, a PGD (power good) terminal, a BST (bootstrap) terminal, a SW (switch) terminal, an FB (feedback) terminal, and an AGND (analog ground) terminal.

[0108] An input voltage Vin can be applied to the VIN terminal. A ground potential can be applied to the PGND terminal. An input capacitor CIN is connected between the application terminal of the input voltage Vin and the application terminal of the ground potential.

[0109] The semiconductor device 1 has an upper switching element and a lower switching element (not shown). Both the upper switching element and the lower switching element are configured by NMOS transistors (N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs)). The upper switching element and the lower switching element are connected in series between a VIN terminal and a PGND terminal. A node at which the upper switching element and the lower switching element are connected is connected to an SW terminal.

[0110] The SW terminal is connected to one end of an inductor L. The other end of the inductor L is connected to one end of an output capacitor COUT. The other end of the output capacitor COUT and the AGND terminal are connected to a terminal to which a ground potential is applied. An output voltage Vout is generated at the other end of the inductor L.

[0111] Voltage-dividing resistors Ru and Rl are connected in series between the other end of the inductor L and the AGND terminal. A node to which the voltage-dividing resistors Ru and Rl are connected is connected to the FB terminal. A feedback voltage Vfb generated by dividing the output voltage Vout by the voltage-dividing resistors Ru and Rl is applied to the FB terminal. The semiconductor device 1 has a feedback control unit (not shown). The feedback control unit controls the switching of the upper switching element and the lower switching element based on the feedback voltage Vfb. This controls the output voltage Vout to a desired voltage value. The feedback control unit includes an error amplifier, a control logic unit, a driver, and the like.

[0112] A bootstrap capacitor CBST is connected between the BST terminal and the SW terminal. By charging the bootstrap capacitor CBST, the upper switching element formed by an NMOS transistor can be turned on.

[0113] The upper switching element, the lower switching element, and the feedback control section are integrated into the power supply IC and provided in the semiconductor device 1.

[0114] The configuration of the EN terminal, VREG terminal, and PGD terminal will be described later.

[0115] <Internal Power Supply> Fig. 13 is a diagram showing a part of the internal configuration of the semiconductor device 1. As shown in Fig. 13, the semiconductor device 1 includes a pre-regulator (PREREG) 2, a reference voltage generating unit 3, and a regulator (REG) 4, and these configurations are integrated into the power supply IC.

[0116] The pre-regulator 2 generates a first power supply voltage Vprereg based on an input voltage Vin applied to a VIN terminal. The first power supply voltage Vprereg is a constant voltage.

[0117] 14 is a diagram showing an example of the configuration of the pre-regulator 2. The pre-regulator 2 includes voltage dividing resistors 20 and 21, an NMOS transistor 22, a Zener diode 23, a PMOS transistor (P-channel MOSFET) 24, a resistor 25, a Zener diode 26, a capacitor 27, a resistor 28, a capacitor 29, and an NMOS transistor 201.

[0118] The voltage dividing resistors 20 and 21 are connected in series between the application terminal of the input voltage Vin and the drain of the NMOS transistor 22. The source of the NMOS transistor 22 is connected to the application terminal of the ground potential. The gate of the NMOS transistor 22 is driven by an enable signal En applied to the EN terminal (FIG. 13).

[0119] The anode of the Zener diode 23 is connected to a node N20 to which the voltage dividing resistors 20 and 21 are connected. The cathode of the Zener diode 23 is connected to the application terminal of the input voltage Vin. The Zener diode 23 clamps the voltage of the node N20 to prevent excessive decrease.

[0120] The node N20 is connected to the gate of a PMOS transistor 24. The source of the PMOS transistor 24 is connected to a terminal to which an input voltage Vin is applied. The drain of the PMOS transistor 24 is connected to one terminal of a resistor 25. The other terminal of the resistor 25 is connected to the cathode of a Zener diode 26. The anode of the Zener diode 26 is connected to a terminal to which a ground potential is applied.

[0121] The cathode of the Zener diode 26 is connected to one end of a capacitor 27. The other end of the capacitor 27 is connected to a terminal to which the ground potential is applied. The cathode of the Zener diode 26 is connected to one end of a resistor 28. The other end of the resistor 28 is connected to one end of a capacitor 29. The other end of the capacitor 29 is connected to a terminal to which the ground potential is applied. The resistor 28 and the capacitor 29 form a low-pass filter.

[0122] The other end of the resistor 28 is connected to the gate of the NMOS transistor 201. The drain of the NMOS transistor 201 is connected to the application terminal of the input voltage Vin. The first power supply voltage Vprereg is generated at the source of the NMOS transistor 201.

[0123] With this configuration, when the enable signal En is at a low level, the NMOS transistor 22 is in an off state, and therefore the input voltage Vin is applied to the gate of the PMOS transistor 24. As a result, the PMOS transistor 24 is in an off state, and the first power supply voltage Vprereg is not generated.

[0124] On the other hand, when the enable signal En is at a high level, the NMOS transistor 22 is in an ON state, a voltage obtained by dividing the input voltage Vin by the voltage-dividing resistors 20 and 21 is generated at the node N20, and the PMOS transistor 24 is in an ON state. As a result, the first power supply voltage Vprereg is generated as Vprereg=Vz-Vgs, where Vz is the Zener voltage of the Zener diode 26, and Vgs is the gate-source voltage of the NMOS transistor 201.

[0125] 13 , the reference voltage generation unit 3 generates a reference voltage Vref based on the first power supply voltage Vprereg. The reference voltage generation unit 3 is configured by, for example, a bandgap reference. The reference voltage Vref is used to generate a second power supply voltage Vreg in the regulator 4, for example.

[0126] The regulator 4 generates a second power supply voltage Vreg based on the input voltage Vin. The regulator 4 is configured, for example, by an LDO (Low Dropout) regulator. In this case, the reference voltage Vref is input to an error amplifier in the LDO regulator. The second power supply voltage Vreg is generated at a VREG terminal. As shown in FIG. 12 , the VREG terminal is connected to a capacitor CREG. The second power supply voltage Vreg is supplied to each component of the power supply IC. The second power supply voltage Vreg is supplied, for example, to a power-good circuit 5, which will be described later.

[0127] The first power supply voltage Vprereg and the second power supply voltage Vreg may have the same voltage value or different voltage values.

[0128] 13, the semiconductor device 1 includes a power-good circuit 5. The power-good circuit 5 is integrated into the power supply IC.

[0129] The power-good circuit 5 is connected between the PGD terminal and a terminal to which a ground potential is applied. As shown in Fig. 12, a pull-up resistor Rpu is connected between the PGD terminal and the VREG terminal. That is, the PGD terminal is pulled up to the second power supply voltage Vreg.

[0130] The power-good circuit 5 has a switch (output transistor) not shown in Fig. 13 connected between the PGD terminal and a terminal to which a ground potential is applied. When the switch is in an on state, the flag signal PGDOUT (Fig. 12) output from the PGD terminal becomes low level, and when the switch is in an off state, the flag signal PGDOUT becomes high level.

[0131] When the power supply IC is started and the output voltage Vout rises, the power-good circuit 5 detects that the output voltage Vout has reached a set voltage value based on the feedback voltage Vfb generated at the FB terminal, and outputs a high-level flag signal PGDOUT. The flag signal PGDOUT can notify the outside that the output voltage Vout output from the power supply circuit (DC / DC converter) has risen normally.

[0132] 15 is a diagram showing the configuration of a power-good circuit 5 according to a comparative example. The comparative example is described for comparison with the embodiment of the present disclosure described later. The description of the comparative example will clarify the issues.

[0133] 15 includes an output transistor MA and inverters IVA and IVB. The output transistor MA is an NMOS transistor. The drain of the output transistor MA is connected to the PGD terminal. The source of the output transistor MA is connected to a terminal to which a ground potential is applied.

[0134] The input terminal of the inverter IVA is connected to an application terminal of the control input signal PGDIN. The control input signal PGDIN is a signal generated inside the power-good circuit 5. The output terminal of the inverter IVA is connected to the input terminal of the inverter IVB. The output terminal of the inverter IVB is connected to the gate of the output transistor MA. As a result, the control input signal PGDIN is logically inverted by the inverters IVA and IVB and input to the gate of the output transistor MA.

[0135] The inverters IVA and IVB each have a PMOS transistor and an NMOS transistor (not shown). The source of the PMOS transistor is connected to an application terminal for the second power supply voltage Vreg. The drain of the PMOS transistor is connected to the drain of the NMOS transistor. The source of the NMOS transistor is connected to an application terminal for the ground potential. The gates of the PMOS transistor and the NMOS transistor are connected to an input terminal of the inverter. A node connecting the drain of the PMOS transistor and the drain of the NMOS transistor is connected to an output terminal of the inverter. That is, the inverters IVA and IVB use the second power supply voltage Vreg as a power supply voltage.

[0136] 16 is a timing chart showing the operation of the power-good circuit 5 according to the comparative example when the power supply IC is started up. From the top to bottom, the diagram shows the enable signal En, the first power supply voltage Vprereg, the second power supply voltage Vreg, the control input signal PGDIN, the on / off state of the output transistor MA, and the flag signal PGDOUT.

[0137] First, the enable signal En switches from a low level indicating disable to a high level indicating enable (timing ta). Then, the pre-regulator 2 is activated, and the first power supply voltage Vprereg starts to rise (timing tb). After that, the reference voltage generator 3 is activated, and the regulator 4 is activated by the reference voltage Vref. At this time, the second power supply voltage Vreg starts to rise (timing tc). That is, the pre-regulator 2, the reference voltage generator 3, and the regulator 4 are activated in this order.

[0138] The control input signal PGDIN is at a low level until the second power supply voltage Vreg reaches the threshold voltage Vth (Vreg = low level) (Vreg reaches Vth at timing td). The threshold voltage Vth is the threshold voltage of the inverters IVA and IVB and also the threshold voltage of the output transistor MA.

[0139] When the second power supply voltage Vreg is lower than the threshold voltage Vth, the outputs of the inverters IVA and IVB are logically indeterminate, and the output transistor MA is turned off. At this time, since the PGD terminal is pulled up to the second power supply voltage Vreg, the rising edge of the second power supply voltage Vreg appears as it is in the flag signal PGDOUT (between timings tc and td) until the second power supply voltage Vreg reaches the threshold voltage Vth.

[0140] When the second power supply voltage Vreg exceeds the threshold voltage Vth, the control input signal PGDIN goes high, a high-level signal is input to the gate of the output transistor MA, and the output transistor MA is turned on. As a result, the flag signal PGDOUT goes low.

[0141] The rising edge of the second power supply voltage Vreg activates a control logic unit (not shown) and activates the DC / DC converter function of the semiconductor device 1. When the output voltage Vout rises and reaches a set voltage value, the control input signal PGDIN is switched to low level. Therefore, the output transistor MA is turned off, and the flag signal PGDOUT is switched to high level.

[0142] As described above, the power-good circuit 5 according to the comparative example has a problem in that the output transistor MA cannot be turned on when the power supply IC is started up, causing the flag signal PGDOUT to rise. In order to solve this problem, the following embodiment of the present disclosure is implemented.

[0143] 17 is a diagram showing the configuration of a power-good circuit 5 according to a first embodiment of the present disclosure. The power-good circuit 5 shown in FIG. 17 includes an output transistor M1, an output transistor M2, inverters IV1 to IV4, pull-up resistors R1 and R2, and a level shift circuit 51.

[0144] The output transistor M1 is an NMOS transistor. The drain of the output transistor M1 is connected to the PGD terminal. The source of the output transistor M1 is connected to a terminal to which a ground potential is applied. A pull-up resistor R1 is connected between the gate of the output transistor M1 and a terminal to which a first power supply voltage Vprereg is applied.

[0145] The input terminal of the level shift circuit 51 is connected to the application terminal of the control input signal PGDIN. The output terminal of the level shift circuit 51 is connected to the input terminal of the inverter IV3. The output terminal of the inverter IV3 is connected to the input terminal of the inverter IV4. The output terminal of the inverter IV4 is connected to the gate of the output transistor M1. The level of the control input signal PGDIN is converted from the second power supply voltage Vreg to the first power supply voltage Vprereg by the level shift circuit 51. The level-converted control input signal PGDIN is logically inverted by each of the inverters IV3 and IV4 and input to the gate of the output transistor M1. In this embodiment, the first power supply voltage Vprereg and the second power supply voltage Vreg have different voltage values ​​(for example, Vprereg = 4.5 V, Vreg = 3 V, etc.).

[0146] The inverters IV3 and IV4 have the same configuration as the inverters IVA and IVB according to the comparative example, except that they use the first power supply voltage Vprereg as their power supply voltage. That is, the inverters IV3 and IV4 have PMOS transistors and NMOS transistors (not shown).

[0147] The drain of the output transistor M2 is connected to the PGD terminal, and the source of the output transistor M2 is connected to a terminal to which the ground potential is applied.

[0148] The input terminal of inverter IV1 is connected to the application terminal of control input signal PGDIN. The output terminal of inverter IV1 is connected to the input terminal of inverter IV2. The output terminal of inverter IV2 is connected to the gate of output transistor M2. As a result, the control input signal PGDIN is logically inverted by inverters IV1 and IV2 and input to the gate of output transistor M2.

[0149] The inverters IV1 and IV2 use the second power supply voltage Vreg as a power supply voltage, and have the same configuration as the inverters IVA and IVB according to the comparative example described above.

[0150] A pull-up resistor R2 is connected between the gate of the output transistor M2 and the application terminal of the second power supply voltage Vreg.

[0151] 18 is a timing chart showing the operation of the power-good circuit 5 according to the first embodiment at the start-up and shutdown of the power supply IC. From the top to bottom, the diagram shows the enable signal En, the first power supply voltage Vprereg, the second power supply voltage Vreg, the control input signal PGDIN, the on / off states of the output transistors M1 and M2, and the flag signal PGDOUT.

[0152] First, the enable signal En switches from low to high (timing t1). Then, the first power supply voltage Vprereg starts to rise (timing t2). Then, the first power supply voltage Vprereg reaches a threshold voltage Vth1 (timing t3). The threshold voltage Vth1 is the threshold voltage of the output transistor M1 as well as the threshold voltage of the inverters IV3 and IV4. When the first power supply voltage Vprereg reaches the threshold voltage Vth1, the first power supply voltage Vprereg is applied to the gate of the output transistor M1 via the pull-up resistor R1, switching the output transistor M1 from an off state to an on state.

[0153] When the second power supply voltage Vreg is at a low level (less than or equal to the threshold voltage Vth2), the level shift circuit 51 outputs a high-level signal as an initial value. Until the first power supply voltage Vprereg reaches the threshold voltage Vth1, the outputs of the inverters IV3 and IV4 are logically undefined. However, once the first power supply voltage Vprereg reaches the threshold voltage Vth1, the output of the inverter IV4 is determined to be at a high level, and the output transistor M1 is turned on.

[0154] Note that, until the first power supply voltage Vprereg reaches the threshold voltage Vth1 (timing t2 to t3), the outputs of the inverters IV3 and IV4 are logically indeterminate, but the voltage level of the gate of the output transistor M1 is determined by applying the first power supply voltage Vprereg to the gate of the output transistor M1 via the pull-up resistor R1.

[0155] After that, the second power supply voltage Vreg starts to rise (timing t4), and reaches the threshold voltage Vth2 (timing t5). The threshold voltage Vth2 is the threshold voltage of the output transistor M2 and also the threshold voltage of the inverters IV1 and IV2.

[0156] Until the second power supply voltage Vreg reaches the threshold voltage Vth2 (timing t4 to t5), the control input signal PGDIN is at a low level, and the outputs of the inverters IV1 and IV2 are logically undefined. At this time, the second power supply voltage Vreg is applied to the gate of the output transistor M2 via the pull-up resistor R2, but the output transistor M2 is in an off state.

[0157] When the second power supply voltage Vreg reaches the threshold voltage Vth2, the control input signal PGDIN goes high, and the output of the inverter IV2 is set to a high level. This switches the output transistor M2 to the on state. That is, both the output transistors M1 and M2 are now in the on state.

[0158] In this embodiment, until the second power supply voltage Vreg reaches the threshold voltage Vth2 (timing t4 to t5), the output transistor M1 is already turned on by the first power supply voltage Vprereg, and therefore the flag signal PGDOUT output from the PGD terminal is prevented from rising.

[0159] The pull-up resistor R2 that pulls up the gate of the output transistor M2 to the second power supply voltage Vreg is not necessarily provided. However, by providing the pull-up resistor R2, the second power supply voltage Vreg can be applied to the gate of the output transistor M2 via the pull-up resistor R2 even when the output of the inverter IV2 is in a logically undefined state, and the voltage level of the gate of the output transistor M2 can be determined.

[0160] Furthermore, when the power supply IC is started up in this way and the output voltage Vout rises and reaches the set voltage value, the control input signal PGDIN is switched from high to low. As a result, the levels of the gates of the output transistors M1 and M2 become low, and both the output transistors M1 and M2 are turned off. As a result, the flag signal PGDOUT is switched from low to high.

[0161] Next, the operation of the power supply IC during shutdown will be described. As shown in Figure 18, the enable signal En falls from high to low (timing t6). This causes the output voltage Vout to fall, and the control input signal PGDIN to switch from low to high. This causes both output transistors M1 and M2 to switch from off to on. Therefore, the flag signal PGDOUT switches from high to low.

[0162] Thereafter, the first power supply voltage Vprereg and the second power supply voltage Vreg start to fall (timing t7). Because the capacitor CREG is connected to the VREG terminal, the second power supply voltage Vreg falls more slowly than the first power supply voltage Vprereg.

[0163] When the first power supply voltage Vprereg falls below the threshold voltage Vth1, the output transistor M1 is turned off (timing t8). At this time, the second power supply voltage Vreg is equal to or higher than the threshold voltage Vth2, so the output transistor M2 is turned on. Therefore, the flag signal PGDOUT is maintained at a low level.

[0164] After that, when the second power supply voltage Vreg falls below the threshold voltage Vth2, the control input signal PGDIN switches from high to low (timing t9), turning off the output transistor M2. Here, both the output transistors M1 and M2 are turned off.

[0165] As described above, in this embodiment, the output transistors M1 and M2 can be controlled in a state in which at least one of the first power supply voltage Vprereg and the second power supply voltage Vreg is activated (the period from timing t3 to t9).

[0166] 19 is a diagram showing the configuration of a power-good circuit 5 according to a second embodiment of the present disclosure. The power-good circuit 5 shown in FIG. 19 further includes a control transistor M3 compared to the configuration according to the first embodiment (FIG. 17). Note that the configuration shown in FIG. 19 does not include the level shift circuit 51 and the inverters IV3 and IV4.

[0167] The control transistor M3 is an NMOS transistor. The drain of the control transistor M3 is connected to the gate of the output transistor M1. The source of the control transistor M3 is connected to a terminal to which a ground potential is applied. The gate of the control transistor M3 is connected to a terminal to which a second power supply voltage Vreg is applied.

[0168] 20 is a timing chart showing the operation of the power-good circuit 5 according to the second embodiment at the start-up and shutdown of the power supply IC. From the top to bottom, the diagram shows the enable signal En, the first power supply voltage Vprereg, the second power supply voltage Vreg, the control input signal PGDIN, the on / off states of the output transistors M1 and M2 and the control transistor M3, and the flag signal PGDOUT.

[0169] When the power supply IC is started up, the first power supply voltage Vprereg reaches the threshold voltage Vth1 (at timing t11), and the first power supply voltage Vprereg is applied to the gate of the output transistor M1 via the pull-up resistor R1, switching the output transistor M1 from an off state to an on state. At this time, the output transistor M2 and the control transistor M3 are both in an off state.

[0170] Thereafter, when the second power supply voltage Vreg reaches the threshold voltage Vth2 (timing t12), the output transistor M2 and the control transistor M3 are switched from the OFF state to the ON state. Since the control transistor M3 is switched ON, the output transistor M1 is switched OFF.

[0171] In this embodiment, the output transistor M1 remains on until the second power supply voltage Vreg reaches the threshold voltage Vth2, preventing the flag signal PGDOUT from rising. Furthermore, after the output transistor M1 switches from on to off, the flag signal PGDOUT is subsequently controlled by the output transistor M2. That is, in this embodiment, the output transistor M1 is pulled up to the first power supply voltage Vprereg by the pull-up resistor R1, thereby giving priority to setting the flag signal PGDOUT to a low level at startup.

[0172] Furthermore, when the power supply IC is shut down, the enable signal En switches from high to low (timing t13). At this time, the output voltage Vout falls, and the control input signal PGDIN switches from low to high. This causes the output transistor M2 to switch from an off state to an on state. Therefore, the flag signal PGDOUT switches from high to low.

[0173] Thereafter, when the second power supply voltage Vreg falls below the threshold voltage Vth2 (timing t14), the output transistor M2 and the control transistor M3 are both switched from the on state to the off state, thereby turning both the output transistors M1 and M2 off.

[0174] 21 is a diagram showing the configuration of a power-good circuit 5 according to a third embodiment of the present disclosure. The power-good circuit 5 shown in FIG. 21 includes an output transistor M1, voltage-dividing resistors R3 and R4, inverters IV11 and IV12, and diodes D1 and D2. That is, in this embodiment, there is one output transistor.

[0175] The voltage dividing resistors R3 and R4 are connected in series between the application terminal of the first power supply voltage Vprereg and the application terminal of the ground potential. A node N1 to which the voltage dividing resistors R3 and R4 are connected is connected to the gate of the output transistor M1.

[0176] The input terminal of the inverter IV11 is connected to a terminal to which the control input signal PGDIN is applied, and the output terminal of the inverter IV11 is connected to the input terminal of the inverter IV12.

[0177] The inverter IV11 uses the second power supply voltage Vreg as its power supply voltage and has the same configuration as the inverter IV1 described above. The inverter IV12 has a PMOS transistor PM and an NMOS transistor NM. The source of the PMOS transistor PM is connected to the application terminal of the second power supply voltage Vreg. The drain of the PMOS transistor PM is connected to the drain of the NMOS transistor NM. The source of the NMOS transistor NM is connected to the application terminal of the ground potential.

[0178] A node N3, where the gate of the PMOS transistor PM and the gate of the NMOS transistor NM are connected, serves as an input terminal. A node N2, where the drain of the PMOS transistor PM and the drain of the NMOS transistor NM are connected, serves as an output terminal, and is connected to the node N1.

[0179] The anode of the diode D1 is connected to the application terminal of the first power supply voltage Vprereg. The cathode of the diode D1 is connected to one end of the voltage dividing resistor R3. The anode of the diode D2 is connected to the drain of the PMOS transistor PM. The cathode of the diode D2 is connected to the node N2.

[0180] 22 is a timing chart showing the operation of the power-good circuit 5 according to the third embodiment at the start-up and shutdown of the power supply IC. From the top to bottom, the diagram shows the enable signal En, the first power supply voltage Vprereg, the second power supply voltage Vreg, the control input signal PGDIN, the on / off state of the output transistor M1, and the flag signal PGDOUT.

[0181] When the enable signal En switches from low to high, the first power supply voltage Vprereg begins to rise and reaches the threshold voltage Vth11 (timing t21). At this time, the first power supply voltage Vprereg is divided by voltage-dividing resistors R3 and R4, and the resulting voltage is applied to the gate of the output transistor M1. The resistance of voltage-dividing resistor R4 is higher than the resistance of voltage-dividing resistor R3 (e.g., R3 = 1 MΩ, R4 = 5 MΩ). This switches the output transistor M1 from an off state to an on state. At this time, because the control input signal PGDIN is low, the outputs of inverters IV11 and IV12 are logically undefined.

[0182] Thereafter, when the second power supply voltage Vreg reaches the threshold voltage Vth2 (timing t22), the control input signal PGDIN goes high, and the output of the inverter IV12 is fixed at the high level. The threshold voltage Vth2 is the threshold voltage of the output transistor M1 and also the threshold voltage of the inverters IV11 and IV12.

[0183] When the first power supply voltage Vprereg rises, the path from the node N1 to the application terminal of the second power supply voltage Vreg, which is at the level of the ground potential, via the PMOS transistor PM can be cut off by the diode D2.

[0184] Furthermore, when the power supply IC is shut down, the enable signal En switches from high to low (timing t23). At this time, the output voltage Vout falls, and the control input signal PGDIN switches from low to high. This causes the output transistor M1 to switch from an off state to an on state. Therefore, the flag signal PGDOUT switches from high to low.

[0185] After that, the first power supply voltage Vprereg falls to ground potential. Even if the first power supply voltage Vprereg is at ground potential, the output of the inverter IV12 is at high level, so the output transistor M1 remains on. At this time, the path from the node N1 to the application terminal of the first power supply voltage Vprereg, which is at ground potential, via the voltage-dividing resistor R3 can be blocked by the diode D1.

[0186] When the second power supply voltage Vreg falls below the threshold voltage Vth2 (timing t24), the control input signal PGDIN goes low, causing the output of the inverter IV2 to become logically undefined, and the output transistor M1 is switched from the on state to the off state.

[0187] <Others> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0188] <Note> As described above, a power-good circuit (5) according to one aspect of the present disclosure includes: a first output transistor (M1) having a first terminal connected to a power-good terminal (PGD) and a second terminal connected to an application terminal of ground potential; a resistor (R1) for applying a voltage based on a first power supply voltage (Vprereg) to a control terminal of the first output transistor; a first inverter stage (IV1, IV2) that uses a second power supply voltage (Vreg) as a power supply voltage and is configured to be able to input a control input signal (PGDIN); and a second output transistor (M2) having a control terminal connected to an output terminal of the first inverter stage, a first terminal connected to the power-good terminal, and a second terminal connected to an application terminal of ground potential, and the power-good terminal is configured to be able to be pulled up to the second power supply voltage (first configuration).

[0189] In the first configuration, the resistor may be a voltage dividing resistor (R3, R4) connected in series between an application terminal of the first power supply voltage (Vprereg) and an application terminal of a ground potential, and a connection node (N1) of the voltage dividing resistors may be connected to a control terminal of the first output transistor (M1) (second configuration).

[0190] In addition, in the second configuration, the first output transistor (M1) and the second output transistor (M1) may be the same transistor, and may include a first diode (D1) for blocking a path from the connection node (N1) to the application terminal of the first power supply voltage (Vprereg) via the voltage dividing resistor (R3), and a second diode (D2) for blocking a path from the connection node to the application terminal of the second power supply voltage (Vreg) via the first inverter stage (IV12) (third configuration).

[0191] In addition, in the first configuration, the resistor may be a first pull-up resistor (R1) connected between the application terminal of the first power supply voltage (Vprereg) and the control terminal of the first output transistor (M1) (fourth configuration).

[0192] In the fourth configuration, the first output transistor (M1) and the second output transistor (M2) may be separate transistors (fifth configuration).

[0193] In addition, the fifth configuration may be configured to include a second pull-up resistor (R2) connected between the control terminal of the second output transistor (M2) and the application terminal of the second power supply voltage (Vreg) (sixth configuration).

[0194] Furthermore, in the fifth or sixth configuration, a seventh configuration may be provided, which further comprises: a level shift circuit (51) configured to convert the level of the control input signal (PGDIN) from the second power supply voltage (Vreg) to the first power supply voltage (Vprereg); and a second inverter stage (IV3, IV4) provided between an output terminal of the level shift circuit and a control terminal of the first output transistor (M1), and using the first power supply voltage as a power supply voltage.

[0195] Furthermore, the fifth configuration may be configured to include a control transistor (M3) having a first terminal connected to the control terminal of the first output transistor (M1), a second terminal connected to the application terminal of the ground potential, and a control terminal connected to the application terminal of the second power supply voltage (Vreg) (eighth configuration).

[0196] Furthermore, a semiconductor device (1) according to one aspect of the present disclosure is configured to include a power-good circuit (5) of any one of the first to eighth configurations described above; a pre-regulator (2) to which an enable signal (En) can be input and configured to generate the first power supply voltage (Vprereg); a reference voltage generating unit (3) configured to generate a reference voltage (Vref) based on the first power supply voltage; and a regulator (4) activated based on the reference voltage and configured to generate the second power supply voltage (Vreg) (ninth configuration).

[0197] 23 is a diagram showing the overall configuration of a switching power supply. The switching power supply 1 of this configuration example is a synchronous rectification step-down DC / DC converter that generates a desired output voltage VOUT (e.g., 0.6 to 5.5 V) from an input voltage VIN (e.g., 4 to 16 V), and includes a semiconductor device 100 and various discrete components (e.g., capacitors C1 to C5, an inductor L1, a resistor R ＩＬＩＭ , and resistors R2 to R5).

[0198] The switching power supply device 1 can be suitably used as a step-down power supply for, for example, a SoC (system-on-a-chip), an FPGA (field-programmable gate array), or a microprocessor, or as a step-down power supply for a server or a base station.

[0199] The semiconductor device 100 is a monolithic semiconductor integrated circuit device (a so-called power supply control IC) that comprehensively controls the switching power supply device 1. The semiconductor device 100 has a plurality of external terminals (BST, AGND, ILIM, MODE, SS / REF, RGND, FB, PGD, VIN, PGND, and VCC in this figure) as means for establishing electrical connection with the outside of the device.

[0200] The BST terminal is a bootstrap terminal. A bootstrap capacitor C4 (e.g., 0.1 μF) is externally connected between the BST terminal and the SW terminal. The boost voltage VB (≈ VSW + VCC) that appears at the BST terminal serves as the gate drive voltage for the upper transistor (not shown in this figure) built into the semiconductor device 100.

[0201] The AGND terminal is a ground terminal for the control circuit (analog circuit).

[0202] The ILIM terminal is a terminal for setting an overcurrent detection value. The overcurrent detection value IOCP is set by an external resistor R ＩＬＩＭ It is possible to set it arbitrarily using

[0203] The MODE terminal is a terminal for setting the switching control mode. For example, by pulling up the MODE terminal or adjusting the external resistor R2 connected between the MODE terminal and the ground terminal (=AGND), it is possible to arbitrarily switch between combinations of switching frequency (e.g., 600 kHz, 800 kHz, and 1 MHz) and operation mode (light load mode and fixed PWM [pulse width modulation] mode).

[0204] The SS / REF terminal is a soft-start time setting terminal / internal reference voltage setting terminal. For example, the soft-start time tSS of the output voltage VOUT can be adjusted arbitrarily depending on the capacitance value of a capacitor C5 externally connected between the SS / REF terminal and the ground terminal (= RGND terminal). The soft-start function allows the output voltage VOUT to rise gradually, preventing overshoot and inrush current of the output voltage VOUT. Furthermore, the semiconductor device 100 can externally input an internal reference voltage VREF from an external power supply using the SS / REF terminal for output voltage tracking. Therefore, the internal reference voltage VREF can be set within any voltage range after startup to a predetermined target value (e.g., 0.6 V).

[0205] The RGND terminal is a remote sense ground terminal. If the remote sense function is omitted, the components connected to the RGND terminal can be connected to the AGND terminal.

[0206] The FB terminal is an output voltage feedback terminal. The FB terminal is connected to the connection node (= the application terminal of the feedback voltage VFB) between resistors R3 and R4, which are connected in series between the application terminal of the output voltage VOUT and the ground terminal (= the RGND terminal). The target value of the output voltage VOUT can be set as {(R3 + R4) / R4} × VREF.

[0207] The EN terminal is an enable terminal. For example, when the enable voltage VEN applied to the EN terminal becomes equal to or greater than an upper threshold (e.g., 1.22 V), the semiconductor device 100 starts up, and when the enable voltage VEN becomes equal to or less than a lower threshold (e.g., 1.02 V), the semiconductor device 100 shuts down. The EN terminal must be terminated. It is also desirable that the enable voltage VEN start up simultaneously with or after the input voltage VIN is turned on (VIN=VEN).

[0208] The PGD terminal is a power good terminal. Because the PGD terminal is an open-drain output, it requires a pull-up resistor R5. If the PGD terminal is not used, it can be left floating or connected to ground.

[0209] The VIN terminal is a power supply input terminal. An input smoothing capacitor C1 (e.g., a ceramic capacitor of about 0.1 μF) is externally connected between the VIN terminal and the ground terminal (= PGND terminal). Capacitor C1 is effective in reducing input ripple noise, and this effect is best achieved by placing it as close as possible to the VIN terminal and PGND terminal.

[0210] The SW terminal is a switching output terminal. The SW terminal is connected to the source of the upper transistor and the drain of the lower transistor (neither of which are shown in this figure) built into the semiconductor device 100, and outputs a rectangular-wave switching voltage VSW. An inductor L1 is externally connected between the SW terminal and the application terminal of the output voltage VOUT. A capacitor C3 (e.g., a ceramic capacitor) is externally connected between the application terminal of the output voltage VOUT and the RGND terminal. As such, the switching power supply device 1 requires an LC filter for output smoothing in order to supply a continuous current to the load.

[0211] The PGND terminal is the ground terminal of the switching output stage (=power circuit).

[0212] The VCC terminal is an internal power supply output terminal. The internal power supply voltage VCC (e.g., 3 V) output from the VCC terminal is supplied to, for example, a control circuit (=analog circuit) of the semiconductor device 100. Note that a capacitor C2 (e.g., a ceramic capacitor of about 1 μF) is externally connected between the VCC terminal and the ground terminal (=AGND terminal).

[0213] 24 is a diagram showing the internal configuration of a semiconductor device 100. The semiconductor device 100 of this configuration example includes an upper transistor 101, a lower transistor 102, an upper driver 103, a lower driver 104, a control logic 105, an internal power supply voltage generation circuit 106, an internal reference voltage generation circuit 107, an error amplifier 108, a capacitor 109, a ramp voltage generation circuit 110, a voltage superposition circuit 111, a main comparator 112, an on-time setting circuit 113, a P-channel MOS field-effect transistor 114, an N-channel MOS field-effect transistor 115, comparators 116, 117, and 118, an under input voltage malfunction prevention circuit 119, a temperature protection circuit 120, a low voltage protection circuit 121, an overvoltage protection circuit 122, a power good circuit 123, an N-channel MOS field-effect transistor 124, and a mode selector 125.

[0214] The drain of the upper transistor 101 (for example, an N-channel MOS field effect transistor) is connected to the VIN terminal. The source of the upper transistor 101 is connected to the SW terminal. The gate of the upper transistor 101 is connected to the application terminal of the upper gate signal G1 (= the output terminal of the upper driver 103). The upper transistor 101 is turned on when the upper gate signal G1 is at a high level (≒ VB) and turned off when the upper gate signal G1 is at a low level (≒ VSW).

[0215] The drain of the lower transistor 102 (e.g., an N-channel MOS field effect transistor) is connected to the SW terminal. The source of the lower transistor 102 is connected to the PGND terminal. The gate of the lower transistor 102 is connected to the application terminal of the lower gate signal G2 (= the output terminal of the lower driver 104). The lower transistor 102 is turned on when the lower gate signal G2 is at a high level (≈ VCC) and turned off when the lower gate signal G2 is at a low level (≈ PGND).

[0216] The upper transistor 101 and the lower transistor 102 connected in this manner form a step-down switching output stage that employs synchronous rectification, together with discrete components (inductor L1 and capacitor C3) externally attached to the semiconductor device 100. However, the rectification method is not necessarily limited to synchronous rectification, and a rectifying diode may be used instead of the lower transistor 102.

[0217] If a large current output (for example, a maximum output of 20 A) is required for the switching power supply device 1, it is desirable to use elements with low on-resistance as the upper transistor 101 and the lower transistor 102.

[0218] Furthermore, the upper transistor 101 and the lower transistor 102 do not necessarily need to be built into the semiconductor device 100, but may be attached externally to the semiconductor device 100 as discrete components.

[0219] The high-side driver 103 operates by receiving the boot voltage VB and the switch voltage VSW, and generates the high-side gate signal G1 based on the high-side control signal S1 output from the control logic 105. For example, the high-side driver 103 sets the high-side gate signal G1 to a high level (≒VB) when the high-side control signal S1 is at a high level, and sets the high-side gate signal G1 to a low level (≒VSW) when the high-side control signal S1 is at a low level.

[0220] The low-side driver 104 operates by receiving the internal power supply voltage VCC and the ground voltage PGND, and generates the low-side gate signal G2 based on the low-side control signal S2 output from the control logic 105. For example, the low-side driver 104 sets the low-side gate signal G2 to a high level (≈ VCC) when the low-side control signal S2 is at a high level, and sets the low-side gate signal G2 to a low level (≈ PGND) when the low-side control signal S2 is at a low level.

[0221] When an enable signal (=enable voltage VEN) input to an EN terminal is at a high level, the control logic 105 complementarily turns on / off the upper transistor 101 and the lower transistor N2 using a fixed on-time control method.

[0222] More specifically, the control logic 105 sets the upper control signal S1 to a high level and the lower control signal S2 to a low level when turning on the upper transistor 101 and turning off the lower transistor N2. Also, the control logic 105 sets the upper control signal S1 to a low level and the lower control signal S2 to a high level when turning off the upper transistor 101 and turning on the lower transistor 102.

[0223] In this way, when the upper transistor 101 and the lower transistor 102 that form the switching output stage are complementarily turned on / off, a switch voltage VSW having a rectangular waveform (high level: VB, low level: PGND) is generated at the SW terminal. The switching power supply device 1 can generate a desired output voltage VOUT by rectifying and smoothing this switch voltage VSW with an LC filter (= inductor L1 and capacitor C3).

[0224] The control logic 105 also has a function of preventing the upper transistor 101 and the lower transistor 102 from being turned on simultaneously in order to prevent excessive through current. Furthermore, the control logic 105 also has a function of forcibly stopping the on / off driving of the upper transistor 101 and the lower transistor 102 based on various protection signals (HOCP, LOCP, ZX / ROCP, UVLO, TSD, SCP, and OVP). For example, when an abnormality is detected, the control logic 105 sets both the upper control signal S1 and the lower control signal S2 to a low level, thereby turning off both the upper transistor 101 and the lower transistor 102.

[0225] The internal power supply voltage generating circuit 106 generates an internal power supply voltage VCC (for example, 3 V) and outputs it to the VCC terminal and each part of the semiconductor device 100 .

[0226] When an enable signal (=enable voltage VEN) input to an EN terminal is at a high level, the internal reference voltage generating circuit 107 generates a predetermined internal reference voltage VREF from the internal power supply voltage VCC and outputs it to an SS / REF terminal.

[0227] The error amplifier 108 operates using the RGND terminal as a reference potential and generates an error signal Sa corresponding to the difference between the internal reference voltage VREF input to the non-inverting input terminal (+) and the feedback voltage VFB input to the inverting input terminal (-). Therefore, the error signal Sa increases when VREF>VFB and decreases when VREF<VFB.

[0228] The capacitor 109 is provided between the output terminal and the ground terminal (=RGND terminal) of the error amplifier 108. The capacitor 109 is an example of a phase compensation circuit, and prevents the error amplifier 108 from oscillating.

[0229] The ramp voltage generating circuit 110 generates a ramp voltage VR having a sawtooth or triangular waveform.

[0230] The voltage superimposing circuit 111 superimposes the ramp voltage VR on the feedback voltage VFB to generate a slope signal Sb.

[0231] The main comparator 112 compares the error signal Sa input to the non-inverting input terminal (+) with the slope signal Sb input to the inverting input terminal (-) to generate a comparison signal Sc and output it to the on-time setting circuit 113. The comparison signal Sc goes high when Sa > Sb and goes low when Sa < Sb. In other words, the main comparator 112 raises the comparison signal Sc to high level to feed back to the on-time setting circuit 113 that the output voltage VOUT has dropped below the target value.

[0232] The ON time setting circuit 113 sets a predetermined ON time Ton when the comparison signal Sc rises to a high level. The control logic 105 keeps the upper transistor 101 on and the lower transistor N2 off until the ON time Ton has elapsed.

[0233] In this way, of the above components, the error amplifier 108, the main comparator 112, and the on-time setting circuit 113 form an output feedback control circuit that controls the drive of the switching output stage using a fixed on-time control method so that the feedback voltage VFB matches the internal reference voltage VREF.

[0234] However, the output feedback control method is not necessarily limited to the fixed on-time control method, and a voltage mode control method, a current mode control method, a hysteresis control method (ripple control method), or the like may also be adopted.

[0235] The drain of the transistor 114 is connected to the VCC terminal (= the terminal to which the internal power supply voltage VCC is applied), and the source of the transistor 114 is connected to the BST terminal (= the terminal to which the boot voltage VB is applied). The transistor 114 connected in this manner forms a bootstrap circuit together with a capacitor C4 externally connected between the BST terminal and the SW terminal.

[0236] The transistor 114 is turned on when the control signal S3 (= a binary signal having essentially the same logical level as the control signal S1) input to the gate from the control logic 105 is at a low level, and is turned off when the control signal S3 is at a high level.

[0237] The above bootstrap circuit generates a boot voltage VB (≈VSW+VCC) that is always higher than the switch voltage VSW by the voltage across the capacitor C4 (≈VCC). That is, the boot voltage VB is VB≈VIN+VCC during the high-level period of the switch voltage VSW (VSW≈VIN), and VB≈VCC during the low-level period of the switch voltage VSW (VSW≈PGND).

[0238] The boot voltage VB thus generated is supplied to the upper driver 103 and is used as the high level of the upper gate signal G1 (=gate voltage for turning on the upper transistor 101). Therefore, during the on-period of the upper transistor 101, the high level (≈VB) of the upper gate signal G1 is raised to a voltage value (≈VIN+VCC) higher than the high level (≈VIN) of the switch voltage VSW, thereby increasing the gate-source voltage of the upper transistor 101 and enabling the upper transistor 101 to be reliably turned on.

[0239] As a component of the bootstrap circuit, a diode with an anode connected to the VCC terminal and a cathode connected to the BST terminal may be used instead of the transistor 114. In this case, the boot voltage VB is VB≈VSW+VCC-Vf (where Vf is the forward voltage drop of the diode).

[0240] The drain of the transistor 115 is connected to the SW terminal (= the application terminal of the switch voltage VSW). The source of the transistor 115 is connected to the PGND terminal (= the ground terminal of the power circuit). The transistor 114 is turned on when the control signal S4 input to the gate from the control logic 105 is at a high level, and turned off when the control signal S4 is at a low level.

[0241] The transistor 115 connected in this manner functions as a resistive load (e.g., 80Ω) for discharging the output smoothing capacitor C3 when the semiconductor device 100 is shut down from an operating state by enable control. That is, the transistor 115 may be turned on when both the upper transistor 101 and the lower transistor 102 are turned off by shutting down the semiconductor device 100. The output voltage VOUT may be discharged to, for example, 10% of the target value.

[0242] The comparator 116 monitors the voltage (=VIN-VSW) across the upper transistor 101 for each cycle of the switching period and generates the upper overcurrent detection signal HOCP. When the current flowing through the upper transistor 101 while the upper transistor 101 is on reaches the overcurrent detection value IOCPH, the upper overcurrent detection signal HOCP goes high. At this time, the control logic 105 turns off the upper transistor 101 and turns on the lower transistor 102.

[0243] The comparator 117 monitors the voltage (=VSW) across the lower-side transistor 102 every cycle of the switching period and generates the lower-side overcurrent detection signal LOCP. In other words, the comparator 117 is a lower-side overcurrent detection circuit. When the current flowing through the lower-side transistor 102 reaches the overcurrent detection value IOCPL while the lower-side transistor 102 is on, the lower-side overcurrent detection signal LOCP goes high. At this time, the control logic 105 turns off the upper-side transistor 101 and keeps the lower-side transistor 102 on, even if the feedback voltage FB falls below the internal reference voltage VREF. Thereafter, when the current flowing through the lower-side transistor 102 falls below the upper limit, the upper-side transistor 101 can be turned on.

[0244] The comparator 118 monitors the voltage (=VSW) across the lower-side transistor 102 for each cycle of the switching period and generates a zero-cross / sink (reverse) overcurrent detection signal ZX / ROCP. For example, in the light-load mode, the control logic 105 detects the zero-cross timing of the current flowing through the lower-side transistor 102 when the lower-side transistor 102 is on, and turns off the lower-side transistor 102. In the fixed PWM mode, the control logic 105 detects that the sink current (reverse current) flowing from the SW terminal toward the lower-side transistor 102 when the lower-side transistor 102 is on has reached an upper limit, and turns off the lower-side transistor 102 and turns on the upper-side transistor 101.

[0245] The under voltage lockout (UVLO) circuit 119 monitors the input voltage VIN and the internal power supply voltage VCC to provide UVLO (under voltage lock out) protection. For example, if the input voltage VIN falls below 1.85 V or the internal power supply voltage VCC falls below 2.5 V, the semiconductor device 100 shuts down. On the other hand, if the input voltage VIN rises above 2.4 V and the internal power supply voltage VCC rises above 2.8 V, the semiconductor device 100 starts up.

[0246] The temperature protection circuit 120 monitors the junction temperature Tj of the semiconductor device 100 and applies temperature protection. For example, when the junction temperature Tj reaches 175° C. or higher, the semiconductor device 100 shuts down. Thereafter, when the junction temperature Tj falls to 150° C. or lower (hysteresis 25° C.), the semiconductor device 100 automatically restarts.

[0247] The low-voltage protection circuit 121 monitors the feedback voltage VFB and applies low-voltage protection. For example, after the semiconductor device 100 is started, if the feedback voltage VFB falls to 80% or less of the internal reference voltage VREF, the semiconductor device 100 shuts down. Note that, after 117 ms has elapsed since the shutdown, the semiconductor device 100 automatically restarts.

[0248] The overvoltage protection circuit 122 monitors the feedback voltage VFB and applies overvoltage protection. For example, when the feedback voltage VFB becomes 116% or more of the internal reference voltage VREF, the lower transistor 102 turns on, suppressing the increase in the output voltage VOUT. Thereafter, when the feedback voltage VFB becomes 105% or less of the internal reference voltage VREF, the normal operating state is restored.

[0249] The power-good circuit 123 monitors the feedback voltage VFB and performs on / off control of the transistor 124 (and consequently, output control of the power-good signal PGD). For example, when the output voltage VOUT reaches 92.5% to 105% of the target value and this state continues for 0.9 ms, the transistor 124 is turned off. On the other hand, when the output voltage VOUT falls to 116% or more or 80% or less of the target value, the transistor 124 is turned on.

[0250] The drain of the transistor 124 is connected to the PGD terminal. The source of the transistor 124 is connected to the ground terminal (=AGND terminal). As described above, the transistor 124 is turned on / off by the power good circuit 123. When the transistor 124 is off, the PGD terminal is in a high impedance state. On the other hand, when the transistor 124 is on, the PGD terminal is pulled down to the ground terminal. By providing such a power good function, sequence control of the entire system becomes possible.

[0251] The mode selector 125 sets the switching frequency FREQ and the operating mode MODE according to the state of the MODE terminal. When the light load mode is selected as the operating mode, switching is performed using PWM mode control in heavy load conditions, and switching is performed using LLM (light load mode) mode control in light load conditions to improve efficiency. On the other hand, when the fixed PWM mode is selected as the operating mode, switching is performed using PWM mode control forcibly regardless of the load weight. In the light load mode, efficiency is improved in the light load range, making it suitable for devices that require reduced standby power consumption.

[0252] 25 is a diagram showing a comparative example (i.e., a general configuration to be compared with the embodiments described later) of the lower overcurrent detection circuit 117. The lower overcurrent detection circuit 117 of this comparative example includes a current generating circuit 2 and a comparator COMP1.

[0253] The current generating circuit 2 generates a current I corresponding to the current flowing through the lower transistor 102. ＩＬＩＭ Generates a current I ＩＬＩＭ is the resistance R ＩＬＩＭ The voltage V ＩＬＩＭ is converted to

[0254] The comparator COMP1 outputs a voltage V ＩＬＩＭ The overcurrent detection value IOCPL is calculated by comparing the threshold value (for example, 1.2 V) and the resistance R ＩＬＩＭ is determined by the resistance value of

[0255] The current generating circuit 2 has a current source IS1, P-channel MOS field effect transistors Q1 to Q3 and Q7 to Q8, N-channel MOS field effect transistors Q4 to Q6, and switches S1 and S2.

[0256] The sources of the P-channel MOS field effect transistors Q1 to Q3 and Q7 to Q8 are connected to a power supply voltage application terminal. The gates of the P-channel MOS field effect transistors Q1 to Q3 and the drain of the P-channel MOS field effect transistor Q1 are connected to a first terminal of a current source IS1. The second terminal of the current source IS1 is connected to the ground terminal.

[0257] The drain of the P-channel MOS field effect transistor Q2 is connected to the gates of the N-channel MOS field effect transistors Q4 and Q5 and the drain of the N-channel MOS field effect transistor Q4, whose source is connected to the PGND terminal.

[0258] The drain of the P-channel MOS field effect transistor Q3 is connected to the gates of the P-channel MOS field effect transistors Q7 and Q8 via the switch S1, and to the drain of the N-channel MOS field effect transistor Q5.

[0259] The source of N-channel MOS field effect transistor Q5 is connected to the drain of N-channel MOS field effect transistor Q6 and the drain of P-channel MOS field effect transistor Q7. A lower gate signal G2 is supplied to the gate of N-channel MOS field effect transistor Q6. A switch voltage VSW is applied to the source of N-channel MOS field effect transistor Q6. A node NA, which connects the drain of N-channel MOS field effect transistor Q6 and the drain of P-channel MOS field effect transistor Q7, is connected to the ground terminal via switch S2.

[0260] The drain of the N-channel MOS field effect transistor Q8 is connected to the non-inverting input terminal (+) of the comparator COMP1 and the ILIM terminal.

[0261] The current I generated by the current generating circuit 2 ＩＬＩＭ and the current I flowing through the inductor L1 Ｌ The following relationship exists between

[0262] When the lower transistor 102 is on, the current I Ｌ is expressed by the following formula (1): ＯＮＬ is the on-resistance of the lower transistor 102. Ｌ =(PGND-VSW) / R ＯＮＬ …(1)

[0263] When the lower transistor 102 is on, the following equation (2) holds true for the N-channel MOS field effect transistor Q6. ＲＥＦ is the on-resistance of the N-channel MOS field effect transistor Q6. The mirror ratio between the P-channel MOS field effect transistor Q7 and the P-channel MOS field effect transistor Q8 is 1:K. ＩＬＩＭ / K=(PGND-VSW) / R ＲＥＦ …(2)

[0264] From the above equations (1) and (2), the following equation (3) is established: K×R ＯＮＬ / R ＲＥＦ is, for example, 10 －５ It is set to I ＩＬＩＭ =I Ｌ ×K×R ＯＮＬ / R ＲＥＦ …(3)

[0265] 26 is a timing chart showing ideal waveforms of voltages and currents at various points in the switching power supply device 1. Ｌ is K×R ＯＮＬ / R ＲＥＦ is multiplied to get the current I ＩＬＩＭ Then, the current I ＩＬＩＭ is the resistance R ＩＬＩＭ The voltage V ＩＬＩＭ is converted to

[0266] However, the current generating circuit 2 operates when the lower transistor 102 is on. Specifically, when the lower transistor 102 is on, that is, when the lower gate signal G2 is at high level, the N-channel MOS field effect transistor Q6 is on, the switch S1 is on, and the switch S2 is off. On the other hand, when the lower transistor 102 is off, that is, when the lower gate signal G2 is at low level, the N-channel MOS field effect transistor Q6 is off, the switch S1 is off, and the switch S2 is on. As a result, when the lower transistor 102 is off, the gates of the P-channel MOS field effect transistors Q7 and Q8 are in a floating state, and this state is maintained, so that the current I ＩＬＩＭ is the current I Ｌ Therefore, the actual waveforms of the voltages and currents at each part of the switching power supply device are as shown by the solid lines in Fig. 27. In Fig. 27, ideal waveforms are shown by the broken lines. ＩＬＩＭ is the current I Ｌ As a result, there is a risk that overcurrent may go undetected.

[0267] In view of the above considerations, a novel embodiment that can suppress overcurrent detection failure will be proposed below.

[0268] <Lower-Side Overcurrent Detection Circuit (First Embodiment)> Figure 28 is a diagram showing a first embodiment of the lower-side overcurrent detection circuit 117. In Figure 28, the same components as those in Figure 25 are designated by the same reference numerals, and detailed descriptions thereof will be omitted. The lower-side overcurrent detection circuit 117 of this embodiment, together with the control logic 105, constitutes a switching control circuit that controls the upper-side transistor 101 and the lower-side transistor 102.

[0269] The lower-side overcurrent detection circuit 117 of this embodiment includes current generation circuits 2 and 3 and a comparator COMP1.

[0270] The current generating circuit 3 generates a ripple current I ＲＩＰＰＬＥ Generates a ripple current I ＲＩＰＰＬＥis greater than zero when the lower transistor 102 switches from off to on, and fluctuates in synchronization with the switching of the upper transistor 101 and the lower transistor 102. ＩＬＩＭ and ripple current I ＲＩＰＰＬＥ and the sum of the current I ＳＵＭ is the resistance R ＩＬＩＭ The voltage V ＩＬＩＭ is converted to

[0271] 29 is a diagram showing a first configuration example of the current generating circuit 3. The current generating circuit 3 of the first configuration example has a current source IS11, N-channel MOS field effect transistors Q11 to Q12 and Q15 to Q17, P-channel MOS field effect transistors Q13 to Q14 and Q18 to Q19, a capacitor C11, and resistors R11 and R12.

[0272] A first terminal of the current source IS11 and the sources of the P-channel MOS field effect transistors Q13 to Q14 and Q18 to Q19 are connected to a power supply voltage application terminal, and a second terminal of the current source IS11 is connected to the gates of the N-channel MOS field effect transistors Q11 and Q12 and the drain of the N-channel MOS field effect transistor Q11.

[0273] The sources of the N-channel MOS field effect transistors Q11 and Q12 are connected to the ground terminal, and the drain of the N-channel MOS field effect transistor Q12 is connected to the gates of the P-channel MOS field effect transistors Q13 and Q14 and the drain of the P-channel MOS field effect transistor Q13.

[0274] The drain of the P-channel MOS field effect transistor Q14 is connected to the drain of the N-channel MOS field effect transistor Q15, whose gate is supplied with an upper gate signal G1.

[0275] The source of the N-channel MOS field effect transistor Q15 is connected to the first end of the capacitor C11, the gates of the N-channel MOS field effect transistors Q16 and Q17, and the drain of the N-channel MOS field effect transistor Q16.

[0276] The source of the N-channel MOS field effect transistor Q16 is connected to the ground terminal via a resistor R11, and the source of the N-channel MOS field effect transistor Q17 is connected to the ground terminal via a resistor R12.

[0277] The drain of the N-channel MOS field effect transistor Q17 is connected to the gates of the P-channel MOS field effect transistors Q18 and Q19 and to the drain of the P-channel MOS field effect transistor Q18. A ripple current I ＲＩＰＰＬＥ is output. Ripple current I ＲＩＰＰＬＥ The ripple current I ＲＩＰＰＬＥ increases over time when the lower transistor 102 is off, and decreases over time when the lower transistor 102 is on. ＩＬＩＭ can be made closer to the ideal waveform.

[0278] For example, if the settings are as follows, the ripple current I ＲＩＰＰＬＥ The maximum value of the current I output from the current source IS11 is 40 μA. ＢＩＡＳ is 0.5 μA. The capacitance of the capacitor is 0.7 pF. The resistance value of resistor R11 is 50 kΩ. The resistance value of resistor R12 is 12.5 kΩ. The mirror ratio between N-channel MOS field effect transistor Q11 and N-channel MOS field effect transistor Q12 is 1:2. The mirror ratio between P-channel MOS field effect transistor Q13 and P-channel MOS field effect transistor Q14 is 1:2. The mirror ratio between N-channel MOS field effect transistor Q16 and N-channel MOS field effect transistor Q17 is 1:4. The mirror ratio between P-channel MOS field effect transistor Q18 and P-channel MOS field effect transistor Q19 is 1:5.

[0279] 31 to 33 may be used instead of the current generating circuit 3 of the first configuration example. The current generating circuits 3 of the second to fourth configuration examples, like the current generating circuit 3 of the first configuration example, have an N-channel MOS field effect transistor Q15 whose gate is supplied with the upper gate signal G1, a capacitor C11, and a resistor R11.

[0280] Furthermore, the current generating circuit 3 of the first configuration example may be replaced by a current generating circuit 3 of a fifth configuration example shown in FIG. 34 . A lower gate signal G2 is supplied to the current generating circuit 3 of the fifth configuration example shown in FIG. 34 . The current generating circuit 3 of the fifth configuration example shown in FIG. 34 has a first circuit 3A and a second circuit 3B. The first circuit 3A of FIG. 34 may be replaced by the first circuit 3A of FIG. 35A or the first circuit 3A of FIG. 35B. The second circuit 3B of FIG. 34 may be replaced by the second circuit 3B of any of FIGS. 36A to 36C. FIG. 37 is a timing chart showing actual waveforms of voltages and currents at various parts of a switching power supply 1 having the current generating circuit 3 of the fifth configuration example shown in FIG. 34 .

[0281] 38 is a diagram showing a second embodiment of the lower-side overcurrent detection circuit 117. The lower-side overcurrent detection circuit 117 of this embodiment, together with the control logic 105, constitutes a switching control circuit that controls the upper-side transistor 101 and the lower-side transistor 102.

[0282] The lower overcurrent detection circuit 117 of this embodiment is configured by adding switches SW1 to SW5, a P-channel MOS field effect transistor Q21, N-channel MOS field effect transistors Q22 and Q23, a capacitor C12, and a current source IS12 to the lower overcurrent detection circuit 117 of the comparative example.

[0283] The switches SW1 to SW3 are turned off when the lower transistor 102 is off, and turned on when the lower transistor 102 is on. The switches SW4 and SW5 are turned on when the lower transistor 102 is off, and turned off when the lower transistor 102 is on.

[0284] The capacitor C12 receives the current I just before the lower transistor 102 turns off. ＩＬＩＭ When the lower transistor 102 is off, the current generating circuit 3 outputs a current obtained by adding together the current of the information held by the capacitor C12 and the current output from the current source IS12.

[0285] The lower overcurrent detection circuit 117 of this embodiment detects a current I having a waveform shown in FIG. ＩＬＩＭ ' can be obtained, and thus, like the lower overcurrent detection circuit 117 of the first embodiment, it is possible to prevent overcurrent detection from being missed.

[0286] <Lower-Side Overcurrent Detection Circuit (Third Embodiment)> The lower-side overcurrent detection circuit 117 of the first embodiment and the lower-side overcurrent detection circuit 117 of the second embodiment detect the current I when there is an offset in the N-channel MOS field-effect transistors Q4 and Q5, which are the input differential pair transistors of the first current generating circuit 2. ＩＬＩＭ The accuracy of

[0287] The lower overcurrent detection circuit 117 of the third embodiment is configured to cancel the offset of the N-channel MOS field effect transistors Q4 and Q5, which are the input differential pair transistors of the first current generating circuit 2. Therefore, the lower overcurrent detection circuit 117 of the third embodiment is configured to cancel the current I ＩＬＩＭ The accuracy of the calculation can be improved.

[0288] 40 is a diagram showing a third embodiment of the low-side overcurrent detection circuit 117. The low-side overcurrent detection circuit 117 of this embodiment is a circuit based on the low-side overcurrent detection circuit 117 of the first embodiment. In FIG. 40, the same components as those in FIG. 28 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0289] The lower overcurrent detection circuit 117 of this embodiment has an input differential section 2A, an offset sampling section 2B, a phase compensation and output drive section 2C, an output section 2D, P-channel MOS field effect transistors Q1 and Q22, a current source IS1, an N-channel MOS field effect transistor Q6, and switches SW9 to SW11.

[0290] The switches SW6, SW7, SW8, and SW11 and the switches SW9 and SW10 are turned on / off in a complementary manner.

[0291] The switches SW6, SW7, SW8, and SW11 are on when the lower transistor 102 is off. At this time, the source of the N-channel MOS field effect transistor Q4 and the source of the N-channel MOS field effect transistor Q5 are short-circuited by the switch SW8. Then, the capacitors C12 and C13 are charged so that the drain voltage of the P-channel MOS field effect transistor Q22 and the drain voltage of the P-channel MOS field effect transistor Q24 become equal.

[0292] The switches SW9 and SW10 are on when the lower transistor 102 is on. At this time, the drain currents of the N-channel MOS field effect transistors Q4 and Q5 are adjusted by the charging voltages of the capacitors C12 and C13, and as a result, the offsets of the N-channel MOS field effect transistors Q4 and Q5 are canceled.

[0293] <Others> In addition to the above-described embodiments, various modifications can be made to the configuration of the invention without departing from the spirit of the invention. The above-described embodiments are illustrative in all respects and should be considered not to be limiting. The technical scope of the present invention is defined by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0294] <Additional Note> In the above-described embodiment, the resistor R ＩＬＩＭ is an external component of the semiconductor device 100, and the resistor R ＩＬＩＭ may be built into the semiconductor device 100. In the above-described embodiment and modified example, the ripple current I ＲＩＰＰＬＥ The current generating circuit 3 that generates the current is a circuit that operates with the ground potential as a reference, but may be a circuit that operates with the power supply voltage as a reference.

[0295] The overcurrent detection circuit (117) described above is an overcurrent detection circuit configured to detect an overcurrent flowing in a circuit in which a first switch (101) and a second switch (102) are connected in series, the second switch is provided on a lower potential side than the first switch, and an inductor is connected to a connection node between the first switch and the second switch, and has a configuration (first configuration) including: a first current generation circuit (2) configured to generate a first current corresponding to the current flowing in the second switch; a second current generation circuit (3) configured to generate a second current that is greater than zero at the timing when the second switch switches from off to on and that fluctuates in synchronization with the switching of the first switch and the second switch; and a comparator (COMP1) configured to compare a voltage corresponding to the first current and the second current with a threshold value.

[0296] The overcurrent detection circuit of the first configuration can prevent overcurrent from being missed.

[0297] In the overcurrent detection circuit of the first configuration described above, the second current generation circuit may be configured to include a third switch (Q15) configured to be on when the first switch is on and off when the first switch is off, or a fourth switch configured to be off when the first switch is on and on when the first switch is off (second configuration).

[0298] The overcurrent detection circuit of the second configuration described above makes it easy to generate the second current.

[0299] In the overcurrent detection circuit of the first or second configuration, the second current generating circuit may be configured (third configuration) to include a circuit configured by a resistor (R11) and a capacitor (C11).

[0300] The overcurrent detection circuit of the third configuration can easily vary the second current by using the RC time constant.

[0301] In the overcurrent detection circuit of any of the above first to third configurations, the second current may be configured (fourth configuration) to increase over time when the second switch is off and decrease over time when the second switch is on.

[0302] The overcurrent detection circuit of the fourth configuration can make the voltages corresponding to the first current and the second current closer to ideal waveforms.

[0303] In the overcurrent detection circuit of the first configuration described above, the second current generating circuit may be configured (fifth configuration) to include a third switch (SW5) that is turned on when the first switch is on and turned off when the first switch is off, and a fourth switch (SW3) that is turned off when the first switch is on and turned on when the first switch is off.

[0304] The overcurrent detection circuit of the fifth configuration described above makes it easy to generate the second current.

[0305] In the overcurrent detection circuit of the first or fifth configuration, the second current generating circuit may be configured to retain information about the first current immediately before the second switch is turned off (sixth configuration).

[0306] The overcurrent detection circuit of the sixth configuration can set the second current to an appropriate value by using information about the first current immediately before the second switch is turned off.

[0307] In the overcurrent detection circuit of the sixth configuration, the second current may have a value corresponding to the information when the second switch is off (seventh configuration).

[0308] The overcurrent detection circuit of the seventh configuration can set the second current to an appropriate value by using information about the first current immediately before the second switch is turned off.

[0309] In the overcurrent detection circuits of the first to seventh configurations, the first current generation circuit may be configured to cancel the offset of the input differential pair transistors of the first current generation circuit (eighth configuration).

[0310] The overcurrent detection circuit of the eighth configuration can improve the accuracy of the first current.

[0311] The switching control circuit described above has a configuration (ninth configuration) including an overcurrent detection circuit of any one of the first to eighth configurations and a control unit (105) configured to control the first switch and the second switch.

[0312] The switching control circuit of the ninth configuration can suppress overcurrent detection failure.

[0313] The switching power supply device (1) described above has a configuration (tenth configuration) including the switching control circuit of the ninth configuration, the first switch, and the second switch.

[0314] The switching power supply device having the tenth configuration can suppress overcurrent detection failure.

[0315] <<Fourth Disclosed Technology>> <Switching Power Supply> Fig. 41 is a diagram showing the overall configuration of a switching power supply. The switching power supply 1 of this configuration example is a synchronous rectification step-down DC / DC converter that generates a desired output voltage VOUT (e.g., 0.6 to 5.5 V) from an input voltage VIN (e.g., 4 to 16 V), and has a semiconductor device 100 and various discrete components (e.g., capacitors C1 to C5, an inductor L1, and resistors R1 to R5) attached externally thereto.

[0316] The switching power supply device 1 can be suitably used as a step-down power supply for, for example, a SoC (system-on-a-chip), an FPGA (field-programmable gate array), or a microprocessor, or as a step-down power supply for a server or a base station.

[0317] The semiconductor device 100 is a monolithic semiconductor integrated circuit device (a so-called power supply control IC) that comprehensively controls the switching power supply device 1. The semiconductor device 100 has a plurality of external terminals (BST, AGND, ILIM, MODE, SS / REF, RGND, FB, PGD, VIN, PGND, and VCC in the figure) as means for establishing electrical connection with the outside of the device.

[0318] The BST terminal is a bootstrap terminal. A bootstrap capacitor C4 (e.g., 0.1 μF) is externally connected between the BST terminal and the SW terminal. The boost voltage VB (≈ VSW + VCC) that appears at the BST terminal serves as the gate drive voltage for the upper transistor (not shown in this figure) built into the semiconductor device 100.

[0319] The AGND terminal is a ground terminal for the control circuit (analog circuit).

[0320] The ILIM terminal is a terminal for setting an overcurrent detection value. The overcurrent detection value IOCP can be set arbitrarily using an external resistor R1 connected between the ILIM terminal and the ground terminal (=AGND terminal).

[0321] The MODE terminal is a terminal for setting the switching control mode. For example, by pulling up the MODE terminal or adjusting the external resistor R2 connected between the MODE terminal and the ground terminal (=AGND), it is possible to arbitrarily switch between combinations of switching frequency (e.g., 600 kHz, 800 kHz, and 1 MHz) and operating mode (light load mode and fixed PWM [pulse width modulation] mode).

[0322] The SS / REF terminal is a soft-start time setting terminal / internal reference voltage setting terminal. For example, the soft-start time tSS of the output voltage VOUT can be adjusted arbitrarily depending on the capacitance value of a capacitor C5 externally connected between the SS / REF terminal and the ground terminal (= RGND terminal). The soft-start function allows the output voltage VOUT to rise gradually, preventing overshoot and inrush current of the output voltage VOUT. Furthermore, the semiconductor device 100 can externally input an internal reference voltage VREF from an external power supply using the SS / REF terminal for output voltage tracking. Therefore, the internal reference voltage VREF can be set within any voltage range after startup to a predetermined target value (e.g., 0.6 V).

[0323] The RGND terminal is a remote sense ground terminal. If the remote sense function is omitted, the components connected to the RGND terminal can be connected to the AGND terminal.

[0324] The FB terminal is an output voltage feedback terminal. The FB terminal is connected to the connection node (= the application terminal of the feedback voltage VFB) between resistors R3 and R4, which are connected in series between the application terminal of the output voltage VOUT and the ground terminal (= the RGND terminal). The target value of the output voltage VOUT can be set as {(R3 + R4) / R4} × VREF.

[0325] The EN terminal is an enable terminal. For example, when the enable voltage VEN applied to the EN terminal becomes equal to or greater than an upper threshold (e.g., 1.22 V), the semiconductor device 100 starts up, and when the enable voltage VEN becomes equal to or less than a lower threshold (e.g., 1.02 V), the semiconductor device 100 shuts down. The EN terminal must be terminated. It is also desirable that the enable voltage VEN start up simultaneously with or after the input voltage VIN is turned on (VIN=VEN).

[0326] The PGD terminal is a power good terminal. Because the PGD terminal is an open-drain output, it requires a pull-up resistor R5. If the PGD terminal is not used, it can be left floating or connected to ground.

[0327] The VIN terminal is the power supply input terminal. An input smoothing capacitor C1 (e.g., a ceramic capacitor of about 0.1 μF) is externally connected between the VIN terminal and the ground terminal (= PGND terminal). Capacitor C1 is effective in reducing input ripple noise, and this effect is best achieved by placing it as close as possible to the VIN terminal and PGND terminal.

[0328] The SW terminal is a switching output terminal. The SW terminal is connected to the source of the upper transistor and the drain of the lower transistor (neither of which are shown in this figure) built into the semiconductor device 100, and outputs a rectangular-wave switching voltage VSW. An inductor L1 is externally connected between the SW terminal and the application terminal of the output voltage VOUT. A capacitor C3 (e.g., a ceramic capacitor) is externally connected between the application terminal of the output voltage VOUT and the RGND terminal. As such, the switching power supply device 1 requires an LC filter for output smoothing in order to supply a continuous current to the load.

[0329] The PGND terminal is the ground terminal of the switching output stage (=power circuit).

[0330] The VCC terminal is an internal power supply output terminal. The internal power supply voltage VCC (e.g., 3 V) output from the VCC terminal is supplied to, for example, a control circuit (=analog circuit) of the semiconductor device 100. Note that a capacitor C2 (e.g., a ceramic capacitor of about 1 μF) is externally connected between the VCC terminal and the ground terminal (=AGND terminal).

[0331] 42 is a diagram showing the internal configuration of a semiconductor device 100. The semiconductor device 100 of this configuration example includes an upper transistor 101, a lower transistor 102, an upper driver 103, a lower driver 104, a control logic 105, an internal power supply voltage generating circuit 106, an internal reference voltage generating circuit 107, an error amplifier 108, a capacitor 109A, a lower clamp circuit 109B, an upper clamp circuit 109C, a resistor 109D, a ramp voltage generating circuit 110, a voltage superimposing circuit 111, and a main comparator 112. The power supply circuit includes a power supply 112, an ON time setting circuit 113, a P-channel MOS field effect transistor 114, an N-channel MOS field effect transistor 115, comparators 116, 117, and 118, an under input voltage malfunction prevention circuit 119, a temperature protection circuit 120, a low voltage protection circuit 121, an over voltage protection circuit 122, a power good circuit 123, an N-channel MOS field effect transistor 124, and a mode selector 125.

[0332] The drain of the upper transistor 101 (for example, an N-channel MOS field effect transistor) is connected to the VIN terminal. The source of the upper transistor 101 is connected to the SW terminal. The gate of the upper transistor 101 is connected to the application terminal of the upper gate signal G1 (= the output terminal of the upper driver 103). The upper transistor 101 is turned on when the upper gate signal G1 is at a high level (≒ VB) and turned off when the upper gate signal G1 is at a low level (≒ VSW).

[0333] The drain of the lower transistor 102 (e.g., an N-channel MOS field effect transistor) is connected to the SW terminal. The source of the lower transistor 102 is connected to the PGND terminal. The gate of the lower transistor 102 is connected to the application terminal of the lower gate signal G2 (= the output terminal of the lower driver 104). The lower transistor 102 is turned on when the lower gate signal G2 is at a high level (≈ VCC) and turned off when the lower gate signal G2 is at a low level (≈ PGND).

[0334] The upper transistor 101 and the lower transistor 102 connected in this manner form a step-down switching output stage that employs synchronous rectification, together with discrete components (inductor L1 and capacitor C3) externally attached to the semiconductor device 100. However, the rectification method is not necessarily limited to synchronous rectification, and a rectifying diode may be used instead of the lower transistor 102.

[0335] If a large current output (for example, a maximum output of 20 A) is required for the switching power supply device 1, it is desirable to use elements with low on-resistance as the upper transistor 101 and the lower transistor 102.

[0336] Furthermore, the upper transistor 101 and the lower transistor 102 do not necessarily need to be built into the semiconductor device 100, but may be attached externally to the semiconductor device 100 as discrete components.

[0337] The high-side driver 103 operates by receiving the boot voltage VB and the switch voltage VSW, and generates the high-side gate signal G1 based on the high-side control signal S1 output from the control logic 105. For example, the high-side driver 103 sets the high-side gate signal G1 to a high level (≒VB) when the high-side control signal S1 is at a high level, and sets the high-side gate signal G1 to a low level (≒VSW) when the high-side control signal S1 is at a low level.

[0338] The low-side driver 104 operates by receiving the internal power supply voltage VCC and the ground voltage PGND, and generates the low-side gate signal G2 based on the low-side control signal S2 output from the control logic 105. For example, the low-side driver 104 sets the low-side gate signal G2 to a high level (≈ VCC) when the low-side control signal S2 is at a high level, and sets the low-side gate signal G2 to a low level (≈ PGND) when the low-side control signal S2 is at a low level.

[0339] When an enable signal (=enable voltage VEN) input to an EN terminal is at a high level, the control logic 105 complementarily turns on / off the upper transistor 101 and the lower transistor N2 using a fixed on-time control method.

[0340] More specifically, the control logic 105 sets the upper control signal S1 to a high level and the lower control signal S2 to a low level when turning on the upper transistor 101 and turning off the lower transistor N2. Also, the control logic 105 sets the upper control signal S1 to a low level and the lower control signal S2 to a high level when turning off the upper transistor 101 and turning on the lower transistor 102.

[0341] In this way, when the upper transistor 101 and the lower transistor 102 that form the switching output stage are complementarily turned on / off, a switch voltage VSW having a rectangular waveform (high level: VB, low level: PGND) is generated at the SW terminal. The switching power supply device 1 can generate the desired output voltage VOUT by rectifying and smoothing this switch voltage VSW with an LC filter (= inductor L1 and capacitor C3).

[0342] The control logic 105 also has a function of preventing the upper transistor 101 and the lower transistor 102 from being turned on simultaneously to prevent excessive through current. Furthermore, the control logic 105 also has a function of forcibly stopping the on / off driving of the upper transistor 101 and the lower transistor 102 based on various protection signals (HOCP, LOCP, ZX / ROCP, UVLO, TSD, SCP, and OVP). For example, when an abnormality is detected, the control logic 105 sets both the upper control signal S1 and the lower control signal S2 to a low level, thereby turning off both the upper transistor 101 and the lower transistor 102.

[0343] The internal power supply voltage generating circuit 106 generates an internal power supply voltage VCC (for example, 3 V) and outputs it to the VCC terminal and each part of the semiconductor device 100 .

[0344] When an enable signal (=enable voltage VEN) input to an EN terminal is at a high level, the internal reference voltage generating circuit 107 generates a predetermined internal reference voltage VREF from the internal power supply voltage VCC and outputs it to an SS / REF terminal.

[0345] The error amplifier 108 operates using the RGND terminal as a reference potential and generates an error signal Sa corresponding to the difference between the internal reference voltage VREF input to the non-inverting input terminal (+) and the feedback voltage VFB input to the inverting input terminal (-). Therefore, the error signal Sa increases when VREF>VFB and decreases when VREF<VFB.

[0346] Capacitor 109A is provided between the output terminal of error amplifier 108 and the ground terminal (=RGND terminal). Capacitor 109A is an example of a phase compensation circuit and prevents oscillation of error amplifier 108. Lower clamp circuit 109B clamps error signal Sa so that it does not fall below a first predetermined value. Upper clamp circuit 109C clamps error signal Sa so that it does not exceed a second predetermined value (>first predetermined value). Resistor 109D is provided between signal line LN1, which transmits error signal Sa, and upper clamp circuit 109C.

[0347] The ramp voltage generating circuit 110 generates a ramp voltage VR having a sawtooth or triangular waveform.

[0348] The voltage superimposing circuit 111 superimposes the ramp voltage VR on the feedback voltage VFB to generate a slope signal Sb.

[0349] The main comparator 112 compares the error signal Sa input to the non-inverting input terminal (+) with the slope signal Sb input to the inverting input terminal (-) to generate a comparison signal Sc and output it to the on-time setting circuit 113. The comparison signal Sc goes high when Sa > Sb and goes low when Sa < Sb. In other words, the main comparator 112 raises the comparison signal Sc to high level to feed back to the on-time setting circuit 113 that the output voltage VOUT has dropped below the target value.

[0350] The ON time setting circuit 113 sets a predetermined ON time Ton when the comparison signal Sc rises to a high level. The control logic 105 keeps the upper transistor 101 on and the lower transistor N2 off until the ON time Ton has elapsed.

[0351] In this way, of the above components, the error amplifier 108, the main comparator 112, and the on-time setting circuit 113 form an output feedback control circuit that controls the drive of the switching output stage using a fixed on-time control method so that the feedback voltage VFB matches the internal reference voltage VREF.

[0352] However, the output feedback control method is not necessarily limited to the fixed on-time control method, and a voltage mode control method, a current mode control method, a hysteresis control method (ripple control method), or the like may also be adopted.

[0353] The drain of the transistor 114 is connected to the VCC terminal (= the terminal to which the internal power supply voltage VCC is applied), and the source of the transistor 114 is connected to the BST terminal (= the terminal to which the boot voltage VB is applied). The transistor 114 connected in this manner forms a bootstrap circuit together with a capacitor C4 externally connected between the BST terminal and the SW terminal.

[0354] The transistor 114 is turned on when the control signal S3 (= a binary signal having essentially the same logical level as the control signal S1) input to the gate from the control logic 105 is at a low level, and is turned off when the control signal S3 is at a high level.

[0355] The above bootstrap circuit generates a boot voltage VB (≈VSW+VCC) that is always higher than the switch voltage VSW by the voltage across the capacitor C4 (≈VCC). That is, the boot voltage VB is VB≈VIN+VCC during the high-level period of the switch voltage VSW (VSW≈VIN), and VB≈VCC during the low-level period of the switch voltage VSW (VSW≈PGND).

[0356] The boot voltage VB thus generated is supplied to the upper driver 103 and is used as the high level of the upper gate signal G1 (=gate voltage for turning on the upper transistor 101). Therefore, during the on-period of the upper transistor 101, the high level (≈VB) of the upper gate signal G1 is raised to a voltage value (≈VIN+VCC) higher than the high level (≈VIN) of the switch voltage VSW, thereby increasing the gate-source voltage of the upper transistor 101 and enabling the upper transistor 101 to be reliably turned on.

[0357] As a component of the bootstrap circuit, a diode with an anode connected to the VCC terminal and a cathode connected to the BST terminal may be used instead of the transistor 114. In this case, the boot voltage VB is VB≈VSW+VCC-Vf (where Vf is the forward voltage drop of the diode).

[0358] The drain of the transistor 115 is connected to the SW terminal (= the application terminal of the switch voltage VSW). The source of the transistor 115 is connected to the PGND terminal (= the ground terminal of the power circuit). The transistor 114 is turned on when the control signal S4 input to the gate from the control logic 105 is at a high level, and turned off when the control signal S4 is at a low level.

[0359] The transistor 115 connected in this manner functions as a resistive load (e.g., 80Ω) for discharging the output smoothing capacitor C3 when the semiconductor device 100 is shut down from an operating state by enable control. That is, the transistor 115 may be turned on when both the upper transistor 101 and the lower transistor 102 are turned off by shutting down the semiconductor device 100. The output voltage VOUT may be discharged to, for example, 10% of the target value.

[0360] The comparator 116 monitors the voltage (=VIN-VSW) across the upper transistor 101 for each cycle of the switching period and generates the upper overcurrent detection signal HOCP. When the current flowing through the upper transistor 101 while the upper transistor 101 is on reaches the overcurrent detection value IOCPH, the upper overcurrent detection signal HOCP goes high. At this time, the control logic 105 turns off the upper transistor 101 and turns on the lower transistor 102.

[0361] The comparator 117 monitors the voltage (=VSW) across the lower-side transistor 102 every cycle of the switching period and generates a lower-side overcurrent detection signal LOCP. When the current flowing through the lower-side transistor 102 reaches an overcurrent detection value IOCPL while the lower-side transistor 102 is on, the lower-side overcurrent detection signal LOCP goes high. At this time, the control logic 105 turns off the upper-side transistor 101 and keeps the lower-side transistor 102 on, even if the feedback voltage FB falls below the internal reference voltage VREF. Thereafter, when the current flowing through the lower-side transistor 102 falls below the upper limit, the upper-side transistor 101 can be turned on.

[0362] The comparator 118 monitors the voltage (=VSW) across the lower-side transistor 102 for each cycle of the switching period and generates a zero-cross / sink (reverse) overcurrent detection signal ZX / ROCP. For example, in the light-load mode, the control logic 105 detects the zero-cross timing of the current flowing through the lower-side transistor 102 when the lower-side transistor 102 is on, and turns off the lower-side transistor 102. In the fixed PWM mode, the control logic 105 detects that the sink current (reverse current) flowing from the SW terminal toward the lower-side transistor 102 when the lower-side transistor 102 is on has reached an upper limit, and turns off the lower-side transistor 102 and turns on the upper-side transistor 101.

[0363] The under voltage lockout (UVLO) circuit 119 monitors the input voltage VIN and the internal power supply voltage VCC to provide UVLO (under voltage lock out) protection. For example, if the input voltage VIN falls below 1.85 V or the internal power supply voltage VCC falls below 2.5 V, the semiconductor device 100 shuts down. On the other hand, if the input voltage VIN rises above 2.4 V and the internal power supply voltage VCC rises above 2.8 V, the semiconductor device 100 starts up.

[0364] The temperature protection circuit 120 monitors the junction temperature Tj of the semiconductor device 100 and applies temperature protection. For example, when the junction temperature Tj reaches 175° C. or higher, the semiconductor device 100 shuts down. Thereafter, when the junction temperature Tj falls to 150° C. or lower (hysteresis 25° C.), the semiconductor device 100 automatically restarts.

[0365] The low-voltage protection circuit 121 monitors the feedback voltage VFB and applies low-voltage protection. For example, after the semiconductor device 100 is started, if the feedback voltage VFB falls to 80% or less of the internal reference voltage VREF, the semiconductor device 100 shuts down. Note that, after 117 ms has elapsed since the shutdown, the semiconductor device 100 automatically restarts.

[0366] The overvoltage protection circuit 122 monitors the feedback voltage VFB and applies overvoltage protection. For example, when the feedback voltage VFB becomes 116% or more of the internal reference voltage VREF, the lower transistor 102 turns on, suppressing the increase in the output voltage VOUT. Thereafter, when the feedback voltage VFB becomes 105% or less of the internal reference voltage VREF, the normal operating state is restored.

[0367] The power-good circuit 123 monitors the feedback voltage VFB and performs on / off control of the transistor 124 (and consequently, output control of the power-good signal PGD). For example, when the output voltage VOUT reaches 92.5% to 105% of the target value and this state continues for 0.9 ms, the transistor 124 is turned off. On the other hand, when the output voltage VOUT falls to 116% or more or 80% or less of the target value, the transistor 124 is turned on.

[0368] The drain of the transistor 124 is connected to the PGD terminal. The source of the transistor 124 is connected to the ground terminal (=AGND terminal). As described above, the transistor 124 is turned on / off by the power good circuit 123. When the transistor 124 is off, the PGD terminal is in a high impedance state. On the other hand, when the transistor 124 is on, the PGD terminal is pulled down to the ground terminal. By providing such a power good function, sequence control of the entire system becomes possible.

[0369] The mode selector 125 sets the switching frequency FREQ and the operating mode MODE according to the state of the MODE terminal. When the light load mode is selected as the operating mode, switching is performed using PWM mode control in heavy load conditions, and switching is performed using LLM (light load mode) mode control in light load conditions to improve efficiency. On the other hand, when the fixed PWM mode is selected as the operating mode, switching is performed using PWM mode control forcibly regardless of the load weight. In the light load mode, efficiency is improved in the light load range, making it suitable for devices that require reduced standby power consumption.

[0370] <Oscillation Prevention Circuit> The oscillation prevention circuit has the above-mentioned signal line LN1, capacitor 109A, upper clamp circuit 109C, and resistor 109D. The oscillation prevention circuit, together with error amplifier 108, main comparator 112, on-time setting circuit 113, and control logic 105, constitutes a switching control circuit that controls the upper transistor 101 and the lower transistor 102. Figure 43 is a diagram showing an example configuration of the error amplifier 108, lower clamp circuit 109B, and upper clamp circuit 109C.

[0371] The error amplifier 108 has a DC voltage source 1081 and an error amplifier 1082. The DC voltage source 1081 is connected to the non-inverting input terminal (+) of the error amplifier 1082, and supplies a voltage obtained by adding a first offset voltage to the internal reference voltage VREF to the non-inverting input terminal (+) of the error amplifier 1082.

[0372] The lower clamp circuit 109B includes a DC voltage source 1091, a DC voltage source 1092, a differential amplifier 1093, and an NMOS field-effect transistor 1094 functioning as a switch. The DC voltage source 1091 supplies a voltage obtained by adding a second offset voltage to the internal reference voltage VREF to the DC voltage source 1092. The DC voltage source 1092 supplies a voltage obtained by adding a voltage corresponding to the first predetermined value to the sum of the internal reference voltage VREF and the second offset voltage to the non-inverting input terminal (+) of the differential amplifier 1093. The inverting input terminal (-) of the differential amplifier 1093 is connected to the signal line LN1.

[0373] When the error signal Sa falls to the first predetermined value, the differential amplifier 1093 turns on the NMOS field-effect transistor 1094. When the NMOS field-effect transistor 1094 turns on, the capacitor 109A is charged, suppressing the fall of the error signal Sa. Therefore, the lower clamp circuit 109B clamps the error signal Sa so that it does not fall below the first predetermined value.

[0374] Because the output impedance of the differential amplifier 1093 is high and the output impedance of the NMOS field-effect transistor 1094 is low, the lower clamp circuit 109B has only one pole (see FIG. 44). As a result, the phase of the lower clamp circuit 109B lags only by 90° (see FIG. 44). Therefore, the lower clamp circuit 109B does not oscillate.

[0375] The upper clamp circuit 109C includes a DC voltage source 1095, a DC voltage source 1096, a differential amplifier 1097, and an NMOS field-effect transistor 1098 functioning as a switch. The DC voltage source 1095 supplies a voltage obtained by adding a third offset voltage to the internal reference voltage VREF to the DC voltage source 1096. The DC voltage source 1096 supplies a voltage obtained by adding a voltage corresponding to the second predetermined value to the sum of the internal reference voltage VREF and the third offset voltage to the inverting input terminal (−) of the differential amplifier 1097. The non-inverting input terminal (+) of the differential amplifier 1097 is connected to a first terminal of a resistor 109D. The second terminal of the resistor 109D is connected to the signal line LN1.

[0376] When the error signal Sa rises to the second predetermined value, the differential amplifier 1097 turns on the NMOS field-effect transistor 1098. When the NMOS field-effect transistor 1098 turns on, the capacitor 109A is discharged, suppressing the rise of the error signal Sa. Therefore, the upper clamp circuit 109C clamps the error signal Sa so that it does not exceed the second predetermined value.

[0377] Because the output impedance of both the differential amplifier 1097 and the NMOS field-effect transistor 1094 is high, the upper clamp circuit 109C has two poles (see FIG. 45). As a result, the phase of the upper clamp circuit 109C lags by 180° (see FIG. 45). Therefore, the upper clamp circuit 109C oscillates.

[0378] However, the upper clamp circuit 109C, capacitor 109A, and resistor 109D have two poles and one zero point (see FIG. 46). Because the zero point causes the phase to move back by 90°, the upper clamp circuit 109C, capacitor 109A, and resistor 109D only delay the phase by 90°. Therefore, the oscillation prevention circuit of this embodiment can prevent oscillation of the upper clamp circuit 109C. In other words, generating a zero point using capacitor 109A and resistor 109D prevents oscillation of the upper clamp circuit 109C.

[0379] The capacitor 109A is a phase compensation circuit for preventing oscillation of the error amplifier 108, and is also used to prevent oscillation of the upper clamp circuit 109C. In other words, the capacitor 109A has two functions, which helps prevent an increase in the number of parts.

[0380] Fig. 47 is a diagram showing an example of the configuration of the differential amplifier 1097. The differential amplifier 1097 of the example configuration shown in Fig. 47 has a current source IS1, P-channel MOS field effect transistors Q1 and Q2 which are an input differential pair, and N-channel MOS field effect transistors Q3 and Q4 which form a current mirror circuit.

[0381] A first terminal of the current source IS1 is connected to a power supply voltage application terminal. A second terminal of the current source IS1 is connected to the sources of the P-channel MOS field effect transistors Q1 and Q2. The drains of the P-channel MOS field effect transistors Q1 and Q2 are connected to the drains and gates of the N-channel MOS field effect transistors Q3 and Q4. The sources of the N-channel MOS field effect transistors Q3 and Q4 are connected to the ground potential.

[0382] <Others> In addition to the above-described embodiments, various modifications can be made to the configuration of the invention without departing from the spirit of the invention. The above-described embodiments are illustrative in all respects and should be considered not to be limiting. The technical scope of the present invention is defined by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0383] In this embodiment, the oscillation prevention circuit is provided after the error amplifier, but the location of the oscillation prevention circuit is not limited to the after the error amplifier. The oscillation prevention circuit may also be mounted in devices other than switching power supplies.

[0384] <Additional Notes> The oscillation prevention circuit described above has a signal line (LN1), a first circuit (109C), a capacitor (109A) connected to the signal line, and a resistor (109D) provided between the signal line and the first circuit, wherein the first circuit has two poles, and the first circuit, the capacitor, and the resistor each have two poles and one zero point (first configuration).

[0385] The oscillation prevention circuit of the first configuration can prevent oscillation of the first circuit having two poles.

[0386] In the oscillation prevention circuit of the first configuration described above, the first circuit may be configured (second configuration) to be a clamp circuit configured to clamp the voltage applied to the signal line so that the voltage applied to the signal line does not exceed a predetermined value.

[0387] The oscillation prevention circuit of the second configuration can prevent the voltage applied to the signal line from exceeding a predetermined value.

[0388] In the oscillation prevention circuit of the second configuration described above, the clamp circuit may have a differential amplifier (1097) configured to output a voltage corresponding to the difference between the voltage applied to the signal line and the predetermined voltage value, and a switch (1098) configured to be controlled by the output voltage of the differential amplifier, and the capacitor may be configured to be discharged when the switch is on (third configuration).

[0389] The oscillation prevention circuit of the third configuration can prevent the voltage applied to the signal line from exceeding a predetermined value with a simple circuit configuration.

[0390] In the oscillation prevention circuit of the third configuration, the switch may be an N-channel MOS field effect transistor (fourth configuration).

[0391] The oscillation prevention circuit of the fourth configuration allows the switch to be made smaller.

[0392] In the oscillation prevention circuit of any one of the first to fourth configurations, the signal line may be connected to the output terminal of the second circuit (fifth configuration).

[0393] The oscillation prevention circuit of the fifth configuration can be provided in the subsequent stage of the second circuit.

[0394] In the oscillation prevention circuit of the fifth configuration, the second circuit may be an error amplifier (108) (sixth configuration).

[0395] The oscillation prevention circuit of the sixth configuration can use a capacitor to prevent oscillation of the error amplifier.

[0396] The switching control circuit described above has a configuration (seventh configuration) that includes the oscillation prevention circuit of the sixth configuration, the error amplifier, and a control unit (112, 113, 105) that is configured to control the switching element based on the output voltage of the error amplifier.

[0397] The switching control circuit of the seventh configuration can prevent oscillation of the first circuit having two poles.

[0398] The switching power supply device described above has a configuration (eighth configuration) including the switching control circuit of the seventh configuration and the switching elements (101, 102).

[0399] The switching power supply device having the eighth configuration can prevent oscillation of the first circuit having two poles.

[0400] The present disclosure can be used, for example, in a semiconductor device having a DC / DC converter function.

[0401] REFERENCE SIGNS LIST 1 semiconductor device 2 gate drive circuit 3 control logic unit 4 switch 21 high-side pre-driver 22 low-side pre-driver 23 high-side gate voltage monitor unit 23A resistor 23B, 23C switch 23D, 23E inverter 211 first high-side drive unit 211A, 211B inverter 212 second high-side drive unit 221 first low-side drive unit 221A, 221B inverter 221C inverter 221D AND circuit 222 second low-side drive unit 2111 first high-side gate signal generation unit 2112 second high-side gate signal generation unit 2211 first low-side gate signal generation unit 2212 second low-side gate signal generation unit Cbst boot capacitor Cout output capacitor HM high-side transistor HNM1 first high-side NMOS transistor HNM2 Second high-side NMOS transistor HPM1 First high-side PMOS transistor HPM2 Second high-side PMOS transistor L Inductor LM Low-side transistor LNM1 First low-side NMOS transistor LNM2 Second low-side NMOS transistor LPM1 First low-side PMOS transistor LPM2 Second low-side PMOS transistor

Claims

1. A gate drive circuit for driving a half bridge in which a driven high-side transistor and a driven low-side transistor are connected in series between a power supply voltage and a ground potential, a high-side pre-driver configured to drive a gate of the high-side transistor to be driven; a low-side pre-driver configured to drive a gate of the driven low-side transistor; Equipped with the high-side pre-driver includes a first high-side transistor and a second high-side transistor; the low-side pre-driver includes a third high-side transistor and a fourth high-side transistor; between a first gate signal that turns on the first high-side transistor and a second gate signal that turns on the second high-side transistor; A gate drive circuit, wherein a delay is provided between at least one of a third gate signal that turns on the third high side transistor and a fourth gate signal that turns on the fourth high side transistor.

2. 2. The gate drive circuit of claim 1, wherein the high side pre-driver comprises a high side drive portion configured to generate the first and second gate signals based on a high side control input signal.

3. The high side drive unit is a first high side gate signal generating unit having a plurality of first inverters and configured to generate the first gate signal; a second high side gate signal generating unit having a plurality of second inverters and configured to generate the second gate signal; having 3. The gate drive circuit according to claim 2, wherein at least one of the second inverters in the second high side gate signal generation unit has a transistor size smaller than that of at least one of the first inverters in the first high side gate signal generation unit.

4. 4. The gate drive circuit according to claim 3, wherein the second inverter in the first stage of the second high side gate signal generation unit has a transistor size smaller than that of the first inverter in the first high side gate signal generation unit.

5. 2. The gate drive circuit of claim 1, wherein the low side pre-driver comprises a low side drive portion configured to generate the third gate signal and the fourth gate signal based on a low side control input signal.

6. The low side drive unit is a first low-side gate signal generating unit having a plurality of third inverters and configured to generate the third gate signal; a second low-side gate signal generating unit having a plurality of fourth inverters and configured to generate the fourth gate signal; having 6. The gate drive circuit according to claim 5, wherein at least any of the fourth inverters in the second low side gate signal generation unit has a transistor size smaller than that of at least any of the third inverters in the first low side gate signal generation unit.

7. 7. The gate drive circuit according to claim 6, wherein the fourth inverter in the first stage of the second low side gate signal generation unit has a transistor size smaller than that of the third inverter in the first stage of the first low side gate signal generation unit.

8. a monitor unit for monitoring whether a gate voltage of the driven high-side transistor is at a low level and a voltage of a node to which the driven high-side transistor and the driven low-side transistor are connected is at a low level; 2. The gate drive circuit according to claim 1, wherein the fourth gate signal is generated based on a monitor signal output from the monitor section.

9. The monitor unit includes: a resistor having a first end connected to the gate of the driven transistor; an inverter stage having an input connected to the second end of the resistor; 9. The gate drive circuit of claim 8, comprising:

10. a first output transistor having a first end connected to a power good terminal and a second end connected to an application end of a ground potential; a resistor for applying a voltage based on a first power supply voltage to a control end of the first output transistor; a first inverter stage configured to use the second power supply voltage as a power supply voltage and to be able to receive a control input signal; a second output transistor having a control terminal connected to the output terminal of the first inverter stage, a first terminal connected to the power good terminal, and a second terminal connected to an application terminal of a ground potential; Equipped with The power-good terminal is capable of being pulled up to the second power supply voltage.

11. the resistor is a voltage dividing resistor connected in series between an application terminal of the first power supply voltage and an application terminal of a ground potential, The power-good circuit according to claim 10 , wherein a connection node of the voltage dividing resistors is connected to a control end of the first output transistor.

12. the first output transistor and the second output transistor are the same transistor, a first diode for blocking a path from the connection node through the voltage dividing resistor to an application terminal of the first power supply voltage; 12. The power-good circuit according to claim 11, further comprising: a second diode for blocking a path from the connection node through the first inverter stage to an application terminal of the second power supply voltage.

13. 11. The power-good circuit according to claim 10, wherein the resistor is a first pull-up resistor connected between an application terminal of the first power supply voltage and a control terminal of the first output transistor.

14. 14. The power good circuit of claim 13, wherein the first output transistor and the second output transistor are separate transistors.

15. 15. The power-good circuit according to claim 14, further comprising a second pull-up resistor connected between a control terminal of the second output transistor and an application terminal of the second power supply voltage.

16. a level shift circuit configured to level-shift the control input signal from the second power supply voltage to the first power supply voltage; a second inverter stage provided between an output terminal of the level shift circuit and a control terminal of the first output transistor, the second inverter stage using the first power supply voltage as a power supply voltage; 16. The power-good circuit of claim 14 or 15, comprising:

17. 16. The power-good circuit according to claim 14, further comprising a control transistor having a first terminal connected to a control terminal of the first output transistor, a second terminal connected to an application terminal of a ground potential, and a control terminal connected to an application terminal of the second power supply voltage.

18. A power good circuit according to claim 10; a pre-regulator configured to receive an enable signal and generate the first power supply voltage; a reference voltage generating unit configured to generate a reference voltage based on the first power supply voltage; a regulator activated based on the reference voltage and configured to generate the second power supply voltage; A semiconductor device comprising:

19. An overcurrent detection circuit configured to detect an overcurrent flowing through a circuit in which a first switch and a second switch are connected in series, the second switch is provided on a lower potential side than the first switch, and an inductor is connected to a connection node between the first switch and the second switch, a first current generating circuit configured to generate a first current corresponding to a current flowing through the second switch; a second current generating circuit configured to generate a second current that is greater than zero when the second switch is switched from off to on and that varies in synchronization with switching of the first switch and the second switch; a comparator configured to compare a voltage responsive to the first current and the second current with a threshold; An overcurrent detection circuit comprising:

20. 20. The overcurrent detection circuit of claim 19, wherein the second current generating circuit includes a third switch configured to be on when the first switch is on and off when the first switch is off, or a fourth switch configured to be off when the first switch is on and on when the first switch is off.

21. The overcurrent detection circuit according to claim 19 , wherein the second current generating circuit includes a circuit formed by a resistor and a capacitor.

22. 20. The overcurrent detection circuit of claim 19, wherein the second current increases over time when the second switch is off and decreases over time when the second switch is on.

23. 20. The overcurrent detection circuit of claim 19, wherein the second current generating circuit includes: a third switch that is on when the first switch is on and off when the first switch is off; and a fourth switch that is off when the first switch is on and on when the first switch is off.

24. 20. The overcurrent detection circuit of claim 19, wherein the second current generating circuit is configured to hold information of the first current immediately before the second switch is turned off.

25. 25. The overcurrent detection circuit according to claim 24, wherein the second current has a value according to the information when the second switch is off.

26. 20. The over-current detection circuit of claim 19, wherein the first current generating circuit is configured to cancel an offset of an input differential pair transistor of the first current generating circuit.

27. An overcurrent detection circuit according to any one of claims 19 to 26; A controller configured to control the first switch and the second switch; A switching control circuit having a

28. A switching control circuit according to claim 27; the first switch and the second switch; A switching power supply device comprising:

29. A signal line; A first circuit; a capacitor connected to the signal line; a resistor provided between the signal line and the first circuit; having The first circuit has two poles; The first circuit, the capacitor, and the resistor have two poles and one zero.

30. 30. The oscillation prevention circuit of claim 29, wherein the first circuit is a clamp circuit configured to clamp a voltage applied to the signal line so that the voltage applied to the signal line does not exceed a predetermined value.

31. The clamp circuit includes: a differential amplifier configured to output a voltage corresponding to a difference between a voltage applied to the signal line and the predetermined voltage; a switch configured to be controlled by an output voltage of the differential amplifier; having 31. The oscillation prevention circuit of claim 30, wherein the capacitor is discharged when the switch is on.

32. 32. The oscillation prevention circuit according to claim 31, wherein the switch is an N-channel MOS field effect transistor.

33. 33. The oscillation prevention circuit according to claim 29, wherein the signal line is connected to an output terminal of a second circuit.

34. 34. The oscillation prevention circuit of claim 33, wherein the second circuit is an error amplifier.

35. An oscillation prevention circuit according to claim 34; The error amplifier; a control unit configured to control a switching element based on an output voltage of the error amplifier; A switching control circuit having a

36. A switching control circuit according to claim 35; The switching element; A switching power supply device comprising: