Switching regulator

Abstract

A switching regulator according to the present invention comprises: a comparator that compares a switching voltage corresponding to an inductor current flowing from the switching regulator to an inductor with a prescribed reference voltage, and outputs a comparison result signal; a monitoring circuit that generates a current for generating a monitoring voltage that monitors the switching voltage; a reference voltage circuit that generates a current for generating the reference voltage; and a control circuit that outputs a plurality of selection signals indicating a plurality of mutually different timings to at least one of the monitoring circuit and the reference voltage circuit. At least one of the monitoring circuit and the reference voltage circuit changes the generated current according to the plurality of timings, and at least one of the monitoring circuit and the reference voltage circuit is shared for the plurality of timings.

Description

Switching Regulator

[0001] The present invention relates to a switching regulator.

[0002] It is already known that in conventional switching regulators, miniaturization of integrated circuits (ICs) is required to reduce the mounting area.

[0003] For example, Patent Document 1 discloses a conventional switching regulator that operates with low power consumption and occupies a small area in a semiconductor device, and is characterized by including a comparator circuit, multiple switch circuits, and a switch control circuit, and by switching the multiple switch circuits using multiple control signals from the switch control circuit, thereby realizing multiple abnormality detection functions with a single comparator circuit.

[0004] That is, in order to reduce the chip area, Patent Document 1 discloses a technology in which, for example, the reference voltage and monitoring voltage of multiple detection circuits with different operation timings are switched and one comparator circuit is used for both purposes.

[0005] Patent No. 6656956

[0006] However, conventional analog switching regulators require a circuit to correct manufacturing variations in electrical characteristics and relative accuracy in order to maintain high and stable quality, making it difficult to reduce the circuit area. In particular, the invention described in Patent Document 1 does not solve the problem of requiring a circuit to correct manufacturing variations for each application.

[0007] SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide a switching regulator that can reduce the circuit area compared to the prior art while maintaining high and stable quality.

[0008] A switching regulator according to one aspect of the present invention is a switching regulator having a pair of switch elements connected in series with each other, and is further equipped with: a comparator that compares a switching voltage corresponding to an inductor current flowing from the switching regulator to an inductor with a predetermined reference voltage and outputs a comparison result signal; a monitoring circuit that generates a current for generating a monitoring voltage for monitoring the switching voltage; a reference voltage circuit that generates a current for generating the reference voltage; and a control circuit that outputs a plurality of selection signals indicating a plurality of different timings to at least one of the monitoring circuit and the reference voltage circuit, wherein at least one of the monitoring circuit and the reference voltage circuit changes the current it generates in accordance with the plurality of timings, and at least one of the monitoring circuit and the reference voltage circuit is shared for the plurality of timings.

[0009] Therefore, according to the switching regulator according to one aspect of the present invention, the circuit area can be reduced compared to the prior art while maintaining high and stable quality in the switching regulator.

[0010] 1. A block diagram showing the configuration of a switching regulator 1 according to a basic circuit. 2. A block diagram showing the configuration of a zero-cross detector 11 of FIG. 1. 3. A timing chart of each signal showing an example of operation of the switching regulator 1 of FIG. 1. 4. A block diagram showing the configuration of a current monitor circuit 11A according to Modification 1. 5. A timing chart of each signal showing an example of operation of a switching regulator including the current monitor circuit 11A of FIG. 4. 6. A block diagram showing the configuration of a current monitor circuit 11B according to Modification 2. 7. A timing chart of each signal showing an example of operation of a switching regulator including the current monitor circuit 11B of FIG. 6. 8. A block diagram showing the configuration of a current monitor circuit 11C according to Modification 3. 9. A timing chart of each signal showing an example of operation of a switching regulator including the current monitor circuit 11C of FIG. 8. 10. A block diagram showing the configuration of a current monitor circuit 11D according to Modification 4. 11D. A timing chart of each signal showing an example of operation of a switching regulator including the current monitor circuit 11D of FIG. 10. 11E. A block diagram showing the configuration of a current monitor circuit 11E according to a comparative example. 12. A block diagram showing the configuration of a portion of the current monitor circuit 11E of FIG. 12. 13. A timing chart of each signal showing an example of operation of a switching regulator including the current monitor circuit 11E of FIG. 13. 14. A block diagram showing the configuration of a portion of the current monitor circuit 11E of FIG. 12. 16 is a timing chart of each signal showing an example of operation of a switching regulator including the current monitor circuit 11E of FIG. 15. FIG. 17 is a block diagram showing an example of a configuration of a switching regulator including a current monitor circuit 11F according to embodiment 1. FIG. 18 is a block diagram showing an example of a configuration of a switching regulator including a current monitor circuit 11G according to embodiment 2. FIG. 19 is a block diagram showing an example of a configuration of a switching regulator including a current monitor circuit 11H according to embodiment 3. FIG. 20 is a block diagram showing an example of a configuration of a switching regulator including a current monitor circuit 11I according to embodiment 4. FIG. 21 is a block diagram showing an example of a configuration of a switching regulator including a current monitor circuit 11J according to embodiment 5. FIG. 22 is a block diagram showing an example of a configuration of a switching regulator including a current monitor circuit 11K according to embodiment 6. FIG. 23 is a block diagram showing an example of a configuration of a switching regulator including a current monitor circuit 11L according to embodiment 7.FIG. 13 is a block diagram showing a configuration example of a switching regulator including a current monitor circuit 11M according to an eighth embodiment.

[0011] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings, in which the same or similar components are designated by the same reference numerals.

[0012] (Inventor's Findings) First, in order to explain the problem to be solved by the present invention, a basic circuit will be described below.

[0013] (Basic Circuit) Fig. 1 is a block diagram showing the configuration of a switching regulator 1 according to a basic circuit. In Fig. 1, the switching regulator 1 includes a switching modulation circuit 10, an inverter INV1, an OR gate NOR1, a zero-cross detector 11, MOS transistors Q1 and Q2 as a pair of switch elements, and terminals T1 to T4.

[0014] 1, a switching modulation circuit 10 generates, for example, a PWM signal for switching MOS transistors Q1 and Q2 constituting an inverter circuit based on an output voltage Vout fed back to a terminal T4 so that the output voltage Vout becomes a predetermined value. The PWM signal is output to the gate of MOS transistor Q1 via inverter INV1 and to the gate of MOS transistor Q2 via NOR gate NOR1, thereby switching MOS transistors Q1 and Q2. A power supply voltage Vdd is connected to ground via terminal T1, the source and drain of MOS transistor Q1, the drain and source of MOS transistor Q2, and terminal T2. The output voltages from the drains of MOS transistors Q1 and Q2 are output to output capacitor Cout as output voltage Vout via terminal T3, current detector 12, and inductor Ind. Here, output voltage Vout is fed back to terminal T4.

[0015] A current signal corresponding to the inductor current Iind detected by the current detector 12 is input to the zero-cross detector 11, which generates an H-level zero-cross detection signal ZCDET every time the inductor current Iind crosses zero and outputs it to the NOR gate NOR1.

[0016] The basic circuit shown in Fig. 1, which is configured as described above, is a diagram illustrating the basic operation of monitoring the inductor current Iind, and is characterized in that the zero-cross detector 11 detects when the inductor current during rectification reaches zero and controls the switching operation. Specifically, in Fig. 1, in response to the zero-cross detection signal ZCDET at H level, the switching operation is stopped to prevent current backflow.

[0017] Next, modifications of the basic circuit will be described below.

[0018] (Variation 1) Fig. 2 is a block diagram showing the configuration of the zero-cross detector 11 of Fig. 1, and Fig. 3 is a timing chart of each signal showing an example of the operation of the switching regulator 1 of Fig. 1. In Fig. 2, the zero-cross detector 11 is configured to include a "current monitor circuit" including a comparator 13.

[0019] 2, a switching voltage Vsw at the connection point between the drain of MOS transistor Q1 and the drain of MOS transistor Q2 is applied to the non-inverting input terminal of a comparator 13, and the ground voltage at the source of MOS transistor Q2 is applied to the inverting input terminal of the comparator 13. The comparator 13 outputs a comparison result signal as a zero-crossing detection signal ZCDET.

[0020] In the zero-crossing detector 11 configured as described above, when the inductor current Iind becomes "0 A," the drain-source voltage Vds of the MOS transistor Q2 becomes 0 V, so "0 A" can be detected by comparing the voltages across the MOS transistor Q2. However, as shown in FIG. 3, there is a problem in that a backflow current Iind occurs due to the delay time tdelay.

[0021] Therefore, a current monitor circuit 11A (included in the zero-cross detector 11) according to the following first modification has been proposed.

[0022] (Modification 1) Fig. 4 is a block diagram showing the configuration of a current monitor circuit 11A according to Modification 1. Fig. 5 is a timing chart of signals showing an example of the operation of a switching regulator including the current monitor circuit 11A of Fig. 4. The current monitor circuit 11A of Fig. 4 differs from the current monitor circuit 11 of Fig. 2 in the following respects: (1) A constant current source IS1 is inserted between the power supply voltage Vdd and the non-inverting input terminal of the comparator 13. (2) A MOS transistor Q3, the gate of which is applied with the power supply voltage Vdd, is inserted between the non-inverting input terminal of the comparator 13 and the drain of the MOS transistor Q2.

[0023] According to the switching regulator including the current monitor circuit 11A configured as described above, as shown in FIG. 5, the voltage Vmoni, which is obtained by level-shifting the switching voltage Vsw by a predetermined voltage, can be compared with the ground voltage, thereby enabling detection to be performed earlier by the delay time.

[0024] The detection voltage of the comparator 13 is expressed by the following equation.

[0025] 0V<0V-Vdsdrv+Vdsmoni

[0026] Here, Vdsdrv is the voltage across the MOS transistor Q2, and Vdsmoni is the voltage across the MOS transistor Q3. The inductor current Iind, which is the DC detection current, is expressed by the following equation.

[0027] Iind = (on-resistance of Q3) x (bias current by IS1) ÷ (on-resistance of Q2)

[0028] The AC detection current taking the delay time tdelay into consideration is expressed by the following equation:

[0029] AC detection current = DC detection current - Vout x tDelay / Ind Vdsdrv = (on-resistance of Q2) x (current Iind of Q2) Vdsmoni = (on-resistance of Q3) x (bias current by IS1)

[0030] Next, a current monitor circuit for detecting currents other than zero will be described below.

[0031] (Modification 2) Fig. 6 is a block diagram showing the configuration of a current monitor circuit 11B according to Modification 2. Fig. 7 is a timing chart of signals showing an example of the operation of a switching regulator including the current monitor circuit 11B of Fig. 6. The current monitor circuit 11B of Fig. 6 differs from the current monitor circuit 11A of Fig. 4 in the following respects: (1) Instead of the constant current source IS1, a constant current source IS12 is provided, thereby making the voltage Vdsmoni larger than that at the time of zero detection in Fig. 4, causing the comparator 13 to detect a current value larger than "0 A." (2) The comparator 13 outputs a voltage VCDET of a comparison result signal.

[0032] (Modification 3) FIG. 8 is a block diagram showing the configuration of a current monitor circuit 11C according to Modification 3. FIG. 9 is a timing chart of signals showing an example of the operation of a switching regulator including the current monitor circuit 11C of FIG. 8. The current monitor circuit 11C of FIG. 8 differs from the current monitor circuit 11B of FIG. 6 in the following respects: (1) A constant current source IS2 is provided instead of the constant current source IS1A. Here, the power supply voltage Vdd is connected to the inverting input terminal of the comparator 13 via the constant current source IS2. (2) The switching voltage Vsw is applied to the non-inverting input terminal of the comparator 13. (3) A MOS transistor Q4, whose gate receives the power supply voltage Vdd, is inserted between the inverting input terminal (reference voltage Vref) of the comparator 13 and ground.

[0033] The current monitor circuit 11C configured as above is characterized in that the comparator 13 detects a current that flows backward by the voltage Vdsref.

[0034] (Modification 4) Fig. 10 is a block diagram showing the configuration of a current monitor circuit 11D according to Modification 4. Fig. 11 is a timing chart of each signal showing an example of the operation of a switching regulator including the current monitor circuit 11D of Fig. 10.

[0035] 10, the current monitor circuit 11D is configured to include three constant current sources IS1, IS2, and IS12, MOS transistors Q3 to Q5, switches SW1 to SW6, and a comparator 13. Here, switches SW1 and SW2 are turned on or off based on a selection signal RCSEL, switches SW3 and SW4 are turned on or off based on a selection signal VCSEL, and switches SW5 and SW6 are turned on or off based on a selection signal ZCSEL, and any pair of switches is turned on. The comparator 13 outputs a comparison result signal voltage LSCDET.

[0036] The current monitor circuit 11D configured as above is an example of a circuit in which three types of inductor currents are detected by one comparator 13.

[0037] Comparative Example FIG. 12 is a block diagram showing the configuration of a current monitor circuit 11E according to a comparative example disclosed in Patent Document 1. In FIG.

[0038] 12, the current monitor circuit 11E is configured to include three variable constant current sources VIS1 to VIS3, MOS transistors Q3 to Q5, switches SW1 to SW6, and a comparator 13. Here, switches SW1 and SW2 are turned on or off based on a selection signal RCSEL, switches SW3 and SW4 are turned on or off based on a selection signal VCSEL, and switches SW5 and SW6 are turned on or off based on a selection signal ZCSEL, and any pair of switches is turned on. The comparator 13 outputs a comparison result signal voltage LSCDET.

[0039] Problems 1 to 3 of the current monitor circuit 11E configured as above will be described below.

[0040] (Issue 1) When it is desired to monitor multiple detection values, such as zero inductor current Iind, forward overcurrent, and reverse overcurrent, even if the input-equivalent offset voltage Voffset of the shared comparator 13 is the same, the reference voltage Vrefr and monitoring voltages Vmoniz and Vmoniv will vary, and therefore correction such as trimming will be required to individually adjust the voltages generated by MOS transistors Q3 to Q5. This increases the number of correction items during mass production and increases the chip area due to the correction circuit (FIG. 12).

[0041] Fig. 13 is a block diagram showing a configuration of a part of the current monitor circuit 11E of Fig. 12. Fig. 14 is a timing chart of each signal showing an example of the operation of a switching regulator including the current monitor circuit of Fig. 13.

[0042] (Issue 2) Because both the reference voltage and the monitoring voltage have finite impedance, there was a concern that noise transmitted through the parasitic capacitances C1 and C2 would be superimposed on the differential input and generated voltage of the comparator 13 when the selector switches SW1 to SW6 were opened or closed, resulting in erroneous detection (FIGS. 13 and 14).

[0043] Fig. 15 is a block diagram showing the configuration of the current monitor circuit 11E of Fig. 12. Fig. 16 is a timing chart of each signal showing an example of the operation of a switching regulator including the current monitor circuit of Fig. 15.

[0044] (Issue 3) When opening and closing the selector switches SW1 to SW6, if the control signals of SW1 to SW6 are turned on simultaneously due to timing differences, there is a concern that the reference voltages and monitoring voltages may be mixed up, resulting in erroneous detection (FIGS. 15 and 16).

[0045] An embodiment for solving the above problems 1 to 3 will be described below.

[0046] First Embodiment FIG. 17 is a block diagram showing an example of the configuration of a switching regulator including a current monitor circuit 11F according to a first embodiment.

[0047] 17, the current monitor circuit 11F is configured to include four constant current sources IS21 to IS24, switches SW11 and SW12, MOS transistors Q3 and Q4, and a comparator 13. The switching regulator including the current monitor circuit 11F includes a switching modulation circuit 10, which is a control circuit.

[0048] The power supply voltage Vdd is connected to the inverting input terminal of the comparator 13 via a constant current source IS21, and is also connected to the inverting input terminal of the comparator 13 via a switch SW11, which is on / off controlled by a selection signal RCSEL, and a constant current source IS22. The power supply voltage Vdd is also connected to the non-inverting input terminal of the comparator 13 via a constant current source IS23, and is also connected to the non-inverting input terminal of the comparator 13 via a switch SW12, which is on / off controlled by a selection signal VCSEL, and a constant current source IS24. A MOS transistor Q3, whose gate receives the power supply voltage Vdd, is inserted between the non-inverting input terminal of the comparator 13 and the switching voltage Vsw. A MOS transistor Q4, whose gate receives the power supply voltage Vdd, is inserted between the inverting input terminal of the comparator 13 and ground.

[0049] The non-inverting input terminal of the comparator 13 is the generation point of the monitoring voltage Vmoni and becomes the monitoring voltage Vmoni, and its inverting input terminal is the generation point of the reference voltage Vref and becomes the reference voltage Vref, and the comparator 13 compares these voltages and outputs a comparison result signal voltage LSCDET. That is, the constant current sources IS21, IS22 and the switch SW11 form a reference voltage circuit for generating the reference voltage Vref, and the constant current sources IS23, IS24 and the switch SW12 form a monitoring circuit for generating the monitoring voltage Vmoni for monitoring the switching voltage Vsw.

[0050] 17, based on the output voltage Vout fed back to a terminal T4, a switching modulation circuit 10 generates, for example, a PWM signal for switching the MOS transistors Q1 and Q2 that constitute an inverter circuit, and switches the MOS transistors Q1 and Q2 so that the output voltage Vout becomes a predetermined value. Also, as described above, the switching modulation circuit 10 generates the selection signals RCSEL and VCSEL at mutually different timings and outputs them to the control terminals of the switches SW11 and SW12, respectively, thereby controlling the on / off of the switches SW11 and SW12.

[0051] 17 configured as described above, the reference voltage Vref and the monitoring voltage Vmoni are not generated separately and then switched, but rather the voltages generated by the MOS transistors Q3 and Q4 are changed at different timings, thereby changing the reference voltage Vref or the monitoring voltage Vmoni, thereby solving the three problems 1 to 3 of the comparative example in Fig. 12. Furthermore, by sharing the reference voltage circuit and the monitoring circuit, it is possible to reduce the chip area and reduce the circuit current consumption.

[0052] (Solution to Problem 1) In contrast to Problem 1 of the comparative example, by sharing the MOS transistor Q4 that generates the reference voltage Vref and its bias current (by IS21 and IS22) and the MOS transistor Q3 that generates the monitoring voltage and its bias current (by IS23 and IS24), correcting any one of the three types of detection currents also corrects the other detection values.

[0053] In the current monitor circuit 11E of Fig. 12, if the on-resistance of MOS transistor Q5 is finished smaller than the design value and the on-resistance of MOS transistor Q3 is finished larger than the design value, the monitor voltages Vmoniz and Vmoniv must be corrected in opposite directions. In contrast, in the current monitor circuit 11F of Fig. 17, since the circuits are shared as described above and the finish variations are the same, correction can be completed by simply trimming the input-equivalent offset, on-resistance, bias current, etc. of the comparator 13 once. This solves the problem 1.

[0054] (Solution of Problem 2) Problem 2 can be solved by making the direct parasitic capacitances of the switches SW11 and SW12 invisible at the node of the reference voltage Vref and the node of the monitoring voltage Vmoni.

[0055] (Solution to Problem 3) Because the switches SW11 and SW12 can be turned on with a single switch in both cases of zero and forward overcurrent (switching by the selection signal VCSEL to turn on the switch SW12 and turn off the switch SW11) and zero and reverse overcurrent (switching by the selection signal RCSEL to turn on the switch SW11 and turn off the switch SW12), there is no need to adjust the control timing, thereby solving Problem 3.

[0056] As described above, according to the first embodiment, not only the comparator 13 but also the monitoring circuit and reference voltage circuit are shared, so that manufacturing variations of a plurality of detection circuits can be collectively corrected. In addition, there is no need to adjust the control timing, and the parasitic capacitance is not directly visible at the input terminal of the comparator 13, so erroneous detection can be avoided.

[0057] (Embodiment 2) Fig. 18 is a block diagram showing an example configuration of a switching regulator including a current monitor circuit 11G according to embodiment 2. The current monitor circuit 11G of Fig. 18 differs from the current monitor circuit 11F of Fig. 17 in the following respects: (1) A constant current source IS22 is inserted between the switch SW11 and the inverting input terminal of the comparator 13. (2) A constant current source IS24 is inserted between the switch SW11 and the inverting input terminal of the comparator 13. The differences will be described below.

[0058] There are multiple embodiments of the method or technology for generating the reference voltage Vref or the monitoring voltage Vmoni, and the second embodiment shown in Fig. 18 is one example. In this example, the switches SW11 and SW12 are arranged downstream of the current of the constant current sources IS22 and IS24 when the impedance of the reference voltage Vref or the monitoring voltage Vmoni is low or the parasitic capacitance of the switches SW11 and SW12 is small.

[0059] According to the second embodiment configured as above, in addition to the above-mentioned effects, the same effects as those of the first embodiment are obtained.

[0060] 19 is a block diagram showing an example of the configuration of a switching regulator including a current monitor circuit 11H according to a third embodiment. The current monitor circuit 11H of FIG. 19 differs from the current monitor circuit 11F of FIG. 17 in the following respects: (1) A resistor Rmoni is provided instead of the MOS transistor Q3. (2) A resistor Rref is provided instead of the MOS transistor Q4. The differences will be described below.

[0061] 19 is an example in which the reference voltage Vref or the monitoring voltage Vmoni is generated by resistors Rmoni and Rref instead of MOS transistors Q3 and Q4. As a result, the reference voltage Vref or the monitoring voltage Vmoni is changed by the resistance value rather than the on-resistance of the MOS transistors.

[0062] According to the third embodiment configured as above, the same effects as those of the first embodiment are obtained.

[0063] (Fourth Embodiment) Fig. 20 is a block diagram showing an example of the configuration of a switching regulator including a current monitor circuit 11I according to a fourth embodiment. The current monitor circuit 11I of Fig. 20 differs from the current monitor circuit 11F of Fig. 17 in the following respects: (1) A MOS transistor Q3A is provided instead of the switch SW12, the constant current source IS24, and the MOS transistor Q3. (2) A MOS transistor Q4A is provided instead of the switch SW11, the constant current source IS22, and the MOS transistor Q4. The differences will be described below.

[0064] 20, MOS transistors Q3A and Q4A are each formed, for example, by a circuit in which a plurality of MOS transistors are connected in series, and by shorting out some of the MOS transistors based on selection signals VCSEL and RCSEL, the effective transistor size is changed, thereby changing the resistance value between the source and drain of MOS transistors Q3A and Q4A, and changing the current flowing therethrough, thereby changing the monitoring voltage Vmoni and reference voltage Vref. Note that instead of MOS transistors Q3A and Q4A formed by a plurality of MOS transistors connected in series, a circuit in which a plurality of resistors are connected in series may be used, for example.

[0065] According to the fourth embodiment configured as above, in addition to the above-mentioned effects, the fourth embodiment has the same effects as the first embodiment.

[0066] 21 is a block diagram showing an example of the configuration of a switching regulator including a current monitor circuit 11J according to a fifth embodiment. The current monitor circuit 11J in FIG. 21 differs from the current monitor circuit 11F in FIG. 17 in the following respects: (1) The switch SW11 and the constant current source IS22 are eliminated. The differences will be described below.

[0067] In the current monitor circuit 11J of FIG. 21 configured as described above, the current for generating the monitoring voltage Vmoni can be switched between two values ​​between a predetermined current value I11 and a predetermined current value I12, thereby switching the monitoring voltage Vmoni between two values ​​between a predetermined voltage value V11 and a predetermined voltage value V12.

[0068] According to the fifth embodiment configured as above, in addition to the above-mentioned effects, the fifth embodiment has the same effects as the first embodiment.

[0069] Sixth Embodiment Fig. 22 is a block diagram showing an example of the configuration of a switching regulator including a current monitor circuit 11K according to a sixth embodiment. The current monitor circuit 11K in Fig. 22 differs from the current monitor circuit 11F in Fig. 17 in the following respects: (1) The switch SW12 and the constant current source IS24 are eliminated. The differences will be described below.

[0070] In the current monitor circuit 11K of FIG. 22 configured as described above, the current for generating the reference voltage Vref may be switched between two values ​​between a predetermined current value I11 and a predetermined current value I12, thereby switching the reference voltage Vref between two values ​​between a predetermined voltage value V11 and a predetermined voltage value V12.

[0071] According to the sixth embodiment configured as above, in addition to the above-mentioned effects, the sixth embodiment has the same effects as the first embodiment.

[0072] Seventh Embodiment Fig. 23 is a block diagram showing an example of the configuration of a switching regulator including a current monitor circuit 11L according to a seventh embodiment. The current monitor circuit 11L in Fig. 23 differs from the current monitor circuit 11F in Fig. 17 in the following respects: (1) The switch SW11, constant current sources IS21 and IS22, and MOS transistor Q4 are eliminated. (2) The inverting input terminal of the comparator 13 is grounded.

[0073] According to the seventh embodiment configured as described above, the same effects as those of the first embodiment are obtained.

[0074] 24 is a block diagram showing a configuration example of a switching regulator including a current monitor circuit 11M according to embodiment 8. The current monitor circuit 11M in Fig. 24 includes a comparator 13, constant current sources IS31 and IS32, a switch SW21, and a MOS transistor Q3a.

[0075] 24, the power supply voltage Vdd is connected to the non-inverting input terminal of a comparator 13 via a grounded-gate MOS transistor Q3a. The non-inverting input terminal of the comparator 13 is grounded via a constant current source IS31 and also via a switch SW21 and a constant current source IS32. The switch SW21 is turned on or off based on an overcurrent selection signal.

[0076] 24 configured as above, the current from the MOS transistor Q3a at the non-inverting input terminal of the comparator 13 is changed by turning on or off the switch SW21, thereby changing the reference voltage Vref. The comparator 13 compares the switching voltage Vsw with the reference voltage Vref, and outputs a comparison result signal HSCDET.

[0077] The current monitor circuit 11M in FIG. 24 is characterized by monitoring the inductor current Iind when the inductor current Iind is passing through the MOS transistor Q1, which is the high-side driver element.

[0078] The eighth embodiment configured as described above has the same effects as the first embodiment, except for the effects described above.

[0079] (Other Modifications) In the above-described first to eighth embodiments, the pair of switch elements, MOS transistors Q1 and Q2, are arranged outside the current monitor circuits 11F to 11M, but the present invention is not limited to this, and they may be built into the current monitor circuits 11F to 11M.

[0080] As described above in detail, the switching regulator according to the present invention can reduce the circuit area compared to the prior art while maintaining high and stable quality in the switching regulator.

[0081] 1 Switching regulator 10 Switching modulation circuit 11 Zero cross detector 11A to 11M Current monitor circuit 12 Current detector 13 Comparator C1 to C2 Parasitic capacitance Cout Output capacitor Ind Inductor INV1 Inverter IS1 to IS32, IS1A Constant current source NOR1 NOR gate Q1 to Q5, Q3A, Q5A MOS transistor Rload Load resistance Rref Reference resistance SW1 to SW21 Switch T1 to T4 Terminal VIS1 to VIS3 Variable current source

Claims

1. A switching regulator comprising a pair of switch elements connected in series with each other, a comparator that compares a switching voltage corresponding to an inductor current flowing from the switching regulator to an inductor with a predetermined reference voltage and outputs a comparison result signal; a monitoring circuit that generates a current to generate a monitoring voltage for monitoring the switching voltage; a reference voltage circuit that generates a current for generating the reference voltage; a control circuit that generates a plurality of selection signals indicating a plurality of timings different from one another and outputs the selection signals to at least one of the monitoring circuit and the reference voltage circuit; At least one of the monitoring circuit and the reference voltage circuit changes the generated current in response to the multiple timings; At least one of the monitoring circuit and the reference voltage circuit is shared for the multiple timings. Switching regulator.

2. At least one of the monitoring circuit and the reference voltage circuit includes a circuit in which a first constant current source and a series circuit of a second constant current source and a switch connected in series with each other are connected in parallel.

2. The switching regulator according to claim 1.

3. The reference voltage of the reference voltage circuit is generated by grounding a MOS transistor having a gate to which a predetermined voltage is applied.

3. The switching regulator according to claim 2.

4. The reference voltage of the reference voltage circuit is such that a generating point of the reference voltage is grounded via a resistor.

3. The switching regulator according to claim 2.

5. The reference voltage of the reference voltage circuit is generated at a point grounded.

3. The switching regulator according to claim 2.

6. the monitoring circuit and the reference voltage circuit each include a first constant current source and a MOS transistor having a gate to which a predetermined voltage is applied, the first constant current source and the reference voltage being connected to a generating point of the monitoring voltage or the reference voltage; applying the selection signal to a back gate of the MOS transistor to change a resistance value of the MOS transistor and thereby change the monitoring voltage or the reference voltage; 2. The switching regulator according to claim 1.