Transistor

Abstract

Provided is a transistor having little variation in electrical characteristics. The transistor has first to fourth conductors, first to tenth insulators, and an oxide. The third to fifth insulators are positioned on the second insulator, the sixth insulator has an area that is in contact with an upper surface of the first insulator, a side surface of the oxide, a side surface and an upper surface of the second conductor, and a side surface and an upper surface of the third conductor, the first conductor overlaps with the oxide and the fourth conductor, the third insulator overlaps with the oxide and the fourth conductor, the fourth insulator overlaps with the oxide and the second conductor, the fifth insulator overlaps with the oxide and the third conductor, the eighth insulator is in contact with each of a side surface of the third insulator, a side surface of the oxide, and a side surface of the seventh insulator, and an upper surface of the third insulator matches, or substantially matches, the heights of the upper surface of the fourth insulator and the upper surface of the fifth insulator.

Description

transistor

[0001] 1. Field of the Invention

[0003] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0004] In recent years, semiconductor devices have been developed and are mainly used in LSIs, CPUs, memories, etc. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] Impurities and defects in an oxide semiconductor used in a transistor affect the electrical characteristics of the transistor. One example of defects in an oxide semiconductor is oxygen vacancies. Therefore, it is considered preferable that an oxide semiconductor used in a transistor has fewer oxygen vacancies. Patent Documents 3 and 4 disclose methods of supplying oxygen to an oxide semiconductor from an insulator provided below the oxide semiconductor to compensate for the oxygen vacancies.

[0009] Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits, and there is also a demand for improved productivity in semiconductor devices including integrated circuits.

[0010] JP 2012-257187 A JP 2011-151383 A International Publication No. 2019 / 048983 International Publication No. 2019 / 123109

[0011] An object of one embodiment of the present invention is to provide a transistor with little variation in electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with high reliability.An object of one embodiment of the present invention is to provide a transistor with good electrical characteristics.An object of one embodiment of the present invention is to provide a novel transistor.

[0012] Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors.Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability.Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics.Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current.Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0013] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc.

[0014] One aspect of the present invention is a transistor including a first conductor, a first insulator on the first conductor, a second insulator on the first insulator, a third insulator, a fourth insulator, and a fifth insulator on the second insulator, an oxide on the third insulator, the fourth insulator, and the fifth insulator, a second conductor and a third conductor on the oxide, a sixth insulator on the second conductor and the third conductor, a seventh insulator on the sixth insulator, an eighth insulator on the oxide, a ninth insulator on the eighth insulator, a fourth conductor on the ninth insulator, and a tenth insulator on the seventh insulator, the eighth insulator, the ninth insulator, and the fourth conductor. The sixth insulator has a region in contact with the top surface of the first insulator, the side surface of the oxide, the side surface and top surface of the second conductor, and the side surface and top surface of the third conductor; the first conductor is arranged to overlap the oxide and the fourth conductor; the third insulator is arranged to overlap the oxide and the fourth conductor; the fourth insulator is arranged to overlap the oxide and the second conductor; the fifth insulator is arranged to overlap the oxide and the third conductor; the eighth insulator is in contact with each of the side surface of the third insulator, the side surface of the oxide, and the side surface of the seventh insulator; the eighth insulator has a region thinner than the ninth insulator; and the top surface of the third insulator is flush or approximately flush with the top surfaces of the fourth insulator and the fifth insulator.

[0015] In the above transistor, it is preferable that the upper surface of the fourth conductor is flush or approximately flush with the upper surface of the seventh insulator.

[0016] In the above transistor, the top surface of the fourth conductor is preferably at the same or approximately the same height as the top of the eighth insulator and the top of the ninth insulator.

[0017] In the above transistor, it is preferable that the eighth insulator contain aluminum and oxygen and have a region with a thickness greater than or equal to 1.0 nm and less than or equal to 3.0 nm.

[0018] In the above transistor, it is preferable that the first insulator and the sixth insulator each contain silicon and nitrogen, the second insulator and the tenth insulator each contain aluminum and oxygen, and the third insulator, the seventh insulator, and the ninth insulator each contain silicon and oxygen.

[0019] Furthermore, it is preferable that the above transistor has an eleventh insulator on the tenth insulator, the eleventh insulator being in contact with the top surface of the first insulator, the side surface of the sixth insulator, the side surface of the seventh insulator, the side surface of the tenth insulator, and the top surface of the tenth insulator, and the eleventh insulator contains silicon and nitrogen.

[0020] Another embodiment of the present invention is a transistor including a first insulator, a second insulator on the first insulator, a third insulator, a fourth insulator, and a fifth insulator on the second insulator, an oxide on the third insulator, the fourth insulator, and the fifth insulator, a first conductor and a second conductor on the oxide, a sixth insulator on the first conductor and the second conductor, a seventh insulator on the sixth insulator, an eighth insulator on the oxide, a third conductor on the eighth insulator, and a ninth insulator on the seventh insulator, the eighth insulator, and the third conductor. The sixth insulator has an area in contact with the top surface of the first insulator, the side surface of the oxide, the side surface and top surface of the first conductor, and the side surface and top surface of the second conductor; the third insulator is arranged so as to overlap the oxide and the third conductor; the fourth insulator is arranged so as to overlap the oxide and the first conductor; the fifth insulator is arranged so as to overlap the oxide and the second conductor; the eighth insulator is in contact with each of the side surface of the third insulator, the side surface of the oxide, and the side surface of the seventh insulator; and the top surface of the third insulator is at or approximately at the same height as the top surface of the fourth insulator and the top surface of the fifth insulator.

[0021] In the above transistor, it is preferable that the top surface of the third conductor is flush or approximately flush with the top surface of the seventh insulator.

[0022] In the above transistor, the top surface of the third conductor is preferably flush or approximately flush with the height of the top of the eighth insulator.

[0023] In the above transistor, it is preferable that the first insulator and the sixth insulator each contain silicon and nitrogen, the second insulator and the ninth insulator each contain aluminum and oxygen, and the third insulator, the seventh insulator, and the eighth insulator each contain silicon and oxygen.

[0024] Furthermore, it is preferable that the above transistor has a tenth insulator on the ninth insulator, the tenth insulator being in contact with the top surface of the first insulator, the side surface of the sixth insulator, the side surface of the seventh insulator, the side surface of the ninth insulator, and the top surface of the ninth insulator, and the tenth insulator contains silicon and nitrogen.

[0025] In the above transistor, it is preferable that each of the oxide, the fourth insulator, and the fifth insulator contains indium, gallium, zinc, and oxygen, and that the atomic ratio of gallium to indium in the fourth insulator is larger than the atomic ratio of gallium to indium in the oxide.

[0026] In addition, when the oxide of the transistor was measured by secondary ion mass spectrometry, the hydrogen concentration in the oxide was 1×10 １９ atoms / cm ３ It is preferred that the ion exchange membrane has an area that is less than 1000 nm.

[0027] According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a transistor with high reliability can be provided. Alternatively, according to one embodiment of the present invention, a transistor with good electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a novel transistor can be provided.

[0028] According to one embodiment of the present invention, a semiconductor device with little variation in electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0029] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc.

[0030] FIG. 1A is a top view of a transistor according to one embodiment of the present invention. FIGS. 1B and 1C are cross-sectional views of a transistor according to one embodiment of the present invention. FIGS. 2A and 2B are cross-sectional views of a transistor according to one embodiment of the present invention. FIGS. 3A to 3E are cross-sectional views of a transistor according to one embodiment of the present invention. FIGS. 4A to 4J are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. FIGS. 5A to 5H are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. FIGS. 6A to 6F are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. FIG. 7 is a top view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 8 is a schematic cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 9 is a schematic cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 10 is a schematic view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIGS. 11A to 11D are cross-sectional views of a transistor according to one embodiment of the present invention. FIGS. 12A to 12D are cross-sectional views of a transistor according to one embodiment of the present invention. FIGS. 13A to 13D are cross-sectional views of a transistor according to one embodiment of the present invention. FIG. 14A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 14B to 14D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIGS. 15A and 15B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 18B to 18D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 19A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 19B to 19D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 20A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 20B to 20D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.FIG. 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 21B to 21D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 22A is a top view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 22B to 22D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 23A is a top view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 23B to 23D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 24A is a top view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 24B to 24D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 25A is a top view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 25B to 25D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 26A is a top view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 26B to 26D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 27A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 27B to 27D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 28A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 28B to 28D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 29A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 29B to 29D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 30A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 30B to 30D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 31A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 31B and 31C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 32 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 33 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 34 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIGS. 35A and 35B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 36 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 37A is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.FIG. 37B is a perspective view illustrating a configuration example of a memory device according to one embodiment of the present invention. FIGS. 38A to 38H are circuit diagrams illustrating a configuration example of a memory device according to one embodiment of the present invention. FIGS. 39A and 39B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. FIGS. 40A and 41B are diagrams illustrating a configuration example of a CPU. FIGS. 41A and 41B are diagrams illustrating a configuration example of a CPU. FIG. 42 is a diagram illustrating a power gating sequence of a CPU. FIGS. 43A and 43B are diagrams illustrating an example of an electronic component. FIGS. 44A to 44E are schematic diagrams of a memory device according to one embodiment of the present invention. FIGS. 45A to 45H are diagrams illustrating electronic devices according to one embodiment of the present invention.

[0031] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0032] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers and resist masks may be unintentionally thinned by etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions, and repeated explanations may be omitted. When referring to similar functions, the same hatching pattern may be used and no particular symbols may be assigned.

[0033] In order to make the invention easier to understand, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings, and some hidden lines may be omitted.

[0034] In addition, in this specification and the like, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for explanation. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification and the like.

[0035] Furthermore, in this specification, terms indicating placement, such as "above" or "below," are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0036] For example, if it is explicitly stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. Here, X and Y are assumed to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, or a layer, etc.).

[0037] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0038] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0039] Note that the channel length refers to, for example, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or in a channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be determined to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0040] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0041] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may become unnegligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0042] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0043] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM (Transmission Electron Microscope) image, for example.

[0044] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, oxygen vacancies (also called oxygen vacancies) may be formed.

[0045] In this specification and the like, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. Silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen. Aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen. Aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen. Hafnium oxynitride refers to a material whose composition contains more oxygen than nitrogen. Hafnium nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0046] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0047] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0048] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0049] In this specification, the term "normally off" refers to a state in which, when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 −２０ A or less, 1 x 10 at 85°C −１８ A or less, or 1 x 10 at 125°C −１６ This means that it is A or below.

[0050] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0051] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m, n]” may be added to the symbol.

[0052] In this specification, the term "having the same or approximately the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a semiconductor device manufacturing process, a planarization process (typically a CMP process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces processed by the CMP process have the same height from the reference surface. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the processed surface during the CMP process. In this specification, this case is also considered to be "having the same or approximately the same height." For example, in the case of a structure having two layers (here, a first layer and a second layer) with different heights relative to the reference surface, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "having the same or approximately the same height."

[0053] In this specification, "edges that coincide or approximately coincide" means that, when viewed from above, at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "edges that coincide or approximately coincide" is also used.

[0054] Embodiment 1 In this embodiment, a structural example of a transistor according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0055] <Configuration Example 1> A configuration example of a transistor according to one embodiment of the present invention will be described with reference to FIG. 1. FIGS. 1A to 1C are top views and cross-sectional views of a transistor 20. FIG. 1A is a top view of the transistor 20. FIGS. 1B and 1C are cross-sectional views of the transistor 20. FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 1A and is also a cross-sectional view of the transistor 20 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 1A and is also a cross-sectional view of a channel formation region and its vicinity in the channel width direction of the transistor 20. Note that some elements are omitted from the top view in FIG. 1A for clarity.

[0056] The transistor 20 has a conductor 15 on a substrate (not shown), an insulator 14 on the conductor 15, an insulator 22 on the insulator 14, insulators 24, 23a, and 23b on the insulator 22, an oxide 30 on the insulators 24, 23a, and 23b, conductors 42a, 42b, and an insulator 50 on the oxide 30, a conductor 60 located on the insulator 50 and overlapping with a portion of the oxide 30, an insulator 75 arranged on the insulators 14, 22, 24, 23a, 23b, oxide 30, conductor 42a, and conductor 42b, an insulator 80 on the insulator 75, and an insulator 82 on the insulators 80, 50, and conductor 60.

[0057] In the following description, the insulators 23a and 23b may be collectively referred to as the insulators 23. The conductors 42a and 42b may be collectively referred to as the conductors 42.

[0058] Openings are provided in the insulator 80 and the insulator 75, reaching the oxide 30. The insulator 50 and the conductor 60 are disposed in the openings. The insulator 50 and the conductor 60 are also provided between the conductor 42 a and the conductor 42 b in the channel length direction of the transistor 20.

[0059] The insulator 50 has a region in contact with the side surface of the conductor 60 and a region in contact with the bottom surface of the conductor 60. The insulator 50 also has regions in contact with the top surface of the insulator 14, the side surface of the insulator 22, the side surface of the insulator 24, the side surface of the oxide 30, the top surface of the oxide 30, the side surface of the conductor 42a, the side surface of the conductor 42b, the side surface of the insulator 75, and the side surface of the insulator 80.

[0060] The upper surface of the conductor 60 is positioned so that it is flush or approximately flush with the top of the insulator 50 and the upper surface of the insulator 80 .

[0061] 1B, the side of the opening into which the conductor 60 and the like are embedded is approximately perpendicular to the surface on which the oxide 30 is to be formed, but this embodiment is not limited to this. For example, the bottom of the opening may be U-shaped with a gently curved surface. Also, for example, the side of the opening may be inclined with respect to the surface on which the oxide 30 is to be formed.

[0062] The upper surface of the insulator 24 is disposed so as to be flush or approximately flush with the upper surfaces of the insulators 23a and 23b.

[0063] The conductor 60 functions as a first gate (also referred to as a top gate) electrode, and the conductor 15 functions as a second gate (also referred to as a back gate) electrode. The insulator 50 functions as a first gate insulator, and the insulators 22 and 24 function as second gate insulators. Note that the insulator 23 may function as a second gate insulator. The conductor 42a functions as one of a source electrode and a drain electrode, and the conductor 42b functions as the other of the source electrode and the drain electrode. At least a part of the region of the oxide 30 that overlaps with the conductor 60 functions as a channel formation region.

[0064] In the transistor 20, a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 30 including the channel formation region.

[0065] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0066] As the oxide 30, for example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. Note that the above metal oxide in which element M is gallium may be referred to as In-Ga-Zn oxide. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as the oxide 30.

[0067] The oxide 30 preferably has crystallinity. In particular, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 30.

[0068] CAAC-OS has a highly crystalline and dense structure, and contains impurities or defects (e.g., oxygen vacancies (V Ｏ In particular, by performing heat treatment after forming the metal oxide at a temperature at which the metal oxide does not polycrystallize (for example, 400° C. or higher and 600° C. or lower), the CAAC-OS can have a dense structure with higher crystallinity. In this way, the density of the CAAC-OS can be increased, and impurities or defects in the CAAC-OS can be further reduced.

[0069] Furthermore, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0070] Although FIGS. 1B and 1C show a configuration in which the oxide 30 is a single layer, the present invention is not limited to this, and a laminated structure of two or more layers may also be used.

[0071] When the oxide 30 has a stacked structure of two or more layers, the regions 30a, 30b, and 30c described below may be formed in some of the layers or in all of the layers.

[0072] The oxide 30 may have a stacked structure of multiple oxide layers with different chemical compositions. For example, the atomic ratio of In to M in the metal oxide used in the oxide layer on the conductor 60 side is preferably larger than the atomic ratio of In to M in the metal oxide used in the oxide layer on the conductor 15 side. With this configuration, the transistor 20 can achieve a large on-state current and high frequency characteristics.

[0073] Furthermore, since the oxide layers contain a common element other than oxygen as a main component, the defect level density at the interface of the oxide layers can be reduced, which reduces the effect of interface scattering on carrier conduction and allows for a high on-current.

[0074] 2A shows an enlarged view of the channel formation region and its vicinity in FIG. 1B, and FIG. 2B shows an enlarged view of the channel formation region and its vicinity in FIG. 1C. As shown in FIG. 2A, the oxide 30 has a region 30c and a pair of regions 30a and 30b sandwiching the region 30c. At least a portion of the region 30c overlaps with the conductor 60. In other words, the region 30c is provided in a region between the conductor 42a and the conductor 42b. The region 30a is provided overlapping with the conductor 42a, and the region 30b is provided overlapping with the conductor 42b.

[0075] The region 30c functions as a channel formation region of the transistor 20. The region 30a functions as one of the source region and the drain region of the transistor 20, and the region 30b functions as the other of the source region and the drain region of the transistor 20.

[0076] The region 30c, which functions as a channel formation region, has fewer oxygen vacancies and a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the regions 30a and 30b, and is therefore a high-resistance region with a low carrier concentration. For example, the carrier concentration of the region 30c is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ The lower limit of the carrier concentration of the region 30c is not particularly limited, but is preferably, for example, 1×10 −９ cm −３ It can be said that:

[0077] Furthermore, for example, when the oxide 30 is measured by secondary ion mass spectrometry (SIMS), the hydrogen concentration in the oxide 30 is 1×10 ２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ , more preferably 1 × 10 １８ atoms / cm ３ In particular, it is preferable that the region is located within region 30c of oxide 30. In this specification, "the impurity concentration in the layer when the layer is measured by SIMS" may be referred to as "the impurity concentration in the layer obtained by SIMS."

[0078] The regions 30a and 30b, which function as source and drain regions, have many oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, which increases the carrier concentration and reduces the resistance. That is, the regions 30a and 30b have a higher carrier concentration and lower resistance than the region 30c. For example, the carrier concentration of each of the regions 30a and 30b is 1×10 １７ cm −３ It is preferable that the ratio is 1×10 or more. １８ cm −３ More preferably, it is 1×10 or more. １９ cm −３ The upper limit of the carrier concentration of each of the regions 30a and 30b is not particularly limited, but may be, for example, 1×10 ２１ cm −３ It can be said that:

[0079] Furthermore, a region may be formed between region 30c and region 30a or region 30b, in which the carrier concentration is equal to or lower than that of regions 30a and 30b, and equal to or higher than that of region 30c. That is, this region functions as a junction region between region 30c and region 30a or region 30b. The junction region may have a hydrogen concentration equal to or lower than that of regions 30a and 30b, and equal to or higher than that of region 30c. The junction region may also have oxygen vacancies equal to or lower than those of regions 30a and 30b, and equal to or higher than those of region 30c.

[0080] It may be difficult to clearly detect the boundaries between the regions in the oxide 30. The concentrations of impurity elements such as metal elements, hydrogen, and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of impurity elements such as metal elements, hydrogen, and nitrogen decrease in a region closer to the channel formation region.

[0081] In a transistor using an oxide semiconductor, if impurities or oxygen vacancies exist in a channel formation region of the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and the channel formation region be i-type (intrinsic) or substantially i-type.

[0082] On the other hand, the source and drain regions in the oxide semiconductor preferably have a high carrier concentration and are n-type. Ｏ However, V contained in the source region and the drain region is preferably contained. Ｏ The diffusion of H into the channel forming region must be suppressed. Ｏ It is preferable that H is stable. In particular, V contained in the source region and the drain region Ｏ Variations in H within the substrate surface result in variations in the electrical characteristics of the transistor.

[0083] That is, in the oxide semiconductor, the region 30c that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type. On the other hand, the regions 30a and 30b that function as source and drain regions preferably have a high carrier concentration and are n-type. The i-type or substantially i-type region 30c and the n-type regions 30a and 30b are preferably stable.

[0084] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V Ｏ However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 20. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies across the substrate surface, the electrical characteristics of the transistor will vary.

[0085] Therefore, in the oxide semiconductor, the region 30c that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 30a and 30b that function as source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 30a and 30b.

[0086] Therefore, in this embodiment, an insulator containing excess oxygen is used as the insulator in contact with the upper surface of region 30c and the insulator in contact with the lower surface of region 30c, and an insulator that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) is used as the insulator in contact with the lower surface of region 30a and the insulator in contact with the lower surface of region 30b. This configuration allows oxygen to be efficiently supplied to region 30c, making the channel formation region a stable i-type region. Furthermore, since the amount of oxygen supplied to regions 30a and 30b is smaller than that to region 30c, a decrease in the carrier concentration in the source and drain regions can be prevented.

[0087] 1B, the insulator 50 is in contact with the upper surface of the region 30c, and the insulator 24 is in contact with the lower surface of the region 30c. Since the region 30c is provided overlapping with the conductor 60, the insulator 24 overlaps with the conductor 60 via the region 30c. In other words, the insulator 24 is arranged to overlap with the oxide 30 and the conductor 60.

[0088] The insulators 50 and 24 preferably contain excess oxygen, so that the oxygen contained in the insulators 50 and 24 can be efficiently supplied to the region 30c.

[0089] Note that when the insulator in contact with the insulator 50 contains excess oxygen, the insulator 50 may be formed using an insulating material that easily transmits oxygen. In this case, the oxygen contained in the insulator in contact with the insulator 50 can be supplied to the region 30c through the insulator 50. In the transistor 20 shown in FIGS. 1B and 1C , an example of the insulator in contact with the insulator 50 is the insulator 80. That is, the insulator 80 is preferably an insulator containing excess oxygen. In this case, the insulator 24 may be formed using an insulating material that easily transmits oxygen. With this configuration, the oxygen contained in the insulator 80 can be supplied to the region 30c through the insulator 50 and the insulator 24.

[0090] The arrows shown in Fig. 2A visualize the state in which oxygen contained in insulator 80 diffuses to region 30c via insulator 50 and the state in which oxygen contained in insulator 24 diffuses to region 30c. The arrows shown in Fig. 2B visualize the state in which oxygen contained in insulator 80 diffuses to region 30c via insulator 50, the state in which oxygen contained in insulator 80 diffuses to region 30c via insulators 50 and 24, and the state in which oxygen contained in insulator 24 diffuses to region 30c.

[0091] For the insulators 50, 24, and 80, insulating materials such as silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide with vacancies can be used. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulators 50, 24, and 80 are insulators containing at least oxygen and silicon. The above insulating materials also have low dielectric constants. Because the insulator 80 also functions as an interlayer film, forming the insulator 80 using the above insulating materials can reduce parasitic capacitance between wirings.

[0092] It is preferable that the concentrations of impurities such as water and hydrogen are reduced in the insulators 50, 24, and 80. At least one of the insulators 50, 24, and 80 has a hydrogen concentration in the film obtained by SIMS of 2×10 ２０ atoms / cm ３ less than 1×10 ２０ atoms / cm ３ less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ has an area that is less than

[0093] The insulator 50 needs to be provided in an opening formed in the insulator 80 or the like together with the conductor 60. To miniaturize the transistor 20, it is preferable that the insulator 50 has a thin film thickness. The film thickness of the insulator 50 is preferably 0.5 nm or more and 20 nm or less, and more preferably 1.0 nm or more and 15.0 nm or less. In this case, it is sufficient that at least a portion of the insulator 50 has a region with the above-mentioned film thickness.

[0094] Although FIGS. 1B and 1C illustrate a single-layer structure of the insulator 50, the present invention is not limited thereto and may include a stacked structure of two or more layers. For example, when the insulator 50 has a two-layer stacked structure, it is preferable to form the lower layer using an insulator that is easily permeable to oxygen and the upper layer using an insulator that has the function of suppressing oxygen diffusion. This structure can suppress the diffusion of oxygen contained in the lower layer into the conductor 60. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 30. It can also suppress oxidation of the conductor 60 due to oxygen contained in the lower layer. For example, it is preferable to form the lower layer using a material that can be used for the insulator 50 described above, and to use an insulator containing one or both of aluminum and hafnium oxides for the upper layer. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). For example, when hafnium oxide is used as the upper layer, the upper layer becomes an insulator containing at least oxygen and hafnium.

[0095] In the transistor 20 shown in FIGS. 1B and 1C , the insulator 23a is in contact with the bottom surface of the region 30a. Because the region 30a is provided overlapping the conductor 42a, the insulator 23a overlaps with the conductor 42a via the region 30a. In other words, the insulator 23a is arranged to overlap with the oxide 30 and the conductor 42a. The insulator 23b is in contact with the bottom surface of the region 30b. Because the region 30b is provided overlapping with the conductor 42b, the insulator 23b overlaps with the conductor 42b via the region 30b. In other words, the insulator 23b is arranged to overlap with the oxide 30 and the conductor 42b.

[0096] The insulators 23a and 23b preferably have a function of suppressing oxygen diffusion. Examples of insulators having a function of suppressing oxygen diffusion include aluminum oxide, magnesium oxide, hafnium oxide, oxides containing hafnium and silicon, oxides containing hafnium and aluminum, oxides containing hafnium and zirconium, gallium oxide, oxides containing gallium and zinc, In—Ga—Zn oxide, silicon nitride, and silicon nitride oxide. Note that the insulators 23a and 23b only need to have a function of suppressing oxygen diffusion, and are not limited to insulating materials, and semiconductor materials may also be used as the insulators 23a and 23b.

[0097] Furthermore, the insulators 23a and 23b preferably have compressive stress, and more preferably have compressive stress greater than that of the oxide 30. For example, silicon nitride applicable to the insulators 23a and 23b has compressive stress greater than that of the oxide 30. By using an insulator having compressive stress, particularly an insulator having compressive stress greater than that of the oxide 30, as the insulators 23a and 23b, it is possible to form strain (hereinafter sometimes referred to as tensile strain) that expands in the tensile direction in the regions 30a and 30b. The tensile strain increases V Ｏ By stably forming H, regions 30a and 30b can be stable n-type regions. The compressive stress of an insulator is a stress that attempts to relax the compressed shape of the insulator, and is a stress having a vector in the direction from the center to the end of the insulator.

[0098] As described above, In—Ga—Zn oxide is a metal oxide that can also be used for the oxide 30. When In—Ga—Zn oxide is used for the channel formation region of a transistor, the on-state current and field-effect mobility of the transistor tend to improve as the atomic ratio of indium to gallium increases. Furthermore, in In—Ga—Zn oxide, the atomic ratio of gallium to indium increases, and oxygen diffusion tends to be more suppressed. Therefore, when In—Ga—Zn oxide is used for the oxide 30 and the insulators 23 a and 23 b, the atomic ratio of indium to gallium in the In—Ga—Zn oxide used for the oxide 30 is preferably greater than the atomic ratio of indium to gallium in the In—Ga—Zn oxide used for the insulators 23 a and 23 b. Furthermore, in the In—Ga—Zn oxide used for the insulators 23 a and 23 b, it is preferable that the atomic ratio of gallium to indium is larger than the atomic ratio of gallium to indium in the In—Ga—Zn oxide used for the oxide 30.

[0099] Specifically, the insulators 23a and 23b may be metal oxides having an atomic ratio of In:M:Zn = 1:3:4 or a similar composition. The oxide 30 may be metal oxides having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0100] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0101] 2A shows a configuration in which the end of insulator 23a on the conductor 60 side coincides or roughly coincides with the end of region 30a on the conductor 60 side, and the end of insulator 23b on the conductor 60 side coincides or roughly coincides with the end of region 30b on the conductor 60 side, but the present invention is not limited to this. One or both of insulators 23a and 23b may have an area that overlaps with region 30c.

[0102] FIG. 3A shows a modification of the transistor 20 shown in FIG. 1B . FIG. 3A is a cross-sectional view of the transistor 20 in the channel length direction. Note that the cross-sectional structure of the transistor 20 in the channel width direction shown in FIG. 3A can be similar to that of the transistor 20 in FIG. 1C . In the transistor 20 shown in FIG. 3A , the insulator 23 a and the insulator 23 b may have a region overlapping with the channel formation region of the oxide 30. In this case, the width of the insulator 24 in the channel length direction of the transistor 20 is narrower than the width of the channel formation region. Oxygen supplied to the CAAC-OS tends to diffuse in a direction perpendicular to the c-axis. Therefore, when the CAAC-OS is used as the oxide 30, it is estimated that the structure can prevent excessive oxygen from being supplied to the source and drain regions.

[0103] It is preferable to use, as the insulator 82, an insulator that can add oxygen to the insulator 80. For example, it is preferable to use aluminum oxide as the insulator 82. In this case, the insulator 82 contains at least oxygen and aluminum. The insulator 82 or the insulating film that will become the insulator 82 is preferably formed by a sputtering method, and more preferably by a sputtering method in an oxygen-containing atmosphere. By forming the insulator 82 or the insulating film that will become the insulator 82 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulator 80 during film formation. This allows the insulator 80 to contain excess oxygen.

[0104] Furthermore, it is preferable to use a metal oxide having an amorphous structure as the insulator 82. For example, it is preferable to use a metal oxide such as aluminum oxide or magnesium oxide. A metal oxide having an amorphous structure contains oxygen atoms with dangling bonds, and may have the property of capturing or fixing hydrogen through the dangling bonds. By using such a metal oxide having an amorphous structure as a component of the transistor 20 or providing it around the transistor 20, it is possible to capture or fix hydrogen contained in the transistor 20 or hydrogen present around the transistor 20. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 20. By using a metal oxide having an amorphous structure as a component of the transistor 20 or providing it around the transistor 20, it is possible to manufacture a highly reliable transistor 20 with excellent characteristics.

[0105] The insulator 82 preferably has an amorphous structure, but may have a polycrystalline region formed in a portion thereof. The insulator 82 may also have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, the insulator 82 may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0106] As shown in FIG. 1B , the insulator 75 is configured to contact a portion of the upper surface of the insulator 14. Therefore, the oxide 30 is disposed within the region sealed by the insulators 75 and 14. Here, the insulators 75 and 14 preferably function as barrier insulating films that suppress the diffusion of impurities such as water and hydrogen into the sealed region. Therefore, the insulators 14 and 75 are preferably made of an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (i.e., the impurities are less likely to permeate). This configuration can suppress impurities such as water and hydrogen contained outside the sealed region from mixing into the sealed region. Therefore, impurities such as water and hydrogen can be suppressed from mixing into the oxide 30.

[0107] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0108] For the insulators 14 and 75, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen. For example, one or more materials selected from aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, oxides containing gallium and zinc, In—Ga—Zn oxide, silicon nitride, and silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has a higher hydrogen barrier property, for the insulators 14 and 75. In this case, the insulators 14 and 75 are insulators containing at least nitrogen and silicon. Note that the insulators 14 and 75 may each have a stacked structure (a stacked structure of two or more layers) combining the above-mentioned materials.

[0109] It is preferable to select an insulator that functions as an etching stopper film when the insulating film that will become insulators 23a and 23b is etched to form the grooves as insulator 22. For example, if silicon nitride is used for the insulating film that forms the grooves, aluminum oxide or In-Ga-Zn oxide may be used as insulator 22. In this way, it is preferable to select an appropriate material for insulator 22 in accordance with the material used for the insulating film that forms the grooves.

[0110] Alternatively, a metal oxide having an amorphous structure may be used for the insulator 22. For example, the metal oxide that can be used for the insulator 82 may be used for the insulator 22. With this structure, hydrogen contained in the channel formation region of the transistor 20 and diffused into the insulator 22 through the insulator 24 can be captured or fixed.

[0111] The conductor 60 is formed in a self-aligned manner so as to fill the opening formed in the insulator 80 etc. By forming the conductor 60 in this manner, the conductor 60 can be reliably positioned in the region between the conductors 42 a and 42 b without alignment.

[0112] Since the conductor 60 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 60 can be made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0113] Although the conductor 60 is shown as having a single layer structure in FIGS. 1B and 1C, it may have a laminated structure of two or more layers.

[0114] When the conductor 60 has a two-layer laminated structure, the layer on the insulator 50 side is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0115] Furthermore, since the layer on the insulator 50 side has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity caused by oxidation of a layer disposed more inward than the layer on the insulator 50 side due to oxygen contained in the insulator 50. As the conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0116] 1C , in the channel width direction of the transistor 20, the height of the bottom surface of the conductor 60 in a region where the conductor 60 and the oxide 30 do not overlap is preferably lower than the height of the bottom surface of the oxide 30, relative to the bottom surface of the insulator 14. The conductor 60, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 30 via the insulator 50, making it easier for the electric field of the conductor 60 to act on the entire channel formation region of the oxide 30. This increases the on-state current of the transistor 20 and improves its frequency characteristics. The difference between the height of the bottom surface of the conductor 60 in a region where the oxide 30 and the oxide 30 do not overlap and the height of the bottom surface of the oxide 30, relative to the bottom surface of the insulator 14, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0117] The conductors 42 a and 42 b are provided in contact with the upper surface of the oxide 30 .

[0118] The conductor 42 is preferably made of one or more selected from the group consisting of nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum. In one embodiment of the present invention, nitrides containing tantalum are particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel may also be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0119] 1B shows a configuration in which the conductor 42 is provided as a single layer, but the present invention is not limited to this. For example, the conductor 42 may be provided as a laminated structure of two or more layers. In this case, it is preferable to laminate multiple conductive layers formed from the above materials. Alternatively, it is preferable to laminate multiple conductive layers formed from the above materials with different compositions. When the conductor 42 has a laminated structure, for example, a laminated structure of a nitride containing tantalum and a nitride containing titanium on the nitride containing tantalum can be suitably used.

[0120] Note that hydrogen contained in the oxide 30 and the like may diffuse into the conductor 42a or the conductor 42b. In particular, by using a nitride containing tantalum for the conductors 42a and 42b, hydrogen contained in the oxide 30 and the like is likely to diffuse into the conductor 42a or the conductor 42b, and the diffused hydrogen may bond with nitrogen contained in the conductor 42a or the conductor 42b. In other words, hydrogen contained in the oxide 30 and the like may be absorbed by the conductor 42a or the conductor 42b.

[0121] Furthermore, when heat treatment is performed while the conductor 42a (conductor 42b) and the oxide 30 are in contact with each other, the sheet resistance of the oxide 30 in the region overlapping with the conductor 42a (conductor 42b) may decrease. Also, the carrier concentration may increase. Therefore, the resistance of the oxide 30 in the region overlapping with the conductor 42a (conductor 42b) can be reduced in a self-aligned manner.

[0122] It is preferable to perform microwave treatment in an oxygen-containing atmosphere with the conductors 42a and 42b provided on the oxide 30. By performing the microwave treatment, oxygen vacancies in the region 30c and V Ｏ The microwave treatment can reduce H. Here, the microwave treatment refers to a treatment using a device having a power source that generates high-density plasma using microwaves. In this specification, the microwave refers to an electromagnetic wave having a frequency of 300 MHz or more and 300 GHz or less.

[0123] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can be irradiated onto the region 30c. The action of the plasma, microwaves, etc. can be used to irradiate the V of the region 30c. Ｏ The hydrogen is separated into oxygen vacancies and hydrogen, the hydrogen is removed from the region 30c, and the oxygen vacancies are filled with oxygen. Ｏ In addition, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave processing, it is possible to prevent the carrier concentration in the regions 30a and 30b from being excessively reduced.

[0124] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 42a and 42b and do not reach the regions 30a and 30b. Ｏ Since H is reduced and an excessive amount of oxygen is not supplied, a decrease in the carrier concentration can be prevented.

[0125] Furthermore, it is preferable to perform microwave treatment in an atmosphere containing oxygen after forming the insulating film that will become insulator 50. By performing microwave treatment in an atmosphere containing oxygen through insulator 50 in this manner, oxygen can be efficiently injected into region 30c.

[0126] The oxygen implanted into the region 30c can take various forms, such as oxygen atoms, oxygen molecules, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 30c may take one or more of the above forms, and oxygen radicals are particularly preferred. Furthermore, the film quality of the insulator 50 can be improved, thereby improving the reliability of the transistor 20.

[0127] In this way, oxygen vacancies and V ＯBy removing H, the region 30c can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 30a and 30b, which function as source and drain regions, can be prevented, and the n-type state of the regions before the microwave treatment can be maintained. This prevents fluctuations in the electrical characteristics of the transistor 20 and prevents the electrical characteristics of the transistor 20 from varying across the substrate.

[0128] The conductor 15 is arranged to overlap the oxide 30 and the conductor 60. Furthermore, as shown in FIG. 1B , the conductor 15 is preferably larger than the area of ​​the oxide 30 that does not overlap with the conductors 42 a and 42 b. Furthermore, as shown in FIG. 1C , the conductor 15 preferably extends to an area outside the end of the oxide 30 in the channel width direction. That is, outside the side surface of the oxide 30 in the channel width direction, the conductor 15 and the conductor 60 preferably overlap with each other via an insulator. This configuration allows the channel formation region of the oxide 30 to be electrically surrounded by the electric field of the conductor 60, which functions as the first gate electrode, and the electric field of the conductor 15, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0129] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from a fin structure and a planar structure. By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to make the transistor less susceptible to the short channel effect.

[0130] By configuring the transistor 20 as a normally-off transistor and having the above-described S-channel structure, the channel formation region can be electrically surrounded. Therefore, the transistor 20 can also be considered to have a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By configuring the transistor 20 as an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide 30 and the gate insulator can be the entire bulk of the oxide 30. Therefore, it is possible to improve the current density flowing through the transistor, which is expected to improve the on-current of the transistor or the field-effect mobility of the transistor.

[0131] 1C, the conductor 15 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 15. Furthermore, it is not necessary to provide one conductor 15 for each transistor. For example, the conductor 15 may be shared by multiple transistors.

[0132] 1B shows a configuration in which the conductor 15 is provided as a single layer, the present invention is not limited to this. For example, the conductor 15 may be provided as a laminated structure of two or more layers.

[0133] The conductor 15 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 20 can be controlled by changing the potential applied to the conductor 15 independently of the potential applied to the conductor 60. In particular, applying a negative potential to the conductor 15 can increase the Vth of the transistor 20 and reduce the off-state current. Therefore, applying a negative potential to the conductor 15 can reduce the drain current when the potential applied to the conductor 60 is 0 V, compared to when no negative potential is applied.

[0134] The electrical resistivity of the conductor 15 is designed taking into consideration the potential to be applied to the conductor 15, and the film thickness of the conductor 15 is set in accordance with the electrical resistivity.

[0135] Note that when the transistor 20 has normally-off characteristics or when the off-state current of the transistor 20 is small, the conductor 15 may not be provided. By not providing the conductor 15, the manufacturing process of the transistor can be simplified and productivity can be improved.

[0136] 1B shows a configuration in which the insulator 80 and the insulator 50 are in contact with each other, but the present invention is not limited to this. For example, a configuration in which an insulator is provided between the insulator 80 and the insulator 50 may be used.

[0137] 3B and 3C show variations of the transistor 20 shown in FIGS. 1B and 1C. FIGS. 3B and 3C are cross-sectional views of the transistor 20. FIG. 3B is a cross-sectional view of the transistor 20 in the channel length direction, and FIG. 3C is a cross-sectional view of the transistor 20 in the channel width direction.

[0138] 3B and 3C includes an insulator 52 on an oxide 30. The insulator 50 is provided on the insulator 52. The insulator 52 is provided between the insulator 80 and the insulator 50.

[0139] The insulator 52 is disposed in openings formed in the insulators 80 and 75, and is in contact with the top surface of the insulator 14, the side surface of the insulator 22, the side surface of the insulator 24, the side surface of the oxide 30, the top surface of the oxide 30, the side surface of the conductor 42a, the side surface of the conductor 42b, the side surface of the insulator 75, and the side surface of the insulator 80. The insulator 50 is disposed in the opening via the insulator 52. The conductor 60 is disposed so as to fill the opening via the insulators 52 and 50. The top surface of the conductor 60 is disposed so as to be flush or approximately flush with the top surface of the insulator 80, the top of the insulator 52, and the top of the insulator 50.

[0140] A part of the insulator 52 functions as a first gate insulator. A barrier insulating film against oxygen is preferably used as the insulator 52. Any of the insulators that can be used for the insulator 82 described above may be used as the insulator 52. For example, an insulator containing an oxide of one or both of aluminum and hafnium may be used as the insulator 52. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 52. In this case, the insulator 52 is an insulator containing at least oxygen and aluminum.

[0141] The insulator 52 is provided in contact with the top and side surfaces of the oxide 30, the side surfaces of the insulator 24, the side surfaces of the insulator 22, and the top surface of the insulator 14. In other words, the regions of the oxide 30 and the insulator 24 that overlap with the conductor 60 are covered with the insulator 52 in the cross section in the channel width direction. This allows the insulator 52, which has oxygen barrier properties, to block oxygen from being released from the oxide 30 when heat treatment or the like is performed. This reduces the formation of oxygen vacancies in the oxide 30. This prevents oxygen vacancies and V formed in the region 30c from being desorbed. Ｏ H can be reduced. Therefore, the electrical characteristics of the transistor 20 can be improved, and the reliability can be improved.

[0142] Furthermore, even if an excessive amount of oxygen is contained in the insulators 80, 50, and 24, the oxygen can be prevented from being excessively supplied to the oxide 30. Therefore, it is possible to prevent the regions 30a and 30b from being excessively oxidized via the region 30c, thereby preventing a decrease in the on-state current or the field-effect mobility of the transistor 20.

[0143] 3B , the insulator 52 is provided in contact with the side surfaces of the conductor 42, the insulator 75, and the insulator 80. This prevents the side surfaces of the conductor 42 from being oxidized and an oxide film from being formed on the side surfaces. This prevents a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 20.

[0144] Furthermore, the insulator 52, together with the insulator 50 and the conductor 60, must be provided in an opening formed in the insulator 80 or the like. To miniaturize the transistor 20, it is preferable that the insulator 52 have a thin film thickness. The film thickness of the insulator 52 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that at least a portion of the insulator 52 has a region with the above-described film thickness. It is also preferable that the film thickness of the insulator 52 is thinner than the film thickness of the insulator 50. In this case, it is sufficient that at least a portion of the insulator 52 has a region with a film thickness thinner than the insulator 50.

[0145] To form the insulator 52 to a thin film thickness as described above, it is preferable to form the film using atomic layer deposition (ALD). The ALD method includes thermal ALD, in which a precursor and a reactant react using only thermal energy, and plasma enhanced ALD, in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, allowing film formation at a lower temperature.

[0146] The ALD method can deposit atoms layer by layer, and therefore has the following advantages: it is possible to form an extremely thin film, it is possible to form a film on a structure with a high aspect ratio, it is possible to form a film with few defects such as pinholes, it is possible to form a film with excellent coverage, it is possible to form a film at a low temperature, etc. Therefore, the insulator 52 can be formed with good coverage on the side surface of an opening formed in the insulator 80 or the like, and with a thin film thickness as described above.

[0147] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using SIMS, X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0148] It is preferable to perform microwave treatment in the oxygen-containing atmosphere described above after forming the insulating film that will become the insulator 52. By performing microwave treatment in an oxygen-containing atmosphere through the insulating film in this manner, oxygen can be efficiently injected into the region 30c. Furthermore, by arranging the insulator 52 so that it contacts the side surface of the conductor 42 and the surface of the region 30c, it is possible to prevent more oxygen than necessary from being injected into the region 30c and to prevent oxidation of the side surface of the conductor 42. Furthermore, it is possible to prevent oxidation of the side surface of the conductor 42 during the formation of the insulating film that will become the insulator 50. Furthermore, since the film quality of the insulator 52 can be improved, the reliability of the transistor 20 is improved.

[0149] When microwave treatment is performed after the formation of the insulating film that will become the insulator 52, the microwave treatment may or may not be performed after the formation of the insulating film that will become the insulator 50. When microwave treatment is performed after the formation of the insulating film that will become the insulator 50, the microwave treatment may or may not be performed after the formation of the insulating film that will become the insulator 52.

[0150] In addition, by appropriately adjusting the film formation conditions of the insulating film that becomes the insulator 50, the conditions of the microwave treatment in an oxygen-containing atmosphere, the amount of oxygen added to the insulator 80 by the film formation of the insulator 82, etc., the oxygen vacancies and V formed in the region 30c can be reduced. Ｏ 1B , the insulator 52 is not provided, which can simplify the manufacturing process of the transistor and improve productivity.

[0151] 3B and 3C show a configuration in which the insulator 50 and the conductor 60 are in contact with each other, but the present invention is not limited to this. For example, a configuration in which an insulator is provided between the insulator 50 and the conductor 60 may also be used.

[0152] 3D and 3E show variations of the transistor 20 shown in FIG. 3B and FIG. 3E are cross-sectional views of the transistor 20. FIG. 3D is a cross-sectional view of the transistor 20 in the channel length direction, and FIG. 3E is a cross-sectional view of the transistor 20 in the channel width direction.

[0153] 3D and 3E includes an insulator 54 over an insulator 50. The conductor 60 is provided over the insulator 54. The insulator 52 is provided between the insulator 50 and the conductor 60.

[0154] The insulator 54 is disposed in openings formed in the insulators 80 and 75, and is in contact with the insulators 50 and conductor 60. The insulator 54 is disposed in the opening via the insulators 50 and 52. The conductor 60 is disposed so as to fill the opening via the insulators 54, 50, and 52. The upper surface of the conductor 60 is disposed so as to be flush or approximately flush with the upper surface of the insulator 80, the top of the insulator 52, the top of the insulator 50, and the top of the insulator 54.

[0155] A portion of the insulator 54 functions as a first gate insulator. It is preferable to use a barrier insulating film against hydrogen and water molecules as the insulator 54. This prevents impurities such as hydrogen contained in the conductor 60 from diffusing into the insulator 50 and the oxide 30. The insulator 54 may be any of the insulators that can be used for the insulator 14 described above. For example, silicon nitride formed by the PEALD method may be used as the insulator 54. In this case, the insulator 54 is an insulator containing at least nitrogen and silicon.

[0156] Furthermore, the insulator 54 may also have a barrier property against oxygen, which can prevent oxygen contained in the insulator 50 from diffusing into the conductor 60.

[0157] Furthermore, the insulator 54, together with the insulators 52, 50, and conductor 60, must be provided in an opening formed in the insulator 80 or the like. To miniaturize the transistor 20, it is preferable that the insulator 54 have a thin film thickness. The film thickness of the insulator 54 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that at least a portion of the insulator 54 has a region with the above-described film thickness. It is also preferable that the film thickness of the insulator 54 is thinner than the film thickness of the insulator 50. In this case, it is sufficient that at least a portion of the insulator 54 has a region with a film thickness thinner than the insulator 50.

[0158] <Constituent Materials> Constituent materials that can be used for the transistor and semiconductor device of one embodiment of the present invention are described below.

[0159] <<Substrate>> The substrate on which the transistor 20 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, or the like.

[0160] <<Insulator>> Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0161] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current can occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the insulator's function.

[0162] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0163] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0164] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0165] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 30, oxygen vacancies in the oxide 30 can be compensated for.

[0166] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0167] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0168] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0169] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0170] <<Metal Oxide>> A metal oxide that functions as a semiconductor (oxide semiconductor) is preferably used as the oxide 30. Metal oxides that can be used as the oxide 30 according to the present invention will be described below.

[0171] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0172] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, an element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, the element M may be a combination of two or more of the above-mentioned elements. In particular, the element M is preferably one or more selected from gallium, aluminum, yttrium, and tin.

[0173] In particular, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) may be used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (IAGZO) may be used for the semiconductor layer of the transistor.

[0174] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0175] Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) will be described as an example of a metal oxide. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In—Ga—Zn oxide.

[0176] <Classification of Crystal Structure> Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0177] The crystalline structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incident XRD) measurement. The GIXD method is also called the thin film method or the Seemann-Bohlin method. In the following, the XRD spectrum obtained by GIXD measurement may be simply referred to as the XRD spectrum.

[0178] For example, in the case of a quartz glass substrate, the peak shape of the XRD spectrum is almost symmetrical. On the other hand, in the case of an In-Ga-Zn oxide film having a crystalline structure, the peak shape of the XRD spectrum is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0179] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, confirming that the quartz glass is in an amorphous state. Furthermore, a spot-like pattern is observed in the diffraction pattern of an In—Ga—Zn oxide film formed at room temperature, rather than a halo. For this reason, it is estimated that the In—Ga—Zn oxide formed at room temperature is neither single crystal nor polycrystalline, nor in an amorphous state, but is in an intermediate state, and it cannot be concluded that it is in an amorphous state.

[0180] <<Structure of Oxide Semiconductor>> Note that oxide semiconductors may be classified differently from the above when focusing on their structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0181] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0182] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0183] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of the crystalline region may be several tens of nanometers.

[0184] In an In—Ga—Zn oxide, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as a (Ga, Zn) layer) are stacked. Note that indium and gallium are mutually substituted. Therefore, the (Ga, Zn) layer may contain indium. The In layer may contain gallium. The In layer may contain zinc. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0185] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0186] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the spots are observed at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0187] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundary can be identified even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the a-b plane and the change in interatomic bond distance caused by metal atom substitution.

[0188] Note that a crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and are likely to trap carriers, resulting in a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming a CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0189] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities, the formation of defects, or the like, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor having the CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having the CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using the CAAC-OS in a transistor having a metal oxide in a channel formation region (sometimes referred to as an OS transistor) can increase the flexibility of the manufacturing process.

[0190] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0191] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0192] <<Structure of Oxide Semiconductor>> Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0193] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0194] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0195] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In—Ga—Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In—Ga—Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0196] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be referred to as a region whose main component is In. The second region can be referred to as a region whose main component is Ga.

[0197] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0198] Furthermore, CAC-OS in In—Ga—Zn oxide refers to a structure in which a mosaic of regions containing Ga as the main component and regions containing In as the main component are randomly arranged in a material composition containing In, Ga, Zn, and O. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0199] The CAC-OS can be formed by sputtering without heating the substrate. When forming the CAC-OS by sputtering, any one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0200] Furthermore, for example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region containing In as a main component (first region) and a region containing Ga as a main component (second region) are unevenly distributed and mixed.

[0201] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving a high field-effect mobility (μ).

[0202] On the other hand, the second region has higher insulating properties than the first region, that is, the second region being distributed in the metal oxide can suppress leakage current.

[0203] Therefore, when a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (a function of turning on / off). That is, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0204] Furthermore, a transistor using the CAC-OS has high reliability, and therefore, the CAC-OS is ideal for various semiconductor devices such as display devices.

[0205] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0206] <Transistor Having Oxide Semiconductor> Next, a case where the oxide semiconductor is used for a transistor will be described.

[0207] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0208] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 １７ cm −３ Below 1 × 10, preferably １５ cm −３ More preferably, 1×10 １３ cm −３ or less, more preferably 1 × 10 １１ cm −３ More preferably, 1×10 １０ cm−３ is less than 1×10 −９ cm −３ The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0209] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0210] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0211] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0212] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0213] When an oxide semiconductor contains silicon or carbon, which is one of Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, when the concentration of silicon or carbon in the oxide semiconductor (concentration obtained by SIMS) is set to 2×10 １８ atoms / cm ３ Below 2 × 10, preferably １７ atoms / cm ３ The following applies.

[0214] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0215] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 １９ atoms / cm ３ Less than 5×10 １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ Do the following:

[0216] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor obtained by SIMS is measured to be 1×10 ２０atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Make it less than.

[0217] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0218] <<Other Semiconductor Materials>> The oxide 30 can be rephrased as a semiconductor layer including a channel formation region of the transistor 20. Note that the semiconductor material that can be used for the semiconductor layer is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the semiconductor layer. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, or the like) is preferably used as the semiconductor material. In particular, a layered material that functions as a semiconductor is preferably used as the semiconductor material.

[0219] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0220] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0221] For example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer. Specific examples of transition metal chalcogenides that can be used for the semiconductor layer include molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0222] 4 to 6, a method for manufacturing the transistor 20 shown in FIG. 1 will be described. In each figure, A, C, E, G, and I are cross-sectional views of the transistor 20 in the channel length direction. In each figure, B, D, F, H, and J are cross-sectional views of the transistor 20 in the channel width direction.

[0223] In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed as a film by appropriately using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0224] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0225] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0226] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0227] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0228] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0229] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0230] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0231] First, a substrate (not shown) is prepared, and then a conductor 15 is formed on the substrate (see FIGS. 4A and 4B). The conductor 15 may be formed by forming an opening in an insulator (not shown) on the substrate, depositing a conductive film, and then performing CMP processing. Alternatively, the conductor 15 may be formed by processing the deposited conductive film into an island shape. Here, the island shape refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0232] Next, the insulator 14, the insulating film 22A, and the insulating film 23A are sequentially formed on the conductor 15 (see FIGS. 4A and 4B). It is preferable to form the insulator 14, the insulating film 22A, and the insulating film 23A consecutively without exposing them to the atmospheric environment. By forming the films without exposing them to the atmospheric environment, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulator 14, the insulating film 22A, and the insulating film 23A, and to keep the vicinity of the interface between the insulator 14 and the insulating film 22A and the vicinity of the interface between the insulating film 22A and the insulating film 23A clean.

[0233] The insulator 14, the insulating film 22A, and the insulating film 23A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0234] Next, an opening is formed in the insulating film 23A down to the insulating film 22A (see FIGS. 4C and 4D). The opening may be, for example, a groove or a slit. The opening may also refer to a region where an opening is formed. While wet etching may be used to form the opening, dry etching is preferred for fine processing. For the insulating film 22A, it is preferable to select an insulator that functions as an etching stopper film when etching the insulating film 23A to form the opening. For example, if silicon oxide or silicon oxynitride is used for the insulating film 23A in which the opening is formed, it is preferable to use silicon nitride, aluminum oxide, or hafnium oxide for the insulating film 22A.

[0235] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

[0236] Next, the insulating film 24A is formed (see FIGS. 4E and 4F). The insulating film 24A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a silicon oxide film is formed as the insulating film 24A by sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulating film 24A can be reduced. Since the insulating film 24A will come into contact with the oxide 30 in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0237] Next, a portion of the insulating film 24A is removed by CMP processing to expose the insulating film 23A (see FIGS. 4G and 4H). As a result, the insulating layer 24B remains only in the opening. Note that the CMP processing may remove a portion of the insulating film 23A.

[0238] Next, an oxide film 30A is formed on the insulating layer 24B and the insulating film 23A (see FIGS. 4I and 4J). The oxide film 30A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The ALD method is preferable for forming the oxide film 30A because it can form a film of uniform thickness even in a groove or opening with a large aspect ratio. The PEALD method is also preferable because it can form the oxide film 30A at a lower temperature than the thermal ALD method. In this embodiment, the oxide film 30A is formed by a sputtering method.

[0239] For example, when the oxide film 30A is formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the In-M-Zn oxide target or the like can be used.

[0240] During the deposition of the oxide film 30A, some of the oxygen contained in the sputtering gas may be supplied to the insulating layer 24B. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0241] When the oxide film 30A is formed by a sputtering method, an oxygen-excess oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 30A is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0242] In this embodiment, the oxide film 30A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1, an oxide target with an atomic ratio of In:Ga:Zn=1:1:1, an oxide target with an atomic ratio of In:Ga:Zn=1:1:1.2, or an oxide target with an atomic ratio of In:Ga:Zn=1:1:2. Each oxide film can be formed to suit the characteristics desired for the oxide 30 by appropriately selecting the film formation conditions and atomic ratio.

[0243] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the oxide film 30A does not polycrystallize, such as 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0244] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the moisture content of the gas used in the heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas to perform the heat treatment, it is possible to prevent moisture and other contaminants from being absorbed into the oxide film 30A as much as possible.

[0245] In this embodiment, the heat treatment is performed at 450° C. for one hour with a nitrogen gas to oxygen gas flow ratio of 4:1. This heat treatment using oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 30A. Reducing the impurities in the film in this manner improves the crystallinity of the oxide film 30A, resulting in a denser, more compact structure. This increases the crystalline region in the oxide film 30A, reducing the in-plane variation of the crystalline region in the oxide film 30A. This reduces the in-plane variation of the electrical characteristics of the transistor 20.

[0246] Furthermore, by performing the heat treatment, hydrogen in the insulating layer 24B and the oxide film 30A moves to the insulating film 22A and is absorbed into the insulating film 22A. In other words, hydrogen in the insulating layer 24B and the oxide film 30A diffuses into the insulating film 22A. Therefore, the hydrogen concentration in the insulating film 22A increases, but the hydrogen concentrations in the insulating layer 24B and the oxide film 30A decrease.

[0247] In particular, the insulator 24 formed by processing the insulating layer 24B functions as a gate insulator of the transistor 20, and the oxide 30 formed by processing the oxide film 30A functions as a channel formation region of the transistor 20. Therefore, the transistor 20 having the insulator 24 and oxide 30 with reduced hydrogen concentration is preferable because it has good reliability.

[0248] Next, a conductive film 42A is formed on the oxide film 30A (see FIGS. 4I and 4J). The conductive film 42A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, tantalum nitride may be formed as the conductive film 42A by sputtering. Note that heat treatment may be performed before the formation of the conductive film 42A. The heat treatment may be performed under reduced pressure, and the conductive film 42A may be formed successively without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 30A can be removed and the moisture and hydrogen concentrations in the oxide film 30A can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the heat treatment temperature is 250° C.

[0249] Next, lithography is used to process the insulating film 22A, insulating film 23A, insulating layer 24B, oxide film 30A, and conductive film 42A into island shapes to form insulators 22, 23a, 23b, insulator 24, oxide 30, and conductive layer 42B (see FIGS. 5A and 5B ). The insulator 24, oxide 30, and conductive layer 42B are formed so that at least a portion of each overlaps with the conductor 15. This processing can be performed using a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. The insulating film 22A, insulating film 23A, insulating layer 24B, oxide film 30A, and conductive film 42A may be processed under different conditions.

[0250] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Then, etching is performed through the resist mask to process a conductor, semiconductor, or insulator into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or ion beam may also be used instead of the light described above. When an electron beam or ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0251] Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as the hard mask material is formed on the conductive film 42A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of the desired shape. Etching of the conductive film 42A and the like may be performed after removing the resist mask, or may be performed while leaving the resist mask in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 42A and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0252] Next, an insulator 75 is formed to cover the insulators 22, 23a, 23b, 24, the oxide 30, and the conductive layer 42B (see FIGS. 5A and 5B ). The insulator 75 preferably contacts the top surface of the insulator 14, the side surfaces of the insulators 22, 23a, 23b, and 24. The insulator 75 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulator 75 is preferably an insulating film that suppresses oxygen permeation. For example, the insulator 75 may be formed of silicon nitride using the PEALD method. This configuration can suppress oxygen diffusion. Alternatively, the insulator 75 may be formed of aluminum oxide using the sputtering method, and then a silicon nitride film may be formed thereon using the PEALD method. By forming the insulator 75 in such a layered structure, the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen may be improved.

[0253] In this way, the oxide 30 and the conductive layer 42B can be covered with the insulator 75, which has a function of suppressing the diffusion of oxygen. This makes it possible to reduce the direct diffusion of oxygen from the insulator 80 or the like into the oxide 30 and the conductive layer 42B in a later process.

[0254] Next, an insulating film to be the insulator 80 is formed on the insulator 75. The insulating film can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be formed by sputtering. The insulating film can be formed by sputtering in an oxygen-containing atmosphere to form the insulator 80 containing excess oxygen. Furthermore, the hydrogen concentration in the insulator 80 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Heat treatment may be performed before the formation of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 75 can be removed, and the moisture and hydrogen concentrations in the oxide 30 and the insulator 24 can be further reduced. The heat treatment conditions described above can be used for the heat treatment.

[0255] Next, the insulating film that will become the insulator 80 is subjected to CMP treatment to form the insulator 80 with a flat upper surface (see FIGS. 5A and 5B). Alternatively, a silicon nitride film may be formed on the insulator 80 by, for example, a sputtering method, and the CMP treatment may be performed on the silicon nitride until it reaches the insulator 80.

[0256] Next, a portion of the insulator 80, a portion of the insulator 75, and a portion of the conductive layer 42B are processed to form an opening that reaches the oxide 30. The opening is preferably formed so as to overlap the conductor 15. By forming the opening, the conductors 42a and 42b are formed (see FIGS. 5C and 5D). Although not shown in FIGS. 5C and 5D, the upper portion of the oxide 30 may be removed when the opening is formed.

[0257] Furthermore, a portion of the insulator 80, a portion of the insulator 75, and a portion of the conductive layer 42B can be processed by dry etching or wet etching. Dry etching is suitable for fine processing. These processes may be performed under different conditions. For example, a portion of the insulator 80 may be processed by dry etching, a portion of the insulator 75 may be processed by wet etching, and a portion of the conductive layer 42B may be processed by dry etching.

[0258] Here, impurities may adhere to the top and side surfaces of the oxide 30, the side surfaces of the conductor 42, the side surfaces of the insulator 80, etc., or may diffuse into these surfaces. A process for removing such impurities may be performed. Furthermore, the dry etching may result in damaged regions being formed on the surface of the oxide 30. Such damaged regions may be removed. Examples of such impurities include those originating from components contained in the insulator 80, the insulator 75, and the conductive layer 42B, components contained in the materials used in the device used to form the opening, and components contained in the gas or liquid used in etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0259] In particular, impurities such as aluminum and silicon may reduce the crystallinity of the oxide 30. Therefore, it is preferable to remove impurities such as aluminum and silicon from the surface of the oxide 30 and its vicinity. It is also preferable to reduce the concentration of these impurities. For example, the concentration of aluminum atoms on the surface of the oxide 30 and its vicinity may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0260] In addition, in the region where the crystallinity of the oxide 30 is low due to impurities such as aluminum and silicon, the density of the crystal structure is reduced. Ｏ A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the region of low crystallinity in the oxide 30 is reduced or removed.

[0261] In contrast, it is preferable that the oxide 30 has a CAAC structure. In particular, it is preferable that the oxide 30 has a CAAC structure up to the bottom end of the drain. Here, in the transistor 20, the conductor 42a or conductor 42b and its vicinity function as the drain. In other words, it is preferable that the oxide 30 near the bottom end of the conductor 42a (conductor 42b) has a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the low-crystalline region of the oxide 30 is removed, and by having a CAAC structure, fluctuations in the electrical characteristics of the transistor 20 can be further suppressed. Furthermore, the reliability of the transistor 20 can be improved.

[0262] A cleaning process is performed to remove impurities and the like that have adhered to the surface of the oxide 30 during the etching process. Cleaning methods include wet cleaning using a cleaning solution (also called wet etching), plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0263] Wet cleaning may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0264] In this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration, temperature, etc. of the aqueous solution may be adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0265] In addition, it is preferable to use a frequency of 200 kHz or more, preferably 900 kHz or more, for ultrasonic cleaning, since the use of such a frequency can reduce damage to the oxide 30 and the like.

[0266] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0267] In this embodiment, the cleaning process is performed by wet cleaning using diluted ammonia water. By performing this cleaning process, impurities attached to the surface of the oxide 30 or diffused inside can be removed. Furthermore, the crystallinity of the oxide 30 can be improved.

[0268] A heat treatment may be performed after the etching or cleaning. The heat treatment may be performed at a temperature of 100°C or higher and 450°C or lower, preferably 350°C or higher and 400°C or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 30, thereby reducing oxygen vacancies. Furthermore, such heat treatment can improve the crystallinity of the oxide 30. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, a heat treatment in a nitrogen atmosphere may be performed consecutively without exposure to the air.

[0269] Next, the insulating film 50A is formed (see FIGS. 5E and 5F). A heat treatment may be performed before the formation of the insulating film 50A. The heat treatment may be performed under reduced pressure, and the insulating film 50A may be formed immediately after the formation of the insulating film 50A without exposure to the atmosphere. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 30 can be removed, and the moisture and hydrogen concentrations in the oxide 30 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0270] The insulating film 50A can be formed by a sputtering method, a CVD method, a PECVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 50A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration in the insulating film 50A to be reduced. In this embodiment, silicon oxynitride is formed as the insulating film 50A by a PECVD method.

[0271] Next, it is preferable to carry out microwave treatment in an atmosphere containing oxygen.

[0272] The microwave treatment preferably uses a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device may be 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz. The use of high-density plasma can generate high-density oxygen radicals. The power of the power supply that applies microwaves to the microwave treatment device may be 1000 W or more and 10,000 W or less, preferably 2000 W or more and 5,000 W or less. The microwave treatment device may also have a power supply that applies RF to the substrate side. By applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the oxide 30.

[0273] The microwave treatment is preferably carried out under reduced pressure, with the pressure being 10 Pa to 1000 Pa, preferably 300 Pa to 700 Pa. The treatment temperature is 750°C or less, preferably 500°C or less, for example, about 400°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. For example, the temperature may be 100°C to 750°C, preferably 300°C to 500°C.

[0274] For example, the microwave treatment may be performed using oxygen gas and argon gas. ２ / (O ２+Ar)) may be greater than 0% and less than 100%, preferably greater than 0% and less than 50%, more preferably 10% to 40%, and even more preferably 10% to 30%.

[0275] In microwave treatment, thermal energy may be transferred directly to the oxide 30 due to electromagnetic interaction between the microwaves and molecules in the oxide 30. This thermal energy may heat the oxide 30. Such a heat treatment may be called microwave annealing. By performing microwave treatment in an oxygen-containing atmosphere, an effect equivalent to that of oxygen annealing may be obtained. Furthermore, if the oxide 30 contains hydrogen, it is thought that this thermal energy is transferred to the hydrogen in the oxide 30, thereby activating and releasing the hydrogen from the oxide 30.

[0276] Next, the conductive film 60A is formed. The conductive film 60A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. When the conductor 60 has a two-layer laminated structure, the method of forming the conductive film that becomes the conductor 60 can be referred to in the description of the second embodiment described later.

[0277] Next, the insulating film 50A and the conductive film 60A are polished by CMP until the insulator 80 is exposed, thereby forming the insulator 50 and the conductor 60 (see FIGS. 5G and 5H). As a result, the insulator 50 is disposed so as to cover the opening that reaches the oxide 30. The conductor 60 is disposed so as to fill the opening via the insulator 50.

[0278] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. This heat treatment can reduce the moisture and hydrogen concentrations in the insulator 50 and the insulator 80. Note that after the heat treatment, the insulator 82 may be formed without exposure to the air.

[0279] Next, an insulator 82 is formed on the insulator 50, the conductor 60, and the insulator 80 (see FIGS. 1B and 1C). The insulator 82 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 82 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulator 82 can be reduced.

[0280] In this embodiment, an aluminum oxide film is formed by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas as the insulator 82. By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0281] Furthermore, by depositing the insulator 82 in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulator 80 during deposition. This allows excess oxygen to be contained in the insulator 80. In this case, it is preferable to deposit the insulator 82 while heating the substrate.

[0282] Through the above steps, the transistor 20 shown in FIGS. 1A to 1C can be manufactured.

[0283] The method for forming the insulating film 23A and the insulating layer 24B is not limited to the above. Another method for forming the insulating film 23A and the insulating layer 24B will be described below with reference to FIG.

[0284] First, the conductor 15, the insulator 14, and the insulating film 22A are formed on a substrate (not shown). The above description can be referred to for the methods of forming the conductor 15, the insulator 14, and the insulating film 22A.

[0285] Next, an insulating film that will become the insulating layer 24B is formed on the insulating film 22A. Next, the insulating film is processed by lithography to form the insulating layer 24B (see FIGS. 6A and 6B). At this time, a part of the insulating film 22A that does not overlap with the insulating layer 24B may be removed.

[0286] Next, the insulating film 23f is formed on the insulating film 22A and the insulating layer 24B (see FIGS. 6C and 6D). Note that the above description can be referred to for the method of forming the insulating film 23f.

[0287] Next, a part of the insulating film 23f is removed by CMP to expose the insulating layer 24B (see FIGS. 6E and 6F).By this CMP, an insulating film 23A is formed.

[0288] In this way, the insulating film 23A and the insulating layer 24B can be formed.

[0289] <Microwave Processing Apparatus> A microwave processing apparatus that can be used in manufacturing methods for a transistor, a semiconductor device, a memory device, and the like will be described below.

[0290] First, the configuration of a manufacturing apparatus that reduces the inclusion of impurities during the manufacturing of transistors, semiconductor devices, and the like will be described with reference to FIGS.

[0291] 7 is a schematic top view of a single-wafer processing multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 has an atmosphere-side substrate supply chamber 2701 equipped with a cassette port 2761 for accommodating substrates and an alignment port 2762 for aligning the substrates, an atmosphere-side substrate transfer chamber 2702 for transferring substrates from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703a for loading substrates and for switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading substrates and for switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring substrates in a vacuum, and chambers 2706a, 2706b, 2706c, and 2706d.

[0292] The atmospheric side substrate transfer chamber 2702 is connected to a load lock chamber 2703a and an unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to a transfer chamber 2704, and the transfer chamber 2704 is connected to chambers 2706a, 2706b, 2706c, and 2706d.

[0293] A gate valve GV is provided at the connection between each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702. A transfer robot 2763a is provided in the atmosphere-side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. Substrates can be transferred within the manufacturing apparatus 2700 by the transfer robots 2763a and 2763b.

[0294] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 −４ Pa or less, preferably 3×10 −５ Pa or less, more preferably 1×10 −５ The partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 −５ Pa or less, preferably 1×10 −５ Pa or less, more preferably 3×10 −６ The partial pressure of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 −５ Pa or less, preferably 1×10 −５ Pa or less, more preferably 3×10 −６ The partial pressure of gas molecules (atoms) with m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 −５ Pa or less, preferably 1×10 −５ Pa or less, more preferably 3×10 −６ Pa or less.

[0295] The total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using an ionization vacuum gauge, a mass spectrometer, or the like.

[0296] It is also desirable that the transfer chamber 2704 and each chamber have a configuration with little external or internal leakage. For example, the leak rate of the transfer chamber 2704 is 1×10 ０ Pa / min or less, preferably 5 x 10 −１The leak rate of each chamber is 1 x 10 −１ Pa / min or less, preferably 5 x 10 −２ Pa / min or less.

[0297] The leak rate may be derived from the total pressure and partial pressure measured using an ionization vacuum gauge, mass spectrometer, or the like. For example, it may be derived from the total pressure 10 minutes after starting evacuation using a vacuum pump such as a turbomolecular pump, and the total pressure 10 minutes after closing the valve. The total pressure 10 minutes after starting evacuation may be the average value of multiple measurements of the total pressure.

[0298] The leak rate depends on external and internal leaks. External leaks are gases that enter from outside the vacuum system due to tiny holes, poor seals, etc. Internal leaks are caused by leaks from partitions such as valves within the vacuum system or gases released from internal components. To keep the leak rate below the above figures, measures must be taken to prevent both external and internal leaks.

[0299] For example, it is advisable to seal the opening and closing portions of the transfer chamber 2704 and each chamber with a metal gasket. It is preferable to use a metal gasket coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. Furthermore, by using a passivated metal coated with iron fluoride, aluminum oxide, chromium oxide, or the like, the release of gas containing impurities from the metal gasket can be suppressed, thereby reducing internal leakage.

[0300] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit little impurity-containing gases, are used as components constituting the manufacturing apparatus 2700. Furthermore, the aforementioned metals that emit little impurity-containing gases may be coated on alloys containing iron, chromium, nickel, and the like. Alloys containing iron, chromium, nickel, and the like are rigid, heat-resistant, and suitable for processing. Here, reducing the surface roughness of the components by polishing or the like to reduce the surface area can reduce the amount of emitted gases.

[0301] Alternatively, the components of the manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0302] It is preferable that the components of the manufacturing apparatus 2700 be constructed solely from metal as much as possible, and even if a viewing window made of quartz or the like is installed, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide or the like to suppress gas emissions.

[0303] The adsorbed substances present in the transfer chamber 2704 and each chamber are adsorbed to the inner walls and do not affect the pressure of the transfer chamber 2704 or each chamber. However, they can cause gas emissions when the transfer chamber 2704 or each chamber is evacuated. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump with high exhaust capacity to desorb as much adsorbed substances as possible from the transfer chamber 2704 and each chamber and evacuate them in advance. To promote the desorption of adsorbed substances, the transfer chamber 2704 and each chamber may be baked. Baking can increase the desorption rate of adsorbed substances by approximately 10 times. Baking can be performed at a temperature of 100°C or higher and 450°C or lower. In this case, introducing an inert gas into the transfer chamber 2704 and each chamber while removing the adsorbed substances can further increase the desorption rate of water and other substances that are difficult to desorb by exhaust alone. Heating the introduced inert gas to the same temperature as the baking temperature can further increase the desorption rate of adsorbed substances. Here, a rare gas is preferably used as the inert gas.

[0304] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as a heated rare gas or oxygen, and then evacuating the transfer chamber 2704 and each chamber again after a certain period of time has elapsed. The introduction of heated gas can desorb adsorbates from the transfer chamber 2704 and each chamber, thereby reducing impurities present in the transfer chamber 2704 and each chamber. It is effective to repeat this process two to 30 times, preferably five to 15 times. Specifically, by introducing an inert gas or oxygen at a temperature of 40°C to 400°C, preferably 50°C to 200°C, the pressure in the transfer chamber 2704 and each chamber can be increased to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa, and the pressure can be maintained for a period of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Thereafter, the transfer chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0305] Next, the chamber 2706b and the chamber 2706c will be described with reference to the schematic cross-sectional view shown in FIG.

[0306] Chamber 2706b and chamber 2706c are chambers capable of, for example, performing microwave treatment on a workpiece. Note that chamber 2706b and chamber 2706c differ only in the atmosphere during microwave treatment. Since the other configurations are common, they will be described together below.

[0307] Chamber 2706b and chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Also, outside chamber 2706b and chamber 2706c, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided.

[0308] The high-frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with a dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is sent to chambers 2706b and 2706c through a gas pipe 2806 passing through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 has the function of evacuating gases and the like from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to a substrate holder 2812 via a matching box 2815.

[0309] The substrate holder 2812 has a function of holding the substrate 2811. For example, it has a function of electrostatically or mechanically chucking the substrate 2811. It also has a function as an electrode to which power is supplied from a high-frequency power supply 2816. It also has an internal heating mechanism 2813 and has a function of heating the substrate 2811.

[0310] For example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used as the vacuum pump 2817. A cryotrap may also be used in addition to the vacuum pump 2817. The use of a cryopump or a cryotrap is particularly preferable because water can be efficiently evacuated.

[0311] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like for heating. Alternatively, a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas may be used for heating. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heat treatment using a high-temperature gas. An inert gas is used as the gas.

[0312] The gas supply source 2801 may be connected to a refiner via a mass flow controller. The gas used preferably has a dew point of −80° C. or lower, preferably −100° C. or lower. For example, oxygen gas, nitrogen gas, or a rare gas (such as argon gas) may be used.

[0313] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria). Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of, for example, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Because the dielectric plate 2809 is exposed to a particularly high-density region of the high-density plasma 2810 described below, providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0314] The high-frequency generator 2803 has a function of generating microwaves of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to a mode converter 2805 via a waveguide 2804. The mode converter 2805 converts the microwaves transmitted in TE (Transverse Electric) mode into TEM (Transverse Electric and Magnetic) mode. The microwaves are then transmitted to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 has a plurality of slot holes, and the microwaves pass through the slot holes and a dielectric plate 2809. An electric field is then generated below the dielectric plate 2809, generating a high-density plasma 2810. The high density plasma 2810 contains ions and radicals according to the type of gas supplied from the gas supply source 2801. For example, oxygen radicals and the like are present.

[0315] At this time, ions and radicals generated in the high-density plasma 2810 can modify a film or the like on the substrate 2811. It may be preferable to apply a bias to the substrate 2811 side using a high-frequency power supply 2816. For example, an RF (Radio Frequency) power supply with a frequency of 13.56 MHz, 27.12 MHz, or the like may be used as the high-frequency power supply 2816. Applying a bias to the substrate side allows ions in the high-density plasma 2810 to efficiently reach the depths of openings in a film or the like on the substrate 2811.

[0316] For example, oxygen radical treatment can be performed using high density plasma 2810 by introducing oxygen from a gas supply source 2801 into the chamber 2706b or the chamber 2706c.

[0317] Next, the chamber 2706a and the chamber 2706d will be described with reference to the schematic cross-sectional view shown in FIG.

[0318] Chamber 2706a and chamber 2706d are chambers capable of irradiating an object to be treated with electromagnetic waves, for example. The only difference between chamber 2706a and chamber 2706d is the type of electromagnetic wave. Since the other configurations are largely common, they will be described together below.

[0319] The chamber 2706a and the chamber 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. In addition, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the chamber 2706a and the chamber 2706d.

[0320] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. The lamp 2820 is disposed opposite a substrate holder 2825. The substrate holder 2825 has a function of holding a substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 and has a function of heating the substrate 2824.

[0321] A light source capable of emitting electromagnetic waves such as visible light or ultraviolet light may be used as the lamp 2820. For example, a light source capable of emitting electromagnetic waves having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0322] For example, the lamp 2820 may be a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp.

[0323] For example, the electromagnetic waves emitted from the lamps 2820 can be partially or completely absorbed by the substrate 2824, thereby modifying a film on the substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. Note that if the process is performed while the substrate 2824 is heated, defects can be generated or reduced, or impurities can be removed efficiently.

[0324] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have the heating mechanism 2826 inside.

[0325] For the vacuum pump 2828, refer to the description of the vacuum pump 2817. For the heating mechanism 2826, refer to the description of the heating mechanism 2813. For the gas supply source 2821, refer to the description of the gas supply source 2801.

[0326] The microwave processing apparatus that can be used in this embodiment is not limited to the above. A microwave processing apparatus 2900 shown in FIG. 10 can be used. The microwave processing apparatus 2900 includes a quartz tube 2901, an exhaust port 2819, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas pipe 2806, a vacuum pump 2817, and a valve 2818. The microwave processing apparatus 2900 also includes a substrate holder 2902 that holds a plurality of substrates 2811 (2811_1 to 2811_n, where n is an integer of 2 or more) inside the quartz tube 2901. The microwave processing apparatus 2900 may also include a heating unit 2903 outside the quartz tube 2901.

[0327] Microwaves generated by a high-frequency generator 2803 are irradiated onto a substrate provided in a quartz tube 2901 via a waveguide 2804. A vacuum pump 2817 is connected to an exhaust port 2819 via a valve 2818, and the pressure inside the quartz tube 2901 can be adjusted. A gas supply source 2801 is connected to a gas pipe 2806 via a valve 2802, and a desired gas can be introduced into the quartz tube 2901. A heating means 2903 can heat the substrate 2811 in the quartz tube 2901 to a desired temperature. Alternatively, the heating means 2903 may heat the gas supplied from the gas supply source 2801. The microwave processing device 2900 can simultaneously perform a heat treatment and a microwave treatment on the substrate 2811. Alternatively, the microwave treatment can be performed after the substrate 2811 is heated. Alternatively, a heat treatment can be performed on the substrate 2811 after the microwave treatment.

[0328] The substrates 2811_1 to 2811_n may all be processing substrates for forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates. For example, the substrates 2811_1 and 2811_n may be dummy substrates, and the substrates 2811_2 to 2811_n-1 may be processing substrates. Alternatively, the substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be dummy substrates, and the substrates 2811_3 to 2811_n-2 may be processing substrates. Using dummy substrates is preferable because multiple processing substrates can be uniformly processed during microwave processing or heat treatment, reducing variations between processing substrates. For example, placing a dummy substrate on the processing substrate closest to the high-frequency generator 2803 and the waveguide 2804 is preferable because it prevents the processing substrate from being directly exposed to microwaves.

[0329] By using the above manufacturing apparatus, it is possible to modify the film while suppressing the inclusion of impurities in the processed object.

[0330] 11A and 11B show a configuration example different from the above-described transistor 20. Fig. 11A is a cross-sectional view of the transistor 20A in the channel length direction, and Fig. 11B is a cross-sectional view of the transistor 20A in the channel width direction.

[0331] The transistor 20A differs from the transistor 20 mainly in that the transistor 20A has an insulator 83 on an insulator 82. The following mainly describes the differences from the above-described configuration example 1, and omits a description of the overlapping parts.

[0332] The insulator 83 is arranged to contact the top surface of the insulator 14, the side surface of the insulator 75, the side surface of the insulator 80, the side surface of the insulator 82, and the top surface of the insulator 82. With this configuration, the insulator 80 is disposed within the area sealed by the insulators 83 and 14. Here, the insulator 83 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the sealed area. With this configuration, impurities such as water and hydrogen contained outside the sealed area can be suppressed from mixing into the sealed area. Therefore, impurities such as water and hydrogen can be suppressed from mixing into the insulator 80. Furthermore, impurities such as water and hydrogen can be suppressed from mixing into the oxide 30 via the insulator 80.

[0333] The insulator 83 can be an insulator applicable to the insulators 14 and 75. For example, it is preferable to use silicon nitride, which has a higher hydrogen barrier property, as the insulator 83. In this case, the insulator 83 is an insulator containing at least nitrogen and silicon.

[0334] 11C and 11D show a configuration example different from the above-described transistor 20A. Fig. 11C is a cross-sectional view of the transistor 20B in the channel length direction, and Fig. 11D is a cross-sectional view of the transistor 20B in the channel width direction.

[0335] Transistor 20B differs from transistor 20A mainly in that conductor 15 is provided between insulator 22 and insulator 24. In the following, differences from configuration example 2 described above will be mainly described, and overlapping portions will not be described.

[0336] The conductor 15 is disposed between the insulator 22 and the insulator 24. The conductor 15 is also disposed between the insulator 23a and the insulator 23b. In other words, in a cross-sectional view in the channel length direction, the end of the conductor 15 and the end of the insulator 24 coincide or approximately coincide.

[0337] With the above configuration, the conductor 15 is disposed within the area sealed by the insulators 75 and 14. Therefore, impurities such as water and hydrogen can be prevented from being mixed into the conductor 15.

[0338] 11D, the conductor 15 has regions in contact with the insulator 24 and the insulator 50. Therefore, the conductor 15 is preferably provided as a two-layer laminated structure, and the layer in contact with the insulator 24 and the insulator 50 is preferably formed using a conductive material that has the function of suppressing oxygen diffusion. This configuration can suppress oxidation of the layer in contact with the insulator 22, which would otherwise cause a decrease in conductivity. The conductor 15 may be provided as a single layer or as a laminated structure of three or more layers.

[0339] 11D , the conductor 15 extends in the channel width direction and also functions as a wiring. In a cross-sectional view in the channel width direction, the side surface of the conductor 15 may coincide or approximately coincide with the side surface of the insulator 24. In this case, a conductor functioning as a wiring may be provided below the conductor 15, and the conductor 15 may be electrically connected to the conductor 15.

[0340] 12A and 12B show a configuration example different from the above-described transistor 20A. Fig. 12A is a cross-sectional view of a transistor 20C in the channel length direction, and Fig. 12B is a cross-sectional view of the transistor 20C in the channel width direction.

[0341] The transistor 20C differs from the transistor 20A mainly in that a portion of the top surface of the insulator 22 is in contact with the insulator 75. Hereinafter, differences from the above-described configuration example 2 will be mainly described, and descriptions of overlapping parts will be omitted.

[0342] 12A, the insulator 22 is provided so as to extend also in a region outside the ends of the insulators 23a and 23b in the channel length direction, which allows the insulator 22 to function as an etching stopper film when the insulators 23a and 23b are formed by processing the insulating film 23A using a lithography method.

[0343] Furthermore, when a metal oxide having an amorphous structure is used as the insulator 22, the amount of hydrogen that can be captured or fixed can be increased by increasing the area of ​​the insulator 22 in a top view, thereby reducing the hydrogen concentration in the insulator 24 and the oxide 30.

[0344] 12C and 12D show a configuration example different from the above-described transistor 20C. Fig. 12C is a cross-sectional view of the transistor 20D in the channel length direction, and Fig. 12D is a cross-sectional view of the transistor 20D in the channel width direction.

[0345] Transistor 20D differs from transistor 20C mainly in that it has insulator 16 and that conductor 15 is provided between insulator 14 and insulator 22. In the following, differences from configuration example 4 described above will be mainly described, and overlapping portions will not be described.

[0346] 12C , conductor 15 and insulator 16 are provided on insulator 14, and insulator 22 is provided on conductor 15 and insulator 16. Furthermore, conductor 15 is disposed so as to be embedded in insulator 16. With this configuration, conductor 15 is disposed within a region sealed by insulators 75 and 14. Therefore, impurities such as water and hydrogen can be prevented from entering conductor 15.

[0347] The insulator 16 functions as an interlayer film. Therefore, it is preferable that the insulator 16 has a lower dielectric constant than the insulator 14. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. The insulator 16 is preferably formed using an insulating material that can be used for the insulator 80.

[0348] 12C, the conductor 15 has a region in contact with the insulator 16. Therefore, the conductor 15 is preferably provided as a two-layer laminated structure, and the layer in contact with the insulator 16 is preferably formed using a conductive material that has the function of suppressing oxygen diffusion. This configuration can suppress oxidation of the layer not in contact with the insulator 16, which would otherwise cause a decrease in conductivity. The conductor 15 may be provided as a single layer or as a laminated structure of three or more layers.

[0349] 13A and 13B show a configuration example different from the above-described transistor 20A. Fig. 13A is a cross-sectional view of a transistor 20E in the channel length direction, and Fig. 13B is a cross-sectional view of the transistor 20E in the channel width direction.

[0350] The transistor 20E differs from the transistor 20A mainly in that the insulator 24 has a protruding portion. In the following, differences from the above-described configuration example 2 will be mainly described, and a description of overlapping parts will be omitted.

[0351] The insulator 24 has a convex portion in the region overlapping with the oxide 30 and the conductor 60. The convex portion is located between the insulator 23a and the insulator 23b. The insulator 24 also has a region in contact with the insulator 75. The top of the insulator 24 is flush or approximately flush with the upper surfaces of the insulators 23a and 23b.

[0352] The insulators 23a and 23b are disposed on the insulator 24. That is, a portion of the insulator 24 is located between the insulator 23a or the insulator 23b and the insulator 22. The insulator 24 also has regions that overlap with the insulators 23a and 23b, respectively.

[0353] The above configuration increases the area of ​​the insulator 22 in a top view and increases the amount of excess oxygen contained in the insulator 24. Furthermore, by providing the insulators 23a and 23b so as to overlap the source and drain regions of the oxide 30, oxygen can be efficiently supplied to the channel formation region of the oxide 30 via the protruding portions of the insulator 24.

[0354] 13A shows a configuration in which the end of the insulator 24 and the end of the insulator 22 are aligned or approximately aligned, but the present invention is not limited to this. The insulator 22 may also extend in a region outside the end of the insulator 24.

[0355] 13C and 13D show a configuration example different from the above-described transistor 20E. Fig. 13C is a cross-sectional view of the transistor 20F in the channel length direction, and Fig. 13D is a cross-sectional view of the transistor 20F in the channel width direction.

[0356] Transistor 20F differs from transistor 20E mainly in that insulators 22 and 24 extend to contact insulator 83, and insulator 75 has opening 91. The following mainly describes the differences from configuration example 6 described above, and omits a description of overlapping parts.

[0357] The insulators 22 and 24 extend beyond the ends of the insulators 23a and 23b, so that portions of the insulators 22 and 24 are located between the insulator 75 and the insulator 14. The insulators 22 and 24 also have regions in contact with the insulator 83.

[0358] The insulator 75 has a region in contact with the insulator 24 in a region that does not overlap with the oxide 30. The insulator 75 also has an opening 91 in a region that does not overlap with the oxide 30. Note that the openings 91 shown by the dashed dotted lines in FIG. 13C are provided in the region between the insulator 23a and the insulator 83 and in the region between the insulator 23b and the insulator 83. The insulator 80 contacts the insulator 24 through the opening 91. With this configuration, oxygen contained in the insulator 80 can be supplied to the channel formation region of the oxide 30 through the opening 91 and the insulator 24. That is, oxygen contained in the insulator 80 can be supplied to the channel formation region of the oxide 30 in the channel width direction and the channel length direction of the transistor 20F.

[0359] According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a transistor with high reliability can be provided. Alternatively, according to one embodiment of the present invention, a transistor with good electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a novel transistor can be provided.

[0360] The structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment or structures and methods described in other embodiments.

[0361] Embodiment 2 In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS. 14A to 31C.

[0362] <Structural Example of Semiconductor Device> The structure of a semiconductor device including a transistor 200 will be described with reference to FIG. 14 . FIGS. 14A to 14D are top views and cross-sectional views of a semiconductor device including a transistor 200. FIG. 14A is a top view of the semiconductor device. FIGS. 14B to 14D are cross-sectional views of the semiconductor device. FIG. 14B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 14A , which is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 14C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 14A , which is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 14D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 14A . Note that some elements are omitted from the top view of FIG. 14A for clarity.

[0363] A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, an insulator 283 over the insulator 282, an insulator 274 over the insulator 283, and insulators 285 over the insulators 283 and 274. The insulators 212, 214, 280, 282, 283, 285, and 274 function as interlayer films. The semiconductor device also includes a conductor 240 (conductor 240a and 240b) electrically connected to the transistor 200 and functioning as a plug. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with a side surface of the conductor 240 functioning as a plug. Conductors 246 (conductors 246a and 246b) that are electrically connected to the conductor 240 and function as wiring are provided on the insulator 285 and the conductor 240. The insulator 283 is in contact with a part of the top surface of the insulator 214, the side surface of the insulator 222, the side surface of the insulator 275, the side surface of the insulator 280, and the side surface and top surface of the insulator 282.

[0364] Insulator 241a is provided in contact with the inner walls of the openings of insulators 280, 282, 283, and 285, and conductor 240a is provided in contact with the side surface of insulator 241a. Insulator 241b is provided in contact with the inner walls of the openings of insulators 280, 282, 283, and 285, and conductor 240b is provided in contact with the side surface of insulator 241b. Note that insulator 241 has a structure in which a first insulator is provided in contact with the inner wall of the opening, and a second insulator is provided further inward. Note that conductor 240 has a structure in which a first conductor is provided in contact with the side surface of insulator 241, and a second conductor is provided further inward. Here, the height of the top surface of conductor 240 and the height of the top surface of insulator 285 in the region overlapping with conductor 246 can be made approximately the same.

[0365] Although the transistor 200 illustrates a structure in which the first insulator of the insulator 241 and the second insulator of the insulator 241 are stacked, the present invention is not limited to this. For example, the insulator 241 may be provided as a single layer or a stacked structure of three or more layers. Furthermore, the transistor 200 illustrates a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, but the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. When a structure has a stacked structure, ordinal numbers may be assigned to indicate the order of formation to distinguish the structures.

[0366] [Transistor 200] As shown in FIGS. 14A to 14D , the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, insulators 224, 223a, and 223b on the insulator 222, an oxide 230 on the insulator 224, the insulator 223a, and the insulator 223b, a conductor 242a on the oxide 230, and an insulator 271a on the conductor 242a. The oxide 230 includes a conductor 242b on the oxide 230, an insulator 271b on the conductor 242b, an insulator 252 on the oxide 230, an insulator 250 on the insulator 252, an insulator 254 on the insulator 250, a conductor 260 (conductor 260a and conductor 260b) located on the insulator 254 and overlapping with part of the oxide 230, and an insulator 275 arranged on the insulators 222, 224, 223a, 223b, the oxide 230, the conductor 242a, the conductor 242b, the insulator 271a, and the insulator 271b. 14B and 14C , insulator 252 contacts the top surface of insulator 222, the side surface of insulator 224, the side surface and top surface of oxide 230, the side surface of conductor 242, the side surface of insulator 271, the side surface of insulator 275, the side surface of insulator 280, and the bottom surface of insulator 250. Furthermore, the top surface of conductor 260 is positioned so that its height is coincident or approximately coincident with the top of insulator 254, the top of insulator 250, the top of insulator 252, and the top surface of insulator 280. Furthermore, insulator 282 contacts at least a portion of the top surfaces of conductor 260, insulator 252, insulator 250, insulator 254, and insulator 280. Insulator 283 contacts the side surface of insulator 216.

[0367] In the following, the insulators 223a and 223b may be collectively referred to as the insulators 223. The conductors 242a and 242b may be collectively referred to as the conductors 242. The insulators 271a and 271b may be collectively referred to as the insulators 271.

[0368] Openings reaching the oxide 230 are provided in the insulator 280 and the insulator 275. The insulators 252, 250, 254, and the conductor 260 are arranged in the openings. In addition, the conductor 260, the insulator 252, the insulator 250, and the insulator 254 are provided between the insulator 271a and the conductor 242a and between the insulator 271b and the conductor 242b in the channel length direction of the transistor 200. The insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260.

[0369] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulators 252, 250, and 254 function as first gate insulators, and the insulators 222 and 224 function as second gate insulators. The gate insulators may also be referred to as a gate insulating layer or a gate insulating film. The conductor 242a functions as one of a source electrode and a drain electrode, and the conductor 242b functions as the other of the source electrode and the drain electrode. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region. The insulator 216 functions as an interlayer film.

[0370] 15A shows an enlarged view of the channel formation region and its vicinity in FIG. 14B. As shown in FIG. 15A, the oxide 230 includes a region 230c that functions as a channel formation region of the transistor 200, and regions 230a and 230b that are provided on either side of the region 230c and function as source and drain regions of the transistor 200.

[0371] The oxide 230 corresponds to the oxide 30 described in the previous embodiment. The region 230c corresponds to the region 30c described in the previous embodiment. The regions 230a and 230b correspond to the regions 30a and 30b described in the previous embodiment, respectively. Therefore, for details of the regions of the oxide 230 (such as the region 230c, the region 230a, and the region 230b), the contents described in the first embodiment can be referred to.

[0372] In the transistor 200, a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 including the channel formation region. For example, a metal oxide that can be used for the oxide 30 described in the above embodiment can be used for the oxide 230. The description in Embodiment 1 can be referred to for the structure of the oxide 230.

[0373] 14C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230 and the top surface of the oxide 230. In other words, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0374] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230 in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. By using such a shape, the coverage of the oxide 230 by the insulators 252, 250, 254, and conductor 260 can be improved.

[0375] 14C and other figures, by providing an insulator 252 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 230, indium contained in the oxide 230 may be unevenly distributed at and near the interface between the oxide 230 and the insulator 252. As a result, the atomic ratio near the surface of the oxide 230 becomes similar to that of indium oxide or In—Zn oxide. The increase in the atomic ratio of indium in the oxide 230, particularly near the surface of the oxide 230, can improve the field-effect mobility of the transistor 200.

[0376] At least one of the insulators 212, 214, 271, 275, 282, 283, and 285 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing into the transistor 200 from the substrate side or from above the transistor 200. Therefore, at least one of the insulators 212, 214, 271, 275, 282, 283, and 285 preferably suppresses diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (i.e., impurities are less likely to permeate through it), or that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., oxygen is less likely to permeate through it).

[0377] For the insulators 212, 214, 271, 275, 282, 283, and 285, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has a higher hydrogen barrier property, for the insulators 212, 275, and 283. Furthermore, it is preferable to use aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen, for the insulators 214, 271, 282, and 285. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, impurities such as water and hydrogen can be prevented from diffusing toward the transistor 200 from an interlayer insulating film disposed outside the insulator 285. Alternatively, oxygen contained in the insulator 224 or the like can be prevented from diffusing toward the substrate through the insulators 212 and 214. Alternatively, oxygen contained in the insulator 280 or the like can be prevented from diffusing upward from the transistor 200 through the insulator 282 or the like. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 275, 282, 283, and 285, which have the function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0378] Here, it is preferable to use an oxide having an amorphous structure as the insulators 212, 214, 271, 275, 282, 283, and 285. For example, AlO ｘ (x is any number greater than 0), or MgO ｙIt is preferable to use a metal oxide such as a metal oxide having an amorphous structure (where y is an arbitrary number greater than 0). In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, a highly reliable transistor 200 and a semiconductor device can be manufactured.

[0379] Furthermore, the insulators 212, 214, 271, 275, 282, 283, and 285 preferably have an amorphous structure, but may have a polycrystalline structure region formed in a portion thereof. Furthermore, the insulators 212, 214, 271, 275, 282, 283, and 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0380] The insulators 212, 214, 271, 275, 282, 283, and 285 can be formed by, for example, a sputtering method. Sputtering does not require the use of molecules containing hydrogen in the film formation gas, and therefore can reduce the hydrogen concentrations of the insulators 212, 214, 271, 275, 282, 283, and 285. Note that the film formation method is not limited to sputtering, and CVD, MBE, PLD, ALD, or the like may also be used as appropriate.

[0381] It may also be preferable to reduce the resistivity of the insulators 212, 275, and 283. For example, it may be preferable to reduce the resistivity of the insulators 212, 275, and 283 to approximately 1×10 １３ By setting the resistivity to Ωcm, the insulators 212, 275, and 283 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 246 in a process using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulators 212, 275, and 283 is preferably 1×10 １０ Ωcm or more 1×10 １５ Ωcm or less.

[0382] The insulators 216, 274, 280, and 285 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 216, 274, 280, and 285.

[0383] The conductor 205 is arranged to overlap the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. In addition, a part of the conductor 205 may be embedded in the insulator 214.

[0384] The conductor 205 includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of an opening formed in the insulator 216. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the height of the upper surface of the conductor 205b is the same as or approximately the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216.

[0385] Here, the conductor 205a is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0386] By using a conductive material for the conductor 205a that has the function of reducing hydrogen diffusion, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224 or the like. Furthermore, by using a conductive material for the conductor 205a that has the function of suppressing oxygen diffusion, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be formed as a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be made of titanium nitride.

[0387] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0388] Note that although the conductor 205 in the transistor 200 has a stacked structure of the conductor 205a and the conductor 205b, the present invention is not limited to this. For example, the conductor 205 may have a single layer structure or a stacked structure of three or more layers.

[0389] The electrical resistivity of the conductor 205 is designed taking into account the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. In the transistor 200 shown in FIG. 14 , the film thickness of the conductor 205 is approximately the same as that of the insulator 216. Here, it is preferable to reduce the film thicknesses of the conductor 205 and the insulator 216 within the range permitted by the design of the conductor 205. By reducing the film thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of the impurities into the oxide 230.

[0390] The conductor 205 corresponds to the conductor 15 described in Embodiment 1. Therefore, the material, structure, and the like used for the conductor 205 can be referred to the content of the conductor 15 described in Embodiment 1. Furthermore, the material, structure, and the like used for the conductor 15 described in Embodiment 1 can be referred to the description of the conductor 205 described in this embodiment.

[0391] The insulators 222 and 224 function as gate insulators.

[0392] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0393] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. Alternatively, an oxide containing hafnium and zirconium, such as hafnium zirconium oxide, is preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with the oxygen contained in the insulator 224 and the oxide 230.

[0394] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0395] The insulator 222 may be a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. The insulator 222 may be made of lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), (Ba,Sr)TiO ３ In some cases, a material with a high dielectric constant such as (BST) can be used.

[0396] The insulator 224 in contact with the oxide 230 may be made of, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0397] During the manufacturing process of the transistor 200, heat treatment is preferably performed while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 600° C. or lower, more preferably 350° C. or higher and 550° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230, thereby reducing oxygen vacancies. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to replenish desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher, followed by another heat treatment in a nitrogen gas or inert gas atmosphere.

[0398] By performing oxygen addition treatment on the oxide 230, oxygen vacancies in the oxide 230 can be repaired by the supplied oxygen. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide 230 to convert the hydrogen into H ２ As a result, the hydrogen remaining in the oxide 230 is recombined with the oxygen vacancies to form V. Ｏ The formation of H can be suppressed.

[0399] The insulator 222 and the insulator 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 224 may be formed in an island shape by overlapping with the oxide 230. In this case, the insulator 275 is configured to contact the side surface of the insulator 224 and the top surface of the insulator 222.

[0400] The insulators 222 and 224 correspond to the insulators 22 and 24 described in embodiment 1, respectively. Therefore, the materials and configurations used for the insulators 222 and 224 can be taken into consideration, respectively, of the insulators 22 and 24 described in embodiment 1. Furthermore, the materials and configurations used for the insulators 22 and 24 described in embodiment 1 can be taken into consideration, respectively, of the insulators 222 and 224 described in this embodiment.

[0401] Part of the insulator 223a and part of the insulator 223b may function as a gate insulator. Note that the insulator 223a corresponds to the insulator 23a described in Embodiment 1, and the insulator 223b corresponds to the insulator 23b described in Embodiment 1. Therefore, the materials, structures, and the like used for the insulators 223a and 223b can be determined based on the contents of the insulators 23a and 23b described in Embodiment 1.

[0402] The conductor 242a and the conductor 242b are provided in contact with the top surface of the oxide 230. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0403] It is preferable that no curved surface be formed between the side surface of the conductor 242 and the top surface of the conductor 242. The conductor 242 having no curved surface can increase the cross-sectional area of ​​the conductor 242 in the cross section in the channel width direction, as shown in Fig. 14D. This can increase the conductivity of the conductor 242 and the on-state current of the transistor 200.

[0404] Note that the conductor 242a corresponds to the conductor 42a described in Embodiment 1, and the conductor 242b corresponds to the conductor 42b described in Embodiment 1. Therefore, the materials and structures used for the conductors 242a and 242b can also be determined by referring to the details of the conductors 42a and 42b described in Embodiment 1.

[0405] The insulator 271a is provided in contact with the top surface of the conductor 242a, and the insulator 271b is provided in contact with the top surface of the conductor 242b. The insulator 271 preferably functions as a barrier insulating film at least against oxygen. Therefore, the insulator 271 preferably has a function of suppressing oxygen diffusion. For example, the insulator 271 preferably has a function of suppressing oxygen diffusion more than the insulator 280. The insulator 271 may be, for example, an insulator such as aluminum oxide or magnesium oxide.

[0406] The insulator 275 is provided to cover the insulator 224, the insulator 223a, the insulator 223b, the oxide 230, the conductor 242, and the insulator 271. The insulator 275 preferably has the function of capturing and fixing hydrogen. In this case, the insulator 275 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 275 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0407] By providing the insulators 271 and 275 as described above, the conductor 242 can be wrapped in an insulator that has a barrier property against oxygen. In other words, it is possible to prevent the oxygen contained in the insulators 224 and 280 from diffusing into the conductor 242. This makes it possible to suppress the conductor 242 from being directly oxidized by the oxygen contained in the insulators 224 and 280, which would increase the resistivity and reduce the on-current.

[0408] The insulator 275 corresponds to the insulator 75 described in Embodiment 1. Therefore, the material, structure, and the like used for the insulator 275 can be determined based on the details of the insulator 75 described in Embodiment 1.

[0409] The insulator 252 functions as part of the gate insulator. Note that the insulator 252 corresponds to the insulator 52 described in Embodiment 1. Therefore, the material, structure, and the like used for the insulator 252 can be referred to for the insulator 52 described in Embodiment 1.

[0410] The insulator 250 functions as part of the gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the insulator 252. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 250 is an insulator containing at least oxygen and silicon.

[0411] 14A to 14D, the insulator 250 is shown as a single layer, but the present invention is not limited to this and may have a stacked structure of two or more layers. For example, as shown in FIG. 15B, the insulator 250 may have a two-layer stacked structure of an insulator 250a and an insulator 250b on the insulator 250a.

[0412] As shown in FIG. 15B , when the insulator 250 has a two-layer stacked structure, it is preferable that the lower insulator 250a be formed using an insulator that is easily permeable to oxygen, and the upper insulator 250b be formed using an insulator that has the function of suppressing oxygen diffusion. This structure can suppress the diffusion of oxygen contained in the insulator 250a into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulator 250a may be formed using a material that can be used for the insulator 250 described above, and the insulator 250b may be an insulator containing oxides of one or both of aluminum and hafnium. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 250b. In this case, the insulator 250b contains at least oxygen and hafnium. The thickness of the insulator 250b is 0.5 nm to 5.0 nm, preferably 1.0 nm to 5.0 nm, and more preferably 1.0 nm to 3.0 nm. In this case, the insulator 250b only needs to have a region with the above thickness in at least a portion thereof.

[0413] When silicon oxide or silicon oxynitride is used for the insulator 250a, the insulator 250b may be an insulating material that is a high-k material with a high dielectric constant. By forming the gate insulator into a layered structure of the insulators 250a and 250b, a thermally stable layered structure with a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. This allows the dielectric strength of the insulator 250 to be increased.

[0414] The insulator 250 corresponds to the insulator 50 described in embodiment 1. Therefore, the materials and configuration used for the insulator 250 can be referred to the details of the insulator 50 described in embodiment 1. The materials and configuration used for the insulator 50 described in embodiment 1 can be referred to the details of the insulator 250 described in this embodiment.

[0415] The insulator 254 functions as part of the gate insulator.

[0416] 15B , when the insulator 250 has a two-layer stacked structure, by using an insulator such as hafnium oxide that has a function of suppressing the permeation of impurities such as hydrogen and oxygen as the insulator 250b, the insulator 250b can also function as the insulator 254. In such a case, by not providing the insulator 254, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0417] The insulator 254 corresponds to the insulator 54 described in Embodiment 1. Therefore, the material, structure, and the like used for the insulator 254 can be determined based on the content of the insulator 54 described in Embodiment 1.

[0418] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIGS. 14B and 14C , the top surface of the conductor 260 coincides or approximately coincides with the top surface of the insulator 250. Note that although the conductor 260 is shown as having a two-layer structure of the conductor 260a and the conductor 260b in FIGS. 14B and 14C , it may have a single-layer structure or a stacked structure of three or more layers.

[0419] The conductor 260a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0420] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0421] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0422] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 242 a and the conductor 242 b without alignment.

[0423] The conductor 260 corresponds to the conductor 60 described in embodiment 1. Therefore, the materials and configuration used for the conductor 260 can be referred to the contents of the conductor 60 described in embodiment 1. Furthermore, the materials and configuration used for the conductor 60 described in embodiment 1 can be referred to the description of the conductor 260 described in this embodiment.

[0424] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulators 252, 250, 254, and conductor 260 are provided. The top surface of the insulator 280 may be flattened.

[0425] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form a region containing oxygen that is released by heating.

[0426] The insulator 280 corresponds to the insulator 80 described in embodiment 1. Therefore, the material and configuration used for the insulator 280 can be taken into consideration of the details of the insulator 80 described in embodiment 1. The material and configuration used for the insulator 80 described in embodiment 1 can also be taken into consideration of the details of the insulator 280 described in this embodiment.

[0427] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280 and preferably has a function of capturing impurities such as hydrogen. The insulator 282 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 282 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 282 contains at least oxygen and aluminum. By providing the insulator 282 in contact with the insulator 280 in the region sandwiched between the insulators 212 and 283 and having a function of capturing impurities such as hydrogen, the insulator 282 can capture impurities such as hydrogen contained in the insulator 280 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 282 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with excellent characteristics.

[0428] The insulator 282 corresponds to the insulator 82 described in Embodiment 1. Therefore, the material, structure, and the like used for the insulator 282 can be referred to the details of the insulator 82 described in Embodiment 1. The material, structure, and the like used for the insulator 82 described in Embodiment 1 can be referred to the details of the insulator 282 described in this embodiment.

[0429] The insulator 283 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 283 is disposed over the insulator 282. It is preferable to use a nitride containing silicon, such as silicon nitride or silicon nitride oxide, as the insulator 283. For example, silicon nitride formed by a sputtering method may be used as the insulator 283. By forming the insulator 283 by a sputtering method, a high-density silicon nitride film can be formed. Alternatively, the insulator 283 may be formed by stacking a silicon nitride film formed by a PEALD method or a CVD method on a silicon nitride film formed by a sputtering method.

[0430] The insulator 283 corresponds to the insulator 83 described in Embodiment 1. Therefore, the material, structure, and the like used for the insulator 283 can be referred to the details of the insulator 83 described in Embodiment 1. The material, structure, and the like used for the insulator 83 described in Embodiment 1 can be referred to the details of the insulator 283 described in this embodiment.

[0431] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a layered structure.

[0432] Furthermore, when the conductor 240 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the first conductor arranged near the insulators 285, 283, 282, 280, 275, and 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from mixing into the oxide 230 through the conductors 240a and 240b.

[0433] The insulators 241a and 241b may be a barrier insulating film that can be used for the insulator 275, for example. For example, the insulators 241a and 241b may be made of an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 241a and 241b are provided in contact with the insulators 283, 282, and 271, and thus can prevent impurities such as water and hydrogen contained in the insulator 280 from mixing with the oxide 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because of its high blocking properties against hydrogen. Furthermore, the oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.

[0434] When the insulators 241a and 241b are formed into a layered structure as shown in FIG. 14B, it is preferable that the first insulator in contact with the inner wall of an opening such as the insulator 280 and the second insulator inside it be formed by combining a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0435] For example, aluminum oxide formed by ALD may be used as the first insulator, and silicon nitride formed by PEALD may be used as the second insulator. This configuration can suppress oxidation of the conductor 240 and further reduce hydrogen contamination of the conductor 240.

[0436] Conductors 246 (conductors 246a and 246b) may be disposed in contact with the upper surfaces of the conductors 240a and 240b, functioning as wiring. Conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as its main component. The conductor may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0437] <Manufacturing Method of Semiconductor Device> Next, a manufacturing method of the semiconductor device of one embodiment of the present invention shown in FIGS. 14A to 14D will be described with reference to FIGS. 16A to 27D.

[0438] A in each figure shows a top view. B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in A of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. D in each figure is a cross-sectional view of the portion indicated by the dashed dotted line A5-A6 in A of each figure. Note that some elements are omitted from the top view in A of each figure for clarity.

[0439] 14 has components in common with the transistor 20 described in Embodiment 1. Therefore, in the manufacturing method of the semiconductor device illustrated in FIG. 14 , Embodiment 1 can be referred to for the description of parts in common with the manufacturing method of the transistor 20.

[0440] First, a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate (see FIGS. 16A to 16D ). The insulator 212 is preferably formed by sputtering. By using sputtering, which does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulator 212 can be reduced. However, the method for forming the insulator 212 is not limited to sputtering, and CVD, MBE, PLD, ALD, or the like may also be used as appropriate.

[0441] In this embodiment, a silicon nitride film is formed as the insulator 212 by pulsed DC sputtering using a silicon target in an atmosphere containing nitrogen gas. The use of pulsed DC sputtering can suppress particle generation due to arcing on the target surface, resulting in a more uniform film thickness distribution. Furthermore, the use of pulsed voltage can make the rise and fall of discharge steeper than with high-frequency voltage. This allows for more efficient supply of power to the electrodes, improving the sputtering rate and film quality.

[0442] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below the insulator 212. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer (not shown) below the insulator 212, it is possible to suppress the upward diffusion of the metal through the insulator 212.

[0443] Next, the insulator 214 is deposited over the insulator 212 (see FIGS. 16A to 16D). The insulator 214 is preferably deposited by sputtering. By using sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to sputtering, and CVD, MBE, PLD, ALD, or the like may also be used as appropriate.

[0444] In this embodiment, an aluminum oxide film is formed as the insulator 214 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen implanted into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is set to 0 W / cm. ２ More than 1.86 W / cm ２The following is true. That is, the amount of oxygen suitable for the characteristics of the transistor can be changed and injected by changing the RF power when forming the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be injected. The RF frequency is preferably 10 MHz or higher, typically 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0445] It is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high function of capturing and fixing hydrogen, as the insulator 214. This makes it possible to capture or fix hydrogen contained in the insulator 216 or the like and prevent the hydrogen from diffusing into the oxide 230. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 214 is preferable because it may be possible to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with favorable characteristics.

[0446] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 is preferably deposited by sputtering. The hydrogen concentration in the insulator 216 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. However, the deposition of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0447] In this embodiment, a silicon oxide film is formed as the insulator 216 by pulsed DC sputtering using a silicon target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0448] The insulators 212, 214, and 216 are preferably successively deposited without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This allows the insulators 212, 214, and 216 to be deposited with reduced hydrogen content and also reduces the amount of hydrogen mixed into the films between deposition steps.

[0449] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be formed by wet etching, but dry etching is preferable for fine processing. Furthermore, it is preferable to select an insulator for the insulator 214 that functions as an etching stopper film when the insulator 216 is etched to form the groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 214 may be made of silicon nitride, aluminum oxide, or hafnium oxide.

[0450] After the opening is formed, a conductive film that becomes the conductor 205a is formed. The conductive film preferably includes a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film may be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0451] In this embodiment, titanium nitride is formed as the conductive film that becomes the conductor 205a. By using such a metal nitride as the lower layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like. Furthermore, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0452] Next, a conductive film to be the conductor 205b is formed. For the conductive film, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film.

[0453] Next, CMP treatment is performed to remove a portion of the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216 (see FIGS. 16A to 16D). As a result, the conductor 205a and the conductor 205b remain only in the openings. Note that the CMP treatment may remove a portion of the insulator 216.

[0454] Next, an insulator 222 is formed over the insulator 216 and the conductor 205 (see FIGS. 17A to 17D ). The insulator 222 may contain one or both of aluminum and hafnium oxides. Note that aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing one or both of aluminum and hafnium oxides. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. The insulator 222 having barrier properties against hydrogen and water prevents hydrogen and water contained in structures provided around the transistor 200 from diffusing into the transistor 200 through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0455] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, hafnium oxide is formed as the insulator 222 by an ALD method. In particular, it is preferable to use a method for forming hafnium oxide with a reduced hydrogen concentration, which is one embodiment of the present invention.

[0456] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0457] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being taken into the insulator 222 as much as possible.

[0458] In this embodiment, after the insulator 222 is formed, heat treatment is performed at 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4:1. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment may cause part of the insulator 222 to crystallize. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0459] Next, an insulating layer 224B and an insulating film 223A are formed over the insulator 222 (see FIGS. 17A to 17D). Note that the insulating layer 224B and the insulating film 223A may be formed by referring to the formation method of the insulating layer 24B and the insulating film 23A described in Embodiment 1.

[0460] Next, an oxide film 230A is formed on the insulating layer 224B and the insulating film 223A (see FIGS. 17A to 17D). When the oxide 230 has a stacked structure of multiple oxide layers, it is preferable that some or all of the multiple oxide films included in the oxide film that becomes the oxide 230 are formed successively without being exposed to the air environment. By forming the films without exposing them to the air, it is possible to prevent impurities or moisture from the air environment from adhering to each oxide layer, and the vicinity of the interface with the oxide layer can be kept clean.

[0461] The oxide film 230A may be formed by taking into consideration the method for forming the oxide film 30A described in the first embodiment.

[0462] Next, it is preferable to perform heat treatment. For this heat treatment, Embodiment 1 can be referred to. By performing this heat treatment, hydrogen in the insulator 216, the insulating layer 224B, and the oxide film 230A moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the insulator 216, the insulating layer 224B, and the oxide film 230A diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216, the insulating layer 224B, and the oxide film 230A decrease.

[0463] In particular, the insulator 224 formed by processing the insulating layer 224B functions as a gate insulator of the transistor 200, and the oxide 230 formed by processing the oxide film 230A functions as a channel formation region of the transistor 200. Therefore, the transistor 200 including the insulating layer 224B and the oxide film 230A with reduced hydrogen concentration has good reliability and is therefore preferable.

[0464] Next, a conductive film 242A is formed over the oxide film 230A (see FIGS. 17A to 17D). Note that the conductive film 242A may be formed by referring to the method for forming the conductive film 42A described in Embodiment 1.

[0465] Next, an insulating film 271A is formed over the conductive film 242A (see FIGS. 17A to 17D). The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271A is preferably an insulating film that has a function of suppressing oxygen permeation. For example, an aluminum oxide film or a silicon nitride film may be formed by sputtering as the insulating film 271A.

[0466] Note that the conductive film 242A and the insulating film 271A are preferably formed by sputtering without exposure to the atmosphere. For example, a multi-chamber film formation apparatus may be used. This allows the conductive film 242A and the insulating film 271A to be formed with reduced hydrogen content and further reduces the incorporation of hydrogen into the films between film formation steps. Furthermore, when a hard mask is provided on the insulating film 271A, the film to be the hard mask may also be formed continuously without exposure to the atmosphere.

[0467] Next, the insulating layer 224B, the insulating film 223A, the oxide film 230A, the conductive film 242A, and the insulating film 271A are processed into island shapes by lithography to form the insulator 224, the insulator 223a, the insulator 223b, the oxide 230, the conductive layer 242B, and the insulating layer 271B (see FIGS. 18A to 18D ). The insulator 224, the oxide 230, the conductive layer 242B, and the insulating layer 271B are formed so that at least a portion of each overlaps with the conductor 205. This processing can be performed by dry etching or wet etching. Dry etching is suitable for microfabrication. The insulating layer 224B, the insulating film 223A, the oxide film 230A, the conductive film 242A, and the insulating film 271A may be processed under different conditions.

[0468] Here, because the insulating layer 271B functions as a mask for the conductive layer 242B, the conductive layer 242B does not have a curved surface between its side surface and top surface, as shown in FIGS. 18B to 18D . As a result, the conductors 242a and 242b shown in FIGS. 14B and 14D have angular ends where their side surfaces and top surfaces intersect. Because the angular ends where the side surfaces and top surfaces of the conductor 242 intersect are angular, the cross-sectional area of ​​the conductor 242 is larger than when the ends have a curved surface. This reduces the resistance of the conductor 242, thereby increasing the on-state current of the transistor 200.

[0469] 18B to 18D , the side surfaces of the insulator 224, the insulator 223a, the insulator 223b, the oxide 230, the conductive layer 242B, and the insulating layer 271B may be tapered. In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of the structure is inclined with respect to the substrate surface. For example, the angle between the inclined side surface and the substrate surface (hereinafter sometimes referred to as the taper angle) is preferably less than 90°. The insulator 224, the insulator 223a, the insulator 223b, the oxide 230, the conductive layer 242B, and the insulating layer 271B may have a taper angle of, for example, 60° or more and less than 90°. Tapering the side surfaces in this manner improves the coverage of the insulator 275 and the like in subsequent processes, reducing defects such as voids.

[0470] However, the present invention is not limited to the above, and the side surfaces of the insulator 224, the insulator 223a, the insulator 223b, the oxide 230, the conductive layer 242B, and the insulating layer 271B may be substantially perpendicular to the top surface of the insulator 222. With such a structure, it is possible to reduce the area and increase the density when providing a plurality of transistors 200.

[0471] Furthermore, by-products generated in the etching process may be formed in layers on the side surfaces of the insulator 224, the insulator 223a, the insulator 223b, the oxide 230, the conductive layer 242B, and the insulating layer 271B. In this case, the layer-like by-products are formed between the insulator 224, the insulator 223a, the insulator 223b, the oxide 230, the conductive layer 242B, and the insulating layer 271B and the insulator 275. Therefore, it is preferable to remove the layer-like by-products formed in contact with the upper surface of the insulator 222.

[0472] Next, the insulator 275 is formed to cover the insulator 224, the insulator 223a, the insulator 223b, the oxide 230, the conductive layer 242B, and the insulating layer 271B (see FIGS. 19A to 19D). The insulator 275 may be formed by referring to the method for forming the insulator 75 described in Embodiment 1.

[0473] Here, it is preferable that the insulator 275 be in close contact with the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the insulator 223a, and the side surface of the insulator 223b. With this configuration, the oxide 230 and the conductive layer 242B can be covered with the insulator 275 and the insulating layer 271B, which have the function of suppressing oxygen diffusion. This makes it possible to reduce the direct diffusion of oxygen from the insulator 280, etc., to the oxide 230 and the conductive layer 242B in a later process.

[0474] Next, the insulator 280 is formed over the insulator 275 (see FIGS. 19A to 19D). The insulator 280 may be formed by referring to the method for forming the insulator 80 described in Embodiment 1.

[0475] Next, a part of the insulator 280, a part of the insulator 275, a part of the insulating layer 271B, and a part of the conductive layer 242B are processed to form openings that reach the oxide 230. The openings are preferably formed to overlap with the conductor 205. By forming the openings, the insulator 271a, the insulator 271b, the conductor 242a, and the conductor 242b are formed (see FIGS. 20A to 20D).

[0476] 20B and 20C, the side surfaces of the insulator 280, the insulator 275, the insulator 271, and the conductor 242 may have tapered shapes. The taper angle of the insulator 280 may be larger than the taper angle of the conductor 242. Although not shown in FIGS. 20A to 20C, the upper portion of the oxide 230 may be removed when the opening is formed.

[0477] Furthermore, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, and a portion of the conductive layer 242B can be processed by dry etching or wet etching. Processing by dry etching is suitable for fine processing. Furthermore, the processing may be performed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 275 and a portion of the insulating layer 271B may be processed by wet etching, and a portion of the conductive layer 242B may be processed by dry etching.

[0478] It is preferable to perform cleaning treatment after the etching. Furthermore, heat treatment may be performed after the etching or the cleaning treatment. Embodiment 1 can be referred to for the cleaning treatment and the heat treatment.

[0479] Next, an insulating film 252A is formed (see FIGS. 21A to 21D ). The insulating film 252A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 252A is preferably formed using the ALD method. As described above, the insulating film 252A is preferably formed to a thin film thickness, and it is necessary to minimize film thickness variation. In contrast, the ALD method is a film formation method that alternately introduces a precursor and a reactant (e.g., an oxidizer). The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Furthermore, as shown in FIGS. 21B and 21C , the insulating film 252A must be formed with good coverage on the bottom and side surfaces of the opening formed by the insulator 280, etc. In particular, it is preferable that the insulating film 252A be formed with good coverage on the top and side surfaces of the oxide 230 and the side surfaces of the conductor 242. Since atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 252A can be formed with good coverage over the opening.

[0480] When the insulating film 252A is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ ) as an oxidizing agent, hydrogen diffusing into the oxide 230 can be reduced.

[0481] In this embodiment, the insulating film 252A is formed by depositing aluminum oxide using a thermal ALD method.

[0482] Next, microwave treatment is preferably performed in an atmosphere containing oxygen (see FIGS. 21A to 21D). The dotted lines in FIGS. 21B to 21D indicate microwaves, high-frequency waves such as RF, oxygen plasma, oxygen radicals, or the like. Embodiment 1 can be referred to for the microwave treatment.

[0483] 21B to 21D, by performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230. At this time, microwaves or high frequency waves such as RF can also be irradiated to the region 230c. In other words, microwaves, high frequency waves such as RF, oxygen plasma, etc. can be applied to the region 230c shown in FIG. 15A. The action of plasma, microwaves, etc. can increase the V of the region 230c. Ｏ H can be split off and hydrogen can be removed from the region 230c. Ｏ Therefore, oxygen vacancies and V in the region 230c can be reduced. Ｏ By supplying oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancies formed in the region 230c, the oxygen vacancies in the region 230c can be further reduced, and the carrier concentration can be lowered.

[0484] 15A , conductors 242a and 242b are provided on regions 230a and 230b. Here, conductor 242 preferably functions as a shielding film against the effects of microwaves, high-frequency waves such as RF, oxygen plasma, and the like when microwave processing is performed in an oxygen-containing atmosphere. Therefore, conductor 242 preferably has the function of blocking electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0485] 21B to 21D, the conductors 242a and 242b shield the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc., so that these effects do not reach the regions 230a and 230b. As a result, V Ｏ Since H is reduced and an excessive amount of oxygen is not supplied, a decrease in the carrier concentration can be prevented.

[0486] Furthermore, an insulator 252 having a barrier property against oxygen is provided in contact with the side surfaces of the conductor 242 a and the conductor 242 b, thereby making it possible to prevent an oxide film from being formed on the side surfaces of the conductor 242 a and the conductor 242 b by microwave processing.

[0487] In addition, the film quality of the insulator 252 can be improved, thereby improving the reliability of the transistor 200.

[0488] In this manner, oxygen vacancies and V Ｏ By removing H, the region 230c can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230a and 230b, which function as source and drain regions, can be suppressed, thereby maintaining the n-type state of the regions before the microwave treatment. This suppresses fluctuations in the electrical characteristics of the transistor 200 and suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0489] Next, the insulating film 250A is formed (see FIGS. 22A to 22D). The insulating film 250A may be formed by referring to the method for forming the insulating film 50A described in the first embodiment. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulating film 250A to be reduced. Since the insulating film 250A will become the insulator 250 that faces the oxide 230 via the thin insulator 252 in a later process, it is preferable that the hydrogen concentration be reduced in this way.

[0490] In this embodiment, the insulating film 250A is formed of silicon oxynitride by PECVD.

[0491] Furthermore, when the insulator 250 has a two-layer stacked structure as shown in FIG. 15B , the insulating film that becomes the insulator 250b can be formed after the insulating film 250A is formed. The insulating film that becomes the insulator 250b can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating film that becomes the insulator 250b is preferably formed using an insulator that has the function of suppressing oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the insulator 250a into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. The insulating film that becomes the insulator 250b can be formed using the same material as the insulator 222. For example, the insulating film that becomes the insulator 250b can be formed using hafnium oxide by thermal ALD.

[0492] Microwave treatment may be performed after the formation of the insulating film 250A (see FIGS. 22A to 22D ). The microwave treatment may be performed under the same conditions as those performed after the formation of the insulating film 252A described above. Alternatively, the microwave treatment may be performed after the formation of the insulating film 250A without performing the microwave treatment after the formation of the insulating film 252A. Furthermore, when an insulating film to be the insulator 250b is provided as described above, the microwave treatment may be performed after the film formation. The microwave treatment may be performed under the same conditions as those performed after the formation of the insulating film 252A described above. Alternatively, the microwave treatment may be performed after the formation of the insulating film to be the insulator 250b without performing the microwave treatment after the formation of the insulating film 252A or the insulating film 250A.

[0493] Furthermore, after the formation of the insulating film 252A, the insulating film 250A, and the insulating film that will become the insulator 250b, a heat treatment may be performed while maintaining a reduced pressure after each microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from the insulating film 252A, the insulating film 250A, the insulating film that will become the insulator 250b, and the oxide 230. Some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, a heat treatment step may be performed multiple times while maintaining a reduced pressure after the microwave treatment. Repeated heat treatments can more efficiently remove hydrogen from the insulating film 252A, the insulating film 250A, the insulating film that will become the insulator 250b, and the oxide 230. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. The microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 230 and the like are sufficiently heated by microwave annealing, the heat treatment may not be necessary.

[0494] Furthermore, by performing microwave processing to modify the film quality of the insulating film 252A, the insulating film 250A, and the insulating film that will become the insulator 250b, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230, etc., via the insulator 252 in a post-process such as film formation of the conductive film that will become the conductor 260, or in a post-treatment such as heat treatment.

[0495] Next, the insulating film 254A is formed (see FIGS. 23A to 23D). The insulating film 254A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating film 254A is preferably formed by ALD, similar to the insulating film 252A. By forming the insulating film 254A by ALD, the insulating film 254A can be formed to a thin thickness with good coverage. In this embodiment, silicon nitride is formed as the insulating film 254A by PEALD.

[0496] Next, a conductive film to become the conductor 260a and a conductive film to become the conductor 260b are formed in this order. The conductive film to become the conductor 260a and the conductive film to become the conductor 260b can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, titanium nitride is formed as the conductive film to become the conductor 260a by the ALD method, and tungsten is formed as the conductive film to become the conductor 260b by the CVD method.

[0497] Next, the insulating film 252A, the insulating film 250A, the insulating film 254A, the conductive film that will become the conductor 260a, and the conductive film that will become the conductor 260b are polished by CMP until the insulator 280 is exposed, thereby forming the insulators 252, 250, 254, and the conductor 260 (the conductors 260a and 260b) (see FIGS. 24A to 24D). As a result, the insulator 252 is arranged to cover the opening that reaches the oxide 230. The conductor 260 is arranged to fill the opening via the insulators 252, 250, and 254.

[0498] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. This heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0499] Next, the insulator 282 is formed over the insulator 252, the insulator 250, the insulator 254, the conductor 260, and the insulator 280 (see FIGS. 24A to 24D ). The insulator 282 may be formed by referring to the method for forming the insulator 82 described in Embodiment 1.

[0500] Next, an etching mask is formed on the insulator 282 by lithography, and a part of the insulator 282, a part of the insulator 280, a part of the insulator 275, a part of the insulator 222, and a part of the insulator 216 are processed until the top surface of the insulator 214 is exposed (see FIGS. 25A to 25D). This processing may be performed by wet etching, but dry etching is preferable for fine processing.

[0501] Next, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 350° C. or higher and 600° C. or lower. The temperature of this heat treatment is preferably lower than the temperature of the heat treatment performed after the formation of the oxide film 230A. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere. By performing this heat treatment, part of the oxygen added to the insulator 280 diffuses into the oxide 230 via the insulator 250 or the like.

[0502] Furthermore, by performing this heat treatment, oxygen contained in the insulator 280 and hydrogen bonded to the oxygen can be released to the outside from the side surface of the formed insulator 280 by processing the insulators 282, 280, 275, 222, and 216. Note that the hydrogen bonded to the oxygen is released as water. Therefore, unnecessary oxygen and hydrogen contained in the insulator 280 can be reduced.

[0503] Furthermore, in the region of the oxide 230 overlapping with the conductor 260, an insulator 252 is provided in contact with the top surface and side surface of the oxide 230. The insulator 252 has a barrier property against oxygen, and can reduce the diffusion of an excessive amount of oxygen into the oxide 230. This allows oxygen to be supplied to the region 230c and its vicinity without excessive oxygen being supplied thereto. This prevents the side surface of the conductor 242 from being oxidized by excess oxygen, and reduces oxygen vacancies and V formed in the region 230c. Ｏ H can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved, and the reliability can be improved.

[0504] On the other hand, when the transistors 200 are highly integrated, the volume of the insulator 280 for each transistor 200 may become excessively small. In this case, the amount of oxygen diffusing into the oxide 230 during the heat treatment is significantly reduced. If the oxide 230 is heated while being in contact with an oxide insulator (such as the insulator 250) that does not contain sufficient oxygen, oxygen constituting the oxide 230 may be released. However, in the transistor 200 described in this embodiment, the insulator 252 is provided in contact with the top surface and side surface of the oxide 230 in a region of the oxide 230 that overlaps with the conductor 260. The insulator 252 has a barrier property against oxygen, and therefore can reduce release of oxygen from the oxide 230 during the heat treatment. This reduces oxygen vacancies and V formed in the region 230c. Ｏ H can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved, and the reliability can be improved.

[0505] As described above, in the semiconductor device according to this embodiment, a transistor having good electrical characteristics and good reliability can be formed regardless of whether the amount of oxygen supplied from the insulator 280 is large or small. Therefore, a semiconductor device in which variations in the electrical characteristics of the transistor 200 within the substrate surface are suppressed can be provided.

[0506] Next, the insulator 283 is formed over the insulator 282 (see FIGS. 26A to 26D ). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 283 is preferably formed by a sputtering method. The hydrogen concentration in the insulator 283 can be reduced by using a sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas. The insulator 283 may also have a multilayer structure. For example, a silicon nitride film may be formed by a sputtering method, and then a silicon nitride film may be formed on the silicon nitride by an ALD method. The insulator 283 and the insulator 214, which have high barrier properties, surround the transistor 200, thereby preventing moisture and hydrogen from entering from the outside.

[0507] Next, the insulator 274 is formed over the insulator 283. The insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 274 by a CVD method.

[0508] Next, the insulator 274 is polished by CMP until the insulator 283 is exposed, thereby planarizing the upper surface of the insulator 274 (see FIGS. 26A to 26D). The CMP process may remove a part of the upper surface of the insulator 283.

[0509] Next, the insulator 285 is formed over the insulator 274 and the insulator 283 (see FIGS. 27A to 27D ). The insulator 285 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 285 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 285 can be reduced.

[0510] In this embodiment, a silicon oxide film is formed as the insulator 285 by a sputtering method.

[0511] Next, openings are formed in the insulators 271, 275, 280, 282, 283, and 285, reaching the conductor 242 (see FIGS. 27A and 27B ). The openings may be formed using lithography. Note that while the shape of the openings is circular in top view in FIG. 27A , the shape is not limited to this. For example, the openings may have a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners in top view.

[0512] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see FIG. 27B). The insulating film can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. As the insulating film, it is preferable to use an insulating film that has the function of suppressing oxygen permeation. For example, it is preferable to form an aluminum oxide film by ALD, and then form a silicon nitride film thereon by PEALD. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0513] Furthermore, dry etching, for example, may be used for anisotropic etching of the insulating film that will become the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the conductors 240a and 240b.

[0514] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film preferably has a layered structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, the conductive film may be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0515] Next, CMP processing is performed to remove portions of the conductive film that will become the conductors 240a and 240b, thereby exposing the upper surface of the insulator 285. As a result, the conductive film remains only in the openings, thereby forming the conductors 240a and 240b with flat upper surfaces (see FIGS. 27A to 27D). Note that the CMP processing may remove portions of the upper surface of the insulator 285.

[0516] Next, a conductive film is formed to become the conductor 246. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0517] Next, the conductive film that will become the conductor 246 is processed by lithography to form a conductor 246a that contacts the top surface of the conductor 240a and a conductor 246b that contacts the top surface of the conductor 240b. At this time, a part of the insulator 285 in the region where the conductor 246a and the conductor 246b do not overlap with the insulator 285 may be removed.

[0518] 14A to 14D can be manufactured. As shown in FIGS. 16A to 27D, the transistor 200 can be manufactured by the manufacturing method of a semiconductor device described in this embodiment.

[0519] <Modification of Semiconductor Device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS. 28A to 30D.

[0520] A in each figure shows a top view of the semiconductor device. B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in A in each figure. C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in A in each figure. D in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in A in each figure. In the top view A in each figure, some elements are omitted for clarity.

[0521] In the semiconductor devices shown in A to D of each figure, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. In this section, the materials described in detail in <Configuration Example of Semiconductor Device> can also be used as the constituent materials of the semiconductor device.

[0522] <Variation 1 of Semiconductor Device> The semiconductor device shown in Figures 28A to 28D is a variation of the semiconductor device shown in Figures 14A to 14D. The semiconductor device shown in Figures 28A to 28D differs from the semiconductor device shown in Figures 14A to 14D in that the insulator 282 is not provided. Therefore, in the semiconductor device shown in Figures 28A to 28D, the insulator 283 contacts the upper surface of the conductor 260, the upper surface of the insulator 280, the uppermost part of the insulator 254, the uppermost part of the insulator 250, and the uppermost part of the insulator 252.

[0523] 21 or 22, the region 230c can be made substantially i-type without providing the insulator 282 and adding oxygen to the insulator 280. In such a case, by using a structure in which the insulator 282 is not provided, as shown in FIGS. 28A to 28D, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0524] <Semiconductor Device Variation 2> The semiconductor device shown in Figures 29A to 29D is a variation of the semiconductor device shown in Figures 14A to 14D. The semiconductor device shown in Figures 29A to 29D differs from the semiconductor device shown in Figures 14A to 14D in that an oxide 243 (oxide 243a and oxide 243b) is provided. The oxide 243a is provided between the oxide 230 and the conductor 242a, and the oxide 243b is provided between the oxide 230 and the conductor 242b. Here, the oxide 243a is preferably in contact with the upper surface of the oxide 230 and the lower surface of the conductor 242a. Furthermore, the oxide 243b is preferably in contact with the upper surface of the oxide 230 and the lower surface of the conductor 242b.

[0525] The oxide 243 preferably has a function of suppressing oxygen permeation. By disposing the oxide 243 having a function of suppressing oxygen permeation between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230, the electrical resistance between the conductor 242 and the oxide 230 is reduced, which is preferable. With such a structure, the electrical characteristics, field-effect mobility, and reliability of the transistor 200 can be improved in some cases.

[0526] Alternatively, a metal oxide containing element M may be used as the oxide 243. In particular, aluminum, gallium, yttrium, or tin may be used as the element M. Preferably, the oxide 243 has a higher concentration of element M than the oxide 230. Alternatively, gallium oxide may be used as the oxide 243. Alternatively, a metal oxide such as In-M-Zn oxide may be used as the oxide 243. Specifically, the atomic ratio of element M to In in the metal oxide used for the oxide 243 is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230. The thickness of the oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. Preferably, the oxide 243 has crystallinity. When the oxide 243 has crystallinity, oxygen release from the oxide 230 can be effectively suppressed. For example, if the oxide 243 has a crystal structure such as a hexagonal crystal structure, oxygen release from the oxide 230 may be effectively suppressed.

[0527] <Semiconductor Device Variation 3> The semiconductor device illustrated in FIGS. 30A to 30D is a variation of the semiconductor device illustrated in FIGS. 14A to 14D . The semiconductor device illustrated in FIGS. 30A to 30D differs from the semiconductor device illustrated in FIGS. 14A to 14D in that the insulator 283 is in contact with part of the top surface of the insulator 212. Therefore, the transistor 200 is disposed in a region sealed with the insulator 283 and the insulator 212. This configuration can prevent hydrogen contained outside the sealed region from entering the sealed region. Although the transistor 200 illustrated in FIGS. 30A to 30D has a configuration in which the insulators 212 and 283 are provided as single layers, the present invention is not limited thereto. For example, the insulators 212 and 283 may each have a stacked structure of two or more layers.

[0528] OS transistors such as the transistor 200 have small changes in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. For example, OS transistors can be suitably used in outer space. Specifically, OS transistors can be used as transistors for semiconductor devices installed in space shuttles, artificial satellites, space probes, and the like. Examples of radiation include X-rays and neutron rays. Although outer space refers to an altitude of 100 km or higher, the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0529] <Application Example of Semiconductor Device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS.

[0530] FIG. 31A shows a top view of the semiconductor device 500. The x-axis in FIG. 31A is parallel to the channel length direction of the transistor 200, and the y-axis is perpendicular to the x-axis. FIG. 31B is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in FIG. 31A and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 31C is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in FIG. 31A and is also a cross-sectional view of the opening region 400 and its vicinity. Note that some elements are omitted from the top view in FIG. 31A for clarity.

[0531] 31A to 31C, structures having the same functions as those constituting the semiconductor device shown in <Configuration example of semiconductor device> are denoted by the same reference numerals. Note that, in this section as well, the materials described in detail in <Configuration example of semiconductor device> can be used as the constituent materials of the semiconductor device.

[0532] 31A to 31C is a modified example of the semiconductor device shown in Figures 14A to 14D. The semiconductor device 500 shown in Figures 31A to 31C differs from the semiconductor device shown in Figures 14A to 14D in that an opening region 400 is formed in the insulator 282 and the insulator 280. The semiconductor device 500 also differs from the semiconductor device shown in Figures 14A to 14D in that a sealing portion 265 is formed so as to surround the multiple transistors 200.

[0533] The semiconductor device 500 has a plurality of transistors 200 and a plurality of opening regions 400 arranged in a matrix. Furthermore, a plurality of conductors 260 functioning as gate electrodes of the transistors 200 are provided extending in the y-axis direction. The opening regions 400 are formed in regions that do not overlap with the oxide 230 and the conductors 260. Furthermore, a sealing portion 265 is formed so as to surround the plurality of transistors 200, the plurality of conductors 260, and the plurality of opening regions 400. Note that the number, arrangement, and size of the transistors 200, the conductors 260, and the opening regions 400 are not limited to the structure shown in FIG. 31 , and may be set appropriately in accordance with the design of the semiconductor device 500.

[0534] As shown in FIGS. 31B and 31C , the sealing portion 265 is provided to surround the multiple transistors 200, the insulators 216, 222, 275, 280, and 282. In other words, the insulator 283 is provided to cover the insulators 216, 222, 275, 280, and 282. Furthermore, in the sealing portion 265, the insulator 283 is in contact with the upper surface of the insulator 214. Furthermore, above the sealing portion 265, an insulator 274 is provided between the insulators 283 and 285. The upper surface of the insulator 274 is flush or approximately flush with the uppermost surface of the insulator 283. Furthermore, the insulator 274 may be made of the same insulator as the insulator 280.

[0535] With this structure, the multiple transistors 200 can be enclosed by the insulators 283, 214, and 212. Here, it is preferable that one or more of the insulators 283, 214, and 212 function as a barrier insulating film against hydrogen. This can prevent hydrogen contained outside the region of the sealing portion 265 from mixing into the region of the sealing portion 265.

[0536] 31C , insulator 282 has an opening in opening region 400. In addition, insulator 280 may have a groove in opening region 400, overlapping the opening of insulator 282. The depth of the groove in insulator 280 may be at most deep enough to expose the top surface of insulator 275, and may be, for example, approximately ¼ to ½ of the maximum film thickness of insulator 280.

[0537] 31C , insulator 283 contacts the side surface of insulator 282, the side surface of insulator 280, and the top surface of insulator 280 inside opening region 400. In addition, a portion of insulator 274 may be formed within opening region 400 so as to fill a recess formed in insulator 283. In this case, the height of the top surface of insulator 274 formed within opening region 400 may coincide or approximately coincide.

[0538] By performing heat treatment in a state where the opening region 400 is formed and the insulator 280 is exposed through the opening of the insulator 282, oxygen can be supplied to the oxide 230 while some of the oxygen contained in the insulator 280 diffuses outward from the opening region 400. This allows sufficient oxygen to be supplied from the insulator 280 containing oxygen released by heating to a region in the oxide semiconductor layer that functions as a channel formation region and its vicinity, while preventing excessive oxygen from being supplied.

[0539] At this time, the hydrogen contained in the insulator 280 can be bonded with oxygen and released to the outside through the opening region 400. The hydrogen bonded with oxygen is released as water. Therefore, the hydrogen contained in the insulator 280 can be reduced, and the hydrogen contained in the insulator 280 can be prevented from mixing with the oxide 230.

[0540] 31A, the shape of the opening region 400 in a top view is substantially rectangular, but the present invention is not limited to this. For example, the shape of the opening region 400 in a top view may be rectangular, elliptical, circular, diamond-shaped, or a combination thereof. The area and spacing of the opening regions 400 can be appropriately set in accordance with the design of the semiconductor device including the transistors 200. For example, in a region where the density of the transistors 200 is low, the area of ​​the opening regions 400 can be increased or the spacing between the opening regions 400 can be narrowed. For example, in a region where the density of the transistors 200 is high, the area of ​​the opening regions 400 can be narrowed or the spacing between the opening regions 400 can be widened.

[0541] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high field-effect mobility can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0542] At least part of the structures, methods, and the like described in this embodiment mode can be implemented in appropriate combination with other embodiment modes and examples described in this specification.

[0543] Embodiment 3 In this embodiment, one mode of a semiconductor device will be described with reference to FIGS. 32 to 36. Note that the semiconductor device described in this embodiment can be rephrased as a memory device in some cases. In addition, since a memory device is one mode of a semiconductor device in this specification and the like, the memory device described in this embodiment can also be rephrased as a semiconductor device.

[0544] 32 illustrates an example of a memory device of one embodiment of the present invention. In the memory device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0545] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a memory device, the stored data can be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced.

[0546] 32 , a wiring 1001 is electrically connected to the source of a transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of a transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of a capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0547] Moreover, the memory device shown in FIG. 32 can be arranged in a matrix to form a memory cell array.

[0548] The transistor 300 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel or n-channel transistor.

[0549] Here, in the transistor 300 shown in FIG. 32 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Although the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0550] Note that the transistor 300 illustrated in FIG. 32 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0551] <Capacitor 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, the insulator 130 is preferably the same as the insulator 283 described in the above embodiment.

[0552] For example, the conductor 110 and the conductor 112 provided over the conductor 240 can be formed simultaneously. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0553] 32, the conductor 112 and the conductor 110 are shown as having a single-layer structure, but are not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0554] The insulator 130 can be made using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be formed as a stacked layer or a single layer.

[0555] For example, it is preferable to use a layered structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitor 100 can improve the dielectric strength by having an insulator with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitor 100.

[0556] Examples of high dielectric constant (high-k) materials (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0557] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0558] <Wiring Layer> A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Here, for conductors that function as plugs or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a portion of the conductor functions as the wiring, and cases where a portion of the conductor functions as the plug.

[0559] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330 electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0560] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0561] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 32, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0562] Similarly, a conductor 218, a conductor (conductor 205) constituting the transistor 200, and the like are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0563] Here, similar to the insulator 241 described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. That is, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0564] The insulator 217 may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 217 is provided in contact with the insulators 210, 212, 214, and 222, and therefore can prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from mixing into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, the insulator 217 can prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0565] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0566] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0567] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0568] For example, the insulators 150, 210, 352, and 354 preferably have an insulator with a low dielectric constant. For example, the insulator preferably includes fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, resin, or the like. Alternatively, the insulator preferably has a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

[0569] Furthermore, when a transistor including an oxide semiconductor is surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, the insulators 214, 212, 350, and the like can be insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0570] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0571] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0572] For example, the conductors 328, 330, 356, conductor 218, and 112 can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, they are preferably formed using a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance.

[0573] <Wiring or Plug in Layer Including Oxide Semico...

Claims

1. A first conductor; a first insulator on the first conductor; and a second insulator on the first insulator; and a third insulator, a fourth insulator, and a fifth insulator on the second insulator; an oxide on the third insulator, on the fourth insulator, and on the fifth insulator; a second conductor and a third conductor on the oxide; a sixth insulator on the second conductor and on the third conductor; and a seventh insulator on the sixth insulator; and an eighth insulator on the oxide; and a ninth insulator on the eighth insulator; and a fourth conductor on the ninth insulator; and a tenth insulator on the seventh insulator, on the eighth insulator, on the ninth insulator, and on the fourth conductor; and having the sixth insulator has a region in contact with a top surface of the first insulator, a side surface of the oxide, a side surface and a top surface of the second conductor, and a side surface and a top surface of the third conductor; the first conductor is disposed to overlap the oxide and the fourth conductor; the third insulator is disposed to overlap the oxide and the fourth conductor; the fourth insulator is disposed to overlap the oxide and the second conductor; the fifth insulator is disposed to overlap the oxide and the third conductor; the eighth insulator contacts each of a side surface of the third insulator, a side surface of the oxide, and a side surface of the seventh insulator; the eighth insulator has a region having a thickness smaller than that of the ninth insulator, an upper surface of the third insulator is flush or approximately flush with an upper surface of the fourth insulator and an upper surface of the fifth insulator; Transistor.

2. In claim 1, an upper surface of the fourth conductor is flush or approximately flush with an upper surface of the seventh insulator; Transistor.

3. In claim 2, an upper surface of the fourth conductor is flush or approximately flush with a top of the eighth insulator and a top of the ninth insulator; Transistor.

4. In any one of claims 1 to 3, the eighth insulator comprises aluminum and oxygen; the eighth insulator has a region having a film thickness of 1.0 nm or more and 3.0 nm or less; Transistor.

5. In any one of claims 1 to 3, each of the first insulator and the sixth insulator comprises silicon and nitrogen; each of the second insulator and the tenth insulator comprises aluminum and oxygen; Each of the third insulator, the seventh insulator, and the ninth insulator comprises silicon and oxygen. Transistor.

6. In any one of claims 1 to 3, an eleventh insulator on the tenth insulator; the eleventh insulator is in contact with a top surface of the first insulator, a side surface of the sixth insulator, a side surface of the seventh insulator, a side surface of the tenth insulator, and a top surface of the tenth insulator; The eleventh insulator comprises silicon and nitrogen. Transistor.

7. A first insulator; a second insulator on the first insulator; and a third insulator, a fourth insulator, and a fifth insulator on the second insulator; an oxide on the third insulator, on the fourth insulator, and on the fifth insulator; a first conductor and a second conductor on the oxide; a sixth insulator on the first conductor and on the second conductor; and a seventh insulator on the sixth insulator; and an eighth insulator on the oxide; and a third conductor on the eighth insulator; and a ninth insulator on the seventh insulator, on the eighth insulator, and on the third conductor; and having the sixth insulator has a region in contact with a top surface of the first insulator, a side surface of the oxide, a side surface and a top surface of the first conductor, and a side surface and a top surface of the second conductor; the third insulator is disposed to overlap the oxide and the third conductor; the fourth insulator is disposed to overlap the oxide and the first conductor; the fifth insulator is disposed to overlap the oxide and the second conductor; the eighth insulator contacts each of a side surface of the third insulator, a side surface of the oxide, and a side surface of the seventh insulator; an upper surface of the third insulator is flush or approximately flush with an upper surface of the fourth insulator and an upper surface of the fifth insulator; Transistor.

8. In claim 7, an upper surface of the third conductor is flush or approximately flush with an upper surface of the seventh insulator; Transistor.

9. In claim 8, The upper surface of the third conductor is flush or approximately flush with the top of the eighth insulator. Transistor.

10. In any one of claims 7 to 9, each of the first insulator and the sixth insulator comprises silicon and nitrogen; each of the second insulator and the ninth insulator comprises aluminum and oxygen; each of the third insulator, the seventh insulator, and the eighth insulator comprises silicon and oxygen; Transistor.

11. In any one of claims 7 to 9, a tenth insulator on the ninth insulator; the tenth insulator is in contact with a top surface of the first insulator, a side surface of the sixth insulator, a side surface of the seventh insulator, a side surface of the ninth insulator, and a top surface of the ninth insulator; The tenth insulator comprises silicon and nitrogen. Transistor.

12. In any one of claims 1 to 3, each of the oxide, the fourth insulator, and the fifth insulator comprises indium, gallium, zinc, and oxygen; an atomic ratio of gallium to indium in the fourth insulator is greater than an atomic ratio of gallium to indium in the oxide; Transistor.

13. In any one of claims 1 to 3, When the oxide is measured by secondary ion mass spectrometry, the hydrogen concentration in the oxide has a region of less than 1×10 19 atoms / cm 3 . Transistor.

14. In any one of claims 7 to 9, each of the oxide, the fourth insulator, and the fifth insulator comprises indium, gallium, zinc, and oxygen; an atomic ratio of gallium to indium in the fourth insulator is greater than an atomic ratio of gallium to indium in the oxide; Transistor.

15. In any one of claims 7 to 9, When the oxide was measured by secondary ion mass spectrometry, the hydrogen concentration in the oxide was 1×10 １９ atoms / cm ３ having an area that is less than Transistor.