SiC JUNCTION FIELD EFFECT TRANSISTOR AND SiC COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR

Abstract

A SiC junction field effect transistor comprises: a SiC substrate 10; a first conduction-type channel region 11 that is formed on a main surface of the SiC substrate; a second conduction-type embedded gate region 14 that is formed below the channel region on the main surface side of the SiC substrate; and a first conduction-type source region 12 and drain region 13 that are formed so as to sandwich the channel region on the main surface of the SiC substrate.

Description

SiC junction field effect transistor and SiC complementary junction field effect transistor

[0001] The present invention relates to a SiC junction field effect transistor (hereinafter referred to as "SiC JFET") formed using a silicon carbon (SiC) substrate, and a SiC complementary junction field effect transistor (hereinafter referred to as "SiC complementary JFET") including an n-channel JFET and a p-channel JFET configured with this SiC JFET.

[0002] Currently, semiconductor integrated circuits are mainly made of silicon (Si), but in the industrial field, there is a strong demand for integrated circuits that can operate at high temperatures of 200°C or higher, which is not possible with Si, for applications such as engine control in automobiles and aircraft, automobile tire monitors, and space electronics.

[0003] Since SiC has a band gap approximately three times higher than that of Si, it is possible to fabricate integrated circuits that operate in high-temperature environments of 500° C. or higher.

[0004] As an example of an integrated circuit fabricated using a SiC substrate, Non-Patent Document 1 discloses an integrated circuit configured with complementary MOSFETs. Patent Document 1 also discloses a complementary JFET in which an n-channel JFET and a p-channel JFET are insulated and separated by a semi-insulating SiC layer.

[0005] JP 2011-166025 A

[0006] SH Ryu et al., IEEE Trans. Electron Devices, vol.45 (1998), p.45.

[0007] However, the complementary MOSFET disclosed in Non-Patent Document 1 has a problem that the threshold voltage varies greatly with temperature due to the presence of high density defects and charges at the interface between the SiC substrate and the gate oxide film, preventing stable operation. There is also a problem that the gate oxide film deteriorates at high temperatures.

[0008] Furthermore, the complementary JFET disclosed in Patent Document 1 has a structure in which an n-channel JFET and a p-channel JFET are insulated and separated by an intrinsic SiC layer formed by a hot wall CVD method, and since it is necessary to repeat fine trench formation, embedding growth, and surface planarization polishing, there is a problem in that the manufacturing process becomes very complicated.

[0009] To date, several studies have been reported on integrated circuits using SiC substrates, but only confirmed high-temperature operation. However, all of these have left issues such as instability at high temperatures and difficulty in fabricating complementary logic circuits, and have not yet reached a level where they can be put to practical use.

[0010] The present invention has been made in view of the above-mentioned problems, and a main object of the present invention is to provide a SiC junction field effect transistor that can operate stably at high temperatures and that is easy to fabricate as a complementary JFET.

[0011] The SiC junction field effect transistor according to the present invention includes a SiC substrate, a channel region of a first conductivity type formed on a main surface of the SiC substrate, a buried gate region of a second conductivity type formed on the main surface side of the SiC substrate below the channel region, and a source region and a drain region of the first conductivity type formed on the main surface of the SiC substrate on either side of the channel region.

[0012] The SiC complementary junction field effect transistor according to the present invention is a SiC complementary junction field effect transistor in which an n-channel junction field effect transistor and a p-channel junction field effect transistor are formed on a SiC substrate, and the n-channel junction field effect transistor and the p-channel junction field effect transistor are each formed of the above-mentioned normally-off SiC junction field effect transistor, and the n-channel junction field effect transistor and the p-channel junction field effect transistor are formed in the SiC substrate in a spaced-apart and electrically insulated state from each other.

[0013] Another SiC junction field effect transistor according to the present invention includes a SiC substrate, a buried channel region of a first conductivity type formed below and spaced apart from a main surface of the SiC substrate, a buried gate region of a second conductivity type formed below the buried channel region, and a source region and a drain region of the first conductivity type formed on the main surface of the SiC substrate, sandwiching the buried channel region.

[0014] According to the present invention, it is possible to provide a SiC junction field effect transistor that can operate stably at high temperatures and that is easy to fabricate as a complementary JFET.

[0015] FIG. 1A is a plan view schematically illustrating the configuration of a SiC JFET according to a first embodiment of the present invention. FIG. 1B is a cross-sectional view taken along line IB-IB in FIG. 1A. FIG. 1C is a cross-sectional view taken along line IC-IC in FIG. 1A. FIG. 2A is a graph obtained by simulation of the impurity density profile in the depth direction from the surface of the channel region in an n-channel JFET according to this embodiment, when the channel region and buried gate region are formed by ion implantation. FIG. 2B is a graph showing the results of measuring the impurity density profile using SIMS when the channel region and buried gate region are formed under the ion implantation conditions specified in FIG. 2A. FIG. 3A is a graph showing the results of measuring the drain current-drain voltage characteristics of an n-channel SiC JFET. FIG. 3B is a graph showing the results of measuring the drain current-drain voltage characteristics of a p-channel SiC JFET. FIG. 4 is a circuit diagram of an inverter circuit composed of SiC complementary JFETs constructed using SiC JFETs. FIG. 5 is a cross-sectional view schematically illustrating the structure of SiC complementary JFETs constituting an inverter circuit. FIG. 6A is a cross-sectional view schematically showing a modified example of a SiC complementary JFET constituting an inverter circuit. FIG. 6B is a cross-sectional view taken along line VIB-VIB in FIG. 6A. FIG. 7A is a plan view schematically showing the configuration of a SiC JFET according to a second embodiment of the present invention. FIG. 7B is a cross-sectional view taken along line VIIB-VIIB in FIG. 7A. FIG. 7C is a cross-sectional view taken along line VIIC-VIIC in FIG. 7A. FIG. 8 is a cross-sectional view schematically showing the structure of a SiC complementary JFET constituting an inverter circuit. FIG. 9A is a cross-sectional view schematically showing another configuration of a SiC complementary JFET constituting an inverter circuit. FIG. 9B is a cross-sectional view taken along line IXB-IXB in FIG. 9A. FIG. 10A is a plan view schematically showing the configuration of a SiC JFET according to a modified example of the second embodiment. FIG. 10B is a cross-sectional view taken along line XB-XB in FIG. 10A. FIG. 10C is a cross-sectional view taken along line XC-XC in FIG. 10A. Fig. 11 is a cross-sectional view showing a typical structure of a SiC JFET in another modified example, and Fig. 12 is a cross-sectional view showing the structure of a SiC JFET disclosed in a previous application by the applicant of the present application.Fig. 13A is a graph showing a simulated impurity density profile in the depth direction from the surface of the channel region when the channel region and the buried gate region are formed by ion implantation in the n-channel JFET shown in Fig. 12. Fig. 13B is a graph showing the results of measuring the impurity density profile using SIMS when the channel region and the buried gate region are formed under the ion implantation conditions set in Fig. 13A.

[0016] The applicant of the present application has disclosed in the specification of a previous application (JP 2017-212397 A) a structure of a SiC JFET that operates normally-off over a wide range of gate voltages. Figure 12 is a cross-sectional view showing an example of the structure of the SiC JFET disclosed in that specification. Here, an n-channel JFET is shown, but a p-channel JFET also has a similar structure.

[0017] As shown in FIG. 12, the SiC JFET disclosed in the above specification comprises an n-type buried channel region 111 formed on the main surface side of a SiC substrate 110 and a p-type buried channel region 112 formed on the buried channel region 111. ＋ A gate region 114 of the n type and a gate region 114 of the n type formed on both sides of the gate region 114 ＋ The gate electrode 111 is made up of a source region 112 and a drain region 113 .

[0018] The threshold voltage V of the SiC JFET having such a configuration ｔｈ In the case of an n-channel SiC JFET, the threshold voltage V can be expressed by the following equation (1) using a depletion layer analysis model of a semiconductor pn junction. ｔｈ can also be expressed by a similar formula.

[0019]

[0020] where k is the Boltzmann constant, n is the electron density of the buried channel region 111, p is the hole density of the gate region 114, and n ｉ is the intrinsic carrier density, q is the electron charge, ε ｓ is the dielectric constant of SiC, N is the impurity concentration of the buried channel region 111, and a is the thickness of the buried channel region 111 immediately below the gate region 114.

[0021] As shown in equation (1), the threshold voltage V of the SiC JFET ｔｈ can be controlled by adjusting the impurity concentration N and thickness a of the buried channel region 111 immediately below the gate region 114. ｔｈ By setting the impurity density N and thickness a of the buried channel region 111 to predetermined values ​​so that becomes positive, a normally-off operating SiC JFET can be realized.

[0022] A SiC complementary JFET having an n-channel SiC JFET and a p-channel SiC JFET that operate normally off can be easily fabricated by forming a buried channel region 111, a gate region 114, a source region 112, and a drain region 113 of different conductivity types in the same SiC substrate 110 by ion implantation.

[0023] FIG. 13A shows an n-channel SiC JFET with an n-type buried channel region 111 and a p ＋ 13A is a graph showing a simulated profile of impurity density in the depth direction from the surface of gate region 114 when gate regions 114 are formed by ion implantation. Here, the graph indicated by arrow A shows the profile of buried channel region 111, and the graph indicated by arrow B shows the profile of gate region 114. In FIG. 13A , the region indicated by arrow P is buried channel region 111. The simulation was performed using simulation software SRIM (Stopping and Range In Matter), which calculates the distribution of implanted ions using the Monte Carlo method.

[0024] The ion implantation conditions (dose and acceleration energy) are set to the target threshold voltage V ｔｈ The impurity density N and thickness a of the buried channel region 111 are set to predetermined values ​​so that the following can be obtained. Here, P (phosphorus) is used as the impurity for the n-type buried channel region 111, and p ＋ The impurity of the mold gate region 114 is Al (aluminum).

[0025] In ion implantation, when a dopant such as P or Al is implanted as an ion beam along a specific crystal direction of a SiC substrate, a channeling phenomenon occurs in which the implanted atoms reach deeper positions compared to when the ion beam is not implanted along the crystal direction. This channeling phenomenon affects the impurity density profile.

[0026] One method for suppressing the effects of the channeling phenomenon is to slightly tilt the angle of ion implantation relative to the SiC substrate, but even if this method is adopted, it is difficult to prevent a large number of implanted atoms from reaching a position deeper than the peak of the impurity density profile.

[0027] 13B is a graph showing the results of measuring the impurity density profile using SIMS (Secondary Ion Mass Spectrometry) when the buried channel region 111 and the gate region 114 are formed under the ion implantation conditions determined in FIG. 13A. Here, the graph indicated by arrow A shows the profile of the buried channel region 111, and the graph indicated by arrow B shows the profile of the gate region 114. In FIG. 13B, the region indicated by arrow P becomes the buried channel region 111.

[0028] 13B, both the buried channel region 111 and the gate region 114 are formed with their bases widened at positions deeper than the peaks. Therefore, impurities from the base of the high-density gate region 114 penetrate into the low-density buried channel region 111, so that the impurity density N of the buried channel region 111 is significantly reduced from the design value, while the thickness a of the buried channel region 111 is significantly increased from the design value.

[0029] In this way, the actual impurity density N and thickness a of the buried channel region 111 are significantly different from the design values. Therefore, when designing the structure of the SiC JFET, the threshold voltage V ｔｈ It becomes difficult to control the value according to the design value.

[0030] The inventors of the present invention have considered a structure in which the impurity density profile in the buried channel region 111 is not affected by the channeling phenomenon even when the buried channel region 111 and the gate region 114 are formed by ion implantation, and have arrived at the present invention.

[0031] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiment. Furthermore, appropriate modifications are possible within the scope of the effects of the present invention.

[0032] 1A to 1C are diagrams showing the configuration of a SiC JFET according to a first embodiment of the present invention, with Fig. 1A being a plan view, Fig. 1B being a cross-sectional view taken along line IB-IB in Fig. 1A, and Fig. 1C being a cross-sectional view taken along line IC-IC in Fig. 1A. An n-channel SiC JFET is shown here.

[0033] As shown in FIGS. 1A to 1C, the SiC JFET of this embodiment includes a semi-insulating SiC substrate 10, an n-type (first conductivity type) channel region 11 formed on the main surface of the semi-insulating SiC substrate 10, and a p-type (first conductivity type) channel region 11 formed on the main surface side of the semi-insulating SiC substrate 10 below the channel region 11. ＋ a buried gate region 14 of a second conductivity type and a n-type (n-type) buried gate region 14 formed on the main surface of the semi-insulating SiC substrate 10 with a channel region 11 interposed therebetween; ＋ The semi-insulating SiC substrate 10 has a source region 12 and a drain region 13 of a first conductivity type. In this embodiment, the term "main surface" refers to the largest surface among the surfaces constituting the semi-insulating SiC substrate 10.

[0034] Here, the impurity concentration of the channel region 11 is set to be lower than the impurity concentration of the buried gate region 14. Moreover, the channel region 11, the buried gate region 14, the source region 12, and the drain region 13 are all formed of ion-implanted layers.

[0035] 1A and 1C, a p ＋A gate contact region 15 of a second conductivity type is formed, and the buried gate region 14 extends to directly below the gate contact region 15 and is connected to the gate contact region 15 .

[0036] 1A to 1C, a semi-insulating SiC substrate 10 is used as the SiC substrate 10, but a SiC substrate 10 having a p-type epitaxial layer formed on the surface may also be used. In this case, the channel region 11, the buried gate region 14, the source region 12, and the drain region 13 are formed in the p-type epitaxial layer.

[0037] In the p-channel SiC JFET, the channel region 11 is p-type and the buried gate region 14 is n-type. ＋ The source region 12 and the drain region 13 are p ＋ The gate contact region 15 is ＋ It can be formed by changing the mold.

[0038] The threshold voltage V of the SiC JFET in this embodiment ｔｈ In the case of an n-channel SiC JFET, the impurity concentration of the channel region 11 is N Ｄ , the impurity concentration of the buried gate region 14 is N Ａ When the thickness of the channel region 11 is a, it can be expressed by the following formula (2).

[0039]

[0040] where k is the Boltzmann constant, n is the electron density in the channel region 11, p is the hole density in the buried gate region 14, and n ｉ is the intrinsic carrier density, q is the electron charge, ε ｓ is the dielectric constant of SiC. The threshold voltage V ｔｈ can also be expressed by a similar formula.

[0041] In the SiC JFET of this embodiment, a P ＋ The buried gate region 14 is formed as an ion-implanted layer. Therefore, the impurity density of the buried gate region 14 is NＤ Therefore, the above formula (2) is based on the impurity density of the channel region 11 being N Ｄ and the impurity concentration N Ａ This formula takes into account cases where the difference between Ｄ <N Ａ In the case of ｔｈ can be calculated using the above formula (1).

[0042] As shown in equation (2), the threshold voltage V of the SiC JFET ｔｈ is the impurity concentration N Ｄ and thickness a, and the impurity density N Ａ It can be controlled by adjusting the threshold voltage V ｔｈ The impurity density N Ｄ and thickness a, and the impurity density N Ａ By setting the value to a predetermined value, a SiC JFET that operates normally off can be realized.

[0043] FIG. 2A shows an n-channel JFET with an n-type channel region 11 and a p ＋ 2A and 2B are graphs showing the impurity density profile in the depth direction from the surface of the channel region 11 when the buried gate regions 14 are formed by ion implantation. The graph indicated by arrow A shows the profile of the channel region 11, and the graph indicated by arrow B shows the profile of the buried gate region 14. In FIG. 2A , the region indicated by arrow P is the channel region 11. The simulation was performed using simulation software SRIM (Stopping and Range In Matter), which calculates the distribution of implanted ions using the Monte Carlo method.

[0044] The ion implantation conditions (dose and acceleration energy) are set to the target threshold voltage V ｔｈ The impurity density N Ｄ and thickness a, and the impurity density NＡ Here, P (phosphorus) is used as the impurity for the n-type channel region 11, and p ＋ The impurity for the buried gate region 14 of the mold was Al (aluminum).

[0045] 2B is a graph showing the results of measuring the impurity density profile using SIMS (Secondary Ion Mass Spectrometry) when the channel region 11 and the buried gate region 14 are formed under the ion implantation conditions defined in FIG. 2A. Here, the graph indicated by arrow A shows the profile of the channel region 11, and the graph indicated by arrow B shows the profile of the buried gate region 14. In FIG. 2B, the region indicated by arrow P becomes the channel region 11.

[0046] As shown in Figure 2B, both the channel region 11 and the buried gate region 14 are formed with their bases widened at positions deeper than the peak, but the impurity density profiles of the channel region 11 and the buried gate region 14 at positions shallower than the peak are almost the same as the profiles shown in Figure 2A. Ｄ and thickness a, and the impurity density N Ａ is almost the same as the design value shown in FIG. 2A. Therefore, when designing the structure of the SiC JFET, the threshold voltage V ｔｈ can be controlled according to the design value.

[0047] 2A and 2B, the impurity density N Ｄ , the impurity concentration N Ａ However, regardless of the magnitude relationship between the impurity densities of the two, the actual impurity density N Ｄ and thickness a, and the impurity density N Ａ However, the fact remains that the results are almost identical to the design values.

[0048] According to this embodiment, by forming the buried gate region 14 below the channel region 11, even if the channel region 11 and the buried gate region 14 are made of ion-implanted layers, the threshold voltage V of the SiC JFET is not affected by the channeling phenomenon. ｔｈ Since the channel region 11, the buried gate region 14, the source region 12, and the drain region 13 are all formed from ion-implanted layers, complementary JFETs can be easily fabricated on the same SiC substrate 10.

[0049] 3A shows the results of measuring the drain current-drain voltage characteristics of an n-channel SiC JFET fabricated with the configuration shown in FIGS. 1A to 1C. The measurements were carried out at a temperature of 300 K. The ion-implanted layers were formed under the following conditions, and annealing after ion implantation was carried out at 1650° C. The ion implantation was carried out with the acceleration energy changed in multiple stages (multi-stage implantation). The length of the channel region 11 was 50 μm, and the width of the channel region 11 was 100 μm.

[0050] <Channel region 11> Impurity: P, total dose: 1.57×10 １３ cm －２ , acceleration energy: 10-170 keV (multi-stage implantation) <Buried gate region 14> Impurity: Al, total dose: 2.30×10 １３ cm －２ , acceleration energy: 450-520 keV (multi-stage implantation) <Source / drain regions 12, 13> Impurity: P, total dose: 4.23×10 １５ cm －２ , acceleration energy: 10-600 keV (multi-stage implantation) The n-channel SiC JFET fabricated under the above conditions has an impurity density of 5×10 in the channel region 11. １７ cm －３ The impurity density of the buried gate region 14 is 1×10 １８ cm －３ The thickness a of the channel region 11 was 281 nm.

[0051] As shown in Figure 3A, the fabricated n-channel SiC JFET exhibited good drain current-drain voltage characteristics. ｔｈ The difference from the design value (-50.6 V) was only 0.1 V.

[0052] 3B shows the results of measuring the drain current-drain voltage characteristics of a p-channel SiC JFET fabricated with the configuration shown in FIGS. 1A to 1C. The measurements were carried out at a temperature of 300 K. The ion-implanted layers were formed by multi-stage implantation under the following conditions, and annealing after the ion implantation was carried out at 1650° C. The length of the channel region 11 was 50 μm, and the width of the channel region 11 was 100 μm.

[0053] <Channel region 11> Impurity: Al, total dose: 1.6×10 １３ cm －２ , acceleration energy: 10-220 keV (multi-stage implantation) <Buried gate region 14> Impurity: P, total dose: 2×10 １３ cm －２ , acceleration energy: 600-650 keV (multi-stage implantation) <Source / drain regions 12, 13> Impurity: Al, total dose: 3.67×10 １５ cm －２ , acceleration energy: 10-450 keV (multi-stage implantation) The p-channel SiC JFET fabricated under the above conditions has an impurity density of 5×10 in the channel region 11. １７ cm －３ The impurity density of the buried gate region 14 is 1×10 １８ cm －３ The thickness a of the channel region 11 was 281 nm.

[0054] (SiC Complementary JFET) FIG. 4 is a circuit diagram showing an example of an inverter circuit configured using SiC complementary JFETs constructed using the SiC JFET of this embodiment. ｒ１ is a normally-off n-channel JFET, T ｒ２ is a normally-off type p-channel JFET. The gate electrodes G of the n-channel JFET and the p-channel JFET are connected to the input terminal V of the inverter circuit. ｉｎThe drain electrodes D of the n-channel JFET and the p-channel JFET are connected to the output terminal V of the inverter circuit. out The source electrode S of the n-channel JFET is connected to the ground, and the source electrode S of the p-channel JFET is connected to the power supply (V ＤＤ ) is connected.

[0055] FIG. 5 is a cross-sectional view showing a schematic structure of the SiC complementary JFETs that constitute this inverter circuit.

[0056] As shown in FIG. 5, an n-channel JFET (T ｒ１ ) formation region, an n-type channel region 11 is formed, and a p-channel JFET (T ｒ２ A p-type channel region 11 is formed in each of the n-type and n-type semiconductor layers 11a and 11b. ＋ A buried gate region 14 of the n-type is formed on both sides of the channel region 11. ＋ A p-type source region 12 and a drain region 13 are formed. ＋ A buried gate region 14 of p type is formed, sandwiching the channel region 11. ＋ A source region 12 and a drain region 13 are formed.

[0057] In this embodiment, the channel region 11, the buried gate region 14, the source region 12, and the drain region 13 are all formed by ion implantation, so that complementary JFETs can be easily fabricated on the same SiC substrate 10. Furthermore, the n-channel JFET and the p-channel JFET are formed spaced apart from each other in the semi-insulating SiC substrate 10, so that electrical isolation between the n-channel JFET and the p-channel JFET can be easily achieved. In addition, the impurity density N and thickness a of the channel region 11 can be set by adjusting the acceleration energy and dose of the ion implantation, so that the JFET can easily be made normally off.

[0058] In this embodiment, the semi-insulating SiC substrate 10 may have a high resistance enough to electrically isolate the n-channel JFET and the p-channel JFET from each other. ９ A SiC substrate 10 having a resistivity of Ωcm or more can be used.

[0059] 6A and 6B are cross-sectional views schematically showing a modified example of a SiC complementary JFET constructed using the SiC JFET of this embodiment, where Fig. 6A is a plan view and Fig. 6B is a cross-sectional view taken along line VIB-VIB of Fig. 6A.

[0060] The SiC complementary JFET in this modification is a p-channel JFET formed on a SiC substrate 10, in which an n-channel JFET and a p-channel JFET having the structures shown in FIGS. 1A to 1C are formed. － The lightly doped epitaxial layer 20 is formed on the substrate.

[0061] As shown in FIGS. 6A and 6B, in the SiC complementary JFET of this modification, p － Two n-type well regions 21 are formed in a low-concentration epitaxial layer 20, spaced apart from each other. A p-type well region 22 is further formed in one of the well regions 21, and an n-channel JFET is formed in this well region 22. A p-channel JFET is formed in the other well region 21. As a result, the n-channel JFET and the p-channel JFET are connected to each other via a p-type well region 22. － By applying a reverse bias to the pn junction between the low concentration epitaxial layer 20 and the n-type well region 21, they can be electrically isolated from each other.

[0062] On the SiC substrate 10, n － Even if a low concentration epitaxial layer of the same type is formed, by changing the conductivity type of the well regions 21 and 22, a SiC complementary JFET of the same configuration can be formed.

[0063] 7A to 7C are diagrams showing the configuration of a SiC JFET according to a second embodiment of the present invention, where Fig. 7A is a plan view, Fig. 7B is a cross-sectional view taken along line VIIB-VIIB in Fig. 7A, and Fig. 7C is a cross-sectional view taken along line VIIC-VIIC in Fig. 7A. An n-channel SiC JFET is shown here.

[0064] In the SiC JFET of the first embodiment, as shown in FIGS. 1A to 1C, an n-type (first conductivity type) channel region 11 is formed in the main surface of the semi-insulating SiC substrate 10, but in the SiC JFET of this embodiment, as shown in FIGS. 7A to 7C, an n-type (first conductivity type) buried channel region 11 is formed at a position spaced downward from the main surface of the semi-insulating SiC substrate 10.

[0065] In this embodiment, similarly to the first embodiment, p ＋ A buried gate region 14 of a second conductivity type is formed on the main surface of the semi-insulating SiC substrate 10, and the buried channel region 11 is sandwiched between the n-type and n-type buried gate regions 14. ＋ A source region 12 and a drain region 13 of a first conductivity type are formed.

[0066] In addition, p ＋ A gate contact region 15 of a second conductivity type is formed, and the buried gate region 14 extends to directly below the gate contact region 15 and is connected to the gate contact region 15 .

[0067] When a channel region 11 is formed on the main surface of the SiC substrate 10, if charges exist on the surface of the SiC substrate 10, the depletion layer in the channel region 11 may unintentionally extend when a voltage is applied to the buried gate region 14, causing the threshold voltage V ｔｈ In this embodiment, the buried channel region 11 is formed at a position below and away from the main surface of the SiC substrate 10, so that the threshold voltage V ｔｈ This can suppress variations in the

[0068] Here, the depth of the buried channel region 11 from the main surface of the SiC substrate 10 may be determined appropriately depending on the amount of charge present on the surface of the SiC substrate 10. Typically, the buried channel region 11 may be formed 3 to 500 nm below the main surface of the SiC substrate 10, more preferably 20 to 300 nm below. If the buried channel region 11 is formed at a position shallower than 3 nm from the main surface of the SiC substrate 10, it becomes difficult to avoid the influence of the charge present on the surface of the SiC substrate 10. Furthermore, if the buried channel region 11 is formed at a position deeper than 500 nm from the main surface of the SiC substrate 10, the buried gate region 14 must be formed at an even deeper position, which increases the energy of ion implantation and leads to increased costs.

[0069] In this embodiment, as in the first embodiment, the buried gate region 14 is formed below the buried channel region 11, so that even if the buried channel region 11 and the buried gate region 14 are made of ion-implanted layers, the threshold voltage V of the SiC JFET is not affected by the channeling phenomenon. ｔｈ Since the impurity concentration of the buried channel region 11 can be controlled exactly as designed, a SiC JFET capable of stable operation at high temperatures can be realized. It is preferable that the impurity concentration of the buried channel region 11 is set to be lower than the impurity concentration of the buried gate region 14.

[0070] It is also preferable that the buried channel region 11, the buried gate region 14, the source region 12, and the drain region 13 are all formed of ion-implanted layers, which makes it possible to easily fabricate complementary JFETs on the same SiC substrate 10.

[0071] In addition, the threshold voltage V of the SiC JFET ｔｈ is the impurity concentration N of the buried channel region 11 Ｄ and thickness a, and the impurity density N Ａ It can be controlled by adjusting the threshold voltage V ｔｈ The impurity density N Ｄ and thickness a, and the impurity density N ＡBy setting the value to a predetermined value, a SiC JFET that operates normally off can be realized.

[0072] FIG. 8 is a cross-sectional view showing a schematic structure of a SiC complementary JFET in which the inverter circuit shown in FIG. 4 is configured using the SiC JFET of this embodiment.

[0073] As shown in FIG. 8, an n-channel JFET (T ｒ１ ) forming region, an n-type buried channel region 11 is formed, and a p-channel JFET (T ｒ２ A p-type buried channel region 11 is formed in each of the n-type buried channel regions 11. ＋ A buried gate region 14 of the n-type is formed, sandwiching the buried channel region 11. ＋ A p-type source region 12 and a drain region 13 are formed. ＋ A buried gate region 14 of a p type is formed, sandwiching the buried channel region 11. ＋ A source region 12 and a drain region 13 are formed.

[0074] In this embodiment, the buried channel region 11, the buried gate region 14, the source region 12, and the drain region 13 are all formed by ion implantation, so that complementary JFETs can be easily fabricated in the same SiC substrate 10. Furthermore, the n-channel JFET and the p-channel JFET are formed spaced apart from each other in the semi-insulating SiC substrate 10, so that electrical isolation between the n-channel JFET and the p-channel JFET can be easily achieved. In addition, the impurity density N and thickness a of the buried channel region 11 can be set by adjusting the acceleration energy and dose of the ion implantation, so that the JFET can easily be made normally off.

[0075] In this embodiment, the semi-insulating SiC substrate 10 may have a high resistance enough to electrically isolate the n-channel JFET and the p-channel JFET from each other. ９ A SiC substrate 10 having a resistivity of Ωcm or more can be used.

[0076] 9A and 9B are cross-sectional views schematically showing another configuration of the SiC complementary JFET according to this embodiment, in which an n-channel JFET and a p-channel JFET are formed on a SiC substrate 10. － 9A is a plan view, and FIG. 9B is a cross-sectional view taken along line IXB-IXB of FIG. 9A.

[0077] As shown in FIGS. 9A and 9B, p － Two n-type well regions 21 are formed in a low-concentration epitaxial layer 20, spaced apart from each other. A p-type well region 22 is further formed in one of the well regions 21, and an n-channel JFET is formed in this well region 22. A p-channel JFET is formed in the other well region 21. As a result, the n-channel JFET and the p-channel JFET are connected to each other via a p-type well region 22. － By applying a reverse bias to the pn junction between the low concentration epitaxial layer 20 and the n-type well region 21, they can be electrically isolated from each other.

[0078] On the SiC substrate 10, n － Even if a low concentration epitaxial layer of the same type is formed, by changing the conductivity type of the well regions 21 and 22, a SiC complementary JFET of the same configuration can be formed.

[0079] 10A to 10C are diagrams schematically showing modifications of the SiC JFET shown in Fig. 7A to 7C, where Fig. 10A is a plan view, Fig. 10B is a cross-sectional view taken along line XB-XB in Fig. 10A, and Fig. 10C is a cross-sectional view taken along line XC-XC in Fig. 10A. An n-channel SiC JFET is shown here.

[0080] The SiC JFET of this modification is the SiC JFET shown in FIGS. 7A to 7C, except that a p ＋A p-type (second conductivity type) surface gate region 16 is formed at a position facing the p-type buried gate region 14. That is, the SiC JFET in this modification has a double gate structure in which the buried channel region 11 is sandwiched between a pair of the buried gate region 14 and the surface gate region 16.

[0081] With this configuration, the depletion layer in the buried channel region 11 is controlled by the pair of buried gate regions 14 and surface gate regions 16 formed on both sides of the buried channel region 11, so that the same threshold voltage V ｔｈ The drain current at this time can be increased by approximately two times, thereby realizing a SiC JFET with high current driving capability.

[0082] In this modification, it is preferable to connect the surface gate region 16 to the gate contact region 15 by wiring or the like in order to apply a gate voltage to both the buried gate region 14 and the surface gate region 16. Alternatively, as shown in Fig. 11, the surface gate region 16 may be connected to the gate contact region 15 by extending the surface gate region 16 to the gate contact region 15 on the main surface. Alternatively, the surface gate region 16 may not be connected to the gate contact region 15 by wiring or the like, but may be used as a gate different from the buried gate region 14, and different gate voltages may be applied to the buried gate region 14 and the surface gate region 16, respectively, to control the depletion layer in the buried channel region 11.

[0083] In this modification, it is preferable that the impurity concentration of the surface gate region 16 is set to be lower than the impurity concentration of the buried gate region 14. As a result, even if the surface gate region 16 is made of an ion-implanted layer, it is hardly affected by the channeling phenomenon to the buried channel region 11, and the threshold voltage V ｔｈ can be controlled according to the design value.

[0084] Furthermore, by using the SiC JFET of this modification, it is possible to form a SiC complementary JFET having the structure shown in FIG. 8, or FIGS. 9A and 9B.

[0085] Although the present invention has been described above with reference to preferred embodiments, such description is not intended to be limiting and various modifications are possible.

[0086] For example, in the above embodiment, an example has been described in which the SiC complementary JFET is applied to an inverter circuit, but it goes without saying that it may also be applied to other integrated circuits.

[0087] The structures of the SiC complementary JFETs shown in FIGS. 6A, 6B, 9A, and 9B can also be applied to a single SiC JFET.

[0088] Furthermore, the SiC JFET in the above embodiment can of course be applied not only to a normally-off type but also to a normally-on type.

[0089] In the above embodiment, the impurity density N Ｄ is the impurity density N Ａ Although an example in which the density is set lower than that of the first line has been described, both may have approximately the same density.

[0090] 10 SiC substrate 11 Channel region (buried channel region) 12 Source region 13 Drain region 14 Buried gate region 15 Gate contact region 16 Surface gate region 20 p － N-type epitaxial layer 21 N-type well region 22 P-type well region

Claims

1. A SiC junction field effect transistor comprising: a SiC substrate; a channel region of a first conductivity type formed on a main surface of the SiC substrate; a buried gate region of a second conductivity type formed on the main surface side of the SiC substrate below the channel region; and a source region and a drain region of the first conductivity type formed on the main surface of the SiC substrate, sandwiching the channel region.

2. The SiC junction field effect transistor according to claim 1, wherein the impurity concentration of said channel region is set to be lower than the impurity concentration of said buried gate region.

3. The SiC junction field effect transistor according to claim 1, wherein the channel region, the buried gate region, the source region, and the drain region are all composed of ion-implanted layers.

4. The SiC junction field effect transistor according to claim 1, wherein a gate contact region of a second conductivity type is formed on the main surface of the SiC substrate at a position spaced apart from the source region and the drain region, and the buried gate region extends to directly below the gate contact region and is connected to the gate contact region.

5. A SiC complementary junction field effect transistor in which a normally-off n-channel junction field effect transistor and a normally-off p-channel junction field effect transistor are formed on a SiC substrate, wherein the n-channel junction field effect transistor and the p-channel junction field effect transistor are each composed of a SiC junction field effect transistor as defined in any one of claims 1 to 4, and the n-channel junction field effect transistor and the p-channel junction field effect transistor are formed in the SiC substrate separated from each other and electrically insulated.

6. A SiC junction field effect transistor comprising: a SiC substrate; a buried channel region of a first conductivity type formed below and spaced apart from a main surface of the SiC substrate; a buried gate region of a second conductivity type formed below the buried channel region; and a source region and a drain region of the first conductivity type formed on the main surface of the SiC substrate, sandwiching the buried channel region.

7. The SiC junction field effect transistor according to claim 6, wherein the impurity concentration of said buried channel region is set to be lower than the impurity concentration of said buried gate region.

8. The SiC junction field effect transistor according to claim 6, wherein the buried channel region, the buried gate region, the source region, and the drain region are all composed of ion-implanted layers.

9. The SiC junction field effect transistor according to claim 6, wherein a gate contact region of a second conductivity type is formed on the main surface of the SiC substrate at a position spaced apart from the source region and the drain region, and the buried gate region extends to directly below the gate contact region and is connected to the gate contact region.

10. The SiC junction field effect transistor according to claim 6, wherein a surface gate region of the second conductivity type is formed on the main surface of the SiC substrate above the buried channel region and at a position facing the buried gate region.

11. A SiC complementary junction field effect transistor in which a normally-off n-channel junction field effect transistor and a normally-off p-channel junction field effect transistor are formed on a SiC substrate, wherein the n-channel junction field effect transistor and the p-channel junction field effect transistor are each composed of a SiC junction field effect transistor as defined in any one of claims 6 to 10, and the n-channel junction field effect transistor and the p-channel junction field effect transistor are formed in the SiC substrate separated from each other and electrically insulated.