Secondary battery protection circuit, secondary battery protection device, and battery pack

Abstract

This secondary battery protection circuit protects a secondary battery by using charging control and discharging control switch elements inserted between a positive terminal of the secondary battery and a high-potential terminal of a charger. The secondary battery protection circuit comprises: a first voltage detection circuit that detects whether the battery voltage is less than a first threshold; a switch circuit that outputs a high-potential voltage of the charger at the time of detection and outputs a battery voltage at the time of non-detection; a booster circuit that boosts and outputs the battery voltage by using the output voltage of the switch circuit; and a drive circuit that performs control to turn on only the charging control switch element by outputting the output volage of the booster circuit at the time of detection only to the control terminal of this switch element, and to turn on both the charging control switch element and the discharging control switch element by outputting the output volage of the booster circuit at the time of non-detection to the control terminals of these switch elements.

Description

Secondary battery protection circuit, secondary battery protection device, and battery pack

[0001] The present invention relates to a secondary battery protection circuit, a secondary battery protection device, and a battery pack.

[0002] A secondary battery protection circuit according to Prior Art 1 is known, which controls the on / off of a pair of N-channel charge / discharge control MOS field effect transistors (hereinafter, "field effect transistor" will be referred to as "FET" and "charge / discharge control MOSFET" will be referred to as "charge / discharge control FET." Here, "charge / discharge control FET" includes "charge control FET" and "discharge control FET") inserted in series in a current path between the positive electrode of the secondary battery and a positive terminal connected to the high-potential power supply terminal of the load and charger, by boosting the voltage supplied from the secondary battery using a charge pump and supplying it to the gates of the pair of charge / discharge control FETs.

[0003] However, in the secondary battery protection circuit of Conventional Example 1, boost operation is not possible when the secondary battery voltage is near zero volts, which is below the minimum operating voltage of the charge pump, and the voltage required to turn on the charge control FET cannot be supplied to the gate, which means that charging is not possible.

[0004] To solve this problem, when the battery voltage is near zero volts, the gate voltage Vg of the charge control FET is set to the high potential voltage (positive electrode voltage) VP of the charger. ＋ A secondary battery protection circuit according to Prior Art 2 is already known, which uses a method in which a switch that switches the secondary battery protection circuit to supply a charge control FET is provided in the secondary battery protection circuit, thereby enabling the charge control FET to be turned on even when the secondary battery is near zero volts (see, for example, Patent Document 1).

[0005] Patent No. 6614388

[0006] In the secondary battery protection circuit of Conventional Example 2, when charging a secondary battery near zero volts, the charger is assumed to start charging with a constant current known as "CC charging." Here, to charge a secondary battery near zero volts, a gate-source voltage Vgs that allows the current supplied by the charger to flow must be generated in the charge control FET. In this case, the gate-source voltage of the charge control FET required to drive the charger's supply current is the threshold voltage Vth, and the condition for driving the charger's supply current is expressed by the following equation, where Vs is the source voltage of the charge control FET:

[0007] Vg = Charger voltage (≒ Positive electrode voltage VP ＋ ) Vs = battery voltage VB + (≒ power supply voltage VDD)

[0008] Therefore, the positive voltage VP ＋ is the charger voltage VP ＋ and is expressed by the following equation:

[0009] Vgs>Vth

[0010] That is, the following equation is obtained.

[0011] VP ＋ >VDD+Vth

[0012] Charger voltage VP ＋ The larger the voltage at the positive terminal (V ＋ ) and the voltage drop between the positive terminal of the battery increases, resulting in increased heat loss during charging. This can be a bottleneck, especially when charging at a high current from a low battery voltage state in order to shorten the charging time. Therefore, it is desirable to charge at a lower charger voltage.

[0013] The object of the present invention is to provide a secondary battery protection circuit, a secondary battery protection device equipped with a secondary battery protection circuit, and a battery pack equipped with a secondary battery protection circuit that can reduce heat loss more than conventional techniques by charging a secondary battery that is near zero volts with a charger voltage that is lower than conventional techniques.

[0014] The secondary battery protection circuit of the present invention is a secondary battery protection circuit that protects the secondary battery using a charge control switch element and a discharge control switch element that are inserted between the positive terminal of the secondary battery and the high potential terminals of a load and a charger and are connected in series to each other, and includes: a first voltage detection circuit that detects whether the battery voltage of the secondary battery is less than a predetermined first threshold; a switch circuit that outputs an output voltage that is a high potential voltage of the charger when it detects that the secondary battery is less than the first threshold, and outputs an output voltage that is the battery voltage when it does not detect that the secondary battery is less than the first threshold; a boost circuit that boosts the battery voltage using the output voltage of the switch circuit and outputs the battery voltage; and a drive circuit that outputs the output voltage of the boost circuit only to the control terminal of the charge control switch element when it detects that the secondary battery is less than the first threshold, thereby turning on only the charge control switch element, and outputs the output voltage of the boost circuit to each control terminal of the charge control switch element and the discharge control switch element when it does not detect that the secondary battery is less than the first threshold, thereby controlling both the charge control switch element and the discharge control switch element to be turned on.

[0015] Therefore, with the secondary battery protection circuit etc. according to the present invention, by charging a secondary battery that is near zero volts with a charger voltage lower than conventional, heat loss can be reduced more than with conventional technology.

[0016] 5A is a circuit diagram showing an example of the configuration of a battery pack BP1 and its peripheral circuits according to embodiment 1 of the present invention. FIG. 5B is a block diagram showing an example of the configuration of the switch circuit 3 and the boost circuit 6 of FIG. 1. FIG. 5C is a timing chart showing each voltage after a charger is connected in a secondary battery protection circuit according to conventional example 2. FIG. 5D is a timing chart showing each voltage after a charger is connected in the secondary battery protection circuit 16 of FIG. 1. FIG. 5E is a circuit diagram showing an example of the configuration of a battery pack BP2 and its peripheral circuits according to embodiment 2 of the present invention. FIG. 5F is a block diagram showing an example of the configuration of the switch circuit 3 and the boost circuit 6 of FIG. 5A. FIG. 5G is a circuit diagram showing an example of the configuration of a battery pack BP3 and its peripheral circuits according to embodiment 3 of the present invention. FIG. 5H is a circuit diagram showing an example of the configuration of a battery pack BP4 and its peripheral circuits according to embodiment 4 of the present invention. FIG. 5I is a circuit diagram showing an example of the configuration of a battery pack BP5 and its peripheral circuits according to embodiment 5 of the present invention. FIG. 5I is a circuit diagram showing an example of the configuration of a battery pack BP6 and its peripheral circuits according to embodiment 6 of the present invention.

[0017] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings, in which the same or similar components are designated by the same reference numerals.

[0018] First Embodiment FIG. 1 is a circuit diagram showing an example of the configuration of a battery pack BP1 and its peripheral circuits according to a first embodiment of the present invention.

[0019] 1, the battery pack BP1 includes a secondary battery B1 having a positive terminal 21 and a negative terminal 22, a secondary battery protection device 20, a positive terminal 13, and a negative terminal 12. A parallel circuit of a system load RL and a charger CH1 is connected between the positive terminal 13 and the negative terminal 12. That is, the high potential terminal of the charger CH1 is connected to the positive terminal 13, and the low potential terminal of the charger CH1 is connected to the negative terminal 12. The negative terminal 22 of the secondary battery B1 has a ground voltage VSS and is connected to the negative terminal 12. The secondary battery B1 has a battery voltage (power supply voltage) VDD, which is the potential difference between its positive and negative terminals.

[0020] The secondary battery protection device 20 is configured to include a secondary battery protection circuit 16, a charge control FET (CFET) 14, which is, for example, an N-channel MOSFET and has a body diode 10, and a discharge control FET (DFET) 15, which is, for example, an N-channel MOSFET and has a body diode 11. The charge control FET 14 and the discharge control FET 15 are connected in series with each other, and this series circuit is connected between a positive terminal 21 and a positive terminal 13. The secondary battery protection circuit 16 is configured to include an over-discharge detection circuit 2, a switch circuit 3 including a control circuit 3A, a boost circuit 6 including a control circuit 6A, and a drive circuit 7.

[0021] The over-discharge detection circuit 2 compares the battery voltage VDD with a predetermined over-discharge detection threshold Vthe to generate a detection signal S2, which is a comparison result signal. If the battery voltage VDD is below the over-discharge detection threshold Vthe, the over-discharge detection circuit 2 outputs an L-level detection signal S2 indicating "over-discharge detected" to the drive circuit 7 and the control circuit 3A. On the other hand, if the battery voltage VDD is equal to or higher than the over-discharge detection threshold Vthe, the over-discharge detection circuit 2 outputs an H-level detection signal S2 indicating "over-discharge not detected" to the drive circuit 7 and the control circuit 3A. The over-discharge detection threshold Vthe is set to, for example, the discharge end-of-voltage or a voltage slightly lower than the discharge end-of-voltage.

[0022] The switch circuit 3 is configured to include a control circuit 3A and switches 4 and 5. In response to a detection signal S2 of H level, the control circuit 3A of the switch circuit 3 turns off the switch 4 and turns on the switch 5, thereby outputting the battery voltage VDD as the output voltage VSW to the boost circuit 6. On the other hand, in response to a detection signal S2 of L level, the control circuit 3A of the switch circuit 3 turns on the switch 4 and turns off the switch 5, thereby outputting the positive voltage VP, which is the charger voltage of the positive terminal 13 ＋ is output to the boost circuit 6 as the output voltage VSW.

[0023] The boost circuit 6 operates using the output voltage VSW from the switch circuit 3 as a power supply voltage, and generates a boosted voltage VCP (=VDD+VSW) based on the battery voltage VDD and the output terminal VSW.

[0024] Based on the detection signal S2, the drive circuit 7 uses the boosted voltage VCP to control the on / off of the charge control FET 14 and the discharge control FET 15. Here, based on the H-level detection signal S2, the drive circuit 7 outputs H-level (=VCP) control signals COUT and DOUT to the gates (control terminals) of the charge control FET 14 and the discharge control FET 15, respectively, to turn on both the charge control FET 14 and the discharge control FET 15. On the other hand, based on the L-level detection signal S2, the drive circuit 7 outputs an H-level (=VCP) control signal COUT to the gate of the charge control FET 14 and an L-level (=VSS) control signal DOUT to the gate of the discharge control FET 15, to turn on the charge control FET 14 and turn off the discharge control FET 15.

[0025] FIG. 2 is a block diagram showing an example of the configuration of the switch circuit 3 and the booster circuit 6 shown in FIG.

[0026] 2, the switch circuit 3 is configured to include a control circuit 3A and switches 4 and 5, and operates as described above. The boost circuit 6 is a typical charge pump circuit, and is configured to include a control circuit 6A, four switches 6a to 6d, and a boost capacitor C1. In the boost circuit 6, the output voltage VSW from the switch circuit 3 is supplied as a power supply voltage to the control circuit 6A, and is also output as a boosted voltage VCP to the drive circuit 7 via switches 6a and 6b. The battery voltage VDD is grounded via switches 6c and 6d. Here, the connection point between switches 6a and 6b is connected to the connection point between switches 6c and 6d via the boost capacitor C1.

[0027] In the boost circuit 6 configured as described above, the control circuit 6A controls the operation of the boost circuit 6 in accordance with a predetermined clock to repeat the following operations: (1) turning on switch 6a, turning off switch 6b, turning off switch 6c, and turning on switch 6d to charge capacitor C1 with an electric charge equivalent to the voltage difference between output voltage VSW and ground voltage VSS, and (2) turning off switch 6a, turning on switch 6b, turning on switch 6c, and turning off switch 6d to generate and output a boosted voltage VCP (=VDD+VSW) to drive circuit 7. In switch circuit 3, when battery voltage VDD is equal to or higher than over-discharge detection threshold Vthe, switch circuit 3 turns on switch 5 and turns off switch 4 in response to an H-level detection signal S2 from over-discharge detection circuit 2, and the positive voltage VDD at positive terminal 21 is supplied to boost circuit 6 via switch 5 as output voltage VSW. As described above, the output voltage VSW is electrically connected to the battery voltage VDD, so that VCP=VDD+VDD.

[0028] On the other hand, when the battery voltage VDD falls below the over-discharge detection threshold Vthe, the switch 5 is turned off and the switch 4 is turned on in response to the L-level detection signal S2 from the over-discharge detection circuit 2, and the positive voltage VP at the positive terminal 13 is ＋ is supplied to the boost circuit 6 as the output voltage VSW via the switch 4. At this time, since the output voltage VSW is electrically connected to the positive terminal 13 as described above, the boost voltage VCP=VDD+VP ＋ This becomes:

[0029] Next, a method for charging the zero-volt battery according to this embodiment and the output voltage conditions of the charger CH1 that enable charging will be described.

[0030] (A) When the battery voltage VDD is equal to or higher than a predetermined over-discharge detection threshold Vthe, the over-discharge detection circuit 2 is in the "over-discharge not detected" state and outputs an H-level detection signal S2, so that the switch 5 of the switch circuit 3 is turned on and the switch 4 is turned off, causing the battery voltage VDD to be output as the output voltage VSW to the boost circuit 6. In other words, VSW = VDD. Therefore, regardless of whether the charger CH1 is connected or not, the boost voltage VCP generated by the boost circuit 6 is expressed by the following equation:

[0031] VCP=VDD+VSW=VDD+VDD=2×VDD

[0032] At this time, the drive circuit 7 outputs H level (=VCP) control signals COUT and DOUT to the gates of the charge control FET 14 and the discharge control FET 15, respectively, to turn on both the charge control FET 14 and the discharge control FET 15.

[0033] (B) On the other hand, when charging a zero-volt battery, that is, when the battery voltage VDD is below the over-discharge detection threshold Vthe, the over-discharge detection circuit 2 is in the "over-discharge detected" state and outputs an L-level detection signal S2, so the drive circuit 7 outputs an L-level (=VSS) control signal DOUT to the gate of the discharge control FET 15 to turn off the discharge control FET 15. The switch circuit 3 turns off the switch 5 and turns on the switch 4 to turn on the charger voltage VP ＋ is output as the output voltage VSW. That is, VSW=VP ＋ This becomes:

[0034] When the charger CH1 is not connected, the discharge control FET 15 is turned off and the discharge path from the secondary battery B1 is cut off, so the positive voltage VP of the positive terminal 13 ＋ is pulled down to the ground voltage VSS by the system load RL. That is, VSW=VSS (=0 V). Here, since the boost circuit 6 uses the output voltage VSW as the power supply voltage, it does not perform a boost operation in this case, and does not supply to the drive circuit 7 a boosted voltage VCP that would turn on the charge control FET 14, so the charge control FET 14 is driven off.

[0035] On the other hand, when the charger CH1 is connected, the positive voltage VP ＋ is equal to the output voltage of the charger CH1. Therefore, the charger output voltage VP ＋=VSW. The boost circuit 6 performs a boost operation using the output voltage VSW as the power supply voltage, and the drive circuit 7 outputs an H-level (=VCP) control signal COUT to the gate of the charge control FET 14 to turn on the charge control FET 14 and make the charge path conductive, thereby enabling charging of the zero-volt battery. Here, the boost voltage VCP generated by the boost operation of the boost circuit 6 is expressed by the following equation:

[0036] VCP=VDD+VSW=VDD+VP ＋

[0037] Here, if the gate-source voltage of the charge control FET14 is Vgs and the gate-source voltage of the charge control FET14 necessary to drive the supply current of the charger CH1 is Vth, the differential voltage (Vg-Vs) between the gate voltage Vg and source voltage Vs of the charge control FET14 is expressed by the following equation:

[0038] Vg-Vs=COUT-VDD=(VDD+VP ＋ ) -VDD =VP ＋

[0039] Here, the condition for enabling charging is Vgs≧Vth, that is, P ＋ ≧Vth.

[0040] Fig. 3 is a timing chart showing each voltage after the charger is connected in the secondary battery protection circuit of Conventional Example 2. Fig. 4 is a timing chart showing each voltage after the charger is connected in the secondary battery protection circuit 16 of Fig. 1. Below, the timing charts during charging of a zero-volt battery in Conventional Example 2 and Embodiment 1 will be described with reference to Figs. 3 and 4.

[0041] In the secondary battery protection circuit of Conventional Example 2, when a charger is connected to a secondary battery whose voltage is near zero volts, a potential difference is generated between the positive terminal 13 and the negative terminal 12 until a voltage that satisfies the charger's output voltage conditions that enable charging is reached. Specifically, the gate-source voltage Vgs of the charge control FET 14 is expressed by the following equation:

[0042] Vgs=COUT-VDD

[0043] Here, the voltage COUT of the control signal is expressed by the following equation (FIG. 3): COUT=VP ＋

[0044] Therefore, the following equation is obtained.

[0045] Vgs = VP ＋ -VDD

[0046] If the gate-source voltage of the charge control FET 14 required to drive the supply current of the charger CH1 is Vth, the condition for enabling charging is Vgs≧Vth, and therefore, VP ＋ −VDD≧Vth, that is, VP ＋ ≧VDD+Vth (FIG. 3).

[0047] In the secondary battery protection circuit 16 according to the first embodiment, when the gate-source voltage of the charge control FET 14 is Vgs and the gate-source voltage of the charge control FET 14 required to drive the supply current of the charger CH1 is Vth, the following equation can be expressed:

[0048] COUT=VCP=VDD+VSW=VDD+VP ＋

[0049] Therefore, it is expressed by the following equation.

[0050] Vgs=COUT-VDD=(VDD+P ＋ ) -VDD=P ＋

[0051] Here, the condition that enables charging is Vgs>Vth, that is, P+≧Vth (FIG. 4). As is clear from FIG. 4, unlike Conventional Example 2, it is not dependent on the battery voltage VDD, and as a result, charging is performed at a lower charger voltage than Conventional Example 2. On the other hand, the condition for starting charging when the VDD voltage rises as charging continues is expressed by the following equation, where Vf is the forward voltage of the body diode 11 of the discharge control FET 15 and Vds is the drain-source voltage of the charge control FET:

[0052] VP ＋ ≧VDD+Vds+Vf

[0053] To satisfy this condition, the charger CH1 must be set to a positive voltage VP ＋In the conventional example 2 shown in FIG. 3, the positive electrode voltage VP increases as the battery voltage VDD increases immediately after the start of charging. ＋ In contrast, in the first embodiment shown in FIG. 4, the positive electrode voltage VP ＋ Since there is a time period in which the charge voltage does not rise, charging can be maintained at a lower charger voltage than in Conventional Example 2.

[0054] As described above, according to the first embodiment, as is clear from FIG. 4, by charging the secondary battery B1 at near zero volts with a charger voltage lower than conventionally, heat loss can be reduced more than with conventional technology.

[0055] (Embodiment 2) Fig. 5A is a circuit diagram showing an example of the configuration of a battery pack BP2 and its peripheral circuits according to embodiment 2 of the present invention, and Fig. 5B is a block diagram showing an example of the configuration of the switch circuit 3 and boost circuit 6 of Fig. 5A. The battery pack BP2 of Fig. 5A differs from the battery pack BP1 of Fig. 1 in the following respects: (1) Instead of the secondary battery protection circuit 16, it has a secondary battery protection circuit 16A further including a voltage detection circuit 1. (2) Instead of the secondary battery protection device 20, it has a secondary battery protection device 20A including the secondary battery protection circuit 16A. (3) Instead of the control circuit 6A, the boost circuit 6 has a control circuit 6B. The differences will be explained below.

[0056] In FIG. 5A, the voltage detection circuit 1 detects the positive voltage VP ＋ The voltage detection circuit 1 compares the positive voltage VP with a predetermined voltage threshold Vthd and generates a detection signal S1, which is a comparison result signal. ＋ is equal to or greater than the voltage threshold Vthd, the boost circuit 6 is determined to be in a normal operating state, and a high-level detection signal S1 is output to the drive circuit 7. ＋ If the voltage threshold Vthd is less than a predetermined voltage threshold Vthd, it is determined that the boost circuit 6 is not in a normal operating state, and an L-level detection signal S1 is output to the drive circuit 7. Here, the voltage threshold Vthd is set higher than the minimum operating voltage of the boost circuit 6.

[0057] 5A and 5B, the control circuit 6B of the boost circuit 6 operates the boost circuit 6 in response to an H-level detection signal S1 from the voltage detection circuit 1, but stops the boosting operation of the boost circuit 6 in response to an H-level detection signal S2 (over-discharge detection signal) and an L-level detection signal S1 from the over-discharge detection circuit 2. The detection signal S1 from the voltage detection circuit 1 is also output to the drive circuit 7 to notify it of the stop of the boosting operation of the boost circuit 6.

[0058] The effects of further providing the "voltage detection circuit 1" in the second embodiment configured as above will be described below.

[0059] When the over-discharge detection circuit 2 detects the "over-discharge" state of the secondary battery B1, the discharge control FET 15 is turned off and the discharge from the secondary battery B1 stops, the positive electrode voltage VP ＋ and negative electrode voltage VP － The voltage between the positive pole and the negative pole is pulled down to 0 V by the system load RL. ＋ At this time, in order to charge the zero-volt battery, the switch 5 of the switch circuit 3 is turned off and the switch 4 is turned on to set the positive electrode voltage VP ＋ When the output voltage VSW is supplied as the power supply voltage of the boost circuit 6, the positive voltage VP ＋ If the boost circuit 6 is started up during the period when the voltage drops from 0V to the minimum operating voltage of the boost circuit 6 (the period when the boost circuit 6 is not in a normal operating state), it is possible that malfunction or a through current will occur depending on the configuration of the boost circuit 6.

[0060] Therefore, in the second embodiment, the positive electrode voltage VP ＋ is less than the minimum operating voltage of the boost circuit 6 (a period when the boost circuit 6 is not in a normal operating state). ＋is less than the minimum operating voltage of the boost circuit 6, thereby preventing the boost circuit 6 from starting up and preventing malfunction or through-current from occurring in the boost circuit 6. Similarly, even in a case where a charger CH1 that outputs an abnormally low voltage due to a fault is connected and a voltage less than the minimum operating voltage of the boost circuit 6 is steadily applied to the positive terminal 13, the voltage detection circuit 1 is in the "non-detection" state, outputs an L-level detection signal S1, and stops the boost circuit 6, thereby preventing malfunction or through-current from occurring in the boost circuit 6.

[0061] Moreover, the secondary battery protection circuit 16A according to the second embodiment has the same effects as the secondary battery protection circuit 16 according to the first embodiment.

[0062] (Embodiment 3) Fig. 6 is a circuit diagram showing an example of the configuration of a battery pack BP3 and its peripheral circuits according to embodiment 3 of the present invention. The battery pack BP3 in Fig. 6 differs from the battery pack BP2 in Fig. 2 in the following respects: (1) Instead of the secondary battery protection circuit 16A, a secondary battery protection circuit 16B further including a clamp circuit 8 is provided. (2) Instead of the secondary battery protection device 20A, a secondary battery protection device 20B including the secondary battery protection circuit 16B is provided. The differences will be explained below.

[0063] In FIG. 6, the clamp circuit 8 controls the positive voltage VP ＋ and negative electrode voltage VP － (=VSS) is clamped to a constant clamp voltage VCL that is lower than the withstand voltage of the switches 4 and 5 and the boost circuit 6 and is output to one end of the switch 4 of the switch circuit 3.

[0064] The effects of further providing the "clamp circuit 8" in the third embodiment configured as above will be described below.

[0065] In FIG. 1 or FIG. 5A, (1) the over-discharge detection circuit 2 detects that the battery voltage VDD has fallen below the over-discharge threshold Vthe and outputs an L-level detection signal S2, (2) the switch 5 of the switch circuit 3 is turned off and the switch 4 is turned on, and the positive electrode voltage VP is set as the output voltage VSW. ＋is output, (3) a charger CH1 that outputs a voltage equal to or higher than the voltage threshold Vthd is connected to the positive terminal 13, (4) the voltage detection circuit 1 detects the connection of the charger CH1, (5) the boost circuit 6 performs a boost operation and the drive circuit 7 outputs a control signal COUT of H level (=VCP) to the gate of the charge control FET 14 to turn on the charge control FET 14 and charge the secondary battery B1 which is near zero volts, (6) the charger CH1 fails for some reason, and (7) the output voltage changes abruptly, causing a high voltage P ＋ (8) In other words, a voltage higher than the withstand voltage is applied to the switches 4 and 5 and the boost circuit 6 connected to the output voltage VSW, and it is assumed that the switches 4 and 5 and the boost circuit 6 will be destroyed.

[0066] To solve this problem, it is conceivable to configure the switches 4 and 5 and the boost circuit 6 using high-voltage elements, but this would result in disadvantages such as an increase in area, an increase in the number of masks used in the manufacturing process of the semiconductor manufacturing equipment, and an increase in lead time.

[0067] As described above, according to the third embodiment, by further providing the clamp circuit 8, it is possible to prevent the switches 4 and 5 and the boost circuit 6 from being destroyed.

[0068] Furthermore, because secondary battery B1 is typically used at 4.2V or less, when secondary battery protection circuit 16B is configured as a semiconductor integrated circuit (IC), the protection circuit IC connected only to the battery voltage generally uses elements based on a 5V process. Therefore, by setting the clamp voltage VCL from clamp circuit 8 to 5V or less, secondary battery protection circuit 16B, including switches 4 and 5 and boost circuit 6, can be configured using low-voltage elements based on a 5V process that are generally used in protection circuit ICs. This provides the benefits of reduced area, fewer masks, and shorter lead times.

[0069] Furthermore, the secondary battery protection circuit 16B according to the third embodiment has the same effects as the secondary battery protection circuits 16 and 16A according to the first and second embodiments.

[0070] In the third embodiment shown in FIG. 6, the voltage detection circuit 1 may be omitted (a modified example of the third embodiment).

[0071] (Fourth Embodiment) Fig. 7 is a circuit diagram showing an example of the configuration of a battery pack BP4 and its peripheral circuits according to a fourth embodiment of the present invention. The battery pack BP4 of Fig. 7 differs from the battery pack BP3 of Fig. 6 in the following respects: (1) Instead of the secondary battery protection circuit 16B, a secondary battery protection circuit 16C is provided in which the insertion position of the clamp circuit 8 is changed. The clamp circuit 8 is inserted between the positive terminal 13 and one end of the voltage detection circuit 1 and the switch 4 of the switch circuit 3. (2) Instead of the secondary battery protection device 20B, a secondary battery protection device 20C including the secondary battery protection circuit 16C is provided. The differences will be described below.

[0072] In FIG. 7, the clamp circuit 8 controls the positive voltage VP ＋ and negative electrode voltage VP － (=VSS) and outputs a constant clamp voltage VCL that is lower than the withstand voltages of the switches 4, 5 and the boost circuit 6 to one end of the switch 4 of the switch circuit 3 and to the voltage detection circuit 1. When the clamp voltage VCL is equal to or higher than the voltage threshold Vthd, the voltage detection circuit 1 generates an H-level detection signal S1 and outputs it to the drive circuit 7, whereas when the clamp voltage VCL is lower than the voltage threshold Vthd, the voltage detection circuit 1 generates an L-level detection signal S1 and outputs it to the drive circuit 7.

[0073] According to the fourth embodiment configured as described above, as shown in FIG. 7 , by arranging the voltage detection circuit 1 after the clamp circuit 8 and monitoring the clamp voltage VCL from the clamp circuit 8, it is possible to configure the voltage detection circuit 1 with a low withstand voltage of 5V, thereby obtaining the advantages of saving area, reducing the number of masks, and shortening the lead time.

[0074] Furthermore, the secondary battery protection circuit 16C according to the fourth embodiment has the same effects as the secondary battery protection circuits 16, 16A to 16B according to the first to third embodiments.

[0075] (Embodiment 5) Fig. 8A is a circuit diagram showing an example of the configuration of a battery pack BP5 and its peripheral circuits according to embodiment 5 of the present invention. The battery pack BP5 of Fig. 8A differs from the battery pack BP4 of Fig. 7 in the following respects: (1) Instead of the secondary battery protection circuit 16C, a secondary battery protection circuit 16D further including a voltage detection circuit 17 is provided. The voltage detection circuit 17 is inserted between the positive terminal 13 and the clamp circuit 8 and the voltage detection circuit 1. (2) Instead of the secondary battery protection device 20C, a secondary battery protection device 20D including the secondary battery protection circuit 16D is provided. The differences will be described below.

[0076] In FIG. 8A, the voltage detection circuit 17 detects the positive voltage VP, which is the charger voltage. ＋ The voltage detection circuit 17 is a charger voltage monitoring circuit that monitors the positive electrode voltage VP ＋ By comparing the positive electrode voltage VP with the voltage threshold Vthf, a so-called "high voltage" is detected and a detection signal S17, which is a comparison result signal, is generated as follows: (A) The voltage detection circuit 17 detects the positive electrode voltage VP ＋ becomes equal to or greater than the voltage threshold Vthf, the voltage detection circuit 17 generates a detection signal S17 of H level (=VCL) and outputs it to the voltage detection circuit 1. (B) On the other hand, the voltage detection circuit 17 detects the positive voltage VP ＋ If Vthf is less than the voltage threshold Vthf, the detection signal S17 at L level (=VSS) is generated and output to the voltage detection circuit 1.

[0077] In response to the H-level detection signal S17, the voltage detection circuit 1 generates an L-level (=VSS) detection signal S1 and outputs it to the drive circuit 7 and the control circuit 6B of the boost circuit 6. On the other hand, in response to the L-level detection signal S17, if the positive voltage VP+ is equal to or higher than the voltage threshold Vthd, the voltage detection circuit 1 generates an H-level (=VCL) detection signal S1 and outputs it to the drive circuit 7 and the control circuit 6B of the boost circuit 6, ＋ is less than the voltage threshold Vthd, the detection signal S1 of L level (=VSS) is generated and output to the drive circuit 7 and the control circuit 6B of the boost circuit 6.

[0078] Next, the effects of the voltage detection circuit 17 according to the fifth embodiment will be described below.

[0079] In the conventional example 2 and the first to fourth embodiments, when a charger CH1 that outputs a relatively high voltage is connected between the positive terminal 13 and the negative terminal 12 to the secondary battery B1 that is near zero volts, the positive terminal VP ＋ Since the potential difference between the charger voltage and the battery voltage VDD is large, a rush current flows into the secondary battery B1, which can damage or ignite the secondary battery B1. To solve this problem, the voltage detection circuit 17 is further provided.

[0080] 8A further includes a voltage detection circuit 17. When a charger CH1 that outputs a relatively high voltage equal to or greater than the voltage threshold Vthf is connected between the positive terminal 13 and the negative terminal 12, the voltage detection circuit 17 generates an H-level (=VCL) detection signal S17 and outputs it to the voltage detection circuit 1. In response to the H-level detection signal S17, the voltage detection circuit 1 generates an L-level (=VSS) detection signal S1 and outputs it to the drive circuit 7 and the control circuit 6B of the boost circuit 6. Therefore, the boost circuit 6 does not perform a boost operation, and the drive circuit 7 outputs an L-level control signal COUT to the gate of the charge control FET 14, turning off the charge control FET 14 and cutting off the charge path. As a result, charging of the secondary battery B1, which is near zero volts, is not initiated, and no inrush current flows into the secondary battery B1, preventing damage to or fire of the secondary battery B1.

[0081] Furthermore, the secondary battery protection circuit 16D according to the fifth embodiment has the same effects as the secondary battery protection circuits 16, 16A to 16C according to the first to fourth embodiments.

[0082] 8B is a circuit diagram showing an example of the configuration of a battery pack BP6 and its peripheral circuits according to a sixth embodiment of the present invention. The battery pack BP6 in FIG. 8B differs from the battery pack BP5 in FIG. 8A in the following respects: (1) The voltage detection circuit 17 detects the positive electrode voltage VP ＋(2) Instead of the secondary battery protection device 20D having the secondary battery protection circuit 16D, a secondary battery protection device 20E having a secondary battery protection circuit 16E is provided. The differences will be described below.

[0083] In FIG. 8B, the voltage detection circuit 17 detects the positive voltage VP from the clamp circuit 8 via the clamp voltage VCL. ＋ The charger voltage monitoring circuit 17 monitors the positive electrode voltage VP based on the clamp voltage VCL from the clamp circuit 8. The voltage threshold Vthf is set higher than the voltage threshold Vthd of the voltage detection circuit 1. ＋ In order to make it possible to detect when the clamp voltage VCL is equal to or greater than the voltage threshold Vthf, the clamp voltage from the clamp circuit 8 is set higher than Vthf. The voltage detection circuit 17 detects a so-called "high voltage" by comparing the clamp voltage VCL with the voltage threshold Vthf and generates a detection signal S17, which is a comparison result signal, as follows: (A) When the clamp voltage VCL is equal to or greater than the voltage threshold Vthf, the voltage detection circuit 17 generates a detection signal S17 of H level (=VCL) and outputs it to the voltage detection circuit 1. (B) On the other hand, when the clamp voltage VCL is less than the voltage threshold Vthf, the voltage detection circuit 17 generates a detection signal S17 of L level (=VSS) and outputs it to the voltage detection circuit 1.

[0084] The secondary battery protection circuit 16E according to the sixth embodiment configured as described above has the same effects as the secondary battery protection circuit 16D according to the fifth embodiment, except for the detected voltage of the voltage detection circuit 17.

[0085] (Modification) In the above embodiment, the over-discharge detection circuit 2 detects over-discharge of the secondary battery B1, but the present invention is not limited to this. For example, the over-discharge detection circuit 2 may detect a drop in the battery voltage at the positive terminal 21 of the secondary battery B1 due to an increase in the current consumption of the secondary battery B1. In other words, the over-discharge detection threshold Vthe may be a threshold for detecting other voltage drops.

[0086] In the above embodiments, a secondary battery protection circuit, a secondary battery protection device, and a battery pack have been described, but the present invention is not limited to this, and various modifications may be made, such as configuring a control circuit or control method for a secondary battery protection circuit, or combining part or all of one embodiment with another embodiment.

[0087] For example, the positions of the charge control FET 14 and the discharge control FET 15 may be interchanged.

[0088] In the above embodiment, the charge control FET 14 and the discharge control FET 15 are used, but the present invention is not limited to this, and other types of switch elements such as bipolar transistors (having a control terminal as a base) may also be used.

[0089] 1 Voltage detection circuit 2 Over-discharge detection circuit 3 Switch circuit 3A Control circuit 4, 5 Switch 6 Boost circuit 6A, 6B Control circuit 6a to 6d Switch 7 Drive circuit 8 Clamp circuit 9 Control circuit 10, 11 Body diode 12 Negative terminal 13 Positive terminal 14 Charge control FET 15 Discharge control FET 16, 16A to 16E Secondary battery protection circuit 17 Voltage detection circuit 20, 20A to 20E Secondary battery protection device 21 Positive terminal 22 Negative terminal B1 Secondary battery BP1 to BP6 Battery pack C1 Capacitor CH1 Charger RL System load

Claims

1. A secondary battery protection circuit that protects a secondary battery by using a charge control switch element and a discharge control switch element that are inserted between a positive terminal of the secondary battery and a high potential terminal of a load and a charger and are connected in series with each other, a first voltage detection circuit that detects whether a battery voltage of the secondary battery is less than a predetermined first threshold value; a switch circuit that outputs an output voltage which is a high potential voltage of the charger when it detects that the voltage is less than the first threshold, and outputs an output voltage which is the battery voltage when it does not detect that the voltage is less than the first threshold; a boost circuit that boosts the battery voltage using an output voltage of the switch circuit and outputs the boosted voltage; a drive circuit which controls so that when it is detected that the voltage is less than the first threshold, the output voltage of the boost circuit is output only to the control terminal of the charge control switch element, thereby turning on only the charge control switch element, and when it is not detected that the voltage is less than the first threshold, the output voltage of the boost circuit is output to each control terminal of the charge control switch element and the discharge control switch element, thereby turning on both the charge control switch element and the discharge control switch element; A secondary battery protection circuit comprising:

2. The secondary battery protection circuit further comprises: a second voltage detection circuit for detecting a normal operation state of the boost circuit when the voltage of the high potential terminal of the charger is equal to or higher than a second predetermined threshold value higher than a minimum operating voltage of the boost circuit; the second voltage detection circuit operates the boost circuit when it detects that the boost circuit is in a normal operable state, and stops the operation of the boost circuit when it detects that the voltage is less than the first threshold and that the boost circuit is not in a normal operable state.

2. The secondary battery protection circuit according to claim 1.

3. The secondary battery protection circuit further comprises: a first clamp circuit that clamps the high potential voltage of the charger to a predetermined clamp voltage and outputs the clamp voltage to the switch circuit instead of the high potential voltage of the charger; 3. The secondary battery protection circuit according to claim 1.

4. The secondary battery protection circuit further comprises: a second clamp circuit that clamps the high potential voltage of the charger to a predetermined clamp voltage and outputs the clamp voltage to the switch circuit and the second voltage detection circuit instead of the high potential voltage of the charger; 3. The secondary battery protection circuit according to claim 2.

5. The secondary battery protection circuit further comprises: a third voltage detection circuit configured to detect a high voltage when the voltage of the high potential terminal of the charger is equal to or higher than a third threshold value that is higher than the second threshold value; the third voltage detection circuit stops the operation of the boost circuit when it detects the high voltage.

5. The secondary battery protection circuit according to claim 2 or 4.

6. The secondary battery protection circuit further comprises: a third voltage detection circuit configured to detect a high voltage when the clamp voltage is equal to or higher than a third threshold value that is higher than the second threshold value; the third voltage detection circuit stops the operation of the boost circuit when it detects the high voltage.

5. The secondary battery protection circuit according to claim 4.

7. A secondary battery protection circuit according to claim 1 or 2; The charge control switch element; The discharge control switch element; Equipped with Secondary battery protection device.

8. A secondary battery protection circuit according to claim 1 or 2; The secondary battery; The charge control switch element; The discharge control switch element; Equipped with Battery pack.