Silicon carbide epitaxial substrate and method for manufacturing silicon carbide semiconductor device
Patent Information
- Application Number
- JP2024535023
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Filing Date
- 2025-01-07
- Publication Date
- 2025-03-28
AI Technical Summary
The existing methods for manufacturing silicon carbide semiconductor devices face challenges in improving yield due to defects such as triangular recesses on the epitaxial layer, which are caused by silicon droplets and result in reduced device performance and increased production costs.
A silicon carbide epitaxial substrate is developed with a specific configuration, including a recess with a triangular shape and a polytype difference at the bottom surface, where the silane flow rate is controlled relative to temperature to minimize the formation of silicon droplets and stacking faults, thereby reducing the areal density of recesses on the substrate.
This approach enhances the yield of silicon carbide semiconductor devices by reducing the number of defects, maintaining a high growth rate of the epitaxial layer, and supporting the production of larger diameter substrates with improved device performance.
Abstract
Description
Silicon carbide epitaxial substrate and method for manufacturing silicon carbide semiconductor device
[0001] The present disclosure relates to a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device. This application claims priority to Japanese Patent Application No. 2022-115800, filed on July 20, 2022. The entire contents of this Japanese patent application are incorporated herein by reference.
[0002] Japanese Patent Laid-Open No. 2011-121847 (Patent Document 1) describes a method for forming a silicon carbide epitaxial layer having a surface with a triangular defect density of 1 / cm. 2 The following silicon carbide epitaxial wafer is disclosed.
[0003] JP 2011-121847 A
[0004] A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer. The silicon carbide epitaxial layer is on the silicon carbide substrate. The silicon carbide epitaxial layer has a first main surface. Recesses are formed in the first main surface. When viewed in a direction perpendicular to the first main surface, the recesses have a triangular outer shape. The depth of the recesses in the direction perpendicular to the first main surface is 100 nm or more. The length of the recesses in a direction projecting the <11-20> direction onto the first main surface is 80 μm or less. The areal density of the recesses on the first main surface is 0.1 recesses / cm 2 The polytype of silicon carbide forming the bottom surface of the recess is different from the polytype of silicon carbide forming the silicon carbide epitaxial layer.
[0005] FIG. 1 is a plan view schematic diagram showing the configuration of a silicon carbide epitaxial substrate according to this embodiment. FIG. 2 is a cross-sectional view schematic diagram taken along line II-II in FIG. 1. FIG. 3 is an enlarged cross-sectional view schematic diagram of region III in FIG. 1. FIG. 4 is a cross-sectional view schematic diagram taken along line IV-IV in FIG. 3. FIG. 5 is a partial cross-sectional view schematic diagram showing the configuration of an apparatus for manufacturing a silicon carbide epitaxial substrate. FIG. 6 is a schematic diagram showing the relationship between the silane flow rate and time with respect to temperature. FIG. 7 is a flowchart generally showing a method for manufacturing a silicon carbide semiconductor device according to this embodiment. FIG. 8 is a cross-sectional view schematic diagram showing the step of forming a body region. FIG. 9 is a cross-sectional view schematic diagram showing the step of forming a source region. FIG. 10 is a cross-sectional view schematic diagram showing the step of forming a trench in a first main surface of a silicon carbide epitaxial layer. FIG. 11 is a cross-sectional view schematic diagram showing the step of forming a gate insulating film. FIG. 12 is a cross-sectional view schematic diagram showing the step of forming a gate electrode and an interlayer insulating film. FIG. 13 is a cross-sectional view schematic diagram showing the configuration of a silicon carbide semiconductor device according to this embodiment.
[0006] [Problem to be Solved by the Present Disclosure] An object of the present disclosure is to provide a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device that can improve the yield of silicon carbide semiconductor devices.
[0007] Effect of the Present Disclosure The present disclosure can provide a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device that can improve the yield of silicon carbide semiconductor devices.
[0008] [Description of Embodiments of the Present Disclosure] First, an outline of an embodiment of the present disclosure will be described. In the crystallographic descriptions in this specification, individual orientations are represented by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. Furthermore, for negative indices, in crystallography, a "-" (bar) is placed before the number, but in this specification, a negative sign is placed before the number.
[0009] (1) Silicon carbide epitaxial substrate 100 according to the present disclosure includes a silicon carbide substrate 30 and a silicon carbide epitaxial layer 40. Silicon carbide epitaxial layer 40 is on silicon carbide substrate 30. Silicon carbide epitaxial layer 40 has a first main surface 1. Recesses 29 are formed in first main surface 1. When viewed in a direction perpendicular to first main surface 1, recesses 29 have a triangular outer shape. The depth of recesses 29 in the direction perpendicular to first main surface 1 is 100 nm or more. The length of recesses 29 in a direction obtained by projecting the <11-20> direction onto first main surface 1 is 80 μm or less. The areal density of recesses 29 on first main surface 1 is 0.1 recesses / cm 2 The polytype of silicon carbide constituting the bottom surface of recess 29 is different from the polytype of silicon carbide constituting silicon carbide epitaxial layer 40 .
[0010] (2) In silicon carbide epitaxial substrate 100 according to (1) above, recess 29 may have a depth of 140 nm or less in a direction perpendicular to first main surface 1 .
[0011] (3) In silicon carbide epitaxial substrate 100 according to (1) or (2) above, recess 29 may have a length of 15 μm or more in the direction in which the <11-20> direction is projected onto first main surface 1.
[0012] (4) In silicon carbide epitaxial substrate 100 according to any one of (1) to (3) above, the polytype of silicon carbide forming the bottom surface of recess 29 may be 3C.
[0013] (5) In silicon carbide epitaxial substrate 100 according to any one of (1) to (4) above, the polytype of silicon carbide constituting silicon carbide epitaxial layer 40 may be 4H.
[0014] (6) In silicon carbide epitaxial substrate 100 according to any one of (1) to (5) above, the surface density of recesses 29 on first main surface 1 is 0.005 / cm 2 It may be more than that.
[0015] (7) In silicon carbide epitaxial substrate 100 according to any one of (1) to (6) above, first main surface 1 may be a plane inclined with respect to the (000-1) plane.
[0016] (8) Silicon carbide epitaxial substrate 100 according to any one of (1) to (7) above may further have stacking faults 20 forming the bottom surfaces of recesses 29. Silicon carbide epitaxial substrate 100 may not have downfalls continuous with stacking faults 20.
[0017] (9) In silicon carbide epitaxial substrate 100 according to any one of (1) to (8) above, silicon carbide epitaxial layer 40 may have a thickness in a direction perpendicular to first main surface 1 of not less than 7 μm and not more than 15 μm.
[0018] (10) In silicon carbide epitaxial substrate 100 according to any one of (1) to (9) above, first main surface 1 may have a diameter of 100 mm or more.
[0019] (11) A method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes the following steps: Silicon carbide epitaxial substrate 100 according to any one of (1) to (10) above is prepared; Silicon carbide epitaxial substrate 100 is processed.
[0020] [Details of the Embodiments of the Present Disclosure] Hereinafter, the details of the embodiments of the present disclosure will be described with reference to the drawings. Note that in the following drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated.
[0021] (Silicon Carbide Epitaxial Substrate) FIG. 1 is a plan view schematically showing the configuration of a silicon carbide epitaxial substrate 100 according to this embodiment. FIG. 2 is a cross-sectional view schematically showing the configuration along line II-II in FIG. 1. As shown in FIGS. 1 and 2, the silicon carbide epitaxial substrate 100 according to this embodiment has a silicon carbide substrate 30 and a silicon carbide epitaxial layer 40. The silicon carbide epitaxial layer 40 is on the silicon carbide substrate 30. The silicon carbide epitaxial layer 40 is in contact with the silicon carbide substrate 30. The silicon carbide epitaxial layer 40 has a first main surface 1.
[0022] Silicon carbide epitaxial layer 40 forms the front surface (first main surface 1) of silicon carbide epitaxial substrate 100. Silicon carbide substrate 30 forms the back surface (second main surface 2) of silicon carbide epitaxial substrate 100. As shown in FIG. 1 , silicon carbide epitaxial substrate 100 has an outer peripheral edge 5. Outer peripheral edge 5 has, for example, an orientation flat 3 and an arc-shaped portion 4. Orientation flat 3 extends along first direction 101. As shown in FIG. 1 , orientation flat 3 is linear when viewed in a direction perpendicular to first main surface 1. Arc-shaped portion 4 is continuous with orientation flat 3. Arc-shaped portion 4 is arc-shaped when viewed in a direction perpendicular to first main surface 1.
[0023] 1 , when viewed in a direction perpendicular to the first main surface 1, the first main surface 1 extends along a first direction 101 and a second direction 102. When viewed in a direction perpendicular to the first main surface 1, the second direction 102 is a direction perpendicular to the first direction 101.
[0024] The first direction 101 is a direction obtained by projecting the <11-20> direction onto the first main surface 1. From another perspective, the first direction 101 is a direction that includes a <11-20> direction component.
[0025] The second direction 102 is, for example, the <1-100> direction. The second direction 102 may be, for example, the [1-100] direction. The second direction 102 may be, for example, a direction obtained by projecting the <1-100> direction onto the first main surface 1. From another perspective, the second direction 102 may be, for example, a direction including a <1-100> direction component.
[0026] The first main surface 1 is a surface inclined with respect to the {0001} plane. The inclination angle (off angle θ) with respect to the {0001} plane is, for example, greater than 0° and equal to or less than 8°. The off angle θ is not particularly limited, but may be, for example, equal to or greater than 1°, or equal to or greater than 2°. The off angle θ is not particularly limited, but may be, for example, equal to or less than 7°, or equal to or less than 6°. The first main surface 1 may be a surface inclined by the off angle θ with respect to the (000-1) plane, or may be a surface inclined by the off angle θ with respect to the (0001) plane. The inclination direction (off direction) of the first main surface 1 is, for example, the <11-20> direction.
[0027] As shown in FIG. 1 , the maximum diameter W of the first main surface 1 is not particularly limited, but is, for example, 100 mm (4 inches) or more. The maximum diameter W may be 125 mm (5 inches) or more, or 150 mm (6 inches) or more. The maximum diameter W may be, for example, 200 mm (8 inches) or less. The maximum diameter W is the maximum distance between any two points on the outer circumferential edge 5.
[0028] In this specification, 4 inches refers to 100 mm or 101.6 mm (4 inches x 25.4 mm / inch). 6 inches refers to 150 mm or 152.4 mm (6 inches x 25.4 mm / inch). 8 inches refers to 200 mm or 203.2 mm (8 inches x 25.4 mm / inch).
[0029] As shown in FIG. 2 , silicon carbide substrate 30 has second main surface 2 and third main surface 9. Third main surface 9 is on the opposite side to second main surface 2. Second main surface 2 is the back surface of silicon carbide epitaxial substrate 100. Second main surface 2 is spaced apart from silicon carbide epitaxial layer 40. Third main surface 9 is in contact with silicon carbide epitaxial layer 40. The polytype of silicon carbide constituting silicon carbide substrate 30 is, for example, 4H. Similarly, the polytype of silicon carbide constituting silicon carbide epitaxial layer 40 is, for example, 4H.
[0030] 2 , silicon carbide epitaxial layer 40 has a fourth main surface 6. At fourth main surface 6, silicon carbide epitaxial layer 40 is in contact with silicon carbide substrate 30. Silicon carbide epitaxial layer 40 has a buffer layer 41, a transition layer 43, and a drift layer 42. Drift layer 42 may be a single layer, or may be two or more layers.
[0031] The buffer layer 41 is on the silicon carbide substrate 30. The buffer layer 41 is in contact with the silicon carbide substrate 30. The transition layer 43 is on the buffer layer 41. The transition layer 43 is in contact with the buffer layer 41. The drift layer 42 is on the transition layer 43. The drift layer 42 is in contact with the transition layer 43. The drift layer 42 constitutes the first main surface 1. The buffer layer 41 constitutes the fourth main surface 6.
[0032] Silicon carbide substrate 30 contains an n-type impurity such as nitrogen (N). The conductivity type of silicon carbide substrate 30 is, for example, n-type. Silicon carbide substrate 30 has a thickness of, for example, 200 μm or more and 600 μm or less. Silicon carbide epitaxial layer 40 contains an n-type impurity such as nitrogen. The conductivity type of silicon carbide epitaxial layer 40 is, for example, n-type.
[0033] The concentration of n-type impurities contained in buffer layer 41 may be lower than the concentration of n-type impurities contained in silicon carbide substrate 30. The concentration of n-type impurities contained in drift layer 42 may be lower than the concentration of n-type impurities contained in buffer layer 41. The concentration of n-type impurities contained in transition layer 43 may be lower than the concentration of n-type impurities contained in buffer layer 41 and higher than the concentration of n-type impurities contained in drift layer 42.
[0034] The concentration of the n-type impurity contained in the transition layer 43 may monotonically decrease from the buffer layer 41 toward the drift layer 42. The concentration of the n-type impurity contained in the drift layer 42 may be, for example, 1×10 14 cm -3 1x10 or more 17 cm -3 The concentration of the n-type impurity contained in the buffer layer 41 is, for example, 1×10 18 cm -3 1x10 or more 19 cm-3 The following is the result.
[0035] (Stacking Faults and Recesses) Figure 3 is an enlarged schematic plan view of region III in Figure 1. The enlarged schematic plan view shown in Figure 3 shows a state observed with a confocal differential interference contrast microscope. As shown in Figure 3, silicon carbide epitaxial substrate 100 according to this embodiment has stacking faults 20. As shown in Figure 3, stacking faults 20 have, for example, a triangular shape when viewed in a direction perpendicular to first main surface 1.
[0036] Fig. 4 is a schematic cross-sectional view taken along line IV-IV in Fig. 3. The cross section shown in Fig. 4 is a cross section perpendicular to first main surface 1. As shown in Figs. 3 and 4, recesses 29 are formed in first main surface 1 of silicon carbide epitaxial substrate 100 according to this embodiment. Recesses 29 are composed of silicon carbide epitaxial layer 40 and stacking faults 20. When viewed in a direction perpendicular to first main surface 1, recesses 29 have a triangular outer shape.
[0037] As shown in FIG. 3 , the stacking fault 20 has a first side portion 23, a second side portion 24, a first bottom portion 22, and a top surface portion 25. The second side portion 24 is continuous with the first side portion 23. The boundary between the second side portion 24 and the first side portion 23 is the vertex 21. From another perspective, the first side portion 23 and the second side portion 24 branch into two at the vertex 21. The first base portion 22 is continuous with each of the first side portion 23 and the second side portion 24. The first side portion 23 is continuous with one end (first end) of the first bottom portion 22, and the second side portion 24 is continuous with the other end (second end) of the first bottom portion 22. The top surface portion 25 is surrounded by the first side portion 23, the second side portion 24, and the first bottom portion 22. When viewed in a direction perpendicular to the first main surface 1, the shape of the top surface portion 25 is triangular.
[0038] When viewed in a direction perpendicular to the first main surface 1, the first side portion 23 is inclined with respect to each of the first direction 101 and the second direction 102. The first side portion 23 may be inclined from a straight line parallel to the first direction 101 toward the second direction 102. The second side portion 24 may be inclined from a straight line parallel to the first direction 101 in a direction opposite to the second direction 102. When viewed in a direction perpendicular to the first main surface 1, the first base portion 22 extends along the second direction 102. When viewed in a direction perpendicular to the first main surface 1, the width of the stacking fault 20 in the second direction 102 may increase from the vertex 21 toward the first base portion 22.
[0039] 3 , silicon carbide epitaxial layer 40 has a third side portion 63, a fourth side portion 64, and a second bottom portion 62. When viewed in a direction perpendicular to first main surface 1, a portion of third side portion 63 may overlap first side portion 23 of stacking fault 20. When viewed in a direction perpendicular to first main surface 1, a portion of fourth side portion 64 may overlap second side portion 24 of stacking fault 20.
[0040] 3 , when viewed in a direction perpendicular to the first main surface 1, the fourth side portion 64 is connected to the third side portion 63 at the vertex 21. From another perspective, when viewed in a direction perpendicular to the first main surface 1, the third side portion 63 and the fourth side portion 64 branch into two from the vertex 21. The second bottom portion 62 is connected to each of the third side portion 63 and the fourth side portion 64. The third side portion 63 is connected to one end (third end portion) of the second bottom portion 62, and the fourth side portion 64 is connected to the other end (fourth end portion) of the second bottom portion 62.
[0041] When viewed in a direction perpendicular to the first main surface 1, the third side 63 is inclined with respect to each of the first direction 101 and the second direction 102. The third side 63 may be inclined from a straight line parallel to the first direction 101 toward the second direction 102. The third side 63 may be substantially parallel to the first side 23 of the stacking fault 20. The fourth side 64 may be inclined from a straight line parallel to the first direction 101 in a direction opposite to the second direction 102. The fourth side 64 may be substantially parallel to the second side 24 of the stacking fault 20. When viewed in a direction perpendicular to the first main surface 1, the second base 62 extends along the second direction 102. When viewed in a direction perpendicular to the first main surface 1, the second base 62 may be substantially parallel to the first base 22 of the stacking fault 20.
[0042] 3 , the length of stacking fault 20 in first direction 101 is defined as a first length A1. First length A1 is the distance between vertex 21 and first base 22 when viewed in a direction perpendicular to first main surface 1. First length A1 is, for example, not less than 10 μm and not more than 60 μm.
[0043] As shown in FIG. 3 , the length of the recess 29 in the first direction 101 is defined as a second length A2. The second length A2 is the distance between the vertex 21 and the second base portion 62 when viewed in a direction perpendicular to the first main surface 1. The second length A2 is 80 μm or less. The second length A2 is not particularly limited, but may be, for example, 70 μm or less or 60 μm or less. The second length A2 is not particularly limited, but may be, for example, 15 μm or more or 20 μm or more.
[0044] When viewed in a direction perpendicular to the first main surface 1, the width of the recess 29 in the <1-100> direction (second direction 102) is defined as width B. Width B may be equal to the length of the second base portion 62. The ratio of width B to the second length A2 is, for example, 0.5 or more and 5 or less. The ratio of width B to the second length A2 is not particularly limited, but may be, for example, 0.8 or more or 1.2 or more. The ratio of width B to the second length A2 is not particularly limited, but may be, for example, 4 or less or 3 or less. When viewed in a direction perpendicular to the first main surface 1, the width of the recess 29 in the second direction 102 may increase from the apex 21 toward the second base portion 62.
[0045] As shown in Figure 4, the stacking fault 20 may have a first side surface portion 27 and a bottom surface portion 26. The first side surface portion 27 extends along a third direction 103. The bottom surface portion 26 extends along a fourth direction 104. The surface extending along the fourth direction 104 is a basal surface. The bottom surface portion 26 is continuous with the first side surface portion 27. The boundary between the bottom surface portion 26 and the first side surface portion 27 is defined as an origin 28.
[0046] The third direction 103 is a direction perpendicular to each of the first direction 101 and the second direction 102. The fourth direction 104 is inclined with respect to each of the first direction 101 and the third direction 103. The fourth direction 104 is inclined toward the third direction 103 with respect to the first direction 101. The angle formed between the fourth direction 104 and the first direction 101 is an off angle θ.
[0047] The top surface portion 25 is continuous with each of the bottom surface portion 26 and the first side surface portion 27. The top surface portion 25 extends along the first direction 101. The top surface portion 25 may be substantially parallel to the first main surface 1. The top surface portion 25 forms the bottom surface of the recess 29. The plane orientation of the top surface portion 25 may be the same as the plane orientation of the first main surface 1.
[0048] Origin 28 is located within drift layer 42, for example. From another perspective, origin 28 is located between first main surface 1 and transition layer 43, for example, in third direction 103. Silicon carbide epitaxial substrate 100 according to this embodiment does not have downfalls connected to stacking faults 20. Downfalls are, for example, deposits adhering to the inner wall of a film formation apparatus that have fallen onto silicon carbide substrate 30. Downfalls are, for example, particles of polycrystalline silicon carbide. Downfalls may also be, for example, carbon particles.
[0049] A silicon droplet may be present at the initiation point 28. From another perspective, the silicon carbide epitaxial substrate 100 may have a silicon droplet. From another perspective, the silicon carbide epitaxial substrate 100 may have a silicon particle formed by solidification of the silicon droplet at the initiation point 28. From another perspective, the silicon carbide epitaxial substrate 100 may have a silicon particle. At the initiation point 28, the stacking fault 20 may be connected to the silicon particle.
[0050] The length of the stacking fault 20 in the first direction 101 may increase from the initiation point 28 toward the top surface portion 25. The initiation point 28 may be located in the transition layer 43 or in the buffer layer 41. In other words, the bottom surface portion 26 may penetrate through both the transition layer 43 and the drift layer 42.
[0051] 4 , silicon carbide epitaxial layer 40 has second side surface portion 67 and third side surface portion 66. Second side surface portion 67 may extend along third direction 103. Second side surface portion 67 may extend along first side surface portion 27 of stacking fault 20.
[0052] The third side surface portion 66 is continuous with the second side surface portion 67. The third side surface portion 66 extends along the fourth direction 104. The third side surface portion 66 may extend along the bottom surface portion 26 of the stacking fault 20. The second side surface portion 67 and the third side surface portion 66 form the side surfaces of the recess 29.
[0053] 3 and 4 , recess 29 is defined by top surface portion 25 of stacking fault 20 and second side surface portion 67 and third side surface portion 66 of silicon carbide epitaxial layer 40. From another perspective, the bottom surface of recess 29 is defined by stacking fault 20. The side surface of recess 29 is defined by silicon carbide epitaxial layer 40.
[0054] The polytype of silicon carbide constituting stacking fault 20 is different from the polytype of silicon carbide constituting silicon carbide epitaxial layer 40. From another perspective, the polytype of silicon carbide constituting the bottom surface of recess 29 is different from the polytype of silicon carbide constituting silicon carbide epitaxial layer 40. The polytype of silicon carbide constituting stacking fault 20 is, for example, 3C. From another perspective, the polytype of silicon carbide constituting the bottom surface of recess 29 is, for example, 3C.
[0055] 4 , silicon carbide epitaxial layer 40 has a thickness H in a direction perpendicular to first main surface 1. Thickness H is, for example, 7 μm or more and 15 μm or less. Thickness H is not particularly limited, but may be, for example, 8 μm or more, or 9 μm or more. Thickness H is not particularly limited, but may be, for example, 14 μm or less, or 13 μm or less.
[0056] As shown in Figure 4, the depth of the recess 29 in a direction perpendicular to the first main surface 1 is depth D. Depth D is the distance between the first main surface 1 and the top surface portion 25 in a direction perpendicular to the first main surface 1. Depth D is 100 nm or more. Depth D is not particularly limited, but may be, for example, 105 nm or more, or 110 nm or more. Depth D is not particularly limited, but may be, for example, 140 nm or less, 135 nm or less, or 130 nm or less.
[0057] The depth D can be measured using, for example, a white light interference microscope manufactured by Nikon Corporation (product name "BW-D507"). A mercury lamp is used as the light source. The measurement field of view is 256 μm × 256 μm. Light emitted from the light source is split into two by a beam splitter. One light is irradiated onto a reference surface. The other light is irradiated onto the first principal surface 1 and the top surface portion 25. The light reflected from both surfaces forms an image on a camera. The depth D is measured based on information about interference fringes obtained from the optical path difference caused by the unevenness formed on the first principal surface 1 and the top surface portion 25.
[0058] (Area Density of Recesses) Next, a method for measuring the area density of recesses 29 on first main surface 1 will be described. Recesses 29 are identified by observing first main surface 1 of silicon carbide epitaxial substrate 100 using a defect inspection device having a confocal differential interference microscope. As a defect inspection device having a confocal differential interference microscope, for example, a WASAVI series "SICA 6X" manufactured by Lasertec Corporation can be used. The magnification of the objective lens is, for example, 10x. Light with a wavelength of 546 nm is irradiated onto first main surface 1 of silicon carbide epitaxial substrate 100 from a light source such as a mercury xenon lamp, and the reflected light of the light is observed by a light receiving element. A threshold value, which is an index of the measurement sensitivity of SICA, is, for example, ThreshS40.
[0059] The number of recesses 29 is determined in the measurement region of first main surface 1. Specifically, first, a confocal differential interference contrast image (SICA image) is measured in the entire measurement region of first main surface 1 of silicon carbide epitaxial substrate 100 using "SICA 6X." The total number of recesses 29 in the measurement region of first main surface 1 is counted based on the SICA image. The surface density of recesses 29 on first main surface 1 is the total number of recesses 29 in the measurement region of first main surface 1 divided by the area of the measurement region of first main surface 1. Note that, on first main surface 1, a region within 5 mm from outer circumferential edge 5 is excluded from the measurement region for the surface density of recesses 29 (edge exclusion).
[0060] The surface density of the recesses 29 on the first main surface 1 is 0.1 / cm 2The surface density of the recesses 29 on the first main surface 1 is not particularly limited, but may be, for example, 0.08 pieces / cm 2 or less, and may be 0.06 particles / cm 2 The surface density of the recesses 29 on the first main surface 1 is not particularly limited, but may be, for example, 0.005 pieces / cm 2 It may be 0.01 particles / cm or more. 2 or more, or 0.02 particles / cm 2 It may be more than that.
[0061] (Apparatus for manufacturing silicon carbide epitaxial substrate) Next, the configuration of an apparatus for manufacturing silicon carbide epitaxial substrate 100 will be described. FIG. 5 is a partial cross-sectional schematic diagram showing the configuration of an apparatus for manufacturing silicon carbide epitaxial substrate 100. Apparatus 300 for manufacturing silicon carbide epitaxial substrate 100 is, for example, a hot-wall horizontal CVD (Chemical Vapor Deposition) apparatus. As shown in FIG. 5, apparatus 300 for manufacturing silicon carbide epitaxial substrate 100 mainly includes reaction chamber 201, gas supply unit 235, control unit 245, heating element 203, quartz tube 204, a heat insulating material (not shown), and an induction heating coil (not shown).
[0062] The heating element 203 has, for example, a cylindrical shape, and defines a reaction chamber 201 therein. The heating element 203 is made of, for example, graphite. The heating element 203 is provided inside a quartz tube 204. A heat insulating material surrounds the outer periphery of the heating element 203. The induction heating coil is wound, for example, along the outer periphery of the quartz tube 204. The induction heating coil is configured so that an alternating current can be supplied to it from an external power source (not shown). This causes the heating element 203 to be induction heated. As a result, the reaction chamber 201 is heated by the heating element 203.
[0063] The reaction chamber 201 is a space surrounded by an inner wall surface 205 of a heating element 203. A susceptor 210 that holds a silicon carbide substrate 30 is provided in the reaction chamber 201. The susceptor 210 is made of silicon carbide. The silicon carbide substrate 30 is placed on the susceptor 210. The susceptor 210 is placed on a stage 202. The stage 202 is rotatably supported by a rotation shaft 209. The rotation of the stage 202 causes the susceptor 210 to rotate.
[0064] Manufacturing apparatus 300 for silicon carbide epitaxial substrate 100 further has gas inlet 207 and gas exhaust outlet 208. Gas exhaust outlet 208 is connected to an exhaust pump (not shown). Arrows in Fig. 5 indicate the flow of gas. Gas is introduced into reaction chamber 201 from gas inlet 207 and exhausted from gas exhaust outlet 208. The pressure inside reaction chamber 201 is adjusted by balancing the amount of gas supplied and the amount of gas exhausted.
[0065] The gas supply unit 235 is configured to be able to supply a mixed gas containing a source gas, a dopant gas, and a carrier gas to the reaction chamber 201. Specifically, the gas supply unit 235 includes, for example, a first gas supply unit 231, a second gas supply unit 232, a third gas supply unit 233, and a fourth gas supply unit 234.
[0066] The first gas supply unit 231 is configured to be able to supply a first gas containing, for example, carbon atoms. The first gas supply unit 231 is, for example, a gas cylinder filled with the first gas. The first gas is, for example, propane (C3H8) gas. The first gas may also be, for example, methane (CH4) gas, ethane (C2H6) gas, acetylene (C2H2) gas, etc.
[0067] The second gas supply unit 232 is configured to be able to supply a second gas containing, for example, silane gas. The second gas supply unit 232 is, for example, a gas cylinder filled with the second gas. The second gas is, for example, silane (SiH4) gas. The second gas may be a mixed gas of silane gas and a gas other than silane.
[0068] The third gas supply unit 233 is configured to be able to supply a third gas containing, for example, nitrogen atoms. The third gas supply unit 233 is, for example, a gas cylinder filled with the third gas. The third gas is a doping gas. The third gas is, for example, ammonia gas. Ammonia gas is more susceptible to thermal decomposition than nitrogen gas, which has a triple bond.
[0069] The fourth gas supply unit 234 is configured to be able to supply a fourth gas (carrier gas) such as hydrogen. The fourth gas supply unit 234 is, for example, a gas cylinder filled with hydrogen. The fourth gas may be argon gas.
[0070] The control unit 245 is configured to be able to control the flow rate of the mixed gas supplied from the gas supply unit 235 to the reaction chamber 201. Specifically, the control unit 245 may include a first gas flow rate control unit 241, a second gas flow rate control unit 242, a third gas flow rate control unit 243, and a fourth gas flow rate control unit 244. Each control unit may be, for example, an MFC (Mass Flow Controller). The control unit 245 is disposed between the gas supply unit 235 and the gas inlet 207.
[0071] (Method for Manufacturing Silicon Carbide Epitaxial Substrate) Next, a method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment will be described.
[0072] First, a silicon carbide substrate 30 is prepared. A silicon carbide single crystal of polytype 4H is manufactured by, for example, sublimation. Next, the silicon carbide single crystal is sliced by, for example, a wire saw, to prepare the silicon carbide substrate 30. The silicon carbide substrate 30 contains an n-type impurity, for example, nitrogen. The conductivity type of the silicon carbide substrate 30 is, for example, n-type. Next, mechanical polishing is performed on the silicon carbide substrate 30. Next, chemical mechanical polishing is performed on the silicon carbide substrate 30.
[0073] Next, silicon carbide epitaxial layer 40 is formed on silicon carbide substrate 30. Specifically, using a hot-wall type horizontal CVD apparatus shown in FIG. 5 , silicon carbide epitaxial layer 40 is formed by epitaxial growth on third main surface 9 of silicon carbide substrate 30. In the epitaxial growth, for example, silane (SiH 4 ) and propane (C 3 H 8 ) are used as source gases, and hydrogen (H 2 ) is used as a carrier gas. In the epitaxial growth, an n-type impurity such as nitrogen is introduced into silicon carbide epitaxial layer 40.
[0074] 6 is a schematic diagram showing the relationship between the silane flow rate and time relative to temperature. The silane flow rate relative to temperature is the value obtained by dividing the silane flow rate (sccm) by the temperature (°C). As shown in FIG. 6 , at a first point in time P1, the silane flow rate relative to temperature is set to a first ratio C1. Between the first point in time P1 and the second point in time P2, the silane flow rate relative to temperature is maintained at the first ratio C1. Between the first point in time P1 and the second point in time P2, a buffer layer 41 is formed on the silicon carbide substrate 30.
[0075] From the second point in time P2 to the third point in time P3, the silane flow rate with respect to temperature increases monotonically. From the second point in time P2 to the third point in time P3, the silane flow rate with respect to temperature increases from a first ratio C1 to a second ratio C2. From the second point in time P2 to the third point in time P3, a transition layer 43 is formed on the buffer layer 41. From the third point in time P3 to the fourth point in time P4, the silane flow rate with respect to temperature is maintained at the second ratio C2. From the third point in time P3 to the fourth point in time P4, a drift layer 42 is formed on the transition layer 43.
[0076] The silane flow rate versus temperature is adjusted by varying both the silane flow rate and the temperature. The first rate C1 is, for example, 0.036 (sccm / °C). The second rate C2 is, for example, 0.044 (sccm / °C). From the second point P2 to the third point P3, the rate of increase of the silane flow rate versus temperature is, for example, 0.002 (sccm / °C) per minute.
[0077] The temperature at which drift layer 42 is formed is higher than the temperature at which buffer layer 41 is formed, for example. The temperature at which drift layer 42 is formed is 1720°C, for example. The temperature at which buffer layer 41 is formed is 1610°C, for example. In the step of forming transition layer 43, the temperature is elevated, for example. In this manner, silicon carbide epitaxial substrate 100 including silicon carbide substrate 30 and silicon carbide epitaxial layer 40 is fabricated (see FIG. 2 ).
[0078] Silane gas and propane gas are used to form silicon carbide epitaxial layer 40. When compared at the same temperature, silane gas has the property of decomposing more easily than propane gas. After extensive research, the inventors discovered that recesses 29 can be reduced by controlling the ratio of the silane gas flow rate to the temperature.
[0079] It is believed that stacking faults 20 and recesses 29 are generated due to silicon droplets. Specifically, it is believed that stacking faults 20 are generated due to silicon droplets, and that stacking faults 20 form recesses 29. It is believed that the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment can suppress the generation of silicon droplets from decomposed silane gas, thereby suppressing the generation of stacking faults 20 due to silicon droplets. It is believed that this can reduce the surface density of recesses 29 on first main surface 1.
[0080] (Method of Manufacturing Silicon Carbide Semiconductor Device) Next, a method of manufacturing the silicon carbide semiconductor device 400 according to this embodiment will be described. FIG. 7 is a flowchart that schematically shows the method of manufacturing the silicon carbide semiconductor device according to this embodiment. As shown in FIG. 7, the method of manufacturing the silicon carbide semiconductor device 400 according to this embodiment mainly includes a step (S1) of preparing a silicon carbide epitaxial substrate and a step (S2) of processing the silicon carbide epitaxial substrate.
[0081] First, the step of preparing a silicon carbide epitaxial substrate (S1) is performed. In the step of preparing a silicon carbide epitaxial substrate (S1), a silicon carbide epitaxial substrate 100 according to the present embodiment is prepared (see FIG. 1).
[0082] Next, the step (S2) of processing the silicon carbide epitaxial substrate is carried out. Specifically, the following processing is carried out on silicon carbide epitaxial substrate 100. First, ions are implanted into silicon carbide epitaxial substrate 100.
[0083] 8 is a schematic cross-sectional view showing a step of forming a body region. In the step of forming the body region, p-type impurities such as aluminum are ion-implanted into first main surface 1 of silicon carbide epitaxial layer 40. This forms body region 113 having p-type conductivity. The portion where body region 113 is not formed becomes drift layer 42. The thickness of body region 113 is, for example, 0.9 μm.
[0084] Next, a step of forming a source region is performed. FIG. 9 is a schematic cross-sectional view showing the step of forming the source region. Specifically, n-type impurities such as phosphorus are ion-implanted into the body region 113. This forms a source region 114 having n-type conductivity. The thickness of the source region 114 is, for example, 0.4 μm. The concentration of the n-type impurities contained in the source region 114 is higher than the concentration of the p-type impurities contained in the body region 113.
[0085] Next, a p-type impurity such as aluminum is ion-implanted into the source region 114 to form a contact region 118. The contact region 118 is formed to penetrate the source region 114 and the body region 113 and to be in contact with the drift layer 42. The concentration of the p-type impurity contained in the contact region 118 is higher than the concentration of the n-type impurity contained in the source region 114.
[0086] Next, activation annealing is performed to activate the implanted impurities. The temperature of the activation annealing is, for example, 1500° C. or higher and 1900° C. or lower. The activation annealing time is, for example, about 30 minutes. The atmosphere of the activation annealing is, for example, an argon atmosphere.
[0087] Next, a step of forming trenches in first main surface 1 of silicon carbide epitaxial layer 40 is performed. FIG. 10 is a cross-sectional schematic diagram showing the step of forming trenches in first main surface 1 of silicon carbide epitaxial layer 40. A mask 117 having openings is formed on first main surface 1 including source region 114 and contact region 118. Using mask 117, source region 114, body region 113, and a portion of drift layer 42 are removed by etching. As an etching method, for example, inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF or a mixed gas of SF and O as a reactive gas is used. A recess is formed in first main surface 1 by etching.
[0088] Next, thermal etching is performed on the recesses. Thermal etching can be performed, for example, by heating the first main surface 1 with the mask 117 formed thereon in an atmosphere containing a reactive gas having at least one type of halogen atom. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, Cl2, BCl3, SF6, or CF4. For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as the reactive gas, with the heat treatment temperature set to, for example, 700°C or higher and 1000°C or lower. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. Examples of the carrier gas that can be used include nitrogen gas, argon gas, and helium gas.
[0089] 10 , a trench 56 is formed in the first main surface 1 by thermal etching. The trench 56 is defined by a sidewall surface 53 and a bottom wall surface 54. The sidewall surface 53 is formed by the source region 114, the body region 113, and the drift layer 42. The bottom wall surface 54 is formed by the drift layer 42. Next, the mask 117 is removed from the first main surface 1.
[0090] Next, a step of forming a gate insulating film is performed. FIG. 11 is a cross-sectional schematic view showing the step of forming a gate insulating film. Specifically, silicon carbide epitaxial substrate 100 having trench 56 formed in first main surface 1 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. This forms gate insulating film 115 that is in contact with drift layer 42 at bottom wall surface 54, in contact with drift layer 42, body region 113, and source region 114 at sidewall surface 53, and in contact with source region 114 and contact region 118 at first main surface 1.
[0091] Next, a step of forming a gate electrode is performed. FIG. 12 is a schematic cross-sectional view showing the step of forming a gate electrode and an interlayer insulating film. The gate electrode 127 is formed inside the trench 56 so as to be in contact with the gate insulating film 115. The gate electrode 127 is disposed inside the trench 56 and is formed on the gate insulating film 115 so as to face each of the sidewall surface 53 and the bottom wall surface 54 of the trench 56. The gate electrode 127 is formed by, for example, a low pressure chemical vapor deposition (LPCVD) method.
[0092] Next, an interlayer insulating film 126 is formed. The interlayer insulating film 126 is formed so as to cover the gate electrode 127 and to be in contact with the gate insulating film 115. The interlayer insulating film 126 is formed by, for example, chemical vapor deposition. The interlayer insulating film 126 is made of, for example, a material containing silicon dioxide. Next, the interlayer insulating film 126 and part of the gate insulating film 115 are etched so as to form openings over the source region 114 and the contact region 118. As a result, the contact region 118 and the source region 114 are exposed from the gate insulating film 115.
[0093] Next, a step of forming a source electrode is performed. The source electrode 116 is formed so as to be in contact with each of the source region 114 and the contact region 118. The source electrode 116 is formed by, for example, a sputtering method. The source electrode 116 is made of, for example, a material containing Ti (titanium), Al (aluminum), and Si (silicon).
[0094] Next, alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is maintained at a temperature of, for example, 900° C. or higher and 1100° C. or lower for about 5 minutes. As a result, at least a portion of the source electrode 116 is silicided. This forms the source electrode 116 in ohmic contact with the source region 114. The source electrode 116 may also form an ohmic contact with the contact region 118.
[0095] Next, the source wiring 119 is formed. The source wiring 119 is electrically connected to the source electrode 116. The source wiring 119 is formed so as to cover the source electrode 116 and the interlayer insulating film 126.
[0096] Next, a step of forming a drain electrode is carried out. First, silicon carbide substrate 30 is polished at second main surface 2. This reduces the thickness of silicon carbide substrate 30. Next, drain electrode 123 is formed. Drain electrode 123 is formed so as to be in contact with second main surface 2. In this manner, silicon carbide semiconductor device 400 according to this embodiment is manufactured.
[0097] 13 is a cross-sectional schematic diagram showing the configuration of a silicon carbide semiconductor device according to this embodiment. Silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Silicon carbide semiconductor device 400 mainly includes silicon carbide epitaxial substrate 100, gate electrode 127, gate insulating film 115, source electrode 116, drain electrode 123, source wiring 119, and interlayer insulating film 126. Silicon carbide epitaxial substrate 100 includes drift layer 42, body region 113, source region 114, and contact region 118. Silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like.
[0098] Next, the effects of the method for manufacturing silicon carbide epitaxial substrate 100 and the silicon carbide semiconductor device according to this embodiment will be described.
[0099] Typically, in the process of fabricating silicon carbide epitaxial substrate 100, the higher the flow rate of silane, the faster the growth rate of silicon carbide epitaxial layer 40. However, if the flow rate of silane is excessively high, the yield of silicon carbide semiconductor devices may decrease.
[0100] The inventors have made the following findings while conducting a detailed investigation into the causes of the decrease in yield of silicon carbide semiconductor devices. Specifically, the inventors have found that when silicon carbide semiconductor device 400 is fabricated using silicon carbide epitaxial substrate 100 on which recesses 29 having a certain shape are formed, silicon carbide semiconductor device 400 is likely to suffer from poor characteristics.
[0101] The recesses 29 having a certain shape are thought to be generated due to silicon droplets in the process of forming the silicon carbide epitaxial layer 40. Stacking faults 20 generated due to downfall of carbon particles or silicon carbide particles may protrude in the third direction 103 relative to the first main surface 1. On the other hand, stacking faults 20 generated due to silicon droplets are thought to form recesses 29 without protruding relative to the first main surface 1.
[0102] For this reason, the inventors focused on the flow rate of silane relative to the temperature in the method for manufacturing silicon carbide epitaxial substrate 100. If the flow rate of silane relative to the temperature is excessively high, silane will decompose excessively, generating silicon droplets. This is thought to result in an increase in recesses 29 on first main surface 1. Conversely, if the flow rate of silane relative to the temperature is excessively low, the growth rate of silicon carbide epitaxial layer 40 will be excessively slow. It is thought that the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment can reduce the areal density of recesses 29 on first main surface 1 while maintaining a high growth rate of silicon carbide epitaxial layer 40.
[0103] In silicon carbide epitaxial substrate 100 according to the present disclosure, the surface density of recesses 29 on first main surface 1 is 0.1 / cm 2This allows for an improvement in yield of silicon carbide semiconductor devices 400 fabricated using silicon carbide epitaxial substrates 100.
[0104] In silicon carbide epitaxial substrate 100 according to the present disclosure, first main surface 1 has a diameter (maximum diameter W) of 100 mm or more. Even when silicon carbide epitaxial substrate 100 with such a large diameter is used, the yield of silicon carbide semiconductor device 400 can be improved.
[0105] (Sample Preparation) First, silicon carbide epitaxial substrates 100 according to Samples 1 to 6 were prepared. Silicon carbide epitaxial substrates 100 according to Samples 1 to 3 are comparative examples. Silicon carbide epitaxial substrates 100 according to Samples 4 to 6 are examples. The silicon carbide epitaxial substrates 100 according to Samples 1 to 6 had a diameter of 150 mm.
[0106] Silicon carbide epitaxial substrates 100 according to Samples 1 to 6 were manufactured according to the method shown in FIG.
[0107]
[0108] Silicon carbide epitaxial substrates 100 according to Samples 1 to 3 were manufactured as follows.
[0109] Between the first time point P1 and the second time point P2, the temperature of the reaction chamber 201 was set to 1610° C. Between the second time point P2 and the third time point P3, the temperature increased from 1610° C. to 1720° C. Between the third time point P3 and the fourth time point P4, the temperature was set to 1720° C. Between the first time point P1 and the fourth time point P4, the H flow rate was set to 134 slm.
[0110] The SiH flow rate was 57.5 sccm between the first point P1 and the second point P2, increased from 57.5 sccm to 96 sccm between the second point P2 and the third point P3, and maintained at 96 sccm between the third point P3 and the fourth point P4.
[0111] Between the first point P1 and the second point P2, the C3H8 flow rate was set to 18 sccm. Between the second point P2 and the third point P3, the C3H8 flow rate increased from 18 sccm to 54.5 sccm. Between the third point P3 and the fourth point P4, the C3H8 flow rate was set to 54.5 sccm.
[0112] The time from the first time point P1 to the second time point P2 was 20 minutes, the time from the second time point P2 to the third time point P3 was 4 minutes, and the time from the third time point P3 to the fourth time point P4 was 90 minutes.
[0113] From the first point P1 to the second point P2, the SiH flow rate / temperature (sccm / °C) was 0.036. From the second point P2 to the third point P3, the SiH flow rate / temperature (sccm / °C) increased at a rate of 0.005 per minute. From the third point P3 to the fourth point P4, the SiH flow rate / temperature (sccm / °C) was 0.056.
[0114] Silicon carbide epitaxial substrates 100 according to Samples 4 to 6 were manufactured as follows.
[0115] Between the first time point P1 and the second time point P2, the temperature was set to 1610° C. Between the second time point P2 and the third time point P3, the temperature increased from 1610° C. to 1720° C. Between the third time point P3 and the fourth time point P4, the temperature was set to 1610° C. Between the first time point P1 and the fourth time point P4, the H flow rate was set to 134 slm.
[0116] The SiH flow rate was 57.5 sccm from the first point P1 to the second point P2, increased from 57.5 sccm to 75 sccm from the second point P2 to the third point P3, and maintained at 75 sccm from the third point P3 to the fourth point P4.
[0117] Between the first point P1 and the second point P2, the C3H8 flow rate was set to 18 sccm. Between the second point P2 and the third point P3, the C3H8 flow rate increased from 18 sccm to 37.5 sccm. Between the third point P3 and the fourth point P4, the C3H8 flow rate was set to 37.5 sccm.
[0118] The time from the first time point P1 to the second time point P2 was 20 minutes, the time from the second time point P2 to the third time point P3 was 4 minutes, and the time from the third time point P3 to the fourth time point P4 was 90 minutes.
[0119] From the first point P1 to the second point P2, the SiH flow rate / temperature (sccm / °C) was 0.036. From the second point P2 to the third point P3, the SiH flow rate / temperature (sccm / °C) increased at a rate of 0.002 per minute. From the third point P3 to the fourth point P4, the SiH flow rate / temperature (sccm / °C) was 0.044.
[0120] (Experimental Method) Images of the first main surface 1 of the silicon carbide epitaxial substrate 100 for Samples 1 to 6 were taken using a WASAVI series "SICA 6X" confocal differential interference microscope manufactured by Lasertec Corporation. The areal density of the recesses 29 was calculated by dividing the number of recesses 29 in a measurement region of the first main surface 1 by the area of the measurement region of the first main surface 1. The magnification of the objective lens was 10x. Light with a wavelength of 546 nm was irradiated onto the first main surface 1 of the silicon carbide epitaxial substrate 100 from a light source such as a mercury-xenon lamp, and the reflected light was observed using a light-receiving element. A threshold value, which is an index of the measurement sensitivity of the SICA, was set to, for example, ThreshS40. The region of the first main surface 1 within 5 mm of the outer circumferential edge 5 was excluded from the measurement region for the areal density of the recesses 29.
[0121] (Experimental results)
[0122]
[0123] Table 2 shows the areal density of recesses 29 in silicon carbide epitaxial substrate 100. As shown in Table 2, the areal density of recesses 29 in silicon carbide epitaxial substrate 100 according to Samples 4 to 6 is smaller than the areal density of recesses 29 in silicon carbide epitaxial substrate 100 according to Samples 1 to 3. The areal density of recesses 29 in silicon carbide epitaxial substrate 100 according to Samples 4 to 6 is 0.1 recesses / cm 2 It was as follows.
[0124] From the above results, it was confirmed that the surface density of recesses 29 was reduced in silicon carbide epitaxial substrate 100 of the example compared to silicon carbide epitaxial substrate 100 of the comparative example.
[0125] The present disclosure includes the following embodiments: (Supplementary Note 1) A silicon carbide substrate, and a silicon carbide epitaxial layer on the silicon carbide substrate and having a main surface, wherein recesses are formed in the main surface, the recesses have a triangular outer shape when viewed in a direction perpendicular to the main surface, the depth of the recesses in the direction perpendicular to the main surface is 100 nm or more, the length of the recesses in a direction projecting the <11-20> direction onto the first main surface is 80 μm or less, and the areal density of the recesses on the main surface is 0.1 / cm 2a silicon carbide epitaxial substrate according to claim 1, wherein the polytype of silicon carbide constituting the bottom surface of the recess is different from the polytype of silicon carbide constituting the silicon carbide epitaxial layer; (Supplementary Note 2) The silicon carbide epitaxial substrate according to claim 1, wherein the depth of the recess in a direction perpendicular to the main surface is 140 nm or less; (Supplementary Note 3) The silicon carbide epitaxial substrate according to claim 1 or 2, wherein the length of the recess in a direction projecting the <11-20> direction onto the first main surface is 15 μm or more; (Supplementary Note 4) The silicon carbide epitaxial substrate according to claim 1 or 2, wherein the polytype of silicon carbide constituting the bottom surface of the recess is 3C; (Supplementary Note 5) The silicon carbide epitaxial substrate according to claim 1 or 2, wherein the polytype of silicon carbide constituting the silicon carbide epitaxial layer is 4H. (Note 6) The surface density of the recesses on the main surface is 0.005 pieces / cm 2 The silicon carbide epitaxial substrate according to Appendix 1 or Appendix 2, wherein the main surface is a plane inclined with respect to the (000-1) plane. (Appendix 7) The silicon carbide epitaxial substrate according to Appendix 1 or Appendix 2, wherein the main surface is a plane inclined with respect to the (000-1) plane. (Appendix 8) The silicon carbide epitaxial substrate according to Appendix 1 or Appendix 2, further having stacking faults constituting bottom surfaces of the recesses, and wherein the silicon carbide epitaxial substrate is free from downfalls continuous with the stacking faults. (Appendix 9) The silicon carbide epitaxial substrate according to Appendix 1 or Appendix 2, wherein the silicon carbide epitaxial layer has a thickness of 7 μm or more and 15 μm or less in a direction perpendicular to the main surface. (Appendix 10) The silicon carbide epitaxial substrate according to Appendix 1 or Appendix 2, wherein the main surface has a diameter of 100 mm or more. (Supplementary Note 11) A method for manufacturing a silicon carbide semiconductor device, comprising: preparing the silicon carbide epitaxial substrate according to Supplementary Note 1 or Supplementary Note 2; and processing the silicon carbide epitaxial substrate.
[0126] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments, and is intended to include meanings equivalent to the claims and all modifications within the scope thereof.
[0127] 1 First main surface, 2 Second main surface, 3 Orientation flat, 4 Circular arc portion, 5 Outer periphery, 6 Fourth main surface, 9 Third main surface, 20 Stacking fault, 21 Vertex, 22 First bottom portion, 23 First side portion, 24 Second side portion, 25 Top surface portion, 26 Bottom surface portion, 27 First side portion, 28 Starting point, 29 Recess, 30 Silicon carbide substrate, 40 Silicon carbide epitaxial layer, 41 Buffer layer, 42 Drift layer, 43 Transition layer, 53 Side wall surface, 54 Bottom wall surface, 56 Trench, 62 Second bottom portion, 63 Third side portion, 64 Fourth side portion, 66 Third side portion, 67 Second side portion, 100 Silicon carbide epitaxial substrate, 101 First direction, 102 Second direction, 103 Third direction, 104 Fourth direction, 113 body region, 114 source region, 115 gate insulating film, 116 source electrode, 117 mask, 118 contact region, 119 source wiring, 123 drain electrode, 126 interlayer insulating film, 127 gate electrode, 201 reaction chamber, 202 stage, 203 heating element, 204 quartz tube, 205 inner wall surface, 207 gas inlet, 208 gas exhaust port, 209 rotation shaft, 210 susceptor, 231 first gas supply unit, 232 second gas supply unit, 233 third gas supply unit, 234 fourth gas supply unit, 235 gas supply unit, 241 first gas flow rate control unit, 242 second gas flow rate control unit, 243 third gas flow rate control unit, 244 fourth gas flow rate control unit, 245 control unit, 300 manufacturing apparatus, 400 silicon carbide semiconductor device, A1 First length, A2 Second length, B Width, C1 First ratio, C2 Second ratio, D Depth, H Thickness, P1 First point in time, P2 Second point in time, P3 Third point in time, P4 Fourth point in time, W Maximum diameter, θ Off angle.
Claims
1. a silicon carbide substrate; a silicon carbide epitaxial layer on the silicon carbide substrate and having a main surface; A recess is formed in the main surface, When viewed in a direction perpendicular to the main surface, the recess has a triangular outer shape, The depth of the recess in a direction perpendicular to the main surface is 100 nm or more; The length of the recess in the direction projected onto the main surface in the <11-20> direction is 80 μm or less, The surface density of the recesses on the main surface is 0.1 / cm 2 is as follows: a polytype of silicon carbide constituting a bottom surface of the recess is different from a polytype of silicon carbide constituting the silicon carbide epitaxial layer.
2. 2 . The silicon carbide epitaxial substrate according to claim 1 , wherein a depth of said recess in a direction perpendicular to said main surface is not more than 140 nm.
3. 3. The silicon carbide epitaxial substrate according to claim 1, wherein a length of said recess in a direction projected onto said principal surface in a <11-20> direction is 15 μm or more.
4. 3. The silicon carbide epitaxial substrate according to claim 1, wherein a polytype of silicon carbide constituting a bottom surface of said recess is 3C.
5. 3. The silicon carbide epitaxial substrate according to claim 1, wherein a polytype of silicon carbide constituting said silicon carbide epitaxial layer is 4H.
6. The surface density of the recesses on the main surface is 0.005 cm 2 The silicon carbide epitaxial substrate according to claim 1 or 2.
7. 3. The silicon carbide epitaxial substrate according to claim 1, wherein the main surface is inclined with respect to a (000-1) plane.
8. The recess further has a stacking fault constituting a bottom surface of the recess, 3. The silicon carbide epitaxial substrate according to claim 1, which is free of downfalls connected to said stacking faults.
9. 3. The silicon carbide epitaxial substrate according to claim 1, wherein the silicon carbide epitaxial layer has a thickness of not less than 7 μm and not more than 15 μm in a direction perpendicular to the main surface.
10. 3. The silicon carbide epitaxial substrate according to claim 1, wherein the main surface has a diameter of 100 mm or more.
11. A step of preparing a silicon carbide epitaxial substrate according to claim 1 or 2; and processing the silicon carbide epitaxial substrate.