Switching power supply circuit and switching power supply device

Abstract

The present invention obtains an output voltage by rectifying and smoothing a voltage generated by an operation that switches between a high-side transistor and a low-side transistor. The switching operation is performed on the basis of voltage information corresponding to the output voltage and coil current information generated through a current sensing operation. The switching frequency can be set to a first frequency or a second frequency (< the first frequency). For the second frequency, for a portion of the period from when the most recent current sensing operation was performed until the next current sensing operation is performed, coil current information is generated by adding pseudo current information to information about the current detected by the most recent current sensing operation.

Description

Switching power supply circuit and switching power supply device

[0001] The present disclosure relates to a switching power supply circuit and a switching power supply device.

[0002] One type of switching power supply device includes a high-side transistor and a low-side transistor connected in series, and a rectifying / smoothing circuit having a coil and an output capacitor connected to their connection node. An input voltage is applied between the high-side transistor and the low-side transistor. The high-side transistor and the low-side transistor are alternately turned on and off to generate a rectangular waveform voltage, which is rectified and smoothed by the rectifying / smoothing circuit to obtain an output voltage lower than the input voltage. In this case, current-mode control based on the coil current may be performed.

[0003] Japanese Patent Application Laid-Open No. 2019-221099

[0004] In applications where the input voltage is sufficiently high compared to the output voltage, the on-time of the high-side transistor in each switching cycle becomes significantly short, while the on-time of the low-side transistor becomes sufficiently long. For this reason, the coil current required for current mode control can be detected by performing current detection operation to detect the current flowing through the low-side transistor while it is on.

[0005] However, when the input voltage temporarily drops, the on-time of the low-side transistor decreases as the duty cycle increases in pulse width modulation, and the time required for current detection may not be secured. In such cases, lowering the switching frequency can secure the time required for current detection while also increasing the maximum duty cycle. However, lowering the switching frequency increases the interval between current detection operations, leading to unstable control and fluctuations in the output voltage.

[0006] An object of the present disclosure is to provide a switching power supply circuit and a switching power supply device that contribute to stabilizing the output voltage.

[0007] A switching power supply circuit according to the present disclosure is used in a switching power supply device for generating an output voltage by switching an input voltage, and includes: an output stage circuit having a high-side transistor and a low-side transistor connected in series between an input terminal receiving the input voltage and a ground terminal; a switching control circuit configured to perform a switching operation of alternately turning on and off the high-side transistor and the low-side transistor; and a current information generation circuit configured to perform a current sensing operation of detecting a current flowing through the low-side transistor during an on period of the low-side transistor, wherein a connection node between the high-side transistor and the low-side transistor is connected to a rectifying and smoothing circuit including a coil and an output capacitor, and a switching voltage generated at the connection node by the current sensing operation is rectified and smoothed by the rectifying and smoothing circuit to generate the output voltage, the switching control circuit performs the switching operation based on voltage information corresponding to the output voltage and current information of the coil generated through the current sensing operation, the switching control circuit is capable of setting a switching frequency in the switching operation to a first frequency or a second frequency lower than the first frequency, and when the switching frequency is set to the second frequency, the current information generating circuit generates current information of the coil by adding pseudo current information based on the input voltage and the output voltage to detected current information by the most recent current sensing operation during a part of a period from when the most recent current sensing operation was performed until when the next current sensing operation is performed.Another switching power supply circuit according to the present disclosure is a switching power supply circuit used in a switching power supply device for generating an output voltage through switching of an input voltage, the switching power supply circuit comprising: an output stage circuit having a high-side transistor and a low-side transistor connected in series with each other between an input terminal receiving the input voltage and a ground terminal; a switching control circuit configured to perform a switching operation of alternately turning on and off the high-side transistor and the low-side transistor; and a current information generation circuit configured to perform a first current sense operation of detecting a current flowing through the low-side transistor during an on period of the low-side transistor, or a second current sense operation of detecting a current flowing through the high-side transistor during an on period of the high-side transistor, a connection node between the low-side transistors is connected to a rectifying and smoothing circuit including a coil and an output capacitor, a switching voltage generated at the connection node by the switching operation is rectified and smoothed by the rectifying and smoothing circuit to generate the output voltage, the switching control circuit performs the switching operation based on voltage information corresponding to the output voltage and current information of the coil, and is capable of setting a switching frequency in the switching operation to a first frequency or a second frequency lower than the first frequency, and the current information generation circuit generates current information of the coil by the first current sensing operation when the switching frequency is set to the first frequency, and generates current information of the coil by using a combination of the first current sensing operation and the second current sensing operation when the switching frequency is set to the second frequency.

[0008] According to the present disclosure, it is possible to provide a switching power supply circuit and a switching power supply device that contribute to stabilizing the output voltage.

[0009] FIG. 1 is an overall configuration diagram of a switching power supply device according to a first embodiment of the present disclosure. FIG. 2 is an external perspective view of a power supply IC according to a first embodiment of the present disclosure. FIG. 3 is a configuration diagram of a switching power supply device showing the internal configuration of the power supply IC according to a first embodiment of the present disclosure. FIG. 4 is a relationship diagram between a ramp voltage and a clock signal according to a first embodiment of the present disclosure. FIG. 5 is a timing chart when a switching frequency is stable at a reference frequency according to a first embodiment of the present disclosure. FIG. 6 is a diagram showing relationships between multiple times according to a first embodiment of the present disclosure. FIG. 7 is a timing chart of a first hypothetical operation. FIG. 8 is a timing chart of an example EX1_1 according to the first embodiment of the present disclosure, showing a state in which the switching frequency is switched. FIG. 9 is a diagram showing a coil current waveform in a reference switching operation and a coil current waveform in a frequency-dividing switching operation according to an example EX1_1 according to a first embodiment of the present disclosure. FIG. 10 is a timing chart of an example EX1_2 according to a first embodiment of the present disclosure, showing a state in which the switching frequency is switched. FIG. 11 is a configuration diagram of a switching power supply device showing the internal configuration of a power supply IC according to Example EX1_3 of the first embodiment of the present disclosure. FIG. 12 is a configuration diagram of a switching power supply device showing the internal configuration of a power supply IC according to a second embodiment of the present disclosure. FIG. 13 is a timing chart when the switching frequency is stable at the reference frequency according to the second embodiment of the present disclosure. FIG. 14 is a timing chart of a second hypothetical operation. FIG. 15 is a timing chart of an example EX2_1 according to the second embodiment of the present disclosure, showing a timing around when the switching frequency is switched. FIG. 16 is a diagram illustrating the internal configuration of a current information generation circuit according to Example EX2_1 according to the second embodiment of the present disclosure. FIG. 17 is a diagram illustrating the operation of the current information generation circuit of FIG. 16. FIG. 18 is a timing chart of an example EX2_2 according to the second embodiment of the present disclosure, showing a timing around when the switching frequency is switched. FIG. 19 is a diagram illustrating the internal configuration of a current information generation circuit according to Example EX2_3 according to the second embodiment of the present disclosure.

[0010] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings referred to, the same parts are given the same reference numerals, and duplicated explanations of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, by using symbols or signs that refer to information, signals, physical quantities, functional units, circuits, elements, or parts, the names of the information, signals, physical quantities, functional units, circuits, elements, or parts corresponding to the symbols or signs may be omitted or abbreviated. For example, in the case of "V" described later, C The contrast voltage referred to by " (see FIG. 3) is the contrast voltage V C It may also be written as voltage V C They may be abbreviated as "," but they all refer to the same thing.

[0011] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductive portion having a reference potential of 0 V (zero volts), or refers to the potential of 0 V itself. The reference conductive portion may be formed using a conductor such as metal. The potential of 0 V is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0012] A level refers to a level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, when a signal or voltage is at a high level, strictly speaking, the level of the signal or voltage is at a high level, and when a signal or voltage is at a low level, strictly speaking, the level of the signal or voltage is at a low level.

[0013] In any signal or voltage of interest, a transition from a low level to a high level is referred to as an up-edge, and the timing of the transition from a low level to a high level is referred to as up-edge timing. An up-edge may be read as a rising edge. Similarly, in any signal or voltage of interest, a transition from a high level to a low level is referred to as a down-edge, and the timing of the transition from a high level to a low level is referred to as down-edge timing. A down-edge may be read as a falling edge.

[0014] For any transistor configured as a FET (field-effect transistor), including a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Also, unless otherwise specified, the back gate of any MOSFET can be considered shorted to the source. Any switch can be configured with one or more FETs (field-effect transistors). When a switch is on, both ends of the switch are conductive, while when a switch is off, both ends of the switch are non-conductive.

[0015] Hereinafter, the on and off states of any transistor or switch may be simply expressed as on and off. For any transistor or switch, switching from the off state to the on state is expressed as turning on, and switching from the on state to the off state is expressed as turning off. Furthermore, for any transistor or switch, the period during which the transistor or switch is in the on state is referred to as the on period, and the period during which the transistor or switch is in the off state is referred to as the off period. For any signal that takes a high or low signal level, the period during which the signal level is high is referred to as the high-level period, and the period during which the signal level is low is referred to as the low-level period. The same applies to any voltage that takes a high or low voltage level.

[0016] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, or node, may be understood to refer to an electrical connection.

[0017] [First Embodiment] A first embodiment of the present disclosure will be described. Fig. 1 is an overall configuration diagram of a switching power supply device 1 according to the first embodiment of the present disclosure. The switching power supply device 1 of Fig. 1 includes a power supply IC2 which is a switching power supply circuit (a switching power supply semiconductor device), and a plurality of discrete components externally connected to the power supply IC2, and the plurality of discrete components include a capacitor C1 as an output capacitor, a capacitor C2 as a boot capacitor, resistors R1 and R2 as feedback resistors, and a coil L1. The switching power supply device 1 receives an externally supplied input voltage V IN More desired output voltage V OUT The output terminal OUT outputs an output voltage V OUT That is, the output terminal OUT has an output voltage V OUT The application terminal (output voltage V OUT The output voltage V OUT is supplied to a load LD connected to an output terminal OUT.

[0018] Input voltage V IN and output voltage V OUT is a positive DC voltage, and the output voltage V OUT is the input voltage V IN For example, the input voltage V IN is 12V, the resistance values ​​of resistors R1 and R2 can be adjusted to obtain a desired target voltage V TG (e.g. 5V) at output voltage V OUT can be stabilized.

[0019] FIG. 2 shows a perspective view of the power supply IC2. The power supply IC2 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and multiple external terminals exposed from the housing to the outside of the power supply IC2. The power supply IC2 is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the power supply IC2 and the type of housing for the power supply IC2 shown in FIG. 2 are merely examples and can be designed as desired. The output stage circuit MM, main control block 3, and rectifier element D1 shown in FIG. 1 are included in the semiconductor integrated circuit.

[0020] In FIG. 1, only the input terminal IN, the switch terminal SW, the feedback terminal FB, the output monitoring terminal OS, the boot terminal BOOT, and the ground terminal GND are shown as some of the multiple external terminals provided on the power supply IC 2 (the same applies to FIG. 3 described later, etc.), but other external terminals (for example, an enable terminal and a power good terminal) may also be provided on the power supply IC 2.

[0021] The external configuration of the power supply IC 2 will be described. IN is supplied to the input terminal IN. A coil L1 is connected in series between the switch terminal SW and the output terminal OUT. That is, one end of the coil L1 is connected to the switch terminal SW, and the other end of the coil L1 is connected to the output terminal OUT. Furthermore, the output terminal OUT is connected to ground via a capacitor C1. That is, one end of the capacitor C1 is connected to the output terminal OUT, and the other end of the capacitor C1 is connected to ground. Furthermore, the output terminal OUT is connected to one end of a resistor R1, and the other end of the resistor R1 is connected to ground via a resistor R2. The connection node between the resistors R1 and R2 is connected to a feedback terminal FB. Furthermore, an output monitor terminal OS is connected to the output terminal OUT. Therefore, the output voltage V OUT is applied. The ground terminal GND is connected to ground. The capacitor C2 is provided between the terminals BOOT and SW. That is, one end of the capacitor C2 is connected to the boot terminal BOOT, and the other end of the capacitor C2 is connected to the switch terminal SW. The current flowing through the coil L1 is referred to as the coil current IL.

[0022] The following describes the internal configuration of the power supply IC 2. The power supply IC 2 includes an output stage circuit MM, a main control block 3 for controlling the output stage circuit MM, and a rectifying element D1.

[0023] The output stage circuit MM includes transistors M1 and M2. Here, the transistors M1 and M2 are each an N-channel metal oxide semiconductor field effect transistor (MOSFET). The transistors M1 and M2 are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (in other words, ground). When they are switched, the input voltage V IN is switched and a rectangular wave switching voltage V SW The transistor M1 is a high-side transistor provided on the high side, and the transistor M2 is a low-side transistor provided on the low side. Specifically, the drain of the transistor M1 is connected to the input voltage V IN The source of transistor M1 and the drain of transistor M2 are connected in common to a switch terminal SW. The source of transistor M2 is connected to a ground terminal GND. Note that a resistor (sense resistor) for detecting current may be inserted between the source of transistor M2 and ground.

[0024] The transistor M1 functions as an output transistor, and the transistor M2 functions as a synchronous rectifier transistor. The coil L1 and the capacitor C1 generate a square-wave switching voltage V SW is rectified and smoothed to produce an output voltage V OUT The resistors R1 and R2 form a rectifying and smoothing circuit that generates an output voltage V OUT A voltage divider circuit is formed to divide the output voltage V OUT The feedback voltage V FB The connection node between the resistors R1 and R2 is connected to the feedback terminal FB, so that the feedback voltage V FB is input to the feedback terminal FB.

[0025] Gate signals G1 and G2 are supplied to the gates of transistors M1 and M2, respectively. Transistors M1 and M2 are turned on and off in response to the gate signals G1 and G2. When the gate signal G1 is at a high level, transistor M1 is in an on state, and when the gate signal G1 is at a low level, transistor M1 is in an off state. Similarly, when the gate signal G2 is at a high level, transistor M2 is in an on state, and when the gate signal G2 is at a low level, transistor M2 is in an off state. Basically, transistors M1 and M2 are alternately turned on and off, but both transistors M1 and M2 may also be turned off. That is, the state of the output stage circuit MM is one of an output high state, an output low state, and a Hi-Z state. In the output high state, transistors M1 and M2 are in an on state and an off state, respectively. In the output low state, transistors M1 and M2 are in an off state and an on state, respectively. In the Hi-Z state, both the transistors M1 and M2 are in the off state, and both the transistors M1 and M2 are never in the on state.

[0026] The main control block 3 is connected to the gates of the transistors M1 and M2, the switch terminal SW, the feedback terminal FB, and the output monitoring terminal OS. FB , the on / off states of the transistors M1 and M2 are controlled by controlling the levels of the gate signals G1 and G2, respectively, and a feedback voltage V is applied to the output terminal OUT. FB Output voltage V according to OUT As shown in FIG. 1, the main control block 3 generates an output voltage V OUT The main control block 3 may be provided with an output voltage V OUT In addition to being able to perform overvoltage protection etc. based on the output voltage V OUT It is also possible to generate pseudo current information (described in detail later) by referring to the above.

[0027] The power supply IC2 has an input voltage V IN Based on the internal power supply voltage V REG An internal power supply circuit (not shown) is provided to generate the internal power supply voltage V REGhas a predetermined positive DC voltage value. In the example of FIG. 1, the rectifying element D1 is a diode. In this case, the anode of the diode serving as the rectifying element D1 is connected to the internal power supply voltage V REG The cathode is connected to the application terminal of the transistor M2, and the cathode is connected to the boot terminal BOOT. The rectifying element D1 may be a switching element that is turned on during the on period of the transistor M2. The rectifying element D1 and the capacitor C2 form a bootstrap circuit. The voltage applied to the boot terminal BOOT is referred to as the boot voltage V BOOT The main control block 3 is connected to the internal power supply voltage V REG or boot voltage V BOOT It can be driven based on

[0028] When the output stage circuit MM is in the output low state, the internal power supply voltage V REG The capacitor C2 is charged through the rectifying element D1 based on the boot voltage V BOOT is the switching voltage V SW After that, when the output stage circuit MM is set to the output high state, the boot voltage V BOOT is the switching voltage V SW is maintained at a higher level than

[0029] The gate signal G1 is a signal based on the potential of the switch terminal SW. Specifically, the low-level gate signal G1 has the potential of the switch terminal SW, and the high-level gate signal G1 has a voltage V lower than the potential of the switch terminal SW. BOOT and V SW The main control block 3 is higher by the difference between the boot voltage V BOOT On the other hand, the gate signal G2 is a signal based on the ground potential. Specifically, the low-level gate signal G2 has the ground potential, and the high-level gate signal G2 has a predetermined voltage (for example, an internal power supply voltage V REG ) is more expensive.

[0030] 3 shows the configuration of a switching power supply device 1 having a power supply IC 2A. The power supply IC 2A is an example of the power supply IC 2. Unless contradictory, all of the matters described above regarding the power supply IC 2 also apply to the power supply IC 2A.

[0031] The main control block 3 in the power supply IC 2A includes an error amplifier 11, a phase compensation circuit 12, a differential amplifier 13, a phase compensation circuit 14, a clock generation circuit 15, a ramp voltage generation circuit 16, a comparator 17, a logic circuit 18, a driver 19, and a current information generation circuit 30. The power supply IC 2A performs switching operations using pulse width modulation. The function and operation of each component will be described below.

[0032] The error amplifier 11 is a current output type transconductance amplifier. The error amplifier 11 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The output terminal of the error amplifier 11 is connected to the wiring WR1. The inverting input terminal of the error amplifier 11 is connected to the feedback terminal FB and outputs a feedback voltage V FB The non-inverting input terminal of the error amplifier 11 is supplied with a predetermined reference voltage V REF The reference voltage V REF is a DC voltage having a predetermined positive voltage value, and is generated by a reference voltage generating circuit (not shown) in the power supply IC 2A.

[0033] The error amplifier 11 outputs a feedback voltage V FB and the reference voltage V REF The feedback voltage V FB and the reference voltage V REF Error voltage V according to the difference between ERR The charge generated by the current signal I1 is input to and output from the wiring WR1. Specifically, the error amplifier 11 generates a feedback voltage V FB is the reference voltage V REF When the voltage of the wiring WR1 is lower than the reference voltage V, the error amplifier 11 outputs a current signal I1 to the wiring WR1 so that the potential of the wiring WR1 increases. FB is the reference voltage V REFWhen the feedback voltage V is higher than the reference voltage V, a current is drawn from the wiring WR1 to the error amplifier 11 by the current signal I1 so that the potential of the wiring WR1 decreases. FB and the reference voltage V REF As the absolute value of the difference between increases, the magnitude of the current due to current signal I1 also increases.

[0034] When the power supply IC 2A is started, the reference voltage V REF A soft start voltage that gradually rises toward a voltage exceeding the reference voltage V may be generated in the power supply IC2A. In this case, the error amplifier 11 REF The lower voltage of the soft start voltage and the feedback voltage V FB In this embodiment, the soft start voltage is compared with the reference voltage V REF In the following, the existence of the soft start voltage is ignored.

[0035] The phase compensation circuit 12 is provided between the wiring WR1 and the ground, and receives the input of the current signal I1 to generate an error voltage V ERR The phase compensation circuit 12 includes a series circuit of a resistor 12a and a capacitor 12b. Specifically, one end of the resistor 12a is connected to the wiring WR1, and the other end of the resistor 12a is connected to one end of the capacitor 12b. The other end of the capacitor 12b is connected to the ground. By appropriately setting the resistance value of the resistor 12a and the capacitance value of the capacitor 12b, the error voltage V ERR The phase of the output feedback loop can be compensated to prevent oscillation.

[0036] The differential amplifier 13 is also a current output type transconductance amplifier, similar to the error amplifier 11. The differential amplifier 13 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The output terminal of the differential amplifier 13 is connected to the wiring WR2. The non-inverting input terminal of the differential amplifier 13 is connected to the wiring WR1 and outputs the error voltage V ERR The inverting input terminal of the differential amplifier 13 is supplied with a voltage V IL As will be described in detail later, the voltage V IL is coil current information representing the coil current IL.

[0037] The differential amplifier 13 outputs the error voltage V ERR and voltage V IL The error voltage V ERR and voltage V IL Comparison voltage V according to the difference between C The electric charge due to the current signal I2 is input to and output from the wire WR2. Specifically, the differential amplifier 13 generates an error voltage V ERR is the voltage V IL When the error voltage V is higher than the reference voltage V, a current signal I2 is output from the differential amplifier 13 to the wiring WR2 so that the potential of the wiring WR2 increases. ERR is the voltage V IL When the error voltage V is lower than the reference voltage V, a current is drawn from the wire WR2 to the differential amplifier 13 by the current signal I2 so that the potential of the wire WR2 drops. ERR and voltage V IL As the absolute value of the difference between increases, the magnitude of the current due to current signal I2 also increases.

[0038] The phase compensation circuit 14 is provided between the wiring WR2 and the ground, and receives the input of the current signal I2 to generate a comparison voltage V C The phase compensation circuit 14 includes a series circuit of a resistor 14a and a capacitor 14b. Specifically, one end of the resistor 14a is connected to the wiring WR2, and the other end of the resistor 14a is connected to one end of the capacitor 14b. The other end of the capacitor 14b is connected to the ground. By appropriately setting the resistance value of the resistor 14a and the capacitance value of the capacitor 14b, the comparison voltage V C The phase of the output feedback loop can be compensated to prevent oscillation.

[0039] The clock generation circuit 15 generates and outputs a clock signal CLK. The clock signal CLK has a predetermined reference frequency f REF The clock signal CLK is output from the clock generating circuit 15 to the ramp voltage generating circuit 16 and the logic circuit 18.

[0040] The ramp voltage generating circuit 16 generates a ramp voltage V whose voltage value (in other words, signal level) changes periodically. RAMP Generates a lamp voltage V RAMP has a voltage waveform, for example, a triangular wave or a sawtooth wave. RAMP depends on the clock signal CLK.

[0041] The lamp voltage V RAMP and the clock signal CLK. REF The time corresponding to the reciprocal of the reference time t REF The reference time t REF A rising edge occurs in the clock signal CLK every time t t has elapsed. REF After a predetermined short time Δt has elapsed, a falling edge occurs in the clock signal CLK, and then, after a predetermined short time Δt has elapsed, a new rising edge occurs in the clock signal CLK.

[0042] The ramp voltage generating circuit 16 generates a ramp voltage V RAMP The value of this is set to a predetermined lower limit voltage value V RAMP_MIN and the ramp voltage V RAMP Therefore, the ramp voltage generating circuit 16 generates the ramp voltage V RAMP Lower limit voltage value V RAMP_MIN The lamp voltage V RAMP The ramp voltage generating circuit 16 continues to increase the ramp voltage V RAMP The lower limit voltage value V RAMP_MIN Hereafter, the lower limit voltage value V RAMP_MIN is sometimes referred to as the initial level.

[0043] Ramp voltage V during the high level period of the clock signal CLK RAMP The slope of the rise of the input voltage V IN is set to a larger value (however, the input voltage V IN(It may be set to a constant value independent of the reference time t REF In the following, unless otherwise necessary, the infinitesimal time Δt is the same as the reference time t REF Therefore, it is considered to be sufficiently small and is ignored (i.e., it is treated as if the minute time Δt is zero).

[0044] Referring again to FIG. 3, the non-inverting input terminal of the comparator 17 is connected to the wiring WR2 and outputs the comparison voltage V C The inverting input terminal of the comparator 17 receives the ramp voltage V from the ramp voltage generating circuit 16. RAMP The comparator 17 outputs a comparison voltage V C is the lamp voltage V RAMP and a signal S indicating the comparison result. PWM The signal S PWM is "V C >V RAMP " is at a high level during the period when "V C <V RAMP " is set to a low level. C =V RAMP During the period when the signal S PWM is at high level or low level. C >V RAMP " is the contrast voltage V C is the lamp voltage V RAMP It means that it is higher than C <V RAMP " is the contrast voltage V C is the lamp voltage V RAMP The same applies to other equations that include physical quantities such as voltage.

[0045] The signal S from the comparator 17 is sent to the logic circuit 18. PWM and a clock signal CLK from the clock generation circuit 15. The logic circuit 18 receives the signals CLK and S PWM The driver 19 controls the gate signals G1 and G2 by controlling the driver 19 based on the signals CLK and S. PWMThe gate signals G1 and G2 based on the signals CLK and S are supplied to the transistors M1 and M2, thereby causing the output stage circuit MM to perform a switching operation. PWM The transistors M1 and M2 are alternately turned on and off based on the feedback voltage V FB and the reference voltage V REF In order to generate a current signal I1 so that the output voltage V is equal to the OUT is the reference voltage V REF and a predetermined target voltage V according to the voltage division ratio of resistors R1 and R2. TG It is stabilized at

[0046] The logic circuit 18 controls and sets the output stage circuit MM to an output high state by causing the driver 19 to supply a high-level gate signal G1 and a low-level gate signal G2 to the gates of the transistors M1 and M2. The logic circuit 18 controls and sets the output stage circuit MM to an output low state by causing the driver 19 to supply a low-level gate signal G1 and a high-level gate signal G2 to the gates of the transistors M1 and M2.

[0047] Therefore, the logic circuit 18 switches the state of the output stage circuit MM from the output low state to the output high state by using the driver 19 to generate a rising edge in the gate signal G1 and a falling edge in the gate signal G2. However, at this time, in order to prevent through current, the output stage circuit MM may be switched from the output low state to the output high state via the Hi-Z state. In other words, when switching from the output low state to the output high state, a falling edge may be generated in the gate signal G2 and then a rising edge may be generated in the gate signal G1.

[0048] Similarly, the logic circuit 18 uses the driver 19 to generate a falling edge in the gate signal G1 and an rising edge in the gate signal G2, thereby switching the state of the output stage circuit MM from the output high state to the output low state. However, at this time, in order to prevent through current, the output stage circuit MM may be switched from the output high state to the output low state via the Hi-Z state. In other words, when switching from the output high state to the output low state, a falling edge may be generated in the gate signal G1 and then an rising edge may be generated in the gate signal G2.

[0049] In this way, the logic circuit 18 controls the on / off of the transistors M1 and M2 using the driver 19, but in the following, the description of the driver 19 may be omitted.

[0050] The coil current IL flowing from the switch terminal SW to the output terminal OUT has a positive polarity. In the following, it is assumed that the positive coil current IL flows during both the ON period of the transistor M1 and the ON period of the transistor M2 (i.e., operation in a so-called continuous mode is assumed).

[0051] The current information generating circuit 30 performs a current sensing operation to detect the current flowing through the transistor M2 during the on-period of the transistor M2, and generates a voltage V corresponding to the coil current information through the current sensing operation. IL During the ON period of the transistor M2, the current flowing through the transistor M2 passes through the coil L1. Therefore, the current sensing operation can be said to be an operation of detecting the coil current IL by detecting the current flowing through the transistor M2. The current information generating circuit 30 generates a higher voltage V as the coil current IL increases. IL The voltage V IL is fed back to the differential amplifier 13, the error voltage V ERR The increase in the coil current IL causes an increase in the error voltage V ERR The decrease in the current I L causes a decrease in the coil current I L .

[0052] 3 , the current information generating circuit 30 includes a sense resistor 31, an S / H circuit 32, an amplifier circuit 33, a pseudo current generating circuit 34, and an adder 35. The operation of the current information generating circuit 30 may be controlled by the logic circuit 18. The current information generating circuit 30 can detect the current flowing through the transistor M2 (and therefore the coil current IL) by detecting the voltage drop across the sense resistor 31.

[0053] The sense resistor 31 is connected in series to the transistor M2 and ground. Specifically, a first end of the sense resistor 31 is connected to the source of the transistor M2, and a second end of the sense resistor 31 is connected to the ground terminal GND. During the on-period of the transistor M2, a coil current IL flows through the sense resistor 31 and the transistor M2, and a voltage drop proportional to the coil current IL occurs across the sense resistor 31.

[0054] The S / H circuit 32 is a sampling / holding circuit for the voltage drop across the sense resistor 31. That is, the S / H circuit 32 is connected to the first and second ends of the sense resistor 31, and in a current sensing operation, samples and holds the voltage drop across the sense resistor 31 (i.e., the voltage generated across both terminals of the sense resistor 31) at a sampling timing set by the logic circuit 18. In a current sensing operation, the amplifier circuit 33 amplifies the voltage currently held in the S / H circuit 32 and outputs the amplified voltage. The output voltage of the amplifier circuit 33 is represented by the symbol "V ISNS The value of the coil current IL is detected by a current sensor consisting of a sense resistor 31, an S / H circuit 32, and an amplifier circuit 33. The voltage V ISNS corresponds to detected current information that indicates the detected value (detected current value) of the coil current IL. The detected value of the coil current IL is expressed as a voltage V ISNS It is equivalent to dividing by .

[0055] The pseudo current generating circuit 34 generates a voltage V IPS The voltage V IPS The adder 35 outputs the output voltage V ISNS The output voltage V of the pseudo current generating circuit 34 IPSand the sum of these voltages (V ISNS +V IPS ) to voltage V IL The voltage V IL is coil current information representing the coil current IL.

[0056] The current information generating circuit 30 operates in a stable manner in a period in which the current sensing operation can be stably performed. IPS = 0”, and the detected current information (V ISNS ) itself is the coil current information (V IL During the period when the current sensing operation cannot be performed, the current information generating circuit 30 generates the detected current information (V ISNS ) and pseudo current information (V IPS ) to estimate the coil current IL, and obtain the coil current information (V IL ) can be generated. IPS The meaning and method of producing will be explained in detail later.

[0057] The frequency at which the transistors M1 and M2 are alternately turned on and off is called the switching frequency, and is particularly represented by the symbol "f SW ". Switching frequency f SW is the switching frequency of transistor M1 (hence the frequency of gate signal G1) and is also the switching frequency of transistor M2 (hence the frequency of gate signal G2). IN is the output voltage V OUT When the switching frequency f SW is the reference frequency f REF and stabilizes.

[0058] The switching frequency f SW is the reference frequency f REF Timing chart when the switching frequency is stable (i.e., f SW is the reference frequency f REF 5 shows a timing chart when the signal S PWM , lamp voltage V RAMP , clock signal CLK, gate signal G1, gate signal G2, coil current IL, voltage V ISNSand voltage V IL The waveform of the voltage V is shown by a solid line. C 5, rising edges occur in the clock signal CLK at successive times T11, T12, T13, and T14. When the rising edge of the clock signal CLK occurs at time T11 while the output stage circuit MM is in the output low state, the logic circuit 18 causes a rising edge to occur in the gate signal G1 and a falling edge to occur in the gate signal G2, thereby switching the output stage circuit MM from the output low state to the output high state.

[0059] As described above, the rising edge of the clock signal CLK at time T11 triggers the ramp voltage V RAMP is the initial level (V RAMP_MIN ) and starts rising. Lamp voltage V RAMP When is at the initial level, "V C >V RAMP " is established, and therefore the signal S PWM is at a high level. RAMP During the rise of the lamp voltage V RAMP is the contrast voltage V C When it reaches the signal S PWM A down edge occurs at the lamp voltage V RAMP is the contrast voltage V C To reach this level is to C >V RAMP "From the established state of "V C <V RAMP ” is established. PWM Hereinafter, the reset signal is issued when the comparator 17 outputs a low-level signal S PWM is output, or the signal S PWM This means that a down edge occurs.

[0060] When the reset signal is issued, the logic circuit 18 generates a falling edge in the gate signal G1 and a rising edge in the gate signal G2, thereby switching the output stage circuit MM from the output high state to the output low state (except when the reset signal is invalid). After that, when a falling edge occurs in the clock signal CLK, the ramp voltage VRAMP is the initial level (V RAMP_MIN ), which returns the signal S PWM Then, at time T12, another rising edge occurs in the clock signal CLK. Thereafter, the same operation is repeated.

[0061] When the output stage circuit MM is in the high output state, the input voltage V is applied from the input terminal IN to the output terminal OUT through the transistor M1 and the coil L1. IN When the output stage circuit MM is in the low state, a current based on the stored energy in the coil L1 flows through the transistor M2 and the coil L1, and the coil current IL gradually decreases.

[0062] The logic circuit 18 sets the sampling timing during the ON period of the transistor M2 (i.e., the period during which the output stage circuit MM is in the output low state). The set sampling timing will be hereinafter referred to as "T SMPL ". One sampling timing T SMPL is set, and each sampling timing T SMPL A current sensing operation is performed at

[0063] The S / H circuit 32 detects the voltage drop across the sense resistor 31 at the sampling timing T SMPL The sampling timing T is set between the times T11 and T12. SMPL Specifically, the symbol "T SMPL1 ” and the sampling timing T set between the times T12 and T13. SMPL Specifically, the symbol "T SMPL2 ” and the sampling timing T set between the times T13 and T14. SMPL Specifically, the symbol "T SMPL3 " for reference.

[0064] Sampling timing T SMPL1 , T SMPL2 , T SMPL3 The voltage sampled at the amplifier circuit 33 is amplified by the amplifier circuit 33 to obtain a voltage VISNS are respectively represented by the symbol V ISNS1 , V ISNS2 , V ISNS3 The output voltage V of the amplifier circuit 33 is ISNS is the sampling timing T SMPL1 From the sampling timing T SMPL2 Voltage V ISNS1 Similarly, the output voltage V of the amplifier circuit 33 is maintained at ISNS is the sampling timing T SMPL2 From the sampling timing T SMPL3 Voltage V ISNS2 The same applies to the following. Switching frequency f SW is the reference frequency f REF When the voltage V is stable, no pseudo current information is generated. IPS is maintained at zero. That is, the switching frequency f SW is the reference frequency f REF In a stable state, "V IL =V ISNS "

[0065] Any timing during the ON period of the transistor M2 is the sampling timing T SMPL For example, the logic circuit 18 may set the timing at which a predetermined time has elapsed since the transistor M2 was turned on as the sampling timing T SMPL Alternatively, for example, the logic circuit 18 may set the timing a predetermined time before the turn-off timing of the transistor M2 as the sampling timing T SMPL Here, the center timing of the ON period of the transistor M2 is the sampling timing T SMPL shall be set to

[0066] A certain time is required for the current sensing operation, and the minimum time required for the current sensing operation is the minimum sensing time t MIN_SNS The reference time t REF and the minimum sense time t MIN_SNS The relationship between the reference time t REF The minimum sense time t MIN_SNSis shorter. The time difference (t REF -t MIN_SNS ) is "f SW = f REF The maximum on-time t MAX_ON The maximum on-time t MAX_ON represents the maximum length of the ON period of the transistor M1 in one cycle of the switching operation. For example, the reference frequency f REF is 2 MHz (megahertz) and the minimum sense time t MIN_SNS is 200 nanoseconds, then "f SW = f REF The maximum on-time t MAX_ON is 300 nanoseconds, and "f SW = f REF The maximum duty when "is" is 60%. The duty indicates the proportion of the on time of the transistor M1 that occupies one cycle of the switching operation, and the maximum value that the duty can take is the maximum duty.

[0067] The period between two adjacent rising edge timings of the clock signal CLK is called a unit period. The length of the unit period is the reference time t REF Each unit period is a composite period of a first period and a second period. In each unit period, the first period is followed by the second period. The length of the second period is the minimum sense time t MIN_SNS The length of the first period is "f SW = f REF The maximum on-time t MAX_ON matches.

[0068] The power supply IC2A basically outputs an output voltage V OUT Compared to the input voltage V IN In this application, the on-time of the transistor M1 is considerably short while the on-time of the transistor M2 is sufficiently long in each switching cycle, so that the time required to detect the current flowing through the transistor M2 can be easily and stably secured.

[0069] However, in the switching power supply device 1, IN >V OUT" is the voltage V IN and V OUT The difference between the two becomes smaller, or IN <V OUT For example, in an in-vehicle application, the output voltage of a battery (not shown) mounted on a vehicle such as an automobile may be greater than the input voltage V IN In this case, when starting or restarting the engine using the starter, the battery output voltage may temporarily drop significantly. IN >V OUT " is the voltage V IN and V OUT The difference between the two becomes smaller, or IN <V OUT " Sometimes it becomes like this.

[0070] Input voltage V IN During the period when the duty is decreasing, it is better to increase the duty as high as possible, OUT For example, it is advantageous to maintain the target voltage V TG When the input voltage V is 5V, the input voltage V has a value of 12V. IN When the voltage drops to 7V, if the maximum duty is 60%, the output voltage V OUT can only be raised to about 4.2V, but if the maximum duty is 80%, the output voltage V OUT It is possible to maintain the voltage at around 5V.

[0071] Minimum sense time t MIN_SNS Since is unchanged, to increase the maximum duty, the switching frequency f SW For example, lowering the reference frequency f REF is 2 MHz (megahertz) and the minimum sense time t MIN_SNS When is 200 nanoseconds, the switching frequency f SWBy lowering the switching frequency f from 2 MHz to 1 MHz, the maximum duty can be increased from 60% (= (500 ns - 200 ns) / 500 ns) to 80% (= (1000 ns - 200 ns) / 1000 ns). SW If is further reduced, the maximum duty will further increase.

[0072] The logic circuit 18 controls the switching frequency f SW is the reference frequency f REF or the reference frequency f REF It can be set to (1 / n) times of "f", where n is an arbitrary integer of 2 or more. SW = f REF " is particularly referred to as a reference switching operation. SW = f REF / n" is particularly referred to as a frequency division switching operation.

[0073] The time from the rising edge of the clock signal CLK to the issuance of the reset signal is determined by the input voltage V IN The increase in the time means the need for an increase in duty. SW = f REF ", after turning on the transistor M1, "f SW = f REF The maximum on-time t MAX_ON If the reset signal is not issued before the elapse of the time, the logic circuit 18 transitions the switching operation to be performed from the reference switching operation to the frequency division switching operation, thereby increasing the maximum duty.

[0074] However, when a frequency division switching operation is performed, a high duty can be obtained, but the current sensing operation cannot be performed for a relatively long time.

[0075] 7 shows a timing chart relating to the first hypothetical operation. Unlike the power supply IC 2A according to this embodiment, in the first hypothetical operation, the voltage V IPS In FIG. 7, waveforms 911 to 920 are respectively the input voltage VIN , output voltage V OUT , contrast voltage V C , lamp voltage V RAMP , clock signal CLK, gate signal G1, gate signal G2, coil current I L , voltage V ISNS and voltage V IL The waveform 921 is the output voltage V OUT The waveform 918 of the coil current IL corresponds to an enlarged waveform (the waveform 912 enlarged in the voltage direction). Each white circle shown on the waveform 918 of the coil current IL indicates the sampling timing T SMPL Represents the voltage V ISNS Each white circle shown on the waveform 919 represents each sampling timing T SMPL The detected current information (V ISNS In the first virtual operation, "V IPS =0”, so “V IL =V ISNS "

[0076] In the example of FIG. 7, the reference switching operation is performed until time T21. However, before time T21, the input voltage V IN and output voltage V OUT In other words, in each switching period before time T21, the on time of the transistor M2 is equal to the minimum sense time t MIN_SNS (However, the minimum sense time t MIN_SNS Now, at time T21, the input voltage V IN At time T21, a rising edge occurs in the clock signal CLK. At time T23, the reference time t REF Therefore, the next rising edge of the clock signal CLK occurs at time T23. Time T22 is the time from time T23 to the minimum sense time t MIN_SNS represents the previous time.

[0077] Input voltage V INAs the voltage drops, the reset signal is not issued before time T22 in the switching cycle starting from time T21. Therefore, the logic circuit 18 associated with the first hypothetical operation switches the switching operation to be executed from the reference switching operation to the frequency-dividing switching operation, and keeps the output stage circuit MM in the high output state until the reset signal is issued after time T23.

[0078] 7, at time T24 after time T23, the state of the output stage circuit MM is switched from the output high state to the output low state in response to the issuance of a reset signal, and current sensing operation is performed while the transistor M2 is on. Time T25 is the time when the next rising edge of the clock signal CLK occurs after time T23.

[0079] In the first hypothetical operation in FIG. 7, the current sensing operation is not performed between times T21 and T24. Therefore, the detected current information (V ISNS ) is stored in the coil current information (V IL ) is continuously used as the coil current information (V IL Therefore, the feedback control is performed without reflecting the comparison voltage V C is constant, and as a result, the duty becomes excessively large in the switching operation starting from time T21. The excessive increase in duty causes the coil current IL to increase more than necessary, and the output voltage V OUT After that, an undesirable fluctuation occurs in the coil current IL for a while, causing an overshoot in the output voltage V OUT is unstable.

[0080] Examples EX1_1 to EX1_4 will be described below as a plurality of examples related to the switching power supply device 1 of the first embodiment. Any two or more of Examples EX1_1 to EX1_4 can be combined with each other.

[0081] <<Embodiment EX1_1>> An embodiment EX1_1 will be described. FIG. 8 shows a timing chart relating to embodiment EX1_1. As time passes, times T30 to T36, T41 to T46, T51 to T56, and T61 occur in this order. In FIG. 8, waveforms 611 to 621 respectively represent the input voltage V IN , output voltage V OUT , contrast voltage V C , lamp voltage V RAMP , clock signal CLK, gate signal G1, gate signal G2, coil current I L , voltage V ISNS , voltage V IPS and voltage V IL The waveform 622 is the output voltage V OUT 8 corresponds to the waveform 921 shown in FIG. 7 (the output voltage V OUT Each white circle shown on the waveform 618 of the coil current IL corresponds to the sampling timing T SMPL and each sampling timing T SMPL The current flowing through transistor M2 is sampled and detected at voltage V ISNS Each white circle shown on the waveform 619 represents each sampling timing T SMPL The detected current information (V ISNS ) represents

[0082] In the example of FIG. 8, the reference switching operation is performed up to time T31. SW = f REF " is "f SW = f REF ” when the pseudo current generating circuit 34 generates a voltage V IPS is kept at zero, and therefore "V IL =V ISNS In each switching period before time T31, the current information generating circuit 30 performs a current sensing operation.

[0083] In the example of FIG. 8, the switching operation to be performed is switched from the reference switching operation to the frequency division switching operation of "n=2" at time T31. During a part of the period in which the frequency division switching operation is performed, the pseudo current generating circuit 34 generates a voltage V IPS Generates and outputs a voltage V IPS Each open triangle shown on the waveform 620 represents a voltage V greater than zero. IPS Represents the voltage V IL Each white triangle shown on the waveform 621 represents the voltage I SNS and a voltage greater than zero V IPS Each open triangle on the waveform 618 of the coil current IL represents the sum of the voltage V IL represents the value (estimated value) of the coil current IL indicated by

[0084] Before time T31, the input voltage V IN and output voltage V OUT In other words, in each switching period before time T31, the ON time of the transistor M2 is equal to the minimum sense time t MIN_SNS (However, the minimum sense time t MIN_SNS The time T30 is the sampling timing T of the current sensing operation performed immediately before the time T31. SMPL is.

[0085] Now, the input voltage V IN At time T31, a rising edge occurs in the clock signal CLK, and the state of the output stage circuit MM changes from the output low state to the output high state. Time T34 is the time from time T31 to the reference time t REF Therefore, the next rising edge of the clock signal CLK occurs at time T34. Time T32 is the minimum sense time t MIN_SNS represents the previous time.

[0086] Input voltage V INAs the voltage V decreases, in the switching cycle starting from time T31, a reset signal is not issued before time T32 (i.e., a reset signal is not issued during the previous period: see FIG. 6). On the condition that a reset signal is not issued before time T32, the logic circuit 18 switches the switching operation to be performed from the reference switching operation to the frequency-dividing switching operation. When this switching is performed, the logic circuit 18 invalidates the reset signal issued between times T32 and T34, and the voltage V between times T32 and T34 C and V RAMP Regardless of the high / low relationship between the two, the output stage circuit MM is kept in the output high state between times T32 and T34.

[0087] At time T34, a rising edge occurs in the clock signal CLK, but even at this time, the logic circuit 18 keeps the output stage circuit MM in the high output state. REF In the example of FIG. 8, after time T34, at time T35, the lamp voltage V RAMP is the contrast voltage V C The reset signal is issued when the time T35 is reached. The time T35 is before the time T41, and the time difference between the time T35 and the time T41 is equal to the minimum sense time t MIN_SNS Therefore, at time T35, the logic circuit 18 switches the output stage circuit MM from the high output state to the low output state based on the issued reset signal. The logic circuit 18 sets time T36, which is the time between times T35 and T41, as the sampling timing T SMPL In accordance with the setting result, the current information generating circuit 30 performs a current sensing operation at time T36.

[0088] At time T41, a rising edge occurs in the clock signal CLK, and the state of the output stage circuit MM switches from the output low state to the output high state. REF Therefore, the next rising edge of the clock signal CLK occurs at time T44. Time T42 is the time from time T44 to the minimum sense time t MIN_SNS represents the previous time.

[0089] The input voltage V generated at time T31 IN The decrease in voltage V is maintained after time T41. As a result, in the switching cycle starting from time T41, a reset signal is not issued before time T42 (i.e., a reset signal is not issued during the previous period: see FIG. 6). On the condition that a reset signal is not issued before time T42, the logic circuit 18 maintains the frequency division switching operation as the switching operation to be performed. When the frequency division switching operation is maintained, the logic circuit 18 invalidates the reset signal issued between times T42 and T44, and the voltage V between times T42 and T44 C and V RAMP Regardless of the high / low relationship between the times T42 and T44, the output stage circuit MM is kept in the output high state.

[0090] At time T44, a rising edge occurs in the clock signal CLK, but even at this time, the logic circuit 18 keeps the output stage circuit MM in the high output state. REF In the example of FIG. 8, after time T44, at time T45, the lamp voltage V RAMP is the contrast voltage V C The reset signal is issued when the time T45 is reached. The time T45 is before the time T51, and the time difference between the time T45 and the time T51 is equal to the minimum sense time t MIN_SNS Therefore, at time T45, the logic circuit 18 switches the output stage circuit MM from the high output state to the low output state based on the issued reset signal. The logic circuit 18 sets time T46, which is between times T45 and T51, as the sampling timing T SMPL In accordance with the setting result, the current information generating circuit 30 performs a current sensing operation at time T46.

[0091] At time T51, a rising edge occurs in the clock signal CLK, and the state of the output stage circuit MM switches from the output low state to the output high state. REF Therefore, the next rising edge of the clock signal CLK occurs at time T54. Time T52 is the time from time T54 to the minimum sense time t MIN_SNS represents the previous time.

[0092] The input voltage V generated at time T31 IN The decrease in voltage V is maintained after time T51. As a result, in the switching cycle starting from time T51, a reset signal is not issued before time T52 (i.e., a reset signal is not issued during the previous period: see FIG. 6). On the condition that a reset signal is not issued before time T52, the logic circuit 18 maintains the frequency division switching operation as the switching operation to be performed. When the frequency division switching operation is maintained, the logic circuit 18 invalidates the reset signal issued between times T52 and T54, and the voltage V between times T52 and T54 C and V RAMP Regardless of the high / low relationship between the times T52 and T54, the output stage circuit MM is kept in the output high state.

[0093] At time T54, a rising edge occurs in the clock signal CLK, but even at this time, the logic circuit 18 keeps the output stage circuit MM in the high output state. REF In the example of FIG. 8, after time T54, at time T55, the lamp voltage V RAMP is the contrast voltage V C The reset signal is issued when the time T55 is reached. The time T55 is before the time T61, and the time difference between the time T55 and the time T61 is the minimum sense time t MIN_SNS Therefore, at time T55, the logic circuit 18 switches the output stage circuit MM from the high output state to the low output state based on the issued reset signal. The logic circuit 18 sets time T56, which is a time between times T55 and T61, as the sampling timing T SMPL In accordance with the setting result, the current information generating circuit 30 performs a current sensing operation at time T56.

[0094] Input voltage V IN As long as the decrease in the frequency continues, the same frequency division switching operation of "n=2" continues thereafter.

[0095] Detected current information (i.e., voltage V ISNS) is updated every time the current sensing operation is performed. That is, the detected current information (i.e., the voltage V ISNS ) is continuously output from the amplifier circuit 33 between times T30 and T36. After that, the detected current information (i.e., the voltage V ISNS ) is continuously output from the amplifier circuit 33 between times T36 and T46. After that, the detected current information (i.e., the voltage V ISNS ) is continuously output from the amplifier circuit 33 between times T46 and T56.

[0096] Voltage V representing pseudo current information IPS is zero before time T33, and therefore, "V IL =V ISNS ". The voltage V IPS is a positive voltage value V between times T33 and T36 A1 The voltage V IPS is a positive voltage value V between times T43 and T46 and between times T53 and T56 A2 The voltage value V A1 is the voltage value V A2 Greater than.

[0097] Time T33 falls within the latter period of the unit period starting from time T31 (see FIG. 6). Time T43 falls within the latter period of the unit period starting from time T41. Time T53 falls within the latter period of the unit period starting from time T51.

[0098] In each unit period, the logic circuit 18 monitors whether a reset signal has been issued during the previous period, and provides the monitoring result to the pseudo current generating circuit 34. The pseudo current generating circuit 34 generates a voltage V IPS Determine the value of the voltage V IPS In principle, if a reset signal is not issued during the first half of a specific unit period, the pseudo current generating circuit 34 generates a voltage V that is greater than zero from the timing during the second half of the specific unit period until the next current sensing operation is performed. IPSWhen the current sense operation is performed, the voltage V IPS is returned to zero. A specific unit period refers to a unit period in which transistor M1 is switched from off to on at the start of the unit period. Therefore, a unit period starting at time T31, T41, or T51 corresponds to a specific unit period, but a unit period starting at time T34, T44, or T54 does not correspond to a specific unit period.

[0099] In the example of FIG. 8, a reset signal is not issued during the first half of the unit period starting from time T31. Therefore, the voltage V IPS Voltage value V A1 At time T36, the voltage V IPS is returned to zero, and the voltage V IPS Similarly, a reset signal is not issued during the first half of the unit period starting from time T41. Therefore, the voltage V IPS Voltage value V A2 At time T46, the voltage V IPS is returned to zero, and the voltage V IPS Similarly, a reset signal is not issued during the first half of the unit period starting from time T51. Therefore, the voltage V IPS Voltage value V A2 At time T56, the voltage V IPS is reset to zero.

[0100] "V IPS =0" to "V IPS The timing of the change to >0" can be any timing within the corresponding latter period, but may be, for example, the center timing of the corresponding latter period. ISNS and voltage V IPS The sum of these is voltage VIL This becomes:

[0101] Positive voltage V IPS corresponds to the increase in the coil current IL that occurs during the period when the current sensing operation is not performed, converted into voltage, and an estimate of the increase in the coil current IL is superimposed on the detected coil current IL (detected current information) as a pseudo current. A method for setting the pseudo current will now be described.

[0102] The gradient ΔIL of the coil current IL when the output stage circuit MM is in the high output state is expressed by the following formula (1). L1 in formula (1) represents the inductance (inductance value) of the coil L1 (the same applies to other formulas described later). If the gradient ΔIL of the coil current IL is known, the increase in the coil current IL described above can be determined, and the pseudo current to be superimposed can be found. ΔIL=(V IN -V OUT ) / L1...(1)

[0103] In the switching power supply device 1, the inductance (inductance value) of the coil L1 is set to a predetermined value, and in the power supply IC 2A, the inductance (inductance value) of the coil L1 is known. In addition, the power supply IC 2A detects the voltage of the input terminal IN to obtain the input voltage V IN In addition, the power supply IC 2A can recognize the output voltage V by detecting the voltage at the output monitor terminal OS. OUT Alternatively, the output voltage V OUT Target voltage V TG ) may be fixed to a constant value. In this case, the constant value is recognized in advance by the power supply IC 2A. In this case, the output monitoring terminal OS may be omitted. In any case, the power supply IC 2A (for example, the current information generating circuit 30) IN and output voltage V OUT and the inductance of the coil L1, the slope ΔIL can be calculated according to the formula (1).

[0104] The pseudo current to be superimposed is derived by multiplying the gradient ΔIL by the necessary time information. A1 and V A2is derived and determined according to the following equations (2) and (3): A1 =ΔIL·t REF ・k A1 = ((V IN -V OUT ) / L1) t REF ・k A1 ... (2) V A2 =ΔIL·t REF ・k A2 = ((V IN -V OUT ) / L1) t REF ・k A2 ...(3)

[0105] "ΔIL·t REF " is the output stage circuit MM at a reference time t REF The conversion coefficient k represents the increase in the coil current IL that occurs when the output is maintained in a high state for a certain period of time. A1 and k A2 is a coefficient for converting the amount of current into the amount of voltage. A1 and k A2 is set. Here, "k A1 >k A2 For example, the conversion coefficient k A2 is multiplied by a predetermined value greater than 1 to obtain a conversion coefficient k A1 You can let him hold it.

[0106] The coil current IL does not increase over the entire period between times T30 and T33 in Fig. 8. For this reason, the conversion coefficient k A1 Similarly, for example, a conversion coefficient k may be set in accordance with the time difference between times T36 and T41 and the time difference between times T41 and T43. A2 may be set to superimpose a pseudo current close to the ideal.

[0107] Superposition of pseudo current (actually a positive voltage V IPS The superposition of the current coil current IL is compared to the voltage V CAs shown in FIG. 8, this corresponds to reflecting the comparison voltage V C 7 and 8, an excessive increase in duty is suppressed in the frequency division switching operation. As a result, in the example EX1_1, when the switching operation is switched from the reference switching operation to the frequency division switching operation, the output voltage V OUT (See the waveform 622 according to the embodiment EX1_1 and the waveform 921 according to the reference operation), that is, the fluctuation of the output voltage V OUT can be well stabilized.

[0108] "V A1 >V A2 The reason why "f" is used will be explained with reference to FIG. 9. SW = f REF ” and the peak value of the coil current IL is I PK1 and bottom value I BTM1 Average value between I AVE1 is sampled and the average value I AVE1 After this, feedback control is performed based on "f SW = f REF / 2" and "f SW = f REF The ripple of the coil current IL is doubled compared to when "f SW = f REF / 2”, the peak value of the coil current IL is I PK2 and bottom value I BTM2 Average value between I AVE2 is sampled and the average value I AVE2 The right side of FIG. SW = f REF 1 shows the waveform of the coil current IL in a stable state after a sufficient time has passed since the change to "f / 2". SW = f REF " and "f SW = f REF / 2" and the switching frequency f SW If there are no differences in the operating conditions other than the average value I AVE1 and the average value I AVE2 are equal, so "I PK1 <IPK2 "And "I BTM1 >I BTM2 " holds true.

[0109] "f SW = f REF ” the average value of the coil current IL AVE1 Since feedback control was performed based on SW = f REF Even in / 2", the average value of the coil current IL is I AVE2 The output voltage V OUT It is important for stabilizing the SW = f REF " to "f SW = f REF Immediately after switching to / 2", the coil current IL reaches the bottom value I BTM2 Instead, the bottom value I BTM1 (corresponding to the value of the coil current IL at time T31 in FIG. 8 ), the coil current IL starts to rise, and becomes higher than the ideal value. At this time, if a relatively large pseudo current is superimposed (in reality, a relatively large voltage value V A1 voltage V IPS Voltage I SNS ), the contrast voltage V C A large drop occurs in the coil current IL, and the coil current IL quickly approaches a stable state.

[0110] In this way, the current information generating circuit 30 determines whether the current is equal to or greater than the predetermined time (for example, time (t REF -t MIN_SNS / 2)) has elapsed, the detected current information (V ISNS ) to the coil current information (V IL During the period in which the frequency division switching operation is performed, after the predetermined time has elapsed since the transistor M1 was turned on, the current information generating circuit 30 generates the detected current information (V ISNS ) and pseudo current information (V IPS ) and the coil current information (V IL ) is generated.

[0111] The current information generating circuit 30 SW = f REF " to "f SW = f REF / n”, the value of the pseudo current information immediately after the switching (V A1 ) is used as the value of the subsequent pseudo current information (V A2 ) should be set larger than "f SW = f REF In the frequency division switching operation by " / n", the value of the pseudo current information in the first period (V A1 ) is the value of the pseudo current information from the second period onwards (V A2 ) is set to be larger than the output voltage V OUT This will lead to rapid stabilization of the situation.

[0112] However, “V A1 =V A2 ". The output voltage V OUT For rapid stabilization of A1 >V A2 " is suitable, but "V A1 =V A2 " even if the output voltage V OUT However, it remains possible to stabilize the

[0113] The logic circuit 18 monitors the time from when the transistor M1 is turned on to when the reset signal is issued every time the transistor M1 is turned on. As can be understood from the above description, the logic circuit 18 monitors the time from when the transistor M1 is turned on to when the reset signal is issued, after the specified time t D If a reset signal is not issued before the specified time t has elapsed, the switching operation to be performed is switched from the reference switching operation to the frequency division switching operation. D is "f SW = f REF The maximum on-time t MAX_ON is.

[0114] After that, the transistor M1 is turned on and the predetermined time t DWhen a reset signal is issued before time T61 has elapsed, the condition for returning to the reference switching operation is met. When the condition for returning to the reference switching operation is met, the logic circuit 18 returns the switching operation to be performed to the reference switching operation. In the example of FIG. 8, after time T61, the input voltage V IN As a result of the input voltage V increasing, the switching operation to be performed can return to the reference switching operation. IN When the voltage Vcc is sufficiently increased, the transistor M1 is turned on at time T61, and then the voltage Vcc is increased by a predetermined time t D A reset signal is issued before the input voltage V IN If is sufficiently high, a reset signal is always issued during the previous period in each unit period, so that "f SW = f REF " is maintained.

[0115] <<Embodiment EX1_2>> An embodiment EX1_2 will be described. In embodiment EX1_1, the frequency division switching operation of “n=2” was described. IN Depending on the degree of decrease in the frequency, a frequency division switching operation of "n≧3" may also be performed.

[0116] For example, the following case CS2 is assumed based on the case shown in FIG. 8 (hereinafter referred to as case CS1). The differences between cases CS1 and CS2 are shown below with reference to FIG. 10. In case CS2, the input voltage V IN is significantly reduced. As a result, in case CS2, a reset signal is not issued in the first half of unit period 641 starting at time T31, and a reset signal is not issued in the first half of unit period 642 starting at time T34. In case CS2, a reset signal is then issued at time T41', which belongs to the first half of unit period 643 starting at time T41 (whether or not a reset signal is issued is not shown in FIG. 10). Unit periods 641 to 643 are three consecutive unit periods, and time T41' is a time after time T41 and before time T44.

[0117] In case CS2, the logic circuit 18 switches the output stage circuit MM from the output low state to the output high state at time T31, then maintains the output stage circuit MM in the output high state until time T41', at which point the output stage circuit MM returns to the output low state. Thereafter, at time T43' belonging to the unit period 643, a current sensing operation is performed, and further thereafter, at time T44, the output stage circuit MM switches to the output high state in response to the rising edge of the clock signal CLK.

[0118] In case CS2, the voltage V IPS is set to zero, and between times T33 and T36′, the voltage V IPS The value of this is the above-mentioned voltage value V A1 Between times T36' and T43', the voltage V IPS The value of is the voltage value V A3 where the voltage value V A3 is the voltage value V A1 Time T33 is a time that belongs to the latter period of the unit period 641, and may be, for example, the center timing (center time) of the latter period of the unit period 641. Similarly, time T36' is a time that belongs to the latter period of the unit period 642, and may be, for example, the center timing (center time) of the latter period of the unit period 642. Here, the difference between times T36' and T43' is the reference time t REF is assumed to match.

[0119] In case CS2, at time T31, the switching frequency f SW is the reference frequency f REF to frequency (f REF / 3), and the coil current IL continues to rise between times T31 and T41′. Therefore, the pseudo current superimposed between times T36′ and T43′ is set to a value larger than the pseudo current superimposed between times T33 and T36′ by a difference (V A3 -V A1 The current amount is increased by the amount of current corresponding to "ΔIL·t REF ". That is, the difference (V A3 -V A1 ) is the amount of current (ΔIL・t REF) converted into voltage.

[0120] In case CS2, if a reset signal is not issued in the first half of the first and second unit periods after time T44, and a reset signal is issued in the first half of the third unit period, the frequency division switching operation of "n=3" continues. Here, the first to third unit periods are three consecutive unit periods, and the first unit period is followed by the second unit period and then the third unit period. The conditions for returning to the standard switching operation are as shown in embodiment EX1_1.

[0121] It can be said that the logic circuit 18 operates as follows. After turning on the transistor M1, the logic circuit 18 monitors whether a reset signal is issued during the previous stage period. If a reset signal is issued during the previous stage period of a target unit period, which is an arbitrary unit period, the logic circuit 18 immediately switches the output stage circuit MM from an output high state to an output low state in response to the issuance of the reset signal, and performs a current sensing operation during the on-period of the target unit period. If a reset signal is not issued during the previous stage period of the target unit period, the logic circuit 18 detects the voltage V C and V RAMP The output stage circuit MM is maintained in the high output state throughout the entire unit period of interest regardless of the level of the input voltage V. The next unit period is set as a new unit period of interest, and the same operation as described above is performed. IN Depending on the degree of the decrease in the voltage, the ON period of the transistor M1 may be extended without limit (however, an upper limit may be set).

[0122] <<Embodiment EX1_3>> An embodiment EX1_3 will be described. Fig. 11 shows the configuration of a switching power supply device 1 having a power supply IC 2B. The power supply IC 2B is an example of the power supply IC 2. The current information generating circuit 30 in the power supply IC 2B does not have a sense resistor 31.

[0123] In the power supply IC 2B, the on-resistance of the transistor M2 is used instead of the sense resistor 31 to detect the current (i.e., the coil current IL) flowing through the transistor M2 during the on-period of the transistor M2. For this reason, the S / H circuit 32 in the power supply IC 2B is connected to the drain and source of the transistor M2, and in the current sensing operation, the voltage drop occurring between the drain and source of the transistor M2 is detected at the sampling timing T SMPL The sample is sampled and held at .

[0124] 3 except for the absence of the sense resistor 31 and the above-mentioned matters linked to the absence of the sense resistor 31, the power supply IC 2B is the same as the power supply IC 2A in Fig. 3, and the description of the embodiment EX1_1 also applies to the embodiment EX1_3. In this application, the "voltage drop across the sense resistor 31" and "the value of the sense resistor 31" in the embodiment EX1_1 can be read as the "voltage drop occurring between the drain and source of the transistor M2" and "the value of the on-resistance of the transistor M2" in the embodiment EX1_3.

[0125] <<Example EX1_4>> Example EX1_4 will be described.

[0126] A switching control circuit for performing a switching operation is included in the main control block 3. The switching control circuit can be considered to be formed by including the components referenced by the reference numerals 11 to 19 (see FIG. 3 or FIG. 11). The switching control circuit controls the output voltage V OUT and coil current information (V IL ) and performs switching operation based on the feedback voltage V FB is the output voltage V OUT The voltage information is an example of the voltage information corresponding to the output voltage V OUT The switching control circuit may be the comparison voltage V C The comparison voltage generating circuit can be considered to be formed including the components referenced by the reference numerals 11 to 14 (see FIG. 3 or FIG. 11).

[0127] The ramp voltage V between the rising edge timing and the falling edge timing of the clock signal CLK RAMPAlthough the example in which the change direction of "V" is an increasing direction has been given, the change direction may also be a decreasing direction. C <V RAMP "From the established state of "V C >V RAMP Each circuit in the power supply IC 2 (2A, 2B) is appropriately modified so that a reset signal is issued when the transition to the established state of " is made.

[0128] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0129] The channel types of the FETs (field effect transistors) shown in each embodiment are merely examples. The channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0130] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor other than an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0131] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0132] <<First Supplementary Note>> Supplementary notes will be provided for the present disclosure, the specific configuration example of which is shown in the first embodiment described above.

[0133] A switching power supply circuit according to one aspect of the present disclosure is IN ) to output voltage (V OUT ), the switching power supply circuit (2, 2A, 2B) used in the switching power supply device (1) for generating a switching voltage (V) comprises: an output stage circuit (MM) having a high-side transistor (M1) and a low-side transistor (M2) connected in series between an input terminal (IN) for receiving the input voltage and a ground terminal (GND); switching control circuits (11-19) configured to perform a switching operation of alternately turning on and off the high-side transistor and the low-side transistor; and a current information generating circuit (30) configured to perform a current sensing operation of detecting a current flowing through the low-side transistor during an on period of the low-side transistor, wherein a connection node between the high-side transistor and the low-side transistor is connected to a rectifying and smoothing circuit including a coil (L1) and an output capacitor (C1), and a switching voltage (V) generated at the connection node by the switching operation. SW ) is rectified and smoothed by the rectifying and smoothing circuit to generate the output voltage, and the switching control circuit generates voltage information (V FB ), and the coil current information (V IL ) and the switching operation is performed based on the switching control circuit, and the switching frequency in the switching operation is set to a first frequency (f REF ) or a second frequency (f REF / n), and the current information generating circuit, when the switching frequency is set to the second frequency, generates detected current information (V ISNS ) based on the input voltage and the output voltage, IP) to generate the current information of the coil (hereinafter referred to as configuration P1).

[0134] As a result, when the switching frequency is set to the relatively low second frequency, the interval between current sensing operations becomes longer, but by generating coil current information through the addition of pseudo current information, feedback control that is roughly in line with the actual coil current becomes possible, thereby stabilizing the output voltage.

[0135] In the switching power supply circuit according to the above-described configuration P1, the current information generating circuit may be configured to generate the pseudo current information based on the input voltage, the output voltage, and the inductance of the coil (hereinafter referred to as configuration P2).

[0136] This allows the generation of pseudo current information that accurately simulates fluctuations in the coil current during periods when current sensing is not performed, enabling control that is generally in line with the actual coil current, thereby stabilizing the output voltage.

[0137] In the switching power supply circuit according to the above configuration P2, the current information generating circuit calculates the input voltage, the output voltage, the inductance of the coil, and the time (t REF ) and the pseudo current information may be generated based on the above (hereinafter referred to as configuration P3).

[0138] This allows the generation of pseudo current information that accurately simulates fluctuations in the coil current during periods when current sensing is not performed, enabling control that is generally in line with the actual coil current, thereby stabilizing the output voltage.

[0139] With respect to a switching power supply circuit according to any one of the above configurations P1 to P3, the current information generation circuit may be configured (hereinafter referred to as configuration P4) to generate, as the coil current information, the detected current information from the most recent current sensing operation until a predetermined time has elapsed since the high-side transistor was turned on during the period in which the switching frequency is set to the second frequency, and to generate, as the coil current information, the sum of the detected current information from the most recent current sensing operation and the pseudo current information from the high-side transistor after the predetermined time has elapsed since the high-side transistor was turned on until the next current sensing operation is performed.

[0140] In the switching power supply circuit according to any one of the above configurations P1 to P4, when the switching frequency is switched from the first frequency to the second frequency, the current information generating circuit generates the value of the pseudo current information (V A1 ) is the value of the subsequent pseudo current information (V A2 ) (hereinafter referred to as configuration P5).

[0141] This allows the output voltage to be stabilized quickly after the switching frequency is switched from the first frequency to the second frequency.

[0142] In a switching power supply circuit according to any of the above configurations P1 to P5, the current information generating circuit may be configured to, when the switching frequency is set to the first frequency, perform the current sensing operation in each period having a length equal to the reciprocal of the first frequency, and generate the detected current information obtained by the current sensing operation as current information for the coil (hereinafter referred to as configuration P6).

[0143] In the switching power supply circuit according to the above configuration P6, the switching control circuit calculates a comparison voltage (V Ca comparison voltage generating circuit (11 to 14) configured to generate a comparison voltage that changes monotonically from an initial level to a predetermined direction at a period that is the reciprocal of the first frequency; and a ramp voltage generating circuit (16) configured to generate a ramp voltage that changes monotonically from an initial level to a predetermined direction at a period that is the reciprocal of the first frequency, and in the switching operation, after the high-side transistor is turned on, a reset signal (S PWM a down edge of the reset signal, and turns off the high-side transistor and turns on the low-side transistor based on the issuance of the reset signal. In a state where the switching frequency is set to the first frequency, after the high-side transistor is turned on, a specified time (t MAX_ON ) has elapsed, the switching frequency may be switched from the first frequency to the second frequency (hereinafter referred to as configuration P7).

[0144] This makes it possible to increase the maximum duty of the output stage circuit when the input voltage temporarily drops, for example, thereby making it easier to maintain the output voltage at a desired value.

[0145] In the switching power supply circuit according to the above-described configuration P7, the switching control circuit may be configured to, after switching the switching frequency from the first frequency to the second frequency, return the switching frequency from the second frequency to the first frequency when the reset signal is issued before the specified time has elapsed since the turn-on timing of the high-side transistor (hereinafter referred to as configuration P8).

[0146] This allows the switching frequency to return to the first frequency, for example, when the input voltage rises after a drop in the input voltage.

[0147] A switching power supply device according to one aspect of the present disclosure has a configuration (hereinafter referred to as configuration P9) including a switching power supply circuit according to any one of the above configurations P1 to P8, and a rectifying and smoothing circuit configured to generate the output voltage by rectifying and smoothing the switching voltage.

[0148] Second Embodiment A second embodiment of the present disclosure will now be described. An overall configuration diagram and an external perspective view of a switching power supply device 1 according to the second embodiment are as shown in Figures 1 and 2. In the second embodiment, a power supply IC 2C shown in Figure 12 is used as the power supply IC 2.

[0149] 12 shows the configuration of a switching power supply device 1 having a power supply IC 2C. The power supply IC 2C is an example of the power supply IC 2. Unless contradictory, all of the matters described above regarding the power supply IC 2 also apply to the power supply IC 2C.

[0150] The main control block 3 in the power supply IC 2C includes an error amplifier 11, a phase compensation circuit 12, a differential amplifier 13, a phase compensation circuit 14, a clock generation circuit 15, a ramp voltage generation circuit 16, a comparator 17, a logic circuit 18, a driver 19, and a current information generation circuit 30C. The power supply IC 2C performs switching operations using pulse width modulation. The power supply IC 2C is obtained by replacing the current information generation circuit 30 in FIG. 3 with the current information generation circuit 30C, based on the power supply IC 2A according to the first embodiment. Apart from this replacement, the configuration and operation of the power supply IC 2C are the same as those of the power supply IC 2A. Unless otherwise stated and consistent, the description of the first embodiment may be applied to the second embodiment. The ramp voltage V shown in FIG. 4 RAMP and the clock signal CLK also apply to the second embodiment. In interpreting the description of the second embodiment, the description of the second embodiment takes precedence over any inconsistencies between the first and second embodiments.

[0151] The current information generating circuit 30C performs a low-side current sensing operation to detect the current flowing through the transistor M2 during the on-period of the transistor M2, and generates a voltage V corresponding to the coil current information through the low-side current sensing operation. IL During the on-period of the transistor M2, the current flowing through the transistor M2 passes through the coil L1. Therefore, the low-side current sensing operation can be said to be an operation of detecting the coil current IL by detecting the current flowing through the transistor M2.

[0152] Furthermore, the current information generating circuit 30C may perform a high-side current sensing operation to detect the current flowing through the transistor M1 during the on-period of the transistor M1. At this time, a voltage V corresponding to the coil current information is generated through the high-side current sensing operation. IL During the ON period of the transistor M1, the current flowing through the transistor M1 passes through the coil L1. Therefore, the high-side current sensing operation can be said to be an operation of detecting the coil current IL by detecting the current flowing through the transistor M1.

[0153] The current information generating circuit 30C generates a higher voltage V IL The voltage V IL is fed back to the differential amplifier 13, the error voltage V ERR The increase in the coil current IL causes an increase in the error voltage V ERR The decrease in the current I L causes a decrease in the coil current I L .

[0154] 12, the current information generation circuit 30C includes a sense resistor 31, an S / H circuit 32, and an amplifier circuit 33. The operation of the current information generation circuit 30C may be controlled by the logic circuit 18. The current information generation circuit 30C can detect the current flowing through the transistor M2 (and therefore the coil current IL) by detecting the voltage drop across the sense resistor 31. Note that FIG. 12 only illustrates the portion of the current information generation circuit 30C involved in low-side current sensing operation. The portion involved in high-side current sensing operation is shown in other drawings.

[0155] The sense resistor 31 is connected in series to the transistor M2 and ground. Specifically, a first end of the sense resistor 31 is connected to the source of the transistor M2, and a second end of the sense resistor 31 is connected to the ground terminal GND. During the on-period of the transistor M2, a coil current IL flows through the sense resistor 31 and the transistor M2, and a voltage drop proportional to the coil current IL occurs across the sense resistor 31.

[0156] The S / H circuit 32 is a sampling / hold circuit for the voltage drop across the sense resistor 31. That is, the S / H circuit 32 is connected to the first and second ends of the sense resistor 31, and in low-side current sensing operation, samples and holds the voltage drop across the sense resistor 31 (i.e., the voltage generated across both terminals of the sense resistor 31) at a sampling timing set by the logic circuit 18. In low-side current sensing operation, the amplifier circuit 33 amplifies the voltage currently held in the S / H circuit 32 and outputs the amplified voltage. When the output voltage of the amplifier circuit 33 is voltage V IL The voltage V IL represents the detected value (detected current value) of the coil current IL. In the low-side current sensing operation, the detected value of the coil current IL is expressed as a voltage V IL It is equivalent to dividing by .

[0157] The frequency at which the transistors M1 and M2 are alternately turned on and off is called the switching frequency, and is particularly represented by the symbol "f SW ". Switching frequency f SW is the switching frequency of transistor M1 (hence the frequency of gate signal G1) and is also the switching frequency of transistor M2 (hence the frequency of gate signal G2). IN is the output voltage V OUT When the switching frequency f SW is the reference frequency f REF and stabilizes.

[0158] The switching frequency f SW is the reference frequency f REF Timing chart when the switching frequency is stable (i.e., f SW is the reference frequency f REF 10C shows a timing chart when the current information generating circuit 30C is maintained at "f SW = f REF ", only the low-side current sensing operation is used to detect the coil current IL and obtain the coil current information (V IL ) is generated.PWM , lamp voltage V RAMP , clock signal CLK, gate signal G1, gate signal G2, coil current IL and voltage V IL The waveform of the voltage V is shown by a solid line. C 13, rising edges occur in the clock signal CLK at successive times T11, T12, T13, and T14. When the rising edge occurs in the clock signal CLK at time T11 while the output stage circuit MM is in the output low state, the logic circuit 18 causes a rising edge to occur in the gate signal G1 and a falling edge to occur in the gate signal G2, thereby switching the output stage circuit MM from the output low state to the output high state.

[0159] As described above, the rising edge of the clock signal CLK at time T11 triggers the ramp voltage V RAMP is the initial level (V RAMP_MIN ) and starts rising. Lamp voltage V RAMP When is at the initial level, "V C >V RAMP " is established, and therefore the signal S PWM is at a high level. RAMP During the rise of the lamp voltage V RAMP is the contrast voltage V C When it reaches the signal S PWM A down edge occurs at the lamp voltage V RAMP is the contrast voltage V C To reach this level is to C >V RAMP "From the established state of "V C <V RAMP ” is established. PWM Hereinafter, the reset signal is issued when the comparator 17 outputs a low-level signal S PWM is output, or the signal S PWM This means that a down edge occurs.

[0160] When the reset signal is issued, the logic circuit 18 generates a falling edge in the gate signal G1 and a rising edge in the gate signal G2, thereby switching the output stage circuit MM from the output high state to the output low state (except when the reset signal is invalid). After that, when a falling edge occurs in the clock signal CLK, the ramp voltage V RAMP is the initial level (V RAMP_MIN ), which returns the signal S PWM Then, at time T12, another rising edge occurs in the clock signal CLK. Thereafter, the same operation is repeated.

[0161] When the output stage circuit MM is in the high output state, the input voltage V is applied from the input terminal IN to the output terminal OUT through the transistor M1 and the coil L1. IN When the output stage circuit MM is in the low state, a current based on the stored energy in the coil L1 flows through the transistor M2 and the coil L1, and the coil current IL gradually decreases.

[0162] The logic circuit 18 sets the sampling timing during the ON period of the transistor M2 (i.e., the period during which the output stage circuit MM is in the output low state). The set sampling timing will be hereinafter referred to as "T SMPL ". One sampling timing T SMPL is set, and each sampling timing T SMPL The low-side current sensing operation is performed at

[0163] In the low-side current sensing operation, the S / H circuit 32 detects the voltage drop across the sense resistor 31 at the sampling timing T SMPL The sampling timing T is set between the times T11 and T12. SMPL Specifically, the symbol "T SMPL1 ” and the sampling timing T set between the times T12 and T13. SMPL Specifically, the symbol "T SMPL2” and the sampling timing T set between the times T13 and T14. SMPL Specifically, the symbol "T SMPL3 " for reference.

[0164] Sampling timing T SMPL1 , T SMPL2 , T SMPL3 The voltage sampled at the amplifier circuit 33 is amplified by the amplifier circuit 33 to obtain a voltage V IL are respectively represented by the symbol V IL1 , V IL2 , V IL3 The output voltage V of the amplifier circuit 33 is IL is the sampling timing T SMPL1 From the sampling timing T SMPL2 Voltage V IL1 Similarly, the output voltage V of the amplifier circuit 33 is maintained at IL is the sampling timing T SMPL2 From the sampling timing T SMPL3 Voltage V IL2 This will be maintained in the future.

[0165] Any timing during the ON period of the transistor M2 is the sampling timing T SMPL For example, the logic circuit 18 may set the timing at which a predetermined time has elapsed since the transistor M2 was turned on as the sampling timing T SMPL Alternatively, for example, the logic circuit 18 may set the timing a predetermined time before the turn-off timing of the transistor M2 as the sampling timing T SMPL Here, the center timing of the ON period of the transistor M2 is the sampling timing T SMPL shall be set to

[0166] The low-side current sensing operation requires a certain time. MIN_SNS is understood to refer to the minimum time that must be ensured for the low-side current sensing operation. REF and the minimum sense time t MIN_SNS The relationship between the reference time tREF The minimum sense time t MIN_SNS is shorter. The time difference (t REF -t MIN_SNS ) is "f SW = f REF The maximum on-time t MAX_ON It corresponds to the maximum on-time t MAX_ON represents the maximum length of the ON period of the transistor M1 in one cycle of the switching operation. For example, the reference frequency f REF is 2 MHz (megahertz) and the minimum sense time t MIN_SNS is 200 nanoseconds, then "f SW = f REF The maximum on-time t MAX_ON is 300 nanoseconds, and "f SW = f REF The maximum duty when "is" is 60%. The duty indicates the proportion of the on time of the transistor M1 that occupies one cycle of the switching operation, and the maximum value that the duty can take is the maximum duty.

[0167] As in the first embodiment, the period between two adjacent rising edge timings of the clock signal CLK is called a unit period. The length of the unit period is the reference time t REF Each unit period is a composite period of a first period and a second period. In each unit period, the first period is followed by the second period. The length of the second period is the minimum sense time t MIN_SNS The length of the first period is "f SW = f REF The maximum on-time t MAX_ON matches.

[0168] The power supply IC2C basically outputs an output voltage V OUT Compared to the input voltage V IN In this application, the on-time of the transistor M1 is considerably short while the on-time of the transistor M2 is sufficiently long in each switching cycle, so that the time required to detect the current flowing through the transistor M2 can be easily and stably secured.

[0169] However, in the switching power supply device 1, IN >V OUT " is the voltage V IN and V OUT The difference between the two becomes smaller, or IN <V OUT For example, in an in-vehicle application, the output voltage of a battery (not shown) mounted on a vehicle such as an automobile may be greater than the input voltage V IN In this case, when starting or restarting the engine using the starter, the battery output voltage may temporarily drop significantly. IN >V OUT " is the voltage V IN and V OUT The difference between the two becomes smaller, or IN <V OUT " Sometimes it becomes like this.

[0170] Input voltage V IN During the period when the duty is decreasing, it is better to increase the duty as high as possible, OUT For example, it is advantageous to maintain the target voltage V TG When the input voltage V is 5V, the input voltage V has a value of 12V. IN When the voltage drops to 7V, if the maximum duty is 60%, the output voltage V OUT can only be raised to about 4.2V, but if the maximum duty is 80%, the output voltage V OUT It is possible to maintain the voltage at around 5V.

[0171] Minimum sense time t MIN_SNS Since is unchanged, to increase the maximum duty, the switching frequency f SW For example, lowering the reference frequency f REF is 2 MHz (megahertz) and the minimum sense time t MIN_SNS When is 200 nanoseconds, the switching frequency f SWBy lowering the switching frequency f from 2 MHz to 1 MHz, the maximum duty can be increased from 60% (= (500 ns - 200 ns) / 500 ns) to 80% (= (1000 ns - 200 ns) / 1000 ns). SW If is further reduced, the maximum duty will further increase.

[0172] The logic circuit 18 controls the switching frequency f SW is the reference frequency f REF or the reference frequency f REF It can be set to (1 / n) times of "f", where n is an arbitrary integer of 2 or more. SW = f REF " is particularly referred to as a reference switching operation. SW = f REF / n" is particularly referred to as a frequency division switching operation.

[0173] The time from the rising edge of the clock signal CLK to the issuance of the reset signal is determined by the input voltage V IN The increase in the time means the need for an increase in duty. SW = f REF ", after turning on the transistor M1, "f SW = f REF The maximum on-time t MAX_ON If the reset signal is not issued before the elapse of the time, the logic circuit 18 transitions the switching operation to be performed from the reference switching operation to the frequency division switching operation, thereby increasing the maximum duty.

[0174] However, when a frequency division switching operation is performed, a high duty cycle can be obtained, but the low side current sensing operation cannot be performed for a relatively long time. In the power supply IC 2C according to this embodiment, when a frequency division switching operation is performed, the high side current sensing operation is performed in the output high state, thereby obtaining coil current information (V IL Before describing this in detail, the second hypothetical operation will be described.

[0175] 14 shows a timing chart for the second hypothetical operation. Unlike the power supply IC 2C according to this embodiment, only the low-side current sensing operation is always performed in the second hypothetical operation. In FIG. 14, waveforms 1911 to 1919 respectively represent the input voltage V IN , output voltage V OUT , contrast voltage V C , lamp voltage V RAMP , clock signal CLK, gate signal G1, gate signal G2, coil current I L and voltage V IL The waveform 1920 is the output voltage V OUT The waveform 1918 of the coil current IL corresponds to an enlarged waveform (the waveform 1912 enlarged in the voltage direction). Each white circle shown on the waveform 1918 of the coil current IL indicates the sampling timing T SMPL Represents the voltage V IL Each white circle shown on the waveform 1919 represents each sampling timing T SMPL The coil current information (V IL ) represents

[0176] In the example of FIG. 14, the reference switching operation is performed until time T21. However, before time T21, the input voltage V IN and output voltage V OUT In other words, in each switching period before time T21, the on time of the transistor M2 is equal to the minimum sense time t MIN_SNS (However, the minimum sense time t MIN_SNS Now, at time T21, the input voltage V IN At time T21, a rising edge occurs in the clock signal CLK. At time T23, the reference time t REF Therefore, the next rising edge of the clock signal CLK occurs at time T23. Time T22 is the time from time T23 to the minimum sense time t MIN_SNS represents the previous time.

[0177] Input voltage V INAs the voltage drops, the reset signal is not issued before time T22 in the switching cycle starting from time T21. Therefore, the logic circuit 18 associated with the second virtual operation switches the switching operation to be executed from the reference switching operation to the frequency-dividing switching operation, and keeps the output stage circuit MM in the high output state until the reset signal is issued after time T23.

[0178] 14, at time T24 after time T23, the state of the output stage circuit MM is switched from the output high state to the output low state in response to the issuance of a reset signal, and low-side current sensing operation is performed while transistor M2 is on. Time T25 is the time when the next rising edge of the clock signal CLK occurs after time T23.

[0179] 14, the low-side current sensing operation is not performed between times T21 and T24. Therefore, the detected current information obtained in the low-side current sensing operation immediately before time T21 is not used as the coil current information (V IL ) is continuously used as the coil current information (V IL Therefore, the feedback control is performed without reflecting the comparison voltage V C is constant, and as a result, the duty becomes excessively large in the switching operation starting from time T21. The excessive increase in duty causes the coil current IL to increase more than necessary, and the output voltage V OUT After that, an undesirable fluctuation occurs in the coil current IL for a while, causing an overshoot in the output voltage V OUT is unstable.

[0180] Examples EX2_1 to EX2_4 will be described below as a plurality of examples related to the switching power supply device 1 of the second embodiment. Any two or more of Examples EX2_1 to EX2_4 can be combined with each other.

[0181] <<Embodiment EX2_1>> An embodiment EX2_1 will be described. FIG. 15 shows a timing chart for embodiment EX2_1. As time passes, times T30 to T35, T41 to T45, T51 to T55, and T61 occur in this order. In FIG. 15, waveforms 1611 to 1619 respectively represent the input voltage V IN , output voltage V OUT , contrast voltage V C , lamp voltage V RAMP , clock signal CLK, gate signal G1, gate signal G2, coil current I L and voltage V IL The waveform 1620 is the output voltage V OUT The dashed waveform 1920 shown in FIG. 15 corresponds to the waveform 1920 shown in FIG. 14 (the output voltage V OUT Each white circle shown on the waveform 1618 of the coil current IL corresponds to the sampling timing T SMPL and the low-side current sensing operation is performed at each sampling timing T SMPL The current flowing through the transistor M2 is sampled and detected at HS_D. A period HS_D indicates a period during which the high-side current sensing operation is performed.

[0182] In the example of FIG. 15, the reference switching operation is performed up to time T31. SW = f REF In each switching period before time T31, the current information generating circuit 30C performs a low-side current sensing operation.

[0183] In the example of FIG. 15, the switching operation to be performed is switched from the standard switching operation to the frequency division switching operation of "n=2" at time T31.

[0184] Before time T31, the input voltage V IN and output voltage V OUT In other words, in each switching period before time T31, the ON time of the transistor M2 is equal to the minimum sense time t MIN_SNS(However, the minimum sense time t MIN_SNS The time T30 is the sampling timing T of the low-side current sensing operation performed immediately before the time T31. SMPL is.

[0185] Now, the input voltage V IN At time T31, a rising edge occurs in the clock signal CLK, and the state of the output stage circuit MM changes from the output low state to the output high state. Time T33 is the time from time T31 to the reference time t REF Therefore, the next rising edge of the clock signal CLK occurs at time T33. Time T32 is the time from time T33 to the minimum sense time t MIN_SNS represents the previous time.

[0186] Input voltage V IN As the voltage V decreases, in the switching cycle starting from time T31, a reset signal is not issued before time T32 (i.e., a reset signal is not issued during the previous period: see FIG. 6). On the condition that a reset signal is not issued before time T32, the logic circuit 18 switches the switching operation to be performed from the reference switching operation to the frequency-dividing switching operation. When this switching is performed, the logic circuit 18 invalidates the reset signal issued between times T32 and T33, and the voltage V between times T32 and T33 C and V RAMP Regardless of the high / low relationship between the time T32 and the time T33, the output stage circuit MM is kept in the output high state.

[0187] At time T33, a rising edge occurs in the clock signal CLK, but even at this time, the logic circuit 18 keeps the output stage circuit MM in the high output state. REF In the example of FIG. 15, after time T33, at time T34, the lamp voltage V RAMP is the contrast voltage V C The reset signal is issued when the time T34 is reached. The time T34 is before the time T41, and the time difference between the time T34 and the time T41 is the minimum sense time t MIN_SNSTherefore, at time T34, the logic circuit 18 switches the output stage circuit MM from the high output state to the low output state based on the issued reset signal. The logic circuit 18 sets time T35, which is between times T34 and T41, as the sampling timing T SMPL In accordance with the setting result, the current information generating circuit 30C performs a low-side current sensing operation at time T35.

[0188] At time T41, a rising edge occurs in the clock signal CLK, and the state of the output stage circuit MM switches from the output low state to the output high state. REF Therefore, the next rising edge of the clock signal CLK occurs at time T43. Time T42 is the time from time T43 to the minimum sense time t MIN_SNS represents the previous time.

[0189] The input voltage V generated at time T31 IN The decrease in voltage V is maintained after time T41. As a result, in the switching cycle starting from time T41, a reset signal is not issued before time T42 (i.e., a reset signal is not issued during the previous period: see FIG. 6). On the condition that a reset signal is not issued before time T42, the logic circuit 18 maintains the frequency division switching operation as the switching operation to be performed. When the frequency division switching operation is maintained, the logic circuit 18 invalidates the reset signal issued between times T42 and T43, and the voltage V between times T42 and T43 is C and V RAMP Regardless of the high / low relationship between the time T42 and the time T43, the output stage circuit MM is kept in the output high state.

[0190] At time T43, a rising edge occurs in the clock signal CLK, but even at this time, the logic circuit 18 keeps the output stage circuit MM in the high output state. REF In the example of FIG. 15, after time T43, at time T44, the lamp voltage V RAMP is the contrast voltage V CThe reset signal is issued when the time T44 is reached. The time T44 is before the time T51, and the time difference between the time T44 and the time T51 is the minimum sense time t MIN_SNS Therefore, at time T44, the logic circuit 18 switches the output stage circuit MM from the high output state to the low output state based on the issued reset signal. The logic circuit 18 sets time T45, which is between times T44 and T51, as the sampling timing T SMPL In accordance with the setting result, the current information generating circuit 30C performs the low-side current sensing operation at time T45.

[0191] At time T51, a rising edge occurs in the clock signal CLK, and the state of the output stage circuit MM switches from the output low state to the output high state. REF Therefore, the next rising edge of the clock signal CLK occurs at time T53. Time T52 is the time from time T53 to the minimum sense time t MIN_SNS represents the previous time.

[0192] The input voltage V generated at time T31 IN The decrease in voltage V is maintained after time T51. As a result, in the switching cycle starting from time T51, a reset signal is not issued before time T52 (i.e., a reset signal is not issued during the previous period: see FIG. 6). On the condition that a reset signal is not issued before time T52, the logic circuit 18 maintains the frequency division switching operation as the switching operation to be performed. When the frequency division switching operation is maintained, the logic circuit 18 invalidates the reset signal issued between times T52 and T53, and the voltage V between times T52 and T53 C and V RAMP Regardless of the high / low relationship between the two signals, the output stage circuit MM is kept in the high output state between times T52 and T53.

[0193] At time T53, a rising edge occurs in the clock signal CLK, but even at this time, the logic circuit 18 keeps the output stage circuit MM in the high output state. REFIn the example of FIG. 15, after time T53, at time T54, the lamp voltage V RAMP is the contrast voltage V C The reset signal is issued when the time T54 is reached. The time T54 is before the time T61, and the time difference between the time T54 and the time T61 is the minimum sense time t MIN_SNS Therefore, at time T54, the logic circuit 18 switches the output stage circuit MM from the high output state to the low output state based on the issued reset signal. The logic circuit 18 sets time T55, which is between times T54 and T61, as the sampling timing T SMPL In accordance with the setting result, the current information generating circuit 30C performs a low-side current sensing operation at time T55.

[0194] Input voltage V IN As long as the decrease in the frequency continues, the same frequency division switching operation of "n=2" continues thereafter.

[0195] In the operation example of FIG. 15, from time T31 to “f SW = f REF 15, the logic circuit 18 sets the periods between times T33 and T34, the periods between times T43 and T44, and the periods between times T53 and T54 as periods HS_D during which the high side current sense operation is performed, and performs the high side current sense operation in each period HS_D.

[0196] Hereinafter, the current value detected by the low-side current sensing operation will be referred to as the low-side detected current value, and the current value detected by the high-side current sensing operation will be referred to as the high-side detected current value. The low-side detected current value is the detected value of the current flowing through transistor M2 during the on-period of transistor M2. The high-side detected current value is the detected value of the current flowing through transistor M1 during the on-period of transistor M1.

[0197] During each period HS_D, the current information generating circuit 30C continuously detects the current flowing through the transistor M1 and generates a voltage V IL In each period HS_D, the voltage V IL The value of is updated in real time according to the current flowing through the transistor M1. SMPL Up to voltage V IL has a value corresponding to the current flowing through the transistor M2 (here, a value corresponding to the voltage drop across the sense resistor 31). SMPL When low-side current sensing is performed at IL The value of the voltage V is updated to a value representing the low-side sensed current value. After that, until the next high-side or low-side current sensing operation is performed, IL The value of is maintained.

[0198] Therefore, in the operation example of FIG. 15, from time T30 to just before time T33, the voltage V IL The time T30 is the sampling timing T SMPL represents the low-side detection current value of the low-side current sensing operation (i.e., the low-side detection current value at time T30 is maintained). IL represents the high-side detected current value between times T33 and T34 in real time. From time T34 to time T35, the voltage V IL has a value corresponding to the current flowing through the transistor M2 (here, a value corresponding to the voltage drop across the sense resistor 31). However, from time T34 to time T35, the voltage V IL The value of the voltage V IL The time T35 may be set as the sampling timing T SMPL When the low-side current sensing operation is performed, the voltage V IL The time T35 is the sampling timing T SMPLrepresents the low-side detected current value of the low-side current sensing operation (i.e., the low-side detected current value at time T35 is maintained).

[0199] Therefore, in the operation example of FIG. 15, from time T35 to just before time T43, the voltage V IL The time T35 is the sampling timing T SMPL represents the low-side detection current value of the low-side current sensing operation. IL represents the high-side detected current value between times T43 and T44 in real time. From time T44 to time T45, the voltage V IL has a value corresponding to the current flowing through the transistor M2 (here, a value corresponding to the voltage drop across the sense resistor 31). However, from time T44 to time T45, the voltage V IL The value of the voltage V IL The time T45 may be set as the sampling timing T SMPL When the low-side current sensing operation is performed, the voltage V IL The time T45 is the sampling timing T SMPL represents the low-side detected current value of the low-side current sensing operation (i.e., the low-side detected current value at time T45 is maintained).

[0200] Therefore, in the operation example of FIG. 15, from time T45 to just before time T53, the voltage V IL The time T45 is the sampling timing T SMPL represents the low-side detected current value of the low-side current sensing operation. SW = f REF If / 2" is maintained, the same operation is repeated from time T53 onwards.

[0201] In each unit period, the logic circuit 18 monitors whether a reset signal has been issued during the previous period, thereby making it possible to cause the current information generating circuit 30C to switch between the reference switching operation and the frequency division switching operation.

[0202] FIG. 16 shows a configuration example of a current information generation circuit 30C according to Example EX2_1. The current information generation circuit 30C shown in FIG. 16 includes the above-mentioned sense resistor 31, S / H circuit 31, and amplifier circuit 33, as well as the components referenced by reference numerals 41 to 51. Wiring 52 and 53 and nodes 54 to 46 are also components of the current information generation circuit 30C. In FIG. 16, the S / H circuit 32 includes capacitors 32a and 32b and switches 32c and 32d, and the amplifier circuit 33 includes a positive input terminal 33a, a negative input terminal 33b, and an output terminal 33c. The amplifier circuit 33 may actually be an amplifier circuit configured with an operational amplifier and a resistor. The amplifier circuit 33 amplifies the voltage at the positive input terminal 33a as seen from the potential at the negative input terminal 33b, and outputs the amplified voltage from the output terminal 33c as a voltage V IL Output as

[0203] A capacitor 32a is connected between the positive input terminal 33a and the ground. The positive input terminal 33a is also connected to one end of a switch 32c, the other end of which is connected to the connection node between the sense resistor 31 and the ground terminal GND. A capacitor 32b is connected between the negative input terminal 33b and the ground. The negative input terminal 33b is also connected to one end of a switch 32d, the other end of which is connected to the connection node between the source of the transistor M2 and the sense resistor 31. The voltage of the ground terminal GND as viewed from the source potential of the transistor M2 is referred to as voltage Va. The resistance value of the sense resistor 31 is represented by the symbol "R SNS ". During the ON period of the transistor M2, "Va=R SNS ×IL” is established.

[0204] One end of the switch 41 is connected to the drain of the transistor M1, and the other end of the switch 41 is connected to the non-inverting input terminal of the operational amplifier 43. One end of the switch 42 is connected to the source of the transistor M1, and the other end of the switch 42 is connected to a wiring 52. The inverting input terminal and the output terminal of the operational amplifier 43 are connected to each other. The operational amplifier 43 uses the voltage on the wiring 52 as a negative power supply voltage and a boot voltage V BOOTas a positive power supply voltage and functions as a voltage buffer. Therefore, the operational amplifier 43 outputs the voltage at its non-inverting input terminal from its output terminal with low impedance. The transistors 45 to 47 are P-channel MOSFETs. The sources of the transistors 45 and 46 are connected to the boot voltage V BOOT The gate and drain of transistor 45, the gate of transistor 46, the output terminal of operational amplifier 43, and one end of resistor 44 are connected to node 54. The other end of resistor 44 is connected to wiring 52. The voltage drop occurring across resistor 44 is referred to as voltage Vb. Note that voltage Vb represents the voltage at node 54 as viewed from the potential of wiring 52.

[0205] The drain of the transistor 46 is connected to the source of the transistor 47. The drain of the transistor 47 is connected to one end of a resistor 48 at a node 55, and the other end of the resistor 48 is connected to ground. The gate of the transistor 47 is connected to the internal power supply voltage V REG is applied. The voltage drop across resistor 48 is referred to as voltage Vc. Here, voltage Vc represents the voltage at node 55 as viewed from ground potential. Voltage conversion circuit 49 generates voltage Vd from voltage Vc. In FIG. 16, it is assumed that "Vd<Vc." Therefore, voltage conversion circuit 49 includes an operational amplifier 49a constituting a voltage follower, and resistors 49b and 49c constituting a voltage divider circuit. The non-inverting input terminal of operational amplifier 49a is connected to node 55, and the output terminal is connected to the inverting input terminal and one end of resistor 49. The other end of resistor 49b is connected to one end of resistor 49c at node 56, and the other end of resistor 49c is connected to ground. The voltage drop across resistor 49c is referred to as voltage Vd. Here, voltage Vd represents the voltage at node 56 as viewed from ground potential.

[0206] The current information generating circuit 30C sets the states of the switches 32c, 32d, 41, 42, 50, and 51 as follows (see FIG. 17) under the control of the logic circuit 18. During the ON period of the transistor M2, the current information generating circuit 30C maintains all of the switches 41, 42, 50, and 51 in the OFF state. During the ON period of the transistor M2, the current information generating circuit 30C sets the states of the switches 32c, 32d, 41, 42, 50, and 51 as follows (see FIG. 17). SMPL The switches 32c and 32d are kept in the on state until the sampling timing T SMPL After that, the switches 32c and 32d are kept in the OFF state. The current information generation circuit 30C keeps the switches 32c and 32d in the OFF state while the transistor M1 is ON. The current information generation circuit 30C keeps all of the switches 41, 42, 50, and 51 in the ON state only during the execution period HS_D of the high-side current sensing operation while the transistor M1 is ON, and keeps all of the switches 41, 42, 50, and 51 in the OFF state during the other periods.

[0207] The on-resistance (on-resistance value) of the transistor M1 is set to "R ON Then, in the period HS_D, the coil current IL flows between the drain and source of the transistor M1, and therefore, in the period HS_D, "Vb=R ON H×IL”. The transistors 45 and 46 form a current mirror circuit. Here, it is assumed that the drain current ratio of the transistors 45 and 46 is 1:1, and that the resistance values ​​of the resistors 44 and 48 are the same. In this case, during the period HS_D, a current having the same current value as the current flowing through the resistor 44 flows through the resistor 48, and therefore “Vc=R ON The transistors 45 to 47 form a level shifter that converts the voltage Vb based on the source potential of the transistor M1 into a voltage Vc based on the ground potential.

[0208] In the period HS_D, "Vd=R SNS × IL”, the on-resistance R ON H and sense resistor R SNS The voltage conversion circuit 49 is configured based on the ratio of "R ON H>RSNS ", so that "Vd = R SNS ×IL”. However, “R ON H<R SNS In the case of "R", the voltage Vc is amplified by the voltage conversion circuit 49 to generate the voltage Vd. ON H=R SNS In the case where "Vd=R" is satisfied during the period HS_D, the voltage conversion circuit 49 may be a single voltage follower. SNS ×IL”.

[0209] With the above configuration and operation, the voltage V IL That is, for example, time T30 is set as the sampling timing T SMPL When the low-side current sensing operation is performed, the voltage difference between the voltages held in the capacitors 32a and 32b is amplified at time T30 and becomes a voltage V IL (a voltage representing the low-side detected current value). After time T30, the switches 32c and 32d are kept off until the next on-period of the transistor M2 begins. Therefore, after time T30, the voltage V IL The value of remains unchanged until the next low-side or high-side current sensing operation. After time T30, the high-side current sensing operation starts at time T33, and therefore the switches 41, 42, 50, and 51 are all switched to the ON state. Therefore, during the period HS_D between times T33 and T34, the voltage Vd is applied between the input terminals 33b and 33a of the amplifier circuit 33, and a voltage V IL (a voltage representing the high-side detected current value) is output. At this time, the voltages Vd and V IL changes in real time.

[0210] Then, at time T34, transistor M1 is turned off and transistor M2 is turned on, so that switches 41, 42, 50, and 51 are all turned off while switches 32c and 32d are turned on. LThe voltage V a varies in conjunction with the change in the current flowing through the transistor M2. Then, at time T35, the voltage V a at that time is sampled and held. IL is maintained at a value according to the voltage Va at time T35 until the next low-side or high-side current sensing operation is performed.

[0211] According to this embodiment, the low-side current sensing operation and the high-side current sensing operation are used together in the frequency division switching operation, so that the value of the coil current IL is accurately compared with the voltage V C When the frequency division switching operation is performed, the rise in the coil current IL during the output high state that continues for a relatively long time is fed back to the differential amplifier 13, and the rise in the comparison voltage V C As a result, as can be seen from a comparison between FIG. 14 and FIG. 15, an excessive increase in duty is suppressed in the frequency division switching operation. Therefore, in the embodiment EX2_1, when the switching operation is switched from the reference switching operation to the frequency division switching operation, the output voltage V OUT (See waveform 1620 according to the embodiment EX2_1 and waveform 1920 according to the second hypothetical operation), i.e., the fluctuation of the output voltage V OUT can be well stabilized.

[0212] In the high output state, the coil current IL increases at a rate that corresponds to the inductance of the coil L1. For this reason, when the frequency division switching operation is performed in the high output state, it is considered to superimpose pseudo current information based on the design value of the inductance of the coil L1 onto the coil current information. However, if the inductance value of the coil L1 actually used deviates from the design value, it is not possible to superimpose ideal pseudo current information, and as a result, the output voltage V OUT However, the method of this embodiment does not pose such a concern.

[0213] The logic circuit 18 monitors the time from when the transistor M1 is turned on to when the reset signal is issued every time the transistor M1 is turned on. As can be understood from the above description, the logic circuit 18 monitors the time from when the transistor M1 is turned on to when the reset signal is issued, after the specified time t D If a reset signal is not issued before the specified time t has elapsed, the switching operation to be performed is switched from the reference switching operation to the frequency division switching operation. D is "f SW = f REF The maximum on-time t MAX_ON is.

[0214] After that, the transistor M1 is turned on and the predetermined time t D When a reset signal is issued before time T61 has elapsed, the condition for returning to the reference switching operation is met. When the condition for returning to the reference switching operation is met, the logic circuit 18 returns the switching operation to be performed to the reference switching operation. In the example of FIG. 15, after time T61, the input voltage V IN As a result of the input voltage V increasing, the switching operation to be performed can return to the reference switching operation. IN When the voltage Vcc is sufficiently increased, the transistor M1 is turned on at time T61, and then the voltage Vcc is increased by a predetermined time t D A reset signal is issued before the input voltage V IN If is sufficiently high, a reset signal is always issued during the previous period in each unit period, so that "f SW = f REF " is maintained.

[0215] When the frequency division switching operation is performed, the sense result holding time t P The coil current information (V IL ) represents the low-side detected current value obtained by the most recent low-side current sensing operation. The sense result retention time tP After the time has elapsed, the period until the transistor M1 is turned off is the period HS_D, and during this period HS_D, the coil current information (V IL ) represents the high-side detected current value by the high-side current sensing operation. SMPL When the low-side current sense operation is performed, the coil current information (V IL ) is updated to the information representing the low-side detected current value obtained by the current low-side current sensing operation.

[0216] In the example of FIG. 15, the sense result retention time t P is the reference frequency f REF 15, for example, the time from when the transistor M1 is turned on at time T31 until the sense result holding time t P (= 1 / f REF ) until time T33 when the coil current information (V IL ) is maintained at the low-side detected current value (corresponding to the voltage Va at time T30) obtained by the previous low-side current sensing operation. Then, from the time when the transistor M1 is turned on at time T31 until the sense result holding time t P After the time has elapsed, the coil current information (V IL ) represents the high-side detected current value (corresponding to the voltage Vd between times T33 and T34) obtained by the high-side current sensing operation. SMPL When the current low-side current sensing operation is performed at time T35, the coil current information (V IL ) is updated to information indicating the low-side detected current value by the current low-side current sensing operation (corresponding to voltage Va at time T35).

[0217] Sense result retention time t P is the reference frequency f REF The reciprocal of the time (i.e., the reference time t REF However, the sense result holding time t P is time (2 t REF -t MIN_SNS ) is shorter.

[0218] <<Embodiment EX2_2>> An embodiment EX2_2 will be described. In embodiment EX2_1, the frequency division switching operation of “n=2” was described. IN Depending on the degree of decrease in the frequency, a frequency division switching operation of "n≧3" may also be performed.

[0219] For example, the following case CSb is assumed based on the case shown in FIG. 15 (hereinafter referred to as case CSa). The differences between cases CSa and CSb are shown below with reference to FIG. 18. In case CSb, the input voltage V IN is significantly reduced. As a result, in case CSb, a reset signal is not issued in the first half of unit period 1641 starting at time T31, and a reset signal is not issued in the first half of unit period 1642 starting at time T33. In case CSb, a reset signal is then issued at time T41', which belongs to the first half of unit period 1643 starting at time T41 (whether or not a reset signal is issued is not shown in FIG. 18). Unit periods 1641 to 1643 are three consecutive unit periods. Times T41' and T42' are assumed to be after time T41 and before time T43. Time T42' is assumed to be after time T41'.

[0220] In case CSb, the logic circuit 18 switches the output stage circuit MM from the output low state to the output high state at time T31, and then maintains the output stage circuit MM in the output high state until time T41′, at which point the output stage circuit MM returns to the output low state. SMPL Then, at time T43, the rising edge of the clock signal CLK triggers the output stage circuit MM to switch to the high output state.

[0221] In case CSb, the sense result retention time t P is the reference frequency f REF The reciprocal of the time (i.e., the reference time t REF) from the time T31 when the transistor M1 is turned on until the time T33. IL ) represents the low-side detected current value obtained by the most recent low-side current sensing operation. From time T33 to time T41′ when the transistor M1 is turned off, the coil current information (V IL ) represents the high-side detected current value by the high-side current sensing operation. SMPL When the current low-side current sensing operation is performed at time T42′ (i.e., at time T42′), the coil current information (V IL ) is updated to the information representing the low-side detected current value obtained by the current low-side current sensing operation.

[0222] In case CSb, at time T31, the switching frequency f SW is the reference frequency f REF to frequency (f REF / 3). In case CSb, if a reset signal is not issued in the first half of the first unit period and the second unit period, and a reset signal is issued in the first half of the third unit period, even after time T43, the frequency division switching operation of "n=3" continues. Here, the first to third unit periods are three consecutive unit periods, and the first unit period is followed by the second unit period and then the third unit period. The conditions for returning to the standard switching operation are as shown in embodiment EX2_1.

[0223] It can be said that the logic circuit 18 operates as follows. After turning on the transistor M1, the logic circuit 18 monitors whether a reset signal is issued during the previous stage period. If a reset signal is issued during the previous stage period of a target unit period, which is an arbitrary unit period, the logic circuit 18 immediately switches the output stage circuit MM from an output high state to an output low state in response to the issuance of the reset signal, and performs a low-side current sensing operation during the on-period of the target unit period. If a reset signal is not issued during the previous stage period of the target unit period, the logic circuit 18 monitors the voltage V C and V RAMPThe output stage circuit MM is maintained in the high output state throughout the entire unit period of interest regardless of the level of the input voltage V. The next unit period is set as a new unit period of interest, and the same operation as described above is performed. IN Depending on the degree of the decrease in the voltage, the ON period of the transistor M1 may be extended without limit (however, an upper limit may be set).

[0224] <<Embodiment EX2_3>> Embodiment EX2_3 will be described. Low-side current sensing operation may be performed using the on-resistance of transistor M2 instead of sense resistor 31. In this case, the current information generation circuit 30m shown in FIG. 19 can be used as the current information generation circuit 30C in FIG. 1. In embodiment EX2_3, the current information generation circuit 30m in FIG. 19 is used as the current information generation circuit 30C in FIG. 1.

[0225] The current information generation circuit 30m in Fig. 19 does not have a sense resistor 31. In example EX2_3, the source of the transistor M2 is directly connected to the ground terminal GND. The changes to the current information generation circuit 30m in Fig. 19 from the current information generation circuit 30C in Fig. 16 due to the absence of the sense resistor 31 are as follows: With regard to matters not specifically mentioned in this example, the current information generation circuit 30m has the same configuration and operates in the same way as the current information generation circuit 30C.

[0226] The positive input terminal 33a is connected to one end of the switch 32c, and the other end of the switch 32c is connected to the source of the transistor M2. The negative input terminal 33b is connected to one end of the switch 32d, and the other end of the switch 32d is connected to the drain of the transistor M2. In the example EX2_3, the voltage Va indicates the voltage of the source of the transistor M2 as viewed from the drain potential of the transistor M2. The on-resistance of the transistor M2 is represented by the symbol "R ON L”. Then, during the ON period of the transistor M2, “Va=R ON L×IL” holds.

[0227] In the period HS_D, "Vd=R ON L×IL”, the on-resistance R ON H and R ONThe voltage conversion circuit 49 in the circuit 30m is configured based on the ratio of "R ON H>R ON Since it is assumed that the voltage is "Vd = R" using the voltage divider circuits (49b, 49c), ON L×IL”. However, “R ON H<R ON When the voltage Vc is "R", the voltage Vd can be generated by amplifying the voltage Vc in the voltage conversion circuit 49. ON H=R ON In the case where "Vd=R L" is set, the voltage conversion circuit 49 may be a single voltage follower. ON L x IL".

[0228] Basically, the transistors M1 and M2 may be elements having the same structure and withstand voltage. When the transistors M1 and M2 are elements having the same structure and withstand voltage, the temperature characteristics of the transistor M1 will be the same as the temperature characteristics of the transistor M2 (ignoring errors). The temperature characteristics of the transistors include the temperature characteristics of the on-resistance of the transistors.

[0229] The amplifier circuit 33 can be provided with temperature characteristics to cancel out the temperature characteristics of the on-resistance of the transistor M2. That is, when the on-resistance of the transistor M2 increases in response to a drop in the environmental temperature of the power supply IC 2C, the voltage Va during the on-period of the transistor M2 increases, but the amplifier circuit 33 is configured so that the amplification factor of the amplifier circuit 33 decreases at this time. The same applies when the environmental temperature of the power supply IC 2C rises. As a result, the coil current information (V IL The influence of the environmental temperature of the power supply IC 2C on the on-resistance of the transistor M1 is reduced. When the transistors M1 and M2 are elements having the same structure and withstand voltage, the temperature characteristics of the on-resistance of the transistor M1 can also be canceled out by the amplifier circuit 33. In other words, the circuit for canceling the temperature characteristics of the transistors M1 and M2 can be shared between the transistors M1 and M2, which leads to a reduction in circuit size.

[0230] Except for the absence of the sense resistor 31 and the above-mentioned matters linked to the absence of the sense resistor 31, the power supply IC2C according to the example EX2_3 is similar to the power supply IC2C according to the example EX2_1, and the description of the example EX2_1 also applies to the example EX2_3. In this application, the "voltage drop of the sense resistor 31" and the "value of the sense resistor 31" in the example EX2_1 can be read as the "voltage drop occurring between the drain and source of the transistor M2" and the "value of the on-resistance of the transistor M2" in the example EX2_3.

[0231] <<Example EX2_4>> Example EX2_4 will be described. All of the matters described in Example EX1_4 of the first embodiment are also applied to the second embodiment.

[0232] <<Second Supplementary Note>> A supplementary note will be provided for the present disclosure, the specific configuration example of which is shown in the second embodiment described above.

[0233] A switching power supply circuit according to one aspect of the present disclosure is IN ) to output voltage (V OUT a switching power supply circuit (2, 2A) used in a switching power supply device (1) for generating a switching voltage (V), the switching power supply circuit (2, 2A) comprises: an output stage circuit (MM) having a high-side transistor (M1) and a low-side transistor (M2) connected in series between an input terminal (IN) receiving the input voltage and a ground terminal (GND); a switching control circuit (11-19) configured to perform a switching operation of alternately turning on and off the high-side transistor and the low-side transistor; and a current information generating circuit (30C) configured to perform a first current sensing operation of detecting a current flowing through the low-side transistor during an on-period of the low-side transistor, or a second current sensing operation of detecting a current flowing through the high-side transistor during an on-period of the high-side transistor, wherein a connection node between the high-side transistor and the low-side transistor is connected to a rectifying and smoothing circuit including a coil (L1) and an output capacitor (C1), and a switching voltage (V) generated at the connection node by the switching operation. SW) is rectified and smoothed by the rectifying and smoothing circuit to generate the output voltage, and the switching control circuit generates voltage information (V FB ) and the coil current information (V IL ) and performs the switching operation based on the first frequency (f REF ) or a second frequency (f REF / n), and the current information generation circuit generates current information of the coil by the first current sensing operation when the switching frequency is set to the first frequency, and generates current information of the coil by using both the first current sensing operation and the second current sensing operation when the switching frequency is set to the second frequency (hereinafter referred to as configuration Q1).

[0234] When the switching frequency is set to the relatively low second frequency, the interval between execution of the first current sensing operation becomes longer. However, by performing the second current sensing operation during the on-period of the high-side transistor, feedback control that reflects the coil current becomes possible even during periods when the first current sensing operation cannot be performed. As a result, the output voltage is stabilized.

[0235] In the switching power supply circuit according to the above-described configuration Q1, the current information generation circuit may be configured to, when the switching frequency is set to the second frequency, generate current information about the coil during an on-period of the high-side transistor by performing the second current sensing operation during the on-period of the high-side transistor, and to generate current information about the coil during an on-period of the low-side transistor by performing the first current sensing operation during the on-period of the low-side transistor (hereinafter referred to as configuration Q2).

[0236] In the switching power supply circuit according to the above-described configuration Q2, when the switching frequency is set to the second frequency, the current information generation circuit may be configured to update the coil current information by continuously detecting the current flowing through the high-side transistor during a part of the on-period of the high-side transistor (for example, between T33 and T34 in FIG. 15) in the second current sensing operation, and then, when the high-side transistor is turned off and the low-side transistor is turned on, perform the first current sensing operation to detect the current flowing through the low-side transistor at a sampling timing (for example, T35 in FIG. 15) set within the on-period of the low-side transistor, thereby generating the coil current information during the on-period of the low-side transistor (hereinafter referred to as configuration Q3).

[0237] In the switching power supply circuit according to the above configuration Q3, when the switching frequency is set to the second frequency, the sense result hold time (t P 15 ) has elapsed, the coil current information represents the detected current value by the previous first current sensing operation (for example, the detected current value at T30 in FIG. 15 ), and after the sense result retention time has elapsed since the high-side transistor was turned on, until the high-side transistor is turned off (for example, between T33 and T34 in FIG. 15 ), the coil current information represents the current detection value by the second current sensing operation, and thereafter, when the current first current sensing operation is performed at the sampling timing, the coil current information may be updated to information representing the detected current value by the current first current sensing operation (for example, the detected current value at T35 in FIG. 15 ) (hereinafter referred to as configuration Q4).

[0238] In the switching power supply circuit according to the above configuration Q4, the sense result holding time is a time period equal to the reciprocal of the first frequency (t REF ) or more (hereinafter referred to as configuration Q5).

[0239] In a switching power supply circuit according to any of the above configurations Q1 to Q5, the current information generating circuit may be configured to generate current information of the coil by performing the first current sensing operation in each period having a length equal to the reciprocal of the first frequency when the switching frequency is set to the first frequency (hereinafter referred to as configuration Q6).

[0240] In the switching power supply circuit according to the above configuration Q6, the switching control circuit calculates a comparison voltage (V C a comparison voltage generating circuit (11 to 14) configured to generate a comparison voltage that changes monotonically from an initial level to a predetermined direction at a period that is the reciprocal of the first frequency; and a ramp voltage generating circuit (16) configured to generate a ramp voltage that changes monotonically from an initial level to a predetermined direction at a period that is the reciprocal of the first frequency, and in the switching operation, after the high-side transistor is turned on, a reset signal (S PWM a down edge of the reset signal, and turns off the high-side transistor and turns on the low-side transistor based on the issuance of the reset signal. In a state where the switching frequency is set to the first frequency, after the high-side transistor is turned on, a specified time (t MAX_ON ) has elapsed, the switching frequency may be switched from the first frequency to the second frequency (hereinafter referred to as configuration Q7).

[0241] This makes it possible to increase the maximum duty of the output stage circuit when the input voltage temporarily drops, for example, thereby making it easier to maintain the output voltage at a desired value.

[0242] In the switching power supply circuit according to the above-described configuration Q7, the switching control circuit may be configured to, after switching the switching frequency from the first frequency to the second frequency, return the switching frequency from the second frequency to the first frequency when the reset signal is issued before the specified time has elapsed since the turn-on timing of the high-side transistor (hereinafter referred to as configuration Q8).

[0243] This allows the switching frequency to return to the first frequency, for example, when the input voltage rises after a drop in the input voltage.

[0244] A switching power supply device according to one aspect of the present disclosure has a configuration (hereinafter referred to as configuration Q9) including a switching power supply circuit according to any one of the above configurations Q1 to Q8, and a rectifying and smoothing circuit configured to generate the output voltage by rectifying and smoothing the switching voltage.

[0245] 1 Switching power supply unit 2, 2A, 2B, 2C Power supply IC 3 Main control block L1 Coil C1 Output capacitor C2 Boot capacitor R1, R2 Resistor D1 Rectifier element V IN Input voltage V OUT Output voltage V FB Feedback voltage V SW Switching voltage IN Input terminal GND Ground terminal OUT Output terminal FB Feedback terminal BOOT Boot terminal OS Output monitoring terminal MM Output stage circuit M1 High-side transistor M2 Low-side transistor 11 Error amplifier 12 Phase compensation circuit 13 Differential amplifier 14 Phase compensation circuit 15 Clock generation circuit 16 Ramp voltage generation circuit 17 Comparator 18 Logic circuit 19 Driver 30, 30C, 30m Current information generation circuit 31 Sense resistor 32 S / H circuit 33 Amplification circuit 34 Pseudo current generation circuit 35 Adder IL Coil current V ISNS Voltage (detection current information) V IPS Voltage (pseudo current information) V ILVoltage (coil current information) V ERR Error voltage V C Contrast Voltage

Claims

1. 1. A switching power supply circuit for use in a switching power supply device for generating an output voltage by switching an input voltage, an output stage circuit having a high-side transistor and a low-side transistor connected in series between an input terminal receiving the input voltage and a ground terminal; a switching control circuit configured to perform a switching operation of alternately turning on and off the high-side transistor and the low-side transistor; a current information generating circuit configured to perform a current sensing operation to detect a current flowing through the low-side transistor during an on-period of the low-side transistor; a connection node between the high-side transistor and the low-side transistor is connected to a rectifying and smoothing circuit including a coil and an output capacitor, and a switching voltage generated at the connection node by the switching operation is rectified and smoothed by the rectifying and smoothing circuit to generate the output voltage; The switching control circuit performs the switching operation based on voltage information corresponding to the output voltage and current information of the coil generated through the current sensing operation, the switching control circuit is capable of setting a switching frequency in the switching operation to a first frequency or a second frequency lower than the first frequency, When the switching frequency is set to the second frequency, the current information generating circuit generates current information of the coil by adding pseudo current information based on the input voltage and the output voltage to detected current information by the most recent current sensing operation during a part of a period from when the most recent current sensing operation is performed to when the next current sensing operation is performed. , Circuits for switching power supplies.

2. The current information generating circuit generates the pseudo current information based on the input voltage, the output voltage, and the inductance of the coil.

2. The switching power supply circuit according to claim 1.

3. The current information generating circuit generates the pseudo current information based on the input voltage, the output voltage, the inductance of the coil, and a time that is the reciprocal of the first frequency.

3. The switching power supply circuit according to claim 2.

4. The current information generating circuit, during a period in which the switching frequency is set to the second frequency, until a predetermined time has elapsed since the high-side transistor was turned on, the detected current information obtained by the most recent current sensing operation is generated as current information of the coil; After the predetermined time has elapsed since the high-side transistor was turned on, until the next current sensing operation is performed, a sum of the detected current information and the pseudo current information by the most recent current sensing operation is generated as current information of the coil.

2. The switching power supply circuit according to claim 1.

5. When the switching frequency is switched from the first frequency to the second frequency, the current information generating circuit sets a value of the pseudo current information immediately after the switching to be larger than values ​​of the pseudo current information thereafter.

2. The switching power supply circuit according to claim 1.

6. When the switching frequency is set to the first frequency, the current information generating circuit performs the current sensing operation in each period having a length equal to the reciprocal of the first frequency, and generates the detected current information by the current sensing operation as current information of the coil.

6. A switching power supply circuit according to claim 1.

7. The switching control circuit includes: A comparison voltage generating circuit configured to generate a comparison voltage based on voltage information corresponding to the output voltage and current information of the coil; a ramp voltage generating circuit configured to generate a ramp voltage that changes monotonically from an initial level to a predetermined direction at a period that is the reciprocal of the first frequency; in the switching operation, after turning on the high-side transistor, a reset signal is issued in response to a change in a level relationship between the comparison voltage and the ramp voltage from a first relationship to a second relationship, and the high-side transistor is turned off and the low-side transistor is turned on based on the issuance of the reset signal; When the reset signal is not issued until a specified time shorter than the reciprocal of the first frequency has elapsed after the high-side transistor is turned on in a state in which the switching frequency is set to the first frequency, the switching frequency is switched from the first frequency to the second frequency.

7. The switching power supply circuit according to claim 6.

8. When the reset signal is issued before the specified time has elapsed from a turn-on timing of the high-side transistor after the switching frequency is switched from the first frequency to the second frequency, the switching control circuit returns the switching frequency from the second frequency to the first frequency.

8. The switching power supply circuit according to claim 7.

9. A switching power supply circuit according to any one of claims 1 to 5; a rectifying and smoothing circuit configured to rectify and smooth the switching voltage to generate the output voltage; , switching power supply.

10. 1. A switching power supply circuit for use in a switching power supply device for generating an output voltage by switching an input voltage, an output stage circuit having a high-side transistor and a low-side transistor connected in series between an input terminal receiving the input voltage and a ground terminal; a switching control circuit configured to perform a switching operation of alternately turning on and off the high-side transistor and the low-side transistor; a current information generating circuit configured to perform a first current sensing operation of detecting a current flowing through the low-side transistor during an on-period of the low-side transistor, or a second current sensing operation of detecting a current flowing through the high-side transistor during an on-period of the high-side transistor, a connection node between the high-side transistor and the low-side transistor is connected to a rectifying and smoothing circuit including a coil and an output capacitor, and a switching voltage generated at the connection node by the switching operation is rectified and smoothed by the rectifying and smoothing circuit to generate the output voltage; the switching control circuit performs the switching operation based on voltage information corresponding to the output voltage and current information of the coil, and is capable of setting a switching frequency in the switching operation to a first frequency or a second frequency lower than the first frequency; The current information generating circuit generates the current information of the coil by the first current sensing operation when the switching frequency is set to the first frequency, and generates the current information of the coil by using the first current sensing operation and the second current sensing operation in combination when the switching frequency is set to the second frequency. , Circuits for switching power supplies.

11. When the switching frequency is set to the second frequency, the current information generating circuit generates current information of the coil during an on-period of the high-side transistor by performing the second current sensing operation during an on-period of the high-side transistor, and generates current information of the coil during an on-period of the low-side transistor by performing the first current sensing operation during an on-period of the low-side transistor.

11. The switching power supply circuit according to claim 10.

12. When the switching frequency is set to the second frequency, the current information generating circuit In the second current sensing operation, a current flowing through the high-side transistor is continuously detected during a part of an on-period of the high-side transistor to update current information of the coil; Thereafter, when the high-side transistor is turned off and the low-side transistor is turned on, the first current sensing operation is performed to detect the current flowing through the low-side transistor at a sampling timing set within the on-period of the low-side transistor, thereby generating current information of the coil during the on-period of the low-side transistor.

12. The switching power supply circuit according to claim 11.

13. When the switching frequency is set to the second frequency, From when the high-side transistor is turned on until a sense result hold time has elapsed, the current information of the coil represents a current value detected by the previous first current sense operation, After the sense result holding time has elapsed since the high-side transistor was turned on, until the high-side transistor is turned off, the current information of the coil represents a current detection value by the second current sensing operation, Thereafter, when the current first current sensing operation is performed at the sampling timing, the coil current information is updated to information representing the detected current value by the current first current sensing operation.

13. The switching power supply circuit according to claim 12.

14. The sense result retention time is equal to or longer than the reciprocal of the first frequency.

14. The switching power supply circuit according to claim 13.

15. The current information generating circuit generates current information of the coil by performing the first current sensing operation in each period having a length equal to the reciprocal of the first frequency when the switching frequency is set to the first frequency.

15. A switching power supply circuit according to claim 10.

16. The switching control circuit includes: A comparison voltage generating circuit configured to generate a comparison voltage based on voltage information corresponding to the output voltage and current information of the coil; a ramp voltage generating circuit configured to generate a ramp voltage that changes monotonically from an initial level to a predetermined direction at a period that is the reciprocal of the first frequency; in the switching operation, after turning on the high-side transistor, a reset signal is issued in response to a change in a level relationship between the comparison voltage and the ramp voltage from a first relationship to a second relationship, and the high-side transistor is turned off and the low-side transistor is turned on based on the issuance of the reset signal; When the reset signal is not issued until a specified time shorter than the reciprocal of the first frequency has elapsed after the high-side transistor is turned on in a state in which the switching frequency is set to the first frequency, the switching frequency is switched from the first frequency to the second frequency.

16. The switching power supply circuit according to claim 15.

17. When the reset signal is issued before the specified time has elapsed from a turn-on timing of the high-side transistor after the switching frequency is switched from the first frequency to the second frequency, the switching control circuit returns the switching frequency from the second frequency to the first frequency.

17. The switching power supply circuit according to claim 16.

18. A switching power supply circuit according to any one of claims 10 to 14; a rectifying and smoothing circuit configured to rectify and smooth the switching voltage to generate the output voltage; , switching power supply.