Semiconductor device

Abstract

This semiconductor device is provided with: a first conductive layer; a first semiconductor element; a second conductive layer; a second semiconductor element; a first terminal; and a sealing resin that covers the first semiconductor element and the second semiconductor element. The first semiconductor element has a first electrode and a second electrode that are located on sides opposite to each other in a first direction. The second semiconductor element 22 has a third electrode and a fourth electrode that are located on sides opposite to each other in the first direction. The first electrode is conductively bonded to the first conductive layer. The fourth electrode is conductively bonded to the second conductive layer. The first terminal is conductively bonded to the second electrode and the third electrode. The polarity of the second electrode and the polarity of the third electrode are different from each other. The first terminal is exposed from the sealing resin.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, semiconductor devices equipped with semiconductor elements having a switching function have been widely known. Such semiconductor devices are mainly used for power conversion. Patent Document 1 discloses an example of such a semiconductor device.

[0003] In the semiconductor device disclosed in Patent Document 1, a semiconductor element mounted on the semiconductor device has a source electrode and a drain electrode positioned on opposite sides. An upper plate electrode is conductively connected to the source electrode. A drain electrode pattern is conductively connected to the drain electrode. The semiconductor element is sandwiched between the upper plate electrode and the drain electrode pattern. This configuration makes it possible to reduce the parasitic inductance of the semiconductor device while miniaturizing the semiconductor device. However, the area of ​​the source electrode is generally smaller than the area of ​​the drain electrode. As a result, the semiconductor device has a problem in that the amount of heat dissipated from the source electrode to the upper plate electrode is smaller than the amount of heat dissipated from the drain electrode to the drain electrode pattern, and the heat dissipation of the semiconductor element is not fully realized.

[0004] JP 2013-258387 A

[0005] An object of the present disclosure is to provide a semiconductor device that is improved over conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that can reduce parasitic inductance and improve heat dissipation.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes: a first semiconductor element having a first conductive layer, a first electrode and a second electrode positioned opposite each other in a first direction, the first electrode being conductively bonded to the first conductive layer; a second conductive layer spaced from the first conductive layer in a direction perpendicular to the first direction; a second semiconductor element having a third electrode and a fourth electrode positioned opposite each other in the first direction, the fourth electrode being conductively bonded to the second conductive layer; a first terminal conductively bonded to the second electrode and the third electrode; and a sealing resin covering the first semiconductor element and the second semiconductor element. The polarity of the second electrode and the polarity of the third electrode are different from each other. The first terminal is exposed from the sealing resin.

[0007] According to the above configuration, in the semiconductor device, it is possible to reduce the parasitic inductance and improve the heat dissipation performance.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 3 is a bottom view corresponding to FIG. 2, showing a see-through view of the sealing resin. FIG. 4 is a bottom view corresponding to FIG. 3, showing a further see-through view of the first terminal. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 3. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 3. FIG. 9 is a partial enlarged view of FIG. 4, showing a first semiconductor element and its vicinity, and showing the first semiconductor element in a see-through view. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 9. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 9. FIG. 12 is a partial enlarged view of FIG. 4, showing a second semiconductor element and its vicinity. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12. FIG. 14 is a bottom view of a semiconductor device according to a second embodiment of the present disclosure, showing the sealing resin in a see-through manner. FIG. 15 is a bottom view corresponding to FIG. 14, showing the first terminal in a further see-through manner. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 14. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 14. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 14. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 14. FIG. 20 is a bottom view of a first semiconductor element included in the semiconductor device shown in FIG. 14. FIG. 21 is a plan view of the first semiconductor element shown in FIG. 20. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 20. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 20. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 20. FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. 20. FIG. 26 is a partially enlarged view of FIG. 15, showing the first semiconductor element and its vicinity. FIG. 27 is a cross-sectional view taken along line XXVII-XXVII in FIG. 26. FIG. 28 is a bottom view of a second semiconductor element included in the semiconductor device shown in FIG. 14. FIG. 29 is a plan view of the second semiconductor element shown in FIG. 28. FIG. 30 is a cross-sectional view taken along line XXX-XXX in FIG. 28. FIG. 31 is a cross-sectional view taken along line XXXI-XXXI in FIG. 28. FIG. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG. 28.Fig. 33 is a partially enlarged view of Fig. 15, showing the second semiconductor element and its vicinity. Fig. 34 is a cross-sectional view taken along line XXXIV-XXXIV in Fig. 33. Fig. 35 is a bottom view of the semiconductor device according to the third embodiment of the present disclosure, showing the sealing resin through the view. Fig. 36 is a cross-sectional view taken along line XXXVI-XXXVI in Fig. 35. Fig. 37 is a cross-sectional view taken along line XXXVII-XXXVII in Fig. 35.

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0011] 1 to 13, a semiconductor device A10 according to a first embodiment of the present disclosure will be described. The semiconductor device A10 includes an insulating layer 11, a first conductive layer 12, a second conductive layer 13, a heat dissipation layer 16, a plurality of first semiconductor elements 21, a plurality of second semiconductor elements 22, a plurality of first spacers 31, a plurality of second spacers 32, a first terminal 41, a second terminal 42, a third terminal 43, and a sealing resin 60. The semiconductor device A10 further includes a first gate conductive layer 141, a second gate conductive layer 142, a first detection conductive layer 151, a second detection conductive layer 152, a first gate terminal 441, a second gate terminal 442, a first detection terminal 451, and a second detection terminal 452.

[0012] Here, for ease of understanding, FIG. 3 shows the sealing resin 60 in a see-through manner. For ease of understanding, FIG. 4 shows the first terminal 41 in a see-through manner compared to FIG. 3. For ease of understanding, FIG. 9 shows the first semiconductor element 21 in a see-through manner compared to FIG. 4. In FIGS. 3 and 4, the outer shape of the sealing resin 60 seen through is shown by an imaginary line (two-dot chain line). In FIG. 4, the outer shape of the first terminal 41 seen through is shown by an imaginary line. In FIG. 9, the first semiconductor element 21 seen through is shown by an imaginary line. In FIG. 3, lines VI-VI and VII-VII are respectively shown by dashed dotted lines.

[0013] In the description of the semiconductor device A10, for convenience, the normal direction to a first main surface 12A of a first conductive layer 12 (described later) will be referred to as the "first direction z." One direction perpendicular to the first direction z will be referred to as the "second direction x." A direction perpendicular to both the first direction z and the second direction x will be referred to as the "third direction y."

[0014] The semiconductor device A10 converts a DC power supply voltage applied to the second terminal 42 and the third terminal 43 into AC power using the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22. The converted AC power is input to a power supply target such as a motor from the first terminal 41. The semiconductor device A10 constitutes part of a power conversion circuit such as an inverter.

[0015] As shown in FIGS. 5 and 6 , the insulating layer 11 supports the first conductive layer 12, the second conductive layer 13, the first gate conductive layer 141, the second gate conductive layer 142, the first detection conductive layer 151, the second detection conductive layer 152, and the heat dissipation layer 16. The insulating layer 11 is made of a material with relatively high thermal conductivity. For example, the insulating layer 11 is made of ceramics containing aluminum nitride (AlN). The periphery of the insulating layer 11 is sandwiched between sealing resin 60 in the first direction z. The thickness of the insulating layer 11 is smaller than the thicknesses of the first conductive layer 12, the second conductive layer 13, and the heat dissipation layer 16. Therefore, in the semiconductor device A10, the thicknesses of the first conductive layer 12, the second conductive layer 13, and the heat dissipation layer 16 are greater than the thickness of the insulating layer 11.

[0016] As shown in FIGS. 3 , 4 , 5 , 6 , and 8 , the first conductive layer 12 is bonded to one side of the insulating layer 11 in the first direction z. The first conductive layer 12 carries a plurality of first semiconductor elements 21 and a plurality of first spacers 31. The first conductive layer 12 has a rectangular shape with its long sides extending in the third direction y. As viewed in the first direction z, the first conductive layer 12 is surrounded by the periphery of the insulating layer 11. The first conductive layer 12 contains copper (Cu). The first conductive layer 12 has a first main surface 12A facing the first direction z. The plurality of first semiconductor elements 21 and the plurality of first spacers 31 face the first main surface 12A.

[0017] As shown in FIGS. 3, 4, and 5 to 7, the second conductive layer 13 is located on the same side as the first conductive layer 12 in the first direction z and is bonded to the insulating layer 11. The second conductive layer 13 carries a plurality of second semiconductor elements 22. The second conductive layer 13 is spaced apart from the first conductive layer 12 in the second direction x. The second conductive layer 13 has a rectangular shape with its long sides extending in the third direction y. As viewed in the first direction z, the second conductive layer 13 is surrounded by the periphery of the insulating layer 11. The second conductive layer 13 contains copper. The second conductive layer 13 has a second main surface 13A that faces the same side as the first main surface 12A of the first conductive layer 12 in the first direction z. The plurality of second semiconductor elements 22 face the second main surface 13A.

[0018] As shown in FIGS. 5 to 8 , the heat dissipation layer 16 is located on the opposite side of the insulating layer 11 from the first conductive layer 12 and the second conductive layer 13 and is bonded to the insulating layer 11. The heat dissipation layer 16 is exposed from the sealing resin 60. The volume of the heat dissipation layer 16 is greater than the sum of the volumes of the first conductive layer 12 and the second conductive layer 13. As shown in FIG. 1 , the heat dissipation layer 16 is surrounded by the periphery of the insulating layer 11 when viewed in the first direction z. The heat dissipation layer 16 overlaps the entire first conductive layer 12 and the entire second conductive layer 13 when viewed in the first direction z. The area of ​​the heat dissipation layer 16 is greater than the sum of the area of ​​the first conductive layer 12 and the area of ​​the second conductive layer 13 when viewed in the first direction z. The composition of the heat dissipation layer 16 includes copper. When the semiconductor device A10 is in use, a heat sink (not shown) is bonded to the heat dissipation layer 16.

[0019] As shown in FIGS. 5 and 8 , the multiple first semiconductor elements 21 are bonded to multiple first spacers 31. All of the multiple first semiconductor elements 21 are identical elements. The multiple first semiconductor elements 21 are, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, the multiple first semiconductor elements 21 may be field-effect transistors including metal-insulator-semiconductor field-effect transistors (MISFETs) or bipolar transistors such as insulated gate bipolar transistors (IGBTs). In the description of the semiconductor device A10, the multiple first semiconductor elements 21 are n-channel MOSFETs with a vertical structure. The multiple first semiconductor elements 21 include a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC). The multiple first semiconductor elements 21 are arranged along the third direction y.

[0020] As shown in FIGS. 10 and 11, the plurality of first semiconductor elements 21 have a first electrode 211 , a second electrode 212 and a first gate electrode 213 .

[0021] 10 and 11 , the first electrode 211 faces the first main surface 12A of the first conductive layer 12. A current corresponding to the power converted by the first semiconductor element 21 flows through the first electrode 211. In other words, the first electrode 211 corresponds to the source electrode of the first semiconductor element 21.

[0022] 10 and 11 , the second electrode 212 is located on the side opposite to the side facing the first main surface 12A of the first conductive layer 12 in the first direction z. A current corresponding to the power before being converted by the first semiconductor element 21 flows through the second electrode 212. In other words, the second electrode 212 corresponds to the drain electrode of the first semiconductor element 21.

[0023] 10 and 11 , the first gate electrode 213 faces the first main surface 12A of the first conductive layer 12. Therefore, the first gate electrode 213 is located on the same side as the first electrode 211 in the first direction z. A gate voltage for driving the first semiconductor element 21 is applied to the first gate electrode 213. As shown in FIG. 9 , the area of ​​the first gate electrode 213 is smaller than the area of ​​the first electrode 211 when viewed in the first direction z.

[0024] 5 to 7, the multiple second semiconductor elements 22 are bonded to the second main surface 13A of the second conductive layer 13. The multiple second semiconductor elements 22 are the same elements as the multiple first semiconductor elements 21. Therefore, the multiple second semiconductor elements 22 are n-channel MOSFETs with a vertical structure. The multiple second semiconductor elements 22 are arranged along the third direction y.

[0025] As shown in FIG. 13 , the plurality of second semiconductor elements 22 have a third electrode 221 , a fourth electrode 222 and a second gate electrode 223 .

[0026] 13 , the third electrode 221 is located on the side opposite to the side facing the second main surface 13A of the second conductive layer 13 in the first direction z. A current corresponding to the power converted by the second semiconductor element 22 flows through the third electrode 221. In other words, the third electrode 221 corresponds to the source electrode of the second semiconductor element 22.

[0027] 13 , the fourth electrode 222 faces the second main surface 13A of the second conductive layer 13. A current corresponding to the power before being converted by the second semiconductor element 22 flows through the fourth electrode 222. In other words, the fourth electrode 222 corresponds to the drain electrode of the second semiconductor element 22. The fourth electrode 222 is conductively bonded to the second main surface 13A via a conductive bonding layer 29. As a result, the fourth electrodes 222 of the multiple second semiconductor elements 22 are electrically connected to the second conductive layer 13. The conductive bonding layer 29 is, for example, solder. Alternatively, the conductive bonding layer 29 may be a sintered metal containing silver (Ag) or the like.

[0028] 13 , the second gate electrode 223 is located on the opposite side of the second conductive layer 13 from the side facing the second main surface 13A in the first direction z. Therefore, the second gate electrode 223 is located on the same side as the third electrode 221 in the first direction z. A gate voltage for driving the second semiconductor element 22 is applied to the second gate electrode 223. As shown in FIG. 12 , the area of ​​the second gate electrode 223 is smaller than the area of ​​the third electrode 221 when viewed in the first direction z.

[0029] In the semiconductor device A10, the multiple first semiconductor elements 21 form part of an upper arm circuit, and the multiple second semiconductor elements 22 form part of a lower arm circuit. Furthermore, in the semiconductor device A10, the configuration of the multiple first semiconductor elements 21 is equivalent to the configuration of the multiple second semiconductor elements 22 flipped around a direction perpendicular to the first direction z. Therefore, the polarity of the first electrode 211 of each of the multiple first semiconductor elements 21 is different from the polarity of the fourth electrode 222 of each of the multiple second semiconductor elements 22. Additionally, the second electrode 212 of each of the multiple first semiconductor elements 21 is different from the polarity of the third electrode 221 of each of the multiple second semiconductor elements 22.

[0030] As shown in FIG. 8 , the multiple first spacers 31 are conductively bonded to the first main surface 12A of the first conductive layer 12. As shown in FIGS. 8 , 10 , and 11 , the first electrodes 211 of the multiple first semiconductor elements 21 are individually conductively bonded to the multiple first spacers 31. Therefore, each of the multiple first spacers 31 conductively bonds the first conductive layer 12 to one of the first electrodes 211 of the multiple first semiconductor elements 21. The first electrodes 211 of the multiple first semiconductor elements 21 are individually electrically connected to the multiple first spacers 31 and are conductively bonded to the first conductive layer 12 via one of the multiple first spacers 31. The multiple first spacers 31 are arranged along the third direction y. The multiple first spacers 31 are located between the first main surface 12A and the multiple first semiconductor elements 21. As shown in FIGS. 10 and 11 , the multiple first spacers 31 include a first portion 311 and a second portion 312. 9, the plurality of first spacers 31 are rectangular when viewed in the first direction z. Alternatively, the plurality of first spacers 31 may be circular when viewed in the first direction z. The composition of the plurality of first spacers 31 includes copper.

[0031] As shown in FIGS. 9 to 11 , the first portion 311 has a second surface 311A, a third surface 311B, and a fourth surface 311C. The second surface 311A ​​faces the first main surface 12A of the first conductive layer 12. The second surface 311A ​​is conductively bonded to the first main surface 12A via a conductive bonding layer 29. Alternatively, the second surface 311A ​​may be conductively bonded to the first main surface 12A by solid-state diffusion. The third surface 311B faces the opposite side from the second surface 311A ​​in the first direction z. As viewed in the first direction z, the first semiconductor element 21 is surrounded by the periphery of the third surface 311B. The fourth surface 311C faces a direction perpendicular to the first direction z. In the semiconductor device A10, the fourth surface 311C includes multiple regions.

[0032] 9 to 11 , the first portion 311 has a first recess 311D recessed from the third surface 311B and the fourth surface 311C. When viewed in the first direction z, the first gate electrode 213 of the first semiconductor element 21 overlaps the first recess 311D.

[0033] 10 and 11 , the second portion 312 is located between the first portion 311 and the first electrode 211 of the first semiconductor element 21. The second portion 312 is connected to the first portion 311 at the third surface 311B. As shown in Fig. 9 , the second portion 312 is surrounded by the periphery of the first semiconductor element 21 as viewed in the first direction z. The second portion 312 is spaced apart from the first gate electrode 213 of the first semiconductor element 21 as viewed in the first direction z.

[0034] The dimension t1 of the first portion 311 in the first direction z is larger than the dimension t2 in the thickness direction of the second portion 312. The dimension t1 is 3 to 30 times the dimension t2.

[0035] As shown in FIGS. 9 to 11 , the second portion 312 has a first surface 312A. The first surface 312A faces the first semiconductor element 21. As viewed in the first direction z, the first surface 312A is spaced apart from the first gate electrode 213 of the first semiconductor element 21. As viewed in the first direction z, the first surface 312A is surrounded by the periphery of the second surface 311A ​​of the first portion 311. In the semiconductor device A10, the area of ​​the first surface 312A is smaller than the area of ​​the first electrode 211 of the first semiconductor element 21. The first electrode 211 of each of the multiple first semiconductor elements 21 is individually conductively bonded to the first surface 312A of each of the multiple first spacers 31 by solid-state diffusion. Alternatively, the first electrode 211 of each of the multiple first semiconductor elements 21 may be individually conductively bonded to the first surface 312A of each of the multiple first spacers 31 via a conductive bonding layer 29.

[0036] 9 to 11 , the second portion 312 is provided with a second recess 312B that is recessed in a direction perpendicular to the first direction z. The second recess 312B penetrates the second portion 312 in the first direction z and is connected to the first recess 311D of the first portion 311. When viewed in the first direction z, the second recess 312B overlaps the first recess 311D and the first gate electrode 213 of the first semiconductor element 21.

[0037] As shown in FIGS. 7 and 13 , the multiple second spacers 32 are individually conductively bonded to the third electrodes 221 of the multiple second semiconductor elements 22. The multiple second spacers 32 are arranged along the third direction y. The multiple second spacers 32 are positioned between the multiple second semiconductor elements 22 and the first terminals 41. As shown in FIG. 12 , each of the multiple second spacers 32 is rectangular when viewed in the first direction z. Alternatively, each of the multiple second spacers 32 may be circular when viewed in the first direction z. When viewed in the first direction z, the area of ​​each of the multiple second spacers 32 is smaller than the area of ​​the third electrode 221. The composition of the multiple second spacers 32 includes copper. Each of the multiple second spacers 32 is individually conductively bonded to the third electrode 221 of the multiple second semiconductor elements 22 by solid-state diffusion. Alternatively, each of the plurality of second spacers 32 may be individually conductively bonded to the third electrodes 221 of the plurality of second semiconductor elements 22 via the conductive bonding layer 29 .

[0038] 3 to 6 , the first gate conductive layer 141 is located on the same side as the first conductive layer 12 in the first direction z, and is joined to the insulating layer 11. The first gate conductive layer 141 is located on the opposite side of the second conductive layer 13 from the first conductive layer 12 in the second direction x. The first gate conductive layer 141 extends along the third direction y. The composition of the first gate conductive layer 141 includes copper.

[0039] As shown in FIG. 9 , each of the multiple first gate wirings 51 is conductively joined to the first gate electrode 213 of any one of the multiple first semiconductor elements 21 and the first gate conductive layer 141. As a result, the first gate electrodes 213 of the multiple first semiconductor elements 21 are electrically connected to the first gate conductive layer 141. The multiple first gate wirings 51 are metal leads. The multiple first gate wirings 51 contain copper. As shown in FIG. 3 , the multiple first gate wirings 51 overlap the insulating layer 11 when viewed in the first direction z. As shown in FIG. 5 , the multiple first gate wirings 51 overlap the heat dissipation layer 16 when viewed in the first direction z.

[0040] 3 to 6 , the second gate conductive layer 142 is located on the same side as the second conductive layer 13 in the first direction z, and is joined to the insulating layer 11. The second gate conductive layer 142 is located on the opposite side to the first gate conductive layer 141 in the second direction x, with the first conductive layer 12 and the second conductive layer 13 as the reference. The second gate conductive layer 142 extends along the third direction y. The composition of the second gate conductive layer 142 includes copper.

[0041] As shown in FIG. 12 , each of the multiple second gate wirings 53 is conductively bonded to the second gate electrode 223 of one of the multiple second semiconductor elements 22 and the second gate conductive layer 142. As a result, the second gate electrodes 223 of the multiple second semiconductor elements 22 are electrically connected to the second gate conductive layer 142. The multiple second gate wirings 53 are wires. The composition of the multiple second gate wirings 53 includes gold (Au). Alternatively, the composition of the multiple second gate wirings 53 may include copper or aluminum. As shown in FIG. 3 , the multiple second gate wirings 53 overlap the insulating layer 11 when viewed in the first direction z. As shown in FIG. 5 , the multiple second gate wirings 53 overlap the heat dissipation layer 16 when viewed in the first direction z.

[0042] 3 , 4 , 5 , and 6 , the first detecting conductive layer 151 is located on the same side as the second conductive layer 13 in the first direction z, and is bonded to the insulating layer 11. The first detecting conductive layer 151 is located next to the first gate conductive layer 141 in the second direction x. The first detecting conductive layer 151 extends along the third direction y. The composition of the first detecting conductive layer 151 includes copper.

[0043] As shown in FIG. 9 , each of the multiple first detection wirings 52 is conductively bonded to the third surface 311B of one of the multiple first spacers 31 and the first detection conductive layer 151. As a result, the first electrodes 211 of the multiple first semiconductor elements 21 are electrically connected to the first detection conductive layer 151. The multiple second gate wirings 53 are wires. The composition of the multiple second gate wirings 53 includes gold. Alternatively, the composition of the multiple second gate wirings 53 may include copper or aluminum. As shown in FIG. 3 , the multiple first detection wirings 52 overlap the insulating layer 11 when viewed in the first direction z. As shown in FIG. 6 , the multiple first detection wirings 52 overlap the heat dissipation layer 16 when viewed in the first direction z.

[0044] 3 , 4 , 5 , and 6 , the second detecting conductive layer 152 is located on the same side as the second conductive layer 13 in the first direction z, and is bonded to the insulating layer 11. The second detecting conductive layer 152 is located next to the second gate conductive layer 142 in the second direction x. The second detecting conductive layer 152 extends along the third direction y. The composition of the second detecting conductive layer 152 includes copper.

[0045] As shown in FIG. 12 , each of the multiple second detection wirings 54 is conductively bonded to the third electrode 221 of one of the multiple second semiconductor elements 22 and the second detection conductive layer 152. As a result, the third electrodes 221 of the multiple second semiconductor elements 22 are electrically connected to the second detection conductive layer 152. The multiple second detection wirings 54 are wires. The composition of the multiple second detection wirings 54 includes gold. Alternatively, the composition of the multiple second detection wirings 54 may include copper or aluminum. As shown in FIG. 3 , the multiple second detection wirings 54 overlap the insulating layer 11 when viewed in the first direction z. As shown in FIG. 6 , the multiple second detection wirings 54 overlap the heat dissipation layer 16 when viewed in the first direction z.

[0046] As shown in FIGS. 5 to 8 , the first terminal 41 is located on the opposite side of the first conductive layer 12 and the second conductive layer 13 in the first direction z with respect to the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22. The first terminal 41 is conductively joined to the second electrode 212 of each of the plurality of first semiconductor elements 21 and the third electrode 221 of each of the plurality of second semiconductor elements 22. The first terminal 41 is exposed from the sealing resin 60. The first terminal 41 is a metal lead made of a material containing copper or a copper alloy. AC power converted by the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22 is output from the first terminal 41.

[0047] 5 to 8 , the first terminal 41 has a bonding surface 41A and a mounting surface 41B that face opposite each other in the first direction z. The bonding surface 41A is conductively bonded to the second electrodes 212 of the multiple first semiconductor elements 21 via the conductive bonding layer 29. Furthermore, the bonding surface 41A is conductively bonded to the third electrodes 221 of the multiple second semiconductor elements 22 via the conductive bonding layer 29 and multiple second spacers 32. The mounting surface 41B faces the opposite side to the bonding surface 41A in the first direction z. The mounting surface 41B is exposed from the sealing resin 60. In the semiconductor device A10, the area of ​​the mounting surface 41B is equal to the area of ​​the bonding surface 41A.

[0048] As shown in FIGS. 2 to 4 , the second terminal 42 is located on one side in the third direction y with respect to the insulating layer 11. As shown in FIG. 8 , the second terminal 42 is conductively bonded to the first conductive layer 12. As a result, the second terminal 42 is electrically connected to the first electrodes 211 of the first semiconductor elements 21 via the first conductive layer 12 and the first spacers 31. The second terminal 42 is a metal lead made of a material containing copper or a copper alloy. The second terminal 42 is an N terminal (negative electrode) to which a DC power supply voltage to be converted is applied. The second terminal 42 includes a portion exposed from the sealing resin 60. As shown in FIG. 8 , this portion is bent in a gull-wing shape in the first direction z toward the side where the mounting surface 41B of the first terminal 41 is located.

[0049] As shown in FIGS. 2 to 4 , the third terminal 43 is located on the same side as the second terminal 42 in the third direction y with respect to the insulating layer 11. The third terminal 43 is spaced apart from the second terminal 42 in the second direction x. As shown in FIG. 7 , the third terminal 43 is conductively bonded to the second conductive layer 13. This allows the third terminal 43 to be electrically connected to the fourth electrodes 222 of the multiple second semiconductor elements 22 via the second conductive layer 13. The third terminal 43 is a metal lead made of a material containing copper or a copper alloy. The third terminal 43 is a P terminal (positive electrode) to which a DC power supply voltage to be converted is applied. The third terminal 43 includes a portion exposed from the sealing resin 60. As shown in FIG. 7 , this portion is bent in a gull-wing shape toward the side where the mounting surface 41B of the first terminal 41 is located in the first direction z.

[0050] As shown in FIGS. 2 to 4 , the first gate terminal 441 is located on the same side as the second terminal 42 with respect to the insulating layer 11 in the third direction y. The first gate terminal 441 is located on the opposite side of the third terminal 43 with respect to the second terminal 42 in the second direction x. The first gate terminal 441 is conductively bonded to the first gate conductive layer 141. This allows the first gate terminal 441 to be electrically connected to the first gate electrodes 213 of the multiple first semiconductor elements 21 via the first gate conductive layer 141 and the multiple first gate wirings 51. The first gate terminal 441 is a metal lead made of a material containing copper or a copper alloy. A gate voltage for driving the multiple first semiconductor elements 21 is applied to the first gate terminal 441. The first gate terminal 441 includes a portion exposed from the sealing resin 60. This portion is bent in a gull-wing shape toward the side where the mounting surface 41B of the first terminal 41 is located in the first direction z.

[0051] As shown in FIGS. 2 to 4 , the second gate terminal 442 is located on the same side as the third terminal 43 in the third direction y with respect to the insulating layer 11. The second gate terminal 442 is located on the opposite side of the second terminal 42 with respect to the third terminal 43 in the second direction x. The second gate terminal 442 is conductively bonded to the second gate conductive layer 142. This allows the second gate terminal 442 to be electrically connected to the second gate electrodes 223 of the second semiconductor elements 22 via the second gate conductive layer 142 and the second gate wirings 53. The second gate terminal 442 is a metal lead made of a material containing copper or a copper alloy. A gate voltage for driving the second semiconductor elements 22 is applied to the second gate terminal 442. The second gate terminal 442 includes a portion exposed from the sealing resin 60. This portion is bent in a gull-wing shape toward the mounting surface 41B of the first terminal 41 in the first direction z.

[0052] As shown in FIGS. 2 to 4 , the first detection terminal 451 is located on the same side as the second terminal 42 in the third direction y with respect to the insulating layer 11. The first detection terminal 451 is located on the opposite side from the second terminal 42 with respect to the first gate terminal 441 in the second direction x. The first detection terminal 451 is conductively bonded to the first detection conductive layer 151. As a result, the first detection terminal 451 is electrically connected to the first electrodes 211 of the multiple first semiconductor elements 21 via the first detection conductive layer 151, the multiple first detection wirings 52, and the multiple first spacers 31. The first detection terminal 451 is a metal lead made of a material containing copper or a copper alloy. A voltage equipotential to the voltage applied to each of the first electrodes 211 of the multiple first semiconductor elements 21 is applied to the first detection terminal 451. The first detection terminal 451 includes a portion exposed from the sealing resin 60. This portion is bent in a gull-wing shape in the first direction z toward the side where the mounting surface 41B of the first terminal 41 is located.

[0053] As shown in FIGS. 2 to 4 , the second detection terminal 452 is located on the same side as the third terminal 43 in the third direction y with respect to the insulating layer 11. The second detection terminal 452 is located on the opposite side of the third terminal 43 with respect to the second gate terminal 442 in the second direction x. The second detection terminal 452 is conductively bonded to the second detection conductive layer 152. This allows the second detection terminal 452 to be electrically connected to the third electrodes 221 of the multiple second semiconductor elements 22 via the second detection conductive layer 152 and the multiple second detection wirings 54. The second detection terminal 452 is a metal lead made of a material containing copper or a copper alloy. A voltage equipotential to the voltage applied to each third electrode 221 of the multiple second semiconductor elements 22 is applied to the second detection terminal 452. The second detection terminal 452 includes a portion exposed from the sealing resin 60. This portion is bent in a gull-wing shape in the first direction z toward the side where the mounting surface 41B of the first terminal 41 is located.

[0054] 5 to 8 , the sealing resin 60 covers the plurality of first semiconductor elements 21 and the plurality of second semiconductor elements 22. The sealing resin 60 is an insulator. The sealing resin 60 is made of a material containing, for example, black epoxy resin. A portion of the sealing resin 60 is sandwiched between the insulating layer 11 and the first terminals 41 in the first direction z.

[0055] 1, 2, and 5 to 8, the sealing resin 60 has a top surface 61, a bottom surface 62, two first side surfaces 63, and two second side surfaces 64. The top surface 61 faces the opposite side to the first main surface 12A of the first conductive layer 12 in the first direction z. The heat dissipation layer 16 is exposed from the top surface 61. The bottom surface 62 faces the opposite side to the top surface 61 in the first direction z. The mounting surface 41B of the first terminal 41 is exposed from the bottom surface 62.

[0056] As shown in FIGS. 1, 2, 5 and 6, the two first side surfaces 63 are spaced apart from each other in the second direction x and are connected to the top surface 61 and the bottom surface 62.

[0057] As shown in FIGS. 1 , 2 , 7 , and 8 , the two second side surfaces 64 are spaced apart from each other in the third direction y and are connected to the top surface 61 and the bottom surface 62. The second terminal 42, the third terminal 43, the first gate terminal 441, the second gate terminal 442, the first detection terminal 451, and the second detection terminal 452 are exposed from one of the two second side surfaces 64. The first terminal 41 is exposed from the other of the two second side surfaces 64. When viewed in the first direction z, each of the first terminal 41, the second terminal 42, the third terminal 43, the first gate terminal 441, the second gate terminal 442, the first detection terminal 451, and the second detection terminal 452 extends in the first direction z from one of the two second side surfaces 64.

[0058] Next, the effects of the semiconductor device A10 will be described.

[0059] The semiconductor device A10 includes a first conductive layer 12, a first semiconductor element 21, a second conductive layer 13, a second semiconductor element 22, a first terminal 41, and a sealing resin 60. The first semiconductor element 21 has a first electrode 211 conductively bonded to the first conductive layer 12 and a second electrode 212 to which the first terminal 41 is conductively bonded. The second semiconductor element 22 has a third electrode 221 conductively bonded to the first terminal 41 and a fourth electrode 222 conductively bonded to the second conductive layer 13. The polarity of the second electrode 212 and the polarity of the third electrode 221 are opposite to each other. The first terminal 41 is exposed from the sealing resin 60. This configuration further shortens the length of the conductive path from the second electrode 212 to the third electrode 221. This reduces the parasitic inductance of the semiconductor device A10. Furthermore, with this configuration, heat generated from the first semiconductor element 21 and the second semiconductor element 22 is released to the outside via the first terminal 41. Therefore, with this configuration, in the semiconductor device A10, it is possible to improve the heat dissipation performance of the semiconductor device A10 while reducing the parasitic inductance of the semiconductor device A10.

[0060] The semiconductor device A10 further includes an insulating layer 11 and a heat dissipation layer 16. The heat dissipation layer 16 is located on the opposite side of the insulating layer 11 from the first conductive layer 12 and the second conductive layer 13. The heat dissipation layer 16 is exposed from the sealing resin 60. With this configuration, heat generated from the first semiconductor element 21 and the second semiconductor element 22 can be dissipated to the outside not only from the first terminal 41 but also from the heat dissipation layer 16.

[0061] When viewed in the first direction z, the heat dissipation layer 16 is surrounded by the periphery of the insulating layer 11. With this configuration, when the insulating layer 11 tries to fall off from the sealing resin 60, the periphery of the insulating layer 11 comes into contact with the sealing resin 60 in the first direction z, and therefore, the insulating layer 11 can be prevented from falling off.

[0062] As viewed in the first direction z, the heat dissipation layer 16 overlaps the entire first conductive layer 12 and the entire second conductive layer 13. As viewed in the first direction z, the area of ​​the heat dissipation layer 16 is larger than the sum of the area of ​​the first conductive layer 12 and the area of ​​the second conductive layer 13. With this configuration, heat conducted from the first conductive layer 12 and the second conductive layer 13 to the heat dissipation layer 16 via the insulating layer 11 is more likely to diffuse in a direction perpendicular to the first direction z. This reduces the thermal resistance of the heat dissipation layer 16 in the first direction z.

[0063] The thickness of each of the first conductive layer 12, the second conductive layer 13, and the heat dissipation layer 16 is greater than the thickness of the insulating layer 11. This configuration improves the heat diffusion efficiency in the direction perpendicular to the first direction z in each of the first conductive layer 12, the second conductive layer 13, and the heat dissipation layer 16. This further improves the heat dissipation performance of the semiconductor device A10.

[0064] In the semiconductor device A10, the first gate electrode 213 of the first semiconductor element 21 is located on the same side as the first electrode 211 of the first semiconductor element 21 in the first direction z. The semiconductor device A10 further includes a first spacer 31 that conductively bonds the first conductive layer 12 and the first electrode 211. The first spacer 31 has a first surface 312A that faces the first electrode 211. As viewed in the first direction z, the first surface 312A is spaced apart from the first gate electrode 213. This configuration can prevent short-circuiting between the first gate electrode 213 and the first gate wiring 51 shown in FIG. 10 and the first spacer 31.

[0065] The first spacer 31 has a second surface 311A ​​facing the first conductive layer 12. The area of ​​the second surface 311A ​​is larger than the area of ​​the first surface 312A. As viewed in the first direction z, the first surface 312A is surrounded by the periphery of the second surface 311A. If an imaginary plane extending from the periphery of the first surface 312A toward the second surface 311A ​​and inclined at a 45° angle with respect to the first direction z is defined for the first spacer 31, heat conducted to the first spacer 31 is uniformly diffused in the area surrounded by the imaginary plane. Therefore, by adopting this configuration, heat conducted from the first surface 312A to the first spacer 31 is more likely to be uniformly diffused in the first direction z and in a direction perpendicular to the first direction z. This allows heat conducted from the first electrode 211 of the first semiconductor element 21 to the first spacer 31 to be more quickly conducted to the first conductive layer 12.

[0066] The semiconductor device A10 further includes a second terminal 42 conductively bonded to the first conductive layer 12 and a third terminal 43 conductively bonded to the second conductive layer 13. The second terminal 42 and the third terminal 43 are exposed from the sealing resin 60. The portions of the second terminal 42 and the third terminal 43 exposed from the sealing resin 60 are bent in the first direction z toward the side where the first terminal 41 is located. This configuration makes it possible to surface-mount the semiconductor device A10 on a wiring board.

[0067] Second Embodiment: A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to FIGS. 14 to 34. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and redundant description will be omitted. Here, for ease of understanding, FIG. 14 shows the sealing resin 60 in a see-through manner. For ease of understanding, FIG. 15 shows the first terminal 41 in a see-through manner, which is further different from FIG. 14. In FIGS. 14 and 15, the outline of the sealing resin 60 seen through is shown by an imaginary line. In FIG. 15, the outline of the first terminal 41 seen through is shown by an imaginary line. In FIG. 14, line XVIII-XVIII is shown by a dashed line.

[0068] The semiconductor device A20 differs from the semiconductor device A10 in the configuration of the multiple first semiconductor elements 21 and the multiple second semiconductor elements 22 and in the absence of the multiple first spacers 31 and the multiple second spacers 32.

[0069] 20 to 25, each of the plurality of first semiconductor elements 21 has a first detection electrode 214, a first element body 215, first rewiring 216, second rewiring 217, a first resin 218, and a covering layer 219. The plurality of first semiconductor elements 21 are packaged in resin.

[0070] The first element body 215 is an element corresponding to one of the multiple first semiconductor elements 21 of the semiconductor device A10. The first element body 215 includes a first pad 215A and a first gate pad 215B. As shown in FIG. 27 , the first pad 215A and the first gate pad 215B are located on the side facing the first conductive layer 12 in the first direction z. The first pad 215A corresponds to the first electrode 211 of the first semiconductor element 21 of the semiconductor device A10. The first gate pad 215B corresponds to the first gate electrode 213 of the first semiconductor element 21 of the semiconductor device A10. The first element body 215 includes a second electrode 212.

[0071] 22 to 25 , the first resin 218 covers a part of the first element body 215 and at least a part of each of the first rewiring 216 and the second rewiring 217. The first electrode 211, the second electrode 212, the first gate electrode 213, and the first detection electrode 214 are exposed from the first resin 218.

[0072] 22 to 24, the first electrode 211 is electrically connected to and in contact with the first pad 215A of the first element body 215. As shown in Fig. 21, when viewed in the first direction z, the first electrode 211 includes a portion that protrudes outward from the second electrode 212. When viewed in the first direction z, the area of ​​the first electrode 211 is larger than the area of ​​the first pad 215A.

[0073] 20, 22, and 23, the first gate electrode 213 and the first detection electrode 214 are located on the same side as the second electrode 212 in the first direction z. The first detection electrode 214 is spaced apart from the first gate electrode 213 in the third direction y.

[0074] 20 to 22, the first rewiring 216 electrically connects the first gate pad 215B of the first element body 215 and the first gate electrode 213. A portion of the first rewiring 216 is covered with a first resin 218.

[0075] 20 , 21 , and 23 , the second rewiring 217 electrically connects the first pad 215A of the first element body 215 and the first detection electrode 214. A portion of the second rewiring 217 is covered with a first resin 218. The second rewiring 217 is connected to the first electrode 211.

[0076] The first redistribution wiring 216, the second redistribution wiring 217, and the first resin 218 can be formed by, for example, the laser direct structuring (LDS) method disclosed in U.S. Patent Application Publication No. 2010 / 0019370. In this case, the material of the first resin 218 includes an additive containing a metal element. Each of the first redistribution wiring 216 and the second redistribution wiring 217 includes the metal element.

[0077] 21 to 23 , the covering layer 219 covers the portions of the first rewiring 216 and the second rewiring 217 that are exposed from the first resin 218. The covering layer 219 is an insulator. The covering layer 219 is in contact with the first rewiring 216, the second rewiring 217, and the first resin 218. The covering layer 219 is, for example, a solder resist.

[0078] As shown in FIG. 27, the bonding surface 41A of the third conductive layer 172 of the first terminal 41 is conductively bonded to the second electrode 212 of each of the plurality of first semiconductor elements 21 via the conductive bonding layer 29.

[0079] 15 and 26 , each of the multiple first detection wirings 52 is conductively joined to the first detection electrode 214 of any one of the multiple first semiconductor elements 21 and to the first detection conductive layer 151. The multiple first detection wirings 52 are metal leads. The composition of the multiple first detection wirings 52 includes copper.

[0080] 28 to 32 , each of the plurality of second semiconductor elements 22 has a second detection electrode 224, a second element body 225, third rewiring 226, fourth rewiring 227, and second resin 228. The plurality of second semiconductor elements 22 are packaged in resin.

[0081] The second element body 225 is an element corresponding to one of the multiple second semiconductor elements 22 of the semiconductor device A10. The second element body 225 includes a second pad 225A and a second gate pad 225B. As shown in FIG. 34 , the second pad 225A and the second gate pad 225B are located on the opposite side of the semiconductor device 215 from the side facing the second conductive layer 13 in the first direction z. The second pad 225A corresponds to the third electrode 221 of the second semiconductor element 22 of the semiconductor device A10. The second gate pad 225B corresponds to the second gate electrode 223 of the second semiconductor element 22 of the semiconductor device A10. The first element body 215 includes a fourth electrode 222.

[0082] 30 to 32 , the second resin 228 covers a part of the second element body 225 and at least a part of each of the third rewiring 226 and the fourth rewiring 227. The third electrode 221, the fourth electrode 222, the second gate electrode 223, and the second detection electrode 224 are exposed from the second resin 228.

[0083] 30 to 32, the third electrode 221 is electrically connected to and in contact with the second pad 225A of the second element body 225. As shown in Fig. 28, when viewed in the first direction z, the third electrode 221 includes a portion that protrudes outward from the fourth electrode 222. When viewed in the first direction z, the area of ​​the third electrode 221 is larger than the area of ​​the second pad 225A.

[0084] 28, 30, and 31, the second gate electrode 223 and the second detection electrode 224 are located on the same side as the third electrode 221 in the first direction z. The second detection electrode 224 is spaced apart from the second gate electrode 223 in the third direction y.

[0085] 28 to 30 , the third rewiring 226 electrically connects the second gate pad 225B of the second element body 225 to the second gate electrode 223. A portion of the third rewiring 226 is covered with a second resin 228.

[0086] 28 , 29 , and 31 , the fourth rewiring 227 electrically connects the second pad 225A of the second element body 225 and the second detection electrode 224. A portion of the fourth rewiring 227 is covered with the second resin 228. The fourth rewiring 227 is connected to the third electrode 221.

[0087] The third rewiring 226, the fourth rewiring 227, and the second resin 228 can be formed by the LDS method described above. In this case, the material of the second resin 228 includes an additive containing a metal element. Each of the third rewiring 226 and the fourth rewiring 227 includes the metal element.

[0088] As shown in FIG. 34 , the bonding surface 41A of the third conductive layer 172 of the first terminal 41 is conductively bonded to the third electrodes 221 of the plurality of second semiconductor elements 22 via the conductive bonding layer 29 .

[0089] 15 and 33 , each of the multiple second detection wirings 54 is conductively joined to the second detection electrode 224 of any one of the multiple second semiconductor elements 22 and to the second detection conductive layer 152. Each of the multiple second gate wirings 53 and the multiple second detection wirings 54 is a metal lead. The composition of each of the multiple second gate wirings 53 and the multiple second detection wirings 54 includes copper.

[0090] Next, the effects of the semiconductor device A20 will be described.

[0091] The semiconductor device A20 includes a first conductive layer 12, a first semiconductor element 21, a second conductive layer 13, a second semiconductor element 22, a first terminal 41, and a sealing resin 60. The first semiconductor element 21 has a first electrode 211 conductively bonded to the first conductive layer 12 and a second electrode 212 to which the first terminal 41 is conductively bonded. The second semiconductor element 22 has a third electrode 221 conductively bonded to the first terminal 41 and a fourth electrode 222 conductively bonded to the second conductive layer 13. The polarity of the second electrode 212 and the polarity of the third electrode 221 are opposite to each other. The first terminal 41 is exposed from the sealing resin 60. Therefore, with this configuration, the semiconductor device A20 can also reduce its parasitic inductance and improve its heat dissipation. Furthermore, by incorporating a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0092] In the semiconductor device A20, the first semiconductor element 21 includes a first element body 215 including a second electrode 212, a first pad 215A, and a first gate pad 215B, and a first rewiring 216 electrically connecting the first gate pad 215B and the first gate electrode 213. The first gate electrode 213 is located on the same side as the second electrode 212 in the first direction z. The first electrode 211 is electrically connected to the first pad 215A. This configuration prevents a short circuit between the first gate electrode 213 and the first conductive layer 12, even when the first electrode 211 is electrically connected to the first conductive layer 12 without the first spacer 31. This eliminates the need for the first spacer 31 and the second spacer 32, thereby reducing the dimension of the semiconductor device A10 in the first direction z and further reducing the parasitic inductance of the semiconductor device A10.

[0093] In accordance with the above case, the second semiconductor element 22 has a first element body 215 including a fourth electrode 222, a second pad 225A, and a second gate pad 225B, and a third rewiring 226 that electrically connects the second gate pad 225B and the second gate electrode 223. The second gate electrode 223 is located on the same side as the third electrode 221 in the first direction z. The third electrode 221 is in contact with the second pad 225A. This configuration allows the dimension of the second semiconductor element 22 in the first direction z to match the dimension of the first semiconductor element 21 in the first direction z.

[0094] Third Embodiment: A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to FIGS. 35 to 37. In these figures, elements that are the same as or similar to those in the semiconductor device A10 and semiconductor device A20 described above are given the same reference numerals, and duplicated descriptions will be omitted. Here, for ease of understanding, FIG. 35 shows the sealing resin 60 in a see-through manner. In FIG. 35, the outline of the see-through sealing resin 60 is shown with imaginary lines. In FIG. 35, the lines XXXVII-XXXVII are each shown with a dashed line.

[0095] In the semiconductor device A30, the configuration of the first terminal 41 is different from that of the semiconductor device A20.

[0096] 35 to 37 , the area of ​​the mounting surface 41B of the first terminal 41 is larger than the area of ​​the bonding surface 41A of the first terminal 41. When viewed in the first direction z, the bonding surface 41A is surrounded by the periphery of the mounting surface 41B. A step is provided at the end of the first terminal 41 in a direction perpendicular to the first direction z.

[0097] The first terminal 41 of the semiconductor device A30 can be applied not only to the semiconductor device A20 but also to the semiconductor device A10.

[0098] Next, the effects of the semiconductor device A30 will be described.

[0099] The semiconductor device A30 includes a first conductive layer 12, a first semiconductor element 21, a second conductive layer 13, a second semiconductor element 22, a first terminal 41, and a sealing resin 60. The first semiconductor element 21 has a first electrode 211 conductively bonded to the first conductive layer 12 and a second electrode 212 to which the first terminal 41 is conductively bonded. The second semiconductor element 22 has a third electrode 221 conductively bonded to the first terminal 41 and a fourth electrode 222 conductively bonded to the second conductive layer 13. The polarity of the second electrode 212 and the polarity of the third electrode 221 are opposite to each other. The first terminal 41 is exposed from the sealing resin 60. Therefore, with this configuration, the semiconductor device A30 can also reduce the parasitic inductance of the semiconductor device A30 and improve the heat dissipation of the semiconductor device A30. Furthermore, by incorporating a configuration common to the semiconductor device A10, the semiconductor device A30 achieves the same effects as the semiconductor device A10.

[0100] The first terminal 41 has a bonding surface 41A and a mounting surface 41B. The bonding surface 41A is conductively bonded to the second electrode 212 of the first semiconductor element 21 and the third electrode 221 of the second semiconductor element 22. The mounting surface 41B is exposed from the sealing resin 60. The area of ​​the mounting surface 41B is larger than the area of ​​the bonding surface 41A. When viewed in the first direction z, the bonding surface 41A is surrounded by the periphery of the mounting surface 41B. With this configuration, heat conducted from the first semiconductor element 21 and the second semiconductor element 22 to the bonding surface 41A is more likely to diffuse in a direction perpendicular to the first direction z. This reduces the thermal resistance of the first terminal 41 in the first direction z.

[0101] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0102] The present disclosure includes embodiments described in the following supplementary notes. Supplementary note 1. A semiconductor device comprising: a first conductive layer; a first semiconductor element having a first electrode and a second electrode positioned opposite each other in a first direction, the first electrode being conductively bonded to the first conductive layer; a second conductive layer spaced from the first conductive layer in a direction orthogonal to the first direction; a second semiconductor element having a third electrode and a fourth electrode positioned opposite each other in the first direction, the fourth electrode being conductively bonded to the second conductive layer; a first terminal conductively bonded to the second electrode and the third electrode; and a sealing resin covering the first semiconductor element and the second semiconductor element, wherein the polarity of the second electrode and the polarity of the third electrode are different from each other, and the first terminal is exposed from the sealing resin. Supplementary note 2. The semiconductor device according to Supplementary note 1, further comprising an insulating layer positioned on the opposite side of the first semiconductor element and the second semiconductor element with respect to the first conductive layer and the second conductive layer, the first conductive layer and the second conductive layer being bonded to the insulating layer. Supplementary note 3. The semiconductor device according to Appendix 2, further comprising a heat dissipation layer located on the opposite side of the insulating layer from the first conductive layer and the second conductive layer, the heat dissipation layer being bonded to the insulating layer and exposed from the sealing resin. Appendix 4. The semiconductor device according to Appendix 3, wherein the heat dissipation layer is surrounded by a periphery of the insulating layer when viewed in the first direction. Appendix 5. The semiconductor device according to Appendix 4, wherein the heat dissipation layer overlaps the entire first conductive layer and the entire second conductive layer when viewed in the first direction, and the area of ​​the heat dissipation layer is larger than the sum of the area of ​​the first conductive layer and the area of ​​the second conductive layer when viewed in the first direction. Appendix 6. The semiconductor device according to Appendix 5, wherein the thickness of each of the first conductive layer, the second conductive layer, and the heat dissipation layer is larger than the thickness of the insulating layer. Appendix 7. 7. The semiconductor device according to claim 3, wherein the first semiconductor element has a first gate electrode, and further comprises a first gate wiring conductively connected to the first gate electrode, and the first gate wiring overlaps the insulating layer when viewed in the first direction.Appendix 8. The semiconductor device according to Appendix 7, wherein the first gate wiring overlaps the heat dissipation layer when viewed in the first direction. Appendix 9. The semiconductor device according to Appendix 7 or 8, wherein the first gate electrode is located on the same side as the first electrode in the first direction, and further comprises a first spacer that conductively joins the first conductive layer and the first electrode, the first spacer having a first surface facing the first electrode, and the first surface being spaced apart from the first gate electrode when viewed in the first direction. Appendix 10. The semiconductor device according to Appendix 9, wherein the first spacer has a second surface facing the first conductive layer, an area of ​​the second surface being larger than an area of ​​the first surface, and the first surface being surrounded by a periphery of the second surface when viewed in the first direction. Appendix 11. The semiconductor device according to Appendix 7 or 8, wherein the first semiconductor element has a first element body including a first pad and a first gate pad located on a side facing the first conductive layer in the first direction, and a first rewiring that electrically connects the first gate pad and the first gate electrode, the first element body including the second electrode, the first gate electrode being located on the same side as the second electrode in the first direction, and the first electrode being electrically connected to the first pad. Appendix 12. The semiconductor device according to Appendix 11, wherein the first electrode is in contact with the first pad. Appendix 13. The semiconductor device according to Appendix 12, wherein the first semiconductor element has a first resin that covers a portion of the first element body and at least a portion of the first rewiring, and the first electrode, the second electrode, and the first gate electrode are exposed from the first resin. Appendix 14. The semiconductor device described in Appendix 13, wherein the first semiconductor element has a first detection electrode located on the same side as the first gate electrode in the first direction, and a second rewiring that conducts electricity between the first pad and the first detection electrode, at least a portion of the second rewiring is covered with the first resin, and the first detection electrode is exposed from the first resin.Supplementary Note 15. The semiconductor device according to Supplementary Note 13 or 14, wherein the second semiconductor element has a second element body including a second pad and a second gate pad located on the side opposite to the side facing the second conductive layer in the first direction, and a second gate electrode conductive to the second gate pad, the second element body includes the fourth electrode, the second gate electrode is located on the same side as the third electrode in the first direction, and the third electrode is in contact with the second pad. Supplementary Note 16. The semiconductor device according to any of Supplements 1 to 15, wherein the first terminal has a bonding surface conductively bonded to the second electrode and the third electrode, and a mounting surface facing the side opposite to the bonding surface in the first direction and exposed from the sealing resin, an area of ​​the mounting surface is larger than an area of ​​the bonding surface, and the bonding surface is surrounded by a periphery of the mounting surface as viewed in the first direction. Supplementary Note 17. 17. The semiconductor device according to any one of appendixes 1 to 16, further comprising: a second terminal conductively joined to the first conductive layer; and a third terminal conductively joined to the second conductive layer, wherein the second terminal and the third terminal are exposed from the sealing resin, and each portion of the second terminal and the third terminal exposed from the sealing resin is bent toward the side where the first terminal is located in the first direction.

[0103] A10, A20, A30: semiconductor device 11: insulating layer 12: first conductive layer 12A: first main surface 13: second conductive layer 13A: second main surface 141: first gate conductive layer 142: second gate conductive layer 151: first detection conductive layer 152: second detection conductive layer 16: heat dissipation layer 21: first semiconductor element 211: first electrode 212: second electrode 213: first gate electrode 214: first detection electrode 215: first element body 215A: first pad 215B: first gate pad 216: first rewiring 217: second rewiring 218: first resin 219: covering layer 22: second semiconductor element 221: third electrode 222: fourth electrode 223: second gate electrode 224: second detection electrode 225: Second element body 225A: Second pad 225B: Second gate pad 226: Third rewiring 227: Fourth rewiring 228: Second resin 29: Conductive bonding layer 31: First spacer 311: First part 311A: Second surface 312A: Third surface 313A: Fourth surface 314A: First recess 312: Second part 312A: First surface 312B: Second recess 32: Second spacer 41: First terminal 41A: Bonding surface 41B: Mounting surface 42: Second terminal 43: Third terminal 441: First gate terminal 442: Second gate terminal 451: First detection terminal 452: Second detection terminal 51: First gate wiring 52: First detection wiring 53: Second gate wiring 54: Second detection wiring 55: First wire 56: Second wire 60: Sealing resin 61: Top surface 62: Bottom surface 63: First side surface 64: Second side surface z: First direction x: Second direction y: Third direction

Claims

1. A first conductive layer; a first semiconductor element having a first electrode and a second electrode positioned opposite each other in a first direction, the first electrode being conductively joined to the first conductive layer; a second conductive layer spaced from the first conductive layer in a direction perpendicular to the first direction; a second semiconductor element having a third electrode and a fourth electrode positioned opposite each other in the first direction, the fourth electrode being conductively joined to the second conductive layer; a first terminal conductively connected to the second electrode and the third electrode; a sealing resin that covers the first semiconductor element and the second semiconductor element, The polarity of the second electrode and the polarity of the third electrode are different from each other, The first terminal is exposed from the sealing resin.

2. the first conductive layer and the second conductive layer are disposed on the opposite side of the first semiconductor element and the second semiconductor element. The semiconductor device according to claim 1 , wherein the first conductive layer and the second conductive layer are joined to the insulating layer.

3. a heat dissipation layer located on the opposite side of the insulating layer from the first conductive layer and the second conductive layer, The semiconductor device according to claim 2 , wherein the heat dissipation layer is bonded to the insulating layer and is exposed from the sealing resin.

4. The semiconductor device according to claim 3 , wherein the heat dissipation layer is surrounded by a periphery of the insulating layer when viewed in the first direction.

5. When viewed in the first direction, the heat dissipation layer overlaps the entire first conductive layer and the entire second conductive layer, The semiconductor device according to claim 4 , wherein an area of ​​the heat dissipation layer is larger than a sum of an area of ​​the first conductive layer and an area of ​​the second conductive layer when viewed in the first direction.

6. The semiconductor device according to claim 5 , wherein each of said first conductive layer, said second conductive layer and said heat dissipation layer has a thickness greater than a thickness of said insulating layer.

7. the first semiconductor element has a first gate electrode; a first gate wiring conductively connected to the first gate electrode; The semiconductor device according to claim 3 , wherein the first gate wiring overlaps the insulating layer when viewed in the first direction.

8. The semiconductor device according to claim 7 , wherein the first gate wiring overlaps the heat dissipation layer when viewed in the first direction.

9. the first gate electrode is located on the same side as the first electrode in the first direction, a first spacer that conductively connects the first conductive layer and the first electrode; the first spacer has a first surface facing the first electrode; The semiconductor device according to claim 7 , wherein the first surface is spaced apart from the first gate electrode when viewed in the first direction.

10. the first spacer has a second surface facing the first conductive layer; The area of ​​the second surface is larger than the area of ​​the first surface, The semiconductor device according to claim 9 , wherein the first surface is surrounded by a periphery of the second surface when viewed in the first direction.

11. the first semiconductor element has a first element body including a first pad and a first gate pad located on a side facing the first conductive layer in the first direction, and a first rewiring that electrically connects the first gate pad and the first gate electrode; The first element body includes the second electrode, the first gate electrode is located on the same side as the second electrode in the first direction, The semiconductor device according to claim 7 , wherein the first electrode is electrically connected to the first pad.

12. The semiconductor device according to claim 11 , wherein the first electrode is in contact with the first pad.

13. the first semiconductor element has a first resin covering a portion of the first element body and at least a portion of the first rewiring; The semiconductor device according to claim 12 , wherein the first electrode, the second electrode and the first gate electrode are exposed from the first resin.

14. the first semiconductor element has a first detection electrode located on the same side as the first gate electrode in the first direction, and a second rewiring that electrically connects the first pad and the first detection electrode; At least a portion of the second rewiring is covered with the first resin; The semiconductor device according to claim 13 , wherein the first detection electrode is exposed from the first resin.

15. the second semiconductor element has a second element body including a second pad and a second gate pad located on an opposite side to a side facing the second conductive layer in the first direction, and a second gate electrode conductive to the second gate pad; the second element body includes the fourth electrode, the second gate electrode is located on the same side as the third electrode in the first direction, The semiconductor device according to claim 13 , wherein the third electrode is in contact with the second pad.

16. the first terminal has a bonding surface that is conductively bonded to the second electrode and the third electrode, and a mounting surface that faces an opposite side to the bonding surface in the first direction and is exposed from the sealing resin, an area of ​​the mounting surface is larger than an area of ​​the bonding surface; The semiconductor device according to claim 1 , wherein the bonding surface is surrounded by a periphery of the mounting surface when viewed in the first direction.

17. a second terminal conductively connected to the first conductive layer; a third terminal conductively connected to the second conductive layer; the second terminal and the third terminal are exposed from the sealing resin, 16. The semiconductor device according to claim 1, wherein each of the second terminal and the third terminal has a portion exposed from the sealing resin bent toward the first terminal in the first direction.