Macro model for semiconductor integrated circuit device, circuit design simulation program, and circuit design simulator

Abstract

This macro model 10 for a semiconductor integrated circuit device is used for a circuit design simulator, the model comprising: a virtual input terminal 11a which receives, as a virtual input signal Sa, parameters for the semiconductor integrated circuit device; and a functional block 12 which approximately or equivalently represents, on the circuit design simulator, the characteristics and behaviors of the semiconductor integrated circuit device on the basis of the virtual input signal Sa received by the virtual input terminal 11a.

Description

Macro model of semiconductor integrated circuit device, circuit design simulation program, circuit design simulator

[0001] The present disclosure relates to a macro model of a semiconductor integrated circuit device, and a circuit design simulation program and a circuit design simulator using the same.

[0002] Conventionally, circuit design simulation programs (e.g., SPICE (simulation program with integrated circuit emphasis) based circuit design simulation programs) have been widely used as design support tools for semiconductor integrated circuit devices. A circuit design simulation program is software that causes a computer that runs the program to function as a circuit design simulator.

[0003] In the circuit design simulator, various simulation models (passive element models such as resistors and capacitors, active element models such as transistors and diodes, and macro models such as semiconductor integrated circuit devices) can be combined with voltage sources, current sources, wiring, etc. to create analog circuits and simulate their responses.

[0004] An example of the related prior art is disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0005] Japanese Patent Application Laid-Open No. 2012-216187

[0006] However, conventional macro models have room for further consideration in modeling semiconductor integrated circuit devices equipped with communication units (such as shortening simulation time and omitting complex pattern input / output).

[0007] The macro model of a semiconductor integrated circuit device disclosed in this specification is used in a circuit design simulator, and includes a virtual input terminal configured to receive parameters of the semiconductor integrated circuit device as virtual input signals, and a functional block configured to approximately or equivalently represent the characteristics and behavior of the semiconductor integrated circuit device on the circuit design simulator based on the virtual input signal received at the virtual input terminal.

[0008] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto.

[0009] According to the present disclosure, it is possible to provide a macro model of a semiconductor integrated circuit device that can reduce simulation time and eliminate complex pattern input / output, as well as a circuit design simulation program and a circuit design simulator that use the same.

[0010] FIG. 1 is a diagram showing an example of the actual configuration of a light emitting device. FIG. 2 is a diagram showing an example of pattern input / output in a communication unit. FIG. 3 is a diagram showing an embodiment of a macro model. FIG. 4 is a diagram showing an example of analog input at a virtual input terminal. FIG. 5 is a diagram showing an example of introducing a conversion module. FIG. 6 is a diagram showing an example of the configuration of a circuit design simulator. FIG. 7 is a diagram showing an example of the configuration of a circuit design simulation program.

[0011] 1 is a diagram showing an example of the configuration of a light-emitting device. The light-emitting device X in this diagram includes a semiconductor integrated circuit device 100, a power supply device 110, a control device 120, light-emitting elements LED1 to LED3 (e.g., light-emitting diodes or a light-emitting diode array), and various discrete components (capacitors C1 to C19, resistors R1 to R20, and inductors L1 to L3).

[0012] The semiconductor integrated circuit device 100 is a light emitting element driving device (so-called LED (light emitting diode) driver IC) that drives light emitting elements LED1 to LED3. Note that the number of driving channels of the semiconductor integrated circuit device 100 is not limited to three.

[0013] The semiconductor integrated circuit device 100 has a plurality of external terminals (PIN, VIN, GND, 5VREG, 5VEXT, TON, COMP1 to COMP3, ISET / PWM1 to ISET / PWM3, SO / FAULTB, CSB, SCK, SI, PGND, SNSN1 to SNSN3, SNSP1 to SNSP3, BOOT1 to BOOT3, SW1 to SW3, and TOP_EXP_PAD) as means for establishing electrical connection with the outside of the device.

[0014] The power supply device 110 generates an output voltage from an input voltage (=battery voltage+B) and outputs it to a PIN terminal of the semiconductor integrated circuit device 100. For example, the power supply device 110 may be a step-up DC / DC converter.

[0015] The control device 120 operates by receiving a power supply voltage VCC (e.g., 5 V). The control device 120 is connected to the SO / FAULTB terminal, CSB terminal, SCK terminal, and SI terminal of the semiconductor integrated circuit device 100. The control device 120 performs bidirectional communication with the semiconductor integrated circuit device 100 in accordance with a predetermined protocol (e.g., SPI [serial peripheral interface] or UART [universal asynchronous receiver / transmitter]). For example, the control device 120 may be an MCU [micro controller unit].

[0016] Capacitors C1 and C2 are both connected between the input terminal and ground terminal of the power supply device 110. Capacitors C3 and C4 are both connected between the output terminal and ground terminal of the power supply device 110. Capacitors C5, C6, and C7 are all connected between the PIN terminal and PGND terminal of the semiconductor integrated circuit device 100.

[0017] Capacitor C8 is connected between the VIN terminal and the GND terminal of semiconductor integrated circuit device 100. Capacitor C9 is connected between the 5VREG terminal and the GND terminal of semiconductor integrated circuit device 100. Capacitor C10 is connected between the 5VEXT terminal and the GND terminal of semiconductor integrated circuit device 100.

[0018] The VIN terminal of the semiconductor integrated circuit device 100 is connected to a terminal to which a battery voltage B+ is applied. The GND terminal of the semiconductor integrated circuit device 100 is connected to a ground terminal. The 5VREG terminal and the 5VEXT terminal of the semiconductor integrated circuit device 100 may each be connected to a terminal to which a stabilizing voltage VREG is applied.

[0019] Resistor R1 is connected between the TON terminal of the semiconductor integrated circuit device 100 and the ground terminal. Resistor R2 and capacitor C11 are connected in series between the COMP1 terminal of the semiconductor integrated circuit device 100 and the ground terminal. Resistor R3 and capacitor C12 are connected in series between the COMP2 terminal of the semiconductor integrated circuit device 100 and the ground terminal. Resistor R4 and capacitor C13 are connected in series between the COMP3 terminal of the semiconductor integrated circuit device 100 and the ground terminal.

[0020] Resistor R5 is connected between the application terminal of the stabilized voltage VREG and the ISET / PWM1 terminal of the semiconductor integrated circuit device 100. Resistor R6 is connected between the application terminal of the stabilized voltage VREG and the ISET / PWM2 terminal of the semiconductor integrated circuit device 100. Resistor R7 is connected between the application terminal of the stabilized voltage VREG and the ISET / PWM3 terminal of the semiconductor integrated circuit device 100.

[0021] Resistor R8 is connected between the ISET / PWM1 terminal and ground of the semiconductor integrated circuit device 100. Resistor R9 is connected between the ISET / PWM2 terminal and ground of the semiconductor integrated circuit device 100. Resistor R10 is connected between the ISET / PWM3 terminal and ground of the semiconductor integrated circuit device 100. Resistor R11 is connected between the application terminal of the power supply voltage VCC and the SO / FAULTB terminal of the semiconductor integrated circuit device 100.

[0022] The inductor L1 is connected between the SW1 terminal of the semiconductor integrated circuit device 100 and a first end of the resistor R12. The second end of the resistor R12 is connected to the anode of the light-emitting element LED1. The capacitor C14 is connected between the SW1 terminal and the BOOT1 terminal of the semiconductor integrated circuit device 100. The capacitor C15 is connected between the anode of the light-emitting element LED1 and the cathode of the light-emitting element LED1. The cathode of the light-emitting element LED1 is connected to the ground terminal. The resistor R13 is connected between the SNSN1 terminal of the semiconductor integrated circuit device 100 and a second end of the resistor R12. The resistor R14 is connected between the SNSP1 terminal of the semiconductor integrated circuit device 100 and a first end of the resistor R12.

[0023] The inductor L2 is connected between the SW2 terminal of the semiconductor integrated circuit device 100 and a first end of the resistor R15. The second end of the resistor R15 is connected to the anode of the light-emitting element LED2. The capacitor C16 is connected between the SW2 terminal and the BOOT2 terminal of the semiconductor integrated circuit device 100. The capacitor C17 is connected between the anode of the light-emitting element LED2 and the cathode of the light-emitting element LED2. The cathode of the light-emitting element LED2 is connected to the ground terminal. The resistor R16 is connected between the SNSN2 terminal of the semiconductor integrated circuit device 100 and a second end of the resistor R15. The resistor R17 is connected between the SNSP2 terminal of the semiconductor integrated circuit device 100 and a first end of the resistor R15.

[0024] The inductor L3 is connected between the SW3 terminal of the semiconductor integrated circuit device 100 and a first end of the resistor R18. The second end of the resistor R18 is connected to the anode of the light-emitting element LED3. The capacitor C18 is connected between the SW3 terminal and the BOOT3 terminal of the semiconductor integrated circuit device 100. The capacitor C19 is connected between the anode of the light-emitting element LED3 and the cathode of the light-emitting element LED3. The cathode of the light-emitting element LED3 is connected to the ground terminal. The resistor R19 is connected between the SNSN3 terminal of the semiconductor integrated circuit device 100 and a second end of the resistor R18. The resistor R20 is connected between the SNSP3 terminal of the semiconductor integrated circuit device 100 and a first end of the resistor R18.

[0025] The semiconductor integrated circuit device 100 connected in this manner generates an output current and an output voltage to be supplied to each of the light emitting elements LED1 to LED3. Each of the light emitting elements LED1 to LED3 receives a power supply from the semiconductor integrated circuit device 100 and is illuminated at a desired brightness.

[0026] The semiconductor integrated circuit device 100 also includes a communication unit (not shown) for performing two-way communication with the control device 120 in accordance with a predetermined protocol.

[0027] FIG. 2 is a diagram showing an example of pattern input / output in the communication unit of the semiconductor integrated circuit device 100, depicting, from top to bottom, signal patterns of the CSB terminal, SCK terminal, SI terminal, and SO / FAULTB terminal.

[0028] As shown in the figure, between the semiconductor integrated circuit device 100 and the control device 120, input and output of complex patterns is performed in synchronization with a clock signal input to the SCK terminal.

[0029] <Considerations on Circuit Design Simulation> However, when attempting to provide a highly accurate simulation model that covers actual operating conditions for a semiconductor integrated circuit device (general LSI product), it is necessary to represent all circuit elements (transistors, resistors, capacitors, etc.) that make up the semiconductor integrated circuit device as element models, and to model the actual circuit itself. However, with this method, even when simulating a small-scale semiconductor integrated circuit device, it takes a long time for the circuit design simulator (computer, etc.) to perform calculations.

[0030] In particular, the communication unit mounted on the semiconductor integrated circuit device 100 is configured with complex logic. Therefore, if the communication unit is directly modeled to achieve the same communication control as the actual device, complex pattern input / output is required (see FIG. 2 above). As a result, the load and processing time of the circuit design simulator increase.

[0031] In the following, in view of the above considerations, a macro model of the semiconductor integrated circuit device 100 that can achieve a reduction in simulation time and the omission of complex pattern input / output will be proposed.

[0032] <Macro Model> Figure 3 is a diagram showing one embodiment of a macro model that simulates a semiconductor integrated circuit device 100. In this specification, the term "macro model" refers to one of various simulation models (device models) used in circuit design simulators. A macro model simulates an analog circuit, a digital circuit, or a combination of these (including the entire semiconductor integrated circuit device) formed by multiple circuit elements. In this respect, a macro model can be distinguished from an element model that simulates a single circuit element (such as a resistor, capacitor, or inductor).

[0033] The macro model 10 of the semiconductor integrated circuit device 100 in this embodiment has, as signal input / output nodes, real input terminals (PIN, SNSPx, SNSNx, VIN, 5VREG, 5VEXT, ISET / PWMx, COMPx, TON, GND, BOOTx, SWx, and PGND) that simulate external terminals provided in the semiconductor integrated circuit device 100 of the actual configuration example (FIG. 1), as well as virtual input terminals 11a (VIT1 to VIT9) and virtual output terminals 11b (VOT1 to VOT5) that are not provided in the semiconductor integrated circuit device 100 of the actual configuration example (FIG. 1). Note that the symbol x indicates the channel number of the light-emitting element LED (x=1, 2, or 3, following the aforementioned FIG. 1).

[0034] The macro model 10 also includes a functional block 12. The functional block 12 approximately or equivalently represents the characteristics and behavior of the semiconductor integrated circuit device 100 on a circuit design simulator based on a virtual input signal Sa received at a virtual input terminal 11 a. The functional block 12 also outputs an abnormality detection result of the semiconductor integrated circuit device 100 as a virtual output signal Sb to a virtual output terminal 11 b. For example, the functional block 12 may be a power supply block that generates an output current and an output voltage to be supplied to a light-emitting element LED.

[0035] Furthermore, element models simulating various discrete components (in this figure, capacitors C20 to C23, resistors R21 and R22, inductor L4, and light-emitting element LED) are connected to the macro model 10.

[0036] The PIN terminal of the macro model 10 is connected to an application terminal of a voltage V1 (for example, 60 V). The voltage V1 can be understood as the output voltage of the power supply device 110 in the above-mentioned actual configuration example (FIG. 1).

[0037] The VIN terminal of the macro model 10 is connected to an application terminal of a voltage V2 (for example, 13 V). The voltage V2 can be understood as the battery voltage +B in the previous example of the actual configuration (FIG. 1).

[0038] The ISET / PWMx terminal of the macro model 10 is connected to an application terminal of a voltage V3 (for example, 5 V). The voltage V3 can be understood as the regulated voltage VREG in the above-mentioned actual configuration example (FIG. 1) or a divided voltage thereof.

[0039] The capacitor C20 is connected between the 5VREG terminal and the 5VEXT terminal of the macro model 10 and the ground terminal. The capacitor C20 can be understood as the capacitors C9 and C10 in the above-mentioned actual configuration example (FIG. 1).

[0040] The capacitor C21 is connected between the COMPx terminal and the ground terminal of the macro model 10. The capacitor C21 can be understood as any of the capacitors C11 to C13 in the above-mentioned actual configuration example (FIG. 1).

[0041] The resistor R21 is connected between the TON terminal and the ground terminal of the macro model 10. The resistor R21 can be understood as the resistor R1 in the above-mentioned actual configuration example (FIG. 1).

[0042] The capacitor C22 is connected between the BOOTx terminal and the SWx terminal of the macro model 10. The capacitor C22 can be understood as any of the capacitors C14, C16, and C18 in the above-mentioned actual configuration example (FIG. 1).

[0043] The inductor L4 is connected between the SWx terminal of the macro model 10 and a first end of the resistor R22. The second end of the resistor R22 is connected to the anode of the light-emitting element LED. The inductor L4 can be understood as any of the inductors L1 to L3 in the above-mentioned actual configuration example (FIG. 1). The resistor R22 can be understood as any of the resistors R12, R15, and R18 in the above-mentioned actual configuration example (FIG. 1).

[0044] The capacitor C23 is connected between the anode of the light-emitting element LED and the cathode (=ground terminal) of the light-emitting element LED. The capacitor C23 can be understood as any of the capacitors C15, C17, and C19 in the above-mentioned actual configuration example (FIG. 1).

[0045] The light-emitting element LED includes, for example, a plurality of light-emitting diodes connected in series between the second end of the resistor R22 and the ground end, and a plurality of resistors connected in parallel to each of the light-emitting diodes. The light-emitting element LED can be understood as any of the light-emitting elements LED1 to LED3 in the above-mentioned example configuration (FIG. 1).

[0046] The SNSPx terminal of the macro model 10 is connected to a first end of the resistor R22. The SNSNx terminal of the macro model 10 is connected to a second end of the resistor R22. The GND terminal and the PGND terminal of the macro model 10 are each connected to the ground terminal.

[0047] The virtual input terminal 11a and the virtual output terminal 11b are provided in place of the external terminals for communication (SO / FAULTB, CSB, SCK, and SI) in the above-mentioned actual configuration example (FIG. 1). In other words, the virtual input terminal 11a and the virtual output terminal 11b are external terminals that are not actually provided in the semiconductor integrated circuit device 100.

[0048] The virtual input terminal 11a receives the parameters of the semiconductor integrated circuit device 100 as a virtual input signal Sa. Referring to the figure, the virtual input terminal 11a includes terminals VIT1 to VIT9. The virtual input signal Sa includes virtual input signals S1 to S9.

[0049] The parameters of the semiconductor integrated circuit device 100 include the operation mode, output current, output voltage, drive frequency, and on-duty of the semiconductor integrated circuit device 100. In addition, various parameters such as the frequency characteristics of the DC / DC converter (e.g., the transconductance gm of the error amplifier) ​​or the slew rate may be adjusted.

[0050] The VIT1 terminal receives an input of a virtual input signal S1. The virtual input signal S1 may be a CHONx signal for switching between enabling and disabling channel x. In this case, for example, channel x may be enabled when the virtual input signal S1 is at a high level (e.g., 1 V), and channel x may be disabled when the virtual input signal S1 is at a low level (e.g., 0 V).

[0051] The VIT2 terminal receives an input of a virtual input signal S2, which may be an ISET_dac signal for setting an average output current ILED_AVE supplied to the light-emitting element LED.

[0052] 4 is a diagram showing an example of an analog input at the virtual input terminal 11a (VIT2 terminal). The horizontal axis represents the analog value (voltage value or current value) of the ISET_dac signal. The vertical axis represents the average output current ILED_AVE supplied to the light-emitting element LED.

[0053] When DC dimming is performed in the semiconductor integrated circuit device 100 of the actual configuration example ( FIG. 1 ), the average output current ILEDx_AVE supplied to the light emitting element LEDx is set by the following equation (1) according to the resistance value Rsns of the resistor R12, R15, or R18 connected between the SNSPx terminal and the SNSNx terminal of the semiconductor integrated circuit device 100 and the 10-bit SPI register value ISETx[9:0]: Note that the variables VA, VB, and K are fixed values ​​or variable values.

[0054]

[0055] The above formula (1) is written in the data sheet of the semiconductor integrated circuit device 100. Therefore, a user of the semiconductor integrated circuit device 100 can refer to the above formula (1) and write the SPI register value ISETx[9:0] from the control device 120 to the semiconductor integrated circuit device 100 so as to obtain a desired average output current ILEDx_AVE. The setting range of the SPI register value ISETx[9:0] is 1024 levels, from "000h (0d)" to "3FF (1023d)."

[0056] In consideration of such previous operation, it is desirable that the virtual input signal S2 (=ISET_dac signal) is input within a setting range of, for example, 0V to 1023V, following the decimal notation of the SPI register value ISETx[9:0].

[0057] That is, in the macro model 10 of the semiconductor integrated circuit device 100, the average output current ILED_AVE supplied to the light-emitting element LED may be set by the following equation (2) in accordance with the resistance value Rsns of the resistor R22 and the virtual input signal S2 (=ISET_dac signal).

[0058]

[0059] 4, when the ISET_dac signal is 0 V, the average output current ILED_AVE is set to the minimum value min. On the other hand, when the ISET_dac signal is 1023 V, the average output current ILED_AVE is set to the maximum value max.

[0060] According to such settings, the user of the semiconductor integrated circuit device 100 can set the average output current ILED_AVE even on a circuit design simulator based on the data sheet of the semiconductor integrated circuit device 100. This saves the user time and effort.

[0061] Returning to FIG. 3 , the description of the virtual input terminal 11a will continue. The VIT3 terminal accepts input of a virtual input signal S3. The virtual input signal S3 may be a PWMx signal for turning on / off the PWM dimming function for channel x. In this case, the PWM dimming function may be turned on when the virtual input signal S3 is at a high level (e.g., 1 V), and may be turned off when the virtual input signal S3 is at a low level (e.g., 0 V).

[0062] The VIT4 terminal receives input of a virtual input signal S4. The virtual input signal S4 may be a GMx_dac signal for setting the transconductance gm of an amplifier that forms the output feedback loop of the semiconductor integrated circuit device 100. As with the ISET_dac signal described above, the setting range of the GMx_dac signal is preferably determined based on the contents of the data sheet for the semiconductor integrated circuit device 100.

[0063] The VIT5 terminal receives an input of a virtual input signal S5. The virtual input signal S5 may be a TON_dac signal for setting the on-time Ton of the semiconductor integrated circuit device 100 that employs the bottom detection on-time fixed method. The setting range of the TON_dac signal is preferably determined based on the contents described in the data sheet of the semiconductor integrated circuit device 100, similar to the ISET_dac signal and GMx_dac signal described above.

[0064] The VIT6 terminal receives input of a virtual input signal S6. The virtual input signal S6 may be an SSCG_dac signal for setting the frequency of an SSCG (spread spectrum clock generator). The setting range of the SSCG_dac signal is preferably determined based on the contents of the data sheet for the semiconductor integrated circuit device 100, similar to the ISET_dac signal, GMx_dac, and TON_dac signals described above. When the SSCG_dac signal is 0 V, the SSCG function may be disabled.

[0065] The VIT7 terminal receives a virtual input signal S7. The virtual input signal S7 may be a VMODEx signal for switching on / off the voltage-mode control for channel x. In this case, for example, when the virtual input signal S7 is at a high level (e.g., 1 V), the voltage-mode control may be turned on, and when the virtual input signal S7 is at a low level (e.g., 0 V), the voltage-mode control may be turned off.

[0066] The VIT8 terminal receives input of a virtual input signal S8. The virtual input signal S8 may be an LMPH signal for transitioning the semiconductor integrated circuit device 100 to LIMP_HOME mode (= an operating mode when bidirectional communication between the semiconductor integrated circuit device 100 and the control device 120 cannot be established). In this case, for example, the semiconductor integrated circuit device 100 may transition to the LIMP_HOME mode when the virtual input signal S8 is at a high level (e.g., 1 V), and the semiconductor integrated circuit device 100 may return from the LIMP_HOME mode when the virtual input signal S8 is at a low level (e.g., 0 V).

[0067] The VIT9 terminal receives an input of a virtual input signal S9. The virtual input signal S9 may be an EN signal for switching between enabling and disabling the entire semiconductor integrated circuit device 100. In this case, for example, the semiconductor integrated circuit device 100 may be enabled when the virtual input signal S9 is at a high level (e.g., 1 V), and may be disabled when the virtual input signal S9 is at a low level (e.g., 0 V).

[0068] In the semiconductor integrated circuit device 100 of the actual configuration example (FIG. 1), the above-mentioned CHONx signal, ISET_dac signal, PWMx signal, GMx_dac signal, TON_dac signal, SSCG_dac signal, VMODEx signal, LMPH signal, and EN signal are each input as a pattern to the semiconductor integrated circuit device 100 (particularly the communication unit) as digital communication signals.

[0069] On the other hand, in the macro model 10 of this embodiment, no complex logic processing is required in the communication unit, and the above-mentioned CHONx signal, ISET_dac signal, PWMx signal, GMx_dac signal, TON_dac signal, SSCG_dac signal, VMODEx signal, LMPH signal, and EN signal are input individually and directly to the virtual input terminals 11a (VIT1 to VIT9).

[0070] Such a macro model 10 reduces the computational load on the circuit design simulator, allowing simulation results to be obtained in a shorter time. Furthermore, the need to input complex patterns is eliminated, improving user convenience.

[0071] In the above description, an analog signal having a voltage value or current value according to the setting value of a parameter input from the control device 120 to the semiconductor integrated circuit device 100 is given as an example of the virtual input signal Sa.

[0072] However, the virtual input signal Sa is not limited to this, and may be a pulse-modulated signal modulated in accordance with the set values ​​of parameters. For example, the virtual input signal Sa may be pulse-width modulated so as to include information about the drive frequency and on-duty of the semiconductor integrated circuit device 100.

[0073] Furthermore, the pulse modulation method is not limited to the above-mentioned pulse width modulation method, but may be a pulse frequency modulation method, a pulse amplitude modulation method, a pulse code modulation method, or a pulse position modulation method.

[0074] Next, the virtual output terminal 11b will be described. The virtual output terminal 11b outputs the abnormality detection result of the semiconductor integrated circuit device 100 as a virtual output signal Sb. Referring to the figure, the virtual output terminal 11b includes terminals VOT1 to VOT5.

[0075] The VOT1 terminal outputs, for example, a SWOCPx signal corresponding to the overcurrent detection result of channel x. The VOT2 terminal outputs, for example, a LEDOVERx signal corresponding to the overvoltage detection result of channel x. The VOT3 terminal outputs, for example, a LEDUNDERx signal corresponding to the undervoltage detection result of channel x. The VOT4 terminal outputs, for example, a LODx signal corresponding to the open detection result of channel x. The VOT5 terminal outputs, for example, a LSDx signal corresponding to the short detection result of channel x.

[0076] In the semiconductor integrated circuit device 100 of the actual configuration example (FIG. 1), the above SWOCPx signal, LEDOVERx signal, LEDUNDERx signal, LODx signal, and LSDx signal are each output as a pattern from the semiconductor integrated circuit device 100 (particularly the communication unit) as digital communication signals.

[0077] On the other hand, in the macro model 10 of this embodiment, no complex logic processing is required in the communication section, and the above SWOCPx signal, LEDOVERx signal, LEDUNDERx signal, LODx signal, and LSDx signal are output individually and directly from the virtual output terminals 11b (VOT1 to VOT5).

[0078] Such a macro model 10 reduces the computational load on the circuit design simulator, allowing simulation results to be obtained in a shorter time. In addition, the omission of complex pattern output improves user convenience.

[0079] <Conversion Module> Fig. 5 is a diagram showing an example of the introduction of a conversion module. In the embodiment described above (Fig. 3), the virtual input signal Sa and the virtual output signal Sb are transmitted and received in series between the semiconductor integrated circuit device 100 and the control device 120. Therefore, as described above, complex pattern input / output is not required, which can contribute to improving user convenience.

[0080] However, there may be cases where users wish to continue executing circuit design simulations using digital communication signals that comply with a predetermined protocol, as in the past.

[0081] Therefore, the circuit design simulation program may be provided with a conversion module 20 that converts between digital communication signals (SO / FAULTB, CSB, SCK, and SI) conforming to a predetermined protocol and the virtual input signal Sa and the virtual output signal Sb.

[0082] If such a conversion module 20 is available, it becomes possible to flexibly respond to the above user requests.

[0083] 6 is a block diagram showing an example of the configuration of a circuit design simulator that uses the macro model 10 described above. The circuit design simulator 210 of this example is a computer having a calculation unit 211, a storage unit 212, an operation unit 213, a display unit 214, and a communication unit 215. The circuit design simulator 210 is realized by causing the calculation unit 211 to execute a circuit design simulation program 300 stored in the storage unit 212.

[0084] The calculation unit 211 comprehensively controls the operation of the circuit design simulator 210. For example, the calculation unit 211 executes the circuit design simulation program 300 stored in the storage unit 212 and performs various calculation processes to cause the computer to function as the circuit design simulator 210. The calculation unit 211 also performs recognition processing of user operations input from the operation unit 213 and display control of various screens on the display unit 214. For example, a CPU (central processing unit) can be used as the calculation unit 211.

[0085] The storage unit 212 is used as a storage area for the OS (operation system) program and various software (including the circuit design simulation program 300). The storage unit 212 is also used as a storage area for various data created by the user and a work area for various software. The storage unit 212 may be a hard disk drive, a solid state drive, or a USB (universal serial bus) memory.

[0086] The operation unit 213 accepts various user operations (circuit creation operation, component reference operation, probe installation operation, etc.) and transmits them to the calculation unit 211. The operation unit 213 can be a keyboard, a mouse, a trackball, a pen tablet, a touch panel, or the like.

[0087] The display unit 214 displays various screens (circuit creation field, component palette, waveform drawing window, etc.) based on instructions from the calculation unit 211. As the display unit 214, a liquid crystal display or the like can be used.

[0088] The communication unit 215 performs information communication via a telecommunication line 220 (such as the Internet or a local area network (LAN)) based on instructions from the calculation unit 211. For example, the communication unit 215 performs information communication via the telecommunication line 220 with servers 230X to 230Z of vendors that manufacture and sell semiconductor integrated circuit devices, and downloads macro model files (*.mod) and the like.

[0089] By using such a circuit design simulator 210, it becomes possible to perform simulation verification (characteristic evaluation, operation check, etc.) of an analog circuit before actually fabricating the analog circuit as a prototype.

[0090] <Circuit Design Simulation Program> Figure 7 is a diagram showing an example of the configuration of a circuit design simulation program 300. The circuit design simulation program 300 (e.g., a SPICE-based circuit design simulation program) is software that is executed by a computer and causes the computer to function as a circuit design simulator 210 (see Figure 6). The circuit design simulation program 300 of this example configuration includes a main program 310 and a model library 320. The circuit design simulation program 300 is transferred or distributed via physical media such as an optical disc (CD-ROM, DVD-ROM, etc.) or a semiconductor memory (USB memory, etc.), or via a telecommunications line such as the Internet.

[0091] The main program 310 is the core part that enables the computer to function as the circuit design simulator 210, and is formed as a collection of various module programs (e.g., a circuit creation module 311, a component reference module 312, a probe placement module 313, a waveform drawing module 314, and a waveform analysis module 315).

[0092] The circuit creation module 311 is a component program that causes the calculation unit 211 and the display unit 214 to function so as to create a circuit on the circuit design simulator 210 based on input from the operation unit 213. When a user uses the operation unit 213 to place component symbols (resistors, capacitors, transistors, diodes, semiconductor integrated circuit devices, voltage sources, current sources, wiring, etc.) displayed on the display unit 214 in the circuit creation field, the circuit creation module 311 creates text-based code according to the placement. This allows the user to intuitively create any analog circuit without directly editing the text-based code.

[0093] The component reference module 312 is an element program for causing the calculation unit 211 and the display unit 214 to function so as to refer to the model library 320 based on an input from the operation unit 213. For example, when a user uses the operation unit 213 to select a symbol for a semiconductor integrated circuit device from a component palette displayed on the display unit 214, the component reference module 312 refers to a macro model 323 (corresponding to the aforementioned macro model 10) of the semiconductor integrated circuit device included in the model library 320.

[0094] The probe installation module 313 is a component program for causing the calculation unit 211 and the display unit 214 to function so as to install a probe (a voltage or current measurement point) on the circuit diagram based on an input from the operation unit 213. For example, when a user uses the operation unit 213 to click with a mouse on a specific node on the circuit diagram displayed on the display unit 214, the probe installation module 313 installs a probe at the clicked node.

[0095] The waveform drawing module 314 is a component program for causing the calculation unit 211 and the display unit 214 to function so as to draw a waveform of a node where a probe is placed, based on an input from the operation unit 213. For example, when a user uses the operation unit 213 to place a probe on an output terminal of a semiconductor integrated circuit device displayed on the display unit 214, the waveform drawing module 314 displays the output waveform (pseudo oscilloscope waveform) appearing at the output terminal of the semiconductor integrated circuit device in a waveform drawing window.

[0096] The waveform analysis module 315 is a component program for causing the calculation unit 211 and the display unit 214 to function so as to perform waveform analysis of a node where a probe is installed based on input from the operation unit 213. Examples of waveform analysis that can be performed by the waveform analysis module 315 include transient analysis, DC analysis, small signal AC analysis, and noise analysis.

[0097] The model library 320 includes various simulation models (such as a passive element model 321, an active element model 322, and a macro model 323) used in the circuit design simulator 210, and is referenced by the main program 310 (particularly the component reference module 312) as part of the circuit design simulation program 300.

[0098] The passive element model 321 is a program that causes a computer to operate so as to simulate the response of passive elements (resistors, capacitors, etc.) on the circuit design simulator 210 .

[0099] The active element model 322 is a program that causes a computer to operate so as to simulate the response of an active element (transistor, diode, etc.) on the circuit design simulator 210 .

[0100] The macro model 323 (corresponding to the macro model 10 mentioned above) of the semiconductor integrated circuit device is a program that causes a computer to operate on the circuit design simulator 210 so as to simulate the response of the semiconductor integrated circuit device.

[0101] It should be noted that some of the above-mentioned simulation models (passive element model 321, active element model 322, macro model 323) can be downloaded free of charge via telecommunications line 220 from servers 230X to 230Z of vendors that manufacture and sell semiconductor integrated circuit devices.

[0102] By using such a circuit design simulation program 300, it becomes possible to use a general-purpose computer (such as a personal computer or a workstation) as the circuit design simulator 210.

[0103] <Summary> The various embodiments described above will be summarized below.

[0104] For example, the macro model of a semiconductor integrated circuit device disclosed in this specification is used in a circuit design simulator and has a configuration (first configuration) including a virtual input terminal configured to receive parameters of the semiconductor integrated circuit device as virtual input signals, and a functional block configured to approximately or equivalently represent characteristics and behavior of the semiconductor integrated circuit device on the circuit design simulator based on the virtual input signal received at the virtual input terminal.

[0105] In the macro model according to the first configuration, the parameters may be configured (second configuration) to include at least one of the operation mode, output current, output voltage, drive frequency, on-duty, frequency characteristics, and slew rate of the semiconductor integrated circuit device.

[0106] In the macro model according to the first or second configuration, the virtual input signal may include an analog signal having a voltage value or a current value according to the set value of the parameter (third configuration).

[0107] In the macro model according to any one of the first to third configurations, the virtual input signal may be configured (fourth configuration) to include a pulse-modulated signal that is modulated in accordance with the set value of the parameter.

[0108] In addition, in the macro model having any one of the first to fourth configurations, the semiconductor integrated circuit device may be configured as a light emitting element driving device (fifth configuration).

[0109] In the macro model according to the fifth configuration, the functional block may be a power supply block that generates an output current and an output voltage to be supplied to the light-emitting element (sixth configuration).

[0110] Furthermore, the macro model according to any one of the first to sixth configurations may be configured (seventh configuration) to further include a virtual output terminal configured to output the abnormality detection result of the semiconductor integrated circuit device as a virtual output signal.

[0111] Furthermore, for example, the circuit design simulation program disclosed in this specification is executed by a computer having an arithmetic unit, causing the computer to function as the circuit design simulator, and includes a macro model according to any one of the first to seventh configurations, and is configured to operate the computer so as to simulate the response of a semiconductor integrated circuit device on the circuit design simulator (eighth configuration).

[0112] The circuit design simulation program according to the eighth configuration further includes a conversion module configured to convert a communication signal conforming to a predetermined protocol into the virtual input signal (ninth configuration).

[0113] Furthermore, for example, the circuit design simulator disclosed in this specification has a configuration (tenth configuration) that is realized by causing a computer to execute the circuit design simulation program according to the eighth or ninth configuration.

[0114] <Other Modifications> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0115] 10 Macro model 11a Virtual input terminal 11b Virtual output terminal 12 Functional block 20 Conversion module 100 Semiconductor integrated circuit device 110 Power supply device (step-up DC / DC converter) 120 Control device (MCU) 210 Circuit design simulator (computer) 211 Calculation unit 212 Memory unit 213 Operation unit 214 Display unit 215 Communication unit 220 Telecommunication line (Internet) 230X, 230Y, 230Z Server 300 Circuit design simulation program 310 Main program 311 Circuit creation module 312 Component reference module 313 Probe placement module 314 Waveform drawing module 315 Waveform analysis module 320 Model library 321 Passive element model 322 Active element model 323 Macro model C1 to C23 Capacitors L1 to L4 Inductors LED1 to LED3, LED: Light emitting element R1 to R22: Resistor X: Light emitting device

Claims

1. A macro model of a semiconductor integrated circuit device used in a circuit design simulator, a virtual input terminal configured to receive a parameter of the semiconductor integrated circuit device as a virtual input signal; a functional block configured to approximately or equivalently represent characteristics and behavior of the semiconductor integrated circuit device on the circuit design simulator based on the virtual input signal received at the virtual input terminal; A macro model comprising:

2. 2. The macro model according to claim 1, wherein the parameters include at least one of an operation mode, an output current, an output voltage, a drive frequency, an on-duty, a frequency characteristic, and a slew rate of the semiconductor integrated circuit device.

3. The macro model according to claim 1 , wherein the virtual input signal includes an analog signal having a voltage value or a current value according to a setting value of the parameter.

4. The macro model according to claim 1 , wherein the virtual input signal includes a pulse modulated signal that is modulated in response to a setting value of the parameter.

5. 2. The macro model according to claim 1, wherein the semiconductor integrated circuit device is a light emitting element driving device.

6. The macro model according to claim 5 , wherein the functional block is a power supply block that generates an output current and an output voltage to be supplied to a light-emitting element.

7. 2. The macro model according to claim 1, further comprising a virtual output terminal configured to output a result of the abnormality detection of said semiconductor integrated circuit device as a virtual output signal.

8. A circuit design simulation program that is executed by a computer having a calculation unit and causes the computer to function as the circuit design simulator, 8. A circuit design simulation program comprising at least one macro model according to claim 1, said circuit design simulation program causing said computer to operate so as to simulate a response of a semiconductor integrated circuit device on said circuit design simulator.

9. 9. The circuit design simulation program according to claim 8, further comprising a conversion module configured to convert a communication signal conforming to a predetermined protocol into the virtual input signal.

10. A circuit design simulator that is realized by causing a computer to execute the circuit design simulation program according to claim 8.