Silicon carbide substrate, silicon carbide epitaxial substrate, and method for manufacturing silicon carbide semiconductor device

Abstract

This silicon carbide substrate has a main surface. The main surface is composed of an outer peripheral portion within 3 mm from the outer periphery of the main surface, and a central portion surrounded by the outer peripheral portion. In an arbitrary square area in the central portion, the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is at least 0. The length of one side of the square area is 250 μm.

Description

Silicon carbide substrate, silicon carbide epitaxial substrate, and method for manufacturing silicon carbide semiconductor device

[0001] The present disclosure relates to a silicon carbide substrate, a silicon carbide epitaxial substrate, and a method for manufacturing a silicon carbide semiconductor device. This application claims priority to Japanese Patent Application No. 2022-126501, filed on August 8, 2022. The entire contents of this Japanese patent application are incorporated herein by reference.

[0002] International Publication No. 2016 / 063632 (Patent Document 1) describes a silicon carbide substrate having a main surface with a surface roughness of 0.1 nm or less.

[0003] International Publication No. 2016 / 063632

[0004] A silicon carbide substrate according to the present disclosure has a main surface. The main surface is composed of an outer peripheral portion within 3 mm from the outer peripheral edge of the main surface and a central portion surrounded by the outer peripheral portion. In any square region in the central portion, the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is 0 or greater. The length of one side of the square region is 250 μm.

[0005] FIG. 1 is a schematic plan view showing the configuration of a silicon carbide substrate according to this embodiment. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a schematic plan view showing the configuration of region III in FIG. 1. FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 3. FIG. 5 is a schematic view showing a step of performing chemical mechanical polishing on a silicon carbide substrate. FIG. 6 is a flowchart outlining a method for manufacturing a silicon carbide semiconductor device according to this embodiment. FIG. 7 is a schematic cross-sectional view showing the configuration of a silicon carbide epitaxial substrate according to this embodiment. FIG. 8 is a schematic cross-sectional view showing a step of forming a body region. FIG. 9 is a schematic cross-sectional view showing a step of forming a source region. FIG. 10 is a schematic cross-sectional view showing a step of forming a trench in a third main surface of a silicon carbide epitaxial layer. FIG. 11 is a schematic cross-sectional view showing a step of forming a gate insulating film. FIG. 12 is a schematic cross-sectional view showing a step of forming a gate electrode and an interlayer insulating film. FIG. 13 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this embodiment. Fig. 14 is a diagram showing the relationship between Sa and Ssk, and Fig. 15 is a diagram showing the relationship between Sa and the breakdown voltage defect rate.

[0006] [Problem to be solved by this disclosure]

[0007] An object of the present disclosure is to improve the yield of silicon carbide semiconductor devices.

[0008] According to the present disclosure, the yield of silicon carbide semiconductor devices can be improved.

[0009] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] (1) Silicon carbide substrate 100 according to the present disclosure has a main surface 1. Main surface 1 is configured with a peripheral portion 12 located within 3 mm from a peripheral edge 4 of main surface 1, and a central portion 10 surrounded by peripheral portion 12. In any square region 5 in central portion 10, the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is 0 or greater. The length of one side of square region 5 is 250 μm.

[0011] (2) According to silicon carbide substrate 100 in accordance with (1) above, skewness defined as Ssk may be equal to or less than 0.4.

[0012] (3) According to silicon carbide substrate 100 in accordance with (1) above, skewness defined as Ssk may be equal to or less than 0.3.

[0013] (4) According to silicon carbide substrate 100 according to any one of (1) to (3) above, the arithmetic mean height defined as Sa may be equal to or greater than 0.06 nm.

[0014] (5) According to silicon carbide substrate 100 according to (1) above, the arithmetic mean height defined as Sa may be equal to or greater than 0.06 nm, and the skewness defined as Ssk may be equal to or less than 0.3.

[0015] (6) According to silicon carbide substrate 100 according to any one of (1) to (5) above, the main surface may have a maximum diameter of 150 mm or more.

[0016] (7) A silicon carbide epitaxial substrate 200 according to the present disclosure includes the silicon carbide substrate 100 according to any one of (1) to (6) above, and a silicon carbide epitaxial layer 20 provided on the silicon carbide substrate 100.

[0017] (8) A method for manufacturing silicon carbide semiconductor device 400 according to the present disclosure includes the following steps: Silicon carbide epitaxial substrate 200 as described in (7) above is prepared. Silicon carbide epitaxial substrate 200 is processed. [Details of Embodiments of the Present Disclosure] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that identical or corresponding parts in the following drawings are designated with the same reference numerals, and descriptions thereof will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. Furthermore, for negative indices, in crystallography, a "-" (bar) is placed before the number, but in this specification, a negative sign is placed before the number.

[0018] <Silicon Carbide Substrate> First, the configuration of silicon carbide substrate 100 according to this embodiment will be described. Fig. 1 is a plan view schematically showing the configuration of silicon carbide substrate 100 according to this embodiment. Fig. 2 is a cross-sectional view schematically showing the configuration of silicon carbide substrate 100 along line II-II in Fig. 1.

[0019] As shown in Figures 1 and 2, silicon carbide substrate 100 according to this embodiment mainly has a first main surface 1, a second main surface 2, an outer peripheral edge 4, and an outer peripheral side surface 9. The second main surface 2 is located on the opposite side to first main surface 1. The outer peripheral side surface 9 is continuous with each of first main surface 1 and second main surface 2. The outer peripheral edge 4 is the boundary between first main surface 1 and outer peripheral side surface 9. First main surface 1 is composed of a central portion 10 and an outer peripheral portion 12. Central portion 10 is surrounded by outer peripheral portion 12. Central portion 10 is continuous with outer peripheral portion 12.

[0020] 1 , when viewed in a direction perpendicular to the first main surface 1, the first main surface 1 extends along each of a first direction 101 and a second direction 102. When viewed in a direction perpendicular to the first main surface 1, the second direction 102 is a direction perpendicular to the first direction 101. The outer peripheral edge 4 of the first main surface 1 has, for example, an orientation flat 7 and an arc-shaped portion 8.

[0021] 1 , the orientation flat 7 is linear when viewed in a direction perpendicular to the first main surface 1. The orientation flat 7 extends along a first direction 101. The arc-shaped portion 8 is continuous with the orientation flat 7. The arc-shaped portion 8 is arc-shaped when viewed in a direction perpendicular to the first main surface 1.

[0022] The first direction 101 is, for example, the <11-20> direction. The first direction 101 may be, for example, the [11-20] direction. The first direction 101 may be a direction obtained by projecting the <11-20> direction onto the first main surface 1. From another perspective, the first direction 101 may be, for example, a direction including a <11-20> direction component.

[0023] The second direction 102 is, for example, the <1-100> direction. The second direction 102 may be, for example, the [1-100] direction. The second direction 102 may be, for example, a direction obtained by projecting the <1-100> direction onto the first main surface 1. From another perspective, the second direction 102 may be, for example, a direction including a <1-100> direction component.

[0024] First main surface 1 may be a {0001} plane, or may be a plane inclined with respect to the {0001} plane. When first main surface 1 is inclined with respect to the {0001} plane, the inclination angle (off angle θ) with respect to the {0001} plane is, for example, 1° or more and 8° or less. When first main surface 1 is inclined with respect to the {0001} plane, the inclination direction (off direction) of first main surface 1 is, for example, the <11-20> direction. The off angle θ may be 2° or more and 6° or less.

[0025] The maximum diameter W1 of the first main surface 1 is, for example, 100 mm (4 inches) or more. The maximum diameter W1 of the first main surface 1 may be 150 mm (6 inches) or more, or may be 200 mm (8 inches) or more. The maximum diameter W1 of the first main surface 1 is not particularly limited, but may be, for example, 400 mm (16 inches) or less.

[0026] When viewed in a direction perpendicular to the first main surface 1, the maximum diameter W1 of the first main surface 1 is the longest linear distance between two different points on the outer circumferential edge 4. When viewed in a direction perpendicular to the first main surface 1, the outer circumferential portion 12 is a region within 3 mm from the outer circumferential edge 4 of the first main surface 1. From another perspective, the width W2 of the outer circumferential portion 12 in a direction extending radially from the center of the first main surface 1 (radial direction) is 3 mm.

[0027] In this specification, 4 inches refers to 100 mm or 101.6 mm (4 inches x 25.4 mm / inch). 6 inches refers to 150 mm or 152.4 mm (6 inches x 25.4 mm / inch). 8 inches refers to 200 mm or 203.2 mm (8 inches x 25.4 mm / inch). 16 inches refers to 400 mm or 406.4 mm (16 inches x 25.4 mm / inch).

[0028] 3 is a plan view schematically illustrating the configuration of region III in FIG. 1. As shown in FIG. 3, central portion 10 has a square region 5. The length of one side of square region 5 is 250 μm. When viewed in a direction perpendicular to first main surface 1, a first side of square region 5 is parallel to, for example, first direction 101. When viewed in a direction perpendicular to first main surface 1, a second side of square region 5 is parallel to, for example, second direction 102.

[0029] As shown in Fig. 3, local recesses 6 may be formed in central portion 10. Local recesses 6 are holes formed by scraping away parts of silicon carbide substrate 100 with abrasive grains. It is desirable that the number of local recesses 6 is small. The number of local recesses 6 in square region 5 is not particularly limited, and may be, for example, two or less, one or less, or zero.

[0030] Fig. 4 is a schematic cross-sectional view taken along line IV-IV in Fig. 3. As shown in Fig. 4, the local recess 6 is composed of a side surface 62 and a bottom surface 61. The side surface 62 is continuous with the first main surface 1. The bottom surface 61 is continuous with the side surface 62. In the first direction 101, the length W3 of the local recess 6 is approximately the same as the diameter of the abrasive grain.

[0031] The length W3 of the local recess 6 is not particularly limited, but may be, for example, 1 μm or more and 50 μm or less. The length W3 of the local recess 6 is not particularly limited, but may be, for example, 10 μm or more, or 20 μm or more. The length W3 of the local recess 6 is not particularly limited, but may be, for example, 45 μm or less, or 40 μm or less.

[0032] The depth D of the local recess 6 is smaller than the length W3 of the local recess 6. The depth D of the local recess 6 is not particularly limited, and may be one-fifth or less of the length W3 of the local recess 6, or may be one-tenth or less of the length W3 of the local recess 6. The depth D of the local recess 6 is not particularly limited, and is, for example, 1 μm or more and 5 μm or less.

[0033] According to silicon carbide substrate 100 according to this embodiment, in any square region 5 in central portion 10, the arithmetic mean height defined as Sa is 0.1 nm or less, and the skewness defined as Ssk is 0 or more. Sa and Ssk are used as indices for quantifying the surface roughness of silicon carbide substrate 100. When Ssk is 0, the height distribution on the surface is symmetric in the vertical direction. When Ssk is greater than 0, the surface has many fine peaks. When Ssk is less than 0, the surface has many fine valleys.

[0034] The arithmetic mean height defined as Sa may be, for example, 0.06 nm or more, 0.07 nm or more, or 0.08 nm or more. The arithmetic mean height defined as Sa may be, for example, 0.95 nm or less, or 0.9 nm or less.

[0035] The skewness defined as Ssk may be, for example, 0.4 or less, 0.3 or less, or 0.25 or less, and may be, for example, 0.01 or more, 0.05 or more, or 0.1 or more.

[0036] According to silicon carbide substrate 100 according to the present embodiment, in any square region 5 in central portion 10, the arithmetic mean height defined as Sa may be 0.06 nm or more and 0.1 nm or less, and the skewness defined as Ssk may be 0 or more and 0.3 or less. The arithmetic mean height defined as Sa may be 0.07 nm or more and 0.09 nm or less, and the skewness defined as Ssk may be 0.01 or more and 0.25 or less.

[0037] Next, a method for measuring the arithmetic mean height defined as Sa and the skewness defined as Ssk will be described.

[0038] The arithmetic mean height defined as Sa and the skewness defined as Ssk can be measured, for example, using a white light interference microscope. A Nikon BW-D507 can be used as the white light interference microscope. The objective lens has a magnification of, for example, 20x. Sa is a parameter obtained by expanding Ra, which is the two-dimensional arithmetic mean roughness, into three dimensions. Sa and Ssk are each three-dimensional surface texture parameters defined in the international standard ISO 25178. The measurement area for Sa and Ssk is a square area 5 with a side length of 250 μm.

[0039] <Method for Manufacturing Silicon Carbide Substrate> Next, a method for manufacturing silicon carbide substrate 100 according to this embodiment will be described.

[0040] First, a crystal growth step is carried out. Specifically, a silicon carbide single crystal is formed by sublimation. Next, the silicon carbide single crystal is cut into a plurality of silicon carbide substrates 100 by a saw wire.

[0041] Next, a double-side mechanical polishing step is performed. Specifically, silicon carbide substrate 100 is placed between a first platen (not shown) and a second platen (not shown). Next, slurry is introduced between silicon carbide substrate 100 and the first platen and between silicon carbide substrate 100 and the second platen. The slurry contains, for example, diamond abrasive grains and water. The diameter of the diamond abrasive grains is, for example, not less than 1 μm and not more than 3 μm. In this manner, mechanical polishing is performed on both sides of silicon carbide substrate 100.

[0042] Next, a chemical mechanical polishing step is performed. FIG. 5 is a schematic diagram showing a step of performing chemical mechanical polishing on silicon carbide substrate 100. As shown in FIG. 5, chemical mechanical polishing apparatus 300 has polishing cloth 301, polishing head 302, vibration acceleration sensor 303, vacuum pump 304, and pressure unit 305. Polishing cloth 301 is, for example, a suede polishing cloth (G804W) manufactured by Fujibo Ehime Co., Ltd. Polishing head 302 is, for example, made of ceramic or stainless steel. Vibration acceleration sensor 303 is attached to polishing head 302. Pressure unit 305 is, for example, an air cylinder.

[0043] 5, in the chemical mechanical polishing step, silicon carbide substrate 100 is subjected to chemical mechanical polishing using polishing liquid 310. Polishing liquid 310 contains, for example, abrasive grains 312 and an oxidizing agent 311. Abrasive grains 312 are, for example, colloidal silica. Oxidizing agent 311 is, for example, hydrogen peroxide, permanganate, nitrate, or hypochlorite. Polishing liquid 310 is, for example, DSC-0902 manufactured by Fujimi Incorporated.

[0044] In the chemical mechanical polishing process according to the present disclosure, the silicon carbide substrate 100 is not attached to the polishing head 302 using wax. The silicon carbide substrate 100 is directly attached to the polishing head 302. Specifically, the silicon carbide substrate 100 is vacuum-adsorbed to the polishing head 302 by using a vacuum pump 304.

[0045] In the chemical mechanical polishing process according to the present disclosure, the polishing head 302 is controlled so as to reduce fluctuations in the pressure applied to the silicon carbide substrate 100. Specifically, the vibration of the polishing head 302 is controlled so that the effective value of the vibration acceleration in a frequency band of 1 kHz or less is 20 mG or less. Specifically, the regulator of the air cylinder may be controlled based on the vibration acceleration of the polishing head 302 measured using the vibration acceleration sensor 303. This makes it possible to suppress local pressure fluctuations during the chemical mechanical polishing process.

[0046] Silicon carbide substrate 100 is disposed so as to face polishing cloth 301. A polishing liquid 310 containing abrasive grains 312 is supplied between silicon carbide substrate 100 and polishing cloth 301. The rotation speed of polishing head 302 is, for example, 60 rpm. The rotation speed of a surface plate on which polishing cloth 301 is provided is, for example, 60 rpm. The average processing surface pressure F is, for example, 450 g / cm ２ The flow rate of the polishing liquid is, for example, 2 liters per minute. In this manner, silicon carbide substrate 100 (FIG. 1) according to this embodiment is obtained.

[0047] <Method of Manufacturing Silicon Carbide Semiconductor Device> Next, a method of manufacturing silicon carbide semiconductor device 400 according to this embodiment will be described. Fig. 6 is a flowchart that schematically shows the method of manufacturing silicon carbide semiconductor device 400 according to this embodiment. As shown in Fig. 6, the method of manufacturing silicon carbide semiconductor device 400 according to this embodiment mainly includes a step (S1) of preparing silicon carbide epitaxial substrate 200 and a step (S2) of processing silicon carbide epitaxial substrate 200.

[0048] First, there is performed the step (S1) of preparing silicon carbide epitaxial substrate 200. In the step (S1) of preparing silicon carbide epitaxial substrate 200, first, silicon carbide substrate 100 according to the present embodiment is prepared (see FIG. 1 ).

[0049] Next, silicon carbide epitaxial layer 20 is formed on silicon carbide substrate 100. Specifically, silicon carbide epitaxial layer 20 is formed by epitaxial growth on first main surface 1 of silicon carbide substrate 100. In the epitaxial growth, for example, silane (SiH4) and propane (C3H8) are used as source gases, and hydrogen (H2) is used as a carrier gas. The temperature of the epitaxial growth is, for example, approximately 1400°C or higher and 1700°C or lower. In the epitaxial growth, an n-type impurity such as nitrogen is introduced into silicon carbide epitaxial layer 20. In this way, silicon carbide epitaxial substrate 200 according to this embodiment is prepared.

[0050] Fig. 7 is a cross-sectional schematic diagram showing the configuration of a silicon carbide epitaxial substrate according to this embodiment. As shown in Fig. 7, the silicon carbide epitaxial substrate according to this embodiment has a silicon carbide substrate 100 and a silicon carbide epitaxial layer 20. The silicon carbide epitaxial layer 20 is provided on the silicon carbide substrate 100.

[0051] Silicon carbide epitaxial layer 20 may have a buffer layer 41, a drift layer 42, and a third main surface 3. Buffer layer 41 is in contact with silicon carbide substrate 100. Drift layer 42 is provided on buffer layer 41. The nitrogen concentration contained in drift layer 42 may be lower than the nitrogen concentration contained in buffer layer 41. Third main surface 3 is formed of drift layer 42.

[0052] Next, a step (S2) is performed of processing silicon carbide epitaxial substrate 200. Specifically, silicon carbide epitaxial substrate 200 is processed as follows: First, ions are implanted into silicon carbide epitaxial substrate 200.

[0053] 8 is a schematic cross-sectional view showing a step of forming a body region. In the step of forming the body region, p-type impurities such as aluminum are ion-implanted into third main surface 3 of silicon carbide epitaxial layer 20. This forms body region 113 having p-type conductivity. Portions where body region 113 is not formed become drift layer 42 and buffer layer 41. The thickness of body region 113 is, for example, 0.9 μm. Silicon carbide epitaxial layer 20 includes buffer layer 41, drift layer 42, and body region 113.

[0054] Next, a step of forming a source region is performed. FIG. 9 is a schematic cross-sectional view showing the step of forming the source region. Specifically, n-type impurities such as phosphorus are ion-implanted into the body region 113. This forms a source region 114 having n-type conductivity. The thickness of the source region 114 is, for example, 0.4 μm. The concentration of the n-type impurities contained in the source region 114 is higher than the concentration of the p-type impurities contained in the body region 113.

[0055] Next, a p-type impurity such as aluminum is ion-implanted into the source region 114 to form a contact region 118. The contact region 118 is formed to penetrate the source region 114 and the body region 113 and to be in contact with the drift layer 42. The concentration of the p-type impurity contained in the contact region 118 is higher than the concentration of the n-type impurity contained in the source region 114.

[0056] Next, activation annealing is performed to activate the implanted impurities. The temperature of the activation annealing is, for example, 1500° C. or higher and 1900° C. or lower. The activation annealing time is, for example, about 30 minutes. The atmosphere of the activation annealing is, for example, an argon atmosphere.

[0057] Next, a step of forming trenches in the third main surface 3 of the silicon carbide epitaxial layer 20 is performed. FIG. 10 is a cross-sectional schematic diagram showing the step of forming trenches in the third main surface 3 of the silicon carbide epitaxial layer 20. A mask 117 having openings is formed on the third main surface 3 including the source region 114 and the contact region 118. The source region 114, the body region 113, and a portion of the drift layer 42 are removed by etching using the mask 117. For example, inductively coupled plasma reactive ion etching can be used as the etching method. Specifically, for example, inductively coupled plasma reactive ion etching using SF or a mixed gas of SF and O as the reactive gas is used. A recess is formed in the third main surface 3 by etching.

[0058] Next, thermal etching is performed on the recesses. Thermal etching can be performed, for example, by heating the mask 117 formed on the third main surface 3 in an atmosphere containing a reactive gas having at least one type of halogen atom. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere can include, for example, Cl2, BCl3, SF6, or CF4. For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as the reactive gas, and setting the heat treatment temperature to, for example, 700°C or higher and 1000°C or lower. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. Examples of the carrier gas that can be used include nitrogen gas, argon gas, and helium gas.

[0059] 10 , a trench 56 is formed in the third main surface 3 by thermal etching. The trench 56 is defined by a sidewall surface 53 and a bottom wall surface 54. The sidewall surface 53 is formed by the source region 114, the body region 113, and the drift layer 42. The bottom wall surface 54 is formed by the drift layer 42. Next, the mask 117 is removed from the third main surface 3.

[0060] Next, a step of forming a gate insulating film is performed. FIG. 11 is a schematic cross-sectional view showing the step of forming a gate insulating film. Specifically, silicon carbide epitaxial substrate 200 having trench 56 formed in third main surface 3 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. This forms gate insulating film 115 that is in contact with drift layer 42 at bottom wall surface 54, in contact with drift layer 42, body region 113, and source region 114 at sidewall surface 53, and in contact with source region 114 and contact region 118 at third main surface 3.

[0061] Next, a step of forming a gate electrode is performed. FIG. 12 is a schematic cross-sectional view showing the step of forming a gate electrode and an interlayer insulating film. The gate electrode 127 is formed inside the trench 56 so as to be in contact with the gate insulating film 115. The gate electrode 127 is disposed inside the trench 56 and is formed on the gate insulating film 115 so as to face each of the sidewall surface 53 and the bottom wall surface 54 of the trench 56. The gate electrode 127 is formed by, for example, a low pressure chemical vapor deposition (LPCVD) method.

[0062] Next, an interlayer insulating film 126 is formed. The interlayer insulating film 126 is formed so as to cover the gate electrode 127 and to be in contact with the gate insulating film 115. The interlayer insulating film 126 is formed by, for example, chemical vapor deposition. The interlayer insulating film 126 is made of, for example, a material containing silicon dioxide. Next, the interlayer insulating film 126 and part of the gate insulating film 115 are etched so as to form openings over the source region 114 and the contact region 118. As a result, the contact region 118 and the source region 114 are exposed from the gate insulating film 115.

[0063] Next, a step of forming a source electrode is performed. The source electrode 116 is formed so as to be in contact with each of the source region 114 and the contact region 118. The source electrode 116 is formed by, for example, a sputtering method. The source electrode 116 is made of, for example, a material containing Ti (titanium), Al (aluminum), and Si (silicon).

[0064] Next, alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is maintained at a temperature of, for example, 900° C. or higher and 1100° C. or lower for about 5 minutes. As a result, at least a portion of the source electrode 116 is silicided. This forms the source electrode 116 in ohmic contact with the source region 114. The source electrode 116 may also form an ohmic contact with the contact region 118.

[0065] Next, the source wiring 119 is formed. The source wiring 119 is electrically connected to the source electrode 116. The source wiring 119 is formed so as to cover the source electrode 116 and the interlayer insulating film 126.

[0066] Next, a step of forming a drain electrode is carried out. First, silicon carbide substrate 100 is polished at second main surface 2. This reduces the thickness of silicon carbide substrate 100. Next, drain electrode 123 is formed. Drain electrode 123 is formed so as to be in contact with second main surface 2. In this manner, silicon carbide semiconductor device 400 according to this embodiment is manufactured.

[0067] 13 is a cross-sectional schematic diagram showing the configuration of a silicon carbide semiconductor device according to this embodiment. The silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The silicon carbide semiconductor device 400 mainly includes a silicon carbide epitaxial substrate 200, a gate electrode 127, a gate insulating film 115, a source electrode 116, a drain electrode 123, a source wiring 119, and an interlayer insulating film 126. The silicon carbide epitaxial substrate 200 includes a buffer layer 41, a drift layer 42, a body region 113, a source region 114, and a contact region 118. The silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like.

[0068] Next, the effects of the methods for manufacturing silicon carbide substrate 100, silicon carbide epitaxial substrate 200, and silicon carbide semiconductor device 400 according to the present embodiment will be described.

[0069] Silicon carbide substrate 100 is required to have an extremely smooth main surface. The arithmetic mean height (Sa) is generally used as an index of surface roughness. However, even when main surface 1 of silicon carbide substrate 100 has a low Sa, the yield of silicon carbide semiconductor devices 400 fabricated using silicon carbide substrate 100 has sometimes been poor.

[0070] The inventors have conducted extensive research into the cause of the deterioration in yield of silicon carbide semiconductor device 400 and have found that minute local recesses 6 that do not affect Sa of main surface 1 adversely affect the yield of silicon carbide semiconductor device 400. It is believed that one of the causes of the deterioration in yield is that the breakdown voltage of silicon carbide semiconductor device 400 is reduced due to a decrease in the thickness of the oxide film formed on local recess 6.

[0071] As a result of further investigation, the inventors have noticed that minute local recesses 6 that do not affect Sa of main surface 1 have a strong correlation with skewness defined as Ssk. Specifically, by setting the arithmetic mean height defined as Sa to 0.1 nm or less and the skewness defined as Ssk to 0 or more on main surface 1 of silicon carbide substrate 100, it is possible to improve the yield of silicon carbide semiconductor device 400.

[0072] Silicon carbide is a material with extremely high hardness. Therefore, when silicon carbide substrate 100 is polished, a high load is applied to silicon carbide substrate 100. When silicon carbide substrate 100 is polished using a polishing liquid containing abrasive grains, local pressure fluctuations may occur due to micro-vibrations during pressure application, and local recesses 6 may be formed on the surface of silicon carbide substrate 100. In the method for manufacturing silicon carbide substrate 100 according to the present disclosure, chemical mechanical polishing is performed on silicon carbide substrate 100 while suppressing local pressure fluctuations.

[0073] As a first improvement, in the chemical mechanical polishing process according to the present disclosure, the silicon carbide substrate 100 is attached directly to the polishing head without using wax. Typically, the silicon carbide substrate 100 is attached to the polishing head, which serves as a support, using wax. At this time, the silicon carbide substrate 100 is attached to the polishing head via the wax by pressing the silicon carbide substrate 100. When the silicon carbide substrate 100 is pressed, foreign matter may become trapped in the silicon carbide substrate 100, resulting in the formation of a recess in the silicon carbide substrate 100. In the chemical mechanical polishing process according to the present disclosure, the silicon carbide substrate 100 is attached directly to the polishing head without using wax, thereby making it possible to prevent the formation of a local recess 6 in the silicon carbide substrate 100.

[0074] As a second improvement, in the chemical mechanical polishing process according to the present disclosure, polishing head 302 is controlled to reduce fluctuations in pressure applied to silicon carbide substrate 100. Specifically, the vibration of polishing head 302 is controlled so that the effective value of the vibration acceleration in a frequency band of 1 kHz or less is 20 mG or less. This makes it possible to suppress the occurrence of local pressure fluctuations during the chemical mechanical polishing process. As a result, it is possible to suppress the formation of local recesses 6 in silicon carbide substrate 100.

[0075] According to silicon carbide substrate 100 in accordance with the present embodiment, the arithmetic mean height defined as Sa is equal to or less than 0.1 nm, and the skewness defined as Ssk is equal to or greater than 0. This enables the yield of silicon carbide semiconductor devices 400 to be improved.

[0076] According to silicon carbide substrate 100 in accordance with this embodiment, the skewness defined as Ssk may be equal to or less than 0.4, which can further improve the yield of silicon carbide semiconductor devices 400.

[0077] According to silicon carbide substrate 100 in accordance with this embodiment, the skewness defined as Ssk may be equal to or less than 0.3, which can further improve the yield of silicon carbide semiconductor devices 400.

[0078] According to silicon carbide substrate 100 in accordance with this embodiment, the arithmetic mean height defined as Sa may be equal to or greater than 0.06 nm, thereby enabling a further improvement in the yield of silicon carbide semiconductor devices 400.

[0079] In silicon carbide substrate 100 according to this embodiment, the arithmetic mean height defined as Sa may be 0.06 nm or more, and the skewness defined as Ssk may be 0.3 or less, thereby enabling a further improvement in the yield of silicon carbide semiconductor devices 400.

[0080] According to silicon carbide substrate 100 in accordance with the present embodiment, the maximum diameter of the main surface may be 150 mm or more. This makes it possible to improve the yield of silicon carbide semiconductor devices 400 even when silicon carbide substrate 100 with a large diameter is used.

[0081] Next, examples will be described. Silicon carbide substrates 100 according to samples 1-1 to 1-5 were manufactured using the chemical mechanical polishing process of group G1. Silicon carbide substrates 100 according to samples 2-1 to 2-4 were manufactured using the chemical mechanical polishing process of group G2. Silicon carbide substrates 100 according to samples 3-1 to 3-12 were manufactured using the chemical mechanical polishing process of group G3.

[0082] In the chemical mechanical polishing process for groups G1, G2, and G3, the abrasive grains 312 were colloidal silica. The polishing liquid 310 was DSC-0902 manufactured by Fujimi Incorporated. The rotation speed of the polishing head 302 was 60 rpm. The rotation speed of the surface plate on which the polishing cloth 301 was provided was 60 rpm. The average processing surface pressure F was 450 g / cm. ２ The flow rate of the polishing liquid was 2 liters per minute.

[0083] In the chemical mechanical polishing process for group G1, the silicon carbide substrate 100 was attached to the polishing head 302 using wax. On the other hand, in the chemical mechanical polishing processes for groups G2 and G3, the silicon carbide substrate 100 was directly attached to the polishing head 302 without using wax.

[0084] In the chemical mechanical polishing processes of groups G1 and G2, vibration control of the polishing head 302 was not performed. On the other hand, in the chemical mechanical polishing process of group G3, vibration control of the polishing head 302 was performed. Specifically, the vibration of the polishing head 302 was controlled so that the effective value of the vibration acceleration in a frequency band of 1 kHz or less was 20 mG or less.

[0085] Next, Sa and Ssk were measured in central portions 10 of silicon carbide substrates 100 according to Samples 1-1 to 3-12. Sa and Ssk were measured using a white light interference microscope (Nikon BW-D507). The measurement region for Sa and Ssk was a square region 5 with a side length of 250 μm. MOSFETs were fabricated using silicon carbide substrates 100 according to Samples 1-1 to 3-12, and the breakdown voltage defect rates of the MOSFETs were determined.

[0086]

[0087] Table 1 shows Sa and Ssk in central portion 10 of silicon carbide substrate 100 according to Samples 1-1 to 1-5, and the breakdown voltage defect rates of MOSFETs fabricated using silicon carbide substrate 100. Sa was equal to or greater than 0.117 nm and equal to or less than 0.133 nm. Ssk was equal to or greater than −0.092 and equal to or less than 0.297. The breakdown voltage defect rate was equal to or greater than 29% and equal to or less than 35%.

[0088]

[0089] Table 2 shows Sa and Ssk in central portion 10 of silicon carbide substrate 100 according to Samples 2-1 to 2-4, and the breakdown voltage failure rates of MOSFETs fabricated using silicon carbide substrate 100. Sa was equal to or greater than 0.078 nm and equal to or less than 0.095 nm. Ssk was equal to or greater than −0.427 and equal to or less than −0.015. The breakdown voltage failure rate was equal to or greater than 27% and equal to or less than 31%.

[0090]

[0091] Table 3 shows Sa and Ssk in central portion 10 of silicon carbide substrate 100 according to Samples 3-1 to 3-12, and the breakdown voltage defect rates of MOSFETs fabricated using silicon carbide substrate 100. Sa was equal to or greater than 0.079 nm and equal to or less than 0.095 nm. Ssk was equal to or greater than 0.001 and equal to or less than 0.237. The breakdown voltage defect rate was equal to or greater than 19% and equal to or less than 22%.

[0092] Fig. 14 is a diagram showing the relationship between Sa and Ssk. As shown in Fig. 14, silicon carbide substrates 100 manufactured using the chemical mechanical polishing process of group G2 have low Sa and Ssk less than 0. On the other hand, silicon carbide substrates 100 manufactured using the chemical mechanical polishing process of group G3 have low Sa and Ssk equal to or greater than 0.

[0093] 15 is a diagram showing the relationship between Sa and the breakdown voltage defect rate. As shown in FIG. 15, the breakdown voltage defect rate of silicon carbide semiconductor devices 400 fabricated using silicon carbide substrates 100 manufactured using the chemical mechanical polishing process of group G2 was relatively high. On the other hand, the breakdown voltage defect rate of silicon carbide semiconductor devices 400 fabricated using silicon carbide substrates 100 manufactured using the chemical mechanical polishing process of group G3 was significantly lower. From the above results, it was confirmed that the breakdown voltage defect rate of silicon carbide semiconductor devices 400 can be significantly reduced by setting Sa to 0.1 nm or less and Ssk to 0 or more.

[0094] The present disclosure includes the following embodiments. (Supplementary Note 1) A silicon carbide substrate comprising a main surface, the main surface being configured with an outer periphery within 3 mm from an outer periphery of the main surface and a central portion surrounded by the outer periphery, wherein in any square region in the central portion, an arithmetic mean height defined as Sa is 0.1 nm or less and a skewness defined as Ssk is 0 or greater, and the length of one side of the square region is 250 μm. (Supplementary Note 2) The silicon carbide substrate according to Supplementary Note 1, wherein the skewness defined as Ssk is 0.4 or less. (Supplementary Note 3) The silicon carbide substrate according to Supplementary Note 1, wherein the skewness defined as Ssk is 0.3 or less. (Supplementary Note 4) The silicon carbide substrate according to any one of Supplementary Notes 1 to 3, wherein the arithmetic mean height defined as Sa is 0.06 nm or greater. (Supplementary Note 5) The silicon carbide substrate according to Supplementary Note 1, wherein the arithmetic mean height defined as Sa is 0.06 nm or more, and the skewness defined as Ssk is 0.3 or less. (Supplementary Note 6) The silicon carbide substrate according to any one of Supplementary Notes 1 to 3, wherein the main surface has a maximum diameter of 150 mm or more. (Supplementary Note 7) A silicon carbide epitaxial substrate comprising: the silicon carbide substrate according to any one of Supplementary Notes 1 to 3; and a silicon carbide epitaxial layer provided on the silicon carbide substrate.

[0095] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not the above description, and is intended to include meanings equivalent to the claims and all modifications within the scope thereof.

[0096] 1 First main surface (main surface), 2 Second main surface, 3 Third main surface, 4 Outer periphery, 5 Square region, 6 Local recess, 7 Orientation flat, 8 Arc-shaped portion, 9 Outer periphery side surface, 10 Central portion, 12 Outer periphery, 20 Silicon carbide epitaxial layer, 41 Buffer layer, 42 Drift layer, 53 Side wall surface, 54 Bottom wall surface, 56 Trench, 61 Bottom surface, 62 Side surface, 100 Silicon carbide substrate, 101 First direction, 102 Second direction, 113 Body region, 114 Source region, 115 Gate insulating film, 116 Source electrode, 117 Mask, 118 Contact region, 119 Source wiring, 123 Drain electrode, 126 Interlayer insulating film, 127 Gate electrode, 200 Silicon carbide epitaxial substrate, 300 Chemical mechanical polishing apparatus, 301 Polishing cloth, 302 polishing head, 303 vibration acceleration sensor, 304 vacuum pump, 305 pressure unit, 310 polishing liquid, 311 oxidizer, 312 abrasive grains, 400 silicon carbide semiconductor device, D depth, F average processing surface pressure, W1 maximum diameter, W2 width, W3 length, θ off angle.

Claims

1. A main surface is provided. The main surface is composed of an outer peripheral portion within 3 mm from an outer peripheral edge of the main surface and a central portion surrounded by the outer peripheral portion, In any square region in the central portion, an arithmetic mean height defined as Sa is 0.1 nm or less, and a skewness defined as Ssk is 0 or more, A silicon carbide substrate, wherein the length of one side of the square region is 250 μm.

2. The silicon carbide substrate according to claim 1 , wherein said skewness defined as Ssk is equal to or less than 0.

4.

3. The silicon carbide substrate according to claim 1 , wherein said skewness defined as Ssk is equal to or less than 0.

3.

4. The silicon carbide substrate according to claim 1 , wherein said arithmetic mean height defined as Sa is equal to or greater than 0.06 nm.

5. 2 . The silicon carbide substrate according to claim 1 , wherein said arithmetic mean height defined as Sa is not less than 0.06 nm, and said skewness defined as Ssk is not more than 0.

3.

6. The silicon carbide substrate according to claim 1 , wherein said main surface has a maximum diameter of 150 mm or greater.

7. A silicon carbide substrate according to any one of claims 1 to 5; a silicon carbide epitaxial layer provided on the silicon carbide substrate.

8. A step of preparing a silicon carbide epitaxial substrate according to claim 7; and processing the silicon carbide epitaxial substrate.