Crystal, multilayer structure, element, electronic device, electronic appliance, and system

Abstract

[Problem] To provide a crystal having excellent crystallinity, a multilayer structure, and an element, an electronic device, an electronic appliance, and a system which are obtained using these. [Solution] An electroconductive crystal which includes a crystalline nitride, wherein the crystalline nitride includes a nitride of Hf and Zr. The crystal is used to produce, for example, a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal-semiconductor field-effect transistor (MESFET), a high-electron mobility transistor (HEMT), a metal-oxide-film-semiconductor field-effect transistor (MOSFET), a static induction transistor (SIT), a junction-type field-effect transistor (JFET), an insulated-gate bipolar transistor (IGBT), a light-emitting diode (LED), or a semiconductor device comprising a combination of these.

Description

Crystals, laminated structures, elements, electronic devices, electronic equipment and systems

[0001] The present invention relates to a crystal, a layered structure, an element, an electronic device, an electronic apparatus, and a system.

[0002] Previously, heteroepitaxial growth processes have been investigated, such as growing a gallium nitride crystal film on a sapphire substrate. However, due to differences in thermal expansion coefficients and lattice mismatch, it is not easy to form a high-quality epitaxial film, and the epitaxial film formation process has become complicated and sophisticated, leading to problems such as increased costs.

[0003] In recent years, epitaxial substrates with an adjusted coefficient of thermal expansion (CTE) that substantially matches the epitaxial layer have been studied (see, for example, Patent Document 1). However, the manufacturing process for such epitaxial substrates has become more complex and sophisticated, and fundamental problems have not been solved. In addition, there are problems such as the need to perform surface treatment and polishing after peeling the epitaxial substrate, and further attach electrodes. Therefore, there has been a long-awaited solution to a method that allows for easy formation of epitaxial films of compound semiconductors such as gallium nitride, and further allows for easy manufacture of semiconductor devices.

[0004] Japanese Patent Application Laid-Open No. 2020-161833

[0005] An object of the present invention is to provide a crystal having excellent crystallinity, a layered structure, and an element, an electronic device, an electronic equipment, and a system using the same.

[0006] As a result of intensive research to achieve the above object, the present inventors have found that conductive crystals containing crystalline nitrides, where the crystalline nitrides contain nitrides of Hf and Zr, have excellent crystallinity and are useful for elements, electronic devices, electronic equipment, and systems, and further found that they are useful for crystal growth of nitride functional films, and that these crystals can solve all of the above-mentioned conventional problems at once. Furthermore, after obtaining the above findings, the present inventors have conducted further research and have completed the present invention.

[0007] That is, the present invention relates to the following inventions. [1] A conductive crystal containing a crystalline nitride, characterized in that the crystalline nitride contains nitrides of Hf and Zr. [2] The crystal according to [1] above, wherein the crystalline nitride has a cubic or hexagonal crystal structure. [3] The crystal according to [2] above, wherein the crystalline nitride is oriented in (111), (100), (010), or (0001). [4] The crystal according to any one of [1] to [3] above, wherein the crystalline nitride contains nitrides of Hf at 30 atomic % or more relative to the crystalline nitride. [5] The crystal according to any one of [1] to [4] above, wherein the crystalline nitride contains nitrides of Hf and Zr at 50 atomic % or more relative to the crystalline nitride. [6] The crystal according to any one of [1] to [5] above, which is an electrode. [7] The crystal according to any one of [1] to [6] above, which is in the form of a film. [8] The crystal according to [7], having a film thickness of 1 μm or more. [9] A laminated structure in which a crystal film is laminated directly or via another layer on a crystal substrate, the crystal film being made of the crystal according to any one of [1] to [8].

[10] The laminated structure according to [9], in which the crystal film constitutes part or all of a buffer layer, is a crystal growth substrate.

[11] An element including a crystal or a laminated structure, the element being characterized in that the crystal is the crystal according to any one of [1] to [8], or the laminated structure is the laminated structure according to claim 9 or 10.

[12] The element according to

[11] , which is a piezoelectric element or a semiconductor element.

[13] An electronic device including a crystal or a laminated structure, the electronic device being characterized in that the crystal is the crystal according to any one of [1] to [8], or the laminated structure is the laminated structure according to [9] or

[10] .

[14] The electronic device according to

[13] , which is a piezoelectric device or a semiconductor device.

[15] An electronic device including an electronic device, characterized in that the electronic device is the electronic device described in

[13] or

[14] .

[16] A system including an electronic device, characterized in that the electronic device is the electronic device described in

[15] .

[0008] The crystal and laminated structure of the present invention have excellent crystallinity, and elements, electronic devices, electronic equipment, and systems using the crystal and laminated structure have the effect of improving the properties of their respective functional films.

[0009] FIG. 1 is a diagram schematically showing an example of a preferred embodiment of a laminated structure of the present invention; FIG. 2 is a diagram schematically showing a process of forming a buffer layer; FIG. 3 is a diagram schematically showing an example of a Schottky barrier diode (SBD) according to the present invention; FIG. 4 is a diagram schematically showing a junction barrier Schottky diode (JBS) which is one of preferred embodiments of the present invention; FIG. 5 is a diagram schematically showing an example of a metal semiconductor field effect transistor (MESFET) according to the present invention; FIG. 6 is a diagram schematically showing an example of a high electron mobility transistor (HEMT) according to the present invention; FIG. 7 is a diagram schematically showing an example of a semiconductor device of the present invention where the semiconductor device is a MOSFET; FIG. 8 is a diagram schematically showing an example of a semiconductor device of the present invention where the semiconductor device is a SIT; FIG. 9 is a diagram schematically showing a preferred example of a junction field effect transistor (JFET) of the present invention; FIG. 10 is a diagram schematically showing a preferred example of an insulated gate bipolar transistor (IGBT) of the present invention; FIG. 11 is a diagram schematically showing an example of a semiconductor device where the semiconductor device is a light emitting diode (LED); FIG. 12 is a diagram schematically showing a preferred example of a power supply system; FIG. 13 is a diagram schematically showing a preferred example of a system device; and FIG. 14 is a diagram schematically showing a preferred example of a power supply circuit diagram of a power supply device. FIG. 2 is a diagram schematically illustrating a film forming apparatus preferably used in the examples.

[0010] The crystal of the present invention is a conductive crystal containing a crystalline nitride, characterized in that the crystalline nitride contains nitrides of Hf and Zr. The layered structure of the present invention is a layered structure in which a crystalline film is stacked on a crystal substrate directly or via another layer, characterized in that the crystalline film is made of the crystal. A preferred example of the layered structure is shown in FIG. 1. The layered structure of FIG. 1 has a buffer layer 5 made of the crystal stacked on a crystal substrate 9, and an epitaxial film 1 made of a compound semiconductor stacked on the buffer layer 5. In this specification, the terms "film" and "layer" may be used interchangeably depending on the case or situation.

[0011] In the laminated structure of the present invention, as shown in FIG. 2 , the buffer layer 5 is preferably formed on a crystal substrate 9 using a known crystal growth method using nitrogen. The crystal growth method may be a known method, and may be either a vapor phase crystal growth method or a liquid phase crystal growth method. Examples of the crystal growth method include vapor deposition, CVD, and sputtering. In the present invention, after the buffer layer 5 is formed, an epitaxial film made of a compound semiconductor is preferably formed on the buffer layer using the crystal growth method. By forming the epitaxial film in this manner, the buffer layer is transformed in the crystal growth direction, forming a peak-valley structure at the interface with the epitaxial film, as shown in FIG. 1 . This peak-valley structure makes it easy to obtain a high-quality epitaxial film with excellent crystallinity.

[0012] The crystal substrate (hereinafter also simply referred to as "substrate") is not particularly limited in terms of substrate material, etc., as long as it does not impede the objectives of the present invention, and may be a known crystal substrate. It may be an organic compound or an inorganic compound. In the present invention, it is preferable that the crystal substrate contains an inorganic compound. In the present invention, it is preferable that the substrate has crystals on part or all of its surface, more preferably a crystal substrate having crystals on all or part of the main surface on the crystal growth side, and most preferably a crystal substrate having crystals on the entire main surface on the crystal growth side. The crystal is not particularly limited as long as it does not impede the objectives of the present invention, and the crystal structure is also not particularly limited. It may be any crystal structure, such as a cubic, tetragonal, trigonal, hexagonal, orthorhombic, or monoclinic crystal structure. In the present invention, a cubic or hexagonal crystal structure is preferable, and a crystal oriented in (100) or (200) is more preferable. The crystal substrate may have an off-axis angle, for example, 0.2° to 12.0°. Here, the "off-axis angle" refers to the angle between the substrate surface and the crystal growth plane. The substrate shape is not particularly limited as long as it is plate-shaped and serves as a support for the insulating film. It may be an insulating substrate or a semiconductor substrate. However, in the present invention, the substrate is preferably a Si substrate, more preferably a crystalline Si substrate, and most preferably a crystalline Si substrate oriented in (100). Examples of the substrate material include Si substrates and one or more metals belonging to Groups 3 to 15 of the periodic table, or oxides of these metals. The shape of the substrate is not particularly limited and may be substantially circular (e.g., circular, elliptical, etc.) or polygonal (e.g., triangular, square, rectangular, pentagonal, hexagonal, heptagonal, octagonal, 9-gonal, etc.), and various shapes can be suitably used.

[0013] Furthermore, in the present invention, it is preferable that the crystal substrate has a flat surface, but it is also preferable that the crystal substrate has an uneven shape on part or all of its surface. The crystal substrate having the uneven shape may have an uneven portion consisting of concave or convex portions formed on part or all of its surface. The uneven portion is not particularly limited as long as it consists of convex or concave portions, and may be an uneven portion consisting of convex portions, an uneven portion consisting of concave portions, or an uneven portion consisting of convex and concave portions. Furthermore, the uneven portion may be formed of regular convex or concave portions, or irregular convex or concave portions. In the present invention, it is preferable that the uneven portion is formed periodically, and more preferably, it is patterned periodically and regularly. The shape of the uneven portion is not particularly limited, and examples thereof include stripes, dots, meshes, and random shapes. In the present invention, a dot or stripe shape is preferred, and a dot shape is more preferred. Furthermore, when the concave-convex portions are patterned periodically and regularly, the pattern shape of the concave-convex portions is preferably a polygonal shape such as a triangle, a quadrangle (e.g., a square, a rectangle, or a trapezoid), a pentagon, or a hexagon, a circle, an ellipse, or the like. When the concave-convex portions are formed in a dotted pattern, the lattice shape of the dots is preferably a lattice shape such as a square lattice, an oblique lattice, a triangular lattice, or a hexagonal lattice, and a triangular lattice shape is more preferable. The cross-sectional shape of the concave or convex portions of the concave-convex portions is not particularly limited, but examples thereof include a U-shape, an inverted U-shape, a wave shape, or a polygonal shape such as a triangle, a quadrangle (e.g., a square, a rectangle, or a trapezoid), a pentagon, or a hexagon. The thickness of the crystal substrate is not particularly limited, but is preferably 50 to 2000 μm, and more preferably 100 to 1000 μm.

[0014] The buffer layer is a conductive crystal containing a crystalline nitride. The crystalline nitride is not particularly limited as long as it contains a crystal containing Hf and Zr nitrides. However, in the present invention, the crystal preferably contains HfN and ZrN. By containing HfN and ZrN, even when the epitaxial film is formed by crystal growth of two or more layers, transformations occur in each layer, thereby further improving the crystallinity of the epitaxial film and further improving the controllability of the properties of the functional film at the interface. The crystal preferably has a cubic crystal structure or a hexagonal crystal structure, and preferably contains crystals oriented in (111), (100), (010), or (0001). Furthermore, the crystal preferably contains 30 atomic % or more of Hf nitride relative to the crystalline nitride, and more preferably contains 50 atomic % or more of Hf nitride and Zr nitride relative to the crystalline nitride. The buffer layer can be suitably formed on the crystal substrate by known crystal growth techniques, such as sputtering, using a Hf source, a Zr source, and nitrogen gas at, for example, 350°C to 700°C. The buffer layer may also include a mixed crystal film. The mixed crystal film is not particularly limited as long as it is a crystal film made of a mixed crystal. Suitable examples of the mixed crystal include a mixed crystal containing, in addition to nitrides of Hf and Zr, one or more nitrides selected from Ti, Al, Y, and Ce. Such a preferred mixed crystal not only enhances the stress relaxation effect of the buffer layer, but also improves the film quality of the epitaxial film.

[0015] The epitaxial film is not particularly limited as long as it is a crystal growth film made of a compound semiconductor. The compound semiconductor is also not particularly limited and may be a known compound semiconductor. Examples of the compound semiconductor include nitride semiconductors, carbide semiconductors (e.g., SiC), oxide semiconductors, InP, and GaAs. In the present invention, the compound semiconductor is preferably a wide bandgap semiconductor, and more preferably a nitride semiconductor. Examples of the nitride semiconductor include III-V semiconductors (aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), etc.), or boron nitride (BN). In the present invention, the epitaxial film preferably has a cubic crystal structure or a hexagonal crystal structure, and more preferably is a crystal growth film made of a cubic semiconductor or a hexagonal semiconductor. Examples of the cubic semiconductor or hexagonal semiconductor include c-BN, c-AlN, c-GaN, c-InN, c-SiC, GaAs, AlAs, InAs, GaP, AlP, InP, and mixed crystal semiconductors thereof.

[0016] The laminated structure obtained as described above can be used in a semiconductor device as is or after further processing, etc., according to a conventional method. In the present invention, the buffer layer in the laminated structure can be suitably used as an electrode or buffer layer for ohmic contact or electron emission in the semiconductor device, and the epitaxial film in the laminated structure can be suitably used as a semiconductor layer in the semiconductor device. Furthermore, when the laminated structure is used in a semiconductor device, it may be used as is in the semiconductor device, or other layers (e.g., an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers) may be formed thereon before use. Furthermore, the crystal substrate may be peeled off from the semiconductor device using a known peeling means.

[0017] The semiconductor device is not particularly limited as long as it does not impede the object of the present invention, and may be a known semiconductor device. It may be a vertical device or a horizontal device, but in the present invention, the semiconductor device is preferably a vertical device. Examples of the semiconductor device include diodes and transistors. More specifically, preferred examples include Schottky barrier diodes (SBDs), junction barrier Schottky diodes (JBSs), high electron mobility transistors (HEMTs), metal semiconductor field effect transistors (MESFETs), metal oxide semiconductor field effect transistors (MOSFETs), static induction transistors (SITs), junction field effect transistors (JFETs), insulated gate bipolar transistors (IGBTs), light-emitting diodes (LEDs), and combinations thereof.

[0018] Hereinafter, preferred examples of applying the stacked structure to a semiconductor device, more specifically, applying the buffer layer in the stacked structure to an electrode or buffer layer for ohmic contact or electron emission in the semiconductor device, and applying the epitaxial film in the stacked structure to a semiconductor layer in the semiconductor device will be described with reference to the drawings, but the present invention is not limited to these examples. Note that the semiconductor devices exemplified below may further include other layers (e.g., an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers) as long as the object of the present invention is not impaired, and the crystal substrate, buffer layer, etc. may also be omitted as appropriate.

[0019] 3 shows an example of a Schottky barrier diode (SBD) according to the present invention. The SBD in FIG. 3 includes an n-type semiconductor layer 101, an n-type semiconductor layer 101a, an n+ type semiconductor layer 101b, an insulator layer 104, a Schottky electrode 105a, and an ohmic electrode 105b.

[0020] The material of the electrodes such as the Schottky electrode may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof.

[0021] The electrode can be formed by a known method such as vacuum deposition or sputtering. More specifically, for example, when a Schottky electrode is formed, a layer made of Mo and a layer made of Al are stacked, and the layer made of Mo and the layer made of Al are patterned using a photolithography technique.

[0022] Examples of the material for the insulator layer 104 include GaO, AlGaO, InAlGaO, and AlInZnGaO. ４ , AlN, Hf ２ O ３ , SiN, SiON, Al ２ O ３ , MgO, GdO, SiO ２ or Si ３ N ４ The insulator layer 104 is provided between the n-type semiconductor layer 101 and the Schottky electrode 105a. The insulator layer can be formed by a known method such as a sputtering method, a vacuum deposition method, or a CVD method.

[0023] 3, a depletion layer (not shown) expands into the n-type semiconductor layer 101a, resulting in a high breakdown voltage SBD. Furthermore, when a forward bias is applied, electrons flow from the ohmic electrode 105b to the Schottky electrode 105a. Thus, an SBD using the semiconductor structure described above is excellent for high breakdown voltage and large current applications, has fast switching speed, excellent breakdown voltage and reliability, excellent insulation characteristics, and higher current controllability.

[0024] (JBS) Figure 4 shows a junction barrier Schottky diode (JBS) according to a preferred embodiment of the present invention. The semiconductor device of Figure 4 includes an n-type semiconductor layer 101, an n-type semiconductor layer 101a, an n+-type semiconductor layer 101b, a p-type semiconductor layer 102, a Schottky electrode 105a, an ohmic electrode 105b, and a guard ring 106. The semiconductor device includes an n-type semiconductor layer 101a, a Schottky electrode 105a provided on the n-type semiconductor layer 101a and capable of forming a Schottky barrier between itself and the n-type semiconductor layer 101a, and a p-type semiconductor layer 102 provided between the Schottky electrode 105a and the n-type semiconductor layer 101a and capable of forming a Schottky barrier between itself and the n-type semiconductor layer 101a with a barrier height greater than that of the Schottky barrier of the Schottky electrode 105a. The p-type semiconductor layer 102 is embedded in the n-type semiconductor layer 101a. In the present invention, it is preferable that the p-type semiconductor layers 102 are provided at regular intervals, and it is more preferable that the p-type semiconductor layers 102 are provided between both ends of the Schottky electrode 105a and the n-type semiconductor layer 101a. This preferable embodiment configures the JBS to have better thermal stability and adhesion, further reduce leakage current, and further excel in semiconductor properties such as breakdown voltage.

[0025] 5 shows an example of a metal semiconductor field effect transistor (MESFET) according to the present invention. The MESFET in FIG. 5 includes an n-type semiconductor layer 111a, an n+ type semiconductor layer 111b, a buffer layer 118, a crystal substrate 119, a semi-insulating layer 114, a gate electrode 115a, a source electrode 115b, and a drain electrode 115c.

[0026] The materials for the gate electrode, drain electrode, and source electrode may be known electrode materials, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof. The gate electrode, drain electrode, and source electrode can be formed by known means such as vacuum deposition or sputtering.

[0027] The semi-insulating layer 114 may be made of a semi-insulating material, and examples of the semi-insulating material include a material containing a semi-insulating dopant and a material that has not been doped.

[0028] In the MESFET shown in FIG. 5, a good depletion layer is formed under the gate electrode, so that the current flowing from the drain electrode to the source electrode can be efficiently controlled.

[0029] 6 shows an example of a high-energy electron mobility transistor (HEMT) according to the present invention. The HEMT in FIG. 6 includes an n-type semiconductor layer 121 a having a wide bandgap, an n-type semiconductor layer 121 b having a narrow bandgap, an n+ type semiconductor layer 121 c, an electron transit layer 123, a semi-insulating layer 124, a gate electrode 125 a, a source electrode 125 b, a drain electrode 125 c, a buffer layer 128, and a crystalline substrate 129.

[0030] The materials for the gate electrode, drain electrode, and source electrode may each be a known electrode material, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof. The gate electrode, drain electrode, and source electrode can be formed by known means such as vacuum deposition or sputtering.

[0031] The n-type semiconductor layer below the gate electrode is composed of at least a wide bandgap layer 121a and a narrow bandgap layer 121b, and the semi-insulating layer 124 may be composed of a semi-insulating material, such as a semi-insulating material containing a semi-insulating dopant or a semi-insulating material that has not been doped. For example, when GaN, a nitride semiconductor, is used as the semiconductor, the electron transit layer 123 formed on the semi-insulating layer 124 may be made of i (intentionally undoped)-GaN or the like.

[0032] In the HEMT shown in Figure 6, a good depletion layer is formed under the gate electrode, so the current flowing from the drain electrode to the source electrode can be efficiently controlled. Furthermore, in the present invention, a recess structure is further provided, thereby enabling normally-off operation.

[0033] (MOSFET) An example of a MOSFET as the semiconductor device of the present invention is shown in Figure 7. Figure 7 shows a suitable example of a metal oxide semiconductor field effect transistor (MOSFET) including an n- type semiconductor layer 131a, a first n+ type semiconductor layer 131b, a second n+ type semiconductor layer 131c, a p-type semiconductor layer 132, a p+ type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c. Note that the p+ type semiconductor layer 132a may be a p-type semiconductor layer or may be the same as the p-type semiconductor layer 132.

[0034] An n+ type semiconductor layer 131b having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 135c made of the conductive crystalline film, and an n- type semiconductor layer 131a having a thickness of, for example, 100 nm to 100 μm is formed on the n+ type semiconductor layer 131b.

[0035] Furthermore, a plurality of trenches each having a depth reaching partway through the n-type semiconductor layer 131a are formed in the n-type semiconductor layer 131a and the p-type semiconductor layer 132. A gate electrode 135a is embedded in the trenches via a gate insulating film 134 having a thickness of, for example, 10 nm to 1 μm.

[0036] 7, when a voltage is applied between the source electrode 135b and the drain electrode 135c and a positive voltage is applied to the gate electrode 135a with respect to the source electrode 135b, a channel layer is formed on the side surface of the n-type semiconductor layer 131a, electrons are injected into the n-type semiconductor layer, and the MOSFET is turned on. When the voltage of the gate electrode is set to 0V, no channel layer is formed, and the n-type semiconductor layer is filled with a depletion layer, resulting in the MOSFET being turned off.

[0037] 7, an etching mask is provided in predetermined regions of the n-type semiconductor layer 131a, the p-type semiconductor 132, and the n+ type semiconductor layer 131c, and anisotropic etching is performed using the etching mask by reactive ion etching or the like to form a trench groove with a depth that reaches from the surface of the n+ type semiconductor layer 131c to partway through the n- type semiconductor layer 131a. Next, a gate insulating film 134 with a thickness of, for example, 50 nm to 1 μm is formed on the side and bottom surfaces of the trench groove by known means such as thermal oxidation, vacuum deposition, sputtering, or CVD, and then a gate electrode material such as polysilicon is formed in the trench groove to a thickness equal to or less than the thickness of the n- type semiconductor layer by CVD, vacuum deposition, sputtering, or the like.

[0038] Then, a power MOSFET can be manufactured by forming a source electrode 135b on the n+ type semiconductor layer 131c using a known method such as vacuum deposition, sputtering, or CVD. The electrode material of the source electrode may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof, conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, and mixtures thereof.

[0039] The MOSFET obtained in this manner has a higher breakdown voltage than a conventional trench MOSFET. While Fig. 7 shows an example of a trench-type vertical MOSFET, the present invention is not limited to this and can be applied to various MOSFET configurations. For example, the depth of the trench groove in Fig. 7 may be deepened to a depth that reaches the bottom surface of the n-type semiconductor layer 131a, thereby reducing the series resistance.

[0040] 8 shows an example of the semiconductor device of the present invention being an SIT. The SIT in Fig. 8 includes an n-type semiconductor layer 141a, n+ type semiconductor layers 141b and 141c, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

[0041] An n+ type semiconductor layer 141b having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 145c made of a conductive crystalline film, and an n- type semiconductor layer 141a having a thickness of, for example, 100 nm to 100 μm is formed on the n+ type semiconductor layer 141b. Furthermore, an n+ type semiconductor layer 141c is formed on the n- type semiconductor layer 141a, and a source electrode 145b is formed on the n+ type semiconductor layer 141c.

[0042] Furthermore, a plurality of trenches are formed in the n-type semiconductor layer 141a, penetrating the n+ type semiconductor layer 141c and reaching partway through the n-type semiconductor layer 141a. A gate electrode 145a is formed on the n-type semiconductor layer in the trenches. In the on-state of the SIT shown in FIG. 8, when a voltage is applied between the source electrode 145b and the drain electrode 145c and a positive voltage is applied to the gate electrode 145a relative to the source electrode 145b, a channel layer is formed in the n-type semiconductor layer 141a, electrons are injected into the n-type semiconductor layer, and the device is turned on. In the off-state, when the voltage of the gate electrode is set to 0V, no channel layer is formed, and the n-type semiconductor layer is filled with a depletion layer, resulting in the device being turned off.

[0043] Known methods can be used to manufacture the SIT shown in FIG. 8 . For example, similar to the manufacturing process of the MOSFET described above, an etching mask is provided in predetermined regions of the n− type semiconductor layer 141a and the n+ type semiconductor layer 141c, and anisotropic etching is performed using the etching mask, for example, by reactive ion etching, to form a trench groove with a depth that reaches from the surface of the n+ type semiconductor layer 141c to partway through the n− type semiconductor layer. Next, a gate electrode material, such as polysilicon, is formed in the trench groove by a method such as CVD, vacuum deposition, or sputtering, to a thickness equal to or less than the thickness of the n− type semiconductor layer. Then, a source electrode 145b is formed on the n+ type semiconductor layer 141c, and a drain electrode 145c is formed on the n+ type semiconductor layer 141b, respectively, using known methods such as vacuum deposition, sputtering, or CVD, thereby manufacturing the SIT shown in FIG. 8 .

[0044] The electrode material of the source electrode may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof.

[0045] FIG. 9 shows a preferred example of a junction field effect transistor (JFET) including an n-type semiconductor layer 141a, a first n+ type semiconductor layer 141b, a second n+ type semiconductor layer 141c, a p-type semiconductor layer 142, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

[0046] FIG. 10 shows a preferred example of an insulated gate bipolar transistor (IGBT) including an n-type semiconductor layer 151, an n-type semiconductor layer 151a, an n+ type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155c.

[0047] (LED) An example of a case where the semiconductor device of the present invention is a light-emitting diode (LED) is shown in Figure 11. The semiconductor light-emitting device of Figure 11 has an n-type semiconductor layer 161 on a second electrode 165b, and a light-emitting layer 163 is stacked on the n-type semiconductor layer 161. A p-type semiconductor layer 162 is stacked on the light-emitting layer 163. A translucent electrode 167 that transmits light generated by the light-emitting layer 163 is provided on the p-type semiconductor layer 162, and a first electrode 165a is stacked on the translucent electrode 167. The semiconductor light-emitting device of Figure 11 may be covered with a protective layer except for the electrode portion.

[0048] Examples of materials for the translucent electrode include conductive oxide materials containing indium (In) or titanium (Ti). ２ O ３ , ZnO, SnO ２ , Ga ２ O３ , TiO ２ , CeO ２ Alternatively, a mixed crystal of two or more of these materials or a doped material thereof may be used. A translucent electrode can be formed by applying these materials by a known method such as sputtering. After the formation of the translucent electrode, thermal annealing may be performed to make the translucent electrode transparent.

[0049] In the semiconductor light-emitting element of FIG. 11, the first electrode 165a is a positive electrode and the second electrode 165b is a negative electrode, and current is passed through these electrodes to the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161, causing the light-emitting layer 163 to emit light.

[0050] Examples of materials for the first electrode 165a include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof. The method for forming the electrode is not particularly limited, and the electrode can be formed according to a method appropriately selected from wet methods such as printing, spraying, and coating; physical methods such as vacuum deposition, sputtering, and ion plating; and chemical methods such as CVD and plasma CVD, taking into consideration the suitability for the material.

[0051] In addition to the above features, the semiconductor device of the present invention can be suitably used as a semiconductor device such as a power module, inverter, or converter using known means, and further suitably used in semiconductor systems using a power supply device as a semiconductor device. The power supply device can be fabricated using known means, such as by connecting the semiconductor device to a wiring pattern. FIG. 12 shows an example of a power supply system. FIG. 12 shows a power supply system configured using multiple power supply devices and a control circuit. The power supply system can be combined with an electronic circuit, as shown in FIG. 13, to form a system device. FIG. 14 shows an example of a power supply circuit diagram for a power supply device. FIG. 14 shows the power supply circuit of a power supply device consisting of a power circuit and a control circuit. The inverter (comprising MOSFETs A to D) switches DC voltage at high frequency to convert it to AC, then insulates and transforms it with a transformer, rectifies it with rectifier MOSFETs (A to B'), and smooths it with DCLs (smoothing coils L1 and L2) and a capacitor to output a DC voltage. At this time, a voltage comparator compares the output voltage with a reference voltage, and a PWM control circuit controls the inverter and rectifier MOSFET to achieve the desired output voltage.

[0052] (Example 1) The crystal growth surface side of a Si substrate (100) was subjected to RIE treatment, and a single crystal of a crystalline nitride was formed on the Si substrate by a vapor deposition method using nitrogen gas. The conditions for the vapor deposition method during film formation were as follows: Vapor deposition source: Hf, Zr Voltage: 3.5 to 4.75 V Pressure: 3 x 10 －２ ~6 x 10 －２ Pa Substrate temperature: 350 to 700°C The obtained laminate structure was a laminate structure including a crystalline film having good adhesion and crystallinity, and the obtained crystalline film had a film thickness of 3 μm. When the electrical properties were examined by the four-terminal method, it was found to have good conductivity.

[0053] ScAlN was further laminated on the obtained laminated structure in accordance with the above-mentioned method to obtain a laminated structure as shown in FIG.

[0054] Example 2 A stacked structure was obtained in the same manner as in Example 1, except that a Si substrate was used instead of a (111) Si substrate. The crystalline film of the obtained stacked structure had good conductivity, similar to Example 1.

[0055] The evaporation film-forming apparatus used in Example 1 is shown in Figure 15. The film-forming apparatus in Figure 15 includes at least metal sources 1101a to 1101b in a crucible, earths 1102a to 1102h, ICP electrodes 1103a to 1103b, cut filters 1104a to 1104b, DC power supplies 1105a to 1105b, RF power supplies 1106a to 1106b, lamps 1107a to 1107b, an Ar source 1108, a reactive gas source 1109, a power supply 1110, a substrate holder 1111, a substrate 1112, a cut filter 1113, an ICP ring 1114, a vacuum chamber 1115, and a rotation shaft 1116. Note that the ICP electrodes 1103a to 1103b in Figure 15 have a substantially concave curved or parabolic shape curved toward the center of the substrate 1112.

[0056] As shown in FIG. 15 , a substrate 1112 is secured on a substrate holder 1111. Next, a power supply 1110 and a rotation mechanism (not shown) are used to rotate a rotation shaft 1116, thereby rotating the substrate 1112. The substrate 1112 is heated by lamps 1107a-1107b, and a vacuum chamber 1115 is evacuated to a vacuum or reduced pressure using a vacuum pump (not shown). Ar gas is then introduced into the vacuum chamber 1115 from an Ar source 1108, and argon plasma is formed on the substrate 1112 using DC power supplies 1105a-1105b, RF power supplies 1106a-1106b, ICP electrodes 1103a-1103b, cut filters 1104a-1104b, and earths 1102a-1102h, thereby cleaning the surface of the substrate 1112.

[0057] Ar gas is introduced into the vacuum chamber 1115, and reactive gas is introduced using a reactive gas source 1109. At this time, lamps 1107a to 1107b, which are lamp heaters, are turned on and off alternately, thereby enabling the formation of a crystal growth film of better quality.

[0058] The laminated structure of the present invention can be used in a wide range of fields, including semiconductors (for example, compound semiconductor electronic devices), electronic components, electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is preferably used in semiconductor devices.

[0059] 1 Epitaxial film (compound piezoelectric or compound semiconductor) 5 Nitride film 9 Crystal substrate 101 n-type semiconductor layer 101a n-type semiconductor layer 101b n+ type semiconductor layer 102 p-type semiconductor layer 104 Insulator layer 105a Schottky electrode 105b Ohmic electrode 106 Guard ring 111a n-type semiconductor layer 111b n+ type semiconductor layer 114 Semi-insulator layer 115a Gate electrode 115b Source electrode 115c Drain electrode 118 Buffer layer 119 Crystal substrate 121a Wide band gap n-type semiconductor layer 121b Narrow band gap n-type semiconductor layer 121c n+ type semiconductor layer 123 Electron transit layer 124 Semi-insulator layer 125a Gate electrode 125b Source electrode 125c Drain electrode 128 Buffer layer 129 Crystal substrate 131a n-type semiconductor layer 131b First n+ type semiconductor layer 131c Second n+ type semiconductor layer 132 P type semiconductor layer 134 Gate insulating film 135a Gate electrode 135b Source electrode 135c Drain electrode 141a n- type semiconductor layer 141b First n+ type semiconductor layer 141c Second n+ type semiconductor layer 142 P type semiconductor layer 145a Gate electrode 145b Source electrode 145c Drain electrode 151 N type semiconductor layer 151a n- type semiconductor layer 151b n+ type semiconductor layer 152 P type semiconductor layer 154 Gate insulating film 155a Gate electrode 155b Emitter electrode 155c Collector electrode 161 N type semiconductor layer 162 p-type semiconductor layer 163 light-emitting layer 165a first electrode 165b second electrode 167 light-transmitting electrode 1101a to 101b metal source 1102a to 102j earth 1103a to 103b ICP electrode 1104a to 104b cut filter 1105a to 105b DC power supply1106a to 106b RF power supplies 1107a to 107b Lamps 1108 Ar source 1109 Reactive gas source 1110 Power supply 1111 Substrate holder 1112 Substrate 1113 Cut filter 1114 ICP ring 1115 Vacuum chamber 1116 Rotation axis

Claims

1. A conductive crystal containing a crystalline nitride, wherein the crystalline nitride contains nitrides of Hf and Zr.

2. The crystal according to Claim 1, wherein the crystalline nitride has a cubic or hexagonal crystal structure.

3. The crystal according to Claim 2, wherein the crystalline nitride is oriented in (111), (100), (010), or (0001).

4. The crystal according to any one of Claims 1 to 3, wherein the crystalline nitride contains 30 atomic% or more of the nitride of Hf with respect to the crystalline nitride.

5. The crystal according to any one of Claims 1 to 3, wherein the crystalline nitride contains 50 atomic% or more of the nitride of Hf and the nitride of Zr with respect to the crystalline nitride.

6. The crystal according to any one of Claims 1 to 3, which is an electrode.

7. The crystal according to any one of Claims 1 to 3, which is in a film form.

8. The crystal according to Claim 7, having a film thickness of 1 μm or more.

9. A laminated structure in which a crystal film is laminated directly on a crystal substrate or via another layer, wherein the crystal film is composed of the crystal according to any one of Claims 1 to 3.

10. The laminated structure according to Claim 9, wherein the crystal film constitutes part or all of a buffer layer and is a substrate for crystal growth.

11. An element containing a crystal, wherein the crystal is the crystal according to any one of Claims 1 to 3.

12. The element according to Claim 11, which is a piezoelectric element or a semiconductor element.

13. An electronic device containing a crystal, wherein the crystal is the crystal according to any one of Claims 1 to 3.

14. The electronic device according to Claim 13, which is a piezoelectric device or a semiconductor device.

15. An electronic apparatus containing an electronic device, wherein the electronic device is the electronic device according to Claim 13.

16. A system containing an electronic apparatus, wherein the electronic apparatus is the electronic apparatus according to Claim 15.