Laminate structure, element, electronic device, electronic apparatus, and system

Abstract

[Problem] To provide a crystal having excellent crystallinity and a laminate structure, and an element, an electronic device, an electronic apparatus, and a system using same. [Solution] Provided is a laminate structure in which an epitaxial film, which is composed of a conductive metal oxide, is provided on a buffer layer directly or with another layer therebetween, wherein, by means of the laminate structure including a crystalline film containing an oxide of Hf and / or Zr, the buffer layer is used to manufacture a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal-semiconductor electric field effect transistor (MESFET), a high-electron-mobility transistor (HEMT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a static induction transistor (SIT), a junction electric field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), a light emitting diode (LED), or a semiconductor device composed of the combination of same, etc.

Description

Laminated structure, element, electronic device, electronic equipment and system

[0001] The present invention relates to a laminated structure, an element, an electronic device, an electronic apparatus, and a system.

[0002] Conventionally, in order to prevent malfunctions and breakdowns of ICs caused by parasitic elements in the horizontal and vertical directions that occur in PN isolation, isolation between each element has been performed using SiO ２ Silicon-on-insulator (SOI) technology using a film is known, and in recent years, methods for forming a plurality of semiconductor elements with different breakdown voltages on a single semiconductor substrate have also been considered, and in particular, application to wide bandgap semiconductors (e.g., SiC, GaN, etc.) has also been considered (Patent Document 1).

[0003] Also, attempts have been made to form devices on flexible substrates such as plastic using SOI technology. For example, as disclosed in Patent Document 2, there is a method in which a completed SOI substrate is used, windows are partially opened in the SOI layer to expose a BOX (buried oxide) layer, and then HF etching is performed so that the HF penetrates laterally to etch the BOX and form pillars. After pillar formation, there is also a method in which the SOI layer is attached to PET (polyethylene terephthalate) or the like, peeled from the substrate at the pillar portion, and the SOI layer is formed on PET or the like, thereby transferring the SOI layer on which the device is fabricated onto the flexible substrate.

[0004] However, none of the SOI technologies are yet satisfactory in terms of the crystallinity of the semiconductor film formed on the insulating film, the crystallinity of the insulating film, the insulating properties, etc., and further improvements in crystallinity and semiconductor properties have been desired. Also, there has been a demand for SOI technology that can bring about good crystallinity not only in semiconductors but also in piezoelectric materials and the like as buffer layers. Furthermore, when peeling and transferring an SOI layer, the process becomes complicated and peeling is difficult, so a new SOI technology that allows for easy peeling and transfer has also been desired.

[0005] JP 2021-5718 A JP 2014-179580 A

[0006] An object of the present invention is to provide a layered structure having excellent crystallinity, and an element, an electronic device, an electronic equipment and a system using the layered structure.

[0007] The present inventors have conducted extensive research to achieve the above-mentioned object, and have found that forming an oxide film on a crystal substrate and then laminating a crystal film containing a crystal made of a crystalline metal oxide, primarily containing oxides of Hf and Zr, by forming the crystal film using oxygen atoms in the oxide film, can easily produce crystals and laminated structures with excellent crystallinity, which is particularly useful for crystal growth for producing soft crystal films, and that forming a conductive film, semiconductor film, or piezoelectric film on the crystal results in excellent crystallinity and excellent electrode properties and various functional film properties, and that the crystals and laminated structures are particularly suitable as buffer layers for forming thin functional films with a thickness of less than 1 μm, and are also useful for peeling and transfer. Furthermore, after obtaining the above-mentioned findings, the present inventors have conducted further research and have completed the present invention.

[0008] That is, the present invention relates to the following inventions. [1] A stacked structure in which an epitaxial film made of a conductive metal oxide is formed on a buffer layer directly or via another layer, the buffer layer including a crystalline film containing an oxide of Hf and / or Zr. [2] The stacked structure according to [1] above, in which the crystalline film contains an oxide of Hf. [3] The stacked structure according to [1] or [2] above, in which the crystalline film has a cubic or hexagonal crystal structure. [4] The stacked structure according to any of [1] to [3] above, in which the crystalline film has a (111), (100), (010), or (0001) orientation. [5] The stacked structure according to any of [1] to [4] above, in which the conductive metal oxide is an oxide containing In and / or Sn. [6] The stacked structure according to any of [1] to [5] above, in which the buffer layer is formed on a single crystal substrate having a cubic or hexagonal crystal structure directly or via another layer. [7] The laminated structure according to [6], wherein the buffer layer is deposited on the single crystal substrate by crystal growth. [8] The laminated structure according to [6] or [7], wherein the single crystal substrate is a Si substrate. [9] The laminated structure according to any one of [1] to [8], further comprising a layer made of a piezoelectric or semiconductor deposited on the epitaxial film.

[10] An element including a laminated structure, wherein the laminated structure is the laminated structure according to any one of [1] to [9].

[11] The element according to

[10] , which is a piezoelectric element or a semiconductor element.

[12] An electronic device including a laminated structure, wherein the laminated structure is the laminated structure according to any one of [1] to [9].

[13] The electronic device according to

[12] , which is a piezoelectric device or a semiconductor device.

[14] An electronic device including an electronic device, wherein the electronic device is the electronic device according to

[12] or

[13] .

[15] A system including an electronic device, wherein the electronic device is the electronic device described in

[14] above.

[0009] The laminated structure of the present invention has excellent crystallinity, and an element, an electronic device, an electronic equipment, and a system using the laminated structure exhibit the effect of improving the properties of the respective functional films.

[0010] FIG. 1 is a diagram schematically illustrating an example of a preferred embodiment of the laminated structure of the present invention. FIG. 1 is a diagram schematically illustrating an SOI island formation step in peel-and-transfer, which is an example of a preferred application of the laminated structure of the present invention. FIG. 2 is a diagram schematically illustrating an HF etching step in peel-and-transfer, which is an example of a preferred application of the laminated structure of the present invention. FIG. 3 is a diagram schematically illustrating an attachment step to a flexible substrate in peel-and-transfer, which is an example of a preferred application of the laminated structure of the present invention. FIG. 4 is a diagram schematically illustrating a peel-and-transfer step in peel-and-transfer, which is an example of a preferred application of the laminated structure of the present invention. FIG. 5 is a diagram schematically illustrating an example of a compound film formation step in a preferred manufacturing method of the laminated structure of the present invention. FIG. 6 is a diagram schematically illustrating an example of an insulating film formation step in a preferred manufacturing method of the laminated structure of the present invention. FIG. 7 is a diagram showing cross-sectional STEM images observed in Examples. FIG. 8 is a diagram showing XPS analysis results in Examples. FIG. 9 is a diagram schematically illustrating a preferred example of an insulated gate bipolar transistor (IGBT) obtained in the present invention. FIG. 10 is a diagram schematically illustrating an example of a preferred manufacturing process for the insulated gate bipolar transistor (IGBT) of FIG. 10. FIG. 11 is a diagram schematically illustrating a preferred example of a power supply system. It is a diagram showing a preferred example of a system device. It is a diagram showing a preferred example of a power supply circuit diagram of a power supply device. It is a diagram showing a preferred example of a film forming apparatus used in the examples.

[0011] The laminated structure of the present invention is a laminated structure in which an epitaxial film made of a conductive metal oxide is formed on a buffer layer directly or via another layer, and the buffer layer includes a crystalline film containing an oxide of Hf and / or Zr. The crystal of the crystalline film may be single crystal or polycrystalline.

[0012] The conductive metal oxide is usually a conductive crystalline metal oxide, but the crystalline metal oxide is not particularly limited as long as it contains a metal oxide as a main component. The oxide is also not particularly limited as long as it contains oxides of Hf and Zr, but preferably contains oxides of Hf and Zr as a main component. The "main component" may refer to, for example, oxides of Hf and Zr in an atomic ratio of 0.5 or more in the crystal. In the present invention, the atomic ratio of Hf and Zr to all metal elements in the oxide is preferably 0.7 or more, and more preferably 0.8 or more.

[0013] In the present invention, the oxide or the crystalline metal oxide preferably has a cubic or hexagonal crystal structure, and more preferably has a (111), (100), (010), or (0001) orientation. Furthermore, in the present invention, it is also preferable that the oxide contains 50 atomic % or more of Hf oxide and Zr oxide relative to the crystalline metal oxide. This preferred range is preferable because it can be used as an excellent buffer layer, can exhibit good properties as a ferroelectric, and can further improve electrical properties (particularly the interface between the conductive layer and the insulating layer).

[0014] In the present invention, the crystal is preferably in the form of a film (hereinafter also referred to as "crystal film"). If it is in the form of a film, it is preferable that the film thickness is 1 μm or more from the viewpoint of pressure resistance, etc. Such preferred crystals can be easily obtained by forming at least an oxide film on a crystal substrate, and then laminating a crystal film containing crystals made of a crystalline metal oxide containing a metal oxide as a main component, by forming the crystal film using oxygen atoms in the oxide film. The means for forming the crystal film is not particularly limited and may be a known means (e.g., MBE method, ion plating method, etc.), and the crystal growth conditions, etc. can also be set appropriately. The laminate structure obtained by the above method and the method for producing the same are also encompassed by the present invention.

[0015] 1 shows a preferred example of the laminated structure, in which an oxide film 5 is laminated as a first epitaxial layer on a crystal substrate 9 using an oxide film, and a conductive film, semiconductor film, or piezoelectric film 4 is further laminated as a second epitaxial layer on the first epitaxial layer. Furthermore, an epitaxial film 1 made of a compound piezoelectric or compound semiconductor is laminated on the conductive film 4. In this specification, the terms "film" and "layer" may be interchangeable depending on the case or situation.

[0016] 2, the laminated structure can be easily manufactured by forming an oxide film 5 of the crystal substrate 9 on the crystal substrate 9, and then using oxygen in the oxide film 5 to form a crystal film (first epitaxial layer) made of the crystalline metal oxide on the crystal substrate 9. In the present invention, the laminated structure may have the oxide film 5 on the crystal substrate 9, or the oxide film 5 may disappear when all of the oxygen in the oxide film 5 is taken in during the formation of the crystal film. Preferred embodiments of the present invention will be described in more detail below, but the present invention is not limited to these specific examples.

[0017] The crystal substrate (hereinafter simply referred to as "substrate") is not particularly limited as long as the objectives of the present invention are not impaired, and may be a known crystal substrate. It may be an organic compound or an inorganic compound. In the present invention, it is preferable that the crystal substrate contains an inorganic compound. In the present invention, the substrate preferably has crystals on a portion or all of its surface, more preferably a crystal substrate having crystals on all or a portion of its main surface on the crystal growth side, and most preferably a crystal substrate having crystals on the entire main surface on the crystal growth side. The crystal is not particularly limited as long as the objectives of the present invention are not impaired, and the crystal structure is also not particularly limited. However, it is preferably a cubic, tetragonal, trigonal, hexagonal, orthorhombic, or monoclinic crystal, more preferably a cubic or hexagonal crystal, and most preferably a (111), (100), or (0001) orientation. The crystal substrate may also have an off-angle, and examples of the off-angle include an off-angle of 0.2° to 12.0°. Here, the "off-angle" refers to the angle between the substrate surface and the crystal growth plane. The substrate shape is not particularly limited as long as it is plate-like and serves as a support for the insulating film. It may be an insulating substrate or a semiconductor substrate, but in the present invention, the substrate is preferably a Si substrate, more preferably a crystalline Si substrate, and most preferably a crystalline Si substrate with a (111), (100), or (0001) orientation. Examples of the substrate material include Si substrates and one or more metals belonging to Groups 3 to 15 of the periodic table, or oxides of these metals. The shape of the substrate is not particularly limited and may be approximately circular (e.g., circular, elliptical, etc.) or polygonal (e.g., triangular, square, rectangular, pentagonal, hexagonal, heptagonal, octagonal, 9-agonal, etc.), and various shapes can be suitably used.

[0018] In the present invention, the crystal substrate preferably has a flat surface. However, it is also preferable for the crystal substrate to have an uneven surface on part or all of its surface, as this can improve the quality of crystal growth of the crystal film. The crystal substrate having an uneven surface may have an uneven surface consisting of concave or convex portions formed on part or all of its surface. The uneven surface is not particularly limited as long as it consists of convex or concave portions. It may be an uneven surface consisting of convex portions, an uneven surface consisting of concave portions, or an uneven surface consisting of convex and concave portions. The uneven surface may also be formed of regular convex or concave portions, or irregular convex or concave portions. In the present invention, the uneven surface is preferably formed periodically, and more preferably in a periodic and regularly patterned form. The shape of the uneven surface is not particularly limited, and examples include stripes, dots, meshes, and random patterns. In the present invention, a dot or stripe pattern is preferred, and a dot pattern is more preferred. Furthermore, when the concave-convex portions are patterned periodically and regularly, the pattern shape of the concave-convex portions is preferably a polygonal shape such as a triangle, a quadrangle (e.g., a square, a rectangle, or a trapezoid), a pentagon, or a hexagon, or a circle, an ellipse, or the like. When the concave-convex portions are formed in a dotted pattern, the lattice shape of the dots is preferably a lattice shape such as a square lattice, an oblique lattice, a triangular lattice, or a hexagonal lattice, and a triangular lattice shape is more preferable. The cross-sectional shape of the concave or convex portions of the concave-convex portions is not particularly limited, but examples thereof include a U-shape, an inverted U-shape, a wave shape, or a polygonal shape such as a triangle, a quadrangle (e.g., a square, a rectangle, or a trapezoid), a pentagon, or a hexagon. The thickness of the crystal substrate is not particularly limited, but is preferably 50 to 2000 μm, and more preferably 100 to 1000 μm.

[0019] The oxide film is not particularly limited as long as it is an oxide film capable of incorporating oxygen atoms into the crystal film, and typically contains an oxide material. The oxide material is not particularly limited as long as it does not impede the objectives of the present invention, and may be a known oxide material. Examples of the oxide material include metal or semimetal oxides. In the present invention, the oxide film preferably contains the oxide material of the crystal substrate. Examples of such oxide films include a thermally oxidized film or a natural oxide film of the crystal substrate. In addition, in the present invention, the oxide film may be a sacrificial layer that is partially or completely lost or destroyed when oxygen atoms are absorbed. In the present invention, the oxide film is preferably an oxygen supply sacrificial layer that absorbs oxygen atoms and loses the oxide film itself during the crystal growth of the epitaxial layer. In addition, the oxide film may be patterned, for example, in a striped, dotted, mesh, or random pattern. The thickness of the oxide film is not particularly limited, but is preferably greater than 1 nm and less than 100 nm.

[0020] The crystalline film (first epitaxial layer) preferably includes an epitaxial film incorporating oxygen atoms from the oxide film. Note that "an epitaxial film incorporating oxygen atoms from the oxide film" means that oxygen atoms from the oxide film are taken by the epitaxial film during the crystal growth of the epitaxial film. In addition, in the present invention, it is preferable that the crystalline film includes a neutron absorbing material. The neutron absorbing material may be a known neutron absorbing material. In the present invention, by using such a neutron absorbing material to absorb oxygen from the oxide film, it is possible to improve adhesion, crystallinity, and other functional film properties. Note that hafnium (Hf) is a suitable example of the neutron absorbing material.

[0021] In the present invention, it is preferable that a second epitaxial layer made of a conductive film, a semiconductor film, or a piezoelectric film is stacked on the crystal film, either directly or via another layer. By stacking in this manner, the first epitaxial layer can be regularly transformed at the interface between the first epitaxial layer and the second epitaxial layer so that the lattice constant becomes substantially the same as that of the second epitaxial layer. A preferred example of the regular transformation is a transformation in which the shape is transformed into a peak-valley structure. In the present invention, it is preferable that the angles formed by adjacent peaks and valleys of the peak-valley structure are different from each other, and more preferably, each of the angles is within a range of 30° to 45°. Here, the first epitaxial layer usually has a first crystal plane and a second crystal plane, but since the transformation can cause a difference in lattice constant between the first crystal plane and the second crystal plane, it is preferable that the difference in lattice constant between the first crystal plane and the second crystal plane be within a range of 0.1% to 20%. In the present invention, since the first crystal plane can be made substantially the same as the lattice constant of the second epitaxial layer, it is easy to achieve a difference in lattice constant between the first epitaxial layer and the second epitaxial layer within a range of 0.1% to 20%.

[0022] In the present invention, when a conductive film is laminated on the crystalline film, and the conductive film is made of a single crystal film of a conductive metal, a large-area defect-free film can be easily obtained, and not only the function as an electrode but also the characteristics of the element can be improved. The conductive metal is not particularly limited as long as it does not impede the object of the present invention, and examples thereof include gold, silver, platinum, palladium, silver-palladium, copper, nickel, or alloys thereof, but in the present invention, it is preferable to include platinum. Note that in the present invention, according to the above-mentioned manufacturing method, it is preferable to obtain a film having a thickness of 100 nm. ２ A defect-free single crystal film can be obtained as an electrode with an area of ​​1000 nm or more. ２A defect-free single crystal film can be easily obtained with an area of ​​100 nm or more. Furthermore, a single crystal film having a thickness of 100 nm or more can be easily obtained as an electrode. When a conductive film made of a single crystal film of a conductive metal is laminated on the crystalline film, the laminated structure can be suitably used as an electrode substrate in which a crystalline conductive film is laminated on the insulating film.

[0023] The semiconductor film is not particularly limited as long as it contains a semiconductor, and may be a known semiconductor film, but in the present invention, it preferably contains a cubic semiconductor, such as c-BN, c-AlN, c-GaN, c-InN, c-SiC, GaAs, AlAs, InAs, GaP, AlP, InP, or a mixed crystal semiconductor thereof.

[0024] The piezoelectric film is not particularly limited as long as it is made of a piezoelectric material, and may be a film made of a known piezoelectric material, but in the present invention, it is preferable that the piezoelectric film is a piezoelectric material having a trigonal or hexagonal crystal structure. Examples of the piezoelectric material include lead zirconate titanate (PZT), ABO ３ Other types of ceramic materials having a so-called perovskite structure represented by the formula include barium titanate, lead titanate, potassium niobate, lithium niobate, lithium tantalate, sodium tungstate, zinc oxide, barium strontium titanate (BST), strontium bismuth tantalate (SBT), lead metaniobate, lead zinc niobate, lead scandium niobate, etc., as well as polyvinylidene fluoride, quartz, etc.

[0025] The thickness of each of the conductive film, the semiconductor film, and the piezoelectric film is not particularly limited, but is preferably 10 nm to 1000 μm, and more preferably 10 nm to 100 μm.

[0026] The laminated structure can be easily obtained by a method for manufacturing a laminated structure in which an insulating film is laminated on a crystal substrate via at least an oxide film, by forming a crystal film using oxygen atoms in the oxide film at 350° C. to 700° C. When the temperature is in the range of 350° C. to 700° C., oxygen atoms in the oxide film can be easily incorporated into the crystal film to cause crystal growth.

[0027] In the present invention, it is preferable that the above-mentioned lamination is performed by using oxygen atoms in the oxide film, and then the crystal film is formed by using oxygen gas.

[0028] The lamination means used in the lamination is usually a means for depositing the insulating film, and the film deposition means may be a known film deposition means. In the present invention, the film deposition means is preferably vapor deposition or sputtering.

[0029] The laminated structure obtained as described above can be used in a device as is or after further processing, etc., according to a conventional method. When the laminated structure is used in a device, it may be used as is, or it may be used after forming other layers (e.g., an insulating layer, a semi-insulating layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers). In the present invention, the laminated structure is preferably used as an SOI substrate in which a functional film (e.g., a semiconductor film, a piezoelectric film, etc.) is laminated on the crystalline film.

[0030] The element is used in a conventional manner, for example, in an electronic device (preferably a piezoelectric device). More specifically, for example, the element can be connected as a piezoelectric element to a power source or an electric / electronic circuit, and mounted on a circuit board or packaged to form various electronic devices. In the present invention, the electronic device is preferably a piezoelectric device, and more preferably a piezoelectric device in an electronic device such as a gyroscope or a motion sensor. Furthermore, for example, if an amplifier and a rectifier circuit are connected and packaged, the electronic device can be used in various sensors such as a magnetic sensor.

[0031] The electronic device is suitably used in electronic devices in the usual manner, and can be applied to various electronic devices in addition to the above-mentioned electronic devices, and more specific examples of suitable electronic devices include liquid ejection heads, liquid ejection apparatuses, vibration wave motors, optical devices, vibration devices, imaging devices, piezoelectric acoustic components, and audio playback devices, audio recording devices, mobile phones, and various information terminals that have such piezoelectric acoustic components.

[0032] In the present invention, the element is preferably a semiconductor element, and the electronic device is preferably a semiconductor device. The semiconductor element or semiconductor device (hereinafter collectively referred to as "semiconductor device") is not particularly limited as long as it does not impede the object of the present invention, and may be a known semiconductor element or semiconductor device.

[0033] The semiconductor device is not particularly limited as long as it does not impede the object of the present invention, and may be a known semiconductor device. It may be a vertical device or a horizontal device, but in the present invention, the semiconductor device is preferably a vertical device. Examples of the semiconductor device include diodes and transistors. More specifically, preferred examples include Schottky barrier diodes (SBDs), junction barrier Schottky diodes (JBSs), high electron mobility transistors (HEMTs), metal semiconductor field effect transistors (MESFETs), metal oxide semiconductor field effect transistors (MOSFETs), static induction transistors (SITs), junction field effect transistors (JFETs), insulated gate bipolar transistors (IGBTs), light-emitting diodes (LEDs), and combinations thereof.

[0034] Hereinafter, preferred examples of applying the stacked structure to a semiconductor device, more specifically, applying the buffer layer in the stacked structure to an electrode or buffer layer for ohmic contact or electron emission in the semiconductor device, and applying the epitaxial film in the stacked structure to a semiconductor layer in the semiconductor device will be described with reference to the drawings, but the present invention is not limited to these examples. Note that the semiconductor devices exemplified below may further include other layers (e.g., an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers) as long as the object of the present invention is not impaired, and the crystal substrate, buffer layer, etc. may also be omitted as appropriate.

[0035] 3 shows an example of a Schottky barrier diode (SBD) according to the present invention. The SBD in Fig. 3 includes an n-type semiconductor layer 101, an n-type semiconductor layer 101a, an n+ type semiconductor layer 101b, an insulator layer 104, a Schottky electrode 105a, and an ohmic electrode 105b.

[0036] The material of the electrodes such as the Schottky electrode may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof.

[0037] The electrode can be formed by a known method such as vacuum deposition or sputtering. More specifically, for example, when a Schottky electrode is formed, a layer made of Mo and a layer made of Al are stacked, and the layer made of Mo and the layer made of Al are patterned using a photolithography technique.

[0038] Examples of the material for the insulator layer 104 include GaO, AlGaO, InAlGaO, and AlInZnGaO. ４ , AlN, Hf２ O ３ , SiN, SiON, Al ２ O ３ , MgO, GdO, SiO ２ or Si ３ N ４ The insulator layer 104 is provided between the n-type semiconductor layer 101 and the Schottky electrode 105a. The insulator layer can be formed by a known method such as a sputtering method, a vacuum deposition method, or a CVD method.

[0039] 3, a depletion layer (not shown) expands into the n-type semiconductor layer 101a, resulting in a high breakdown voltage SBD. Furthermore, when a forward bias is applied, electrons flow from the ohmic electrode 105b to the Schottky electrode 105a. Thus, an SBD using the semiconductor structure described above is excellent for high breakdown voltage and large current applications, has fast switching speed, excellent breakdown voltage and reliability, excellent insulation characteristics, and higher current controllability.

[0040] (JBS) Figure 4 shows a junction barrier Schottky diode (JBS) according to a preferred embodiment of the present invention. The semiconductor device of Figure 4 includes an n-type semiconductor layer 101, an n-type semiconductor layer 101a, an n+-type semiconductor layer 101b, a p-type semiconductor layer 102, a Schottky electrode 105a, an ohmic electrode 105b, and a guard ring 106. The semiconductor device includes an n-type semiconductor layer 101a, a Schottky electrode 105a provided on the n-type semiconductor layer 101a and capable of forming a Schottky barrier between itself and the n-type semiconductor layer 101a, and a p-type semiconductor layer 102 provided between the Schottky electrode 105a and the n-type semiconductor layer 101a and capable of forming a Schottky barrier between itself and the n-type semiconductor layer 101a with a barrier height greater than that of the Schottky barrier of the Schottky electrode 105a. The p-type semiconductor layer 102 is embedded in the n-type semiconductor layer 101a. In the present invention, it is preferable that the p-type semiconductor layers 102 are provided at regular intervals, and it is more preferable that the p-type semiconductor layers 102 are provided between both ends of the Schottky electrode 105a and the n-type semiconductor layer 101a. This preferable embodiment configures the JBS to have better thermal stability and adhesion, further reduce leakage current, and further excel in semiconductor properties such as breakdown voltage.

[0041] 5 shows an example of a metal semiconductor field effect transistor (MESFET) according to the present invention. The MESFET in FIG. 5 includes an n-type semiconductor layer 111a, an n+ type semiconductor layer 111b, a buffer layer 118, a crystal substrate 119, a semi-insulating layer 114, a gate electrode 115a, a source electrode 115b, and a drain electrode 115c.

[0042] The materials for the gate electrode, drain electrode, and source electrode may be known electrode materials, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof. The gate electrode, drain electrode, and source electrode can be formed by known means such as vacuum deposition or sputtering.

[0043] The semi-insulating layer 114 may be made of a semi-insulating material, and examples of the semi-insulating material include a material containing a semi-insulating dopant and a material that has not been doped.

[0044] In the MESFET shown in FIG. 5, a good depletion layer is formed under the gate electrode, so that the current flowing from the drain electrode to the source electrode can be efficiently controlled.

[0045] 6 shows an example of a high-energy electron mobility transistor (HEMT) according to the present invention. The HEMT in FIG. 6 includes an n-type semiconductor layer 121 a having a wide bandgap, an n-type semiconductor layer 121 b having a narrow bandgap, an n+ type semiconductor layer 121 c, an electron transit layer 123, a semi-insulating layer 124, a gate electrode 125 a, a source electrode 125 b, a drain electrode 125 c, a buffer layer 128, and a crystalline substrate 129.

[0046] The materials for the gate electrode, drain electrode, and source electrode may each be a known electrode material, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof. The gate electrode, drain electrode, and source electrode can be formed by known means such as vacuum deposition or sputtering.

[0047] The n-type semiconductor layer below the gate electrode is composed of at least a wide bandgap layer 121a and a narrow bandgap layer 121b, and the semi-insulating layer 124 may be composed of a semi-insulating material, such as a semi-insulating material containing a semi-insulating dopant or a semi-insulating material that has not been doped. For example, when GaN, a nitride semiconductor, is used as the semiconductor, the electron transit layer 123 formed on the semi-insulating layer 124 may be made of i (intentionally undoped)-GaN or the like.

[0048] In the HEMT shown in Figure 6, a good depletion layer is formed under the gate electrode, so the current flowing from the drain electrode to the source electrode can be efficiently controlled. Furthermore, in the present invention, a recess structure is further provided, thereby enabling normally-off operation.

[0049] (MOSFET) An example of a MOSFET as the semiconductor device of the present invention is shown in Figure 7. Figure 7 shows a suitable example of a metal oxide semiconductor field effect transistor (MOSFET) including an n- type semiconductor layer 131a, a first n+ type semiconductor layer 131b, a second n+ type semiconductor layer 131c, a p-type semiconductor layer 132, a p+ type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c. Note that the p+ type semiconductor layer 132a may be a p-type semiconductor layer or may be the same as the p-type semiconductor layer 132.

[0050] An n+ type semiconductor layer 131b having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 135c made of the conductive crystalline film, and an n- type semiconductor layer 131a having a thickness of, for example, 100 nm to 100 μm is formed on the n+ type semiconductor layer 131b.

[0051] Furthermore, a plurality of trenches each having a depth reaching partway through the n-type semiconductor layer 131a are formed in the n-type semiconductor layer 131a and the p-type semiconductor layer 132. A gate electrode 135a is embedded in the trenches via a gate insulating film 134 having a thickness of, for example, 10 nm to 1 μm.

[0052] 7, when a voltage is applied between the source electrode 135b and the drain electrode 135c and a positive voltage is applied to the gate electrode 135a with respect to the source electrode 135b, a channel layer is formed on the side surface of the n-type semiconductor layer 131a, electrons are injected into the n-type semiconductor layer, and the MOSFET is turned on. When the voltage of the gate electrode is set to 0V, no channel layer is formed, and the n-type semiconductor layer is filled with a depletion layer, resulting in the MOSFET being turned off.

[0053] 7, an etching mask is provided in predetermined regions of the n-type semiconductor layer 131a, the p-type semiconductor 132, and the n+ type semiconductor layer 131c, and anisotropic etching is performed using the etching mask by reactive ion etching or the like to form a trench groove with a depth that reaches from the surface of the n+ type semiconductor layer 131c to partway through the n- type semiconductor layer 131a. Next, a gate insulating film 134 with a thickness of, for example, 50 nm to 1 μm is formed on the side and bottom surfaces of the trench groove by known means such as thermal oxidation, vacuum deposition, sputtering, or CVD, and then a gate electrode material such as polysilicon is formed in the trench groove to a thickness equal to or less than the thickness of the n- type semiconductor layer by CVD, vacuum deposition, sputtering, or the like.

[0054] Then, a power MOSFET can be manufactured by forming a source electrode 135b on the n+ type semiconductor layer 131c using a known method such as vacuum deposition, sputtering, or CVD. The electrode material of the source electrode may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof, conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, and mixtures thereof.

[0055] The MOSFET obtained in this manner has a higher breakdown voltage than a conventional trench MOSFET. While Fig. 7 shows an example of a trench-type vertical MOSFET, the present invention is not limited to this and can be applied to various MOSFET configurations. For example, the depth of the trench groove in Fig. 7 may be deepened to a depth that reaches the bottom surface of the n-type semiconductor layer 131a, thereby reducing the series resistance.

[0056] 8 shows an example of the semiconductor device of the present invention being an SIT. The SIT in Fig. 8 includes an n-type semiconductor layer 141a, n+ type semiconductor layers 141b and 141c, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

[0057] An n+ type semiconductor layer 141b having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 145c made of a conductive crystalline film, and an n- type semiconductor layer 141a having a thickness of, for example, 100 nm to 100 μm is formed on the n+ type semiconductor layer 141b. Furthermore, an n+ type semiconductor layer 141c is formed on the n- type semiconductor layer 141a, and a source electrode 145b is formed on the n+ type semiconductor layer 141c.

[0058] Furthermore, a plurality of trenches are formed in the n-type semiconductor layer 141a, penetrating the n+ type semiconductor layer 141c and reaching partway through the n-type semiconductor layer 141a. A gate electrode 145a is formed on the n-type semiconductor layer in the trenches. In the on-state of the SIT shown in FIG. 8, when a voltage is applied between the source electrode 145b and the drain electrode 145c and a positive voltage is applied to the gate electrode 145a relative to the source electrode 145b, a channel layer is formed in the n-type semiconductor layer 141a, electrons are injected into the n-type semiconductor layer, and the device is turned on. In the off-state, when the voltage of the gate electrode is set to 0V, no channel layer is formed, and the n-type semiconductor layer is filled with a depletion layer, resulting in the device being turned off.

[0059] Known methods can be used to manufacture the SIT shown in FIG. 8 . For example, similar to the manufacturing process of the MOSFET described above, an etching mask is provided in predetermined regions of the n− type semiconductor layer 141a and the n+ type semiconductor layer 141c, and anisotropic etching is performed using the etching mask, for example, by reactive ion etching, to form a trench groove with a depth that reaches from the surface of the n+ type semiconductor layer 141c to partway through the n− type semiconductor layer. Next, a gate electrode material, such as polysilicon, is formed in the trench groove by a method such as CVD, vacuum deposition, or sputtering, to a thickness equal to or less than the thickness of the n− type semiconductor layer. Then, a source electrode 145b is formed on the n+ type semiconductor layer 141c, and a drain electrode 145c is formed on the n+ type semiconductor layer 141b, respectively, using known methods such as vacuum deposition, sputtering, or CVD, thereby manufacturing the SIT shown in FIG. 8 .

[0060] The electrode material of the source electrode may be a known electrode material, and examples of the electrode material include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof.

[0061] FIG. 9 shows a preferred example of a junction field effect transistor (JFET) including an n-type semiconductor layer 141a, a first n+ type semiconductor layer 141b, a second n+ type semiconductor layer 141c, a p-type semiconductor layer 142, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

[0062] FIG. 10 shows a preferred example of an insulated gate bipolar transistor (IGBT) including an n-type semiconductor layer 151, an n-type semiconductor layer 151a, an n+ type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155c.

[0063] (LED) An example of a case where the semiconductor device of the present invention is a light-emitting diode (LED) is shown in Figure 11. The semiconductor light-emitting device of Figure 11 has an n-type semiconductor layer 161 on a second electrode 165b, and a light-emitting layer 163 is stacked on the n-type semiconductor layer 161. A p-type semiconductor layer 162 is stacked on the light-emitting layer 163. A translucent electrode 167 that transmits light generated by the light-emitting layer 163 is provided on the p-type semiconductor layer 162, and a first electrode 165a is stacked on the translucent electrode 167. The semiconductor light-emitting device of Figure 11 may be covered with a protective layer except for the electrode portion.

[0064] Examples of materials for the translucent electrode include conductive oxide materials containing indium (In) or titanium (Ti). ２ O ３ , ZnO, SnO ２ , Ga ２ O３ , TiO ２ , CeO ２ Alternatively, a mixed crystal of two or more of these materials or a doped material thereof may be used. A translucent electrode can be formed by applying these materials by a known method such as sputtering. After the formation of the translucent electrode, thermal annealing may be performed to make the translucent electrode transparent.

[0065] In the semiconductor light-emitting element of FIG. 11, the first electrode 165a is a positive electrode and the second electrode 165b is a negative electrode, and current is passed through these electrodes to the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161, causing the light-emitting layer 163 to emit light.

[0066] Examples of materials for the first electrode 165a include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof. The method for forming the electrode is not particularly limited, and the electrode can be formed according to a method appropriately selected from wet methods such as printing, spraying, and coating; physical methods such as vacuum deposition, sputtering, and ion plating; and chemical methods such as CVD and plasma CVD, taking into consideration the suitability for the material.

[0067] In addition to the above features, the semiconductor device of the present invention can be suitably used as a semiconductor device such as a power module, inverter, or converter using known means, and further suitably used in semiconductor systems using a power supply device as a semiconductor device. The power supply device can be fabricated using known means, such as by connecting the semiconductor device to a wiring pattern. FIG. 12 shows an example of a power supply system. FIG. 12 shows a power supply system configured using multiple power supply devices and a control circuit. The power supply system can be combined with an electronic circuit, as shown in FIG. 13, to form a system device. FIG. 14 shows an example of a power supply circuit diagram for a power supply device. FIG. 14 shows the power supply circuit of a power supply device consisting of a power circuit and a control circuit. The inverter (comprising MOSFETs A to D) switches DC voltage at high frequency to convert it to AC, then insulates and transforms it with a transformer, rectifies it with rectifier MOSFETs (A to B'), and smooths it with DCLs (smoothing coils L1 and L2) and a capacitor to output a DC voltage. At this time, a voltage comparator compares the output voltage with a reference voltage, and a PWM control circuit controls the inverter and rectifier MOSFET to achieve the desired output voltage.

[0068] (Example 1) The crystal growth surface side of a Si substrate (100) was treated by RIE, and then heated in the presence of oxygen to form a thermal oxide film. After that, a metal from the evaporation source was thermally reacted with oxygen in the oxide film on the Si substrate by evaporation without using oxygen, to form an insulating film made of a crystalline oxide on the Si substrate. Next, oxygen was introduced, the temperature was lowered, and the pressure was increased, and an insulating film was further formed by evaporation. The evaporation conditions for this film formation were as follows: Evaporation source: Hf, Zr Voltage: 3.5 to 4.75 V Pressure: 3 x 10 －２ ~6 x 10 －２ Pa Substrate temperature: 500 to 650°C An ITO film was further laminated on the insulating film of the obtained laminated structure in accordance with the method described above, and a PZT film was laminated on the ITO film to obtain a laminated structure as shown in Figure 1.

[0069] Example 2 A stacked structure was obtained in the same manner as in Example 1, except that a Si substrate was used instead of a (111) Si substrate.

[0070] The evaporation film-forming apparatus used in Example 1 is shown in Figure 15. The film-forming apparatus in Figure 15 includes at least metal sources 1101a to 1101b in a crucible, earths 1102a to 1102h, ICP electrodes 1103a to 1103b, cut filters 1104a to 1104b, DC power supplies 1105a to 1105b, RF power supplies 1106a to 1106b, lamps 1107a to 1107b, an Ar source 1108, a reactive gas source 1109, a power supply 1110, a substrate holder 1111, a substrate 1112, a cut filter 1113, an ICP ring 1114, a vacuum chamber 1115, and a rotation shaft 1116. Note that the ICP electrodes 1103a to 1103b in Figure 15 have a substantially concave curved or parabolic shape curved toward the center of the substrate 1112.

[0071] As shown in FIG. 15 , a substrate 1112 is secured on a substrate holder 1111. Next, a power supply 1110 and a rotation mechanism (not shown) are used to rotate a rotation shaft 1116, thereby rotating the substrate 1112. The substrate 1112 is heated by lamps 1107a-1107b, and a vacuum chamber 1115 is evacuated to a vacuum or reduced pressure using a vacuum pump (not shown). Ar gas is then introduced into the vacuum chamber 1115 from an Ar source 1108, and argon plasma is formed on the substrate 1112 using DC power supplies 1105a-1105b, RF power supplies 1106a-1106b, ICP electrodes 1103a-1103b, cut filters 1104a-1104b, and earths 1102a-1102h, thereby cleaning the surface of the substrate 1112.

[0072] Ar gas is introduced into the vacuum chamber 1115, and reactive gas is introduced using a reactive gas source 1109. At this time, lamps 1107a to 1107b, which are lamp heaters, are turned on and off alternately, thereby enabling the formation of a crystal growth film of better quality.

[0073] The laminated structure of the present invention can be used in a wide range of fields, including semiconductors (for example, compound semiconductor electronic devices), electronic components, electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is preferably used in semiconductor devices.

[0074] 1 Epitaxial film (compound piezoelectric or compound semiconductor) 4 In2O3 film or ITO film 5 Oxide film 9 Crystal substrate 101 n-type semiconductor layer 101a n-type semiconductor layer 101b n+ type semiconductor layer 102 p-type semiconductor layer 104 Insulator layer 105a Schottky electrode 105b Ohmic electrode 106 Guard ring 111a n-type semiconductor layer 111b n+ type semiconductor layer 114 Semi-insulator layer 115a Gate electrode 115b Source electrode 115c Drain electrode 118 Buffer layer 119 Crystal substrate 121a Wide band gap n-type semiconductor layer 121b Narrow band gap n-type semiconductor layer 121c n+ type semiconductor layer 123 Electron transit layer 124 Semi-insulator layer 125a Gate electrode 125b Source electrode 125c Drain electrode 128 Buffer layer 129 Crystal substrate 131a n-type semiconductor layer 131b First n+ type semiconductor layer 131c Second n+ type semiconductor layer 132 P type semiconductor layer 134 Gate insulating film 135a Gate electrode 135b Source electrode 135c Drain electrode 141a n- type semiconductor layer 141b First n+ type semiconductor layer 141c Second n+ type semiconductor layer 142 P type semiconductor layer 145a Gate electrode 145b Source electrode 145c Drain electrode 151 N type semiconductor layer 151a n- type semiconductor layer 151b n+ type semiconductor layer 152 P type semiconductor layer 154 Gate insulating film 155a Gate electrode 155b Emitter electrode 155c Collector electrode 161 n-type semiconductor layer 162 p-type semiconductor layer 163 light-emitting layer 165a first electrode 165b second electrode 167 light-transmitting electrode 1101a to 101b metal source 1102a to 102j earth 1103a to 103b ICP electrodes 1104a to 104b cut filter1105a to 105b DC power supplies 1106a to 106b RF power supplies 1107a to 107b Lamps 1108 Ar source 1109 Reactive gas source 1110 Power supply 1111 Substrate holder 1112 Substrate 1113 Cut filter 1114 ICP ring 1115 Vacuum chamber 1116 Rotation axis

Claims

1. A laminate structure in which an epitaxial film made of a conductive metal oxide is formed directly on a buffer layer or via another layer, wherein the buffer layer includes a crystalline film containing an oxide of Hf and / or Zr. The laminate structure is characterized by this.

2. The laminate structure according to Claim 1, wherein the crystalline film contains an oxide of Hf.

3. The laminate structure according to Claim 1, wherein the crystalline film has a cubic or hexagonal crystal structure.

4. The laminate structure according to any one of Claims 1 to 3, wherein the crystalline film is oriented in (111), (100), (010), or (0001).

5. The laminate structure according to any one of Claims 1 to 3, wherein the conductive metal oxide is an oxide containing In and / or Sn.

6. The laminate structure according to any one of Claims 1 to 3, wherein the buffer layer is laminated directly or via another layer on a single crystal substrate having a cubic or hexagonal crystal structure.

7. The laminate structure according to Claim 6, wherein the buffer layer is laminated on the single crystal substrate by crystal growth.

8. The laminate structure according to Claim 6, wherein the single crystal substrate is a Si substrate.

9. Furthermore, a layer made of a piezoelectric body or a semiconductor is laminated on the epitaxial film. The laminate structure according to any one of Claims 1 to 3.

10. An element including a laminate structure, wherein the laminate structure is the laminate structure according to any one of Claims 1 to 3. The element is characterized by this.

11. The element according to Claim 10, which is a piezoelectric element or a semiconductor element.

12. An electronic device including a laminate structure, wherein the laminate structure is the laminate structure according to any one of Claims 1 to 3. The electronic device is characterized by this.

13. The electronic device according to Claim 12, which is a piezoelectric device or a semiconductor device.

14. An electronic apparatus including an electronic device, wherein the electronic device is the electronic device according to Claim 12. The electronic apparatus is characterized by this.

15. A system including an electronic apparatus, wherein the electronic apparatus is the electronic apparatus according to Claim 14. The system is characterized by this.